diff --git a/.circleci/config.yml b/.circleci/config.yml
new file mode 100644
index 000000000..fd5631e2e
--- /dev/null
+++ b/.circleci/config.yml
@@ -0,0 +1,92 @@
+version: 2.1
+
+setup: true
+orbs:
+  continuation: circleci/continuation@1
+
+jobs:
+  set-matrix:
+    executor: continuation/default
+    docker:
+      - image: cimg/base:current
+    resource_class: small
+    steps:
+      - checkout
+      - run:
+          name: Set matrix
+          command: |
+            MATRIX_JSON=$(python .github/workflows/ci_set_matrix.py)
+            echo "MATRIX_JSON=$MATRIX_JSON"
+
+            BUILDSYSTEM_TOOLCHAIN=(
+              "cmake arm-clang"
+              "make aarch64-gcc"
+              "make arm-gcc"
+              "make msp430-gcc"
+              "make riscv-gcc"
+              "make rx-gcc"
+              "cmake esp-idf"
+            )
+
+            # only build IAR if not forked PR, since IAR token is not shared
+            if [ -z $CIRCLE_PR_USERNAME ]; then
+              BUILDSYSTEM_TOOLCHAIN+=("cmake arm-iar")
+            fi
+
+            RESOURCE_LARGE='["nrf", "imxrt", "stm32f4", "stm32h7"]'
+
+            gen_build_entry() {
+              local build_system="$1"
+              local toolchain="$2"
+              local family="$3"
+              local resource_class="$4"
+
+              if [[ "$toolchain" == "esp-idf" ]]; then
+                echo "      - build-vm:" >> .circleci/config2.yml
+              else
+                echo "      - build:" >> .circleci/config2.yml
+              fi
+
+              echo "          matrix:" >> .circleci/config2.yml
+              echo "            parameters:" >> .circleci/config2.yml
+              echo "              build-system: ['$build_system']" >> .circleci/config2.yml
+              echo "              toolchain: ['$toolchain']" >> .circleci/config2.yml
+              echo "              family: $family" >> .circleci/config2.yml
+              echo "              resource_class: ['$resource_class']" >> .circleci/config2.yml
+            }
+
+            for e in "${BUILDSYSTEM_TOOLCHAIN[@]}"; do
+              e_arr=($e)
+              build_system="${e_arr[0]}"
+              toolchain="${e_arr[1]}"
+              FAMILY=$(echo $MATRIX_JSON | jq -r ".\"$toolchain\"")
+              echo "FAMILY_${toolchain}=$FAMILY"
+
+              # FAMILY_LARGE = FAMILY - RESOURCE_LARGE
+              # Separate large from medium+ resources
+              FAMILY_LARGE=$(jq -n --argjson family "$FAMILY" --argjson resource "$RESOURCE_LARGE" '$family | map(select(IN($resource[])))')
+              FAMILY=$(jq -n --argjson family "$FAMILY" --argjson resource "$RESOURCE_LARGE" '$family | map(select(IN($resource[]) | not))')
+
+              if [[ $toolchain == esp-idf ]]; then
+                gen_build_entry "$build_system" "$toolchain" "$FAMILY" "large"
+              else
+                gen_build_entry "$build_system" "$toolchain" "$FAMILY" "medium+"
+
+                # add large resources if available
+                if [ "$(echo $FAMILY_LARGE | jq 'length')" -gt 0 ]; then
+                    gen_build_entry "$build_system" "$toolchain" "$FAMILY_LARGE" "large"
+                fi
+              fi
+            done
+
+      - continuation/continue:
+          configuration_path: .circleci/config2.yml
+
+workflows:
+  set-matrix:
+    # Only build PR here, Push will be built by github action.
+    when:
+      and:
+        - not: << pipeline.git.branch.is_default >>
+    jobs:
+      - set-matrix
diff --git a/.circleci/config2.yml b/.circleci/config2.yml
new file mode 100644
index 000000000..3b0294168
--- /dev/null
+++ b/.circleci/config2.yml
@@ -0,0 +1,196 @@
+version: 2.1
+
+commands:
+  setup-toolchain:
+    parameters:
+        toolchain:
+            type: string
+
+    steps:
+      - run:
+          name: Set toolchain url and key
+          command: |
+            TOOLCHAIN_JSON='{
+              "aarch64-gcc": "https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz",
+              "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-19.1.1/LLVM-ET-Arm-19.1.1-Linux-x86_64.tar.xz",
+              "arm-gcc": "https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v13.2.1-1.1/xpack-arm-none-eabi-gcc-13.2.1-1.1-linux-x64.tar.gz",
+              "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2",
+              "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz",
+              "rx-gcc": "https://github.com/hathach/rx_device/releases/download/0.0.1/gcc-8.3.0.202411-GNURX-ELF.run",
+              "arm-iar": "https://updates.iar.com/FileStore/STANDARD/001/003/322/cxarm-9.60.3.deb"
+            }'
+            toolchain_url=$(echo $TOOLCHAIN_JSON | jq -r '.["<< parameters.toolchain >>"]')
+
+            # only cache if not a github link
+            if [[ $toolchain_url != "https://github.com"* ]]; then
+              echo "<< parameters.toolchain >>-$toolchain_url" > toolchain_key
+            fi
+            echo "export toolchain_url=$toolchain_url" >> $BASH_ENV
+
+      - restore_cache:
+          name: Restore Toolchain Cache
+          key: deps-{{ checksum "toolchain_key" }}
+          paths:
+            - ~/cache/<< parameters.toolchain >>
+
+      - run:
+          name: Install Toolchain
+          command: |
+            # download if folder does not exist (not cached)
+            if [ ! -d ~/cache/<< parameters.toolchain >> ]; then
+              mkdir -p ~/cache/<< parameters.toolchain >>
+              if [[ << parameters.toolchain >> == rx-gcc ]]; then
+                wget --progress=dot:giga $toolchain_url -O toolchain.run
+                chmod +x toolchain.run
+                ./toolchain.run -p ~/cache/<< parameters.toolchain >>/gnurx -y
+              elif [[ << parameters.toolchain >> == arm-iar ]]; then
+                wget --progress=dot:giga $toolchain_url -O ~/cache/<< parameters.toolchain >>/toolchain.deb
+              else
+                wget --progress=dot:giga $toolchain_url -O toolchain.tar.gz
+                tar -C ~/cache/<< parameters.toolchain >> -xaf toolchain.tar.gz
+              fi
+            fi
+
+            # Add toolchain to PATH
+            if [[ << parameters.toolchain >> == arm-iar ]]; then
+              # Install IAR since we only cache deb file
+              sudo dpkg --ignore-depends=libusb-1.0-0 -i ~/cache/<< parameters.toolchain >>/toolchain.deb
+              echo "export PATH=$PATH:/opt/iar/cxarm/arm/bin" >> $BASH_ENV
+            else
+              echo "export PATH=$PATH:`echo ~/cache/<< parameters.toolchain >>/*/bin`" >> $BASH_ENV
+            fi
+
+      - save_cache:
+          name: Save Toolchain Cache
+          key: deps-{{ checksum "toolchain_key" }}
+          paths:
+            - ~/cache/<< parameters.toolchain >>
+
+  build:
+    parameters:
+      build-system:
+        type: string
+      toolchain:
+        type: string
+      family:
+        type: string
+
+    steps:
+      - checkout
+      - run:
+          name: Get Dependencies
+          command: |
+            python tools/get_deps.py << parameters.family >>
+
+            # Install ninja  if cmake build system
+            if [ << parameters.build-system >> == "cmake" ]; then
+              NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.12.1/ninja-linux.zip
+              wget $NINJA_URL -O ninja-linux.zip
+              unzip ninja-linux.zip -d ~/bin
+            fi
+
+            # rx-gcc is 32-bit binary
+            if [[ << parameters.toolchain >> == rx-gcc ]]; then
+              sudo dpkg --add-architecture i386
+              sudo apt update
+              sudo apt install libc6:i386 libstdc++6:i386 zlib1g:i386
+            fi
+
+            # Install Pico SDK
+            if [ << parameters.family >> == "rp2040" ]; then
+              git clone --depth 1 https://github.com/raspberrypi/pico-sdk.git ~/pico-sdk
+              echo "export PICO_SDK_PATH=~/pico-sdk" >> $BASH_ENV
+            fi
+
+      - when:
+          condition:
+            not:
+              equal: [esp-idf, << parameters.toolchain >>]
+          steps:
+            - setup-toolchain:
+                toolchain: << parameters.toolchain >>
+
+      - run:
+          name: Build
+          command: |
+            if [ << parameters.toolchain >> == esp-idf ]; then
+              docker run --rm -v $PWD:/project -w /project espressif/idf:v5.3.2 python tools/build.py << parameters.family >>
+            else
+              # Toolchain option default is gcc
+              if [ << parameters.toolchain >> == arm-clang ]; then
+                TOOLCHAIN_OPTION="--toolchain clang"
+              elif [ << parameters.toolchain >> == arm-iar ]; then
+                TOOLCHAIN_OPTION="--toolchain iar"
+                echo IAR_LMS_CLOUD_URL=$IAR_LMS_CLOUD_URL
+                iccarm --version
+              elif [ << parameters.toolchain >> == arm-gcc ]; then
+                TOOLCHAIN_OPTION="--toolchain gcc"
+              fi
+
+              python tools/build.py -s << parameters.build-system >> $TOOLCHAIN_OPTION << parameters.family >>
+            fi
+
+jobs:
+  # Build using docker
+  build:
+    parameters:
+      resource_class:
+        type: string
+        default: medium+
+      build-system:
+        type: string
+      toolchain:
+        type: string
+      family:
+        type: string
+
+    docker:
+      - image: cimg/base:current
+    resource_class: << parameters.resource_class >>
+
+    steps:
+      - build:
+          build-system: << parameters.build-system >>
+          toolchain: << parameters.toolchain >>
+          family: << parameters.family >>
+
+  # Build using VM
+  build-vm:
+    parameters:
+      resource_class:
+        type: string
+        default: large
+      build-system:
+        type: string
+      toolchain:
+        type: string
+      family:
+        type: string
+
+    machine:
+      image: ubuntu-2404:current
+    resource_class: << parameters.resource_class >>
+
+    steps:
+      - build:
+          build-system: << parameters.build-system >>
+          toolchain: << parameters.toolchain >>
+          family: << parameters.family >>
+
+workflows:
+  build:
+    jobs:
+#      - build:
+#          matrix:
+#            parameters:
+#              toolchain: [ 'arm-gcc' ]
+#              build-system: [ 'cmake' ]
+#              family: [ 'nrf' ]
+#              resource_class: ['large']
+#      - build-vm:
+#          matrix:
+#            parameters:
+#              toolchain: ['esp-idf']
+#              build-system: ['cmake']
+#              family: ['-bespressif_kaluga_1']
+#              resource_class: ['large']
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 000000000..0fd168e5a
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,66 @@
+# Generated from CLion C/C++ Code Style settings
+BasedOnStyle: LLVM
+AccessModifierOffset: -2
+AlignAfterOpenBracket: Align
+AlignConsecutiveAssignments: None
+AlignOperands: Align
+AllowAllArgumentsOnNextLine: false
+AllowAllConstructorInitializersOnNextLine: false
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortBlocksOnASingleLine: Always
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: All
+AllowShortIfStatementsOnASingleLine: Always
+AllowShortLambdasOnASingleLine: All
+AllowShortLoopsOnASingleLine: true
+AlwaysBreakAfterReturnType: None
+AlwaysBreakTemplateDeclarations: Yes
+BreakBeforeBraces: Custom
+BraceWrapping:
+  AfterCaseLabel: false
+  AfterClass: false
+  AfterControlStatement: Never
+  AfterEnum: false
+  AfterFunction: false
+  AfterNamespace: false
+  AfterUnion: false
+  BeforeCatch: false
+  BeforeElse: false
+  IndentBraces: false
+  SplitEmptyFunction: false
+  SplitEmptyRecord: true
+BreakBeforeBinaryOperators: None
+BreakBeforeTernaryOperators: true
+BreakConstructorInitializers: BeforeColon
+BreakInheritanceList: BeforeColon
+ColumnLimit: 0
+CompactNamespaces: false
+ContinuationIndentWidth: 4
+IndentCaseLabels: true
+IndentPPDirectives: BeforeHash
+IndentWidth: 2
+KeepEmptyLinesAtTheStartOfBlocks: true
+MaxEmptyLinesToKeep: 2
+NamespaceIndentation: All
+ObjCSpaceAfterProperty: false
+ObjCSpaceBeforeProtocolList: true
+PointerAlignment: Right
+ReflowComments: false
+SpaceAfterCStyleCast: true
+SpaceAfterLogicalNot: false
+SpaceAfterTemplateKeyword: false
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCpp11BracedList: false
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeParens: ControlStatements
+SpaceBeforeRangeBasedForLoopColon: false
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 0
+SpacesInAngles: false
+SpacesInCStyleCastParentheses: false
+SpacesInContainerLiterals: true
+SpacesInParentheses: false
+SpacesInSquareBrackets: false
+TabWidth: 2
+UseTab: Never
diff --git a/.codespellrc b/.codespellrc
new file mode 100644
index 000000000..1f06e0c5c
--- /dev/null
+++ b/.codespellrc
@@ -0,0 +1,10 @@
+# See: https://github.com/codespell-project/codespell#using-a-config-file
+[codespell]
+# In the event of a false positive, add the problematic word, in all lowercase, to 'ignore-words.txt' (one word per line).
+# Or copy & paste the whole problematic line to 'exclude-file.txt'
+ignore-words = tools/codespell/ignore-words.txt
+exclude-file = tools/codespell/exclude-file.txt
+check-filenames =
+check-hidden =
+count =
+skip = *.rb,.cproject,.git,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./tests_obsolete
diff --git a/.gitattributes b/.gitattributes
index 2342decc3..140ae8929 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -1,10 +1,10 @@
 # Set the default behavior, in case people don't have core.autocrlf set.
 * text=auto
 
-*.c text 
-*.cpp text 
+*.c text
+*.cpp text
 *.h text
-*.icf text 
+*.icf text
 *.js text
 *.json text
 *.ld text
diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 2958d3b12..d00ee78bd 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -54,21 +54,21 @@ body:
         Exact steps in chronological order, details should be specific e.g if you use a command/script to test with, please post it as well.
         1. Go to '...'
         2. Click on '....'
-        3. See error      
+        3. See error
     validations:
       required: true
 
   - type: textarea
     attributes:
-      label: Debug Log as txt file
+      label: Debug Log as txt file (LOG/CFG_TUSB_DEBUG=2)
       placeholder: |
         Attach your debug log txt file here, where the issue occurred, best with comments to explain the actual events.
-        
-        Note1: Please DO NOT paste your lengthy log contents here since it hurts the readibility.
-        Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. 
+
+        Note1: Please DO NOT paste your lengthy log contents here since it hurts the readability.
+        Note2: To enable logging, add `LOG=2` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h.
         More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md)
     validations:
-      required: false
+      required: true
 
   - type: textarea
     attributes:
diff --git a/.github/actions/get_deps/action.yml b/.github/actions/get_deps/action.yml
new file mode 100644
index 000000000..ae9e7bbef
--- /dev/null
+++ b/.github/actions/get_deps/action.yml
@@ -0,0 +1,29 @@
+name: Get dependencies
+
+inputs:
+  arg:
+    description: 'Arguments to get_deps.py'
+    required: true
+
+runs:
+  using: "composite"
+  steps:
+    - name: Checkout pico-sdk for rp2040
+      if: contains(inputs.arg, 'rp2040') || contains(inputs.arg, 'raspberry_pi_pico')
+      uses: actions/checkout@v4
+      with:
+        repository: raspberrypi/pico-sdk
+        ref: master
+        path: pico-sdk
+
+    - name: Linux dependencies
+      if: runner.os == 'Linux'
+      run: |
+        sudo apt install -y ninja-build
+      shell: bash
+
+    - name: Get Dependencies
+      run: |
+        python3 tools/get_deps.py ${{ inputs.arg }}
+        echo "PICO_SDK_PATH=${{ github.workspace }}/pico-sdk" >> $GITHUB_ENV
+      shell: bash
diff --git a/.github/actions/setup_toolchain/action.yml b/.github/actions/setup_toolchain/action.yml
new file mode 100644
index 000000000..8305daa24
--- /dev/null
+++ b/.github/actions/setup_toolchain/action.yml
@@ -0,0 +1,68 @@
+name: Setup Toolchain
+
+inputs:
+  toolchain:
+    description: 'Toolchain name'
+    required: true
+
+outputs:
+  build_option:
+    description: 'Build option for the toolchain e.g --toolchain clang'
+    value: ${{ steps.set-toolchain-option.outputs.build_option }}
+
+runs:
+  using: "composite"
+  steps:
+    - name: Install ARM GCC
+      if: inputs.toolchain == 'arm-gcc'
+      uses: carlosperate/arm-none-eabi-gcc-action@v1
+      with:
+        release: '13.2.Rel1'
+
+    - name: Pull ESP-IDF docker
+      if: inputs.toolchain == 'esp-idf'
+      uses: ./.github/actions/setup_toolchain/espressif
+      with:
+        toolchain: ${{ inputs.toolchain }}
+
+    - name: Get Toolchain URL
+      if: >-
+        inputs.toolchain != 'arm-gcc' &&
+        inputs.toolchain != 'arm-iar' &&
+        inputs.toolchain != 'esp-idf'
+      id: set-toolchain-url
+      run: |
+        TOOLCHAIN_JSON='{
+          "aarch64-gcc": "https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz",
+          "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-19.1.1/LLVM-ET-Arm-19.1.1-Linux-x86_64.tar.xz",
+          "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2",
+          "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz",
+          "rx-gcc": "https://github.com/hathach/rx_device/releases/download/0.0.1/gcc-8.3.0.202411-GNURX-ELF.run"
+        }'
+        TOOLCHAIN_URL=$(echo $TOOLCHAIN_JSON | jq -r '.["${{ inputs.toolchain }}"]')
+        echo "toolchain_url=$TOOLCHAIN_URL"
+        echo "toolchain_url=$TOOLCHAIN_URL" >> $GITHUB_OUTPUT
+      shell: bash
+
+    - name: Download Toolchain
+      if: >-
+        inputs.toolchain != 'arm-gcc' &&
+        inputs.toolchain != 'arm-iar' &&
+        inputs.toolchain != 'esp-idf'
+      uses: ./.github/actions/setup_toolchain/download
+      with:
+        toolchain: ${{ inputs.toolchain }}
+        toolchain_url: ${{ steps.set-toolchain-url.outputs.toolchain_url }}
+
+    - name: Set toolchain option
+      id: set-toolchain-option
+      run: |
+          BUILD_OPTION=""
+          if [[ "${{ inputs.toolchain }}" == *"clang"* ]]; then
+            BUILD_OPTION="--toolchain clang"
+          elif [[ "${{ inputs.toolchain }}" == "arm-iar" ]]; then
+            BUILD_OPTION="--toolchain iar"
+          fi
+          echo "build_option=$BUILD_OPTION"
+          echo "build_option=$BUILD_OPTION" >> $GITHUB_OUTPUT
+      shell: bash
diff --git a/.github/actions/setup_toolchain/download/action.yml b/.github/actions/setup_toolchain/download/action.yml
new file mode 100644
index 000000000..813197208
--- /dev/null
+++ b/.github/actions/setup_toolchain/download/action.yml
@@ -0,0 +1,39 @@
+name: Download Toolchain
+
+inputs:
+  toolchain:
+    description: 'Toolchain name'
+    required: true
+  toolchain_url:
+    description: 'Toolchain URL'
+    required: true
+
+runs:
+  using: "composite"
+  steps:
+    - name: Cache Toolchain
+      if: ${{ !startsWith(inputs.toolchain_url, 'https://github.com') }}
+      uses: actions/cache@v4
+      id: cache-toolchain-download
+      with:
+        path: ~/cache/${{ inputs.toolchain }}
+        key: ${{ runner.os }}-${{ inputs.toolchain }}-${{ inputs.toolchain_url }}
+
+    - name: Install Toolchain
+      if: steps.cache-toolchain-download.outputs.cache-hit != 'true'
+      run: |
+        mkdir -p ~/cache/${{ inputs.toolchain }}
+        wget --progress=dot:giga ${{ inputs.toolchain_url }} -O toolchain.tar.gz
+        if [[ ${{ inputs.toolchain }} == rx-gcc ]]; then
+          mv toolchain.tar.gz toolchain.run
+          chmod +x toolchain.run
+          ./toolchain.run -p ~/cache/${{ inputs.toolchain }}/gnurx -y
+        else
+          tar -C ~/cache/${{ inputs.toolchain }} -xaf toolchain.tar.gz
+        fi
+      shell: bash
+
+    - name: Set Toolchain Path
+      run: |
+        echo >> $GITHUB_PATH `echo ~/cache/${{ inputs.toolchain }}/*/bin`
+      shell: bash
diff --git a/.github/actions/setup_toolchain/espressif/action.yml b/.github/actions/setup_toolchain/espressif/action.yml
new file mode 100644
index 000000000..b50ffd41d
--- /dev/null
+++ b/.github/actions/setup_toolchain/espressif/action.yml
@@ -0,0 +1,48 @@
+name: Setup ESP-IDF Toolchain
+
+inputs:
+  toolchain:
+    description: 'Toolchain name'
+    required: true
+  toolchain_version:
+    description: 'Toolchain version'
+    required: false
+    default: 'v5.3.2'
+
+runs:
+  using: "composite"
+  steps:
+    - name: Set DOCKER_ESP_IDF
+      run: |
+        DOCKER_ESP_IDF=$HOME/cache/${{ inputs.toolchain }}/docker_image.tar
+        echo "DOCKER_ESP_IDF=$DOCKER_ESP_IDF" >> $GITHUB_ENV
+      shell: bash
+
+    - name: Cache Docker Image
+      uses: actions/cache@v4
+      id: cache-toolchain-espressif
+      with:
+        path: ${{ env.DOCKER_ESP_IDF }}
+        key: ${{ inputs.toolchain }}-${{ inputs.toolchain_version }}
+
+    - name: Pull and Save Docker Image
+      if: steps.cache-toolchain-espressif.outputs.cache-hit != 'true'
+      run: |
+        docker pull espressif/idf:${{ inputs.toolchain_version }}
+        mkdir -p $(dirname $DOCKER_ESP_IDF)
+        docker save -o $DOCKER_ESP_IDF espressif/idf:${{ inputs.toolchain_version }}
+        du -sh $DOCKER_ESP_IDF
+      shell: bash
+
+    - name: Load Docker Image
+      if: steps.cache-toolchain-espressif.outputs.cache-hit == 'true'
+      run: |
+        du -sh $DOCKER_ESP_IDF
+        docker load --input $DOCKER_ESP_IDF
+      shell: bash
+
+    - name: Tag Local Image
+      run: |
+        docker tag espressif/idf:${{ inputs.toolchain_version }} espressif/idf:tinyusb
+        docker images
+      shell: bash
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 000000000..547763bd8
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,164 @@
+name: Build
+
+on:
+  workflow_dispatch:
+  push:
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+      - 'tools/get_deps.py'
+      - 'tools/build.py'
+      - '.github/actions/**'
+      - '.github/workflows/build.yml'
+      - '.github/workflows/build_util.yml'
+      - '.github/workflows/ci_set_matrix.py'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+      - 'tools/get_deps.py'
+      - 'tools/build.py'
+      - '.github/actions/**'
+      - '.github/workflows/build.yml'
+      - '.github/workflows/build_util.yml'
+      - '.github/workflows/ci_set_matrix.py'
+concurrency:
+  group: ${{ github.workflow }}-${{ github.ref }}
+  cancel-in-progress: true
+
+jobs:
+  set-matrix:
+    runs-on: ubuntu-latest
+    outputs:
+      json: ${{ steps.set-matrix-json.outputs.matrix }}
+    steps:
+      - name: Checkout TinyUSB
+        uses: actions/checkout@v4
+
+      - name: Generate matrix json
+        id: set-matrix-json
+        run: |
+          MATRIX_JSON=$(python .github/workflows/ci_set_matrix.py)
+          echo "matrix=$MATRIX_JSON"
+          echo "matrix=$MATRIX_JSON" >> $GITHUB_OUTPUT
+
+  # ---------------------------------------
+  # Build CMake
+  # ---------------------------------------
+  cmake:
+    needs: set-matrix
+    uses: ./.github/workflows/build_util.yml
+    strategy:
+      fail-fast: false
+      matrix:
+        toolchain:
+          # - 'arm-clang' is built by circle-ci in PR
+          - 'aarch64-gcc'
+          - 'arm-gcc'
+          - 'msp430-gcc'
+          - 'riscv-gcc'
+    with:
+      build-system: 'cmake'
+      toolchain: ${{ matrix.toolchain }}
+      build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)[matrix.toolchain]) }}
+      one-per-family: ${{ github.event_name == 'push' }}
+
+  # ---------------------------------------
+  # Build Make (built by circle-ci in PR, only build on push here)
+  # ---------------------------------------
+  make:
+    if: github.event_name == 'push'
+    needs: set-matrix
+    uses: ./.github/workflows/build_util.yml
+    strategy:
+      fail-fast: false
+      matrix:
+        toolchain:
+          # 'arm-clang'
+          - 'arm-gcc'
+          - 'aarch64-gcc'
+          - 'msp430-gcc'
+          - 'riscv-gcc'
+          - 'rx-gcc'
+          - 'esp-idf' # build-system is ignored
+    with:
+      build-system: 'make'
+      toolchain: ${{ matrix.toolchain }}
+      build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)[matrix.toolchain]) }}
+      one-per-family: true
+
+  # ---------------------------------------
+  # Build Make on Windows/MacOS
+  # ---------------------------------------
+  make-os:
+    if: github.event_name == 'pull_request'
+    uses: ./.github/workflows/build_util.yml
+    strategy:
+      fail-fast: false
+      matrix:
+        os: [windows-latest, macos-latest]
+    with:
+      os: ${{ matrix.os }}
+      build-system: 'make'
+      toolchain: 'arm-gcc'
+      build-args: '["stm32h7"]'
+      one-per-family: true
+
+  # ---------------------------------------
+  # Build IAR on HFP self-hosted
+  # Since IAR Token secret is not passed to forked PR, only build on PR from the same repo
+  # ---------------------------------------
+  arm-iar:
+    if: github.repository_owner == 'hathach' && github.event_name == 'push'
+    needs: set-matrix
+    runs-on: [self-hosted, Linux, X64, hifiphile]
+    env:
+      BUILD_ARGS: ${{ join(fromJSON(needs.set-matrix.outputs.json)['arm-iar'], ' ') }}
+      IAR_LMS_CLOUD_URL: ${{ vars.IAR_LMS_CLOUD_URL }}
+      IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }}
+    steps:
+      - name: Clean workspace
+        run: |
+          echo "Cleaning up previous run"
+          rm -rf "${{ github.workspace }}"
+          mkdir -p "${{ github.workspace }}"
+
+      - name: Toolchain version
+        run: |
+          echo IAR_LMS_CLOUD_URL=$IAR_LMS_CLOUD_URL
+          iccarm --version
+
+      - name: Checkout TinyUSB
+        uses: actions/checkout@v4
+
+      - name: Get Dependencies
+        run: python3 tools/get_deps.py $BUILD_ARGS
+
+      - name: Build
+        run: python3 tools/build.py --one-per-family --toolchain iar $BUILD_ARGS
+
+  # ---------------------------------------
+  # Zephyr
+  # ---------------------------------------
+  zephyr:
+    if: github.event_name == 'push'
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout TinyUSB
+        uses: actions/checkout@v4
+
+      - name: Setup Zephyr project
+        uses: zephyrproject-rtos/action-zephyr-setup@v1
+        with:
+          app-path: examples
+          toolchains: arm-zephyr-eabi
+
+      - name: Build
+        run: |
+          west build -b pca10056 -d examples/device/cdc_msc/build examples/device/cdc_msc -- -DRTOS=zephyr
+          west build -b pca10056 -d examples/device/msc_dual_lun/build examples/device/msc_dual_lun -- -DRTOS=zephyr
diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
deleted file mode 100644
index af26f33f2..000000000
--- a/.github/workflows/build_aarch64.yml
+++ /dev/null
@@ -1,72 +0,0 @@
-name: Build AArch64
-
-on:
-  pull_request:
-  push:
-  release:
-    types:
-      - created
-
-jobs:
-  # ---------------------------------------
-  # Build AARCH64 family
-  # ---------------------------------------
-  build-arm:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        family:
-        # Alphabetical order
-        - 'broadcom_64bit'
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v4
-      with:
-        python-version: '3.x'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
-
-    - name: Checkout hathach/linkermap
-      uses: actions/checkout@v3
-      with:
-         repository: hathach/linkermap
-         path: linkermap
-
-    - name: Set Toolchain URL
-      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
-
-    - name: Cache Toolchain
-      uses: actions/cache@v3
-      id: cache-toolchain
-      with:
-        path: ~/cache/
-        key: ${{ runner.os }}-21-11-02-${{ env.TOOLCHAIN_URL }}
-
-    - name: Install Toolchain
-      if: steps.cache-toolchain.outputs.cache-hit != 'true'
-      run: |
-        mkdir -p ~/cache/toolchain
-        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
-        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
-
-    - name: Set Toolchain Path
-      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
-
-    - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
-
-    - name: Build
-      run: python3 tools/build_family.py ${{ matrix.family }}
-
-    - name: Linker Map
-      run: |
-        pip install linkermap/
-        for ex in `ls -d examples/device/*/`; do \
-          find ${ex} -name *.map -print -quit | \
-          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
-        done
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
deleted file mode 100644
index 369048fc6..000000000
--- a/.github/workflows/build_arm.yml
+++ /dev/null
@@ -1,226 +0,0 @@
-name: Build ARM
-
-on:
-  pull_request:
-  push:
-  release:
-    types:
-      - created
-
-jobs:
-  # ---------------------------------------
-  # Unit testing with Ceedling
-  # ---------------------------------------
-  unit-test:
-    runs-on: ubuntu-latest
-    steps:
-    - name: Setup Ruby
-      uses: ruby/setup-ruby@v1
-      with:
-        ruby-version: '2.7'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Unit Tests
-      run: |
-        # Install Ceedling
-        gem install ceedling
-        cd test
-        ceedling test:all
-
-  # ---------------------------------------
-  # Build ARM family
-  # ---------------------------------------
-  build-arm:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        family:
-        # Alphabetical order
-        - 'broadcom_32bit'
-        - 'imxrt'
-        - 'lpc15'
-        - 'lpc18'
-        - 'lpc54'
-        - 'lpc55'
-        - 'mm32'
-        - 'msp432e4'
-        - 'nrf'
-        - 'rp2040'
-        - 'samd11'
-        - 'samd21'
-        - 'samd51'
-        - 'saml2x'
-        - 'stm32f0'
-        - 'stm32f1'
-        - 'stm32f4'
-        - 'stm32f7'
-        - 'stm32g4'
-        - 'stm32h7'
-        - 'stm32l4'
-        - 'stm32wb'
-        - 'tm4c123'
-        - 'xmc4000'
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v4
-      with:
-        python-version: '3.x'
-
-    - name: Install ARM GCC
-      uses: carlosperate/arm-none-eabi-gcc-action@v1
-      with:
-        release: '11.2-2022.02'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
-
-    - name: Checkout hathach/linkermap
-      uses: actions/checkout@v3
-      with:
-         repository: hathach/linkermap
-         path: linkermap
-
-    - name: Checkout pico-sdk for rp2040
-      if: matrix.family == 'rp2040'
-      run: |
-        git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
-        echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
-
-    - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
-
-    - name: Build
-      run: python3 tools/build_family.py ${{ matrix.family }}
-
-    - name: Linker Map
-      run: |
-        pip install linkermap/
-        # find -quit to only print linkermap of 1 board per example
-        for ex in `ls -d examples/*/*/`
-        do
-          find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
-        done
-
-    # Following steps are for Hardware Test with self-hosted
-
-    - name: Prepare Artifacts
-      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
-      run: find examples/ -name "*.elf" -exec mv {} . \;
-
-    - name: Upload Artifacts for Hardware Test
-      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
-      uses: actions/upload-artifact@v3
-      with:
-        name: ${{ matrix.family }}
-        path: |
-          *.elf
-
-  # ---------------------------------------
-  # Build all no-family (orphaned) boards
-  # disable this workflow since it is often failed randomly
-  # ---------------------------------------
-  build-board:
-    runs-on: ubuntu-latest
-    if: false
-    strategy:
-      fail-fast: false
-      matrix:
-        example:
-        # Alphabetical order, a group of 4
-        - 'device/audio_test device/board_test device/cdc_dual_ports device/cdc_msc'
-        - 'device/cdc_msc_freertos device/dfu_runtime device/hid_composite device/hid_composite_freertos'
-        - 'device/hid_generic_inout device/hid_multiple_interface device/midi_test device/msc_dual_lun'
-        - 'device/net_lwip_webserver'
-        - 'device/uac2_headset device/usbtmc device/webusb_serial host/cdc_msc_hid'
-
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v4
-      with:
-        python-version: '3.x'
-
-    - name: Install ARM GCC
-      uses: carlosperate/arm-none-eabi-gcc-action@v1
-      with:
-        release: '11.2-2022.02'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
-    - name: Build
-      run: python3 tools/build_board.py ${{ matrix.example }}
-
-  # ---------------------------------------
-  # Hardware in the loop (HIL)
-  # Current self-hosted instance is running on an RPI4 with
-  # - pico + pico-probe connected via USB
-  # - pico-probe is /dev/ttyACM0
-  # ---------------------------------------
-  hw-rp2040-test:
-    # Limit the run to only hathach due to limited resource on RPI4
-    if: github.repository_owner == 'hathach'
-    needs: build-arm
-    runs-on: [self-hosted, Linux, ARM64, rp2040]
-
-    steps:
-    - name: Clean workspace
-      run: |
-        echo "Cleaning up previous run"
-        rm -rf "${{ github.workspace }}"
-        mkdir -p "${{ github.workspace }}"
-
-    - name: Download rp2040 Artifacts
-      uses: actions/download-artifact@v3
-      with:
-        name: rp2040
-
-    - name: Create flash.sh
-      run: |
-        echo > flash.sh 'cmdout=$(openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit")'
-        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
-        chmod +x flash.sh
-
-    - name: Test cdc_dual_ports
-      run: |
-        ./flash.sh cdc_dual_ports.elf
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-
-    - name: Test cdc_msc
-      run: |
-        ./flash.sh cdc_msc.elf
-        readme='/media/pi/TinyUSB MSC/README.TXT'
-        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -f "$readme" && echo "$readme exists"
-        cat "$readme"
-
-    - name: Test dfu
-      run: |
-        ./flash.sh dfu.elf
-        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
-        dfu-util -d cafe -a 0 -U dfu0
-        dfu-util -d cafe -a 1 -U dfu1
-        grep "TinyUSB DFU! - Partition 0" dfu0
-        grep "TinyUSB DFU! - Partition 1" dfu1
-
-    - name: Test dfu_runtime
-      run: |
-        ./flash.sh dfu_runtime.elf
-        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
-
-#    - name: Test hid_boot_interface
-#      run: |
-#        ./flash.sh hid_boot_interface.elf
-#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
-
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
deleted file mode 100644
index 51d91de49..000000000
--- a/.github/workflows/build_esp.yml
+++ /dev/null
@@ -1,52 +0,0 @@
-name: Build ESP
-
-on:
-  pull_request:
-  push:
-  release:
-    types:
-      - created
-
-jobs:
-  build-esp:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        board:
-        # Alphabetical order
-        # ESP32-S2
-        - 'espressif_saola_1'
-        # ESP32-S3
-        #- 'espressif_s3_devkitm'
-        # S3 compile error with "dangerous relocation: call8: call target out of range: memcpy"
-
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v4
-      with:
-        python-version: '3.x'
-
-    - name: Pull ESP-IDF docker
-      run: docker pull espressif/idf:latest
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Checkout hathach/linkermap
-      uses: actions/checkout@v3
-      with:
-         repository: hathach/linkermap
-         path: linkermap
-
-    - name: Build
-      run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32sx.py ${{ matrix.board }}
-
-    - name: Linker Map
-      run: |
-        pip install linkermap/
-        # find -quit to only print linkermap of 1 board per example
-        for ex in `ls -d examples/device/*/`
-        do
-          find ${ex} -maxdepth 3 -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
-        done
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
deleted file mode 100644
index 1ef25a6a0..000000000
--- a/.github/workflows/build_msp430.yml
+++ /dev/null
@@ -1,71 +0,0 @@
-name: Build MSP430
-
-on:
-  pull_request:
-  push:
-  release:
-    types:
-      - created
-
-jobs:  
-  build-msp430:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        family:
-        # Alphabetical order
-        - 'msp430'
-
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v4
-      with:
-        python-version: '3.x'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
-    - name: Checkout hathach/linkermap
-      uses: actions/checkout@v3
-      with:
-         repository: hathach/linkermap
-         path: linkermap
-
-    - name: Set Toolchain URL
-      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2
-
-    - name: Cache Toolchain
-      uses: actions/cache@v3
-      id: cache-toolchain
-      with:
-        path: ~/cache/
-        key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }}
-
-    - name: Install Toolchain
-      if: steps.cache-toolchain.outputs.cache-hit != 'true'
-      run: |
-        mkdir -p ~/cache/toolchain
-        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.bz2
-        tar -C ~/cache/toolchain -xaf toolchain.tar.bz2
-
-    - name: Set Toolchain Path
-      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
-
-    - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
-
-    - name: Build
-      run: python3 tools/build_family.py ${{ matrix.family }}
-
-    - name: Linker Map
-      run: |
-        pip install linkermap/
-        # find -quit to only print linkermap of 1 board per example
-        for ex in `ls -d examples/device/*/`
-        do
-          find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
-        done
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
deleted file mode 100644
index 2e272c832..000000000
--- a/.github/workflows/build_renesas.yml
+++ /dev/null
@@ -1,71 +0,0 @@
-name: Build Renesas
-
-on:
-  pull_request:
-  push:
-  release:
-    types:
-      - created
-
-jobs:
-  build-rx:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        family:
-        # Alphabetical order
-        - 'rx'
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v4
-      with:
-        python-version: '3.x'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
-    - name: Checkout hathach/linkermap
-      uses: actions/checkout@v3
-      with:
-         repository: hathach/linkermap
-         path: linkermap
-
-    - name: Set Toolchain URL
-      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run
-
-    - name: Cache Toolchain
-      uses: actions/cache@v3
-      id: cache-toolchain
-      with:
-        path: ~/cache/
-        key: ${{ runner.os }}-21-03-30-${{ env.TOOLCHAIN_URL }}
-
-    - name: Install Toolchain
-      if: steps.cache-toolchain.outputs.cache-hit != 'true'
-      run: |
-        mkdir -p ~/cache/toolchain/gnurx
-        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.run
-        chmod +x toolchain.run
-        ./toolchain.run -p ~/cache/toolchain/gnurx -y
-
-    - name: Set Toolchain Path
-      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
-
-    - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
-
-    - name: Build
-      run: python3 tools/build_family.py ${{ matrix.family }}
-
-    - name: Linker Map
-      run: |
-        pip install linkermap/
-        # find -quit to only print linkermap of 1 board per example
-        for ex in `ls -d examples/device/*/`
-        do
-          find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
-        done
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
deleted file mode 100644
index 61c1c60c5..000000000
--- a/.github/workflows/build_riscv.yml
+++ /dev/null
@@ -1,71 +0,0 @@
-name: Build RISC-V
-
-on:
-  pull_request:
-  push:
-  release:
-    types:
-      - created
-
-jobs:
-  build-riscv:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        family:
-        # Alphabetical order
-        - 'fomu'
-        - 'gd32vf103'
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v4
-      with:
-        python-version: '3.x'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
-    - name: Checkout hathach/linkermap
-      uses: actions/checkout@v3
-      with:
-         repository: hathach/linkermap
-         path: linkermap
-
-    - name: Set Toolchain URL
-      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v10.1.0-1.1/xpack-riscv-none-embed-gcc-10.1.0-1.1-linux-x64.tar.gz
-
-    - name: Cache Toolchain
-      uses: actions/cache@v3
-      id: cache-toolchain
-      with:
-        path: ~/cache/
-        key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }}
-
-    - name: Install Toolchain
-      if: steps.cache-toolchain.outputs.cache-hit != 'true'
-      run: |
-        mkdir -p ~/cache/toolchain
-        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
-        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
-
-    - name: Set Toolchain Path
-      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
-
-    - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
-
-    - name: Build
-      run: python3 tools/build_family.py ${{ matrix.family }}
-
-    - name: Linker Map
-      run: |
-        pip install linkermap/
-        # find -quit to only print linkermap of 1 board per example
-        for ex in `ls -d examples/device/*/`
-        do
-          find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
-        done
diff --git a/.github/workflows/build_util.yml b/.github/workflows/build_util.yml
new file mode 100644
index 000000000..2de68c6f3
--- /dev/null
+++ b/.github/workflows/build_util.yml
@@ -0,0 +1,81 @@
+name: Reusable build util
+
+on:
+  workflow_call:
+    inputs:
+      build-system:
+        required: true
+        type: string
+      toolchain:
+        required: true
+        type: string
+      build-args:
+        required: true
+        type: string
+      one-per-family:
+        required: false
+        default: false
+        type: boolean
+      upload-artifacts:
+        required: false
+        default: false
+        type: boolean
+      os:
+        required: false
+        type: string
+        default: 'ubuntu-latest'
+
+jobs:
+  family:
+    runs-on: ${{ inputs.os }}
+    strategy:
+      fail-fast: false
+      matrix:
+        arg: ${{ fromJSON(inputs.build-args) }}
+    steps:
+      - name: Checkout TinyUSB
+        uses: actions/checkout@v4
+
+      - name: Setup Toolchain
+        id: setup-toolchain
+        uses: ./.github/actions/setup_toolchain
+        with:
+          toolchain: ${{ inputs.toolchain }}
+
+      - name: Get Dependencies
+        uses: ./.github/actions/get_deps
+        with:
+          arg: ${{ matrix.arg }}
+
+      - name: Set build one-per-family option
+        id: set-one-per-family
+        run: |
+          if [[ "${{ inputs.one-per-family }}" == "true" ]]; then
+            BUILD_OPTION="--one-per-family"
+          fi
+          echo "build_option=$BUILD_OPTION"
+          echo "build_option=$BUILD_OPTION" >> $GITHUB_OUTPUT
+        shell: bash
+
+      - name: Build
+        run: |
+          if [ "${{ inputs.toolchain }}" == "esp-idf" ]; then
+            docker run --rm -v $PWD:/project -w /project espressif/idf:tinyusb python tools/build.py ${{ matrix.arg }}
+          else
+            python tools/build.py -s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ steps.set-one-per-family.outputs.build_option }} ${{ matrix.arg }}
+          fi
+        shell: bash
+
+      - name: Upload Artifacts for Hardware Testing
+        if: ${{ inputs.upload-artifacts }}
+        uses: actions/upload-artifact@v4
+        with:
+          name: ${{ matrix.arg }}
+          path: |
+            cmake-build/cmake-build-*/*/*/*.elf
+            cmake-build/cmake-build-*/*/*/*.bin
+            cmake-build/cmake-build-*/*/*/*.bin
+            cmake-build/cmake-build-*/*/*/bootloader/bootloader.bin
+            cmake-build/cmake-build-*/*/*/partition_table/partition-table.bin
+            cmake-build/cmake-build-*/*/*/config.env
+            cmake-build/cmake-build-*/*/*/flash_args
diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py
new file mode 100755
index 000000000..410508246
--- /dev/null
+++ b/.github/workflows/ci_set_matrix.py
@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+import json
+
+# toolchain, url
+toolchain_list = [
+    "aarch64-gcc",
+    "arm-clang",
+    "arm-iar",
+    "arm-gcc",
+    "esp-idf",
+    "msp430-gcc",
+    "riscv-gcc",
+    "rx-gcc"
+]
+
+# family: [supported toolchain]
+family_list = {
+    "broadcom_32bit": ["arm-gcc"],
+    "broadcom_64bit": ["aarch64-gcc"],
+    "ch32v10x ch32v20x ch32v307 fomu gd32vf103": ["riscv-gcc"],
+    "da1469x": ["arm-gcc"],
+    "imxrt": ["arm-gcc", "arm-clang"],
+    "kinetis_k kinetis_kl kinetis_k32l2": ["arm-gcc", "arm-clang"],
+    "lpc11 lpc13 lpc15": ["arm-gcc", "arm-clang"],
+    "lpc17 lpc18 lpc40 lpc43": ["arm-gcc", "arm-clang"],
+    "lpc51 lpc54 lpc55": ["arm-gcc", "arm-clang"],
+    "max32650 max32666 max32690 max78002": ["arm-gcc"],
+    "mcx": ["arm-gcc"],
+    "mm32": ["arm-gcc"],
+    "msp430": ["msp430-gcc"],
+    "msp432e4 tm4c": ["arm-gcc"],
+    "nrf": ["arm-gcc", "arm-clang"],
+    "ra": ["arm-gcc"],
+    "rp2040": ["arm-gcc"],
+    "rx": ["rx-gcc"],
+    "samd11 saml2x": ["arm-gcc", "arm-clang"],
+    "samd21": ["arm-gcc", "arm-clang"],
+    "samd5x_e5x samg": ["arm-gcc", "arm-clang"],
+    "stm32c0 stm32f0 stm32f1 stm32f2 stm32f3": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32f4": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32f7": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32g0 stm32g4 stm32h5": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32h7": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32l0 stm32l4": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32u5 stm32wb": ["arm-gcc", "arm-clang", "arm-iar"],
+    "xmc4000": ["arm-gcc"],
+    "-bespressif_kaluga_1": ["esp-idf"],
+    "-bespressif_s3_devkitm": ["esp-idf"],
+    "-bespressif_p4_function_ev": ["esp-idf"],
+}
+
+
+def set_matrix_json():
+    matrix = {}
+    for toolchain in toolchain_list:
+        filtered_families = [family for family, supported_toolchain in family_list.items() if
+                             toolchain in supported_toolchain]
+        matrix[toolchain] = filtered_families
+
+    print(json.dumps(matrix))
+
+
+if __name__ == '__main__':
+    set_matrix_json()
diff --git a/.github/workflows/cifuzz.yml b/.github/workflows/cifuzz.yml
new file mode 100644
index 000000000..d7f1fc066
--- /dev/null
+++ b/.github/workflows/cifuzz.yml
@@ -0,0 +1,36 @@
+name: CIFuzz
+on:
+  workflow_dispatch:
+  pull_request:
+    branches:
+      - master
+    paths:
+      - '**.c'
+      - '**.cc'
+      - '**.cpp'
+      - '**.cxx'
+      - '**.h'
+jobs:
+ Fuzzing:
+   runs-on: ubuntu-latest
+   steps:
+   - name: Build Fuzzers
+     id: build
+     uses: google/oss-fuzz/infra/cifuzz/actions/build_fuzzers@master
+     with:
+       oss-fuzz-project-name: 'tinyusb'
+       language: c++
+
+   - name: Run Fuzzers
+     uses: google/oss-fuzz/infra/cifuzz/actions/run_fuzzers@master
+     with:
+       oss-fuzz-project-name: 'tinyusb'
+       language: c++
+       fuzz-seconds: 400
+
+   - name: Upload Crash
+     uses: actions/upload-artifact@v4
+     if: failure() && steps.build.outcome == 'success'
+     with:
+       name: artifacts
+       path: ./out/artifacts
diff --git a/.github/workflows/codeql-buildscript.sh b/.github/workflows/codeql-buildscript.sh
new file mode 100644
index 000000000..272b55d22
--- /dev/null
+++ b/.github/workflows/codeql-buildscript.sh
@@ -0,0 +1,6 @@
+#!/usr/bin/env bash
+
+FAMILY=stm32l4
+pip install click
+python3 tools/get_deps.py $FAMILY
+python3 tools/build.py -s make $FAMILY
diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml
new file mode 100644
index 000000000..be4c2dd87
--- /dev/null
+++ b/.github/workflows/codeql.yml
@@ -0,0 +1,137 @@
+# For most projects, this workflow file will not need changing; you simply need
+# to commit it to your repository.
+#
+# You may wish to alter this file to override the set of languages analyzed,
+# or to provide custom queries or build logic.
+#
+# ******** NOTE ********
+# We have attempted to detect the languages in your repository. Please check
+# the `language` matrix defined below to confirm you have the correct set of
+# supported CodeQL languages.
+#
+name: "CodeQL"
+
+on:
+  push:
+    branches: [ 'master' ]
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+      - '.github/workflows/codeql.yml'
+  pull_request:
+    branches: [ 'master' ]
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+      - '.github/workflows/codeql.yml'
+  schedule:
+    - cron: '0 0 * * *'
+
+jobs:
+  analyze:
+    name: Analyze
+    # Runner size impacts CodeQL analysis time. To learn more, please see:
+    #   - https://gh.io/recommended-hardware-resources-for-running-codeql
+    #   - https://gh.io/supported-runners-and-hardware-resources
+    #   - https://gh.io/using-larger-runners
+    # Consider using larger runners for possible analysis time improvements.
+    runs-on: ubuntu-latest
+    timeout-minutes: 360
+    permissions:
+      actions: read
+      contents: read
+      security-events: write
+
+    strategy:
+      fail-fast: false
+      matrix:
+        language: [ 'c-cpp' ]
+        # CodeQL supports [ 'c-cpp', 'csharp', 'go', 'java-kotlin', 'javascript-typescript', 'python', 'ruby', 'swift' ]
+        # Use only 'java-kotlin' to analyze code written in Java, Kotlin or both
+        # Use only 'javascript-typescript' to analyze code written in JavaScript, TypeScript or both
+        # Learn more about CodeQL language support at https://aka.ms/codeql-docs/language-support
+
+    steps:
+    - name: Checkout repository
+      uses: actions/checkout@v4
+
+    - name: Setup Toolchain
+      uses: ./.github/actions/setup_toolchain
+      with:
+        toolchain: 'arm-gcc'
+
+    # Initializes the CodeQL tools for scanning.
+    - name: Initialize CodeQL
+      uses: github/codeql-action/init@v2
+      with:
+        languages: ${{ matrix.language }}
+        # If you wish to specify custom queries, you can do so here or in a config file.
+        # By default, queries listed here will override any specified in a config file.
+        # Prefix the list here with "+" to use these queries and those in the config file.
+
+        # For more details on CodeQL's query packs, refer to: https://docs.github.com/en/code-security/code-scanning/automatically-scanning-your-code-for-vulnerabilities-and-errors/configuring-code-scanning#using-queries-in-ql-packs
+        # queries: security-extended,security-and-quality
+        queries: security-and-quality
+
+
+    # Autobuild attempts to build any compiled languages (C/C++, C#, Go, Java, or Swift).
+    # If this step fails, then you should remove it and run the build manually (see below)
+    #- name: Autobuild
+    #  uses: github/codeql-action/autobuild@v2
+
+    # ℹī¸ Command-line programs to run using the OS shell.
+    # 📚 See https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions#jobsjob_idstepsrun
+
+    #   If the Autobuild fails above, remove it and uncomment the following three lines.
+    #   modify them (or add more) to build your code if your project, please refer to the EXAMPLE below for guidance.
+
+    - run: |
+        ./.github/workflows/codeql-buildscript.sh
+
+    - name: Perform CodeQL Analysis
+      uses: github/codeql-action/analyze@v2
+      with:
+        category: "/language:${{matrix.language}}"
+        upload: false
+      id: step1
+
+    # Filter out rules with low severity or high false positive rate
+    # Also filter out warnings in third-party code
+    - name: Filter out unwanted errors and warnings
+      uses: advanced-security/filter-sarif@v1
+      with:
+        patterns: |
+          -**:cpp/path-injection
+          -**:cpp/world-writable-file-creation
+          -**:cpp/poorly-documented-function
+          -**:cpp/potentially-dangerous-function
+          -**:cpp/use-of-goto
+          -**:cpp/integer-multiplication-cast-to-long
+          -**:cpp/comparison-with-wider-type
+          -**:cpp/leap-year/*
+          -**:cpp/ambiguously-signed-bit-field
+          -**:cpp/suspicious-pointer-scaling
+          -**:cpp/suspicious-pointer-scaling-void
+          -**:cpp/unsigned-comparison-zero
+          -**/third*party/**
+          -**/3rd*party/**
+          -**/external/**
+        input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif
+        output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif
+
+    - name: Upload SARIF
+      uses: github/codeql-action/upload-sarif@v2
+      with:
+        sarif_file: ${{ steps.step1.outputs.sarif-output }}
+        category: "/language:${{matrix.language}}"
+
+    - name: Archive CodeQL results
+      uses: actions/upload-artifact@v4
+      with:
+        name: codeql-results
+        path: ${{ steps.step1.outputs.sarif-output }}
+        retention-days: 5
diff --git a/.github/workflows/fail_on_error.py b/.github/workflows/fail_on_error.py
new file mode 100755
index 000000000..29791742b
--- /dev/null
+++ b/.github/workflows/fail_on_error.py
@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+
+import json
+import sys
+
+# Return whether SARIF file contains error-level results
+def codeql_sarif_contain_error(filename):
+    with open(filename, 'r') as f:
+        s = json.load(f)
+
+    for run in s.get('runs', []):
+        rules_metadata = run['tool']['driver']['rules']
+        if not rules_metadata:
+            rules_metadata = run['tool']['extensions'][0]['rules']
+
+        for res in run.get('results', []):
+            if 'ruleIndex' in res:
+                rule_index = res['ruleIndex']
+            elif 'rule' in res and 'index' in res['rule']:
+                rule_index = res['rule']['index']
+            else:
+                continue
+            try:
+                rule_level = rules_metadata[rule_index]['defaultConfiguration']['level']
+            except IndexError as e:
+                print(e, rule_index, len(rules_metadata))
+            else:
+                if rule_level == 'error':
+                    return True
+    return False
+
+if __name__ == "__main__":
+    if codeql_sarif_contain_error(sys.argv[1]):
+        sys.exit(1)
diff --git a/.github/workflows/hil_test.yml b/.github/workflows/hil_test.yml
new file mode 100644
index 000000000..c890933ec
--- /dev/null
+++ b/.github/workflows/hil_test.yml
@@ -0,0 +1,130 @@
+name: Hardware Test
+
+on:
+  workflow_dispatch:
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+      - 'test/hil/**'
+      - 'tools/get_deps.py'
+      - '.github/actions/**'
+      - '.github/workflows/hil_test.yml'
+concurrency:
+  group: ${{ github.workflow }}-${{ github.ref }}
+  cancel-in-progress: true
+
+env:
+  HIL_JSON: test/hil/tinyusb.json
+
+jobs:
+  set-matrix:
+    runs-on: ubuntu-latest
+    outputs:
+      json: ${{ steps.set-matrix-json.outputs.matrix }}
+    steps:
+      - name: Checkout TinyUSB
+        uses: actions/checkout@v4
+
+      - name: Generate matrix json
+        id: set-matrix-json
+        run: |
+          MATRIX_JSON=$(python test/hil/hil_ci_set_matrix.py ${{ env.HIL_JSON }})
+          echo "matrix=$MATRIX_JSON"
+          echo "matrix=$MATRIX_JSON" >> $GITHUB_OUTPUT
+
+  # ---------------------------------------
+  # Build arm-gcc
+  # ---------------------------------------
+  build:
+    if: github.repository_owner == 'hathach'
+    needs: set-matrix
+    uses: ./.github/workflows/build_util.yml
+    strategy:
+      fail-fast: false
+      matrix:
+        toolchain:
+          - 'arm-gcc'
+          - 'esp-idf'
+    with:
+      build-system: 'cmake'
+      toolchain: ${{ matrix.toolchain }}
+      build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)[matrix.toolchain]) }}
+      one-per-family: true
+      upload-artifacts: true
+
+  # ---------------------------------------
+  # Hardware in the loop (HIL)
+  # self-hosted on local VM, for attached hardware checkout HIL_JSON
+  # ---------------------------------------
+  hil-tinyusb:
+    if: github.repository_owner == 'hathach'
+    needs: build
+    runs-on: [self-hosted, X64, hathach, hardware-in-the-loop]
+    steps:
+      - name: Clean workspace
+        run: |
+          echo "Cleaning up previous run"
+          rm -rf "${{ github.workspace }}"
+          mkdir -p "${{ github.workspace }}"
+
+      - name: Checkout TinyUSB
+        uses: actions/checkout@v4
+        with:
+          sparse-checkout: test/hil
+
+      - name: Download Artifacts
+        uses: actions/download-artifact@v4
+        with:
+          path: cmake-build
+          merge-multiple: true
+
+      - name: Test on actual hardware
+        run: |
+          ls cmake-build/
+          python3 test/hil/hil_test.py ${{ env.HIL_JSON }}
+
+  # ---------------------------------------
+  # Hardware in the loop (HIL)
+  # self-hosted by HFP, build with IAR toolchain, for attached hardware checkout test/hil/hfp.json
+  # Since IAR Token secret is not passed to forked PR, only build on PR from the same repo
+  # ---------------------------------------
+  hil-hfp:
+    if: github.repository_owner == 'hathach' && github.event.pull_request.head.repo.fork == false
+    runs-on: [self-hosted, Linux, X64, hifiphile]
+    env:
+      IAR_LMS_CLOUD_URL: ${{ vars.IAR_LMS_CLOUD_URL }}
+      IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }}
+    steps:
+      - name: Clean workspace
+        run: |
+          echo "Cleaning up previous run"
+          rm -rf "${{ github.workspace }}"
+          mkdir -p "${{ github.workspace }}"
+
+      - name: Toolchain version
+        run: |
+          echo IAR_LMS_CLOUD_URL=$IAR_LMS_CLOUD_URL
+          iccarm --version
+
+      - name: Checkout TinyUSB
+        uses: actions/checkout@v4
+
+      - name: Get build boards
+        run: |
+          MATRIX_JSON=$(python test/hil/hil_ci_set_matrix.py test/hil/hfp.json)
+          BUILD_ARGS=$(echo $MATRIX_JSON | jq -r '.["arm-gcc"] | join(" ")')
+          echo "BUILD_ARGS=$BUILD_ARGS"
+          echo "BUILD_ARGS=$BUILD_ARGS" >> $GITHUB_ENV
+
+      - name: Get Dependencies
+        run: python3 tools/get_deps.py $BUILD_ARGS
+
+      - name: Build
+        run: python3 tools/build.py --toolchain iar $BUILD_ARGS
+
+      - name: Test on actual hardware (hardware in the loop)
+        run: python3 test/hil/hil_test.py hfp.json
diff --git a/.github/workflows/labeler.yml b/.github/workflows/labeler.yml
new file mode 100644
index 000000000..c3cc59d0d
--- /dev/null
+++ b/.github/workflows/labeler.yml
@@ -0,0 +1,73 @@
+name: Labeler
+
+on:
+  issues:
+    types: [opened]
+  pull_request_target:
+    types: [opened]
+
+jobs:
+  label-priority:
+    runs-on: ubuntu-latest
+    permissions:
+      issues: write
+      pull-requests: write
+    steps:
+      - name: Label New Issue or PR
+        uses: actions/github-script@v7
+        with:
+          github-token: ${{ secrets.GITHUB_TOKEN }}
+          script: |
+            let label = '';
+            let username = '';
+            let issueOrPrNumber = 0;
+
+            if (context.eventName === 'issues') {
+              username = context.payload.issue.user.login;
+              issueOrPrNumber = context.payload.issue.number;
+            } else if (context.eventName === 'pull_request_target') {
+              username = context.payload.pull_request.user.login;
+              issueOrPrNumber = context.payload.pull_request.number;
+            }
+
+            // Check if an Adafruit member
+            try {
+              const adafruitResponse = await github.rest.orgs.checkMembershipForUser({
+                org: 'adafruit',
+                username: username
+              });
+
+              if (adafruitResponse.status === 204) {
+                console.log('Adafruit Member');
+                label = 'Prio Urgent';
+              }
+            } catch (error) {
+              console.log('Not an Adafruit member');
+            }
+
+            // Check if a contributor
+            if (label == '') {
+              try {
+                const collaboratorResponse = await github.rest.repos.checkCollaborator({
+                  owner: context.repo.owner,
+                  repo: context.repo.repo,
+                  username: username
+                });
+
+                if (collaboratorResponse.status === 204) {
+                  console.log('Contributor');
+                  label = 'Prio Higher';
+                }
+              } catch (error) {
+                console.log('Not a contributor');
+              }
+            }
+
+            if (label !== '') {
+              await github.rest.issues.addLabels({
+                owner: context.repo.owner,
+                repo: context.repo.repo,
+                issue_number: issueOrPrNumber,
+                labels: [label]
+              });
+            }
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
new file mode 100644
index 000000000..ed0efd66e
--- /dev/null
+++ b/.github/workflows/pre-commit.yml
@@ -0,0 +1,45 @@
+name: pre-commit
+
+on:
+  workflow_dispatch:
+  push:
+  pull_request:
+    branches: [ master ]
+
+concurrency:
+  group: ${{ github.workflow }}-${{ github.ref }}
+  cancel-in-progress: true
+
+jobs:
+  pre-commit:
+    runs-on: ubuntu-latest
+    steps:
+    - name: Setup Ruby
+      uses: ruby/setup-ruby@v1
+      with:
+        ruby-version: '3.0'
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v4
+
+    - name: Get Dependencies
+      run: |
+        gem install ceedling
+        #cd test/unit-test
+        #ceedling test:all
+
+    - name: Run pre-commit
+      uses: pre-commit/action@v3.0.1
+
+    - name: Build Fuzzer
+      run: |
+        sudo apt install libc++-dev libc++abi-dev
+        clang --version
+        export CC=clang
+        export CXX=clang++
+        fuzz_harness=$(ls -d test/fuzz/device/*/)
+        for h in $fuzz_harness
+        do
+          make -C $h get-deps
+          make -C $h all
+        done
diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
deleted file mode 100644
index 3ef1fdc56..000000000
--- a/.github/workflows/test_hardware.yml
+++ /dev/null
@@ -1,85 +0,0 @@
-name: Hardware Test
-on:
-  pull_request:
-  push:
-  release:
-    types:
-      - created
-
-# Hardware in the loop (HIL)
-# Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
-# - STM32L412 Nucleo with on-board jlink as ttyACM0
-
-jobs:
-  stm32l412nucleo-test:
-    runs-on: [self-hosted, Linux, X64, hifiphile]
-
-    steps:
-    - name: Clean workspace
-      run: |
-        echo "Cleaning up previous run"
-        rm -rf "${{ github.workspace }}"
-        mkdir -p "${{ github.workspace }}"
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Get Dependencies and Build
-      run: |
-        git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-        python3 tools/get_dependencies.py stm32l4
-        python3 tools/build_family.py stm32l4
-
-    - name: Pick-up elf files
-      run: |
-        mkdir stm32l412nucleo/
-        find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} stm32l412nucleo/ \;
-
-    - name: Create flash.sh
-      run: |
-        echo > flash.sh 'echo halt > flash.jlink'
-        echo >> flash.sh 'echo r >> flash.jlink'
-        echo >> flash.sh 'echo loadfile stm32l412nucleo/$1 >> flash.jlink'
-        echo >> flash.sh 'echo r >> flash.jlink'
-        echo >> flash.sh 'echo go >> flash.jlink'
-        echo >> flash.sh 'echo exit >> flash.jlink'
-        echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
-        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
-        chmod +x flash.sh
-
-    - name: Test cdc_dual_ports
-      run: |
-        ./flash.sh cdc_dual_ports.elf
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-
-      # Debian does not auto mount usb drive. skip this test for now
-    - name: Test cdc_msc
-      if: false
-      run: |
-        ./flash.sh cdc_msc.elf
-        readme='/media/pi/TinyUSB MSC/README.TXT'
-        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -f "$readme" && echo "$readme exists"
-        cat "$readme"
-
-    - name: Test dfu
-      run: |
-        ./flash.sh dfu.elf
-        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
-        dfu-util -d cafe -a 0 -U dfu0
-        dfu-util -d cafe -a 1 -U dfu1
-        grep "TinyUSB DFU! - Partition 0" dfu0
-        grep "TinyUSB DFU! - Partition 1" dfu1
-
-    - name: Test dfu_runtime
-      run: |
-        ./flash.sh dfu_runtime.elf
-        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
-
-#    - name: Test hid_boot_interface
-#      run: |
-#        ./flash.sh hid_boot_interface.elf
-#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
diff --git a/.github/workflows/trigger.yml b/.github/workflows/trigger.yml
index e434ca238..cf40ac955 100644
--- a/.github/workflows/trigger.yml
+++ b/.github/workflows/trigger.yml
@@ -1,6 +1,7 @@
 name: Trigger Repos
 
 on:
+  workflow_dispatch:
   push:
     branches: master
   release:
@@ -22,7 +23,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
     - name: Checkout code
-      uses: actions/checkout@v3
+      uses: actions/checkout@v4
 
     - name: Push to tinyusb_src
       run: |
@@ -43,7 +44,7 @@ jobs:
         if [ -n "$(git status --porcelain)" ]; then
           git add .
           git commit --message "Update from https://github.com/$GITHUB_REPOSITORY/commit/$GITHUB_SHA"
-          git push 
+          git push
         fi
 
     - name: Create tinyusb_src Release
@@ -53,8 +54,7 @@ jobs:
         cd tinyusb_src
         git tag ${{ github.event.release.tag_name }}
         git push origin ${{ github.event.release.tag_name }}
-        
+
         # Send POST reqwuest to release https://docs.github.com/en/rest/reference/repos#create-a-release
-        bb={{ github.event.release.body }}
-        bb=${bb//\n/\\\n}
+        bb="For release note, please checkout https://github.com/hathach/tinyusb/releases/tag/${{ github.event.release.tag_name }}"
         curl -X POST -H "Authorization: token ${{ secrets.API_TOKEN_GITHUB }}" -H "Accept: application/vnd.github.v3+json" --data '{"tag_name": "${{ github.event.release.tag_name }}", "name": "${{ github.event.release.name }}", "body": "$bb", "draft": ${{ github.event.release.draft }}, "prerelease": ${{ github.event.release.prerelease }}}' https://api.github.com/repos/hathach/tinyusb_src/releases
diff --git a/.gitignore b/.gitignore
index 87a5faa80..010b5c9ed 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,18 +1,22 @@
 html
 latex
+*.a
 *.d
 *.o
 *.P
-*.map
 *.axf
 *.bin
+*.elf
+*.env
+*.ind
+*.log
+*.map
+*.obj
 *.jlink
 *.emSession
-*.elf
-*.ind
-.env
+*.ninja*
 .settings/
-.idea/
+.vscode/
 .gdb_history
 /examples/*/*/build*
 test_old/
@@ -21,10 +25,16 @@ _build
 /examples/*/*/ses
 /examples/*/*/ozone
 /examples/obsolete
+hw/bsp/**/cubemx/*/
+.mxproject
 # coverity intermediate files
 cov-int
 # cppcheck build directories
 *-build-dir
 /_bin/
 __pycache__
-
+cmake-build-*
+sdkconfig
+.PVS-Studio
+.vscode/
+build/
diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644
index dcac0d9ab..000000000
--- a/.gitmodules
+++ /dev/null
@@ -1,157 +0,0 @@
-[submodule "hw/mcu/nordic/nrfx"]
-	path = hw/mcu/nordic/nrfx
-	url = https://github.com/NordicSemiconductor/nrfx.git
-[submodule "tools/uf2"]
-	path = tools/uf2
-	url = https://github.com/microsoft/uf2.git
-[submodule "hw/mcu/sony/cxd56/spresense-exported-sdk"]
-	path = hw/mcu/sony/cxd56/spresense-exported-sdk
-	url = https://github.com/sonydevworld/spresense-exported-sdk.git
-[submodule "hw/mcu/ti"]
-	path = hw/mcu/ti
-	url = https://github.com/hathach/ti_driver.git
-[submodule "hw/mcu/microchip"]
-	path = hw/mcu/microchip
-	url = https://github.com/hathach/microchip_driver.git
-[submodule "hw/mcu/nuvoton"]
-	path = hw/mcu/nuvoton
-	url = https://github.com/majbthrd/nuc_driver.git
-[submodule "lib/lwip"]
-	path = lib/lwip
-	url = https://github.com/lwip-tcpip/lwip.git
-[submodule "hw/mcu/st/cmsis_device_f4"]
-	path = hw/mcu/st/cmsis_device_f4
-	url = https://github.com/STMicroelectronics/cmsis_device_f4.git
-[submodule "hw/mcu/st/stm32f4xx_hal_driver"]
-	path = hw/mcu/st/stm32f4xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f0"]
-	path = hw/mcu/st/cmsis_device_f0
-	url = https://github.com/STMicroelectronics/cmsis_device_f0.git
-[submodule "hw/mcu/st/stm32f0xx_hal_driver"]
-	path = hw/mcu/st/stm32f0xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f1"]
-	path = hw/mcu/st/cmsis_device_f1
-	url = https://github.com/STMicroelectronics/cmsis_device_f1.git
-[submodule "hw/mcu/st/stm32f1xx_hal_driver"]
-	path = hw/mcu/st/stm32f1xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f2"]
-	path = hw/mcu/st/cmsis_device_f2
-	url = https://github.com/STMicroelectronics/cmsis_device_f2.git
-[submodule "hw/mcu/st/stm32f2xx_hal_driver"]
-	path = hw/mcu/st/stm32f2xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f3"]
-	path = hw/mcu/st/cmsis_device_f3
-	url = https://github.com/STMicroelectronics/cmsis_device_f3.git
-[submodule "hw/mcu/st/stm32f3xx_hal_driver"]
-	path = hw/mcu/st/stm32f3xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f7"]
-	path = hw/mcu/st/cmsis_device_f7
-	url = https://github.com/STMicroelectronics/cmsis_device_f7.git
-[submodule "hw/mcu/st/stm32f7xx_hal_driver"]
-	path = hw/mcu/st/stm32f7xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_h7"]
-	path = hw/mcu/st/cmsis_device_h7
-	url = https://github.com/STMicroelectronics/cmsis_device_h7.git
-[submodule "hw/mcu/st/stm32h7xx_hal_driver"]
-	path = hw/mcu/st/stm32h7xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l0"]
-	path = hw/mcu/st/cmsis_device_l0
-	url = https://github.com/STMicroelectronics/cmsis_device_l0.git
-[submodule "hw/mcu/st/stm32l0xx_hal_driver"]
-	path = hw/mcu/st/stm32l0xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l1"]
-	path = hw/mcu/st/cmsis_device_l1
-	url = https://github.com/STMicroelectronics/cmsis_device_l1.git
-[submodule "hw/mcu/st/stm32l1xx_hal_driver"]
-	path = hw/mcu/st/stm32l1xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l4"]
-	path = hw/mcu/st/cmsis_device_l4
-	url = https://github.com/STMicroelectronics/cmsis_device_l4.git
-[submodule "hw/mcu/st/stm32l4xx_hal_driver"]
-	path = hw/mcu/st/stm32l4xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_g0"]
-	path = hw/mcu/st/cmsis_device_g0
-	url = https://github.com/STMicroelectronics/cmsis_device_g0.git
-[submodule "hw/mcu/st/stm32g0xx_hal_driver"]
-	path = hw/mcu/st/stm32g0xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_g4"]
-	path = hw/mcu/st/cmsis_device_g4
-	url = https://github.com/STMicroelectronics/cmsis_device_g4.git
-[submodule "hw/mcu/st/stm32g4xx_hal_driver"]
-	path = hw/mcu/st/stm32g4xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l5"]
-	path = hw/mcu/st/cmsis_device_l5
-	url = https://github.com/STMicroelectronics/cmsis_device_l5.git
-[submodule "hw/mcu/st/stm32l5xx_hal_driver"]
-	path = hw/mcu/st/stm32l5xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_wb"]
-	path = hw/mcu/st/cmsis_device_wb
-	url = https://github.com/STMicroelectronics/cmsis_device_wb.git
-[submodule "hw/mcu/st/stm32wbxx_hal_driver"]
-	path = hw/mcu/st/stm32wbxx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git
-[submodule "lib/sct_neopixel"]
-	path = lib/sct_neopixel
-	url = https://github.com/gsteiert/sct_neopixel
-[submodule "lib/FreeRTOS-Kernel"]
-	path = lib/FreeRTOS-Kernel
-	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
-[submodule "lib/CMSIS_5"]
-	path = lib/CMSIS_5
-	url = https://github.com/ARM-software/CMSIS_5.git
-[submodule "hw/mcu/silabs/cmsis-dfp-efm32gg12b"]
-	path = hw/mcu/silabs/cmsis-dfp-efm32gg12b
-	url = https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b
-[submodule "hw/mcu/renesas/rx"]
-	path = hw/mcu/renesas/rx
-	url = https://github.com/kkitayam/rx_device.git
-[submodule "hw/mcu/nxp/lpcopen"]
-	path = hw/mcu/nxp/lpcopen
-	url = https://github.com/hathach/nxp_lpcopen.git
-[submodule "hw/mcu/nxp/mcux-sdk"]
-	path = hw/mcu/nxp/mcux-sdk
-	url = https://github.com/NXPmicro/mcux-sdk.git
-[submodule "hw/mcu/nxp/nxp_sdk"]
-	path = hw/mcu/nxp/nxp_sdk
-	url = https://github.com/hathach/nxp_sdk.git
-[submodule "hw/mcu/gd/nuclei-sdk"]
-	path = hw/mcu/gd/nuclei-sdk
-	url = https://github.com/Nuclei-Software/nuclei-sdk.git
-[submodule "hw/mcu/bridgetek/ft9xx/ft90x-sdk"]
-	path = hw/mcu/bridgetek/ft9xx/ft90x-sdk
-	url = https://github.com/BRTSG-FOSS/ft90x-sdk
-[submodule "hw/mcu/mindmotion/mm32sdk"]
-	path = hw/mcu/mindmotion/mm32sdk
-	url = https://github.com/hathach/mm32sdk.git
-[submodule "hw/mcu/broadcom"]
-	path = hw/mcu/broadcom
-	url = https://github.com/adafruit/broadcom-peripherals.git
-	branch = main-build
-[submodule "hw/mcu/infineon/mtb-xmclib-cat3"]
-	path = hw/mcu/infineon/mtb-xmclib-cat3
-	url = https://github.com/Infineon/mtb-xmclib-cat3.git
-[submodule "hw/mcu/allwinner"]
-	path = hw/mcu/allwinner
-	url = https://github.com/hathach/allwinner_driver.git
-[submodule "hw/mcu/raspberry_pi/Pico-PIO-USB"]
-	path = hw/mcu/raspberry_pi/Pico-PIO-USB
-	url = https://github.com/sekigon-gonnoc/Pico-PIO-USB.git
-[submodule "hw/mcu/st/cmsis_device_u5"]
-	path = hw/mcu/st/cmsis_device_u5
-	url = https://github.com/STMicroelectronics/cmsis_device_u5
-[submodule "hw/mcu/st/stm32u5xx_hal_driver"]
-	path = hw/mcu/st/stm32u5xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32u5xx_hal_driver
diff --git a/.idea/.gitignore b/.idea/.gitignore
new file mode 100644
index 000000000..b0811f163
--- /dev/null
+++ b/.idea/.gitignore
@@ -0,0 +1,10 @@
+# Default ignored files
+/shelf/
+/workspace.xml
+# Datasource local storage ignored files
+/dataSources/
+/dataSources.local.xml
+# Editor-based HTTP Client requests
+/httpRequests/
+# GitHub Copilot persisted chat sessions
+/copilot/chatSessions
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
new file mode 100644
index 000000000..a792b1a05
--- /dev/null
+++ b/.idea/cmake.xml
@@ -0,0 +1,170 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="CMakeSharedSettings">
+    <configurations>
+      <configuration PROFILE_NAME="raspberrypi_zero" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberrypi_zero -DLOG=1" />
+      <configuration PROFILE_NAME="raspberrypi_zero2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberrypi_zero2 -DLOG=1" />
+      <configuration PROFILE_NAME="raspberrypi_cm4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberrypi_cm4 -DLOG=1" />
+      <configuration PROFILE_NAME="raspberry_pi_pico" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=1" />
+      <configuration PROFILE_NAME="raspberry_pi_pico2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico2 -DLOG=1" />
+      <configuration PROFILE_NAME="raspberry_pi_pico2_riscv" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico2_riscv -DLOG=1" />
+      <configuration PROFILE_NAME="raspberry_pi_pico-pio_host" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=1 -DCFLAGS_CLI=&quot;-DCFG_TUH_RPI_PIO_USB=1&quot;" />
+      <configuration PROFILE_NAME="feather_rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pico_sdk -DPICO_BOARD=adafruit_feather_rp2040 -DLOG=1" />
+      <configuration PROFILE_NAME="feather_rp2040_max3421" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_rp2040_max3421 -DLOG=1" />
+      <configuration PROFILE_NAME="metro_rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pico_sdk -DPICO_BOARD=adafruit_metro_rp2040 -DLOG=1 -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="adafruit_feather_esp32_v2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_feather_esp32_v2 -DMAX3421_HOST=1 -DLOG=1">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="adafruit_feather_esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_feather_esp32s2 -DMAX3421_HOST=1 -DLOG=1">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="adafruit_feather_esp32s3" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_feather_esp32s3 -DMAX3421_HOST=1 -DLOG=1">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="adafruit_metro_esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_metro_esp32s2 -DMAX3421_HOST=1 -DLOG=1">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="espressif_kaluga_1" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_kaluga_1 -DMAX3421_HOST=1 -DLOG=1">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="espressif_s3_devkitc" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitc -DLOG=1">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="espressif_p4_function_ev" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_p4_function_ev -DLOG=1">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="espressif_p4_function_ev-DMA" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_p4_function_ev -DLOG=1 -DCFLAGS_CLI=&quot;-DCFG_TUD_DWC2_DMA_ENABLE=1 -DCFG_TUH_DWC2_DMA_ENABLE=1&quot;">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="espressif_c3_devkitc" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_c3_devkitc -DMAX3421_HOST=1 -DLOG=1">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="feather_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m0_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="samd11_xplained" ENABLED="false" CONFIG_NAME="MinSizeRel" GENERATION_OPTIONS="-DBOARD=samd11_xplained" />
+      <configuration PROFILE_NAME="atsaml21_xpro" ENABLED="false" GENERATION_OPTIONS="-DBOARD=atsaml21_xpro" />
+      <configuration PROFILE_NAME="feather_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m4_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro_m4_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="feather_m4_express-zephyr" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m4_express -DLOG=1 -DMAX3421_HOST=1 -DRTOS=zephyr" />
+      <configuration PROFILE_NAME="itsybitsy_m4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=itsybitsy_m4" />
+      <configuration PROFILE_NAME="same54_xplained" ENABLED="false" GENERATION_OPTIONS="-DBOARD=same54_xplained -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="samg55_xplained" ENABLED="false" GENERATION_OPTIONS="-DBOARD=samg55_xplained" />
+      <configuration PROFILE_NAME="feather_nrf52840_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_nrf52840_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="pca10056" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="pca10056-zephyr" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=1 -DTRACE_ETM=1 -DRTOS=zephyr" BUILD_OPTIONS="-v" />
+      <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="metro m7 1011 sd" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011_sd -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="metro_m7_1011" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="mimxrt1060_evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="rt1170 evkb" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1170_evkb -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="stm32f072disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f072disco -DLOG=0 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2 -DLOG=1 -DLOGGGER=RTT" />
+      <configuration PROFILE_NAME="stm32f103ze_iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103ze_iar -DLOG=1 -DLOGGGER=RTT" />
+      <configuration PROFILE_NAME="stm32f207nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f207nucleo -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32f303disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f303disco -DLOG=0 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32f411disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f411disco -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32f412disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f412disco -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32f723disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f723disco -DLOG=0" />
+      <configuration PROFILE_NAME="stm32f723disco-DMA" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f723disco -DLOG=1 -DLOGGER=RTT -DCFLAGS_CLI=&quot;-DCFG_TUD_DWC2_DMA_ENABLE=1 -DCFG_TUH_DWC2_DMA_ENABLE=1&quot;" />
+      <configuration PROFILE_NAME="stm32f723disco_device1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f723disco -DLOG=0 -DRHPORT_DEVICE=1" />
+      <configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g0b1nucleo" />
+      <configuration PROFILE_NAME="stm32g474nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g474nucleo" />
+      <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32h563nucleo" ENABLED="false" GENERATION_OPTIONS="-DBOARD=stm32h563nucleo -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="stm32h743eval-DMA" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1 -DCFLAGS_CLI=&quot;-DCFG_TUD_DWC2_DMA_ENABLE=1&quot;" />
+      <configuration PROFILE_NAME="stm32h743eval_host1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DRHPORT_HOST=1 -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="stm32h743nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743nucleo -DLOG=1" />
+      <configuration PROFILE_NAME="stm32l0538disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l0538disco -DLOG=0 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32u575nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575nucleo -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32u5a5nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u5a5nucleo -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32wb55nucleo" ENABLED="false" GENERATION_OPTIONS="-DBOARD=stm32wb55nucleo" />
+      <configuration PROFILE_NAME="ra2a1_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra2a1_ek -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="ra4m1_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="ra4m3_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m3_ek -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="ra6m1_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="ra6m5_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ra6m5_ek PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1 -DRHPORT_DEVICE=0" />
+      <configuration PROFILE_NAME="ra8m1_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra8m1_ek -DLOG=2 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ra8m1_ek PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra8m1_ek -DLOG=2 -DLOGGER=RTT -DTRACE_ETM=1 -DRHPORT_DEVICE=0" />
+      <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=1" />
+      <configuration PROFILE_NAME="lpcxpresso11u37" ENABLED="false" GENERATION_OPTIONS="-DBOARD=lpcxpresso11u37" />
+      <configuration PROFILE_NAME="lpcxpresso11u68" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso11u68 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpcxpresso1347" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso1347 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpcxpresso1549" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso1549 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpcxpresso1769" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso1769 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ea4357" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4357 -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="lpcxpresso51u68" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso51u68 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpc5414" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54114 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpc54628" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="mcxn947brk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="frdm_mcxa153" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_mcxa153 -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_kl25z -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="frdm_k32l2a4s" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_k32l2a4s" />
+      <configuration PROFILE_NAME="frdm_k64f" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_k64f -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="msp430f5529" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=msp_exp430f5529lp" />
+      <configuration PROFILE_NAME="msp_exp432e401y" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=msp_exp432e401y -DLOG=1" />
+      <configuration PROFILE_NAME="ek_tm4c123gxl" ENABLED="false" CONFIG_NAME="MinSizeRel" GENERATION_OPTIONS="-DBOARD=ek_tm4c123gxl -DLOG=1" />
+      <configuration PROFILE_NAME="xmc4500_relax" ENABLED="false" GENERATION_OPTIONS="-DBOARD=xmc4500_relax -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="xmc4500_relax_dma" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=xmc4500_relax -DLOG=1 -DLOGGER=RTT -DCFLAGS_CLI=&quot;-DCFG_TUD_DWC2_DMA=1&quot;" />
+      <configuration PROFILE_NAME="f1c100s" ENABLED="false" GENERATION_OPTIONS="-DBOARD=f1c100s" />
+      <configuration PROFILE_NAME="mm32f327x_mb39" ENABLED="false" GENERATION_OPTIONS="-DBOARD=mm32f327x_mb39" />
+      <configuration PROFILE_NAME="fomu" ENABLED="false" GENERATION_OPTIONS="-DBOARD=fomu" />
+      <configuration PROFILE_NAME="sipeed_longan_nano" ENABLED="false" GENERATION_OPTIONS="-DBOARD=sipeed_longan_nano" />
+      <configuration PROFILE_NAME="nanoch32v203" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=nanoch32v203" />
+      <configuration PROFILE_NAME="ch32v203c_r0_1v0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203c_r0_1v0 -DLOG=0" />
+      <configuration PROFILE_NAME="ch32v203c_r0_1v0 USBFS" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203c_r0_1v0 -DPORT=1" />
+      <configuration PROFILE_NAME="ch32v203g_r0_1v0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203g_r0_1v0" />
+      <configuration PROFILE_NAME="ch32v307v_r1_1v0" ENABLED="false" GENERATION_OPTIONS="-DBOARD=ch32v307v_r1_1v0 -DLOG=1" />
+      <configuration PROFILE_NAME="ch32v307v_r1_1v0 USBFS" ENABLED="false" GENERATION_OPTIONS="-DBOARD=ch32v307v_r1_1v0 -DSPEED=full" />
+      <configuration PROFILE_NAME="da14695_dk_usb" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=da14695_dk_usb" />
+      <configuration PROFILE_NAME="max32650fthr" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=max32650fthr -DLOG=0 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="max32666fthr" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=max32666fthr -DLOG=0 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="max32690evkit" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=max32690evkit -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="mimxrt1064_evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1064_evk" />
+    </configurations>
+  </component>
+</project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/k64f.xml b/.idea/runConfigurations/k64f.xml
new file mode 100644
index 000000000..6db0dd74e
--- /dev/null
+++ b/.idea/runConfigurations/k64f.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="k64f" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nxp" PROGRAM_PARAMS="-device &quot;MK64FN1M0xxx12&quot; -if swd -speed 10000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/kl25.xml b/.idea/runConfigurations/kl25.xml
new file mode 100644
index 000000000..bb7e1707b
--- /dev/null
+++ b/.idea/runConfigurations/kl25.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nxp" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc1857.xml b/.idea/runConfigurations/lpc1857.xml
new file mode 100644
index 000000000..ef8178e08
--- /dev/null
+++ b/.idea/runConfigurations/lpc1857.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="lpc1857" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nxp" PROGRAM_PARAMS="-device &quot;lpc1857&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="device_info" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="device_info">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc4088.xml b/.idea/runConfigurations/lpc4088.xml
new file mode 100644
index 000000000..6c6886f30
--- /dev/null
+++ b/.idea/runConfigurations/lpc4088.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="lpc4088" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nxp" PROGRAM_PARAMS="-device &quot;lpc4088&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc54628.xml b/.idea/runConfigurations/lpc54628.xml
new file mode 100644
index 000000000..4b871d543
--- /dev/null
+++ b/.idea/runConfigurations/lpc54628.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="lpc54628" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nxp" PROGRAM_PARAMS="-device &quot;LPC54628J512&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc55s69.xml b/.idea/runConfigurations/lpc55s69.xml
new file mode 100644
index 000000000..7ab9fac66
--- /dev/null
+++ b/.idea/runConfigurations/lpc55s69.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="lpc55s69" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nxp" PROGRAM_PARAMS="-device &quot;lpc55s69&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/mcx947.xml b/.idea/runConfigurations/mcx947.xml
new file mode 100644
index 000000000..2a9805145
--- /dev/null
+++ b/.idea/runConfigurations/mcx947.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nxp" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/nrf52840.xml b/.idea/runConfigurations/nrf52840.xml
new file mode 100644
index 000000000..5a4f4837b
--- /dev/null
+++ b/.idea/runConfigurations/nrf52840.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="nrf52840" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nrf" PROGRAM_PARAMS="-select usb=752001685 -device &quot;nrf52840_xxaa&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/nrf5340.xml b/.idea/runConfigurations/nrf5340.xml
new file mode 100644
index 000000000..bf1cb2938
--- /dev/null
+++ b/.idea/runConfigurations/nrf5340.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="nrf5340" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nrf" PROGRAM_PARAMS="-select usb=752001685 -device &quot;nrf5340_xxaa_app&quot; -if swd -speed 16000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra2a1.xml b/.idea/runConfigurations/ra2a1.xml
new file mode 100644
index 000000000..d50b3d729
--- /dev/null
+++ b/.idea/runConfigurations/ra2a1.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra2a1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="renesas" PROGRAM_PARAMS="-device &quot;R7FA2A1AB&quot; -if swd -speed 20000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml
new file mode 100644
index 000000000..0cccb60d2
--- /dev/null
+++ b/.idea/runConfigurations/ra4m1.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="renesas" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml
new file mode 100644
index 000000000..5efd47753
--- /dev/null
+++ b/.idea/runConfigurations/ra6m1.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="renesas" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
new file mode 100644
index 000000000..713fc68cc
--- /dev/null
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="renesas" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rp2040.xml b/.idea/runConfigurations/rp2040.xml
new file mode 100644
index 000000000..da5a8f1ee
--- /dev/null
+++ b/.idea/runConfigurations/rp2040.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rp2040" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
+      <debugger kind="GDB" isBundled="true" />
+    </openocd>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
new file mode 100644
index 000000000..c3582512c
--- /dev/null
+++ b/.idea/runConfigurations/rt1010.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nxp" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/imxrt/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1060.xml b/.idea/runConfigurations/rt1060.xml
new file mode 100644
index 000000000..649fe6dac
--- /dev/null
+++ b/.idea/runConfigurations/rt1060.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt1060" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="nxp" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="device_info" TARGET_NAME="device_info" version="1" RUN_TARGET_PROJECT_NAME="device_info" RUN_TARGET_NAME="device_info">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/samd21g18.xml b/.idea/runConfigurations/samd21g18.xml
new file mode 100644
index 000000000..2ea822493
--- /dev/null
+++ b/.idea/runConfigurations/samd21g18.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="samd21g18" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="microchip" PROGRAM_PARAMS="-device &quot;ATSAMD21G18&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/samd51j19.xml b/.idea/runConfigurations/samd51j19.xml
new file mode 100644
index 000000000..b6cbe253a
--- /dev/null
+++ b/.idea/runConfigurations/samd51j19.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="samd51j19" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="microchip" PROGRAM_PARAMS="-device &quot;ATSAMD51J19A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml
new file mode 100644
index 000000000..e84445add
--- /dev/null
+++ b/.idea/runConfigurations/stlink.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-p 49578 -cp &quot;$USER_HOME$/st/stm32cubeide_1.16.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.1.400.202404281720/tools/bin&quot; --frequency 8000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="raspberry_pi_pico" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::49578" executable="$USER_HOME$/st/stm32cubeide_1.16.1/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.linux64_2.1.400.202404281720/tools/bin/ST-LINK_gdbserver" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stm32g474.xml b/.idea/runConfigurations/stm32g474.xml
new file mode 100644
index 000000000..600b1e555
--- /dev/null
+++ b/.idea/runConfigurations/stm32g474.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="stm32" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stm32h563.xml b/.idea/runConfigurations/stm32h563.xml
new file mode 100644
index 000000000..9c0ffc2ec
--- /dev/null
+++ b/.idea/runConfigurations/stm32h563.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="stm32h563" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="stm32" PROGRAM_PARAMS="-device &quot;stm32h563zi&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stm32h743.xml b/.idea/runConfigurations/stm32h743.xml
new file mode 100644
index 000000000..1565e92cd
--- /dev/null
+++ b/.idea/runConfigurations/stm32h743.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="stm32h743" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="stm32" PROGRAM_PARAMS="-device &quot;stm32h743xi&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc_hid" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc_hid">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stm32u5a5.xml b/.idea/runConfigurations/stm32u5a5.xml
new file mode 100644
index 000000000..92a1293be
--- /dev/null
+++ b/.idea/runConfigurations/stm32u5a5.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="stm32u5a5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="stm32" PROGRAM_PARAMS="-device &quot;stm32u5a5zj&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/uno_r4.xml b/.idea/runConfigurations/uno_r4.xml
new file mode 100644
index 000000000..c69e2939c
--- /dev/null
+++ b/.idea/runConfigurations/uno_r4.xml
@@ -0,0 +1,11 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="uno_r4" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="renesas" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 20000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD" connection-mode="REMOTE" gdbserver-enable="false" console-enabled="false" console-port="0">
+      <debugger kind="GDB" isBundled="true" />
+      <extra-debugger-params debugger-working-dir="" debugger-env-pass-parent="true" custom-script="" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/vcs.xml b/.idea/vcs.xml
new file mode 100644
index 000000000..94a25f7f4
--- /dev/null
+++ b/.idea/vcs.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="VcsDirectoryMappings">
+    <mapping directory="$PROJECT_DIR$" vcs="Git" />
+  </component>
+</project>
\ No newline at end of file
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
new file mode 100644
index 000000000..9cd4a5ed1
--- /dev/null
+++ b/.pre-commit-config.yaml
@@ -0,0 +1,59 @@
+# SPDX-FileCopyrightText: 2020 Diego Elio PettenÃ˛
+#
+# SPDX-License-Identifier: Unlicense
+
+repos:
+- repo: https://github.com/pre-commit/pre-commit-hooks
+  rev: v4.4.0
+  hooks:
+  - id: check-yaml
+  - id: trailing-whitespace
+    exclude: |
+      (?x)^(
+        hw/bsp/mcx/sdk/
+      )
+  - id: end-of-file-fixer
+    exclude: |
+      (?x)^(
+        .idea/|
+        hw/bsp/mcx/sdk/|
+        docs/contributing/code_of_conduct.rst|
+        docs/info/contributors.rst
+      )
+  - id: forbid-submodules
+
+- repo: https://github.com/codespell-project/codespell
+  rev: v2.2.4
+  hooks:
+  - id: codespell
+    args: [-w]
+    exclude: |
+      (?x)^(
+        lib/|
+        hw/bsp/mcx/sdk/
+      )
+
+- repo: local
+  hooks:
+  - id: unit-test
+    name: unit-test
+    files: ^(src/|test/unit-test/)
+    entry: sh -c "cd test/unit-test && ceedling test:all"
+    pass_filenames: false
+    types_or: [c, header]
+    language: system
+
+#  - id: build-fuzzer
+#    name: build-fuzzer
+#    files: ^(src/|test/fuzz/)
+#    language: system
+#    types_or: [c, header]
+#    entry: |
+#      bash -c 'export CC=clang
+#      export CXX=clang++
+#      fuzz_harness=$(ls -d test/fuzz/device/*/)
+#      for h in $fuzz_harness
+#      do
+#        make -C $h get-deps
+#        make -C $h all
+#      done'
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index e83cd90fd..e26b1f475 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -4,15 +4,21 @@
 
 version: 2
 
+# Set the version of Python and other tools you might need
+build:
+  os: ubuntu-22.04
+  tools:
+    python: "3.11"
+
+# Build documentation in the docs/ directory with Sphinx
 sphinx:
    configuration: docs/conf.py
 
+# Optionally declare the Python requirements required to build your docs
 python:
-  version: 3.8
   install:
     - requirements: docs/requirements.txt
 
 submodules:
   include: []
   recursive: false
-    
\ No newline at end of file
diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 5726169f8..085f8082a 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -119,6 +119,7 @@ Notable contributors
 
 -  Port DCD Synopsys to support Silabs EFM32GG12 with SLTB009A board
 -  Rewrite documentation in rst and setup for readthedocs
+-  Generalize Renesas driver and support RA family with EK-RA4M3 board
 
 
 `Raspberry Pi Team <https://github.com/raspberrypi>`__
@@ -199,6 +200,8 @@ Notable contributors
 -  Add new DCD port for Microchip SAMx7x
 -  Add IAR compiler support
 -  Improve UAC2, CDC, DFU class driver
+-  Improve stm32_fsdev, chipidea_ci_hs, lpc_ip3511 DCD
+-  Host IAR Build CI & hardware in the loop (HITL) test
 
 
 `Full contributors list <https://github.com/hathach/tinyusb/contributors>`__
diff --git a/README.rst b/README.rst
index 05963a655..e4ad91e47 100644
--- a/README.rst
+++ b/README.rst
@@ -1,14 +1,24 @@
+|Build Status| |CircleCI Status| |Documentation Status| |Fuzzing Status| |License|
+
+Sponsors
+========
+
+TinyUSB is funded by: Adafruit. Purchasing products from them helps to support this project.
+
+.. figure:: docs/assets/adafruit_logo.svg
+   :alt: Adafruit Logo
+   :target: https://www.adafruit.com
+
+TinyUSB Project
+===============
+
 .. figure:: docs/assets/logo.svg
    :alt: TinyUSB
 
-|Build Status| |Documentation Status| |License|
-
 TinyUSB is an open-source cross-platform USB Host/Device stack for
 embedded system, designed to be memory-safe with no dynamic allocation
 and thread-safe with all interrupt events are deferred then handled in
-the non-ISR task function.
-
-Please take a look at the online `documentation <https://docs.tinyusb.org/>`__.
+the non-ISR task function. Check out the online `documentation <https://docs.tinyusb.org/>`__ for more details.
 
 .. figure:: docs/assets/stack.svg
    :width: 500px
@@ -16,46 +26,30 @@ Please take a look at the online `documentation <https://docs.tinyusb.org/>`__.
 
 ::
 
-	.
-	├── docs            # Documentation
-	├── examples        # Sample with Makefile build support
-	├── hw
-	│   ├── bsp         # Supported boards source files
-	│   └── mcu         # Low level mcu core & peripheral drivers
-	├── lib             # Sources from 3rd party such as freeRTOS, fatfs ...
-	├── src             # All sources files for TinyUSB stack itself.
-	├── test            # Unit tests for the stack
-	└── tools           # Files used internally
+    .
+    ├── docs            # Documentation
+    ├── examples        # Examples with make and cmake build system
+    ├── hw
+    │   ├── bsp         # Supported boards source files
+    │   └── mcu         # Low level mcu core & peripheral drivers
+    ├── lib             # Sources from 3rd party such as freeRTOS, fatfs ...
+    ├── src             # All sources files for TinyUSB stack itself.
+    ├── test            # Tests: unit test, fuzzing, hardware test
+    └── tools           # Files used internally
 
-Supported MCUs
-==============
 
-The stack supports the following MCUs:
+Getting started
+===============
 
-- **Allwinner:** F1C100s/F1C200s
-- **Broadcom:** BCM2837, BCM2711
-- **Dialog:** DA1469x
-- **Espressif:** ESP32-S2, ESP32-S3
-- **GigaDevice:** GD32VF103
-- **Infineon:** XMC4500
-- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x
-- **NordicSemi:** nRF52833, nRF52840, nRF5340
-- **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
-- **NXP:**
+See the `online documentation <https://docs.tinyusb.org>`_ for information about using TinyUSB and how it is implemented.
 
-  - iMX RT Series: RT10xx, RT11xx
-  - Kinetis: KL25, K32L2
-  - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
+Check out `Getting Started`_ guide for adding TinyUSB to your project or building the examples. If you are new to TinyUSB, we recommend starting with the `cdc_msc` example. There is a handful of `Supported Boards`_ that should work out of the box.
 
-- **Raspberry Pi:** RP2040
-- **Renesas:** RX63N, RX65N, RX72N
-- **Silabs:** EFM32GG
-- **Sony:** CXD56
-- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G4, L0, L1, L4, L4+, WB
-- **TI:** MSP430, MSP432E4, TM4C123
-- **ValentyUSB:** eptri
+We use `GitHub Discussions <https://github.com/hathach/tinyusb/discussions>`_ as our forum. It is a great place to ask questions and advice from the community or to discuss your TinyUSB-based projects.
 
-Here is the list of `Supported Devices`_ that can be used with provided examples.
+For bugs and feature requests, please `raise an issue <https://github.com/hathach/tinyusb/issues>`_ and follow the templates there.
+
+See `Porting`_ guide for adding support for new MCUs and boards.
 
 Device Stack
 ============
@@ -82,8 +76,19 @@ Host Stack
 
 - Human Interface Device (HID): Keyboard, Mouse, Generic
 - Mass Storage Class (MSC)
+- Communication Device Class: CDC-ACM
+- Vendor serial over USB: FTDI, CP210x, CH34x
 - Hub with multiple-level support
 
+Similar to the Device Stack, if you have a special requirement, `usbh_app_driver_get_cb()` can be used to write your own class driver without modifying the stack.
+
+Power Delivery Stack
+====================
+
+- Power Delivery 3.0 (PD3.0) with USB Type-C support (WIP)
+- Super early stage, only for testing purpose
+- Only support STM32 G4
+
 OS Abstraction layer
 ====================
 
@@ -94,53 +99,167 @@ TinyUSB is completely thread-safe by pushing all Interrupt Service Request (ISR)
 - `RT-Thread <https://github.com/RT-Thread/rt-thread>`_: `repo <https://github.com/RT-Thread-packages/tinyusb>`_
 - **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its `own repo <https://github.com/hathach/mynewt-tinyusb-example>`_
 
-Docs
-====
+Supported CPUs
+==============
 
-- Info
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Manufacturer | Family                      | Device | Host | Highspeed | Driver                 | Note              |
++==============+=============================+========+======+===========+========================+===================+
+| Allwinner    | F1C100s/F1C200s             | ✔      |      | ✔         | sunxi                  | musb variant      |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Analog       | MAX3421E                    |        | ✔    | ✖         | max3421                | via SPI           |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | MAX32 650, 666, 690,        | ✔      |      | ✔         | musb                   | 1-dir ep          |
+|              | MAX78002                    |        |      |           |                        |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Brigetek     | FT90x                       | ✔      |      | ✔         | ft9xx                  | 1-dir ep          |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Broadcom     | BCM2711, BCM2837            | ✔      |      | ✔         | dwc2                   |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Dialog       | DA1469x                     | ✔      | ✖    | ✖         | da146xx                |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Espressif    | S2, S3                      | ✔      | ✔    | ✖         | dwc2 or esp32sx        |                   |
+|   ESP32      +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | P4                          | ✔      | ✔    | ✔         | dwc2                   |                   |
++--------------+----+------------------------+--------+------+-----------+------------------------+-------------------+
+| GigaDevice   | GD32VF103                   | ✔      |      | ✖         | dwc2                   |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Infineon     | XMC4500                     | ✔      | ✔    | ✖         | dwc2                   |                   |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| MicroChip    | SAM | D11, D21, L21, L22    | ✔      |      | ✖         | samd                   |                   |
+|              |     +-----------------------+--------+------+-----------+------------------------+-------------------+
+|              |     | D51, E5x              | ✔      |      | ✖         | samd                   |                   |
+|              |     +-----------------------+--------+------+-----------+------------------------+-------------------+
+|              |     | G55                   | ✔      |      | ✖         | samg                   | 1-dir ep          |
+|              |     +-----------------------+--------+------+-----------+------------------------+-------------------+
+|              |     | E70,S70,V70,V71       | ✔      |      | ✔         | samx7x                 | 1-dir ep          |
+|              +-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+|              | PIC | 24                    | ✔      |      |           | pic                    | ci_fs variant     |
+|              |     +-----------------------+--------+------+-----------+------------------------+-------------------+
+|              |     | 32 mm, mk, mx         | ✔      |      |           | pic                    | ci_fs variant     |
+|              |     +-----------------------+--------+------+-----------+------------------------+-------------------+
+|              |     | dsPIC33               | ✔      |      |           | pic                    | ci_fs variant     |
+|              |     +-----------------------+--------+------+-----------+------------------------+-------------------+
+|              |     | 32mz                  | ✔      |      |           | pic32mz                | musb variant      |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| Mind Montion | mm32                        | ✔      |      | ✖         | mm32f327x_otg          | ci_fs variant     |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| NordicSemi   | nRF 52833, 52840, 5340      | ✔      | ✖    | ✖         | nrf5x                  | only ep8 is ISO   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Nuvoton      | NUC120                      | ✔      | ✖    | ✖         | nuc120                 |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | NUC121/NUC125               | ✔      | ✖    | ✖         | nuc121                 |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | NUC126                      | ✔      | ✖    | ✖         | nuc121                 |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | NUC505                      | ✔      |      | ✔         | nuc505                 |                   |
++--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+
+| NXP          | iMXRT   | RT 10xx, 11xx     | ✔      | ✔    | ✔         | ci_hs                  |                   |
+|              +---------+-------------------+--------+------+-----------+------------------------+-------------------+
+|              | Kinetis | KL                | ✔      | ⚠    | ✖         | ci_fs, khci            |                   |
+|              |         +-------------------+--------+------+-----------+------------------------+-------------------+
+|              |         | K32L2             | ✔      |      | ✖         | khci                   | ci_fs variant     |
+|              +---------+-------------------+--------+------+-----------+------------------------+-------------------+
+|              | LPC     | 11u, 13, 15       | ✔      | ✖    | ✖         | lpc_ip3511             |                   |
+|              |         +-------------------+--------+------+-----------+------------------------+-------------------+
+|              |         | 17, 40            | ✔      | ⚠    | ✖         | lpc17_40               |                   |
+|              |         +-------------------+--------+------+-----------+------------------------+-------------------+
+|              |         | 18, 43            | ✔      | ✔    | ✔         | ci_hs                  |                   |
+|              |         +-------------------+--------+------+-----------+------------------------+-------------------+
+|              |         | 51u               | ✔      | ✖    | ✖         | lpc_ip3511             |                   |
+|              |         +-------------------+--------+------+-----------+------------------------+-------------------+
+|              |         | 54, 55            | ✔      |      | ✔         | lpc_ip3511             |                   |
+|              +---------+-------------------+--------+------+-----------+------------------------+-------------------+
+|              | MCX     | N9, A15           | ✔      |      | ✔         | ci_fs, ci_hs           |                   |
++--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+
+| Raspberry Pi | RP2040, RP2350              | ✔      | ✔    | ✖         | rp2040, pio_usb        |                   |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| Renesas      | RX  | 63N, 65N, 72N         | ✔      | ✔    | ✖         | rusb2                  |                   |
+|              +-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+|              | RA  | 4M1, 4M3, 6M1         | ✔      | ✔    | ✖         | rusb2                  |                   |
+|              |     +-----------------------+--------+------+-----------+------------------------+-------------------+
+|              |     | 6M5                   | ✔      | ✔    | ✔         | rusb2                  |                   |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| Silabs       | EFM32GG12                   | ✔      |      | ✖         | dwc2                   |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Sony         | CXD56                       | ✔      | ✖    | ✔         | cxd56                  |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| ST STM32     | F0                          | ✔      | ✖    | ✖         | stm32_fsdev            |                   |
+|              +----+------------------------+--------+------+-----------+------------------------+-------------------+
+|              | F1 | 102, 103               | ✔      | ✖    | ✖         | stm32_fsdev            |                   |
+|              |    +------------------------+--------+------+-----------+------------------------+-------------------+
+|              |    | 105, 107               | ✔      | ✔    | ✖         | dwc2                   |                   |
+|              +----+------------------------+--------+------+-----------+------------------------+-------------------+
+|              | F2, F4, F7, H7              | ✔      | ✔    | ✔         | dwc2                   |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | F3                          | ✔      | ✖    | ✖         | stm32_fsdev            |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | C0, G0, H5                  | ✔      |      | ✖         | stm32_fsdev            |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | G4                          | ✔      | ✖    | ✖         | stm32_fsdev            |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | L0, L1                      | ✔      | ✖    | ✖         | stm32_fsdev            |                   |
+|              +----+------------------------+--------+------+-----------+------------------------+-------------------+
+|              | L4 | 4x2, 4x3               | ✔      | ✖    | ✖         | stm32_fsdev            |                   |
+|              |    +------------------------+--------+------+-----------+------------------------+-------------------+
+|              |    | 4x5, 4x6               | ✔      | ✔    | ✖         | dwc2                   |                   |
+|              +----+------------------------+--------+------+-----------+------------------------+-------------------+
+|              | L4+                         | ✔      | ✔    | ✖         | dwc2                   |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | L5                          | ✔      | ✖    | ✖         | stm32_fsdev            |                   |
+|              +----+------------------------+--------+------+-----------+------------------------+-------------------+
+|              | U5 | 535, 545               | ✔      |      | ✖         | stm32_fsdev            |                   |
+|              |    +------------------------+--------+------+-----------+------------------------+-------------------+
+|              |    | 575, 585               | ✔      | ✔    | ✖         | dwc2                   |                   |
+|              |    +------------------------+--------+------+-----------+------------------------+-------------------+
+|              |    | 59x,5Ax,5Fx,5Gx        | ✔      | ✔    | ✔         | dwc2                   |                   |
+|              +----+------------------------+--------+------+-----------+------------------------+-------------------+
+|              | WBx5                        | ✔      | ✖    | ✖         | stm32_fsdev            |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| TI           | MSP430                      | ✔      | ✖    | ✖         | msp430x5xx             |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | MSP432E4                    | ✔      |      | ✖         | musb                   |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | TM4C123                     | ✔      |      | ✖         | musb                   |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| ValentyUSB   | eptri                       | ✔      | ✖    | ✖         | eptri                  |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| WCH          | CH32F20x                    | ✔      |      | ✔         | ch32_usbhs             |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | CH32V20x                    | ✔      |      | ✖         | stm32_fsdev/ch32_usbfs |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | CH32V307                    | ✔      |      | ✔         | ch32_usbfs/hs          |                   |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
 
-  - `Uses`_
-  - `Changelog`_
-  - `Contributors`_
+Table Legend
+------------
 
-- `Reference`_
-
-  - `Supported Devices`_
-  - `Getting Started`_
-  - `Concurrency`_
-
-- `Contributing`_
-
-  - `Code of Conduct`_
-  - `Structure`_
-  - `Porting`_
-
-License
-=======
-
-All TinyUSB sources in the ``src`` folder are licensed under MIT
-license, the `Full license is here <LICENSE>`__. However, each file can be
-individually licensed especially those in ``lib`` and ``hw/mcu`` folder.
-Please make sure you understand all the license term for files you use
-in your project.
+========= =========================
+✔         Supported
+⚠         Partial support
+✖         Not supported by hardware
+\[empty\] Unknown
+========= =========================
 
 
-.. |Build Status| image:: https://github.com/hathach/tinyusb/workflows/Build/badge.svg
+.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/build.yml/badge.svg
    :target: https://github.com/hathach/tinyusb/actions
+.. |CircleCI Status| image:: https://dl.circleci.com/status-badge/img/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master.svg?style=svg
+   :target: https://dl.circleci.com/status-badge/redirect/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master
 .. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest
    :target: https://docs.tinyusb.org/en/latest/?badge=latest
+.. |Fuzzing Status| image:: https://oss-fuzz-build-logs.storage.googleapis.com/badges/tinyusb.svg
+   :target: https://oss-fuzz-build-logs.storage.googleapis.com/index.html#tinyusb
 .. |License| image:: https://img.shields.io/badge/license-MIT-brightgreen.svg
    :target: https://opensource.org/licenses/MIT
 
 
-.. _Uses: docs/info/uses.rst
 .. _Changelog: docs/info/changelog.rst
 .. _Contributors: CONTRIBUTORS.rst
-.. _Reference: docs/reference/index.rst
-.. _Supported Devices: docs/reference/supported.rst
 .. _Getting Started: docs/reference/getting_started.rst
+.. _Supported Boards: docs/reference/boards.rst
+.. _Dependencies: docs/reference/dependencies.rst
 .. _Concurrency: docs/reference/concurrency.rst
 .. _Contributing: docs/contributing/index.rst
 .. _Code of Conduct: CODE_OF_CONDUCT.rst
-.. _Structure: docs/contributing/structure.rst
 .. _Porting: docs/contributing/porting.rst
diff --git a/SConscript b/SConscript
new file mode 100644
index 000000000..b5043f437
--- /dev/null
+++ b/SConscript
@@ -0,0 +1,11 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+
+objs = objs + SConscript(cwd + '/lib/rt-thread/SConscript')
+
+Return('objs')
diff --git a/docs/assets/adafruit_logo.svg b/docs/assets/adafruit_logo.svg
new file mode 100644
index 000000000..cafd5a10e
--- /dev/null
+++ b/docs/assets/adafruit_logo.svg
@@ -0,0 +1,21 @@
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+<style type="text/css">
+	.st0{fill:#0;}
+</style>
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diff --git a/docs/conf.py b/docs/conf.py
old mode 100644
new mode 100755
index 878b29645..4249d41f7
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -1,16 +1,20 @@
+#!/usr/bin/env python3
 # Configuration file for the Sphinx documentation builder.
 #
 # This file only contains a selection of the most common options. For a full
 # list see the documentation:
 # https://www.sphinx-doc.org/en/master/usage/configuration.html
 
+import re
+from pathlib import Path
+
 # -- Path setup --------------------------------------------------------------
 
 
 # -- Project information -----------------------------------------------------
 
 project = 'TinyUSB'
-copyright = '2021, Ha Thach'
+copyright = '2024, Ha Thach'
 author = 'Ha Thach'
 
 
@@ -39,3 +43,16 @@ html_theme_options = {
 }
 
 todo_include_todos = True
+
+# pre-process path in README.rst
+def preprocess_readme():
+    """Modify figure paths in README.rst for Sphinx builds."""
+    src = Path(__file__).parent.parent / "README.rst"
+    tgt = Path(__file__).parent.parent / "README_processed.rst"
+    if src.exists():
+        content = src.read_text()
+        content = re.sub(r"docs/", r"", content)
+        content = re.sub(r".rst", r".html", content)
+        tgt.write_text(content)
+
+preprocess_readme()
diff --git a/docs/contributing/code_of_conduct.rst b/docs/contributing/code_of_conduct.rst
index b52bf14c5..fb1859c75 120000
--- a/docs/contributing/code_of_conduct.rst
+++ b/docs/contributing/code_of_conduct.rst
@@ -1 +1 @@
-../../CODE_OF_CONDUCT.rst
\ No newline at end of file
+.. include:: ../../CODE_OF_CONDUCT.rst
\ No newline at end of file
diff --git a/docs/contributing/index.rst b/docs/contributing/index.rst
index c572894ad..78933a3ca 100644
--- a/docs/contributing/index.rst
+++ b/docs/contributing/index.rst
@@ -6,7 +6,7 @@ Contributing can be highly rewarding, but it can also be frustrating at times.
 It takes time to review patches, and as this is an open source project, that
 sometimes can take a while. The reviewing process depends on the availability
 of the maintainers, who may not be always available. Please try to be
-understanding throught the process.
+understanding through the process.
 
 There a few guidelines you need to keep in mind when contributing. Please have
 a look at them as that will make the contribution process easier for all
@@ -19,5 +19,4 @@ Index
    :maxdepth: 2
 
    code_of_conduct
-   structure
    porting
diff --git a/docs/contributing/porting.rst b/docs/contributing/porting.rst
index 7e9e462f0..f81d98782 100644
--- a/docs/contributing/porting.rst
+++ b/docs/contributing/porting.rst
@@ -62,9 +62,9 @@ Feel free to skip this until you want to verify your demo code is running. To im
 OS Abstraction Layer (OSAL)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-The OS Abstraction Layer is responsible for providing basic data structures for TinyUSB that may allow for concurrency when used with an RTOS. Without an RTOS it simply handles concurrency issues between the main code and interrupts.
+The OS Abstraction Layer is responsible for providing basic data structures for TinyUSB that may allow for concurrency when used with an RTOS. Without an RTOS it simply handles concurrency issues between the main code and interrupts. The code is almost entirely agnostic of MCU and lives in ``src/osal``.
 
-The code is almost entirely agnostic of MCU and lives in ``src/osal``.
+In RTOS configurations, tud_task()/tuh_task() blocks behind a synchronization structure when the event queue is empty, so that the scheduler may give the CPU to a different task. To take advantage of the library's capability to yield the CPU when there are no actionable USB device events, ensure that the `CFG_TUSB_OS` symbol is defined, e.g `OPT_OS_FREERTOS` enables the FreeRTOS scheduler to schedule other threads than that which calls `tud_task()/tuh_task()`.
 
 Device API
 ^^^^^^^^^^
@@ -195,7 +195,7 @@ Others (like the nRF52) may need each USB packet queued individually. To make th
 some state for yourself and queue up an intermediate USB packet from the interrupt handler.
 
 Once the transaction is going, the interrupt handler will notify TinyUSB of transfer completion.
-During transmission, the IN data buffer is guarenteed to remain unchanged in memory until the ``dcd_xfer_complete`` function is called.
+During transmission, the IN data buffer is guaranteed to remain unchanged in memory until the ``dcd_xfer_complete`` function is called.
 
 The dcd_edpt_xfer function must never add zero-length-packets (ZLP) on its own to a transfer. If a ZLP is required,
 then it must be explicitly sent by the stack calling dcd_edpt_xfer(), by calling dcd_edpt_xfer() a second time with len=0.
@@ -238,4 +238,4 @@ Use `WireShark <https://www.wireshark.org/>`_ or `a Beagle <https://www.totalpha
 
 * If the host sends a SETUP packet and its not ACKed then your USB peripheral probably isn't started correctly.
 * If the peripheral is started correctly but it still didn't work, then verify your usb clock is correct. (You did output a PWM based on it right? ;-) )
-* If the SETUP packet is ACKed but nothing is sent back then you interrupt handler isn't queueing the setup packet correctly. (Also, if you are using your own code instead of an example ``tud_task`` may not be called.) If thats OK, the ``dcd_xfer_complete`` may not be setting up the next transaction correctly.
+* If the SETUP packet is ACKed but nothing is sent back then you interrupt handler isn't queueing the setup packet correctly. (Also, if you are using your own code instead of an example ``tud_task`` may not be called.) If that's OK, the ``dcd_xfer_complete`` may not be setting up the next transaction correctly.
diff --git a/docs/contributing/structure.rst b/docs/contributing/structure.rst
deleted file mode 100644
index e8c658850..000000000
--- a/docs/contributing/structure.rst
+++ /dev/null
@@ -1,59 +0,0 @@
-*********
-Structure
-*********
-
-Tree
-====
-
-::
-
-  .
-  ├── docs
-  ├── examples
-  ├── hw
-  │   ├── bsp
-  │   └── mcu
-  ├── lib
-  ├── src
-  ├── test
-  └── tools
-
-docs
-----
-
-Documentation
-
-examples
---------
-
-Sample with Makefile build support
-
-hw/bsp
-------
-
-Supported boards source files
-
-hw/mcu
-------
-
-Low level mcu core & peripheral drivers
-
-lib
----
-
-Sources from 3rd party such as freeRTOS, fatfs ...
-
-src
----
-
-All sources files for TinyUSB stack itself.
-
-test
-----
-
-Unit tests for the stack
-
-tools
------
-
-Files used internally
diff --git a/docs/index.rst b/docs/index.rst
index 2a032c51e..c1c8e4d99 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -1,12 +1,6 @@
 :hide-toc:
 
-*********
-TinyUSB
-*********
-
-TinyUSB is an open-source cross-platform USB Host/Device stack for embedded systems,
-designed to be memory-safe with no dynamic allocation and thread-safe with all interrupt events being deferred and then handled in the non-ISR task function.
-
+.. include:: ../README_processed.rst
 
 .. toctree::
    :caption: Index
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index da29e04fb..0a34c0842 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -2,6 +2,433 @@
 Changelog
 *********
 
+0.18.0
+======
+
+General
+-------
+
+- New MCUs:
+
+  - Add esp32p4 OTG highspeed support
+  - Add stm32 u0, c0, h7rs
+
+- Better support dcache, make sure all usb-transferred buffer are cache line aligned and occupy full cache line
+- Build ARM IAR with CircleCI
+- Improve HIL with dual/host_info_to_device_cdc optional for pico/pico2, enable dwc2 dma test
+
+API Changes
+-----------
+
+- Change signature of ``tusb_init(rhport, tusb_rhport_init_t*)``, tusb_init(void) is now deprecated but still available for backward compatibility
+- Add new ``tusb_int_handler(rhport, in_isr)``
+- Add time-related APIs: ``tusb_time_millis_api()`` and ``tusb_time_delay_ms_api()`` for non-RTOS, required for some ports/configuration
+- New configuration macros:
+
+  - ``CFG_TUD/TUH_MEM_DCACHE_ENABLE`` enable data cache sync for endpoint buffer
+  - ``CFG_TUD/TUH_MEM_DCACHE_LINE_SIZE`` set cache line size
+  - ``CFG_TUD/TUH_DWC2_SLAVE_ENABLE`` enable dwc2 slave mode
+  - ``CFG_TUD/TUH_DWC2_DMA_ENABLE`` enable dwc2 dma mode
+
+Controller Driver (DCD & HCD)
+-----------------------------
+
+- DWC2
+  - Add DMA support for both device and host controller
+  - Add host driver support including: full/high speed, control/bulk/interrupt (CBI) transfer, split CBI i.e FS/LS attached via highspeed hub, hub support
+
+- RP2: implement dcd_edpt_iso_alloc() and dcd_edpt_iso_activate() for isochronous endpoint
+- iMXRT1170 support M4 core
+
+Device Stack
+------------
+
+- Vendor Fix  class reset
+- NCM fix recursions in tud_network_recv_renew()
+- Audio fix align issue of _audiod_fct.alt_setting
+- UVC support format frame based
+- Change dcd_dcache_() return type from void to bool
+- HID add Usage Table for Physical Input Device Page (0x0F)
+
+Host Stack
+----------
+
+- Fix an duplicated attach issue which cause USBH Defer Attach until current enumeration complete message
+
+0.17.0
+======
+
+General
+-------
+
+- Improved CI: build both cmake and make. Make use of CircleCI for part of build process to speed up CI
+- Add CodeQL Workflow for Code Security Analysis
+- Add Clang compiler support
+- Add default implementation for weak callbacks functions for better Keil compatibility
+- Upgrade hardware-in-the-loop (HIL) testing with more boards and examples: including dual stack example
+
+Controller Driver (DCD & HCD)
+-----------------------------
+
+- Chipidea
+
+  - Support MCXA
+
+- DWC2
+
+  - Fix tickless issue with stm32f7: disable ULPI clock during sleep when using internal phy
+  - Fix SOF interrupt handling
+  - Fix fifo level half/empty issue
+  - Add DWC2 Test Mode support.
+  - for esp32 force disconnect/connect using USB_WRAP otg pad override
+
+- FSDEV
+
+  - Rewrite and Generalize driver to support non-stm32 mcu such as wch
+  - Simplify PMA, HW FIFO access and bit manipulation for different access scheme 1x16, 2x16 and 32 bit
+  - Add support for ch32 usbd e.g ch32v203
+  - Add support for STM32G4 and STM32U5 microcontrollers.
+  - Fix h5 (32-bit) errata 2.15.1: Buffer description table update completes after CTR interrupt triggers
+  - ISO EP buffer allocation improvements, implement dcd_edpt_close_all()
+
+  - Fix ch32v203 race condition and stability issue with
+
+    - fix ch32v203 seems to unconditionally accept ZLP on EP0 OUT.
+    - fix v203 race condition between rx bufsize and RX_STAT which cause PMAOVR, occurs with WRITE10
+    - correctly handle setup prepare at dcd_edpt0_status_complete(), which fixes the race condition with windows where we could miss setup packet (setup bit set, but count = 0)
+
+- MAX3421E
+
+  - Add support for rp2040, esp32 (c3, c6, h2, etc..)
+  - Add hcd_deinit() for max3421
+  - Retry NAK handling next frame to reduce CPU and SPI bus usage
+  - add cpuctl and pinctl to tuh_configure() option for max3421
+  - Implement hcd abort transfer for Max3421
+  - Properly Handle NAK Response in MAX3421E driver: correctly switch and skip writing to 2 FIFOs when NAK received. Otherwise, the driver may hang in certain conditions.
+
+- MSP430: support non-bus-powered
+
+- MUSB
+
+  - Add support for Analoog devices: max32650, max32666, max32690, max3278002
+
+- nRF
+
+  - Fix dcd_edpt_open for iso endpoint
+  - Handle ISOOUT CRC errors
+  - Add compile support with old nordic sdk
+  - Fix a few race conditions
+
+- OHCI
+
+  - Allow more than 16 devices
+
+- RP2040
+
+  - Correctly abort control transfer when new setup arrived. Due to RP2040-E2 only able to fix B2 or later
+  - Implement hcd abort transfer for rp2040
+  - Add support for rp2350
+
+- RUSB2
+
+  - Support ra2a1 pipe number scheme
+
+- WCH CH32
+
+  - Added support for USB OTG/FS and FSDev Driver. Update CH32V307 to allow manual select FS or HS driver.
+  - Fixed various bugs in CH32v307 usbhs driver: endpoint handling and data transfer management.
+
+Device Stack
+------------
+
+- Add tud_deinit() and class driver deinit() to deinitialize TinyUSB device stack.
+- Add support for generic SOF callback.
+- Add set address recovery time 2ms per USB spec.
+
+- Audio
+
+  - Add audio_test_freertos & audio_4_channel_mic_freertos
+  - Improved support for Audio Class 2.0 (UAC2) with various bug fixes.
+  - Add feedback by fifo counting.
+
+- Bluetooth HCI
+
+  - Issue ZLP on ACL IN ep when transfer is multiple of endpoint max packet size
+
+- CDC
+
+  - Add tud_cdc_configure_fifo() to make RX/TX buffer persistent (not clear when disconnected)
+  - Add missing capability bit for CDC ACM serial break support
+  - Enhanced CDC class with better handling of large data transmissions.
+  - Add missing capability bit for CDC ACM serial break support
+
+- HID
+
+  - Added missing key codes for keypad
+  - Added HID Lighting and Illumination functionality
+  - Fixed issues in the HID class for more reliable device enumeration.
+  - Support HID Mouse with absolute positioning
+  - Use separate buffer for control SET_REPORT, fix conflict with interrupt endpoint out
+
+- MSC: Added support for SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL
+
+- Net
+
+  - Rewrite of NCM device driver to improve throughput
+  - removed obsolete tud_network_link_state_cb()
+
+- USBTMC Added notification support
+
+- Vendor
+
+  - Migrate to new endpoint stream API, support non-buffered TX/RX
+  - Add ZLP for write() when needed
+
+- Video
+
+  - Enhance UVC descriptors and example
+  - Video Added support for USB Video Class (UVC) with MJPEG.
+  - Fix multiple interfaces, add an example of 2ch video capture.
+  - Fix race for tud_video_n_streaming check
+
+Host Stack
+----------
+
+- Added tuh_deinit() to de-initialize TinyUSB host stack.
+- Added support for new USB mass storage class APIs.
+- Improved error handling and retry mechanisms for unstable devices.
+
+- CDC Serial
+
+  - Add support for ch34x
+  - Allow to overwrite CFG_TUH_CDC_FTDI/CP210X/CH32X_VID_PID_LIST
+  - Enhanced stability of CDC-ACM devices during enumeration.
+
+- HID
+
+  - Add tuh_hid_receive_abort()
+  - Add tuh_hid_get_report()
+
+- Hub
+
+  - Prevent status request to invalid ep_num
+  - Fix double status xfer
+  - unroll hub removal
+
+0.16.0
+======
+
+- New controller driver: MAX3421e (usb host shield), rusb2 (Renesas USB2.0), ChipIdea fullspeed
+- New MCUs: MCXn9, nRF5340, STM32: G0, G4, L5, U575, U5A5, RA6m5, CH32F20x
+- Add initial TypeC PowerDelivery support with STM32G4
+- Remove submodules and use python script to manage repo dependencies #1947
+- Add CMake support for most families and boards, move build file from tools/ to examples/build_system
+- Add ETM trace support with JTrace for nrf52840, nrf5340, mcb1857, stm32h743eval, ra6m5
+- [osal] Make it possible to override the osal_task_delay() in osal_none
+- Add CDC+UAC2 composite device example
+- Enhance Hardware-in-the-loop (HIL) testing with more boards: rp2040, stm32l412nucleo, stm32f746disco, lpcxpresso43s67
+
+Controller Driver (DCD & HCD)
+-----------------------------
+
+- Add new ISO endpoint API: dcd_edpt_iso_alloc() and dcd_edpt_iso_activate()
+- Remove legacy driver st/synopsys
+
+- EHCI
+
+  - [iMXRT] Add dache clean/invalidate when memory is in cacheable memory
+  - Fix portsc write issue which cause problem with enumeration
+  - Fix an issue when doing port reset write to portsc
+  - Fix port change detect is not recognized when power on with attached device
+  - Fix xfer failed with disconnected device as stalled
+  - Fix error on EHCI causes xfer error in non-queued qhd which cause memory fault
+  - Un-roll recursive hub removal with usbh queue
+  - Fix issue when removing queue head
+  - Implement hcd_edpt_abort_xfer()
+  - use standard USB complete interrupt instead of custom chipidea async/period interrupt to be more compatible with other ehci implementation
+  - refactor usb complete & error isr processing, merge, update. Fix EHCI QHD reuses QTD on wrong endpoint
+  - Improve bus reset, fix send_setup() not carried out if halted previously
+  - Fix clear qhd halted bit if not caused by STALL protocol to allow for next transfer
+
+- ChipIdea Highspeed
+
+  - Fix control transfer issue when previous status and new setup complete in the same isr frame
+  - [imxrt] Add dcache support for cache region
+
+- ChipIdea Fullspeed
+
+  - Generalize ChipIdea Fullspeed driver for mcxn9 (port 0), kinetis
+
+- nrf
+
+  - Fix DMA race condition with ISO OUT transfer #1946
+  - Add support for nRF5340 with pca10095 board
+
+- Renesas rusb2
+
+  - Generalize rusb2 driver for ra, rx mcus
+  - rework both dcd and hcd for better multiple ports support
+  - Add support for board with HS USB port: ra6m5 port1
+
+- rp2040
+
+  - [dcd] Make writes to SIE_CTRL aware of concurrent access
+  - [hcd] add hcd_frame_number(), hcd_edpt_abort_xfer() for pio-usb host
+
+- stm32 fsdev:
+
+  - Add STM32L5 support
+  - Implement dcd_edpt_iso_alloc() and dcd_edpt_iso_activate()
+
+- OHCI
+
+  - Allows configurable root hub ports, handles SMM mode (Ref OHCI spec 5.1.1.3.3) and Bios mode (Ref OHCI spec 5.1.1.3.4)
+  - Fix FrameIntervalToggle must be toggled after we write the FrameInterval (Ref OHCI Spec 7.3.1)
+  - Wait PowerOnToPowerGoodTime after we enable power of the RH ports (Ref OHCI Spec 7.4.1)
+  - Generate port interrupts for devices already connected during init.
+  - Fix issue when removing queue head
+  - Disable MIE during IRQ processing and clear HccaDoneHead on completion as per OCHI Spec Page 80
+
+Device Stack
+------------
+
+- Add optional hooks tud_event_hook_cb()
+- Audio (UAC2)
+
+  - Fix feedback EP buffer alignment.
+  - Fix encoding, update example
+  - Improve IN transfer
+
+- Bluetooth
+
+  - Add historical EP compatibility for Bluetooth HCI
+
+- CDC
+
+  - Fix line_coding alignment
+  - Fix typo in cdc line coding enum
+
+- MIDI
+
+  - Fix stream_write() always writes system messages to cable 0
+  - Fix incorrect NOTE_ON, NOTE_OFF definitions
+
+- USBTMC: Fix tmc488 bit order
+
+- Vendor: fix read()/write() race condition
+
+- Video (UVC)
+
+  - Add the capability for video class to handle a bulk endpoint in the streaming interface.
+
+Host Stack
+----------
+
+- USBH
+
+  - Add new APIs: tuh_interface_set(), tuh_task_event_ready(), tuh_edpt_abort_xfer(), tuh_rhport_reset_bus(), tuh_rhport_is_active()
+  - Fix issue when device generate multiple attach/detach/attach when plugging in
+  - Prefer application callback over built-in driver on transfer complete event
+  - Correct hcd_edpt_clear_stall() API signature
+  - Separate bus reset delay and contact debouncing delay in enumeration
+  - Support usbh_app_driver_get_cb() for application drivers
+  - Fix usbh enumeration removal race condition
+  - Add optional hooks tuh_event_hook_cb()
+
+- CDC
+
+  - Breaking: change tuh_cdc_itf_get_info() to use tuh_itf_info_t instead of tuh_cdc_info_t
+  - Fix cdc host enumeration issue when device does not support line request
+  - Add support for vendor usb2uart serial: ftdi, cp210x, ch9102f
+  - Improve sync control API e.g  tuh_cdc_set_control_line_state(), tuh_cdc_set_line_coding()
+
+- HID
+
+  - Add new APIs tuh_hid_send_report(), tuh_hid_itf_get_info(), tuh_hid_receive_ready(), tuh_hid_send_ready(), tuh_hid_set_default_protocol()
+  - Change meaning of CFG_TUH_HID to total number of HID interfaces supported. Previously CFG_TUH_HID is max number of interfaces per device which is rather limited and consume more resources than needed.
+
+- HUB
+
+  - Fix handling of empty "status change" interrupt
+  - Fix issue with hub status_change is not aligned
+
+- MSC
+
+  - Fix bug in tuh_msc_ready()
+  - Fix host msc get maxlun not using aligned section memory
+
+0.15.0
+======
+
+- Add codespell to detect typo
+- Add support for fuzzing and bagde for oss-fuzz
+- [osal]
+
+  - Allow the use of non-static allocation for FreeRTOS
+  - Fix FreeRTOS wrong task switch in some cases
+
+- Fix tu_fifo memory overflown when repeatedly write to overwritable fifo (accumulated more than 2 depths)
+- Better support for IAR (ARM) with ci build check for stm32 mcus.
+- Fix Windows build for some mingw gnu make situations
+
+Controller Driver (DCD & HCD)
+-----------------------------
+
+- Add new port support (WIP) for WCH CH32V307 USB Highspeed
+- Add new port support (WIP) for PIC32MM/MX & PIC24
+
+- [nRF]
+
+  - Fix endpoint internal state when closed
+  - Fix reception of large ISO packets
+
+- [rp2040]
+
+  - [dcd] Implement workaround for Errata 15. This enable SOF when bulk-in endpoint is in use and reduce its bandwidth to only 80%
+  - [hcd] Fix shared irq slots filling up when hcd_init() is called multiple times
+  - [hcd] Support host bulk endpoint using hw "interrupt" endpoint. Note speed limit is 64KB/s
+
+- [samd][dcd] Add support for ISO endpoint
+- [dwc2][dcd] Add support for stm32u5xx
+- [esp32sx] Fix Isochronous transfers only transmitted on even frame
+- [lpc_ip3511][dcd] Add isochronous support and fix endpoint accidental write
+- [ft90x] Improve and enhance support for FT9xx MCU, tested with more examples
+
+Device Stack
+------------
+
+- [Video]
+
+  - Add support for MJPEG
+  - Fix probe on macOS
+
+- [MIDI]
+
+  - Support port name strings
+  - fix MS Header wTotalLength computation
+
+- [HID]
+
+  - Add FIDO descriptor template
+  - change length in tud_hid_report_complete_cb() from uint8 to uint16
+
+- [CDC]
+
+  - Fix autoflush for FIFO < MPS
+  - Fix tx fifo memory overflown when DTR is not set and tud_cdc_write() is called repeatedly with large enough data
+
+- [USBTMC] Fix packet size with highspeed
+
+Host Stack
+----------
+
+- Retry a few times with transfers in enumeration since device can be unstable when starting up
+- [MSC] Rework host masstorage API. Add new **host/msc_file_explorer** example
+- [CDC]
+
+  - Add support for host cdc
+  - Fix host cdc with device without IAD e.g Arduino Due
+
 0.14.0
 ======
 
@@ -9,7 +436,8 @@ Changelog
 - Add timeout to osal_queue_receive()
 - Add tud_task_ext(timeout, in_isr) as generic version of tud_task(). Same as tuh_task_ext(), tuh_task()
 - Enable more warnings -Wnull-dereference -Wuninitialized -Wunused -Wredundant-decls -Wconversion
-- Add new examples 
+- Add new examples
+
   - host/bare_api to demonstrate generic (app-level) enumeration and endpoint transfer
   - dual/host_hid_to_device_cdc to run both device and host stack concurrently, get HID report from host and print out to device CDC. This example only work with multiple-controller MCUs and rp2040 with the help of pio-usb as added controller.
 
@@ -17,30 +445,35 @@ Controller Driver (DCD & HCD)
 -----------------------------
 
 - Enhance rhports management to better support dual roles
+
   - CFG_TUD_ENABLED/CFG_TUH_ENABLED, CFG_TUD_MAX_SPEED/CFG_TUH_MAX_SPEED can be used to replace CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE
   - tud_init(rphort), tuh_init(rhport) can be used to init stack on specified roothub port (controller) instead of tusb_init(void)
-- Add dcd/hcd port specific defines TUP_ (stand for tinyusb port-specific)
+- Add dcd/hcd port specific defines `TUP_` (stand for tinyusb port-specific)
 - [dwc2]
+
   - Update to support stm32 h72x, h73x with only 1 otg controller
   - Fix overwrite with grstctl when disable endpoint
 - [EHCI] Fix an issue with EHCI driver
 - [msp430] Fix for possible bug in msp430-elf-gcc 9.3.0
-- [nrf5x] Fix DMA access race condition using atomic function 
+- [nrf5x] Fix DMA access race condition using atomic function
 - [pic32] Fix PIC32 santiy
 - [rp2040]
+
   - Add PICO-PIO-USB as controller (device/host) support for rp2040
   - Use shared IRQ handlers, so user can also hook the USB IRQ
   - Fix resumed signal not reported to device stack
-- [stm32fsdev] Add support for stm32wb55 
+- [stm32fsdev] Add support for stm32wb55
 
 Device Stack
 ------------
 
 - [Audio] Add support for feedback endpoint computation
+
   - New API tud_audio_feedback_params_cb(), tud_audio_feedback_interval_isr().
   - Supported computation method are: frequency with fixed/float or power of 2. Feedback with fifo count is not yet supported.
   - Fix nitfs (should be 3) in TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR
   - Fix typo in audiod_rx_done_cb()
+
 - [DFU] Fix coexistence with other interfaces BTH, RNDIS
 - [MSC] Fix inquiry response additional length field
 - [Venndor] Improve write performance
@@ -52,9 +485,11 @@ Host Stack
 - [HID] Open OUT endpoint if available
 - [Hub] hub clear port and device interrupts
 - [USBH] Major improvement
+
   - Rework usbh control transfer with complete callback. New API tuh_control_xfer() though still only carry 1 usbh (no queueing) at a time.
   - Add generic endpoint transfer with tuh_edpt_open(), tuh_edpt_xfer(). Require `CFG_TUH_API_EDPT_XFER=1`
   - Support app-level enumeration with new APIs
+
     - tuh_descriptor_get(), tuh_descriptor_get_device(), tuh_descriptor_get_configuration(), tuh_descriptor_get_hid_report()
     - tuh_descriptor_get_string(), tuh_descriptor_get_manufacturer_string(), tuh_descriptor_get_product_string(), tuh_descriptor_get_serial_string()
     - Also add _sync() as sync/blocking version for above APIs
@@ -78,14 +513,14 @@ Controller Driver (DCD & HCD)
 - [MUSB] Add new DCD and HCD for Mentor musb with TI MSP432E4
 - [F1C100s] Add new DCD for Allwinner F1C100s family
 - [PIC32MZ] Add new DCD for PIC32MZ
-- [nRF] Fix/Enhance varous race condtion with: EASY DMA, request HFXO, EPOUT
-- [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed, 
+- [nRF] Fix/Enhance various race condition with: EASY DMA, request HFXO, EPOUT
+- [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed,
 - [RP2040] various update/fix for hcd/dcd
 - [FT9XX] new DCD port for Bridgetek FT90x and FT93x devices
 - [DA1469X] Fix resume
 - [OHCI] Fix device array out of bound
 
-Note: legacy drivers such as st/synopsys, nxp/transdimension are still present in this release but won't recieve more update and could be removed in the future.
+Note: legacy drivers such as st/synopsys, nxp/transdimension are still present in this release but won't receive more update and could be removed in the future.
 
 Device Stack
 ------------
@@ -166,7 +601,7 @@ RP2040
 ^^^^^^
 
 - Add RP2040 suspend & resume support
-- Implement double buffer for both host and device (#891). Howver device EPOUT is still single bufferred due to techinical issue with short packet 
+- Implement double buffer for both host and device (#891). However device EPOUT is still single buffered due to techinical issue with short packet
 
 Device Stack
 ------------
@@ -175,7 +610,7 @@ USBD
 ^^^^
 
 - Better support big endian mcu
-- Add tuh_inited() and tud_inited(), will separte tusb_init/inited() to tud/tuh init/inited
+- Add tuh_inited() and tud_inited(), will separate tusb_init/inited() to tud/tuh init/inited
 - Add dcd_attr.h for defining common controller attribute such as max endpoints
 
 Bluetooth
@@ -187,7 +622,7 @@ DFU
 ^^^
 
 - Enhance DFU implementation to support multiple alternate interface and better support bwPollTimeout
-- Rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU 
+- Rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU
 
 HID
 ^^^
@@ -207,7 +642,7 @@ UAC2
 ^^^^
 
 - Fix bug and enhance of UAC2
- 
+
 Vendor
 ^^^^^^
 
@@ -220,8 +655,8 @@ Host Controller Driver (HCD)
 RP2040
 ^^^^^^
 
-- Implement double bufferred to fix E4 errata and boost performance
-- Lots of rp2040 update and enhancment
+- Implement double buffered to fix E4 errata and boost performance
+- Lots of rp2040 update and enhancement
 
 Host Stack
 ----------
@@ -229,7 +664,7 @@ Host Stack
 - Major update and rework most of host stack, still needs more improvement
 - Lots of improvement and update in parsing configuration and control
 - Rework and major update to HID driver. Will default to enable boot interface if available
-- Sepearate CFG_TUH_DEVICE_MAX and CFG_TUH_HUB for better management and reduce SRAM usage
+- Separate CFG_TUH_DEVICE_MAX and CFG_TUH_HUB for better management and reduce SRAM usage
 
 0.10.1 (2021-06-03)
 ===================
@@ -306,12 +741,12 @@ MIDI
 Host Controller Driver (HCD)
 ----------------------------
 
-- No noticable changes
+- No noticeable changes
 
 USB Host Driver (USBH)
 ----------------------
 
-- No noticable changes
+- No noticeable changes
 
 Host Class Driver
 -----------------
@@ -384,7 +819,7 @@ HID
 MIDI
 
 - Fix dropping MIDI sysex message when fifo is full
-- Fix typo in tud_midi_write24(), make example less ambigous for cable and channel
+- Fix typo in tud_midi_write24(), make example less ambiguous for cable and channel
 - Fix incorrect endpoint descriptor length, MIDI v1 use Audio v1 which has 9-byte endpoint descriptor (instead of 7)
 
 Host Stack
@@ -399,7 +834,7 @@ Host Controller Driver (HCD)
   - Move echi/ohci files to portable/
   - Rename hcd_lpc18_43 to hcd_transdimension
   - Sub hcd API with hcd_ehci_init(), hcd_ehci_register_addr()
-  
+
 - Update NXP transdimention hcd_init() to reset controller to host mode
 
   - Ported hcd to rt10xx
@@ -449,13 +884,13 @@ Device Controller Driver
 
 - ESP32-S2:
   - Add bus suspend and wakeup support
-  
+
 - SAMD21:
   - Fix (walkaround) samd21 setup_packet overflow by USB DMA
-  
+
 - STM32 Synopsys:
   - Rework USB FIFO allocation scheme and allow RX FIFO size reduction
-  
+
 - Sony CXD56
   - Update Update Spresense SDK to 2.0.2
   - Fix dcd issues with setup packets
@@ -474,17 +909,17 @@ USB Device
 
 - CDC
   - Allow to transmit data, even if the host does not support control line states i.e set DTR
-  
+
 - HID
   - change default CFG_TUD_HID_EP_BUFSIZE from 16 to 64
-  
+
 - MIDI
   - Fix midi sysex sending bug
-  
+
 - MSC
   - Invoke only scsi complete callback after status transaction is complete.
   - Fix scsi_mode_sense6_t padding, which cause IAR compiler internal error.
-  
+
 - USBTMC
   - Change interrupt endpoint example size to 8 instead of 2 for better compatibility with mcu
 
@@ -534,20 +969,20 @@ Device Controller Driver
   - Fix FIFO flush during stall
   - Implement dcd_edpt_close() API
   - Support F105, F107
-  
+
 - Enhance STM32 fsdev
   - Improve dcd fifo allocation
   - Fix ISTR race condition
   - Support remap USB IRQ on supported MCUs
   - Implement dcd_edpt_close() API
-  
+
 - Enhance NUC 505: enhance set configure behavior
 
 - Enhance SAMD
   - Fix race condition with setup packet
   - Add SAMD11 option `OPT_MCU_SAMD11`
   - Add SAME5x option `OPT_MCU_SAME5X`
-  
+
 - Fix SAMG control data toggle and stall race condition
 
 - Enhance nRF
@@ -579,7 +1014,7 @@ USB Device
   - `usbd_driver_open()` add max length argument, and return length of interface (0 for not supported). Return value is used for finding appropriate driver
   - Add application implemented class driver via `usbd_app_driver_get_cb()`
   - IAD is handled to assign driver id
-  
+
 - Added `tud_descriptor_device_qualifier_cb()` callback
 - Optimize `tu_fifo` bulk write/read transfer
 - Forward non-std control request to class driver
@@ -595,12 +1030,12 @@ USB Device
   - Send zero length packet for end of data when needed
   - Add `tud_cdc_tx_complete_cb()` callback
   - Change tud_cdc_n_write_flush() return number of bytes forced to transfer, and flush when writing enough data to fifo
-  
+
 - MIDI:
   - Add packet interface
   - Add multiple jack descriptors
   - Fix MIDI driver for sysex
-  
+
 - DFU Runtime: fix response to SET_INTERFACE and DFU_GETSTATUS request
 
 - Rename some configure macro to make it clear that those are used directly for endpoint transfer
@@ -608,7 +1043,7 @@ USB Device
   - CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE
   - CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE
   - CFG_TUD_MIDI_EPSIZE to CFG_TUD_MIDI_EP_BUFSIZE
-  
+
 - HID:
   - Fix gamepad template descriptor
   - Add multiple HID interface API
@@ -620,7 +1055,7 @@ USB Host
 - Rework USB host stack (still work in progress)
    - Fix compile error with pipehandle
    - Rework usbh control and enumeration as non-blocking
-   
+
 - Improve Hub, MSC, HID host driver
 
 Examples
@@ -633,7 +1068,7 @@ Examples
 - Enhance `net_lwip_webserver` example
   - Add multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both)
   - Update lwip to STABLE-2_1_2_RELEASE for net_lwip_webserver
-  
+
 - Added new Audio example: audio_test uac2_headsest
 
 New Boards
@@ -699,7 +1134,7 @@ Changed
 - Generalized dcd_stm32f4.c to dcd_synopsys.c
 - Changed cdc_msc_hid to cdc_msc (drop hid) due to limited endpoints number of some MCUs
 - Improved DCD SAMD stability, fix missing setup packet occasionally
-- Improved usbd/usbd_control with proper hanlding of zero-length packet (ZLP)
+- Improved usbd/usbd_control with proper handling of zero-length packet (ZLP)
 - Improved STM32 DCD FSDev
 - Improved STM32 DCD Synopsys
 - Migrated CI from Travis to Github Action
diff --git a/docs/info/contributors.rst b/docs/info/contributors.rst
index b3748ccb5..35e0b05f5 120000
--- a/docs/info/contributors.rst
+++ b/docs/info/contributors.rst
@@ -1 +1 @@
-../../CONTRIBUTORS.rst
\ No newline at end of file
+.. include:: ../../CONTRIBUTORS.rst
\ No newline at end of file
diff --git a/docs/info/index.rst b/docs/info/index.rst
index fa56512b6..a636f37dc 100644
--- a/docs/info/index.rst
+++ b/docs/info/index.rst
@@ -8,6 +8,5 @@ Index
 .. toctree::
    :maxdepth: 2
 
-   uses
    changelog
    contributors
diff --git a/docs/info/uses.rst b/docs/info/uses.rst
deleted file mode 100644
index f67df49f8..000000000
--- a/docs/info/uses.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-****
-Uses
-****
-
-TinyUSB is currently used by these other projects:
-
--  `Adafruit nRF52 Arduino <https://github.com/adafruit/Adafruit_nRF52_Arduino>`__
--  `Adafruit nRF52 Bootloader <https://github.com/adafruit/Adafruit_nRF52_Bootloader>`__
--  `Adafruit SAMD Arduino <https://github.com/adafruit/ArduinoCore-samd>`__
--  `CircuitPython <https://github.com/adafruit/circuitpython>`__
--  `Espressif IDF <https://github.com/espressif/esp-idf>`__
--  `MicroPython <https://github.com/micropython/micropython>`__
--  `mynewt <https://mynewt.apache.org>`__
--  `openinput <https://github.com/openinput-fw/openinput>`__
--  `Raspberry Pi Pico SDK <https://github.com/raspberrypi/pico-sdk>`__
--  `TinyUF2 Bootloader <https://github.com/adafruit/tinyuf2>`__
--  `TinyUSB Arduino Library <https://github.com/adafruit/Adafruit_TinyUSB_Arduino>`__
diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
new file mode 100644
index 000000000..4739467bc
--- /dev/null
+++ b/docs/reference/boards.rst
@@ -0,0 +1,320 @@
+****************
+Supported Boards
+****************
+
+The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project.
+It is responsible for getting the MCU started and the USB peripheral clocked with minimal of on-board devices
+
+-  One LED : for status
+-  One Button : to get input from user
+-  One UART : optional for device, but required for host examples
+
+Following boards are supported
+
+Analog Devices
+--------------
+
+=============  ================  ========  ===========================================================================================================================  ======
+Board          Name              Family    URL                                                                                                                          Note
+=============  ================  ========  ===========================================================================================================================  ======
+max32650evkit  MAX32650 EVKIT    max32650  https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html#eb-overview
+max32650fthr   MAX32650 Feather  max32650  https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html
+max32651evkit  MAX32651 EVKIT    max32650  https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html
+max32666evkit  MAX32666 EVKIT    max32666  https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html
+max32666fthr   MAX32666 Feather  max32666  https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html
+apard32690     APARD32690-SL     max32690  https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html
+max32690evkit  MAX32690 EVKIT    max32690  https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html
+max78002evkit  MAX78002 EVKIT    max78002  https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html
+=============  ================  ========  ===========================================================================================================================  ======
+
+Bridgetek
+---------
+
+=========  =========  ========  =====================================  ======
+Board      Name       Family    URL                                    Note
+=========  =========  ========  =====================================  ======
+mm900evxb  MM900EVxB  brtmm90x  https://brtchip.com/product/mm900ev1b
+=========  =========  ========  =====================================  ======
+
+Espressif
+---------
+
+=========================  ==============================  =========  ========================================================================================================  ======
+Board                      Name                            Family     URL                                                                                                       Note
+=========================  ==============================  =========  ========================================================================================================  ======
+adafruit_feather_esp32_v2  Adafruit Feather ESP32 v2       espressif  https://www.adafruit.com/product/5400
+adafruit_feather_esp32s2   Adafruit Feather ESP32S2        espressif  https://www.adafruit.com/product/5000
+adafruit_feather_esp32s3   Adafruit Feather ESP32S3        espressif  https://www.adafruit.com/product/5323
+adafruit_magtag_29gray     Adafruit MagTag 2.9" Grayscale  espressif  https://www.adafruit.com/product/4800
+adafruit_metro_esp32s2     Adafruit Metro ESP32-S2         espressif  https://www.adafruit.com/product/4775
+espressif_addax_1          Espresif Addax-1                espressif  n/a
+espressif_c3_devkitc       Espresif C3 DevKitC             espressif  https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c3/esp32-c3-devkitc-02/index.html
+espressif_c6_devkitc       Espresif C6 DevKitC             espressif  https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitc-1/index.html
+espressif_kaluga_1         Espresif Kaluga 1               espressif  https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-kaluga-1/index.html
+espressif_p4_function_ev   Espresif P4 Function EV         espressif  https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/index.html
+espressif_s2_devkitc       Espresif S2 DevKitC             espressif  https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-devkitc-1/index.html
+espressif_s3_devkitc       Espresif S3 DevKitC             espressif  https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitc-1/index.html
+espressif_s3_devkitm       Espresif S3 DevKitM             espressif  https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitm-1/index.html
+espressif_saola_1          Espresif S2 Saola 1             espressif  https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-saola-1/index.html
+=========================  ==============================  =========  ========================================================================================================  ======
+
+GigaDevice
+----------
+
+==================  ==================  =========  =============================  ======
+Board               Name                Family     URL                            Note
+==================  ==================  =========  =============================  ======
+sipeed_longan_nano  Sipeed Longan Nano  gd32vf103  https://longan.sipeed.com/en/
+==================  ==================  =========  =============================  ======
+
+Infineon
+--------
+
+=============  =================  ========  =============================================================================  ======
+Board          Name               Family    URL                                                                            Note
+=============  =================  ========  =============================================================================  ======
+xmc4500_relax  XMC4500 relax kit  xmc4000   https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc45_relax_v1/
+xmc4700_relax  XMC4700 relax kit  xmc4000   https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc47_relax_v1/
+=============  =================  ========  =============================================================================  ======
+
+Microchip
+---------
+
+=========================  ===================================  ==========  =================================================================================  ======
+Board                      Name                                 Family      URL                                                                                Note
+=========================  ===================================  ==========  =================================================================================  ======
+olimex_emz64               Olimex PIC32-EMZ64                   pic32mz     https://www.olimex.com/Products/PIC/Development/PIC32-EMZ64/open-source-hardware
+olimex_hmz144              Olimex PIC32-HMZ144                  pic32mz     https://www.olimex.com/Products/PIC/Development/PIC32-HMZ144/open-source-hardware
+cynthion_d11               Great Scott Gadgets Cynthion         samd11      https://greatscottgadgets.com/cynthion/
+samd11_xplained            SAMD11 Xplained Pro                  samd11      https://www.microchip.com/en-us/development-tool/ATSAMD11-XPRO
+atsamd21_xpro              SAMD21 Xplained Pro                  samd21      https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMD21-XPRO
+circuitplayground_express  Adafruit Circuit Playground Express  samd21      https://www.adafruit.com/product/3333
+curiosity_nano             SAMD21 Curiosty Nano                 samd21      https://www.microchip.com/en-us/development-tool/dm320119
+cynthion_d21               Great Scott Gadgets Cynthion         samd21      https://greatscottgadgets.com/cynthion/
+feather_m0_express         Adafruit Feather M0 Express          samd21      https://www.adafruit.com/product/3403
+itsybitsy_m0               Adafruit ItsyBitsy M0                samd21      https://www.adafruit.com/product/3727
+metro_m0_express           Adafruit Metro M0 Express            samd21      https://www.adafruit.com/product/3505
+qtpy                       Adafruit QT Py                       samd21      https://www.adafruit.com/product/4600
+seeeduino_xiao             Seeeduino XIAO                       samd21      https://wiki.seeedstudio.com/Seeeduino-XIAO/
+sparkfun_samd21_mini_usb   SparkFun SAMD21 Mini                 samd21      https://www.sparkfun.com/products/13664
+trinket_m0                 Adafruit Trinket M0                  samd21      https://www.adafruit.com/product/3500
+d5035_01                   D5035-01                             samd5x_e5x  https://github.com/RudolphRiedel/USB_CAN-FD
+feather_m4_express         Adafruit Feather M4 Express          samd5x_e5x  https://www.adafruit.com/product/3857
+itsybitsy_m4               Adafruit ItsyBitsy M4                samd5x_e5x  https://www.adafruit.com/product/3800
+metro_m4_express           Adafruit Metro M4 Express            samd5x_e5x  https://www.adafruit.com/product/3382
+pybadge                    Adafruit PyBadge                     samd5x_e5x  https://www.adafruit.com/product/4200
+pyportal                   Adafruit PyPortal                    samd5x_e5x  https://www.adafruit.com/product/4116
+same54_xplained            SAME54 Xplained Pro                  samd5x_e5x  https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAME54-XPRO
+samg55_xplained            SAMG55 Xplained Pro                  samg        https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMG55-XPRO
+atsaml21_xpro              SAML21 Xplained Pro                  saml2x      https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b
+saml22_feather             SAML22 Feather                       saml2x      https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather
+sensorwatch_m0             SensorWatch                          saml2x      https://github.com/joeycastillo/Sensor-Watch
+=========================  ===================================  ==========  =================================================================================  ======
+
+MindMotion
+----------
+
+=====================  ======================================  ========  ===============================================================================================  ======
+Board                  Name                                    Family    URL                                                                                              Note
+=====================  ======================================  ========  ===============================================================================================  ======
+mm32f327x_mb39         MM32F3273G9P MB-039                     mm32      https://www.mindmotion.com.cn/support/development_tools/evaluation_boards/evboard/mm32f3273g9p/
+mm32f327x_pitaya_lite  DshanMCU Pitaya Lite with MM32F3273G8P  mm32      https://gitee.com/weidongshan/DshanMCU-Pitaya-c
+=====================  ======================================  ========  ===============================================================================================  ======
+
+NXP
+---
+
+==================  =========================================  =============  =========================================================================================================================================================================  ======
+Board               Name                                       Family         URL                                                                                                                                                                        Note
+==================  =========================================  =============  =========================================================================================================================================================================  ======
+metro_m7_1011       Adafruit Metro M7 1011                     imxrt          https://www.adafruit.com/product/5600
+metro_m7_1011_sd    Adafruit Metro M7 1011 SD                  imxrt          https://www.adafruit.com/product/5600
+mimxrt1010_evk      i.MX RT1010 Evaluation Kit                 imxrt          https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1010-evaluation-kit:MIMXRT1010-EVK
+mimxrt1015_evk      i.MX RT1015 Evaluation Kit                 imxrt          https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1015-EVK
+mimxrt1020_evk      i.MX RT1020 Evaluation Kit                 imxrt          https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1020-EVK
+mimxrt1024_evk      i.MX RT1024 Evaluation Kit                 imxrt          https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1024-evaluation-kit:MIMXRT1024-EVK
+mimxrt1050_evkb     i.MX RT1050 Evaluation Kit revB            imxrt          https://www.nxp.com/part/IMXRT1050-EVKB
+mimxrt1060_evk      i.MX RT1060 Evaluation Kit revB            imxrt          https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1060-EVKB
+mimxrt1064_evk      i.MX RT1064 Evaluation Kit                 imxrt          https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1064-EVK
+mimxrt1170_evkb     i.MX RT1070 Evaluation Kit                 imxrt          https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVKB
+teensy_40           Teensy 4.0                                 imxrt          https://www.pjrc.com/store/teensy40.html
+teensy_41           Teensy 4.1                                 imxrt          https://www.pjrc.com/store/teensy41.html
+frdm_k64f           Freedom K64F                               kinetis_k      https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F
+teensy_35           Teensy 3.5                                 kinetis_k      https://www.pjrc.com/store/teensy35.html
+frdm_k32l2a4s       Freedom K32L2A4S                           kinetis_k32l2  https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-K32L2A4S
+frdm_k32l2b         Freedom K32L2B3                            kinetis_k32l2  https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3
+kuiic               Kuiic                                      kinetis_k32l2  https://github.com/nxf58843/kuiic
+frdm_kl25z          fomu                                       kinetis_kl     https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z
+lpcxpresso11u37     LPCXpresso11U37                            lpc11          https://www.nxp.com/design/design-center/development-boards-and-designs/OM13074
+lpcxpresso11u68     LPCXpresso11U68                            lpc11          https://www.nxp.com/design/design-center/development-boards-and-designs/OM13058
+lpcxpresso1347      LPCXpresso1347                             lpc13          https://www.nxp.com/products/no-longer-manufactured/lpcxpresso-board-for-lpc1347:OM13045
+lpcxpresso1549      LPCXpresso1549                             lpc15          https://www.nxp.com/design/design-center/development-boards-and-designs/OM13056
+lpcxpresso1769      LPCXpresso1769                             lpc17          https://www.nxp.com/design/design-center/development-boards-and-designs/OM13000
+mbed1768            mbed 1768                                  lpc17          https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-arm-cortex-m3/arm-mbed-lpc1768-board:OM11043
+lpcxpresso18s37     LPCXpresso18s37                            lpc18          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso18s37-development-board:OM13076
+mcb1800             Keil MCB1800                               lpc18          https://www.keil.com/arm/mcb1800/
+ea4088_quickstart   Embedded Artists LPC4088 QuickStart Board  lpc40          https://www.embeddedartists.com/products/lpc4088-quickstart-board/
+ea4357              Embedded Artists LPC4357 Development Kit   lpc43          https://www.embeddedartists.com/products/lpc4357-developers-kit/
+lpcxpresso43s67     LPCXpresso43S67                            lpc43          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso43s67-development-board:OM13084
+lpcxpresso51u68     LPCXpresso51u68                            lpc51          https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005
+lpcxpresso54114     LPCXpresso54114                            lpc54          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54114-board:OM13089
+lpcxpresso54608     LPCXpresso54608                            lpc54          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-development-board-for-lpc5460x-mcus:OM13092
+lpcxpresso54628     LPCXpresso54628                            lpc54          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54628-development-board:OM13098
+double_m33_express  Double M33 Express                         lpc55          https://www.crowdsupply.com/steiert-solutions/double-m33-express
+lpcxpresso55s28     LPCXpresso55s28                            lpc55          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s28-development-board:LPC55S28-EVK
+lpcxpresso55s69     LPCXpresso55s69                            lpc55          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK
+mcu_link            MCU Link                                   lpc55          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcu-link-debug-probe:MCU-LINK
+frdm_mcxa153        Freedom MCXA153                            mcx            https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA153
+frdm_mcxn947        Freedom MCXN947                            mcx            https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXN947
+mcxn947brk          MCXN947 Breakout                           mcx            n/a
+==================  =========================================  =============  =========================================================================================================================================================================  ======
+
+Nordic Semiconductor
+--------------------
+
+===========================  =====================================  ========  ==============================================================================  ======
+Board                        Name                                   Family    URL                                                                             Note
+===========================  =====================================  ========  ==============================================================================  ======
+adafruit_clue                Adafruit CLUE                          nrf       https://www.adafruit.com/product/4500
+arduino_nano33_ble           Arduino Nano 33 BLE                    nrf       https://store.arduino.cc/arduino-nano-33-ble
+circuitplayground_bluefruit  Adafruit Circuit Playground Bluefruit  nrf       https://www.adafruit.com/product/4333
+feather_nrf52840_express     Adafruit Feather nRF52840 Express      nrf       https://www.adafruit.com/product/4062
+feather_nrf52840_sense       Adafruit Feather nRF52840 Sense        nrf       https://www.adafruit.com/product/4516
+itsybitsy_nrf52840           Adafruit ItsyBitsy nRF52840 Express    nrf       https://www.adafruit.com/product/4481
+pca10056                     Nordic nRF52840DK                      nrf       https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK
+pca10059                     Nordic nRF52840 Dongle                 nrf       https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle
+pca10095                     Nordic nRF5340 DK                      nrf       https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF5340-DK
+pca10100                     Nordic nRF52833 DK                     nrf       https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK
+===========================  =====================================  ========  ==============================================================================  ======
+
+Raspberry Pi
+------------
+
+=================  =================  ==============  ==========================================================  ======
+Board              Name               Family          URL                                                         Note
+=================  =================  ==============  ==========================================================  ======
+raspberrypi_zero   Raspberry Pi Zero  broadcom_32bit  https://www.raspberrypi.org/products/raspberry-pi-zero/
+raspberrypi_cm4    Raspberry CM4      broadcom_64bit  https://www.raspberrypi.org/products/compute-module-4
+raspberrypi_zero2  Raspberry Zero2    broadcom_64bit  https://www.raspberrypi.org/products/raspberry-pi-zero-2-w
+=================  =================  ==============  ==========================================================  ======
+
+Renesas
+-------
+
+==============  ===========================  ========  ================================================================================================================================================================  ======
+Board           Name                         Family    URL                                                                                                                                                               Note
+==============  ===========================  ========  ================================================================================================================================================================  ======
+da14695_dk_usb  DA14695-00HQDEVKT-U          da1469x   https://www.renesas.com/en/products/wireless-connectivity/bluetooth-low-energy/da14695-00hqdevkt-u-smartbond-da14695-bluetooth-low-energy-52-usb-development-kit
+da1469x_dk_pro  DA1469x Development Kit Pro  da1469x   https://lpccs-docs.renesas.com/um-b-090-da1469x_getting_started/DA1469x_The_hardware/DA1469x_The_hardware.html
+portenta_c33    Arduino Portenta C33         ra        https://www.arduino.cc/pro/hardware-product-portenta-c33/
+ra2a1_ek        RA2A1 EK                     ra        https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2a1-evaluation-kit-ra2a1-mcu-group
+ra4m1_ek        RA4M1 EK                     ra        https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group
+ra4m3_ek        RA4M3 EK                     ra        https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m3-evaluation-kit-ra4m3-mcu-group
+ra6m1_ek        RA6M1 EK                     ra        https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group
+ra6m5_ek        RA6M5 EK                     ra        https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m5-evaluation-kit-ra6m5-mcu-group
+ra8m1_ek        RA8M1 EK                     ra        https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8m1-evaluation-kit-ra8m1-mcu-group
+uno_r4          Arduino UNO R4               ra        https://store-usa.arduino.cc/pages/uno-r4
+==============  ===========================  ========  ================================================================================================================================================================  ======
+
+STMicroelectronics
+------------------
+
+===================  =================================  ========  =================================================================  ======
+Board                Name                               Family    URL                                                                Note
+===================  =================================  ========  =================================================================  ======
+stm32c071nucleo      STM32C071 Nucleo                   stm32c0   https://www.st.com/en/evaluation-tools/nucleo-g071rb.html
+stm32f070rbnucleo    STM32 F070 Nucleo                  stm32f0   https://www.st.com/en/evaluation-tools/nucleo-f070rb.html
+stm32f072disco       STM32 F072 Discovery               stm32f0   https://www.st.com/en/evaluation-tools/32f072bdiscovery.html
+stm32f072eval        STM32 F072 Eval                    stm32f0   https://www.st.com/en/evaluation-tools/stm32072b-eval.html
+stm32f103_bluepill   STM32 F103 Bluepill                stm32f1   https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill
+stm32f103_mini_2     STM32 F103 Mini v2                 stm32f1   https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0
+stm32f103ze_iar      IAR STM32 F103ze starter kit       stm32f1   n/a
+stm32f207nucleo      STM32 F207 Nucleo                  stm32f2   https://www.st.com/en/evaluation-tools/nucleo-f207zg.html
+stm32f303disco       STM32 F303 Discovery               stm32f3   https://www.st.com/en/evaluation-tools/stm32f3discovery.html
+feather_stm32f405    Adafruit Feather STM32F405         stm32f4   https://www.adafruit.com/product/4382
+pyboardv11           Pyboard v1.1                       stm32f4   https://www.adafruit.com/product/2390
+stm32f401blackpill   STM32 F401 Blackpill               stm32f4   https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2
+stm32f407blackvet    STM32 F407 Blackvet                stm32f4   https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0
+stm32f407disco       STM32 F407 Discovery               stm32f4   https://www.st.com/en/evaluation-tools/stm32f4discovery.html
+stm32f411blackpill   STM32 F411 Blackpill               stm32f4   https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0
+stm32f411disco       STM32 F411 Discovery               stm32f4   https://www.st.com/en/evaluation-tools/32f411ediscovery.html
+stm32f412disco       STM32 F412 Discovery               stm32f4   https://www.st.com/en/evaluation-tools/32f412gdiscovery.html
+stm32f412nucleo      STM32 F412 Nucleo                  stm32f4   https://www.st.com/en/evaluation-tools/nucleo-f412zg.html
+stm32f439nucleo      STM32 F439 Nucleo                  stm32f4   https://www.st.com/en/evaluation-tools/nucleo-f439zi.html
+stlinkv3mini         Stlink-v3 mini                     stm32f7   https://www.st.com/en/development-tools/stlink-v3mini.html
+stm32f723disco       STM32 F723 Discovery               stm32f7   https://www.st.com/en/evaluation-tools/32f723ediscovery.html
+stm32f746disco       STM32 F746 Discovery               stm32f7   https://www.st.com/en/evaluation-tools/32f746gdiscovery.html
+stm32f746nucleo      STM32 F746 Nucleo                  stm32f7   https://www.st.com/en/evaluation-tools/nucleo-f746zg.html
+stm32f767nucleo      STM32 F767 Nucleo                  stm32f7   https://www.st.com/en/evaluation-tools/nucleo-f767zi.html
+stm32f769disco       STM32 F769 Discovery               stm32f7   https://www.st.com/en/evaluation-tools/32f769idiscovery.html
+stm32g0b1nucleo      STM32 G0B1 Nucleo                  stm32g0   https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html
+b_g474e_dpow1        STM32 B-G474E-DPOW1 Discovery kit  stm32g4   https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html
+stm32g474nucleo      STM32 G474 Nucleo                  stm32g4   https://www.st.com/en/evaluation-tools/nucleo-g474re.html
+stm32g491nucleo      STM32 G491 Nucleo                  stm32g4   https://www.st.com/en/evaluation-tools/nucleo-g491re.html
+stm32h503nucleo      STM32 H503 Nucleo                  stm32h5   https://www.st.com/en/evaluation-tools/nucleo-h503rb.html
+stm32h563nucleo      STM32 H563 Nucleo                  stm32h5   https://www.st.com/en/evaluation-tools/nucleo-h563zi.html
+stm32h573i_dk        STM32 H573i Discovery              stm32h5   https://www.st.com/en/evaluation-tools/stm32h573i-dk.html
+daisyseed            Daisy Seed                         stm32h7   https://electro-smith.com/products/daisy-seed
+stm32h723nucleo      STM32 H723 Nucleo                  stm32h7   https://www.st.com/en/evaluation-tools/nucleo-h723zg.html
+stm32h743eval        STM32 H743 Eval                    stm32h7   https://www.st.com/en/evaluation-tools/stm32h743i-eval.html
+stm32h743nucleo      STM32 H743 Nucleo                  stm32h7   https://www.st.com/en/evaluation-tools/nucleo-h743zi.html
+stm32h745disco       STM32 H745 Discovery               stm32h7   https://www.st.com/en/evaluation-tools/stm32h745i-disco.html
+stm32h750_weact      STM32 H750 WeAct                   stm32h7   https://www.adafruit.com/product/5032
+stm32h750bdk         STM32 H750b Discovery Kit          stm32h7   https://www.st.com/en/evaluation-tools/stm32h750b-dk.html
+waveshare_openh743i  Waveshare Open H743i               stm32h7   https://www.waveshare.com/openh743i-c-standard.htm
+stm32l052dap52       STM32 L052 DAP                     stm32l0   n/a
+stm32l0538disco      STM32 L0538 Discovery              stm32l0   https://www.st.com/en/evaluation-tools/32l0538discovery.html
+stm32l412nucleo      STM32 L412 Nucleo                  stm32l4   https://www.st.com/en/evaluation-tools/nucleo-l412kb.html
+stm32l476disco       STM32 L476 Disco                   stm32l4   https://www.st.com/en/evaluation-tools/32l476gdiscovery.html
+stm32l4p5nucleo      STM32 L4P5 Nucleo                  stm32l4   https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html
+stm32l4r5nucleo      STM32 L4R5 Nucleo                  stm32l4   https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html
+b_u585i_iot2a        STM32 B-U585i IOT2A Discovery kit  stm32u5   https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html
+stm32u545nucleo      STM32 U545 Nucleo                  stm32u5   https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html
+stm32u575eval        STM32 U575 Eval                    stm32u5   https://www.st.com/en/evaluation-tools/stm32u575i-ev.html
+stm32u575nucleo      STM32 U575 Nucleo                  stm32u5   https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html
+stm32u5a5nucleo      STM32 U5a5 Nucleo                  stm32u5   https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html
+stm32wb55nucleo      STM32 P-NUCLEO-WB55                stm32wb   https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html
+===================  =================================  ========  =================================================================  ======
+
+Sunxi
+-----
+
+=======  =================  ========  =========================================  ======
+Board    Name               Family    URL                                        Note
+=======  =================  ========  =========================================  ======
+f1c100s  Lctech Pi F1C200s  f1c100s   https://linux-sunxi.org/Lctech_Pi_F1C200s
+=======  =================  ========  =========================================  ======
+
+Texas Instruments
+-----------------
+
+=================  =====================  ========  =========================================  ======
+Board              Name                   Family    URL                                        Note
+=================  =====================  ========  =========================================  ======
+msp_exp430f5529lp  MSP430F5529 LaunchPad  msp430    https://www.ti.com/tool/MSP-EXP430F5529LP
+msp_exp432e401y    MSP432E401Y LaunchPad  msp432e4  https://www.ti.com/tool/MSP-EXP432E401Y
+ek_tm4c123gxl      TM4C123G LaunchPad     tm4c      https://www.ti.com/tool/EK-TM4C123GXL
+=================  =====================  ========  =========================================  ======
+
+Tomu
+----
+
+=======  ======  ========  =========================  ======
+Board    Name    Family    URL                        Note
+=======  ======  ========  =========================  ======
+fomu     fomu    fomu      https://tomu.im/fomu.html
+=======  ======  ========  =========================  ======
+
+WCH
+---
+
+================  ================  ========  =====================================================================  ======
+Board             Name              Family    URL                                                                    Note
+================  ================  ========  =====================================================================  ======
+ch32f205r-r0      CH32F205r-r0      ch32f20x  https://github.com/openwch/ch32f20x
+ch32v103r_r1_1v0  CH32V103R-R1-1v1  ch32v10x  https://github.com/openwch/ch32v103/tree/main/SCHPCB/CH32V103R-R1-1v1
+ch32v203c_r0_1v0  CH32V203C-R0-1v0  ch32v20x  https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0
+ch32v203g_r0_1v0  CH32V203G-R0-1v0  ch32v20x  https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0
+nanoch32v203      nanoCH32V203      ch32v20x  https://github.com/wuxx/nanoCH32V203
+ch32v307v_r1_1v0  CH32V307V-R1-1v0  ch32v307  https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0
+================  ================  ========  =====================================================================  ======
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
new file mode 100644
index 000000000..e124466da
--- /dev/null
+++ b/docs/reference/dependencies.rst
@@ -0,0 +1,73 @@
+************
+Dependencies
+************
+
+MCU low-level peripheral driver and external libraries for building TinyUSB examples
+
+========================================  ==============================================================  ========================================  ====================================================================================================================================================================================================================================================================================================================================
+Local Path                                Repo                                                            Commit                                    Required by
+========================================  ==============================================================  ========================================  ====================================================================================================================================================================================================================================================================================================================================
+hw/mcu/allwinner                          https://github.com/hathach/allwinner_driver.git                 8e5e89e8e132c0fd90e72d5422e5d3d68232b756  fc100s
+hw/mcu/analog/max32                       https://github.com/analogdevicesinc/msdk.git                    b20b398d3e5e2007594e54a74ba3d2a2e50ddd75  max32650 max32666 max32690 max78002
+hw/mcu/bridgetek/ft9xx/ft90x-sdk          https://github.com/BRTSG-FOSS/ft90x-sdk.git                     91060164afe239fcb394122e8bf9eb24d3194eb1  brtmm90x
+hw/mcu/broadcom                           https://github.com/adafruit/broadcom-peripherals.git            08370086080759ed54ac1136d62d2ad24c6fa267  broadcom_32bit broadcom_64bit
+hw/mcu/gd/nuclei-sdk                      https://github.com/Nuclei-Software/nuclei-sdk.git               7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7  gd32vf103
+hw/mcu/infineon/mtb-xmclib-cat3           https://github.com/Infineon/mtb-xmclib-cat3.git                 daf5500d03cba23e68c2f241c30af79cd9d63880  xmc4000
+hw/mcu/microchip                          https://github.com/hathach/microchip_driver.git                 9e8b37e307d8404033bb881623a113931e1edf27  sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg
+hw/mcu/mindmotion/mm32sdk                 https://github.com/hathach/mm32sdk.git                          b93e856211060ae825216c6a1d6aa347ec758843  mm32
+hw/mcu/nordic/nrfx                        https://github.com/NordicSemiconductor/nrfx.git                 7c47cc0a56ce44658e6da2458e86cd8783ccc4a2  nrf
+hw/mcu/nuvoton                            https://github.com/majbthrd/nuc_driver.git                      2204191ec76283371419fbcec207da02e1bc22fa  nuc
+hw/mcu/nxp/lpcopen                        https://github.com/hathach/nxp_lpcopen.git                      b41cf930e65c734d8ec6de04f1d57d46787c76ae  lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43
+hw/mcu/nxp/mcux-sdk                       https://github.com/hathach/mcux-sdk.git                         144f1eb7ea8c06512e12f12b27383601c0272410  kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt
+hw/mcu/raspberry_pi/Pico-PIO-USB          https://github.com/sekigon-gonnoc/Pico-PIO-USB.git              fe9133fc513b82cc3dc62c67cb51f2339cf29ef7  rp2040
+hw/mcu/renesas/fsp                        https://github.com/renesas/fsp.git                              edcc97d684b6f716728a60d7a6fea049d9870bd6  ra
+hw/mcu/renesas/rx                         https://github.com/kkitayam/rx_device.git                       706b4e0cf485605c32351e2f90f5698267996023  rx
+hw/mcu/silabs/cmsis-dfp-efm32gg12b        https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git         f1c31b7887669cb230b3ea63f9b56769078960bc  efm32
+hw/mcu/sony/cxd56/spresense-exported-sdk  https://github.com/sonydevworld/spresense-exported-sdk.git      2ec2a1538362696118dc3fdf56f33dacaf8f4067  spresense
+hw/mcu/st/cmsis_device_c0                 https://github.com/STMicroelectronics/cmsis_device_c0.git       fb56b1b70c73b74eacda2a4bcc36886444364ab3  stm32c0
+hw/mcu/st/cmsis_device_f0                 https://github.com/STMicroelectronics/cmsis_device_f0.git       2fc25ee22264bc27034358be0bd400b893ef837e  stm32f0
+hw/mcu/st/cmsis_device_f1                 https://github.com/STMicroelectronics/cmsis_device_f1.git       6601104a6397299b7304fd5bcd9a491f56cb23a6  stm32f1
+hw/mcu/st/cmsis_device_f2                 https://github.com/STMicroelectronics/cmsis_device_f2.git       182fcb3681ce116816feb41b7764f1b019ce796f  stm32f2
+hw/mcu/st/cmsis_device_f3                 https://github.com/STMicroelectronics/cmsis_device_f3.git       5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b  stm32f3
+hw/mcu/st/cmsis_device_f4                 https://github.com/STMicroelectronics/cmsis_device_f4.git       2615e866fa48fe1ff1af9e31c348813f2b19e7ec  stm32f4
+hw/mcu/st/cmsis_device_f7                 https://github.com/STMicroelectronics/cmsis_device_f7.git       25b0463439303b7a38f0d27b161f7d2f3c096e79  stm32f7
+hw/mcu/st/cmsis_device_g0                 https://github.com/STMicroelectronics/cmsis_device_g0.git       3a23e1224417f3f2d00300ecd620495e363f2094  stm32g0
+hw/mcu/st/cmsis_device_g4                 https://github.com/STMicroelectronics/cmsis_device_g4.git       ce822adb1dc552b3aedd13621edbc7fdae124878  stm32g4
+hw/mcu/st/cmsis_device_h5                 https://github.com/STMicroelectronics/cmsis_device_h5.git       cd2d1d579743de57b88ccaf61a968b9c05848ffc  stm32h5
+hw/mcu/st/cmsis_device_h7                 https://github.com/STMicroelectronics/cmsis_device_h7.git       60dc2c913203dc8629dc233d4384dcc41c91e77f  stm32h7
+hw/mcu/st/cmsis_device_l0                 https://github.com/STMicroelectronics/cmsis_device_l0.git       69cd5999fd40ae6e546d4905b21635c6ca1bcb92  stm32l0
+hw/mcu/st/cmsis_device_l1                 https://github.com/STMicroelectronics/cmsis_device_l1.git       7f16ec0a1c4c063f84160b4cc6bf88ad554a823e  stm32l1
+hw/mcu/st/cmsis_device_l4                 https://github.com/STMicroelectronics/cmsis_device_l4.git       6ca7312fa6a5a460b5a5a63d66da527fdd8359a6  stm32l4
+hw/mcu/st/cmsis_device_l5                 https://github.com/STMicroelectronics/cmsis_device_l5.git       d922865fc0326a102c26211c44b8e42f52c1e53d  stm32l5
+hw/mcu/st/cmsis_device_u5                 https://github.com/STMicroelectronics/cmsis_device_u5.git       5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309  stm32u5
+hw/mcu/st/cmsis_device_wb                 https://github.com/STMicroelectronics/cmsis_device_wb.git       9c5d1920dd9fabbe2548e10561d63db829bb744f  stm32wb
+hw/mcu/st/stm32-mfxstm32l152              https://github.com/STMicroelectronics/stm32-mfxstm32l152.git    7f4389efee9c6a655b55e5df3fceef5586b35f9b  stm32h7
+hw/mcu/st/stm32c0xx_hal_driver            https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git  41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3  stm32c0
+hw/mcu/st/stm32f0xx_hal_driver            https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git  0e95cd88657030f640a11e690a8a5186c7712ea5  stm32f0
+hw/mcu/st/stm32f1xx_hal_driver            https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git  1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29  stm32f1
+hw/mcu/st/stm32f2xx_hal_driver            https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git  c75ace9b908a9aca631193ebf2466963b8ea33d0  stm32f2
+hw/mcu/st/stm32f3xx_hal_driver            https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git  1761b6207318ede021706e75aae78f452d72b6fa  stm32f3
+hw/mcu/st/stm32f4xx_hal_driver            https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git  04e99fbdabd00ab8f370f377c66b0a4570365b58  stm32f4
+hw/mcu/st/stm32f7xx_hal_driver            https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git  f7ffdf6bf72110e58b42c632b0a051df5997e4ee  stm32f7
+hw/mcu/st/stm32g0xx_hal_driver            https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git  e911b12c7f67084d7f6b76157a4c0d4e2ec3779c  stm32g0
+hw/mcu/st/stm32g4xx_hal_driver            https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git  8b4518417706d42eef5c14e56a650005abf478a8  stm32g4
+hw/mcu/st/stm32h5xx_hal_driver            https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git  2cf77de584196d619cec1b4586c3b9e2820a254e  stm32h5
+hw/mcu/st/stm32h7xx_hal_driver            https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git  d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04  stm32h7
+hw/mcu/st/stm32l0xx_hal_driver            https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git  fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b  stm32l0
+hw/mcu/st/stm32l1xx_hal_driver            https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git  44efc446fa69ed8344e7fd966e68ed11043b35d9  stm32l1
+hw/mcu/st/stm32l4xx_hal_driver            https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git  aee3d5bf283ae5df87532b781bdd01b7caf256fc  stm32l4
+hw/mcu/st/stm32l5xx_hal_driver            https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git  675c32a75df37f39d50d61f51cb0dcf53f07e1cb  stm32l5
+hw/mcu/st/stm32u5xx_hal_driver            https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git  4d93097a67928e9377e655ddd14622adc31b9770  stm32u5
+hw/mcu/st/stm32wbxx_hal_driver            https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git  2c5f06638be516c1b772f768456ba637f077bac8  stm32wb
+hw/mcu/ti                                 https://github.com/hathach/ti_driver.git                        143ed6cc20a7615d042b03b21e070197d473e6e5  msp430 msp432e4 tm4c
+hw/mcu/wch/ch32f20x                       https://github.com/openwch/ch32f20x.git                         77c4095087e5ed2c548ec9058e655d0b8757663b  ch32f20x
+hw/mcu/wch/ch32v103                       https://github.com/openwch/ch32v103.git                         7578cae0b21f86dd053a1f781b2fc6ab99d0ec17  ch32v10x
+hw/mcu/wch/ch32v20x                       https://github.com/openwch/ch32v20x.git                         c4c38f507e258a4e69b059ccc2dc27dde33cea1b  ch32v20x
+hw/mcu/wch/ch32v307                       https://github.com/openwch/ch32v307.git                         184f21b852cb95eed58e86e901837bc9fff68775  ch32v307
+lib/CMSIS_5                               https://github.com/ARM-software/CMSIS_5.git                     2b7495b8535bdcb306dac29b9ded4cfb679d7e5c  imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg tm4c
+lib/CMSIS_6                               https://github.com/ARM-software/CMSIS_6.git                     b0bbb0423b278ca632cfe1474eb227961d835fd2  ra
+lib/FreeRTOS-Kernel                       https://github.com/FreeRTOS/FreeRTOS-Kernel.git                 cc0e0707c0c748713485b870bb980852b210877f  all
+lib/lwip                                  https://github.com/lwip-tcpip/lwip.git                          159e31b689577dbf69cf0683bbaffbd71fa5ee10  all
+lib/sct_neopixel                          https://github.com/gsteiert/sct_neopixel.git                    e73e04ca63495672d955f9268e003cffe168fcd8  lpc55
+tools/uf2                                 https://github.com/microsoft/uf2.git                            c594542b2faa01cc33a2b97c9fbebc38549df80a  all
+========================================  ==============================================================  ========================================  ====================================================================================================================================================================================================================================================================================================================================
diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index e328757ba..963420f7b 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -5,82 +5,104 @@ Getting Started
 Add TinyUSB to your project
 ---------------------------
 
-It is relatively simple to incorporate tinyusb to your (existing) project
-
+It is relatively simple to incorporate tinyusb to your project
 
 * Copy or ``git submodule`` this repo into your project in a subfolder. Let's say it is *your_project/tinyusb*
 * Add all the .c in the ``tinyusb/src`` folder to your project
 * Add *your_project/tinyusb/src* to your include path. Also make sure your current include path also contains the configuration file tusb_config.h.
-* Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as CFG_TUSB_MCU, CFG_TUSB_OS since they are passed by IDE/compiler to maintain a unique configure for all boards).
+* Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as ``CFG_TUSB_MCU``, ``CFG_TUSB_OS`` since they are passed by IDE/compiler to maintain a unique configure for all boards).
 * If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to implement all **tud descriptor** callbacks for the stack to work.
-* Add tusb_init() call to your reset initialization code.
-* Call ``tud_int_handler()`` (device) and/or ``tuh_int_handler()`` (host) in your USB IRQ Handler
+* Add tusb_init(rhport, role) call to your reset initialization code.
+* Call ``tusb_int_handler(rhport, in_isr)`` in your USB IRQ Handler
 * Implement all enabled classes's callbacks.
 * If you don't use any RTOSes at all, you need to continuously and/or periodically call tud_task()/tuh_task() function. All of the callbacks and functionality are handled and invoked within the call of that task runner.
 
 .. code-block::
 
-   int main(void)
-   {
-     your_init_code();
-     tusb_init(); // initialize tinyusb stack
+   int main(void) {
+     tusb_rhport_init_t dev_init = {
+        .role = TUSB_ROLE_DEVICE,
+        .speed = TUSB_SPEED_AUTO
+     };
+     tusb_init(0, &dev_init); // initialize device stack on roothub port 0
 
-     while(1) // the mainloop
-     {
+     tusb_rhport_init_t host_init = {
+        .role = TUSB_ROLE_HOST,
+        .speed = TUSB_SPEED_AUTO
+     };
+     tusb_init(1, &host_init); // initialize host stack on roothub port 1
+
+     while(1) { // the mainloop
        your_application_code();
-
        tud_task(); // device task
        tuh_task(); // host task
      }
    }
 
+   void USB0_IRQHandler(void) {
+     tusb_int_handler(0, true);
+   }
+
+   void USB1_IRQHandler(void) {
+     tusb_int_handler(1, true);
+   }
+
 Examples
 --------
 
-For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of `the supported boards <supported.rst>`_. Firstly we need to ``git clone`` if not already
+For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of `the supported boards <boards.rst>`_. Firstly we need to ``git clone`` if not already
 
 .. code-block::
 
    $ git clone https://github.com/hathach/tinyusb tinyusb
    $ cd tinyusb
 
-Some TinyUSB examples also requires external submodule libraries in ``/lib`` such as FreeRTOS, Lightweight IP to build. Run following command to fetch them 
+Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide.
+
+Dependencies
+^^^^^^^^^^^^
+
+The hardware code is located in ``hw/bsp`` folder, and is organized by family/boards. e.g raspberry_pi_pico is located in ``hw/bsp/rp2040/boards/raspberry_pi_pico`` where FAMILY=rp2040 and BOARD=raspberry_pi_pico. Before building, we firstly need to download dependencies such as: MCU low-level peripheral driver and external libraries e.g FreeRTOS (required by some examples). We can do that by either ways:
+
+1. Run ``tools/get_deps.py {FAMILY}`` script to download all dependencies for a family as follow. Note: For TinyUSB developer to download all dependencies, use FAMILY=all.
 
 .. code-block::
 
-   $ git submodule update --init lib
+   $ python tools/get_deps.py rp2040
 
-Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide. 
+2. Or run the ``get-deps`` target in one of the example folder as follow.
+
+.. code-block::
+
+   $ cd examples/device/cdc_msc
+   $ make BOARD=raspberry_pi_pico get-deps
+
+You only need to do this once per family. Check out `complete list of dependencies and their designated path here <dependencies.rst>`_
 
 Build
 ^^^^^
 
-To build example, first change directory to an example folder. 
+To build example, first change directory to an example folder.
 
 .. code-block::
 
    $ cd examples/device/cdc_msc
 
-Before building, we need to download MCU driver submodule to provide low-level MCU peripheral's driver first. Run the ``get-deps`` target in one of the example folder as follow. You only need to do this once per mcu
+Then compile with ``make BOARD={board_name} all`` , for example
 
 .. code-block::
 
-   $ make BOARD=feather_nrf52840_express get-deps
+   $ make BOARD=raspberry_pi_pico all
 
-
-Some modules (e.g. RP2040 and ESP32s2) require the project makefiles to be customized using CMake. If necessary apply any setup steps for the platform's SDK.
-
-Then compile with ``make BOARD=[board_name] all``\ , for example
+Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``99-tinyusb.rules`` and reload your udev is good to go
 
 .. code-block::
 
-   $ make BOARD=feather_nrf52840_express all
+   $ cp examples/device/99-tinyusb.rules /etc/udev/rules.d/
+   $ sudo udevadm control --reload-rules && sudo udevadm trigger
 
-Note: ``BOARD`` can be found as directory name in ``hw/bsp``\ , either in its family/boards or directly under bsp (no family).
-Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``/examples/device/99-tinyusb.rules`` file to /etc/udev/rules.d/ then run ``sudo udevadm control --reload-rules && sudo udevadm trigger`` is good enough.
-
-Port Selection
-~~~~~~~~~~~~~~
+RootHub Port Selection
+~~~~~~~~~~~~~~~~~~~~~~
 
 If a board has several ports, one port is chosen by default in the individual board.mk file. Use option ``PORT=x`` To choose another port. For example to select the HS port of a STM32F746Disco board, use:
 
@@ -118,7 +140,7 @@ To compile for debugging add ``DEBUG=1``\ , for example
 Log
 ~~~
 
-Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional ``LOG=``. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet. 
+Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional ``LOG=``. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet.
 
 .. code-block::
 
@@ -127,7 +149,7 @@ Should you have an issue running example and/or submitting an bug report. You co
 Logger
 ~~~~~~
 
-By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols: 
+By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols:
 
 
 * `LOGGER=rtt`: use `Segger RTT protocol <https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/>`_
@@ -170,7 +192,10 @@ Some board use uf2 bootloader for drag & drop in to mass storage device, uf2 can
    $ make BOARD=feather_nrf52840_express all uf2
 
 IAR Support
-^^^^^^^^^^^
+-----------
+
+Use project connection
+^^^^^^^^^^^^^^^^^^^^^^
 
 IAR Project Connection files are provided to import TinyUSB stack into your project.
 
@@ -178,24 +203,24 @@ IAR Project Connection files are provided to import TinyUSB stack into your proj
 
 
   * Take example of STM32F0:
-  
+
     -  You need `stm32l0xx.h`, `startup_stm32f0xx.s`, `system_stm32f0xx.c`.
 
     - `STM32L0xx_HAL_Driver` is only needed to run examples, TinyUSB stack itself doesn't rely on MCU's SDKs.
 
-* Open `Tools -> Configure Custom Argument Variables` (Switch to `Global` tab if you want to do it for all your projects) 
+* Open ``Tools -> Configure Custom Argument Variables`` (Switch to `Global` tab if you want to do it for all your projects)
    Click `New Group ...`, name it to `TUSB`, Click `Add Variable ...`, name it to `TUSB_DIR`, change it's value to the path of your TinyUSB stack,
    for example `C:\\tinyusb`
 
 Import stack only
 ~~~~~~~~~~~~~~~~~
 
-1. Open `Project -> Add project Connection ...`, click `OK`, choose `tinyusb\\tools\\iar_template.ipcf`.
+1. Open ``Project -> Add project Connection ...``, click `OK`, choose `tinyusb\\tools\\iar_template.ipcf`.
 
 Run examples
 ~~~~~~~~~~~~
 
-1. (Python3 is needed) Run `iar_gen.py` to generate .ipcf files of examples:
+1. (Python3 is needed) Run ``iar_gen.py`` to generate .ipcf files of examples:
 
    .. code-block::
 
@@ -204,3 +229,15 @@ Run examples
 
 2. Open `Project -> Add project Connection ...`, click `OK`, choose `tinyusb\\examples\\(.ipcf of example)`.
    For example `C:\\tinyusb\\examples\\device\\cdc_msc\\iar_cdc_msc.ipcf`
+
+Native CMake support (9.50.1+)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+With 9.50.1 release, IAR added experimental native CMake support (strangely not mentioned in public release note). Now it's possible to import CMakeLists.txt then build and debug as a normal project.
+
+Following these steps:
+
+1. Add IAR compiler binary path to system ``PATH`` environment variable, such as ``C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin``.
+2. Create new project in IAR, in Tool chain dropdown menu, choose CMake for Arm then Import ``CMakeLists.txt`` from chosen example directory.
+3. Set up board option in ``Option - CMake/CMSIS-TOOLBOX - CMake``, for example :code:`-DBOARD=stm32f439nucleo -DTOOLCHAIN=iar`, **Uncheck 'Override tools in env'**.
+4. (For debug only) Choose correct CPU model in ``Option - General Options - Target``, to profit register and memory view.
diff --git a/docs/reference/index.rst b/docs/reference/index.rst
index 292fb1a93..8ac3cf924 100644
--- a/docs/reference/index.rst
+++ b/docs/reference/index.rst
@@ -1,59 +1,10 @@
-*********
-Reference
-*********
-
-.. figure:: ../assets/stack.svg
-   :width: 1600px
-   :alt: stackup
-
-   representation of the TinyUSB stack.
-
-Device Stack
-============
-
-Supports multiple device configurations by dynamically changing usb descriptors. Low power functions such like suspend, resume, and remote wakeup. Following device classes are supported:
-
--  Audio Class 2.0 (UAC2)
--  Bluetooth Host Controller Interface (BTH HCI)
--  Communication Class (CDC)
--  Device Firmware Update (DFU): DFU mode (WIP) and Runtinme
--  Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
--  Mass Storage Class (MSC): with multiple LUNs
--  Musical Instrument Digital Interface (MIDI)
--  Network with RNDIS, CDC-ECM (work in progress)
--  USB Test and Measurement Class (USBTMC)
--  Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file.
--  `WebUSB <https://github.com/WICG/webusb>`__ with vendor-specific class
-
-If you have special need, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how RPi team add their reset interface `raspberrypi/pico-sdk#197 <https://github.com/raspberrypi/pico-sdk/pull/197>`__
-
-Host Stack
-==========
-
-- Human Interface Device (HID): Keyboard, Mouse, Generic
-- Mass Storage Class (MSC)
-- Hub currently only supports 1 level of hub (due to my laziness)
-
-OS Abstraction layer
-====================
-
-TinyUSB is completely thread-safe by pushing all ISR events into a central queue, then process it later in the non-ISR context task function. It also uses semaphore/mutex to access shared resources such as CDC FIFO. Therefore the stack needs to use some of OS's basic APIs. Following OSes are already supported out of the box.
-
-- **No OS**
-- **FreeRTOS**
-- **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its `own repo <https://github.com/hathach/mynewt-tinyusb-example>`__
-
-License
-=======
-
-All TinyUSB sources in the `src` folder are licensed under MIT license. However, each file can be individually licensed especially those in `lib` and `hw/mcu` folder. Please make sure you understand all the license term for files you use in your project.
-
 Index
 =====
 
 .. toctree::
    :maxdepth: 2
 
-   supported
    getting_started
+   boards
+   dependencies
    concurrency
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
deleted file mode 100644
index 1fb858a45..000000000
--- a/docs/reference/supported.rst
+++ /dev/null
@@ -1,399 +0,0 @@
-*****************
-Supported Devices
-*****************
-
-Supported MCUs
-==============
-
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Manufacturer | Family                | Device | Host | Highspeed | Driver            | Note         |
-+==============+=======================+========+======+===========+===================+==============+
-| Broadcom     | BCM2711, BCM2837      | ✔      |      | ✔         | dwc2              |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Dialog       | DA1469x               | ✔      | ✖    | ✖         | da146xx           |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Espressif    | ESP32 S2, S3          | ✔      |      | ✖         | dwc2 or esp32sx   |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| GigaDevice   | GD32VF103             | ✔      |      | ✖         | dwc2              |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Infineon     | XMC4500               | ✔      |      | ✖         | dwc2              |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| MicroChip    | SAM D11, D21          | ✔      |      | ✖         | samd              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | SAM D51, E5x          | ✔      |      | ✖         | samd              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | SAM G55               | ✔      |      | ✖         | samg              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | SAM L21, L22          | ✔      |      | ✖         | samd              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | SAM E70,S70,V70,V71   | ✔      |      | ✔         | samx7x            |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| NordicSemi   | nRF52833, nRF52840    | ✔      | ✖    | ✖         | nrf5x             |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | nRF5340               | ✔      | ✖    | ✖         | nrf5x             |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Nuvoton      | NUC120                | ✔      | ✖    | ✖         |                   |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | NUC121/NUC125         | ✔      | ✖    | ✖         |                   |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | NUC126                | ✔      | ✖    | ✖         |                   |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | NUC505                | ✔      |      | ✔         |                   |              |
-+--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
-| NXP          | iMXRT   | RT10xx      | ✔      | ✔    | ✔         | ci_hs             |              |
-|              |         +-------------+--------+------+-----------+-------------------+--------------+
-|              |         | RT11xx      | ✔      | ✔    | ✔         | ci_hs             |              |
-|              +---------+-------------+--------+------+-----------+-------------------+--------------+
-|              | Kinetis | KL25        | ✔      | ⚠    | ✖         |                   |              |
-|              |         +-------------+--------+------+-----------+-------------------+--------------+
-|              |         | K32L2       | ✔      |      | ✖         |                   |              |
-|              +---------+-------------+--------+------+-----------+-------------------+--------------+
-|              | LPC     | 11u, 13, 15 | ✔      | ✖    | ✖         | lpc_ip3511        |              |
-|              |         +-------------+--------+------+-----------+-------------------+--------------+
-|              |         | 17, 40      | ✔      | ⚠    | ✖         | lpc17_40          |              |
-|              |         +-------------+--------+------+-----------+-------------------+--------------+
-|              |         | 18, 43      | ✔      | ✔    | ✔         | ci_hs             |              |
-|              |         +-------------+--------+------+-----------+-------------------+--------------+
-|              |         | 51u         | ✔      | ✖    | ✖         | lpc_ip3511        |              |
-|              |         +-------------+--------+------+-----------+-------------------+--------------+
-|              |         | 54          | ✔      |      | ✔         | lpc_ip3511        |              |
-|              |         +-------------+--------+------+-----------+-------------------+--------------+
-|              |         | 55          | ✔      |      | ✔         | lpc_ip3511        |              |
-+--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
-| Raspberry Pi | RP2040                | ✔      | ✔    | ✖         | rp2040, pio_usb   |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Renesas      | RX 63N, 65N, 72N      | ✔      | ✔    | ✖         | usba              |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Silabs       | EFM32GG12             | ✔      |      | ✖         | dwc2              |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Sony         | CXD56                 | ✔      | ✖    | ✔         | cxd56             |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| ST STM32     | F0                    | ✔      | ✖    | ✖         | stm32_fsdev       |              |
-|              +----+------------------+--------+------+-----------+-------------------+--------------+
-|              | F1 | 102, 103         | ✔      | ✖    | ✖         | stm32_fsdev       |              |
-|              |    +------------------+--------+------+-----------+-------------------+--------------+
-|              |    | 105, 107         | ✔      |      | ✖         | dwc2              |              |
-|              +----+------------------+--------+------+-----------+-------------------+--------------+
-|              | F2                    | ✔      |      | ✔         | dwc2              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | F3                    | ✔      | ✖    | ✖         | stm32_fsdev       |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | F4                    | ✔      |      | ✔         | dwc2              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | F7                    | ✔      |      | ✔         | dwc2              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | H7                    | ✔      |      | ✔         | dwc2              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | G4                    | ✔      | ✖    | ✖         | stm32_fsdev       |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | L0, L1                | ✔      | ✖    | ✖         | stm32_fsdev       |              |
-|              +----+------------------+--------+------+-----------+-------------------+--------------+
-|              | L4 | 4x2, 4x3         | ✔      | ✖    | ✖         | stm32_fsdev       |              |
-|              |    +------------------+--------+------+-----------+-------------------+--------------+
-|              |    | 4x5, 4x6         | ✔      |      |           | dwc2              |              |
-|              +----+------------------+--------+------+-----------+-------------------+--------------+
-|              | L4+                   | ✔      |      |           | dwc2              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | U5                    | ⚠      |      |           | dwc2              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | WBx5                  | ✔      |      |           | stm32_fsdev       |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| TI           | MSP430                | ✔      | ✖    | ✖         | msp430x5xx        |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | MSP432E4              | ✔      |      | ✖         | musb              |              |
-|              +-----------------------+--------+------+-----------+-------------------+--------------+
-|              | TM4C123               | ✔      |      | ✖         | musb              |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| ValentyUSB   | eptri                 | ✔      | ✖    | ✖         | eptri             |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-
-
-Table Legend
-------------
-
-= ===================
-✔ Supported
-⚠ WIP/partial support
-✖ Not supported
-= ===================
-
-Supported Boards
-================
-
-The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project. It is responsible for getting the MCU started and the USB peripheral clocked with minimal of on-board devices
-
--  One LED : for status
--  One Button : to get input from user
--  One UART : optional for device, but required for host examples
-
-The following boards are supported (sorted alphabetically):
-
-Broadcom
---------
-
--  `Raspberry Pi CM4 <https://www.raspberrypi.com/products/compute-module-4>`__
-
-Dialog DA146xx
---------------
-
--  `DA14695 Development Kit – USB <https://www.dialog-semiconductor.com/products/da14695-development-kit-usb>`__
--  `DA1469x Development Kit – Pro <https://www.dialog-semiconductor.com/products/da14695-development-kit-pro>`__
-
-Espressif ESP32-S2
-------------------
-
--  `Adafruit Feather ESP32-S2 <https://www.adafruit.com/product/5000>`__
--  `Adafruit Magtag 2.9" E-Ink WiFi Display <https://www.adafruit.com/product/4800>`__
--  `Adafruit Metro ESP32-S2 <https://www.adafruit.com/product/4775>`__
--  `ESP32-S2-Kaluga-1 <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit.html>`__
--  `ESP32-S2-Saola-1 <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html>`__
-
-GigaDevice
-----------
-
--  `Sipeed Longan Nano <https://longan.sipeed.com/en/>`__
-
-Infineon
----------
-
-XMC4000
-^^^^^^^
-
--  `XMC4500 Relax (Lite) Kit <https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc45_relax_lite_v1/>`__
-
-MicroChip
----------
-
-SAMD11 & SAMD21
-^^^^^^^^^^^^^^^
-
--  `Adafruit Circuit Playground Express <https://www.adafruit.com/product/3333>`__
--  `Adafruit Feather M0 Express <https://www.adafruit.com/product/3403>`__
--  `Adafruit ItsyBitsy M0 Express <https://www.adafruit.com/product/3727>`__
--  `Adafruit Metro M0 Express <https://www.adafruit.com/product/3505>`__
--  `Great Scott Gadgets LUNA <https://greatscottgadgets.com/luna/>`__
--  `Microchip SAMD11 Xplained Pro <https://www.microchip.com/developmenttools/ProductDetails/atsamd11-xpro>`__
--  `Microchip SAMD21 Xplained Pro <https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMD21-XPRO>`__
--  `Seeeduino Xiao <https://www.seeedstudio.com/Seeeduino-XIAO-Arduino-Microcontroller-SAMD21-Cortex-M0+-p-4426.html>`__
-
-SAMD51 & SAME54
-^^^^^^^^^^^^^^^
-
--  `Adafruit Feather M4 Express <https://www.adafruit.com/product/3857>`__
--  `Adafruit ItsyBitsy M4 Express <https://www.adafruit.com/product/3800>`__
--  `Adafruit PyBadge <https://www.adafruit.com/product/4200>`__
--  `Adafruit PyPortal <https://www.adafruit.com/product/4116>`__
--  `Adafruit Metro M4 Express <https://www.adafruit.com/product/3382>`__
--  `D5035-01 <https://github.com/RudolphRiedel/USB_CAN-FD>`__
--  `Microchip SAME54 Xplained Pro <https://www.microchip.com/developmenttools/productdetails/atsame54-xpro>`__
-
-SAME7x
-^^^^^^
-
-- `Microchip SAME70 Xplained <https://www.microchip.com/en-us/development-tool/ATSAME70-XPLD>`_
-- `QMTECH ATSAME70N19 <https://www.aliexpress.com/item/1005003173783268.html>`_
-
-SAMG
-^^^^
-
--  `Microchip SAMG55 Xplained Pro <https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMG55-XPRO>`__
-
-SAML2x
-^^^^^^
-
--  `SAML21 Xplaind Pro <https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAML21-XPRO-B>`__
--  `SAML22 Feather <https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather>`__
--  `Sensor Watch <https://github.com/joeycastillo/Sensor-Watch>`__
-
-Nordic nRF5x
-------------
-
--  `Adafruit Circuit Playground Bluefruit <https://www.adafruit.com/product/4333>`__
--  `Adafruit CLUE <https://www.adafruit.com/product/4500>`__
--  `Adafruit Feather nRF52840 Express <https://www.adafruit.com/product/4062>`__
--  `Adafruit Feather nRF52840 Sense <https://www.adafruit.com/product/4516>`__
--  `Adafruit ItsyBitsy nRF52840 Express <https://www.adafruit.com/product/4481>`__
--  `Arduino Nano 33 BLE <https://store.arduino.cc/usa/nano-33-ble>`__
--  `Arduino Nano 33 BLE Sense <https://store.arduino.cc/usa/nano-33-ble-sense>`__
--  `Maker Diary nRF52840 MDK Dongle <https://wiki.makerdiary.com/nrf52840-mdk-usb-dongle>`__
--  `Nordic nRF52840 Development Kit (aka pca10056) <https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK>`__
--  `Nordic nRF52840 Dongle (aka pca10059) <https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle>`__
--  `Nordic nRF52833 Development Kit (aka pca10100) <https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK>`__
--  `Raytac MDBT50Q-RX Dongle <https://www.raytac.com/product/ins.php?index_id=89>`__
-
-Nuvoton
--------
-
--  NuTiny SDK NUC120
--  `NuTiny NUC121S <https://direct.nuvoton.com/en/nutiny-nuc121s>`__
--  `NuTiny NUC125S <https://direct.nuvoton.com/en/nutiny-nuc125s>`__
--  `NuTiny NUC126V <https://direct.nuvoton.com/en/nutiny-nuc126v>`__
--  `NuTiny SDK NUC505Y <https://direct.nuvoton.com/en/nutiny-nuc505y>`__
-
-NXP
----
-
-iMX RT
-^^^^^^
-
--  `MIMX RT1010 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1010-evaluation-kit:MIMXRT1010-EVK>`__
--  `MIMX RT1015 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1015-evaluation-kit:MIMXRT1015-EVK>`__
--  `MIMX RT1020 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1020-evaluation-kit:MIMXRT1020-EVK>`__
--  `MIMX RT1050 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK>`__
--  `MIMX RT1060 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1060-evk-i.mx-rt1060-evaluation-kit:MIMXRT1060-EVK>`__
--  `MIMX RT1064 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK>`__
--  `Teensy 4.0 Development Board <https://www.pjrc.com/store/teensy40.html>`__
--  `Teensy 4.1 Development Board <https://www.pjrc.com/store/teensy41.html>`__
-
-Kinetis
-^^^^^^^
-
--  `Freedom FRDM-KL25Z <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z>`__
--  `Freedom FRDM-K32L2B3 <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3>`__
--  `KUIIC <https://github.com/nxf58843/kuiic>`__
-
-LPC 11-13-15
-^^^^^^^^^^^^
-
--  `LPCXpresso 11u37 <https://www.nxp.com/design/microcontrollers-developer-resources/lpcxpresso-boards/lpcxpresso-board-for-lpc11u37h:OM13074>`__
--  `LPCXpresso 11u68 <https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc11u68:OM13058>`__
--  `LPCXpresso 1347 <https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1347:OM13045>`__
--  `LPCXpresso 1549 <https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1500-cortex-m3/lpcxpresso-board-for-lpc1549:OM13056>`__
-
-LPC 17-40
-^^^^^^^^^
-
--  `ARM mbed LPC1768 <https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-cortex-m3/arm-mbed-lpc1768-board:OM11043>`__
--  `Embedded Artists LPC4088 Quick Start board <https://www.embeddedartists.com/products/lpc4088-quickstart-board>`__
--  `LPCXpresso 1769 <https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1769:OM13000>`__
-
-LPC 18-43
-^^^^^^^^^
-
--  `Embedded Artists LPC4357 Developer Kit <http://www.embeddedartists.com/products/kits/lpc4357_kit.php>`__
--  `Keil MCB1800 Evaluation Board <http://www.keil.com/mcb1800>`__
--  `LPCXpresso18S37 Development Board <https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc4000-cortex-m4/lpcxpresso18s37-development-board:OM13076>`__
--  `NGX LPC4330-Xplorer <https://www.nxp.com/design/designs/lpc4330-xplorer-board:OM13027>`__
-
-LPC 51
-^^^^^^
-
--  `LPCXpresso 51U68 <https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005>`__
-
-LPC 54
-^^^^^^
-
--  `LPCXpresso 54114 <https://www.nxp.com/design/microcontrollers-developer-resources/lpcxpresso-boards/lpcxpresso54114-board:OM13089>`__
-
-LPC55
-^^^^^
-
--  `Double M33 Express <https://www.crowdsupply.com/steiert-solutions/double-m33-express>`__
--  `LPCXpresso 55s28 EVK <https://www.nxp.com/design/software/development-software/lpcxpresso55s28-development-board:LPC55S28-EVK>`__
--  `LPCXpresso 55s69 EVK <https://www.nxp.com/design/development-boards/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK>`__
--  `MCU-Link <https://www.nxp.com/design/development-boards/lpcxpresso-boards/mcu-link-debug-probe:MCU-LINK>`__
-
-Renesas RX
-----------
-
--  `GR-CITRUS <https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-citrus>`__
--  `Renesas RX65N Target Board <https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n>`__
-
-Raspberry Pi RP2040
--------------------
-
--  `Adafruit Feather RP2040 <https://www.adafruit.com/product/4884>`__
--  `Adafruit ItsyBitsy RP2040 <https://www.adafruit.com/product/4888>`__
--  `Adafruit QT Py RP2040 <https://www.adafruit.com/product/4900>`__
--  `Raspberry Pi Pico <https://www.raspberrypi.org/products/raspberry-pi-pico/>`__
-
-Silabs
-------
-
--  `EFM32GG12 Thunderboard Kit (SLTB009A) <https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit>`__
-
-Sony
-----
-
--  `Sony Spresense CXD5602 <https://developer.sony.com/develop/spresense>`__
-
-ST STM32
---------
-
-F0
-^^
--  `STM32 F070rb Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f070rb.html>`__
--  `STM32 F072 Evaluation <https://www.st.com/en/evaluation-tools/stm32072b-eval.html>`__
--  `STM32 F072rb Discovery <https://www.st.com/en/evaluation-tools/32f072bdiscovery.html>`__
-
-F1
-^^
--  `STM32 F103c8 Blue Pill <https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill>`__
--  `STM32 F103rc Mini v2.0 <https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0>`__
-
-F2
-^^
--  `STM32 F207zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f207zg.html>`__
-
-F3
-^^
--  `STM32 F303vc Discovery <https://www.st.com/en/evaluation-tools/stm32f3discovery.html>`__
-
-F4
-^^
--  `Adafruit Feather STM32F405 <https://www.adafruit.com/product/4382>`__
--  `Micro Python PyBoard v1.1 <https://store.micropython.org/product/PYBv1.1>`__
--  `STM32 F401cc Black Pill <https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2>`__
--  `STM32 F407vg Discovery <https://www.st.com/en/evaluation-tools/stm32f4discovery.html>`__
--  `STM32 F411ce Black Pill <https://www.adafruit.com/product/4877>`__
--  `STM32 F411ve Discovery <https://www.st.com/en/evaluation-tools/32f411ediscovery.html>`__
--  `STM32 F412zg Discovery <https://www.st.com/en/evaluation-tools/32f412gdiscovery.html>`__
--  `STM32 F412zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f412zg.html>`__
--  `STM32 F439zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f439zi.html>`__
-
-F7
-^^
-
--  `STLink-V3 Mini <https://www.st.com/en/development-tools/stlink-v3mini.html>`__
--  `STM32 F723e Discovery <https://www.st.com/en/evaluation-tools/32f723ediscovery.html>`__
--  `STM32 F746zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f746zg.html>`__
--  `STM32 F746g Discovery <https://www.st.com/en/evaluation-tools/32f746gdiscovery.html>`__
--  `STM32 F767zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f767zi.html>`__
--  `STM32 F769i Discovery <https://www.st.com/en/evaluation-tools/32f769idiscovery.html>`__
-
-H7
-^^
--  `STM32 H743zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-h743zi.html>`__
--  `STM32 H743i Evaluation <https://www.st.com/en/evaluation-tools/stm32h743i-eval.html>`__
--  `STM32 H745i Discovery <https://www.st.com/en/evaluation-tools/stm32h745i-disco.html>`__
--  `Waveshare OpenH743I-C <https://www.waveshare.com/openh743i-c-standard.htm>`__
-
-G4
-^^
--  `STM32 G474RE Nucleo <https://www.st.com/en/evaluation-tools/nucleo-g474re.html>`__
-
-L0
-^^
--  `STM32 L035c8 Discovery <https://www.st.com/en/evaluation-tools/32l0538discovery.html>`__
-
-L4
-^^
--  `STM32 L476vg Discovery <https://www.st.com/en/evaluation-tools/32l476gdiscovery.html>`__
--  `STM32 L4P5zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html>`__
--  `STM32 L4R5zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html>`__
-
-WB
-^^
--  `STM32 WB55 Nucleo <https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html>`__
-
-TI
---
-
--  `MSP430F5529 USB LaunchPad Evaluation Kit <http://www.ti.com/tool/MSP-EXP430F5529LP>`__
--  `MSP-EXP432E401Y LaunchPad Evaluation Kit <https://www.ti.com/tool/MSP-EXP432E401Y>`__
--  `TM4C123GXL LaunchPad Evaluation Kit <https://www.ti.com/tool/EK-TM4C123GXL>`__
-
-Tomu
-----
-
--  `Fomu <https://www.crowdsupply.com/sutajio-kosagi/fomu>`__
diff --git a/docs/requirements.txt b/docs/requirements.txt
index 15022e147..ad5c89922 100644
--- a/docs/requirements.txt
+++ b/docs/requirements.txt
@@ -1,4 +1,4 @@
-sphinx~=3.0
+sphinx>=5.0
 furo>=2020.12.30.b24
 sphinx-autodoc-typehints>=1.10
-jinja2==3.0.3
+jinja2>=3.0.3
diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt
new file mode 100644
index 000000000..d34c6ed5d
--- /dev/null
+++ b/examples/CMakeLists.txt
@@ -0,0 +1,11 @@
+cmake_minimum_required(VERSION 3.20)
+
+#set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake)
+
+project(tinyusb_examples C CXX ASM)
+
+add_subdirectory(device)
+add_subdirectory(dual)
+add_subdirectory(host)
+add_subdirectory(typec)
diff --git a/examples/build_system/cmake/cpu/arm1176jzf-s.cmake b/examples/build_system/cmake/cpu/arm1176jzf-s.cmake
new file mode 100644
index 000000000..8029e3987
--- /dev/null
+++ b/examples/build_system/cmake/cpu/arm1176jzf-s.cmake
@@ -0,0 +1,21 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mcpu=arm1176jzf-s
+    -ffreestanding
+  )
+  # set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=arm1176jzf-s
+    -mfpu=none
+    -mfloat-abi=soft
+    -ffreestanding
+  )
+  #set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/arm926ej-s.cmake b/examples/build_system/cmake/cpu/arm926ej-s.cmake
new file mode 100644
index 000000000..c19b9f8a8
--- /dev/null
+++ b/examples/build_system/cmake/cpu/arm926ej-s.cmake
@@ -0,0 +1,21 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mcpu=arm926ej-s
+    -ffreestanding
+    )
+  # set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=arm926ej-s
+    -mfpu=none
+    -mfloat-abi=soft
+    -ffreestanding
+    )
+  #set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-a53.cmake b/examples/build_system/cmake/cpu/cortex-a53.cmake
new file mode 100644
index 000000000..dde8c0a0c
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-a53.cmake
@@ -0,0 +1,17 @@
+if (TOOLCHAIN STREQUAL "gcc")
+	set(TOOLCHAIN_COMMON_FLAGS
+		-mcpu=cortex-a53
+		)
+	# set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+	set(TOOLCHAIN_COMMON_FLAGS
+		--target=arm-none-eabi
+		-mcpu=cortex-a53
+		)
+	#set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+	message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-a72.cmake b/examples/build_system/cmake/cpu/cortex-a72.cmake
new file mode 100644
index 000000000..a44324234
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-a72.cmake
@@ -0,0 +1,17 @@
+if (TOOLCHAIN STREQUAL "gcc")
+	set(TOOLCHAIN_COMMON_FLAGS
+		-mcpu=cortex-a72
+		)
+	# set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+	set(TOOLCHAIN_COMMON_FLAGS
+		--target=arm-none-eabi
+		-mcpu=cortex-a72
+		)
+	#set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+	message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m0.cmake b/examples/build_system/cmake/cpu/cortex-m0.cmake
new file mode 100644
index 000000000..62019d90d
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m0.cmake
@@ -0,0 +1,22 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m0plus
+    -mfloat-abi=soft
+    )
+  set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m0
+    )
+  set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m0
+    )
+  set(FREERTOS_PORT IAR_ARM_CM0 CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m0plus.cmake b/examples/build_system/cmake/cpu/cortex-m0plus.cmake
new file mode 100644
index 000000000..ddf0f16af
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m0plus.cmake
@@ -0,0 +1,22 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m0plus
+    -mfloat-abi=soft
+    )
+  set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m0plus
+    )
+  set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m0
+    )
+  set(FREERTOS_PORT IAR_ARM_CM0 CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m23.cmake b/examples/build_system/cmake/cpu/cortex-m23.cmake
new file mode 100644
index 000000000..00382ed9b
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m23.cmake
@@ -0,0 +1,22 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m23
+    -mfloat-abi=soft
+    )
+  set(FREERTOS_PORT GCC_ARM_CM23_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m23
+    )
+  set(FREERTOS_PORT GCC_ARM_CM23_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m23
+    )
+  set(FREERTOS_PORT IAR_ARM_CM23_NTZ_NONSECURE CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m3.cmake b/examples/build_system/cmake/cpu/cortex-m3.cmake
new file mode 100644
index 000000000..27888604e
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m3.cmake
@@ -0,0 +1,21 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m3
+    )
+  set(FREERTOS_PORT GCC_ARM_CM3 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m3
+    )
+  set(FREERTOS_PORT GCC_ARM_CM3 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m3
+    )
+  set(FREERTOS_PORT IAR_ARM_CM3 CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake b/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake
new file mode 100644
index 000000000..51fd70b0e
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake
@@ -0,0 +1,18 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m33+nodsp
+    -mfloat-abi=soft
+    )
+  set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  message(FATAL_ERROR "Clang is not supported for this target")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m33+nodsp
+    )
+  set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m33-nodsp.cmake b/examples/build_system/cmake/cpu/cortex-m33-nodsp.cmake
new file mode 100644
index 000000000..b3cd743fd
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m33-nodsp.cmake
@@ -0,0 +1,25 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m33+nodsp
+    -mfloat-abi=hard
+    -mfpu=fpv5-sp-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m33+nodsp
+    -mfpu=fpv5-sp-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m33+nodsp
+    --fpu VFPv5-SP
+    )
+  set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m33.cmake b/examples/build_system/cmake/cpu/cortex-m33.cmake
new file mode 100644
index 000000000..d56d07ebc
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m33.cmake
@@ -0,0 +1,25 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m33
+    -mfloat-abi=hard
+    -mfpu=fpv5-sp-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m33
+    -mfpu=fpv5-sp-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m33
+    --fpu VFPv5-SP
+    )
+  set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m4.cmake b/examples/build_system/cmake/cpu/cortex-m4.cmake
new file mode 100644
index 000000000..9cdadc6f8
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m4.cmake
@@ -0,0 +1,32 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m4
+    -mfloat-abi=hard
+    -mfpu=fpv4-sp-d16
+    )
+  if (NOT DEFINED FREERTOS_PORT)
+    set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
+  endif ()
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m4
+    -mfpu=fpv4-sp-d16
+    )
+  if (NOT DEFINED FREERTOS_PORT)
+    set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
+  endif ()
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m4
+    --fpu VFPv4_sp
+    )
+
+  if (NOT DEFINED FREERTOS_PORT)
+    set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
+  endif ()
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m7-fpsp.cmake b/examples/build_system/cmake/cpu/cortex-m7-fpsp.cmake
new file mode 100644
index 000000000..b10f00fc2
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m7-fpsp.cmake
@@ -0,0 +1,25 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m7
+    -mfloat-abi=hard
+    -mfpu=fpv5-sp-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m7
+    -mfpu=fpv5-sp-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m7
+    --fpu VFPv5_sp
+    )
+  set(FREERTOS_PORT IAR_ARM_CM7 CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m7.cmake b/examples/build_system/cmake/cpu/cortex-m7.cmake
new file mode 100644
index 000000000..b41dfded5
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m7.cmake
@@ -0,0 +1,25 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m7
+    -mfloat-abi=hard
+    -mfpu=fpv5-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m7
+    -mfpu=fpv5-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m7
+    --fpu VFPv5_D16
+    )
+  set(FREERTOS_PORT IAR_ARM_CM7 CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m85.cmake b/examples/build_system/cmake/cpu/cortex-m85.cmake
new file mode 100644
index 000000000..30314acbc
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m85.cmake
@@ -0,0 +1,25 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m85
+    -mfloat-abi=hard
+    -mfpu=fpv5-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m85
+    -mfpu=fpv5-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m85
+    --fpu VFPv5_D16
+    )
+  set(FREERTOS_PORT IAR_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/msp430.cmake b/examples/build_system/cmake/cpu/msp430.cmake
new file mode 100644
index 000000000..584ec5741
--- /dev/null
+++ b/examples/build_system/cmake/cpu/msp430.cmake
@@ -0,0 +1,10 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(FREERTOS_PORT GCC_MSP430F449 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  message(FATAL_ERROR "Clang is not supported for this target")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(FREERTOS_PORT IAR_MSP430 CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/rv32i-ilp32.cmake b/examples/build_system/cmake/cpu/rv32i-ilp32.cmake
new file mode 100644
index 000000000..605c40ba1
--- /dev/null
+++ b/examples/build_system/cmake/cpu/rv32i-ilp32.cmake
@@ -0,0 +1,19 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -march=rv32i_zicsr
+    -mabi=ilp32
+    )
+  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -march=rv32i_zicsr
+    -mabi=ilp32
+    )
+  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  message(FATAL_ERROR "IAR not supported")
+  set(FREERTOS_PORT IAR_RISC_V CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake b/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
new file mode 100644
index 000000000..584d90519
--- /dev/null
+++ b/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
@@ -0,0 +1,18 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -march=rv32imac_zicsr
+    -mabi=ilp32
+    )
+  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -march=rv32imac_zicsr
+    -mabi=ilp32
+    )
+  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  message(FATAL_ERROR "IAR not supported")
+  set(FREERTOS_PORT IAR_RISC_V CACHE INTERNAL "")
+endif ()
diff --git a/examples/build_system/cmake/toolchain/aarch64_gcc.cmake b/examples/build_system/cmake/toolchain/aarch64_gcc.cmake
new file mode 100644
index 000000000..ac1e482eb
--- /dev/null
+++ b/examples/build_system/cmake/toolchain/aarch64_gcc.cmake
@@ -0,0 +1,21 @@
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER "aarch64-none-elf-gcc")
+endif ()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+  set(CMAKE_CXX_COMPILER "aarch64-none-elf-g++")
+endif ()
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
+find_program(CMAKE_SIZE aarch64-none-elf-size)
+find_program(CMAKE_OBJCOPY aarch64-none-elf-objcopy)
+find_program(CMAKE_OBJDUMP aarch64-none-elf-objdump)
+
+include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)
+
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+if (IS_IN_TRY_COMPILE)
+  set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+  set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+  cmake_print_variables(CMAKE_C_LINK_FLAGS)
+endif ()
diff --git a/examples/build_system/cmake/toolchain/arm_clang.cmake b/examples/build_system/cmake/toolchain/arm_clang.cmake
new file mode 100644
index 000000000..fe3c2b453
--- /dev/null
+++ b/examples/build_system/cmake/toolchain/arm_clang.cmake
@@ -0,0 +1,21 @@
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER "clang")
+endif ()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+  set(CMAKE_CXX_COMPILER "clang++")
+endif ()
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
+find_program(CMAKE_SIZE llvm-size)
+find_program(CMAKE_OBJCOPY llvm-objcopy)
+find_program(CMAKE_OBJDUMP llvm-objdump)
+
+include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)
+
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+if (IS_IN_TRY_COMPILE)
+  set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+  set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+  cmake_print_variables(CMAKE_C_LINK_FLAGS)
+endif ()
diff --git a/examples/build_system/cmake/toolchain/arm_gcc.cmake b/examples/build_system/cmake/toolchain/arm_gcc.cmake
new file mode 100644
index 000000000..6a660e259
--- /dev/null
+++ b/examples/build_system/cmake/toolchain/arm_gcc.cmake
@@ -0,0 +1,25 @@
+if (RTOS STREQUAL zephyr)
+  return()
+endif ()
+
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER "arm-none-eabi-gcc")
+endif ()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+  set(CMAKE_CXX_COMPILER "arm-none-eabi-g++")
+endif ()
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
+find_program(CMAKE_SIZE arm-none-eabi-size)
+find_program(CMAKE_OBJCOPY arm-none-eabi-objcopy)
+find_program(CMAKE_OBJDUMP arm-none-eabi-objdump)
+
+include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)
+
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+if (IS_IN_TRY_COMPILE)
+  set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+  set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+  cmake_print_variables(CMAKE_C_LINK_FLAGS)
+endif ()
diff --git a/examples/build_system/cmake/toolchain/arm_iar.cmake b/examples/build_system/cmake/toolchain/arm_iar.cmake
new file mode 100644
index 000000000..083815715
--- /dev/null
+++ b/examples/build_system/cmake/toolchain/arm_iar.cmake
@@ -0,0 +1,17 @@
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER "iccarm")
+endif()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+  set(CMAKE_CXX_COMPILER "iccarm")
+endif()
+
+if (NOT DEFINED CMAKE_ASM_COMPILER)
+  set(CMAKE_ASM_COMPILER "iasmarm")
+endif()
+
+find_program(CMAKE_SIZE size)
+find_program(CMAKE_OBJCOPY ielftool)
+find_program(CMAKE_OBJDUMP iefdumparm)
+
+include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)
diff --git a/examples/build_system/cmake/toolchain/common.cmake b/examples/build_system/cmake/toolchain/common.cmake
new file mode 100644
index 000000000..4c181137b
--- /dev/null
+++ b/examples/build_system/cmake/toolchain/common.cmake
@@ -0,0 +1,65 @@
+include(CMakePrintHelpers)
+
+# ----------------------------------------------------------------------------
+# Common
+# ----------------------------------------------------------------------------
+set(CMAKE_SYSTEM_NAME Generic)
+set(CMAKE_SYSTEM_PROCESSOR ${CMAKE_SYSTEM_CPU})
+set_property(GLOBAL PROPERTY TARGET_SUPPORTS_SHARED_LIBS FALSE)
+
+# Look for includes and libraries only in the target system prefix.
+set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+
+# pass TOOLCHAIN_CPU to
+set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_PROCESSOR CMAKE_SYSTEM_CPU)
+include(${CMAKE_CURRENT_LIST_DIR}/../cpu/${CMAKE_SYSTEM_CPU}.cmake)
+
+# ----------------------------------------------------------------------------
+# Compile flags
+# ----------------------------------------------------------------------------
+if (TOOLCHAIN STREQUAL "gcc")
+  list(APPEND TOOLCHAIN_COMMON_FLAGS
+    -fdata-sections
+    -ffunction-sections
+    -fsingle-precision-constant
+    -fno-strict-aliasing
+    )
+  list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
+    -Wl,--print-memory-usage
+    -Wl,--gc-sections
+    -Wl,--cref
+    )
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  #list(APPEND TOOLCHAIN_COMMON_FLAGS)
+  list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
+    --diag_suppress=Li065
+    )
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  list(APPEND TOOLCHAIN_COMMON_FLAGS
+    -fdata-sections
+    -ffunction-sections
+    -fno-strict-aliasing
+    )
+  list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
+    -Wl,--print-memory-usage
+    -Wl,--gc-sections
+    -Wl,--cref
+    )
+endif ()
+
+# join the toolchain flags into a single string
+list(JOIN TOOLCHAIN_COMMON_FLAGS " " TOOLCHAIN_COMMON_FLAGS)
+foreach (LANG IN ITEMS C CXX ASM)
+  set(CMAKE_${LANG}_FLAGS_INIT ${TOOLCHAIN_COMMON_FLAGS})
+  # optimization flags for LOG, LOGGER ?
+  #set(CMAKE_${LANG}_FLAGS_RELEASE_INIT "-Os")
+  #set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0")
+endforeach ()
+
+# Linker
+list(JOIN TOOLCHAIN_EXE_LINKER_FLAGS " " CMAKE_EXE_LINKER_FLAGS_INIT)
diff --git a/examples/build_system/cmake/toolchain/msp430_gcc.cmake b/examples/build_system/cmake/toolchain/msp430_gcc.cmake
new file mode 100644
index 000000000..799518931
--- /dev/null
+++ b/examples/build_system/cmake/toolchain/msp430_gcc.cmake
@@ -0,0 +1,15 @@
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER "msp430-elf-gcc")
+endif ()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+  set(CMAKE_CXX_COMPILER "msp430-elf-g++")
+endif ()
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
+
+find_program(CMAKE_SIZE msp430-elf-size)
+find_program(CMAKE_OBJCOPY msp430-elf-objcopy)
+find_program(CMAKE_OBJDUMP msp430-elf-objdump)
+
+include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)
diff --git a/examples/build_system/cmake/toolchain/riscv_gcc.cmake b/examples/build_system/cmake/toolchain/riscv_gcc.cmake
new file mode 100644
index 000000000..60a24528b
--- /dev/null
+++ b/examples/build_system/cmake/toolchain/riscv_gcc.cmake
@@ -0,0 +1,30 @@
+# default Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+if (NOT DEFINED CROSS_COMPILE)
+  set(CROSS_COMPILE "riscv-none-elf-")
+endif ()
+
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
+endif ()
+
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
+endif ()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+  set(CMAKE_CXX_COMPILER ${CROSS_COMPILE}g++)
+endif ()
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
+find_program(CMAKE_SIZE ${CROSS_COMPILE}size)
+find_program(CMAKE_OBJCOPY ${CROSS_COMPILE}objcopy)
+find_program(CMAKE_OBJDUMP ${CROSS_COMPILE}objdump)
+
+include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)
+
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+if (IS_IN_TRY_COMPILE)
+  set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+  set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+  cmake_print_variables(CMAKE_C_LINK_FLAGS)
+endif ()
diff --git a/examples/build_system/make/cpu/arm1176jzf-s.mk b/examples/build_system/make/cpu/arm1176jzf-s.mk
new file mode 100644
index 000000000..022ccf7ad
--- /dev/null
+++ b/examples/build_system/make/cpu/arm1176jzf-s.mk
@@ -0,0 +1,9 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=arm1176jzf-s \
+
+else ifeq ($(TOOLCHAIN),iar)
+	#CFLAGS += --cpu cortex-a53
+	#ASFLAGS += --cpu cortex-a53
+
+endif
diff --git a/examples/build_system/make/cpu/arm926ej-s.mk b/examples/build_system/make/cpu/arm926ej-s.mk
new file mode 100644
index 000000000..5b84f514f
--- /dev/null
+++ b/examples/build_system/make/cpu/arm926ej-s.mk
@@ -0,0 +1,9 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=arm926ej-s \
+
+else ifeq ($(TOOLCHAIN),iar)
+	#CFLAGS += --cpu cortex-a53
+	#ASFLAGS += --cpu cortex-a53
+
+endif
diff --git a/examples/build_system/make/cpu/cortex-a53.mk b/examples/build_system/make/cpu/cortex-a53.mk
new file mode 100644
index 000000000..42e522ecf
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-a53.mk
@@ -0,0 +1,12 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=cortex-a53 \
+
+else ifeq ($(TOOLCHAIN),iar)
+	CFLAGS += \
+		--cpu cortex-a53 \
+
+	ASFLAGS += \
+		--cpu cortex-a53 \
+
+endif
diff --git a/examples/build_system/make/cpu/cortex-a72.mk b/examples/build_system/make/cpu/cortex-a72.mk
new file mode 100644
index 000000000..1b3d8da4a
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-a72.mk
@@ -0,0 +1,12 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=cortex-a72 \
+
+else ifeq ($(TOOLCHAIN),iar)
+	CFLAGS += \
+		--cpu cortex-a72 \
+
+	ASFLAGS += \
+		--cpu cortex-a72 \
+
+endif
diff --git a/examples/build_system/make/cpu/cortex-m0.mk b/examples/build_system/make/cpu/cortex-m0.mk
new file mode 100644
index 000000000..c2c33a2ee
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m0.mk
@@ -0,0 +1,22 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m0 \
+    -mfloat-abi=soft \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m0 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  # IAR Flags
+  CFLAGS += --cpu cortex-m0
+  ASFLAGS += --cpu cortex-m0
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/examples/build_system/make/cpu/cortex-m0plus.mk b/examples/build_system/make/cpu/cortex-m0plus.mk
new file mode 100644
index 000000000..fe8feb227
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m0plus.mk
@@ -0,0 +1,22 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m0plus \
+    -mfloat-abi=soft \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m0plus \
+
+else ifeq ($(TOOLCHAIN),iar)
+  # IAR Flags
+  CFLAGS += --cpu cortex-m0+
+  ASFLAGS += --cpu cortex-m0+
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/examples/build_system/make/cpu/cortex-m23.mk b/examples/build_system/make/cpu/cortex-m23.mk
new file mode 100644
index 000000000..7ab758352
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m23.mk
@@ -0,0 +1,22 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m23 \
+    -mfloat-abi=soft \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m23 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  # IAR Flags
+  CFLAGS += --cpu cortex-m23
+  ASFLAGS += --cpu cortex-m23
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM23
diff --git a/examples/build_system/make/cpu/cortex-m3.mk b/examples/build_system/make/cpu/cortex-m3.mk
new file mode 100644
index 000000000..b6325313f
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m3.mk
@@ -0,0 +1,22 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m3 \
+    -mfloat-abi=soft \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m3 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  # IAR Flags
+  CFLAGS += --cpu cortex-m3
+  ASFLAGS += --cpu cortex-m3
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/examples/build_system/make/cpu/cortex-m33-nodsp-nofp.mk b/examples/build_system/make/cpu/cortex-m33-nodsp-nofp.mk
new file mode 100644
index 000000000..405053dd0
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m33-nodsp-nofp.mk
@@ -0,0 +1,24 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+	-mthumb \
+	-mcpu=cortex-m33+nodsp \
+	-mfloat-abi=soft \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m33 \
+	  -mfpu=softvp \
+
+else ifeq ($(TOOLCHAIN),iar)
+  CFLAGS += \
+		--cpu cortex-m33+nodsp \
+
+  ASFLAGS += \
+		--cpu cortex-m33+nodsp \
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
diff --git a/examples/build_system/make/cpu/cortex-m33.mk b/examples/build_system/make/cpu/cortex-m33.mk
new file mode 100644
index 000000000..47b0eaecd
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m33.mk
@@ -0,0 +1,27 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m33 \
+    -mfloat-abi=hard \
+    -mfpu=fpv5-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m33 \
+	  -mfpu=fpv5-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  CFLAGS += \
+		--cpu cortex-m33 \
+		--fpu VFPv5-SP \
+
+  ASFLAGS += \
+		--cpu cortex-m33 \
+		--fpu VFPv5-SP \
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
diff --git a/examples/build_system/make/cpu/cortex-m4.mk b/examples/build_system/make/cpu/cortex-m4.mk
new file mode 100644
index 000000000..4e16819d1
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m4.mk
@@ -0,0 +1,22 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m4 \
+    -mfloat-abi=hard \
+    -mfpu=fpv4-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m4 \
+	  -mfpu=fpv4-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  CFLAGS += --cpu cortex-m4 --fpu VFPv4
+  ASFLAGS += --cpu cortex-m4 --fpu VFPv4
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
diff --git a/examples/build_system/make/cpu/cortex-m7-fpsp.mk b/examples/build_system/make/cpu/cortex-m7-fpsp.mk
new file mode 100644
index 000000000..cd42c6fb8
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m7-fpsp.mk
@@ -0,0 +1,27 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m7 \
+    -mfloat-abi=hard \
+    -mfpu=fpv5-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m7 \
+	  -mfpu=fpv5-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  CFLAGS += \
+  	--cpu cortex-m7 \
+  	--fpu VFPv5_sp \
+
+  ASFLAGS += \
+		--cpu cortex-m7 \
+		--fpu VFPv5_sp \
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
diff --git a/examples/build_system/make/cpu/cortex-m7.mk b/examples/build_system/make/cpu/cortex-m7.mk
new file mode 100644
index 000000000..3e6116179
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m7.mk
@@ -0,0 +1,27 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m7 \
+    -mfloat-abi=hard \
+    -mfpu=fpv5-d16 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m7 \
+	  -mfpu=fpv5-d16 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  CFLAGS += \
+  	--cpu cortex-m7 \
+  	--fpu VFPv5_D16 \
+
+  ASFLAGS += \
+		--cpu cortex-m7 \
+		--fpu VFPv5_D16 \
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
diff --git a/examples/build_system/make/cpu/cortex-m85.mk b/examples/build_system/make/cpu/cortex-m85.mk
new file mode 100644
index 000000000..75e8f3aaf
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m85.mk
@@ -0,0 +1,27 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m85 \
+    -mfloat-abi=hard \
+    -mfpu=fpv5-d16 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m85 \
+	  -mfpu=fpv5-d16 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  CFLAGS += \
+  	--cpu cortex-m85 \
+  	--fpu VFPv5_D16 \
+
+  ASFLAGS += \
+		--cpu cortex-m85 \
+		--fpu VFPv5_D16 \
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM85_NTZ/non_secure
diff --git a/examples/build_system/make/cpu/msp430.mk b/examples/build_system/make/cpu/msp430.mk
new file mode 100644
index 000000000..6daa2c38d
--- /dev/null
+++ b/examples/build_system/make/cpu/msp430.mk
@@ -0,0 +1,12 @@
+ifeq ($(TOOLCHAIN),gcc)
+  # nothing to add
+else ifeq ($(TOOLCHAIN),clang)
+  # nothing to add
+else ifeq ($(TOOLCHAIN),iar)
+  # nothing to add
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/GCC_MSP430F449
diff --git a/examples/build_system/make/cpu/rv32i-ilp32.mk b/examples/build_system/make/cpu/rv32i-ilp32.mk
new file mode 100644
index 000000000..af764afc5
--- /dev/null
+++ b/examples/build_system/make/cpu/rv32i-ilp32.mk
@@ -0,0 +1,16 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -march=rv32i_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+    -march=rv32i_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  $(error not support)
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
diff --git a/examples/build_system/make/cpu/rv32imac-ilp32.mk b/examples/build_system/make/cpu/rv32imac-ilp32.mk
new file mode 100644
index 000000000..19c322ebc
--- /dev/null
+++ b/examples/build_system/make/cpu/rv32imac-ilp32.mk
@@ -0,0 +1,17 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -march=rv32imac_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+    -march=rv32imac_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  $(error not support)
+
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
diff --git a/examples/build_system/make/make.mk b/examples/build_system/make/make.mk
new file mode 100644
index 000000000..3101b66b9
--- /dev/null
+++ b/examples/build_system/make/make.mk
@@ -0,0 +1,190 @@
+# ---------------------------------------
+# Common make definition for all examples
+# ---------------------------------------
+
+#-------------------------------------------------------------
+# Toolchain
+# Can be changed via TOOLCHAIN=gcc|iar or CC=arm-none-eabi-gcc|iccarm|clang
+#-------------------------------------------------------------
+ifneq (,$(findstring clang,$(CC)))
+  TOOLCHAIN = clang
+else ifneq (,$(findstring iccarm,$(CC)))
+  TOOLCHAIN = iar
+else ifneq (,$(findstring gcc,$(CC)))
+  TOOLCHAIN = gcc
+endif
+
+# Default to GCC
+ifndef TOOLCHAIN
+  TOOLCHAIN = gcc
+endif
+
+#-------------- TOP and CURRENT_PATH ------------
+
+# Set TOP to be the path to get from the current directory (where make was invoked) to the top of the tree.
+# $(lastword $(MAKEFILE_LIST)) returns the name of this makefile relative to where make was invoked.
+THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
+
+# strip off /examples/build_system/make to get for example ../../..
+# and Set TOP to an absolute path
+TOP = $(abspath $(subst make.mk,../../..,$(THIS_MAKEFILE)))
+
+# Set CURRENT_PATH to the relative path from TOP to the current directory, ie examples/device/cdc_msc_freertos
+CURRENT_PATH = $(subst $(TOP)/,,$(abspath .))
+
+#-------------- Linux/Windows ------------
+
+# Detect whether shell style is windows or not
+# https://stackoverflow.com/questions/714100/os-detecting-makefile/52062069#52062069
+ifeq '$(findstring ;,$(PATH))' ';'
+# PATH contains semicolon - so we're definitely on Windows.
+CMDEXE := 1
+
+# makefile shell commands should use syntax for DOS CMD, not unix sh
+# Force DOS command shell on Windows.
+SHELL := cmd.exe
+endif
+
+ifeq ($(CMDEXE),1)
+  CP = copy
+  RM = del
+  MKDIR = mkdir
+  PYTHON = python
+else
+  CP = cp
+  RM = rm
+  MKDIR = mkdir
+  PYTHON = python3
+endif
+
+
+# Build directory
+BUILD := _build/$(BOARD)
+
+PROJECT := $(notdir $(CURDIR))
+BIN := $(TOP)/_bin/$(BOARD)/$(notdir $(CURDIR))
+
+#-------------------------------------------------------------
+# Board / Family
+#-------------------------------------------------------------
+
+# Board without family
+ifneq ($(wildcard $(TOP)/hw/bsp/$(BOARD)/board.mk),)
+  BOARD_PATH := hw/bsp/$(BOARD)
+  FAMILY :=
+endif
+
+# Board within family
+ifeq ($(BOARD_PATH),)
+  BOARD_PATH := $(subst $(TOP)/,,$(wildcard $(TOP)/hw/bsp/*/boards/$(BOARD)))
+  FAMILY := $(word 3, $(subst /, ,$(BOARD_PATH)))
+  FAMILY_PATH = hw/bsp/$(FAMILY)
+endif
+
+ifeq ($(BOARD_PATH),)
+  $(info You must provide a BOARD parameter with 'BOARD=')
+  $(error Invalid BOARD specified)
+endif
+
+ifeq ($(FAMILY),)
+  include $(TOP)/hw/bsp/$(BOARD)/board.mk
+else
+  # Include Family and Board specific defs
+  include $(TOP)/$(FAMILY_PATH)/family.mk
+  SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(FAMILY_PATH)/*.c))
+endif
+
+#-------------------------------------------------------------
+# Source files and compiler flags
+#-------------------------------------------------------------
+# tinyusb makefile
+include $(TOP)/src/tinyusb.mk
+SRC_C += $(TINYUSB_SRC_C)
+
+# Include all source C in family & board folder
+SRC_C += hw/bsp/board.c
+SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(BOARD_PATH)/*.c))
+
+INC += \
+  $(TOP)/$(FAMILY_PATH) \
+  $(TOP)/src \
+
+BOARD_UPPER = $(subst a,A,$(subst b,B,$(subst c,C,$(subst d,D,$(subst e,E,$(subst f,F,$(subst g,G,$(subst h,H,$(subst i,I,$(subst j,J,$(subst k,K,$(subst l,L,$(subst m,M,$(subst n,N,$(subst o,O,$(subst p,P,$(subst q,Q,$(subst r,R,$(subst s,S,$(subst t,T,$(subst u,U,$(subst v,V,$(subst w,W,$(subst x,X,$(subst y,Y,$(subst z,Z,$(subst -,_,$(BOARD))))))))))))))))))))))))))))
+CFLAGS += -DBOARD_$(BOARD_UPPER)
+
+ifdef CFLAGS_CLI
+	CFLAGS += $(CFLAGS_CLI)
+endif
+
+# use max3421 as host controller
+ifeq (${MAX3421_HOST},1)
+  SRC_C += src/portable/analog/max3421/hcd_max3421.c
+  CFLAGS += -DCFG_TUH_MAX3421=1
+  CMAKE_DEFSYM +=	-DMAX3421_HOST=1
+endif
+
+# Log level is mapped to TUSB DEBUG option
+ifneq ($(LOG),)
+  CMAKE_DEFSYM +=	-DLOG=$(LOG)
+  CFLAGS += -DCFG_TUSB_DEBUG=$(LOG)
+endif
+
+# Logger: default is uart, can be set to rtt or swo
+ifneq ($(LOGGER),)
+  CMAKE_DEFSYM +=	-DLOGGER=$(LOGGER)
+endif
+
+ifeq ($(LOGGER),rtt)
+  CFLAGS += -DLOGGER_RTT -DSEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
+  RTT_SRC = lib/SEGGER_RTT
+  INC   += $(TOP)/$(RTT_SRC)/RTT
+  SRC_C += $(RTT_SRC)/RTT/SEGGER_RTT.c
+else ifeq ($(LOGGER),swo)
+  CFLAGS += -DLOGGER_SWO
+endif
+
+# CPU specific flags
+ifdef CPU_CORE
+  include ${TOP}/examples/build_system/make/cpu/$(CPU_CORE).mk
+endif
+
+# toolchain specific
+include ${TOP}/examples/build_system/make/toolchain/arm_$(TOOLCHAIN).mk
+
+#---------------------- FreeRTOS -----------------------
+FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORTABLE_PATH = $(FREERTOS_SRC)/portable/$(if $(findstring iar,$(TOOLCHAIN)),IAR,GCC)
+
+ifeq ($(RTOS),freertos)
+	SRC_C += \
+		$(FREERTOS_SRC)/list.c \
+		$(FREERTOS_SRC)/queue.c \
+		$(FREERTOS_SRC)/tasks.c \
+		$(FREERTOS_SRC)/timers.c \
+		$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
+
+	SRC_S += $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
+	INC += \
+		$(TOP)/hw/bsp/$(FAMILY)/FreeRTOSConfig \
+		$(TOP)/$(FREERTOS_SRC)/include \
+		$(TOP)/$(FREERTOS_PORTABLE_SRC)
+
+	CFLAGS += -DCFG_TUSB_OS=OPT_OS_FREERTOS
+
+	# Suppress FreeRTOSConfig.h warnings
+	CFLAGS_GCC += -Wno-error=redundant-decls
+
+	# Suppress FreeRTOS source warnings
+	CFLAGS_GCC += -Wno-error=cast-qual
+
+	# FreeRTOS (lto + Os) linker issue
+	LDFLAGS_GCC += -Wl,--undefined=vTaskSwitchContext
+endif
+
+#---------------- Helper ----------------
+check_defined = \
+    $(strip $(foreach 1,$1, \
+    $(call __check_defined,$1,$(strip $(value 2)))))
+__check_defined = \
+    $(if $(value $1),, \
+    $(error Undefined make flag: $1$(if $2, ($2))))
diff --git a/examples/rules.mk b/examples/build_system/make/rules.mk
similarity index 55%
rename from examples/rules.mk
rename to examples/build_system/make/rules.mk
index c3134056a..86de17b6c 100644
--- a/examples/rules.mk
+++ b/examples/build_system/make/rules.mk
@@ -7,77 +7,7 @@
 
 # ---------------- GNU Make Start -----------------------
 # ESP32-Sx and RP2040 has its own CMake build system
-ifeq (,$(findstring $(FAMILY),esp32s2 esp32s3 rp2040))
-
-# ---------------------------------------
-# Compiler Flags
-# ---------------------------------------
-
-LIBS_GCC ?= -lgcc -lm -lnosys
-
-# libc
-LIBS += $(LIBS_GCC)
-
-ifneq ($(BOARD), spresense)
-LIBS += -lc
-endif
-
-# TinyUSB Stack source
-SRC_C += \
-	src/tusb.c \
-	src/common/tusb_fifo.c \
-	src/device/usbd.c \
-	src/device/usbd_control.c \
-	src/class/audio/audio_device.c \
-	src/class/cdc/cdc_device.c \
-	src/class/dfu/dfu_device.c \
-	src/class/dfu/dfu_rt_device.c \
-	src/class/hid/hid_device.c \
-	src/class/midi/midi_device.c \
-	src/class/msc/msc_device.c \
-	src/class/net/ecm_rndis_device.c \
-	src/class/net/ncm_device.c \
-	src/class/usbtmc/usbtmc_device.c \
-	src/class/video/video_device.c \
-	src/class/vendor/vendor_device.c
-
-# TinyUSB stack include
-INC += $(TOP)/src
-
-CFLAGS += $(addprefix -I,$(INC))
-
-# LTO makes it difficult to analyze map file for optimizing size purpose
-# We will run this option in ci
-ifeq ($(NO_LTO),1)
-CFLAGS := $(filter-out -flto,$(CFLAGS))
-endif
-
-ifneq ($(LD_FILE),)
-LDFLAGS_LD_FILE ?= -Wl,-T,$(TOP)/$(LD_FILE)
-endif
-
-LDFLAGS += $(CFLAGS) $(LDFLAGS_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections
-ifneq ($(SKIP_NANOLIB), 1)
-LDFLAGS += -specs=nosys.specs -specs=nano.specs
-endif
-
-ASFLAGS += $(CFLAGS)
-
-# Assembly files can be name with upper case .S, convert it to .s
-SRC_S := $(SRC_S:.S=.s)
-
-# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
-# assembly file should be placed first in linking order
-# '_asm' suffix is added to object of assembly file
-OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
-OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
-
-# Verbose mode
-ifeq ("$(V)","1")
-$(info CFLAGS  $(CFLAGS) ) $(info )
-$(info LDFLAGS $(LDFLAGS)) $(info )
-$(info ASFLAGS $(ASFLAGS)) $(info )
-endif
+ifeq (,$(findstring $(FAMILY),espressif rp2040))
 
 # ---------------------------------------
 # Rules
@@ -87,34 +17,40 @@ all: $(BUILD)/$(PROJECT).bin $(BUILD)/$(PROJECT).hex size
 
 uf2: $(BUILD)/$(PROJECT).uf2
 
+# We set vpath to point to the top of the tree so that the source files
+# can be located. By following this scheme, it allows a single build rule
+# to be used to compile all .c files.
+vpath %.c . $(TOP)
+vpath %.s . $(TOP)
+vpath %.S . $(TOP)
+
+include ${TOP}/examples/build_system/make/toolchain/$(TOOLCHAIN)_rules.mk
+
+# ---------------------------------------
+# Compiler Flags
+# ---------------------------------------
+
+CFLAGS += $(addprefix -I,$(INC))
+
+# Verbose mode
+ifeq ("$(V)","1")
+$(info CFLAGS  $(CFLAGS) ) $(info )
+$(info LDFLAGS $(LDFLAGS)) $(info )
+$(info ASFLAGS $(ASFLAGS)) $(info )
+endif
+
+
 OBJ_DIRS = $(sort $(dir $(OBJ)))
 $(OBJ): | $(OBJ_DIRS)
 $(OBJ_DIRS):
 ifeq ($(CMDEXE),1)
-	@$(MKDIR) $(subst /,\,$@)
+	-@$(MKDIR) $(subst /,\,$@)
 else
 	@$(MKDIR) -p $@
 endif
 
-$(BUILD)/$(PROJECT).elf: $(OBJ)
-	@echo LINK $@
-	@$(CC) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
-
-$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) -O binary $^ $@
-
-$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) -O ihex $^ $@
-
 # UF2 generation, iMXRT need to strip to text only before conversion
-ifeq ($(FAMILY),imxrt)
-$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) -O ihex -R .flash_config -R .ivt $^ $(BUILD)/$(PROJECT)-textonly.hex
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -c -o $@ $(BUILD)/$(PROJECT)-textonly.hex
-else
+ifneq ($(FAMILY),imxrt)
 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).hex
 	@echo CREATE $@
 	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -c -o $@ $^
@@ -122,27 +58,8 @@ endif
 
 copy-artifact: $(BUILD)/$(PROJECT).bin $(BUILD)/$(PROJECT).hex $(BUILD)/$(PROJECT).uf2
 
-# We set vpath to point to the top of the tree so that the source files
-# can be located. By following this scheme, it allows a single build rule
-# to be used to compile all .c files.
-vpath %.c . $(TOP)
-$(BUILD)/obj/%.o: %.c
-	@echo CC $(notdir $@)
-	@$(CC) $(CFLAGS) -c -MD -o $@ $<
-
-# ASM sources lower case .s
-vpath %.s . $(TOP)
-$(BUILD)/obj/%_asm.o: %.s
-	@echo AS $(notdir $@)
-	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
-
-# ASM sources upper case .S
-vpath %.S . $(TOP)
-$(BUILD)/obj/%_asm.o: %.S
-	@echo AS $(notdir $@)
-	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
-
 endif
+# ---------------- GNU Make End -----------------------
 
 .PHONY: clean
 clean:
@@ -151,15 +68,13 @@ ifeq ($(CMDEXE),1)
 else
 	$(RM) -rf $(BUILD)
 endif
-# ---------------- GNU Make End -----------------------
 
 # get depenecies
 .PHONY: get-deps
 get-deps:
-  ifdef DEPS_SUBMODULES
-	git -C $(TOP) submodule update --init $(DEPS_SUBMODULES)
-  endif
+	$(PYTHON) $(TOP)/tools/get_deps.py ${FAMILY}
 
+.PHONY: size
 size: $(BUILD)/$(PROJECT).elf
 	-@echo ''
 	@$(SIZE) $<
@@ -173,7 +88,7 @@ linkermap: $(BUILD)/$(PROJECT).elf
 # Flash Targets
 # ---------------------------------------
 
-# Jlink binary
+# --------------- Jlink -----------------
 ifeq ($(OS),Windows_NT)
   JLINKEXE = JLink.exe
 else
@@ -183,20 +98,24 @@ endif
 # Jlink Interface
 JLINK_IF ?= swd
 
-# Flash using jlink
-flash-jlink: $(BUILD)/$(PROJECT).hex
-	@echo halt > $(BUILD)/$(BOARD).jlink
-	@echo r > $(BUILD)/$(BOARD).jlink
-	@echo loadfile $^ >> $(BUILD)/$(BOARD).jlink
-	@echo r >> $(BUILD)/$(BOARD).jlink
-	@echo go >> $(BUILD)/$(BOARD).jlink
-	@echo exit >> $(BUILD)/$(BOARD).jlink
-	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
+# Jlink script
+$(BUILD)/$(BOARD).jlink: $(BUILD)/$(PROJECT).hex
+	@echo halt > $@
+	@echo loadfile $^ >> $@
+	@echo r >> $@
+	@echo go >> $@
+	@echo exit >> $@
 
+# Flash using jlink
+flash-jlink: $(BUILD)/$(BOARD).jlink
+	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $<
+
+# --------------- stm32 cube programmer -----------------
 # Flash STM32 MCU using stlink with STM32 Cube Programmer CLI
 flash-stlink: $(BUILD)/$(PROJECT).elf
 	STM32_Programmer_CLI --connect port=swd --write $< --go
 
+# --------------- xfel -----------------
 $(BUILD)/$(PROJECT)-sunxi.bin: $(BUILD)/$(PROJECT).bin
 	$(PYTHON) $(TOP)/tools/mksunxi.py $< $@
 
@@ -204,18 +123,40 @@ flash-xfel: $(BUILD)/$(PROJECT)-sunxi.bin
 	xfel spinor write 0 $<
 	xfel reset
 
-# Flash using pyocd
+# --------------- pyocd -----------------
 PYOCD_OPTION ?=
 flash-pyocd: $(BUILD)/$(PROJECT).hex
 	pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $<
 	#pyocd reset -t $(PYOCD_TARGET)
 
-# Flash using openocd
+# --------------- openocd -----------------
 OPENOCD_OPTION ?=
 flash-openocd: $(BUILD)/$(PROJECT).elf
 	openocd $(OPENOCD_OPTION) -c "program $< verify reset exit"
 
-# flash with Black Magic Probe
+# --------------- openocd-wch -----------------
+# wch-linke is not supported yet in official openOCD yet. We need to either use
+# 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
+# 2. compiled from https://github.com/hathach/riscv-openocd-wch or
+#    https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
+#    with  ./configure --disable-werror --enable-wlinke --enable-ch347=no
+OPENOCD_WCH ?= /home/${USER}/app/riscv-openocd-wch/src/openocd
+OPENOCD_WCH_OPTION ?=
+flash-openocd-wch: $(BUILD)/$(PROJECT).elf
+	$(OPENOCD_WCH) $(OPENOCD_WCH_OPTION) -c init -c halt -c "flash write_image $<" -c reset -c exit
+
+# --------------- wlink-rs -----------------
+# flash with https://github.com/ch32-rs/wlink
+WLINK_RS ?= wlink
+flash-wlink-rs: $(BUILD)/$(PROJECT).elf
+	$(WLINK_RS) flash $<
+
+# --------------- dfu-util -----------------
+DFU_UTIL_OPTION ?= -a 0
+flash-dfu-util: $(BUILD)/$(PROJECT).bin
+	dfu-util -R $(DFU_UTIL_OPTION) -D $<
+
+# --------------- Black Magic -----------------
 # This symlink is created by https://github.com/blacksphere/blackmagic/blob/master/driver/99-blackmagic.rules
 BMP ?= /dev/ttyBmpGdb
 
@@ -225,11 +166,20 @@ flash-bmp: $(BUILD)/$(PROJECT).elf
 debug-bmp: $(BUILD)/$(PROJECT).elf
 	$(GDB) -ex 'target extended-remote $(BMP)' -ex 'monitor swdp_scan' -ex 'attach 1' $<
 
+# --------------- TI Uniflash -----------------
+DSLITE ?= dslite.sh
+flash-uniflash: $(BUILD)/$(PROJECT).hex
+	${DSLITE} ${UNIFLASH_OPTION} -f $<
+
 #-------------- Artifacts --------------
 
 # Create binary directory
 $(BIN):
+ifeq ($(CMDEXE),1)
+	@$(MKDIR) $(subst /,\,$@)
+else
 	@$(MKDIR) -p $@
+endif
 
 # Copy binaries .elf, .bin, .hex, .uf2 to BIN for upload
 # due to large size of combined artifacts, only uf2 is uploaded for now
@@ -242,4 +192,4 @@ copy-artifact: $(BIN)
 # Print out the value of a make variable.
 # https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile
 print-%:
-	@echo $* = $($*)
\ No newline at end of file
+	@echo $* = $($*)
diff --git a/examples/build_system/make/toolchain/arm_clang.mk b/examples/build_system/make/toolchain/arm_clang.mk
new file mode 100644
index 000000000..97face39c
--- /dev/null
+++ b/examples/build_system/make/toolchain/arm_clang.mk
@@ -0,0 +1,10 @@
+CC = clang
+CXX = clang++
+AS = $(CC) -x assembler-with-cpp
+LD = $(CC)
+
+GDB = $(CROSS_COMPILE)gdb
+OBJCOPY = llvm-objcopy
+SIZE = llvm-size
+
+include ${TOP}/examples/build_system/make/toolchain/gcc_common.mk
diff --git a/examples/build_system/make/toolchain/arm_gcc.mk b/examples/build_system/make/toolchain/arm_gcc.mk
new file mode 100644
index 000000000..a8576f8ee
--- /dev/null
+++ b/examples/build_system/make/toolchain/arm_gcc.mk
@@ -0,0 +1,20 @@
+# makefile for arm gcc toolchain
+
+# Can be set by family, default to ARM GCC
+CROSS_COMPILE ?= arm-none-eabi-
+
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CC) -x assembler-with-cpp
+LD = $(CC)
+
+GDB = $(CROSS_COMPILE)gdb
+OBJCOPY = $(CROSS_COMPILE)objcopy
+SIZE = $(CROSS_COMPILE)size
+
+CFLAGS += \
+  -fsingle-precision-constant \
+
+LIBS += -lgcc -lm -lnosys
+
+include ${TOP}/examples/build_system/make/toolchain/gcc_common.mk
diff --git a/examples/build_system/make/toolchain/arm_iar.mk b/examples/build_system/make/toolchain/arm_iar.mk
new file mode 100644
index 000000000..17967b41a
--- /dev/null
+++ b/examples/build_system/make/toolchain/arm_iar.mk
@@ -0,0 +1,13 @@
+# makefile for arm iar toolchain
+
+CC = iccarm
+AS = iasmarm
+LD = ilinkarm
+OBJCOPY = ielftool --silent
+SIZE = size
+
+# Enable extension mode (gcc compatible)
+CFLAGS += -e --debug --silent
+
+# silent mode
+ASFLAGS += -S $(addprefix -I,$(INC))
diff --git a/examples/build_system/make/toolchain/clang_rules.mk b/examples/build_system/make/toolchain/clang_rules.mk
new file mode 100644
index 000000000..341f705b1
--- /dev/null
+++ b/examples/build_system/make/toolchain/clang_rules.mk
@@ -0,0 +1 @@
+include ${TOP}/examples/build_system/make/toolchain/gcc_rules.mk
diff --git a/examples/build_system/make/toolchain/gcc_common.mk b/examples/build_system/make/toolchain/gcc_common.mk
new file mode 100644
index 000000000..0cbb6774d
--- /dev/null
+++ b/examples/build_system/make/toolchain/gcc_common.mk
@@ -0,0 +1,72 @@
+# ---------------------------------------
+# Compiler Flags
+# ---------------------------------------
+CFLAGS += \
+  -MD \
+  -ggdb \
+  -fdata-sections \
+  -ffunction-sections \
+  -fno-strict-aliasing \
+  -Wall \
+  -Wextra \
+  -Werror \
+  -Wfatal-errors \
+  -Wdouble-promotion \
+  -Wstrict-prototypes \
+  -Wstrict-overflow \
+  -Werror-implicit-function-declaration \
+  -Wfloat-equal \
+  -Wundef \
+  -Wshadow \
+  -Wwrite-strings \
+  -Wsign-compare \
+  -Wmissing-format-attribute \
+  -Wunreachable-code \
+  -Wcast-align \
+  -Wcast-function-type \
+  -Wcast-qual \
+  -Wnull-dereference \
+  -Wuninitialized \
+  -Wunused \
+  -Wreturn-type \
+  -Wredundant-decls \
+
+#  -Wmissing-prototypes \
+# conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion
+#  -Wconversion
+
+# Size Optimization as default
+CFLAGS_OPTIMIZED ?= -Os
+
+# Debugging/Optimization
+ifeq ($(DEBUG), 1)
+  CFLAGS += -O0
+  NO_LTO = 1
+else
+  CFLAGS += $(CFLAGS_OPTIMIZED)
+endif
+
+# ---------------------------------------
+# Linker Flags
+# ---------------------------------------
+LDFLAGS += \
+  -Wl,-Map=$@.map \
+  -Wl,--cref \
+  -Wl,-gc-sections \
+
+# renesas rx does not support --print-memory-usage flags
+ifneq ($(FAMILY),rx)
+LDFLAGS += -Wl,--print-memory-usage
+endif
+
+ifeq ($(TOOLCHAIN),gcc)
+CC_VERSION := $(shell $(CC) -dumpversion)
+CC_VERSION_MAJOR = $(firstword $(subst ., ,$(CC_VERSION)))
+
+# from version 12
+ifeq ($(strip $(if $(CMDEXE),\
+               $(shell if $(CC_VERSION_MAJOR) geq 12 (echo 1) else (echo 0)),\
+               $(shell expr $(CC_VERSION_MAJOR) \>= 12))), 1)
+LDFLAGS += -Wl,--no-warn-rwx-segment
+endif
+endif
diff --git a/examples/build_system/make/toolchain/gcc_rules.mk b/examples/build_system/make/toolchain/gcc_rules.mk
new file mode 100644
index 000000000..fc5225503
--- /dev/null
+++ b/examples/build_system/make/toolchain/gcc_rules.mk
@@ -0,0 +1,77 @@
+SRC_S += $(SRC_S_GCC)
+
+# Assembly files can be name with upper case .S, convert it to .s
+SRC_S := $(SRC_S:.S=.s)
+
+# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
+# assembly file should be placed first in linking order
+# '_asm' suffix is added to object of assembly file
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
+
+CFLAGS += $(CFLAGS_GCC) -MD
+
+# LTO makes it difficult to analyze map file for optimizing size purpose
+# We will run this option in ci
+ifeq ($(NO_LTO),1)
+CFLAGS := $(filter-out -flto,$(CFLAGS))
+endif
+
+ifneq ($(CFLAGS_SKIP),)
+CFLAGS := $(filter-out $(CFLAGS_SKIP),$(CFLAGS))
+endif
+
+ifeq ($(TOOLCHAIN),clang)
+CFLAGS += $(CFLAGS_CLANG)
+LDFLAGS += $(CFLAGS) $(LDFLAGS_CLANG)
+else
+LDFLAGS += $(CFLAGS) $(LDFLAGS_GCC)
+endif
+
+# TODO should be removed after all examples are updated
+ifdef LD_FILE
+LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE)
+endif
+
+ifdef LD_FILE_GCC
+LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE_GCC)
+endif
+
+ASFLAGS += $(CFLAGS)
+
+# libc
+ifneq ($(BOARD), spresense)
+LIBS += -lc
+endif
+
+# ---------------------------------------
+# Rules
+# ---------------------------------------
+
+# Compile .c file
+$(BUILD)/obj/%.o: %.c
+	@echo CC $(notdir $@)
+	@$(CC) $(CFLAGS) -c -o $@ $<
+
+# ASM sources lower case .s
+$(BUILD)/obj/%_asm.o: %.s
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+# ASM sources upper case .S
+$(BUILD)/obj/%_asm.o: %.S
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+OBJCOPY_BIN_OPTION ?=
+$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	$(OBJCOPY) -O binary $(OBJCOPY_BIN_OPTION) $^ $@
+
+$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) -O ihex $^ $@
+
+$(BUILD)/$(PROJECT).elf: $(OBJ)
+	@echo LINK $@
+	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
diff --git a/examples/build_system/make/toolchain/iar_rules.mk b/examples/build_system/make/toolchain/iar_rules.mk
new file mode 100644
index 000000000..2c066f6da
--- /dev/null
+++ b/examples/build_system/make/toolchain/iar_rules.mk
@@ -0,0 +1,44 @@
+SRC_S += $(SRC_S_IAR)
+
+# Assembly files can be name with upper case .S, convert it to .s
+SRC_S := $(SRC_S:.S=.s)
+
+# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
+# assembly file should be placed first in linking order
+# '_asm' suffix is added to object of assembly file
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
+
+# Linker script
+LDFLAGS += --config $(TOP)/$(LD_FILE_IAR)
+
+# ---------------------------------------
+# Rules
+# ---------------------------------------
+
+# Compile .c file
+$(BUILD)/obj/%.o: %.c
+	@echo CC $(notdir $@)
+	@$(CC) $(CFLAGS) -c -o $@ $<
+
+# ASM sources lower case .s
+$(BUILD)/obj/%_asm.o: %.s
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+# ASM sources upper case .S
+$(BUILD)/obj/%_asm.o: %.S
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) --bin $^ $@
+
+$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) --ihex $^ $@
+
+$(BUILD)/$(PROJECT).elf: $(OBJ)
+	@echo LINK $@
+	@$(LD) -o $@ $(LDFLAGS) $^
diff --git a/examples/build_system/make/toolchain/riscv_gcc.mk b/examples/build_system/make/toolchain/riscv_gcc.mk
new file mode 100644
index 000000000..843aff38c
--- /dev/null
+++ b/examples/build_system/make/toolchain/riscv_gcc.mk
@@ -0,0 +1,20 @@
+# makefile for arm gcc toolchain
+
+# Can be set by family, default to ARM GCC
+CROSS_COMPILE ?= riscv-none-embed-
+
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CC) -x assembler-with-cpp
+LD = $(CC)
+
+GDB = $(CROSS_COMPILE)gdb
+OBJCOPY = $(CROSS_COMPILE)objcopy
+SIZE = $(CROSS_COMPILE)size
+
+CFLAGS += \
+  -fsingle-precision-constant \
+
+LIBS += -lgcc -lm -lnosys
+
+include ${TOP}/examples/build_system/make/toolchain/gcc_common.mk
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index edf5ab805..bb7dd0a0f 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -1,20 +1,25 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
-project(tinyusb_device_examples)
+project(tinyusb_device_examples C CXX ASM)
 family_initialize_project(tinyusb_device_examples ${CMAKE_CURRENT_LIST_DIR})
 
 # family_add_subdirectory will filter what to actually add based on selected FAMILY
 family_add_subdirectory(audio_4_channel_mic)
 family_add_subdirectory(audio_test)
+family_add_subdirectory(audio_4_channel_mic_freertos)
+family_add_subdirectory(audio_test_freertos)
+family_add_subdirectory(audio_test_multi_rate)
 family_add_subdirectory(board_test)
 family_add_subdirectory(cdc_dual_ports)
 family_add_subdirectory(cdc_msc)
 family_add_subdirectory(cdc_msc_freertos)
+family_add_subdirectory(cdc_uac2)
 family_add_subdirectory(dfu)
 family_add_subdirectory(dfu_runtime)
 family_add_subdirectory(dynamic_configuration)
+family_add_subdirectory(hid_boot_interface)
 family_add_subdirectory(hid_composite)
 family_add_subdirectory(hid_composite_freertos)
 family_add_subdirectory(hid_generic_inout)
@@ -23,6 +28,8 @@ family_add_subdirectory(midi_test)
 family_add_subdirectory(msc_dual_lun)
 family_add_subdirectory(net_lwip_webserver)
 family_add_subdirectory(uac2_headset)
+family_add_subdirectory(uac2_speaker_fb)
 family_add_subdirectory(usbtmc)
 family_add_subdirectory(video_capture)
+family_add_subdirectory(video_capture_2ch)
 family_add_subdirectory(webusb_serial)
diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt
index f6e10e2ea..c8086ae46 100644
--- a/examples/device/audio_4_channel_mic/CMakeLists.txt
+++ b/examples/device/audio_4_channel_mic/CMakeLists.txt
@@ -1,28 +1,38 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
   ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-)
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
-)
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Add libm for GCC
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+  target_link_libraries(${PROJECT} PUBLIC m)
+endif()
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/audio_4_channel_mic/Makefile b/examples/device/audio_4_channel_mic/Makefile
index 5a455078e..2c825bbf7 100644
--- a/examples/device/audio_4_channel_mic/Makefile
+++ b/examples/device/audio_4_channel_mic/Makefile
@@ -1,12 +1,14 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
   src \
   $(TOP)/hw \
 
 # Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE += \
+  src/main.c \
+  src/usb_descriptors.c \
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/audio_4_channel_mic/skip.txt b/examples/device/audio_4_channel_mic/skip.txt
index ae9b57f1f..157605df1 100644
--- a/examples/device/audio_4_channel_mic/skip.txt
+++ b/examples/device/audio_4_channel_mic/skip.txt
@@ -1,3 +1,5 @@
 mcu:SAMD11
 mcu:SAME5X
-mcu:SAMG
\ No newline at end of file
+mcu:SAMG
+family:broadcom_64bit
+family:espressif
diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index a6af5fd19..e8c40309e 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Reinhard Panhuber
@@ -34,17 +34,16 @@
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
+#include <math.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
+#include "tusb_config.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
-
-#ifndef AUDIO_SAMPLE_RATE
-#define AUDIO_SAMPLE_RATE   48000
-#endif
+#define AUDIO_SAMPLE_RATE   CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE
 
 /* Blink pattern
  * - 250 ms  : device not mounted
@@ -70,8 +69,13 @@ uint8_t clkValid;
 audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; 			// Volume range state
 audio_control_range_4_n_t(1) sampleFreqRng; 						// Sample frequency range state
 
-// Audio test data
-uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ/2];   // Ensure half word aligned
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+// Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000/CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
+#else
+// Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000];
+#endif
 
 void led_blinking_task(void);
 void audio_task(void);
@@ -82,7 +86,15 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   // Init values
   sampFreq = AUDIO_SAMPLE_RATE;
@@ -93,15 +105,51 @@ int main(void)
   sampleFreqRng.subrange[0].bMax = AUDIO_SAMPLE_RATE;
   sampleFreqRng.subrange[0].bRes = 0;
 
+  // Generate dummy data
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+  uint16_t * p_buff = i2s_dummy_buffer[0];
+  uint16_t dataVal = 0;
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH0 saw wave
+    *p_buff++ = dataVal;
+    // CH1 inverted saw wave
+    *p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+    dataVal+= 32;
+  }
+  p_buff = i2s_dummy_buffer[1];
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH3 square wave
+    *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000;
+    // CH4 sinus wave
+    float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+    *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
+  }
+#else
+  uint16_t * p_buff = i2s_dummy_buffer;
+  uint16_t dataVal = 0;
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH0 saw wave
+    *p_buff++ = dataVal;
+    // CH1 inverted saw wave
+    *p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+    dataVal+= 32;
+    // CH3 square wave
+    *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000;
+    // CH4 sinus wave
+    float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+    *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
+  }
+#endif
+
   while (1)
   {
     tud_task(); // tinyusb device task
     led_blinking_task();
     audio_task();
   }
-
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -132,7 +180,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
@@ -141,8 +189,21 @@ void tud_resume_cb(void)
 
 void audio_task(void)
 {
-  // Yet to be filled - e.g. put meas data into TX FIFOs etc.
-  // asm("nop");
+  // Yet to be filled - e.g. read audio from I2S buffer.
+  // Here we simulate a I2S receive callback every 1ms.
+  static uint32_t start_ms = 0;
+  uint32_t curr_ms = board_millis();
+  if ( start_ms == curr_ms ) return; // not enough time
+  start_ms = curr_ms;
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+  // Write I2S buffer into FIFO
+  for (uint8_t cnt=0; cnt < 2; cnt++)
+  {
+    tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
+  }
+#else
+  tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -290,7 +351,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
 
         // Those are dummy values for now
         ret.bNrChannels = 1;
-        ret.bmChannelConfig = 0;
+        ret.bmChannelConfig = (audio_channel_config_t) 0;
         ret.iChannelNames = 0;
 
         TU_LOG2("    Get terminal connector\r\n");
@@ -363,7 +424,8 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
         {
           case AUDIO_CS_REQ_CUR:
             TU_LOG2("    Get Sample Freq.\r\n");
-            return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+            // Buffered control transfer is needed for IN flow control to work
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
 
           case AUDIO_CS_REQ_RANGE:
             TU_LOG2("    Get Sample Freq. range\r\n");
@@ -399,10 +461,14 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
   (void) ep_in;
   (void) cur_alt_setting;
 
-  for (uint8_t cnt=0; cnt < CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; cnt++)
-  {
-    tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
-  }
+
+  // In read world application data flow is driven by I2S clock,
+  // both tud_audio_tx_done_pre_load_cb() & tud_audio_tx_done_post_load_cb() are hardly used.
+  // For example in your I2S receive callback:
+  // void I2S_Rx_Callback(int channel, const void* data, uint16_t samples)
+  // {
+  //    tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO);
+  // }
 
   return true;
 }
@@ -415,22 +481,6 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
   (void) ep_in;
   (void) cur_alt_setting;
 
-  uint16_t dataVal;
-
-  // Generate dummy data
-  for (uint16_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; cnt++)
-  {
-    uint16_t * p_buff = i2s_dummy_buffer[cnt];              // 2 bytes per sample
-    dataVal = 1;
-    for (uint16_t cnt2 = 0; cnt2 < AUDIO_SAMPLE_RATE/1000; cnt2++)
-    {
-      for (uint8_t cnt3 = 0; cnt3 < CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX; cnt3++)
-      {
-        *p_buff++ = dataVal;
-      }
-      dataVal++;
-    }
-  }
   return true;
 }
 
diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
old mode 100644
new mode 100755
index 9ab15135d..4d61e7f5e
--- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
+++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
 import sounddevice as sd
 import matplotlib.pyplot as plt
 import numpy as np
@@ -10,11 +11,11 @@ if __name__ == '__main__':
     # print(sd.query_devices())
 
     fs = 48000  		# Sample rate
-    duration = 100e-3   # Duration of recording
+    duration = 1   # Duration of recording
 
     if platform.system() == 'Windows':
         # WDM-KS is needed since there are more than one MicNode device APIs (at least in Windows)
-        device = 'Microphone (MicNode_4_Ch), Windows WDM-KS'
+        device = 'Microphone (MicNode_4_Ch), Windows WASAPI'
     elif platform.system() == 'Darwin':
         device = 'MicNode_4_Ch'
     else:
@@ -25,10 +26,13 @@ if __name__ == '__main__':
     sd.wait()  # Wait until recording is finished
     print('Done!')
 
+
     time = np.arange(0, duration, 1 / fs)  # time vector
+    # strip starting zero
+
     plt.plot(time, myrecording)
     plt.xlabel('Time [s]')
     plt.ylabel('Amplitude')
     plt.title('MicNode 4 Channel')
+    plt.legend(['CH-1', 'CH-2', 'CH-3','CH-4'])
     plt.show()
-    
\ No newline at end of file
diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index 5cf6d07c3..46484f847 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -103,6 +103,7 @@ extern "C" {
 //--------------------------------------------------------------------
 
 // Have a look into audio_device.h for all configurations
+#define CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE              48000
 
 #define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                 TUD_AUDIO_MIC_FOUR_CH_DESC_LEN
 
@@ -112,15 +113,27 @@ extern "C" {
 #define CFG_TUD_AUDIO_ENABLE_EP_IN                    1
 #define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX    2         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX            4         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
-#define CFG_TUD_AUDIO_EP_SZ_IN                        (48 + 1) * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX      // 48 Samples (48 kHz) x 2 Bytes/Sample x CFG_TUD_AUDIO_N_CHANNELS_TX Channels - the Windows driver always needs an extra sample per channel of space more, otherwise it complains... found by trial and error
+#define CFG_TUD_AUDIO_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_ENABLE_ENCODING                 1
+#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL              1
+
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          CFG_TUD_AUDIO_EP_SZ_IN
 
-#define CFG_TUD_AUDIO_ENABLE_ENCODING                 1
 #define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING          1
 #define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX      2         // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
 #define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO        (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
-#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       (TUD_OPT_HIGH_SPEED ? 32 : 4) * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Example write FIFO every 1ms, so it should be 8 times larger for HS device
+
+#else
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
+
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index 8929f3057..728a5f9ce 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -44,7 +45,7 @@ tusb_desc_device_t const desc_device =
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = 0x0200,
 
-    // Use Interface Association Descriptor (IAD) for CDC
+    // Use Interface Association Descriptor (IAD) for Audio
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
@@ -96,7 +97,7 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-  // Interface count, string index, total length, attribute, power in mA
+  // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
@@ -116,50 +117,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
-// array of pointer to string descriptors
-char const* string_desc_arr [] =
-{
-    (const char[]) { 0x09, 0x04 }, 	// 0: is supported language is English (0x0409)
-    "PaniRCorp",                   	// 1: Manufacturer
-    "MicNode_4_Ch",    		// 2: Product
-    "123458",                      	// 3: Serials, should use chip ID
-    "UAC2",                 	 	// 4: Audio Interface
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
 };
 
-static uint16_t _desc_str[32];
+// array of pointer to string descriptors
+char const* string_desc_arr [] = {
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "PaniRCorp",                   // 1: Manufacturer
+    "MicNode_4_Ch",                // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "UAC2",                        // 4: Audio Interface
+};
+
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Convert ASCII string into UTF-16
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt b/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt
new file mode 100644
index 000000000..c50d4fef7
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt
@@ -0,0 +1,38 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Add libm for GCC
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+  target_link_libraries(${PROJECT} PUBLIC m)
+endif()
+
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/audio_4_channel_mic_freertos/Makefile b/examples/device/audio_4_channel_mic_freertos/Makefile
new file mode 100644
index 000000000..bd625b345
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/Makefile
@@ -0,0 +1,15 @@
+RTOS = freertos
+include ../../build_system/make/make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE = \
+	src/main.c \
+	src/usb_descriptors.c
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/audio_4_channel_mic_freertos/README.md b/examples/device/audio_4_channel_mic_freertos/README.md
new file mode 100644
index 000000000..a99f28bc3
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/README.md
@@ -0,0 +1,19 @@
+# How to build example for Esp32s3
+1. Load idf environment variables (eg. using the esp-idf alias `get_idf` if configured)
+
+2. cd into examples directory
+```
+$ cd /tinyusb/examples/device/audio_4_channel_mic_freertos
+```
+
+3. Run cmake in project directory specifying the board
+```
+$ cmake -DBOARD=espressif_s3_devkitc -B build -G Ninja .
+$ ninja.exe -C build
+```
+
+4. Flash the binary onto the esp32-s3 by copy-paste of the full command output by the esp-idf build system replacing **(PORT)** with eg. /dev/ttyUSB0
+
+eg.
+
+> /home/kaspernyhus/.espressif/python_env/idf4.4_py3.8_env/bin/python ../../../../esp-idf/components/esptool_py/esptool/esptool.py -p /dev/ttyUSB0 -b 460800 --before default_reset --after hard_reset --chip esp32s3  write_flash --flash_mode dio --flash_size detect --flash_freq 80m 0x0 _build/espressif_s3_devkitc/bootloader/bootloader.bin 0x8000 _build/espressif_s3_devkitc/partition_table/partition-table.bin 0x10000 _build/espressif_s3_devkitc/audio_4_channel_mic_freertos.bin
diff --git a/examples/device/audio_4_channel_mic_freertos/sdkconfig.defaults b/examples/device/audio_4_channel_mic_freertos/sdkconfig.defaults
new file mode 100644
index 000000000..eaa9fb902
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/sdkconfig.defaults
@@ -0,0 +1,4 @@
+CONFIG_IDF_CMAKE=y
+CONFIG_FREERTOS_HZ=1000
+CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
diff --git a/examples/device/audio_4_channel_mic_freertos/skip.txt b/examples/device/audio_4_channel_mic_freertos/skip.txt
new file mode 100644
index 000000000..30cd46e7e
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/skip.txt
@@ -0,0 +1,19 @@
+mcu:CH32V103
+mcu:CH32V20X
+mcu:CH32V307
+mcu:CXD56
+mcu:F1C100S
+mcu:GD32VF103
+mcu:MCXA15
+mcu:MKL25ZXX
+mcu:MSP430x5xx
+mcu:RP2040
+mcu:SAMD11
+mcu:SAMX7X
+mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
+mcu:STM32L0
+board:lpcxpresso11u37
+board:lpcxpresso1347
+family:broadcom_32bit
+family:broadcom_64bit
diff --git a/examples/device/audio_4_channel_mic_freertos/src/CMakeLists.txt b/examples/device/audio_4_channel_mic_freertos/src/CMakeLists.txt
new file mode 100644
index 000000000..cef2b46ee
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c" "usb_descriptors.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/audio_4_channel_mic_freertos/src/main.c b/examples/device/audio_4_channel_mic_freertos/src/main.c
new file mode 100644
index 000000000..c9de4029a
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/main.c
@@ -0,0 +1,584 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Reinhard Panhuber
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* plot_audio_samples.py requires following modules:
+ * $ sudo apt install libportaudio
+ * $ pip3 install sounddevice matplotlib
+ *
+ * Then run
+ * $ python3 plot_audio_samples.py
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <math.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+  // ESP-IDF need "freertos/" prefix in include path.
+  // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+  #include "freertos/FreeRTOS.h"
+  #include "freertos/semphr.h"
+  #include "freertos/queue.h"
+  #include "freertos/task.h"
+  #include "freertos/timers.h"
+
+  #define USBD_STACK_SIZE     4096
+#else
+
+  #include "FreeRTOS.h"
+  #include "semphr.h"
+  #include "queue.h"
+  #include "task.h"
+  #include "timers.h"
+
+  // Increase stack size when debug log is enabled
+  #define USBD_STACK_SIZE    (4*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+#define AUDIO_STACK_SIZE    configMINIMAL_STACK_SIZE
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+#define AUDIO_SAMPLE_RATE   CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t  blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t  usb_device_stack[USBD_STACK_SIZE];
+StaticTask_t usb_device_taskdef;
+
+StackType_t  audio_stack[AUDIO_STACK_SIZE];
+StaticTask_t audio_taskdef;
+#endif
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+bool mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; 				          // +1 for master channel 0
+uint16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; 					// +1 for master channel 0
+uint32_t sampFreq;
+uint8_t clkValid;
+
+// Range states
+audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; 			// Volume range state
+audio_control_range_4_n_t(1) sampleFreqRng; 						// Sample frequency range state
+
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+// Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000/CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
+#else
+// Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000];
+#endif
+
+void led_blinking_task(void* param);
+void usb_device_task(void* param);
+void audio_task(void* param);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  // Init values
+  sampFreq = AUDIO_SAMPLE_RATE;
+  clkValid = 1;
+
+  sampleFreqRng.wNumSubRanges = 1;
+  sampleFreqRng.subrange[0].bMin = AUDIO_SAMPLE_RATE;
+  sampleFreqRng.subrange[0].bMax = AUDIO_SAMPLE_RATE;
+  sampleFreqRng.subrange[0].bRes = 0;
+
+  // Generate dummy data
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+  uint16_t * p_buff = i2s_dummy_buffer[0];
+  uint16_t dataVal = 0;
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH0 saw wave
+    *p_buff++ = dataVal;
+    // CH1 inverted saw wave
+    *p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+    dataVal+= 32;
+  }
+  p_buff = i2s_dummy_buffer[1];
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH3 square wave
+    *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000;
+    // CH4 sinus wave
+    float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+    *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
+  }
+#else
+  uint16_t * p_buff = i2s_dummy_buffer;
+  uint16_t dataVal = 0;
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH0 saw wave
+    *p_buff++ = dataVal;
+    // CH1 inverted saw wave
+    *p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+    dataVal+= 32;
+    // CH3 square wave
+    *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000;
+    // CH4 sinus wave
+    float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+    *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
+  }
+#endif
+
+#if configSUPPORT_STATIC_ALLOCATION
+  // blinky task
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+
+  // Create a task for tinyusb device stack
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+
+   // Create a task for audio
+  xTaskCreateStatic(audio_task, "audio", AUDIO_STACK_SIZE, NULL, configMAX_PRIORITIES-1, audio_stack, &audio_taskdef);
+#else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(audio_task, "audio", AUDIO_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+#endif
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+  #if !TUSB_MCU_VENDOR_ESPRESSIF
+    vTaskStartScheduler();
+  #endif
+
+  return 0;
+}
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+void app_main(void)
+{
+  main();
+}
+#endif
+
+// USB Device Driver task
+// This top level thread process all usb events and invoke callbacks
+void usb_device_task(void* param)
+{
+  (void) param;
+
+  // init device stack on configured roothub port
+  // This should be called after scheduler/kernel is started.
+  // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  // RTOS forever loop
+  while (1)
+  {
+    // tinyusb device task
+    tud_task();
+  }
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// AUDIO Task
+//--------------------------------------------------------------------+
+
+void audio_task(void* param)
+{
+  (void) param;
+  // Yet to be filled - e.g. read audio from I2S buffer.
+  // Here we simulate a I2S receive callback every 1ms.
+  while (1) {
+    vTaskDelay(1);
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+  // Write I2S buffer into FIFO
+    for (uint8_t cnt=0; cnt < 2; cnt++)
+    {
+      tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
+    }
+#else
+    tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
+#endif
+  }
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when audio class specific set request received for an EP
+bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+  (void) pBuff;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) ep;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an interface
+bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+  (void) pBuff;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) itf;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+  uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+  (void) itf;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // If request is for our feature unit
+  if ( entityID == 2 )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_FU_CTRL_MUTE:
+        // Request uses format layout 1
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_1_t));
+
+        mute[channelNum] = ((audio_control_cur_1_t*) pBuff)->bCur;
+
+        TU_LOG2("    Set Mute: %d of channel: %u\r\n", mute[channelNum], channelNum);
+      return true;
+
+      case AUDIO_FU_CTRL_VOLUME:
+        // Request uses format layout 2
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
+
+        volume[channelNum] = ((audio_control_cur_2_t*) pBuff)->bCur;
+
+        TU_LOG2("    Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
+      return true;
+
+        // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+      return false;
+    }
+  }
+  return false;    // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an EP
+bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) ep;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an interface
+bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) itf;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  // uint8_t itf = TU_U16_LOW(p_request->wIndex); 			// Since we have only one audio function implemented, we do not need the itf value
+  uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+  // Input terminal (Microphone input)
+  if (entityID == 1)
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_TE_CTRL_CONNECTOR:
+      {
+        // The terminal connector control only has a get request with only the CUR attribute.
+        audio_desc_channel_cluster_t ret;
+
+        // Those are dummy values for now
+        ret.bNrChannels = 1;
+        ret.bmChannelConfig = 0;
+        ret.iChannelNames = 0;
+
+        TU_LOG2("    Get terminal connector\r\n");
+
+        return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+      }
+      break;
+
+        // Unknown/Unsupported control selector
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  // Feature unit
+  if (entityID == 2)
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_FU_CTRL_MUTE:
+        // Audio control mute cur parameter block consists of only one byte - we thus can send it right away
+        // There does not exist a range parameter block for mute
+        TU_LOG2("    Get Mute of channel: %u\r\n", channelNum);
+        return tud_control_xfer(rhport, p_request, &mute[channelNum], 1);
+
+      case AUDIO_FU_CTRL_VOLUME:
+        switch ( p_request->bRequest )
+        {
+          case AUDIO_CS_REQ_CUR:
+            TU_LOG2("    Get Volume of channel: %u\r\n", channelNum);
+            return tud_control_xfer(rhport, p_request, &volume[channelNum], sizeof(volume[channelNum]));
+
+          case AUDIO_CS_REQ_RANGE:
+            TU_LOG2("    Get Volume range of channel: %u\r\n", channelNum);
+
+            // Copy values - only for testing - better is version below
+            audio_control_range_2_n_t(1)
+            ret;
+
+            ret.wNumSubRanges = 1;
+            ret.subrange[0].bMin = -90;           // -90 dB
+            ret.subrange[0].bMax = 90;		// +90 dB
+            ret.subrange[0].bRes = 1; 		// 1 dB steps
+
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+
+            // Unknown/Unsupported control
+          default:
+            TU_BREAKPOINT();
+            return false;
+        }
+      break;
+
+        // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  // Clock Source unit
+  if ( entityID == 4 )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_CS_CTRL_SAM_FREQ:
+        // channelNum is always zero in this case
+        switch ( p_request->bRequest )
+        {
+          case AUDIO_CS_REQ_CUR:
+            TU_LOG2("    Get Sample Freq.\r\n");
+            // Buffered control transfer is needed for IN flow control to work
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+
+          case AUDIO_CS_REQ_RANGE:
+            TU_LOG2("    Get Sample Freq. range\r\n");
+            return tud_control_xfer(rhport, p_request, &sampleFreqRng, sizeof(sampleFreqRng));
+
+           // Unknown/Unsupported control
+          default:
+            TU_BREAKPOINT();
+            return false;
+        }
+      break;
+
+      case AUDIO_CS_CTRL_CLK_VALID:
+        // Only cur attribute exists for this request
+        TU_LOG2("    Get Sample Freq. valid\r\n");
+        return tud_control_xfer(rhport, p_request, &clkValid, sizeof(clkValid));
+
+      // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  TU_LOG2("  Unsupported entity: %d\r\n", entityID);
+  return false; 	// Yet not implemented
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void) rhport;
+  (void) itf;
+  (void) ep_in;
+  (void) cur_alt_setting;
+
+
+  // In read world application data flow is driven by I2S clock,
+  // both tud_audio_tx_done_pre_load_cb() & tud_audio_tx_done_post_load_cb() are hardly used.
+  // For example in your I2S receive callback:
+  // void I2S_Rx_Callback(int channel, const void* data, uint16_t samples)
+  // {
+  //    tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO);
+  // }
+
+  return true;
+}
+
+bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void) rhport;
+  (void) n_bytes_copied;
+  (void) itf;
+  (void) ep_in;
+  (void) cur_alt_setting;
+
+  return true;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+  (void) p_request;
+
+  return true;
+}
+
+///--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void* param) {
+  (void) param;
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  while (1) {
+    // Blink every interval ms
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    start_ms += blink_interval_ms;
+
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
+}
diff --git a/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py
new file mode 100755
index 000000000..4d5ca28d6
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py
@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+import sounddevice as sd
+import matplotlib.pyplot as plt
+import numpy as np
+import platform
+
+if __name__ == '__main__':
+
+    # If you got "ValueError: No input device matching", that is because your PC name example device
+    # differently from tested list below. Uncomment the next line to see full list and try to pick correct one
+    # print(sd.query_devices())
+
+    fs = 48000  		# Sample rate
+    duration = 100e-3   # Duration of recording
+
+    if platform.system() == 'Windows':
+        # WDM-KS is needed since there are more than one MicNode device APIs (at least in Windows)
+        device = 'Microphone (MicNode_4_Ch), Windows WDM-KS'
+    elif platform.system() == 'Darwin':
+        device = 'MicNode_4_Ch'
+    else:
+        device ='default'
+
+    myrecording = sd.rec(int(duration * fs), samplerate=fs, channels=4, dtype='int16', device=device)
+    print('Waiting...')
+    sd.wait()  # Wait until recording is finished
+    print('Done!')
+
+    time = np.arange(0, duration, 1 / fs)  # time vector
+    plt.plot(time, myrecording)
+    plt.xlabel('Time [s]')
+    plt.ylabel('Amplitude')
+    plt.title('MicNode 4 Channel')
+    plt.show()
diff --git a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h
new file mode 100644
index 000000000..5cd93b0d6
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h
@@ -0,0 +1,148 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+// This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_FREERTOS
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TUSB_MCU_VENDOR_ESPRESSIF
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG            0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED           1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED         BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_AUDIO             1
+#define CFG_TUD_CDC               0
+#define CFG_TUD_MSC               0
+#define CFG_TUD_HID               0
+#define CFG_TUD_MIDI              0
+#define CFG_TUD_VENDOR            0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+// Have a look into audio_device.h for all configurations
+#define CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE              48000
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                 TUD_AUDIO_MIC_FOUR_CH_DESC_LEN
+
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT                 1
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ              64
+
+#define CFG_TUD_AUDIO_ENABLE_EP_IN                    1
+#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX    2         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX            4         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
+#define CFG_TUD_AUDIO_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_ENABLE_ENCODING                 1
+#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL              1
+
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          CFG_TUD_AUDIO_EP_SZ_IN
+
+#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING          1
+#define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX      2         // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
+#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO        (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       (TUD_OPT_HIGH_SPEED ? 32 : 4) * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Example write FIFO every 1ms, so it should be 8 times larger for HS device
+
+#else
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/audio_4_channel_mic_freertos/src/usb_descriptors.c b/examples/device/audio_4_channel_mic_freertos/src/usb_descriptors.c
new file mode 100644
index 000000000..728a5f9ce
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/usb_descriptors.c
@@ -0,0 +1,179 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]     AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+    _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0200,
+
+    // Use Interface Association Descriptor (IAD) for Audio
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+  return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+enum
+{
+  ITF_NUM_AUDIO_CONTROL = 0,
+  ITF_NUM_AUDIO_STREAMING,
+  ITF_NUM_TOTAL
+};
+
+#define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_FOUR_CH_DESC_LEN)
+
+#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO   0x03
+
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
+  // nRF5x ISO can only be endpoint 8
+  #define EPNUM_AUDIO   0x08
+
+#else
+  #define EPNUM_AUDIO   0x01
+#endif
+
+uint8_t const desc_configuration[] =
+{
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+  // Interface number, string index, EP Out & EP In address, EP size
+  TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
+};
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+  return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] = {
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "PaniRCorp",                   // 1: Manufacturer
+    "MicNode_4_Ch",                // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "UAC2",                        // 4: Audio Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index cb321f9a8..6a7e68c3d 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -1,28 +1,33 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
   ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-)
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
-)
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/audio_test/Makefile b/examples/device/audio_test/Makefile
index 5a455078e..7fa475da5 100644
--- a/examples/device/audio_test/Makefile
+++ b/examples/device/audio_test/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
   src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/audio_test/skip.txt b/examples/device/audio_test/skip.txt
index ae9b57f1f..65b137814 100644
--- a/examples/device/audio_test/skip.txt
+++ b/examples/device/audio_test/skip.txt
@@ -1,3 +1,4 @@
 mcu:SAMD11
 mcu:SAME5X
-mcu:SAMG
\ No newline at end of file
+mcu:SAMG
+family:espressif
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index d0849c7ac..018c48994 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Reinhard Panhuber
@@ -35,17 +35,13 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
 
-#ifndef AUDIO_SAMPLE_RATE
-#define AUDIO_SAMPLE_RATE   48000
-#endif
-
 /* Blink pattern
  * - 250 ms  : device not mounted
  * - 1000 ms : device mounted
@@ -71,7 +67,7 @@ audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1];
 audio_control_range_4_n_t(1) sampleFreqRng; 						// Sample frequency range state
 
 // Audio test data
-uint16_t test_buffer_audio[CFG_TUD_AUDIO_EP_SZ_IN/2];
+uint16_t test_buffer_audio[(CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2];
 uint16_t startVal = 0;
 
 void led_blinking_task(void);
@@ -83,15 +79,23 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   // Init values
-  sampFreq = AUDIO_SAMPLE_RATE;
+  sampFreq = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
   clkValid = 1;
 
   sampleFreqRng.wNumSubRanges = 1;
-  sampleFreqRng.subrange[0].bMin = AUDIO_SAMPLE_RATE;
-  sampleFreqRng.subrange[0].bMax = AUDIO_SAMPLE_RATE;
+  sampleFreqRng.subrange[0].bMin = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
+  sampleFreqRng.subrange[0].bMax = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
   sampleFreqRng.subrange[0].bRes = 0;
 
   while (1)
@@ -100,9 +104,6 @@ int main(void)
     led_blinking_task();
     audio_task();
   }
-
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -133,7 +134,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
@@ -291,7 +292,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
 
         // Those are dummy values for now
         ret.bNrChannels = 1;
-        ret.bmChannelConfig = 0;
+        ret.bmChannelConfig = (audio_channel_config_t) 0;
         ret.iChannelNames = 0;
 
         TU_LOG2("    Get terminal connector\r\n");
@@ -400,7 +401,7 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
   (void) ep_in;
   (void) cur_alt_setting;
 
-  tud_audio_write ((uint8_t *)test_buffer_audio, CFG_TUD_AUDIO_EP_SZ_IN);
+  tud_audio_write ((uint8_t *)test_buffer_audio, CFG_TUD_AUDIO_EP_SZ_IN - 2);
 
   return true;
 }
@@ -413,7 +414,7 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
   (void) ep_in;
   (void) cur_alt_setting;
 
-  for (size_t cnt = 0; cnt < CFG_TUD_AUDIO_EP_SZ_IN/2; cnt++)
+  for (size_t cnt = 0; cnt < (CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2; cnt++)
   {
     test_buffer_audio[cnt] = startVal++;
   }
diff --git a/examples/device/audio_test/src/plot_audio_samples.py b/examples/device/audio_test/src/plot_audio_samples.py
old mode 100644
new mode 100755
index 6e3c4978e..ea6aa661e
--- a/examples/device/audio_test/src/plot_audio_samples.py
+++ b/examples/device/audio_test/src/plot_audio_samples.py
@@ -1,7 +1,9 @@
+#!/usr/bin/env python3
 import sounddevice as sd
 import matplotlib.pyplot as plt
 import numpy as np
 import platform
+import csv
 
 if __name__ == '__main__':
 
@@ -31,4 +33,6 @@ if __name__ == '__main__':
     plt.ylabel('Amplitude')
     plt.title('MicNode')
     plt.show()
-    
\ No newline at end of file
+
+    samples = np.array(myrecording)
+    np.savetxt('Output.csv', samples, delimiter=",", fmt='%s')
diff --git a/examples/device/audio_test/src/tusb_config.h b/examples/device/audio_test/src/tusb_config.h
index 355ed1011..8c021e23c 100644
--- a/examples/device/audio_test/src/tusb_config.h
+++ b/examples/device/audio_test/src/tusb_config.h
@@ -106,6 +106,7 @@ extern "C" {
 //--------------------------------------------------------------------
 
 // Have a look into audio_device.h for all configurations
+#define CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE                              48000
 
 #define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                 TUD_AUDIO_MIC_ONE_CH_DESC_LEN
 #define CFG_TUD_AUDIO_FUNC_1_N_AS_INT                                 1                                       // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
@@ -114,9 +115,9 @@ extern "C" {
 #define CFG_TUD_AUDIO_ENABLE_EP_IN                                    1
 #define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX                    2                                       // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                            1                                       // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below - be aware: for different number of channels you need another descriptor!
-#define CFG_TUD_AUDIO_EP_SZ_IN                                        48 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX      // 48 Samples (48 kHz) x 2 Bytes/Sample x 1 Channel
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX                             CFG_TUD_AUDIO_EP_SZ_IN                  // Maximum EP IN size for all AS alternate settings used
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ                          CFG_TUD_AUDIO_EP_SZ_IN + 1
+#define CFG_TUD_AUDIO_EP_SZ_IN                                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX                             CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ                          (TUD_OPT_HIGH_SPEED ? 8 : 1) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
 
 #ifdef __cplusplus
 }
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index da3e203d7..9864377f6 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -44,7 +45,7 @@ tusb_desc_device_t const desc_device =
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = 0x0200,
 
-    // Use Interface Association Descriptor (IAD) for CDC
+    // Use Interface Association Descriptor (IAD) for Audio
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
@@ -96,7 +97,7 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-    // Interface count, string index, total length, attribute, power in mA
+    // Config number, interface count, string index, total length, attribute, power in mA
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
@@ -116,50 +117,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
 char const* string_desc_arr [] =
 {
-    (const char[]) { 0x09, 0x04 }, 	// 0: is supported language is English (0x0409)
-    "PaniRCorp",                   	// 1: Manufacturer
-    "MicNode",              		// 2: Product
-    "123456",                      	// 3: Serials, should use chip ID
-    "UAC2",                 	 	// 4: Audio Interface
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "PaniRCorp",                   // 1: Manufacturer
+    "MicNode",                     // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "UAC2",                        // 4: Audio Interface
+
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Convert ASCII string into UTF-16
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/audio_test_freertos/CMakeLists.txt b/examples/device/audio_test_freertos/CMakeLists.txt
new file mode 100644
index 000000000..6ce9e72fe
--- /dev/null
+++ b/examples/device/audio_test_freertos/CMakeLists.txt
@@ -0,0 +1,33 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/audio_test_freertos/Makefile b/examples/device/audio_test_freertos/Makefile
new file mode 100644
index 000000000..bd625b345
--- /dev/null
+++ b/examples/device/audio_test_freertos/Makefile
@@ -0,0 +1,15 @@
+RTOS = freertos
+include ../../build_system/make/make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE = \
+	src/main.c \
+	src/usb_descriptors.c
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/audio_test_freertos/README.md b/examples/device/audio_test_freertos/README.md
new file mode 100644
index 000000000..9477fcd78
--- /dev/null
+++ b/examples/device/audio_test_freertos/README.md
@@ -0,0 +1,19 @@
+# How to build example for Esp32s3
+1. Load idf environment variables (eg. using the esp-idf alias `get_idf` if configured)
+
+2. cd into examples directory
+```
+$ cd /tinyusb/examples/device/audio_test_freertos
+```
+
+3. Run cmake in project directory specifying the board
+```
+$ cmake -DBOARD=espressif_s3_devkitc -B build -G Ninja .
+$ ninja.exe -C build
+```
+
+4. Flash the binary onto the esp32-s3 by copy-paste of the full command output by the esp-idf build system replacing **(PORT)** with eg. /dev/ttyUSB0
+
+eg.
+
+> /home/kaspernyhus/.espressif/python_env/idf4.4_py3.8_env/bin/python ../../../../esp-idf/components/esptool_py/esptool/esptool.py -p /dev/ttyUSB0 -b 460800 --before default_reset --after hard_reset --chip esp32s3  write_flash --flash_mode dio --flash_size detect --flash_freq 80m 0x0 _build/espressif_s3_devkitc/bootloader/bootloader.bin 0x8000 _build/espressif_s3_devkitc/partition_table/partition-table.bin 0x10000 _build/espressif_s3_devkitc/audio_test_freertos.bin
diff --git a/examples/device/audio_test_freertos/sdkconfig.defaults b/examples/device/audio_test_freertos/sdkconfig.defaults
new file mode 100644
index 000000000..83871619e
--- /dev/null
+++ b/examples/device/audio_test_freertos/sdkconfig.defaults
@@ -0,0 +1,3 @@
+CONFIG_IDF_CMAKE=y
+CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
diff --git a/examples/device/audio_test_freertos/skip.txt b/examples/device/audio_test_freertos/skip.txt
new file mode 100644
index 000000000..650bf355b
--- /dev/null
+++ b/examples/device/audio_test_freertos/skip.txt
@@ -0,0 +1,16 @@
+mcu:CH32V103
+mcu:CH32V20X
+mcu:CH32V307
+mcu:CXD56
+mcu:F1C100S
+mcu:GD32VF103
+mcu:MCXA15
+mcu:MKL25ZXX
+mcu:MSP430x5xx
+mcu:RP2040
+mcu:SAMD11
+mcu:SAMX7X
+mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
+family:broadcom_32bit
+family:broadcom_64bit
diff --git a/examples/device/audio_test_freertos/src/CMakeLists.txt b/examples/device/audio_test_freertos/src/CMakeLists.txt
new file mode 100644
index 000000000..cef2b46ee
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c" "usb_descriptors.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/audio_test_freertos/src/main.c b/examples/device/audio_test_freertos/src/main.c
new file mode 100644
index 000000000..c5143c3fc
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/main.c
@@ -0,0 +1,511 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Reinhard Panhuber
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* plot_audio_samples.py requires following modules:
+ * $ sudo apt install libportaudio
+ * $ pip3 install sounddevice matplotlib
+ *
+ * Then run
+ * $ python3 plot_audio_samples.py
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+  // ESP-IDF need "freertos/" prefix in include path.
+  // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+  #include "freertos/FreeRTOS.h"
+  #include "freertos/semphr.h"
+  #include "freertos/queue.h"
+  #include "freertos/task.h"
+  #include "freertos/timers.h"
+
+  #define USBD_STACK_SIZE     4096
+#else
+
+  #include "FreeRTOS.h"
+  #include "semphr.h"
+  #include "queue.h"
+  #include "task.h"
+  #include "timers.h"
+
+  // Increase stack size when debug log is enabled
+  #define USBD_STACK_SIZE    (4*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t  usb_device_stack[USBD_STACK_SIZE];
+StaticTask_t usb_device_taskdef;
+#endif
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+bool mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; 				          // +1 for master channel 0
+uint16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; 					// +1 for master channel 0
+uint32_t sampFreq;
+uint8_t clkValid;
+
+// Range states
+audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; 			// Volume range state
+audio_control_range_4_n_t(1) sampleFreqRng; 						// Sample frequency range state
+
+// Audio test data
+uint16_t test_buffer_audio[(CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2];
+uint16_t startVal = 0;
+
+void led_blinking_task(void* param);
+void usb_device_task(void* param);
+void audio_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  // Init values
+  sampFreq = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
+  clkValid = 1;
+
+  sampleFreqRng.wNumSubRanges = 1;
+  sampleFreqRng.subrange[0].bMin = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
+  sampleFreqRng.subrange[0].bMax = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
+  sampleFreqRng.subrange[0].bRes = 0;
+
+#if configSUPPORT_STATIC_ALLOCATION
+  // blinky task
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+
+  // Create a task for tinyusb device stack
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+#else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+#endif
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+  #if !TUSB_MCU_VENDOR_ESPRESSIF
+    vTaskStartScheduler();
+  #endif
+
+  return 0;
+}
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+void app_main(void) {
+  main();
+}
+#endif
+
+// USB Device Driver task
+// This top level thread process all usb events and invoke callbacks
+void usb_device_task(void* param)
+{
+  (void) param;
+
+  // init device stack on configured roothub port
+  // This should be called after scheduler/kernel is started.
+  // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  // RTOS forever loop
+  while (1)
+  {
+    // tinyusb device task
+    tud_task();
+  }
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void) {
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void) {
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en) {
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// AUDIO Task
+//--------------------------------------------------------------------+
+
+void audio_task(void)
+{
+  // Yet to be filled - e.g. put meas data into TX FIFOs etc.
+  // asm("nop");
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when audio class specific set request received for an EP
+bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+  (void) pBuff;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) ep;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an interface
+bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+  (void) pBuff;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) itf;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+  uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+  (void) itf;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // If request is for our feature unit
+  if ( entityID == 2 )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_FU_CTRL_MUTE:
+        // Request uses format layout 1
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_1_t));
+
+        mute[channelNum] = ((audio_control_cur_1_t*) pBuff)->bCur;
+
+        TU_LOG2("    Set Mute: %d of channel: %u\r\n", mute[channelNum], channelNum);
+      return true;
+
+      case AUDIO_FU_CTRL_VOLUME:
+        // Request uses format layout 2
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
+
+        volume[channelNum] = (uint16_t) ((audio_control_cur_2_t*) pBuff)->bCur;
+
+        TU_LOG2("    Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
+      return true;
+
+        // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+      return false;
+    }
+  }
+  return false;    // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an EP
+bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) ep;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an interface
+bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) itf;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  // uint8_t itf = TU_U16_LOW(p_request->wIndex); 			// Since we have only one audio function implemented, we do not need the itf value
+  uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+  // Input terminal (Microphone input)
+  if (entityID == 1)
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_TE_CTRL_CONNECTOR:
+      {
+        // The terminal connector control only has a get request with only the CUR attribute.
+        audio_desc_channel_cluster_t ret;
+
+        // Those are dummy values for now
+        ret.bNrChannels = 1;
+        ret.bmChannelConfig = (audio_channel_config_t) 0;
+        ret.iChannelNames = 0;
+
+        TU_LOG2("    Get terminal connector\r\n");
+
+        return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+      }
+      break;
+
+        // Unknown/Unsupported control selector
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  // Feature unit
+  if (entityID == 2)
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_FU_CTRL_MUTE:
+        // Audio control mute cur parameter block consists of only one byte - we thus can send it right away
+        // There does not exist a range parameter block for mute
+        TU_LOG2("    Get Mute of channel: %u\r\n", channelNum);
+        return tud_control_xfer(rhport, p_request, &mute[channelNum], 1);
+
+      case AUDIO_FU_CTRL_VOLUME:
+        switch ( p_request->bRequest )
+        {
+          case AUDIO_CS_REQ_CUR:
+            TU_LOG2("    Get Volume of channel: %u\r\n", channelNum);
+            return tud_control_xfer(rhport, p_request, &volume[channelNum], sizeof(volume[channelNum]));
+
+          case AUDIO_CS_REQ_RANGE:
+            TU_LOG2("    Get Volume range of channel: %u\r\n", channelNum);
+
+            // Copy values - only for testing - better is version below
+            audio_control_range_2_n_t(1)
+            ret;
+
+            ret.wNumSubRanges = 1;
+            ret.subrange[0].bMin = -90;    // -90 dB
+            ret.subrange[0].bMax = 90;		// +90 dB
+            ret.subrange[0].bRes = 1; 		// 1 dB steps
+
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+
+            // Unknown/Unsupported control
+          default:
+            TU_BREAKPOINT();
+            return false;
+        }
+      break;
+
+        // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  // Clock Source unit
+  if ( entityID == 4 )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_CS_CTRL_SAM_FREQ:
+        // channelNum is always zero in this case
+        switch ( p_request->bRequest )
+        {
+          case AUDIO_CS_REQ_CUR:
+            TU_LOG2("    Get Sample Freq.\r\n");
+            return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+
+          case AUDIO_CS_REQ_RANGE:
+            TU_LOG2("    Get Sample Freq. range\r\n");
+            return tud_control_xfer(rhport, p_request, &sampleFreqRng, sizeof(sampleFreqRng));
+
+           // Unknown/Unsupported control
+          default:
+            TU_BREAKPOINT();
+            return false;
+        }
+      break;
+
+      case AUDIO_CS_CTRL_CLK_VALID:
+        // Only cur attribute exists for this request
+        TU_LOG2("    Get Sample Freq. valid\r\n");
+        return tud_control_xfer(rhport, p_request, &clkValid, sizeof(clkValid));
+
+      // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  TU_LOG2("  Unsupported entity: %d\r\n", entityID);
+  return false; 	// Yet not implemented
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void) rhport;
+  (void) itf;
+  (void) ep_in;
+  (void) cur_alt_setting;
+
+  tud_audio_write ((uint8_t *)test_buffer_audio, CFG_TUD_AUDIO_EP_SZ_IN - 2);
+
+  return true;
+}
+
+bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void) rhport;
+  (void) n_bytes_copied;
+  (void) itf;
+  (void) ep_in;
+  (void) cur_alt_setting;
+
+  for (size_t cnt = 0; cnt < (CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2; cnt++)
+  {
+    test_buffer_audio[cnt] = startVal++;
+  }
+
+  return true;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+  (void) p_request;
+  startVal = 0;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void* param) {
+  (void) param;
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  while (1) {
+    // Blink every interval ms
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    start_ms += blink_interval_ms;
+
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
+}
diff --git a/examples/device/audio_test_freertos/src/plot_audio_samples.py b/examples/device/audio_test_freertos/src/plot_audio_samples.py
new file mode 100755
index 000000000..46738eb3f
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/plot_audio_samples.py
@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+import sounddevice as sd
+import matplotlib.pyplot as plt
+import numpy as np
+import platform
+
+if __name__ == '__main__':
+
+    # If you got "ValueError: No input device matching", that is because your PC name example device
+    # differently from tested list below. Uncomment the next line to see full list and try to pick correct one
+    # print(sd.query_devices())
+
+    fs = 48000           # Sample rate
+    duration = 1000e-3    # Duration of recording
+
+    if platform.system() == 'Windows':
+        # MME is needed since there are more than one MicNode device APIs (at least in Windows)
+        device = 'Microphone (MicNode) MME'
+    elif platform.system() == 'Darwin':
+        device = 'MicNode'
+    else:
+        device ='default'
+
+    myrecording = sd.rec(int(duration * fs), samplerate=fs, channels=1, dtype='int16', device=device)
+    print('Waiting...')
+    sd.wait()  # Wait until recording is finished
+    print('Done!')
+
+    time = np.arange(0, duration, 1 / fs)  # time vector
+    plt.plot(time, myrecording)
+    plt.xlabel('Time [s]')
+    plt.ylabel('Amplitude')
+    plt.title('MicNode')
+    plt.show()
diff --git a/examples/device/audio_test_freertos/src/tusb_config.h b/examples/device/audio_test_freertos/src/tusb_config.h
new file mode 100644
index 000000000..61c5cbb96
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/tusb_config.h
@@ -0,0 +1,132 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+// This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS                 OPT_OS_FREERTOS
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TUSB_MCU_VENDOR_ESPRESSIF
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG              0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_AUDIO             1
+#define CFG_TUD_CDC               0
+#define CFG_TUD_MSC               0
+#define CFG_TUD_HID               0
+#define CFG_TUD_MIDI              0
+#define CFG_TUD_VENDOR            0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+// Have a look into audio_device.h for all configurations
+#define CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE                              48000
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                 TUD_AUDIO_MIC_ONE_CH_DESC_LEN
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT                                 1                                       // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ                              64                                      // Size of control request buffer
+
+#define CFG_TUD_AUDIO_ENABLE_EP_IN                                    1
+#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX                    2                                       // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                            1                                       // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below - be aware: for different number of channels you need another descriptor!
+#define CFG_TUD_AUDIO_EP_SZ_IN                                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX                             CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ                          (TUD_OPT_HIGH_SPEED ? 8 : 1) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/audio_test_freertos/src/usb_descriptors.c b/examples/device/audio_test_freertos/src/usb_descriptors.c
new file mode 100644
index 000000000..9864377f6
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/usb_descriptors.c
@@ -0,0 +1,181 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]     AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+    _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0200,
+
+    // Use Interface Association Descriptor (IAD) for Audio
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+  return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+enum
+{
+  ITF_NUM_AUDIO_CONTROL = 0,
+  ITF_NUM_AUDIO_STREAMING,
+  ITF_NUM_TOTAL
+};
+
+#define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_ONE_CH_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO   0x03
+
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
+  // nRF5x ISO can only be endpoint 8
+  #define EPNUM_AUDIO   0x08
+
+#else
+  #define EPNUM_AUDIO   0x01
+#endif
+
+uint8_t const desc_configuration[] =
+{
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
+};
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+  return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] =
+{
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "PaniRCorp",                   // 1: Manufacturer
+    "MicNode",                     // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "UAC2",                        // 4: Audio Interface
+
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt
new file mode 100644
index 000000000..6a7e68c3d
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/CMakeLists.txt
@@ -0,0 +1,33 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/audio_test_multi_rate/Makefile b/examples/device/audio_test_multi_rate/Makefile
new file mode 100644
index 000000000..7fa475da5
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/Makefile
@@ -0,0 +1,11 @@
+include ../../build_system/make/make.mk
+
+INC += \
+  src \
+  $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/audio_test_multi_rate/skip.txt b/examples/device/audio_test_multi_rate/skip.txt
new file mode 100644
index 000000000..65b137814
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/skip.txt
@@ -0,0 +1,4 @@
+mcu:SAMD11
+mcu:SAME5X
+mcu:SAMG
+family:espressif
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
new file mode 100644
index 000000000..8fa902a04
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -0,0 +1,529 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Reinhard Panhuber
+ * Copyright (c) 2022 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* plot_audio_samples.py requires following modules:
+ * $ sudo apt install libportaudio
+ * $ pip3 install sounddevice matplotlib
+ *
+ * Then run
+ * $ python3 plot_audio_samples.py
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+bool mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; 				          // +1 for master channel 0
+uint16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; 					// +1 for master channel 0
+uint32_t sampFreq;
+uint8_t bytesPerSample;
+uint8_t clkValid;
+
+// Range states
+// List of supported sample rates
+static const uint32_t sampleRatesList[] =
+{
+    32000, 48000, 96000
+};
+
+#define N_sampleRates  TU_ARRAY_SIZE(sampleRatesList)
+
+// Bytes per format of every Alt settings
+static const uint8_t bytesPerSampleAltList[CFG_TUD_AUDIO_FUNC_1_N_FORMATS] =
+{
+    CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX,
+    CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX,
+};
+
+audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; 			// Volume range state
+
+
+// Audio test data
+CFG_TUD_MEM_ALIGN uint8_t test_buffer_audio[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
+uint16_t startVal = 0;
+
+void led_blinking_task(void);
+void audio_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  // init device stack on configured roothub port
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  // Init values
+  sampFreq = sampleRatesList[0];
+  clkValid = 1;
+
+  while (1)
+  {
+    tud_task(); // tinyusb device task
+    led_blinking_task();
+    audio_task();
+  }
+
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// AUDIO Task
+//--------------------------------------------------------------------+
+
+void audio_task(void)
+{
+  // Yet to be filled - e.g. put meas data into TX FIFOs etc.
+  // asm("nop");
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when set interface is called, typically on start/stop streaming or format change
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void)rhport;
+  //uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+  uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+  // Clear buffer when streaming format is changed
+  if(alt != 0)
+  {
+    bytesPerSample = bytesPerSampleAltList[alt-1];
+  }
+  return true;
+}
+
+// Invoked when audio class specific set request received for an EP
+bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+  (void) pBuff;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) ep;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an interface
+bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+  (void) pBuff;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) itf;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+  uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+  (void) itf;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // If request is for our feature unit
+  if ( entityID == UAC2_ENTITY_FEATURE_UNIT )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_FU_CTRL_MUTE:
+        // Request uses format layout 1
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_1_t));
+
+        mute[channelNum] = ((audio_control_cur_1_t*) pBuff)->bCur;
+
+        TU_LOG2("    Set Mute: %d of channel: %u\r\n", mute[channelNum], channelNum);
+      return true;
+
+      case AUDIO_FU_CTRL_VOLUME:
+        // Request uses format layout 2
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
+
+        volume[channelNum] = (uint16_t) ((audio_control_cur_2_t*) pBuff)->bCur;
+
+        TU_LOG2("    Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
+      return true;
+
+        // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+      return false;
+    }
+  }
+
+  // Clock Source unit
+  if ( entityID == UAC2_ENTITY_CLOCK )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_CS_CTRL_SAM_FREQ:
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_4_t));
+
+        sampFreq = (uint32_t)((audio_control_cur_4_t *)pBuff)->bCur;
+
+        TU_LOG2("Clock set current freq: %" PRIu32 "\r\n", sampFreq);
+
+        return true;
+      break;
+
+      // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  return false;    // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an EP
+bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) ep;
+
+  //	return tud_control_xfer(rhport, p_request, &tmp, 1);
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an interface
+bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) itf;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  // uint8_t itf = TU_U16_LOW(p_request->wIndex); 			// Since we have only one audio function implemented, we do not need the itf value
+  uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+  // Input terminal (Microphone input)
+  if (entityID == UAC2_ENTITY_INPUT_TERMINAL)
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_TE_CTRL_CONNECTOR:
+      {
+        // The terminal connector control only has a get request with only the CUR attribute.
+        audio_desc_channel_cluster_t ret;
+
+        // Those are dummy values for now
+        ret.bNrChannels = 1;
+        ret.bmChannelConfig = 0;
+        ret.iChannelNames = 0;
+
+        TU_LOG2("    Get terminal connector\r\n");
+
+        return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+      }
+      break;
+
+        // Unknown/Unsupported control selector
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  // Feature unit
+  if (entityID == UAC2_ENTITY_FEATURE_UNIT)
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_FU_CTRL_MUTE:
+        // Audio control mute cur parameter block consists of only one byte - we thus can send it right away
+        // There does not exist a range parameter block for mute
+        TU_LOG2("    Get Mute of channel: %u\r\n", channelNum);
+        return tud_control_xfer(rhport, p_request, &mute[channelNum], 1);
+
+      case AUDIO_FU_CTRL_VOLUME:
+        switch ( p_request->bRequest )
+        {
+          case AUDIO_CS_REQ_CUR:
+            TU_LOG2("    Get Volume of channel: %u\r\n", channelNum);
+            return tud_control_xfer(rhport, p_request, &volume[channelNum], sizeof(volume[channelNum]));
+
+          case AUDIO_CS_REQ_RANGE:
+            TU_LOG2("    Get Volume range of channel: %u\r\n", channelNum);
+
+            // Copy values - only for testing - better is version below
+            audio_control_range_2_n_t(1)
+            ret;
+
+            ret.wNumSubRanges = 1;
+            ret.subrange[0].bMin = -90;    // -90 dB
+            ret.subrange[0].bMax = 30;		// +30 dB
+            ret.subrange[0].bRes = 1; 		// 1 dB steps
+
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+
+            // Unknown/Unsupported control
+          default:
+            TU_BREAKPOINT();
+            return false;
+        }
+      break;
+
+        // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  // Clock Source unit
+  if ( entityID == UAC2_ENTITY_CLOCK )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_CS_CTRL_SAM_FREQ:
+        // channelNum is always zero in this case
+        switch ( p_request->bRequest )
+        {
+          case AUDIO_CS_REQ_CUR:
+            TU_LOG2("    Get Sample Freq.\r\n");
+            return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+
+          case AUDIO_CS_REQ_RANGE:
+          {
+            TU_LOG2("    Get Sample Freq. range\r\n");
+            audio_control_range_4_n_t(N_sampleRates) rangef =
+            {
+                .wNumSubRanges = tu_htole16(N_sampleRates)
+            };
+            TU_LOG1("Clock get %d freq ranges\r\n", N_sampleRates);
+            for(uint8_t i = 0; i < N_sampleRates; i++)
+            {
+                rangef.subrange[i].bMin = (int32_t)sampleRatesList[i];
+                rangef.subrange[i].bMax = (int32_t)sampleRatesList[i];
+                rangef.subrange[i].bRes = 0;
+                TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+            }
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &rangef, sizeof(rangef));
+          }
+           // Unknown/Unsupported control
+          default:
+            TU_BREAKPOINT();
+            return false;
+        }
+      break;
+
+      case AUDIO_CS_CTRL_CLK_VALID:
+        // Only cur attribute exists for this request
+        TU_LOG2("    Get Sample Freq. valid\r\n");
+        return tud_control_xfer(rhport, p_request, &clkValid, sizeof(clkValid));
+
+      // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  TU_LOG2("  Unsupported entity: %d\r\n", entityID);
+  return false; 	// Yet not implemented
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void) rhport;
+  (void) itf;
+  (void) ep_in;
+  (void) cur_alt_setting;
+
+  tud_audio_write((uint8_t *)test_buffer_audio, (uint16_t)(sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000) * bytesPerSample));
+
+  return true;
+}
+
+bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void) rhport;
+  (void) n_bytes_copied;
+  (void) itf;
+  (void) ep_in;
+  (void) cur_alt_setting;
+
+  // 16bit
+  if(bytesPerSample == 2)
+  {
+    uint16_t* pData_16 = (uint16_t*)((void*)test_buffer_audio);
+    for (size_t cnt = 0; cnt < sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000); cnt++)
+    {
+      pData_16[cnt] = startVal++;
+    }
+  }
+  // 24bit in 32bit slot
+  else if(bytesPerSample == 4)
+  {
+    uint32_t* pData_32 = (uint32_t*)((void*)test_buffer_audio);
+    for (size_t cnt = 0; cnt < sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000); cnt++)
+    {
+      pData_32[cnt] = (uint32_t)startVal++ << 16U;
+    }
+  }
+
+  return true;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+  (void) p_request;
+  startVal = 0;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
new file mode 100755
index 000000000..1f33a003e
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
@@ -0,0 +1,38 @@
+#!/usr/bin/env python3
+import sounddevice as sd
+import matplotlib.pyplot as plt
+import numpy as np
+import platform
+import csv
+
+if __name__ == '__main__':
+
+    # If you got "ValueError: No input device matching", that is because your PC name example device
+    # differently from tested list below. Uncomment the next line to see full list and try to pick correct one
+    # print(sd.query_devices())
+
+    fs = 96000           # Sample rate
+    duration = 100e-3    # Duration of recording
+
+    if platform.system() == 'Windows':
+        # MME is needed since there are more than one MicNode device APIs (at least in Windows)
+        device = 'Microphone (MicNode) MME'
+    elif platform.system() == 'Darwin':
+        device = 'MicNode'
+    else:
+        device ='default'
+
+    myrecording = sd.rec(int(duration * fs), samplerate=fs, channels=1, dtype='int16', device=device)
+    print('Waiting...')
+    sd.wait()  # Wait until recording is finished
+    print('Done!')
+
+    time = np.arange(0, duration, 1 / fs)  # time vector
+    plt.plot(time, myrecording)
+    plt.xlabel('Time [s]')
+    plt.ylabel('Amplitude')
+    plt.title('MicNode')
+    plt.show()
+
+    samples = np.array(myrecording)
+    np.savetxt('Output.csv', samples, delimiter=",", fmt='%s')
diff --git a/examples/device/audio_test_multi_rate/src/tusb_config.h b/examples/device/audio_test_multi_rate/src/tusb_config.h
new file mode 100644
index 000000000..1c8288bce
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/tusb_config.h
@@ -0,0 +1,141 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS                 OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG              0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_AUDIO             1
+#define CFG_TUD_CDC               0
+#define CFG_TUD_MSC               0
+#define CFG_TUD_HID               0
+#define CFG_TUD_MIDI              0
+#define CFG_TUD_VENDOR            0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000
+
+// How many formats are used, need to adjust USB descriptor if changed
+#define CFG_TUD_AUDIO_FUNC_1_N_FORMATS                               2
+
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX                  16
+
+// 24bit in 32bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  24
+
+// Have a look into audio_device.h for all configurations
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                 TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESC_LEN
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT                                 1                                       // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ                              64                                      // Size of control request buffer
+
+#define CFG_TUD_AUDIO_ENABLE_EP_IN                                    1
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                            1                                       // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below - be aware: for different number of channels you need another descriptor!
+
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX                             TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)                  // Maximum EP IN size for all AS alternate settings used
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ                          CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.c b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
new file mode 100644
index 000000000..f50e70a25
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
@@ -0,0 +1,185 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2022 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]     AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+    _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0200,
+
+    // Use Interface Association Descriptor (IAD) for Audio
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+  return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+enum
+{
+  ITF_NUM_AUDIO_CONTROL = 0,
+  ITF_NUM_AUDIO_STREAMING,
+  ITF_NUM_TOTAL
+};
+
+#define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO   0x03
+
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
+  // nRF5x ISO can only be endpoint 8
+  #define EPNUM_AUDIO   0x08
+
+#else
+  #define EPNUM_AUDIO   0x01
+#endif
+
+uint8_t const desc_configuration[] =
+{
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_epin*/ 0x80 | EPNUM_AUDIO)
+};
+
+TU_VERIFY_STATIC(sizeof(desc_configuration) == CONFIG_TOTAL_LEN, "Incorrect size");
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+  return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] =
+{
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "PaniRCorp",                   // 1: Manufacturer
+    "MicNode",                     // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "UAC2",                        // 4: Audio Interface
+
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.h b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
new file mode 100644
index 000000000..8381e31f5
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
@@ -0,0 +1,102 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+// #include "tusb.h"
+
+// Unit numbers are arbitrary selected
+#define UAC2_ENTITY_CLOCK                   0x04
+#define UAC2_ENTITY_INPUT_TERMINAL          0x01
+#define UAC2_ENTITY_OUTPUT_TERMINAL         0x03
+#define UAC2_ENTITY_FEATURE_UNIT            0x02
+
+
+#define TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+    + TUD_AUDIO_DESC_STD_AC_LEN\
+    + TUD_AUDIO_DESC_CS_AC_LEN\
+    + TUD_AUDIO_DESC_CLK_SRC_LEN\
+    + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 1, Alternate 1 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 1, Alternate 2 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
+
+
+#define TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESCRIPTOR(_itfnum, _stridx, _epin) \
+  /* Standard Interface Association Descriptor (IAD) */\
+  TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  /* Standard AC Interface Descriptor(4.7.1) */\
+  TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+  /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+  TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_MICROPHONE, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+  /* Clock Source Descriptor(4.7.2.1) */\
+  TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_PRO_CLK, /*_ctrl*/ AUDIO_CTRL_RW << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS | AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_VAL_POS, /*_assocTerm*/ 0x01,  /*_stridx*/ 0x00),\
+  /* Input Terminal Descriptor(4.7.2.4) */\
+  TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS, /*_stridx*/ 0x00),\
+  /* Output Terminal Descriptor(4.7.2.5) */\
+  TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ UAC2_ENTITY_INPUT_TERMINAL, /*_srcid*/ UAC2_ENTITY_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+  /* Feature Unit Descriptor(4.7.2.8) */\
+  TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ UAC2_ENTITY_FEATURE_UNIT, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00),\
+  /* Standard AS Interface Descriptor(4.9.1) */\
+  /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+  TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
+  /* Standard AS Interface Descriptor(4.9.1) */\
+  /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+  TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\
+  /* Class-Specific AS Interface Descriptor(4.9.2) */\
+  TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+  /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+  TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
+  /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, /*_interval*/ 0x01),\
+  /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+  TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
+  /* Interface 1, Alternate 2 - alternate interface for data streaming */\
+  TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\
+  /* Class-Specific AS Interface Descriptor(4.9.2) */\
+  TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+  /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+  TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
+  /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN, /*_interval*/ 0x01),\
+  /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+  TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
+
+
+#endif
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 37113578e..9a604a732 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -1,42 +1,37 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
-# Check for -DFAMILY=
-if(FAMILY MATCHES "^esp32s[2-3]")
-  # use BOARD-Directory name for project id
-  get_filename_component(PROJECT ${CMAKE_CURRENT_SOURCE_DIR} NAME)
-  set(PROJECT ${BOARD}-${PROJECT})
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-  # TOP is absolute path to root directory of TinyUSB git repo
-  set(TOP "../../..")
-  get_filename_component(TOP "${TOP}" REALPATH)
+project(${PROJECT} C CXX ASM)
 
-  project(${PROJECT})
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
-else()
-
-  # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
-  family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-
-  project(${PROJECT})
-
-  # Checks this example is valid for the family and initializes the project
-  family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
-
-  add_executable(${PROJECT})
-
-  # Example source
-  target_sources(${PROJECT} PUBLIC
-          ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-          )
-
-  # Example include
-  target_include_directories(${PROJECT} PUBLIC
-          ${CMAKE_CURRENT_SOURCE_DIR}/src
-          )
-
-  # Configure compilation flags and libraries for the example... see the corresponding function
-  # in hw/bsp/FAMILY/family.cmake for details.
-  family_configure_device_example(${PROJECT})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
 endif()
+
+if (RTOS STREQUAL zephyr)
+  set(EXE_NAME app)
+else()
+  set(EXE_NAME ${PROJECT})
+  add_executable(${EXE_NAME})
+endif()
+
+# Example source
+target_sources(${EXE_NAME} PRIVATE
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  )
+
+# Example include
+target_include_directories(${EXE_NAME} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${EXE_NAME} ${RTOS})
diff --git a/examples/device/board_test/Makefile b/examples/device/board_test/Makefile
index b65575ce6..7fa475da5 100644
--- a/examples/device/board_test/Makefile
+++ b/examples/device/board_test/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
   src \
@@ -9,10 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# board_test example is special example that doesn't enable device or host stack
-# This can cause some TinyUSB API missing, this hack to allow us to fill those API
-# to pass the compilation process
-CFLAGS +=	\
-	-D"tud_int_handler(x)= " \
-
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/board_test/src/CMakeLists.txt b/examples/device/board_test/src/CMakeLists.txt
index e4e1f4e9a..8d85dcafd 100644
--- a/examples/device/board_test/src/CMakeLists.txt
+++ b/examples/device/board_test/src/CMakeLists.txt
@@ -1,17 +1,3 @@
-# FAMILY = esp32sx
 idf_component_register(SRCS "main.c"
                     INCLUDE_DIRS "."
-                    REQUIRES freertos soc)
-                    
-file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
-
-if(EXISTS ${board_cmake})
-    include(${board_cmake})
-endif()
-
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
-  "${TOP}/hw"
-  "${TOP}/src"
-)
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index 0289ca15f..2269d45f1 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -26,39 +26,31 @@
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
-
-#include "bsp/board.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF PROTYPES
-//--------------------------------------------------------------------+
+#include "bsp/board_api.h"
 
 /* Blink pattern
  * - 250 ms  : button is not pressed
  * - 1000 ms : button is pressed (and hold)
  */
-enum  {
+enum {
   BLINK_PRESSED = 250,
   BLINK_UNPRESSED = 1000
 };
 
 #define HELLO_STR   "Hello from TinyUSB\r\n"
 
-int main(void)
-{
+int main(void) {
   board_init();
   board_led_write(true);
 
   uint32_t start_ms = 0;
   bool led_state = false;
 
-  while (1)
-  {
+  while (1) {
     uint32_t interval_ms = board_button_read() ? BLINK_PRESSED : BLINK_UNPRESSED;
 
     // Blink and print every interval ms
-    if ( !(board_millis() - start_ms < interval_ms) )
-    {
+    if (!(board_millis() - start_ms < interval_ms)) {
       board_uart_write(HELLO_STR, strlen(HELLO_STR));
 
       start_ms = board_millis();
@@ -69,18 +61,14 @@ int main(void)
 
     // echo
     uint8_t ch;
-    if ( board_uart_read(&ch, 1) > 0 )
-    {
+    if (board_uart_read(&ch, 1) > 0) {
       board_uart_write(&ch, 1);
     }
   }
-
-  return 0;
 }
 
-#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
-void app_main(void)
-{
+#if TUSB_MCU_VENDOR_ESPRESSIF
+void app_main(void) {
   main();
 }
 #endif
diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h
index 5aea4fd2c..8ac3bc8de 100644
--- a/examples/device/board_test/src/tusb_config.h
+++ b/examples/device/board_test/src/tusb_config.h
@@ -43,6 +43,11 @@
   #define CFG_TUSB_OS               OPT_OS_NONE
 #endif
 
+// Espressif IDF requires "freertos/" prefix in include path
+#if TUSB_MCU_VENDOR_ESPRESSIF
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
 // This example only test LED & GPIO, disable both device and host stack
 #define CFG_TUD_ENABLED   0
 #define CFG_TUH_ENABLED   0
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index abc4d91da..6a7e68c3d 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -1,28 +1,33 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/cdc_dual_ports/Makefile b/examples/device/cdc_dual_ports/Makefile
index 5a455078e..7fa475da5 100644
--- a/examples/device/cdc_dual_ports/Makefile
+++ b/examples/device/cdc_dual_ports/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
   src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/cdc_dual_ports/skip.txt b/examples/device/cdc_dual_ports/skip.txt
new file mode 100644
index 000000000..75184e5e5
--- /dev/null
+++ b/examples/device/cdc_dual_ports/skip.txt
@@ -0,0 +1,2 @@
+board:stm32f407disco
+board:stm32f411disco
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 0264f0566..63ae8a8c9 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -28,44 +28,57 @@
 #include <string.h>
 #include <ctype.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
-//------------- prototypes -------------//
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+static void led_blinking_task(void);
 static void cdc_task(void);
 
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
 
-  while (1)
-  {
-    tud_task(); // tinyusb device task
-    cdc_task();
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
   }
 
-  return 0;
+  while (1) {
+    tud_task(); // tinyusb device task
+    cdc_task();
+    led_blinking_task();
+  }
 }
 
 // echo to either Serial0 or Serial1
 // with Serial0 as all lower case, Serial1 as all upper case
-static void echo_serial_port(uint8_t itf, uint8_t buf[], uint32_t count)
-{
+static void echo_serial_port(uint8_t itf, uint8_t buf[], uint32_t count) {
   uint8_t const case_diff = 'a' - 'A';
 
-  for(uint32_t i=0; i<count; i++)
-  {
-    if (itf == 0)
-    {
+  for (uint32_t i = 0; i < count; i++) {
+    if (itf == 0) {
       // echo back 1st port as lower case
       if (isupper(buf[i])) buf[i] += case_diff;
-    }
-    else
-    {
+    } else {
       // echo back 2nd port as upper case
       if (islower(buf[i])) buf[i] -= case_diff;
     }
@@ -75,21 +88,29 @@ static void echo_serial_port(uint8_t itf, uint8_t buf[], uint32_t count)
   tud_cdc_n_write_flush(itf);
 }
 
+// Invoked when device is mounted
+void tud_mount_cb(void) {
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void) {
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+
 //--------------------------------------------------------------------+
 // USB CDC
 //--------------------------------------------------------------------+
-static void cdc_task(void)
-{
+static void cdc_task(void) {
   uint8_t itf;
 
-  for (itf = 0; itf < CFG_TUD_CDC; itf++)
-  {
+  for (itf = 0; itf < CFG_TUD_CDC; itf++) {
     // connected() check for DTR bit
     // Most but not all terminal client set this when making connection
     // if ( tud_cdc_n_connected(itf) )
     {
-      if ( tud_cdc_n_available(itf) )
-      {
+      if (tud_cdc_n_available(itf)) {
         uint8_t buf[64];
 
         uint32_t count = tud_cdc_n_read(itf, buf, sizeof(buf));
@@ -101,3 +122,38 @@ static void cdc_task(void)
     }
   }
 }
+
+// Invoked when cdc when line state changed e.g connected/disconnected
+// Use to reset to DFU when disconnect with 1200 bps
+void tud_cdc_line_state_cb(uint8_t instance, bool dtr, bool rts) {
+  (void)rts;
+
+  // DTR = false is counted as disconnected
+  if (!dtr) {
+    // touch1200 only with first CDC instance (Serial)
+    if (instance == 0) {
+      cdc_line_coding_t coding;
+      tud_cdc_get_line_coding(&coding);
+      if (coding.bit_rate == 1200) {
+        if (board_reset_to_bootloader) {
+          board_reset_to_bootloader();
+        }
+      }
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void) {
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index cda1b63b6..7776eb958 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,13 +23,14 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
  * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
  *
  * Auto ProductID layout's Bitmap:
- *   [MSB]       MIDI | HID | MSC | CDC          [LSB]
+ *   [MSB]         HID | MSC | CDC          [LSB]
  */
 #define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
@@ -97,8 +98,19 @@ enum
   #define EPNUM_CDC_1_OUT     0x05
   #define EPNUM_CDC_1_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
-  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_CDC_0_NOTIF   0x83
+  #define EPNUM_CDC_0_OUT     0x02
+  #define EPNUM_CDC_0_IN      0x81
+
+  #define EPNUM_CDC_1_NOTIF   0x86
+  #define EPNUM_CDC_1_OUT     0x05
+  #define EPNUM_CDC_1_IN      0x84
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_0_NOTIF   0x81
   #define EPNUM_CDC_0_OUT     0x02
@@ -202,52 +214,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB CDC",                 // 4: CDC Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index fa6e83b7e..b07f92342 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -1,29 +1,40 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
+#set_property(GLOBAL PROPERTY USE_FOLDERS ON)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
-add_executable(${PROJECT})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+if (RTOS STREQUAL zephyr)
+  set(EXE_NAME app)
+else()
+  set(EXE_NAME ${PROJECT})
+  add_executable(${EXE_NAME})
+endif()
 
 # Example source
-target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+target_sources(${EXE_NAME} PRIVATE
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
-target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+target_include_directories(${EXE_NAME} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${EXE_NAME} ${RTOS})
diff --git a/examples/device/cdc_msc/Makefile b/examples/device/cdc_msc/Makefile
index 69b633fea..0c2e37180 100644
--- a/examples/device/cdc_msc/Makefile
+++ b/examples/device/cdc_msc/Makefile
@@ -1,12 +1,15 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
 	$(TOP)/hw \
 
 # Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE += \
+  src/main.c \
+  src/msc_disk.c \
+  src/usb_descriptors.c \
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/cdc_msc/prj.conf b/examples/device/cdc_msc/prj.conf
new file mode 100644
index 000000000..2f5139d9d
--- /dev/null
+++ b/examples/device/cdc_msc/prj.conf
@@ -0,0 +1,6 @@
+CONFIG_GPIO=y
+CONFIG_FPU=y
+CONFIG_NO_OPTIMIZATIONS=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_NRFX_POWER=y
+CONFIG_NRFX_UARTE0=y
diff --git a/examples/device/cdc_msc/skip.txt b/examples/device/cdc_msc/skip.txt
index d844feae8..b6252e405 100644
--- a/examples/device/cdc_msc/skip.txt
+++ b/examples/device/cdc_msc/skip.txt
@@ -1 +1,3 @@
-mcu:SAMD11
\ No newline at end of file
+mcu:SAMD11
+family:espressif
+board:ch32v203g_r0_1v0
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index c3666763b..f36c910d7 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,11 +23,7 @@
  *
  */
 
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
@@ -39,7 +35,7 @@
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
-enum  {
+enum {
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
@@ -51,22 +47,26 @@ void led_blinking_task(void);
 void cdc_task(void);
 
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
 
-  while (1)
-  {
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  while (1) {
     tud_task(); // tinyusb device task
     led_blinking_task();
 
     cdc_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -74,46 +74,40 @@ int main(void)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
-  blink_interval_ms = BLINK_MOUNTED;
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 
 //--------------------------------------------------------------------+
 // USB CDC
 //--------------------------------------------------------------------+
-void cdc_task(void)
-{
+void cdc_task(void) {
   // connected() check for DTR bit
   // Most but not all terminal client set this when making connection
   // if ( tud_cdc_connected() )
   {
     // connected and there are data available
-    if ( tud_cdc_available() )
-    {
-      // read datas
+    if (tud_cdc_available()) {
+      // read data
       char buf[64];
       uint32_t count = tud_cdc_read(buf, sizeof(buf));
       (void) count;
@@ -129,37 +123,32 @@ void cdc_task(void)
 }
 
 // Invoked when cdc when line state changed e.g connected/disconnected
-void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
-{
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) {
   (void) itf;
   (void) rts;
 
   // TODO set some indicator
-  if ( dtr )
-  {
+  if (dtr) {
     // Terminal connected
-  }else
-  {
+  } else {
     // Terminal disconnected
   }
 }
 
 // Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
+void tud_cdc_rx_cb(uint8_t itf) {
   (void) itf;
 }
 
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index e67e381ce..d325d77fa 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
@@ -190,7 +190,14 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
   (void) lun;
 
   // out of ramdisk
-  if ( lba >= DISK_BLOCK_NUM ) return -1;
+  if ( lba >= DISK_BLOCK_NUM ) {
+    return -1;
+  }
+
+  // Check for overflow of offset + bufsize
+  if ( offset + bufsize > DISK_BLOCK_SIZE ) {
+    return -1;
+  }
 
   uint8_t const* addr = msc_disk[lba] + offset;
   memcpy(buffer, addr, bufsize);
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 6b59ed50f..4b6b88041 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -41,35 +42,33 @@
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
-  .bLength            = sizeof(tusb_desc_device_t),
-  .bDescriptorType    = TUSB_DESC_DEVICE,
-  .bcdUSB             = USB_BCD,
+tusb_desc_device_t const desc_device = {
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = USB_BCD,
 
-  // Use Interface Association Descriptor (IAD) for CDC
-  // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
-  .bDeviceClass       = TUSB_CLASS_MISC,
-  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
-  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    // Use Interface Association Descriptor (IAD) for CDC
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
 
-  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-  .idVendor           = USB_VID,
-  .idProduct          = USB_PID,
-  .bcdDevice          = 0x0100,
+    .idVendor           = USB_VID,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
 
-  .iManufacturer      = 0x01,
-  .iProduct           = 0x02,
-  .iSerialNumber      = 0x03,
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
 
-  .bNumConfigurations = 0x01
+    .bNumConfigurations = 0x01
 };
 
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
+uint8_t const *tud_descriptor_device_cb(void) {
   return (uint8_t const *) &desc_device;
 }
 
@@ -77,8 +76,7 @@ uint8_t const * tud_descriptor_device_cb(void)
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
-enum
-{
+enum {
   ITF_NUM_CDC = 0,
   ITF_NUM_CDC_DATA,
   ITF_NUM_MSC,
@@ -95,19 +93,7 @@ enum
   #define EPNUM_MSC_OUT     0x05
   #define EPNUM_MSC_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
-  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
-  //    e.g EP1 OUT & EP1 IN cannot exist together
-  #define EPNUM_CDC_NOTIF   0x81
-  #define EPNUM_CDC_OUT     0x02
-  #define EPNUM_CDC_IN      0x83
-
-  #define EPNUM_MSC_OUT     0x04
-  #define EPNUM_MSC_IN      0x85
-
 #elif CFG_TUSB_MCU == OPT_MCU_CXD56
-  // CXD56 doesn't support a same endpoint number with different direction IN and OUT
-  //    e.g EP1 OUT & EP1 IN cannot exist together
   // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
   // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
   #define EPNUM_CDC_NOTIF   0x83
@@ -117,8 +103,8 @@ enum
   #define EPNUM_MSC_OUT     0x05
   #define EPNUM_MSC_IN      0x84
 
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
-  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_NOTIF   0x81
   #define EPNUM_CDC_OUT     0x02
@@ -140,67 +126,62 @@ enum
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN)
 
 // full speed configuration
-uint8_t const desc_fs_configuration[] =
-{
-  // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+    // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
 
-  // Interface number, string index, EP Out & EP In address, EP size
-  TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64),
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64),
 };
 
 #if TUD_OPT_HIGH_SPEED
 // Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
 
 // high speed configuration
-uint8_t const desc_hs_configuration[] =
-{
-  // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+uint8_t const desc_hs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
+    // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
 
-  // Interface number, string index, EP Out & EP In address, EP size
-  TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
 };
 
 // other speed configuration
 uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
 
 // device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
-tusb_desc_device_qualifier_t const desc_device_qualifier =
-{
-  .bLength            = sizeof(tusb_desc_device_qualifier_t),
-  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
-  .bcdUSB             = USB_BCD,
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength            = sizeof(tusb_desc_device_qualifier_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+    .bcdUSB             = USB_BCD,
 
-  .bDeviceClass       = TUSB_CLASS_MISC,
-  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
-  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
 
-  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
-  .bNumConfigurations = 0x01,
-  .bReserved          = 0x00
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved          = 0x00
 };
 
 // Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
 // device_qualifier descriptor describes information about a high-speed capable device that would
 // change if the device were operating at the other speed. If not highspeed capable stall this request.
-uint8_t const* tud_descriptor_device_qualifier_cb(void)
-{
-  return (uint8_t const*) &desc_device_qualifier;
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const *) &desc_device_qualifier;
 }
 
 // Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 // Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
-uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
-{
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
 
   // if link speed is high return fullspeed config, and vice versa
@@ -220,13 +201,12 @@ uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
 
 #if TUD_OPT_HIGH_SPEED
   // Although we are highspeed, host may be fullspeed.
-  return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_hs_configuration : desc_fs_configuration;
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration;
 #else
   return desc_fs_configuration;
 #endif
@@ -236,53 +216,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
-// array of pointer to string descriptors
-char const* string_desc_arr [] =
-{
-  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
-  "TinyUSB",                     // 1: Manufacturer
-  "TinyUSB Device",              // 2: Product
-  "123456789012",                // 3: Serials, should use chip ID
-  "TinyUSB CDC",                 // 4: CDC Interface
-  "TinyUSB MSC",                 // 5: MSC Interface
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
 };
 
-static uint16_t _desc_str[32];
+// array of pointer to string descriptors
+char const *string_desc_arr[] = {
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "TinyUSB",                     // 1: Manufacturer
+    "TinyUSB Device",              // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "TinyUSB CDC",                 // 4: CDC Interface
+    "TinyUSB MSC",                 // 5: MSC Interface
+};
+
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 639dde99a..f7636a07a 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -1,22 +1,34 @@
-cmake_minimum_required(VERSION 3.5)
-
-# TOP is absolute path to root directory of TinyUSB git repo
-# needed for esp32sx build. TOOD could be removed later on
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
-# Check for -DFAMILY=
-if(FAMILY MATCHES "^esp32s[2-3]")
-else()
-  message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
 endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 3352dd37d..10cff57a0 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -1,38 +1,16 @@
-DEPS_SUBMODULES += lib/FreeRTOS-Kernel
-
-include ../../../tools/top.mk
-include ../../make.mk
-
-FREERTOS_SRC = lib/FreeRTOS-Kernel
+RTOS = freertos
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
-	src/FreeRTOSConfig \
 	$(TOP)/hw \
-	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)
-	
+
 # Example source
 EXAMPLE_SOURCE = \
-	src/freertos_hook.c \
 	src/main.c \
 	src/msc_disk.c \
 	src/usb_descriptors.c
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# FreeRTOS source, all files in port folder
-SRC_C += \
-	$(FREERTOS_SRC)/list.c \
-	$(FREERTOS_SRC)/queue.c \
-	$(FREERTOS_SRC)/tasks.c \
-	$(FREERTOS_SRC)/timers.c \
-	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
-
-# Suppress FreeRTOS warnings
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
-
-# FreeRTOS (lto + Os) linker issue
-LDFLAGS += -Wl,--undefined=vTaskSwitchContext
-
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt
index 1ee51a9d4..b73a6d8dd 100644
--- a/examples/device/cdc_msc_freertos/skip.txt
+++ b/examples/device/cdc_msc_freertos/skip.txt
@@ -1,11 +1,17 @@
+mcu:CH32V103
+mcu:CH32V20X
+mcu:CH32V307
 mcu:CXD56
 mcu:F1C100S
 mcu:GD32VF103
+mcu:MCXA15
 mcu:MKL25ZXX
 mcu:MSP430x5xx
 mcu:RP2040
 mcu:SAMD11
 mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
+mcu:STM32L0
 family:broadcom_32bit
-family:broadcom_64bit
\ No newline at end of file
+family:broadcom_64bit
diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index 9216e2b49..fee264363 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -1,35 +1,4 @@
+# This file is for ESP-IDF only
 idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c"
                     INCLUDE_DIRS "."
-                    REQUIRES freertos soc)
-
-file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
-
-if(EXISTS ${board_cmake})
-    include(${board_cmake})
-endif()
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/hw"
-  "${TOP}/src"
-)
-
-target_compile_definitions(${COMPONENT_TARGET} PUBLIC
-  ESP_PLATFORM
-)
-
-target_sources(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/src/tusb.c"
-  "${TOP}/src/common/tusb_fifo.c"
-  "${TOP}/src/device/usbd.c"
-  "${TOP}/src/device/usbd_control.c"
-  "${TOP}/src/class/cdc/cdc_device.c"
-  "${TOP}/src/class/dfu/dfu_rt_device.c"
-  "${TOP}/src/class/hid/hid_device.c"
-  "${TOP}/src/class/midi/midi_device.c"
-  "${TOP}/src/class/msc/msc_device.c"
-  "${TOP}/src/class/net/ecm_rndis_device.c"
-  "${TOP}/src/class/net/ncm_device.c"
-  "${TOP}/src/class/usbtmc/usbtmc_device.c"
-  "${TOP}/src/class/vendor/vendor_device.c"
-  "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c"
-)
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/cdc_msc_freertos/src/freertos_hook.c b/examples/device/cdc_msc_freertos/src/freertos_hook.c
deleted file mode 100644
index ab885947c..000000000
--- a/examples/device/cdc_msc_freertos/src/freertos_hook.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "FreeRTOS.h"
-#include "task.h"
-#include "common/tusb_common.h"
-
-
-void vApplicationMallocFailedHook(void)
-{
-  taskDISABLE_INTERRUPTS();
-  TU_ASSERT(false, );
-}
-
-void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName)
-{
-  (void) pxTask;
-  (void) pcTaskName;
-
-  taskDISABLE_INTERRUPTS();
-  TU_ASSERT(false, );
-}
-
-/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an
- * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
- * used by the Idle task. */
-void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
-{
-  /* If the buffers to be provided to the Idle task are declared inside this
-   * function then they must be declared static - otherwise they will be allocated on
-   * the stack and so not exists after this function exits. */
-  static StaticTask_t xIdleTaskTCB;
-  static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
-
-  /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
-    state will be stored. */
-  *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
-
-  /* Pass out the array that will be used as the Idle task's stack. */
-  *ppxIdleTaskStackBuffer = uxIdleTaskStack;
-
-  /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
-    Note that, as the array is necessarily of type StackType_t,
-    configMINIMAL_STACK_SIZE is specified in words, not bytes. */
-  *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
-}
-
-/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
- * application must provide an implementation of vApplicationGetTimerTaskMemory()
- * to provide the memory that is used by the Timer service task. */
-void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
-{
-  /* If the buffers to be provided to the Timer task are declared inside this
-   * function then they must be declared static - otherwise they will be allocated on
-   * the stack and so not exists after this function exits. */
-  static StaticTask_t xTimerTaskTCB;
-  static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
-
-  /* Pass out a pointer to the StaticTask_t structure in which the Timer
-    task's state will be stored. */
-  *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
-
-  /* Pass out the array that will be used as the Timer task's stack. */
-  *ppxTimerTaskStackBuffer = uxTimerTaskStack;
-
-  /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
-    Note that, as the array is necessarily of type StackType_t,
-    configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
-  *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
-}
-
-#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X
-#include "iodefine.h"
-void vApplicationSetupTimerInterrupt(void)
-{
-  /* Enable CMT0 */
-  SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
-  MSTP(CMT0)       = 0;
-  SYSTEM.PRCR.WORD = (0xA5u<<8);
-
-  CMT0.CMCNT      = 0;
-  CMT0.CMCOR      = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
-  CMT0.CMCR.WORD  = TU_BIT(6) | 2;
-  IR(CMT0, CMI0)  = 0;
-  IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY;
-  IEN(CMT0, CMI0) = 1;
-  CMT.CMSTR0.BIT.STR0 = 1;
-}
-#endif
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 755220c13..c51e8ea81 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,32 +27,21 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-  // ESP-IDF need "freertos/" prefix in include path.
-  // CFG_TUSB_OS_INC_PATH should be defined accordingly.
-  #include "freertos/FreeRTOS.h"
-  #include "freertos/semphr.h"
-  #include "freertos/queue.h"
-  #include "freertos/task.h"
-  #include "freertos/timers.h"
-
+#if TUSB_MCU_VENDOR_ESPRESSIF
   #define USBD_STACK_SIZE     4096
 #else
-  #include "FreeRTOS.h"
-  #include "semphr.h"
-  #include "queue.h"
-  #include "task.h"
-  #include "timers.h"
-
   // Increase stack size when debug log is enabled
   #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
+#define CDC_STACK_SIZE      configMINIMAL_STACK_SIZE
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+
 //--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF PROTYPES
+// MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
 
 /* Blink pattern
@@ -60,77 +49,82 @@
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
-enum  {
+enum {
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
 };
 
-// static timer
-StaticTimer_t blinky_tmdef;
-TimerHandle_t blinky_tm;
-
 // static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
 StackType_t  usb_device_stack[USBD_STACK_SIZE];
 StaticTask_t usb_device_taskdef;
 
-// static task for cdc
-#define CDC_STACK_SZIE      configMINIMAL_STACK_SIZE
-StackType_t  cdc_stack[CDC_STACK_SZIE];
+StackType_t  cdc_stack[CDC_STACK_SIZE];
 StaticTask_t cdc_taskdef;
+#endif
 
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
-void led_blinky_cb(TimerHandle_t xTimer);
-void usb_device_task(void* param);
-void cdc_task(void* params);
+static void usb_device_task(void *param);
+void led_blinking_task(void* param);
+void cdc_task(void *params);
 
 //--------------------------------------------------------------------+
 // Main
 //--------------------------------------------------------------------+
 
-int main(void)
-{
+int main(void) {
   board_init();
 
-  // soft timer for blinky
-  blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
-  xTimerStart(blinky_tm, 0);
-
-  // Create a task for tinyusb device stack
-  (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
-
-  // Create CDC task
-  (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+  // Create task for: tinyusb, blinky, cdc
+#if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+  xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, cdc_stack, &cdc_taskdef);
+#else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
+#endif
 
+#if !TUSB_MCU_VENDOR_ESPRESSIF
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   vTaskStartScheduler();
 #endif
 
   return 0;
 }
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-void app_main(void)
-{
+#if TUSB_MCU_VENDOR_ESPRESSIF
+void app_main(void) {
   main();
 }
 #endif
 
 // USB Device Driver task
 // This top level thread process all usb events and invoke callbacks
-void usb_device_task(void* param)
-{
+static void usb_device_task(void *param) {
   (void) param;
 
   // init device stack on configured roothub port
   // This should be called after scheduler/kernel is started.
   // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   // RTOS forever loop
-  while (1)
-  {
+  while (1) {
     // put this thread to waiting state until there is new events
     tud_task();
 
@@ -144,49 +138,42 @@ void usb_device_task(void* param)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+void tud_mount_cb(void) {
+  blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
+void tud_umount_cb(void) {
+  blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
+  blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
 // USB CDC
 //--------------------------------------------------------------------+
-void cdc_task(void* params)
-{
+void cdc_task(void *params) {
   (void) params;
 
   // RTOS forever loop
-  while ( 1 )
-  {
+  while (1) {
     // connected() check for DTR bit
     // Most but not all terminal client set this when making connection
     // if ( tud_cdc_connected() )
     {
       // There are data available
-      while ( tud_cdc_available() )
-      {
+      while (tud_cdc_available()) {
         uint8_t buf[64];
 
         // read and echo back
@@ -209,35 +196,37 @@ void cdc_task(void* params)
 }
 
 // Invoked when cdc when line state changed e.g connected/disconnected
-void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
-{
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) {
   (void) itf;
   (void) rts;
 
   // TODO set some indicator
-  if ( dtr )
-  {
+  if (dtr) {
     // Terminal connected
-  }else
-  {
+  } else {
     // Terminal disconnected
   }
 }
 
 // Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
+void tud_cdc_rx_cb(uint8_t itf) {
   (void) itf;
 }
 
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-void led_blinky_cb(TimerHandle_t xTimer)
-{
-  (void) xTimer;
+void led_blinking_task(void* param) {
+  (void) param;
+  static uint32_t start_ms = 0;
   static bool led_state = false;
 
-  board_led_write(led_state);
-  led_state = 1 - led_state; // toggle
+  while (1) {
+    // Blink every interval ms
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    start_ms += blink_interval_ms;
+
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
 }
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index a895f4738..d325d77fa 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,11 +23,14 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
 
+// whether host does safe-eject
+static bool ejected = false;
+
 // Some MCU doesn't have enough 8KB SRAM to store the whole disk
 // We will use Flash as read-only disk with board that has
 // CFG_EXAMPLE_MSC_READONLY defined
@@ -137,7 +140,14 @@ bool tud_msc_test_unit_ready_cb(uint8_t lun)
 {
   (void) lun;
 
-  return true; // RAM disk is always ready
+  // RAM disk is ready until ejected
+  if (ejected) {
+    // Additional Sense 3A-00 is NOT_FOUND
+    tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3a, 0x00);
+    return false;
+  }
+
+  return true;
 }
 
 // Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size
@@ -166,6 +176,7 @@ bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, boo
     }else
     {
       // unload disk storage
+      ejected = true;
     }
   }
 
@@ -179,12 +190,30 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
   (void) lun;
 
   // out of ramdisk
-  if ( lba >= DISK_BLOCK_NUM ) return -1;
+  if ( lba >= DISK_BLOCK_NUM ) {
+    return -1;
+  }
+
+  // Check for overflow of offset + bufsize
+  if ( offset + bufsize > DISK_BLOCK_SIZE ) {
+    return -1;
+  }
 
   uint8_t const* addr = msc_disk[lba] + offset;
   memcpy(buffer, addr, bufsize);
 
-  return bufsize;
+  return (int32_t) bufsize;
+}
+
+bool tud_msc_is_writable_cb (uint8_t lun)
+{
+  (void) lun;
+
+#ifdef CFG_EXAMPLE_MSC_READONLY
+  return false;
+#else
+  return true;
+#endif
 }
 
 // Callback invoked when received WRITE10 command.
@@ -203,7 +232,7 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
   (void) lba; (void) offset; (void) buffer;
 #endif
 
-  return bufsize;
+  return (int32_t) bufsize;
 }
 
 // Callback invoked when received an SCSI command not in built-in list below
@@ -237,14 +266,14 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
   {
     if(in_xfer)
     {
-      memcpy(buffer, response, resplen);
+      memcpy(buffer, response, (size_t) resplen);
     }else
     {
       // SCSI output
     }
   }
 
-  return resplen;
+  return (int32_t) resplen;
 }
 
 #endif
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index 0ec8896b9..c3f2f7fb5 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -54,10 +54,12 @@
 #endif
 
 // This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS           OPT_OS_FREERTOS
+#endif
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUSB_MCU_VENDOR_ESPRESSIF
 #define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
index 30a712275..405a57fe4 100644
--- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c
+++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -41,8 +42,7 @@
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
+tusb_desc_device_t const desc_device = {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = USB_BCD,
@@ -68,8 +68,7 @@ tusb_desc_device_t const desc_device =
 
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
+uint8_t const *tud_descriptor_device_cb(void) {
   return (uint8_t const *) &desc_device;
 }
 
@@ -77,8 +76,7 @@ uint8_t const * tud_descriptor_device_cb(void)
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
-enum
-{
+enum {
   ITF_NUM_CDC = 0,
   ITF_NUM_CDC_DATA,
   ITF_NUM_MSC,
@@ -95,8 +93,18 @@ enum
   #define EPNUM_MSC_OUT     0x05
   #define EPNUM_MSC_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
-  // SAMG doesn't support a same endpoint number with different direction IN and OUT
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x81
+
+  #define EPNUM_MSC_OUT     0x05
+  #define EPNUM_MSC_IN      0x84
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_NOTIF   0x81
   #define EPNUM_CDC_OUT     0x02
@@ -212,53 +220,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456789012",                // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB CDC",                 // 4: CDC Interface
   "TinyUSB MSC",                 // 5: MSC Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/cdc_uac2/CMakeLists.txt b/examples/device/cdc_uac2/CMakeLists.txt
new file mode 100644
index 000000000..c8c797637
--- /dev/null
+++ b/examples/device/cdc_uac2/CMakeLists.txt
@@ -0,0 +1,38 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/uac2_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
+
+# Uncomment me to enable UART based debugging
+# pico_enable_stdio_uart(${PROJECT} 1)
diff --git a/examples/device/cdc_uac2/Makefile b/examples/device/cdc_uac2/Makefile
new file mode 100644
index 000000000..21dcdb0b2
--- /dev/null
+++ b/examples/device/cdc_uac2/Makefile
@@ -0,0 +1,16 @@
+include ../../build_system/make/make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+  src/cdc_app.c \
+  src/main.c \
+  src/uac2_app.c \
+  src/usb_descriptors.c \
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/cdc_uac2/README.md b/examples/device/cdc_uac2/README.md
new file mode 100644
index 000000000..5d120be7d
--- /dev/null
+++ b/examples/device/cdc_uac2/README.md
@@ -0,0 +1,52 @@
+#### Composite CDC + UAC2 on Pico
+
+This example provides a composite CDC + UAC2 device on top of a Raspberry Pi
+Pico board.
+
+
+#### Use Cases
+
+- The CDC + UAC2 composite device happens to be important, especially in the
+  amateur radio community.
+
+  Modern radios (`rigs`) like Icom IC-7300 + IC-705 expose a sound card and a
+  serial device (`composite device`) to the computer over a single USB cable.
+  This allows for Audio I/O and CAT control over a single USB cable which is
+  very convenient.
+
+  By including and maintaining this example in TinyUSB repository, we enable
+  the amateur radio community to build (`homebrew`) radios with similar
+  functionality as the (expensive) commercial rigs.
+
+  This PR is important in bridging this specific gap between the commercial
+  rigs and homebrew equipment.
+
+- https://digirig.net/digirig-mobile-rev-1-9/ is a digital interface for
+  interfacing radios (that lack an inbuilt digital interface) with computers.
+  Digirig Mobile works brilliantly (is OSS!) and is a big improvement over
+  traditional digital interfaces (like the SignaLink USB Interface). By using a
+  Raspberry Pi Pico powered CDC + UAC2 composite device, we can simplify the
+  Digirig Mobile schematic, drastically reduce the manufacturing cost, and
+  (again) enable the homebrewers community to homebrew a modern digital interface
+  with ease themselves.
+
+
+#### Build Steps
+
+```
+cd examples/device/cdc_uac2
+
+export PICO_SDK_PATH=$HOME/pico-sdk
+
+cmake -DFAMILY=rp2040 pico .
+
+cmake -DFAMILY=rp2040 -DCMAKE_BUILD_TYPE=Debug # use this for debugging
+
+make BOARD=raspberry_pi_pico all
+```
+
+
+#### Development Notes
+
+Please try to keep this code synchronized with the `uac2_headset` example
+included in this repository.
diff --git a/examples/device/cdc_uac2/src/cdc_app.c b/examples/device/cdc_uac2/src/cdc_app.c
new file mode 100644
index 000000000..2166c1d6b
--- /dev/null
+++ b/examples/device/cdc_uac2/src/cdc_app.c
@@ -0,0 +1,72 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "common.h"
+
+// Invoked when cdc when line state changed e.g connected/disconnected
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
+{
+  (void) itf;
+  (void) rts;
+
+  if (dtr)
+  {
+    // Terminal connected
+  }
+  else
+  {
+    // Terminal disconnected
+  }
+}
+
+// Invoked when CDC interface received data from host
+void tud_cdc_rx_cb(uint8_t itf)
+{
+  uint8_t buf[64];
+  uint32_t count;
+
+  // connected() check for DTR bit
+  // Most but not all terminal client set this when making connection
+  if (tud_cdc_connected())
+  {
+    if (tud_cdc_available()) // data is available
+    {
+      count = tud_cdc_n_read(itf, buf, sizeof(buf));
+      (void) count;
+
+      tud_cdc_n_write(itf, buf, count);
+      tud_cdc_n_write_flush(itf);
+      // dummy code to check that cdc serial is responding
+      board_led_write(0);
+      board_delay(50);
+      board_led_write(1);
+      board_delay(50);
+      board_led_write(0);
+    }
+  }
+}
diff --git a/examples/device/cdc_uac2/src/common.h b/examples/device/cdc_uac2/src/common.h
new file mode 100644
index 000000000..f281024c7
--- /dev/null
+++ b/examples/device/cdc_uac2/src/common.h
@@ -0,0 +1,34 @@
+#ifndef __COMMON_H__
+#define __COMMON_H__
+
+/* Blink pattern
+ * - 25 ms   : streaming data
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum
+{
+  BLINK_STREAMING = 25,
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+enum
+{
+  VOLUME_CTRL_0_DB = 0,
+  VOLUME_CTRL_10_DB = 2560,
+  VOLUME_CTRL_20_DB = 5120,
+  VOLUME_CTRL_30_DB = 7680,
+  VOLUME_CTRL_40_DB = 10240,
+  VOLUME_CTRL_50_DB = 12800,
+  VOLUME_CTRL_60_DB = 15360,
+  VOLUME_CTRL_70_DB = 17920,
+  VOLUME_CTRL_80_DB = 20480,
+  VOLUME_CTRL_90_DB = 23040,
+  VOLUME_CTRL_100_DB = 25600,
+  VOLUME_CTRL_SILENCE = 0x8000,
+};
+
+#endif
diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c
new file mode 100644
index 000000000..b148593da
--- /dev/null
+++ b/examples/device/cdc_uac2/src/main.c
@@ -0,0 +1,103 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2022 Angel Molina <angelmolinu@gmail.com>
+ * Copyright (c) 2023 Dhiru Kholia <dhiru.kholia@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "common.h"
+
+extern uint32_t blink_interval_ms;
+
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
+#include "pico/stdlib.h"
+#endif
+
+void led_blinking_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  // init device stack on configured roothub port
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
+  stdio_init_all();
+#endif
+
+  TU_LOG1("CDC UAC2 example running\r\n");
+
+  while (1)
+  {
+    tud_task(); // TinyUSB device task
+    led_blinking_task();
+
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
+    // printf("Hello, world!\r\n");
+#endif
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+  (void)remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
diff --git a/examples/device/cdc_uac2/src/tusb_config.h b/examples/device/cdc_uac2/src/tusb_config.h
new file mode 100644
index 000000000..93489cf62
--- /dev/null
+++ b/examples/device/cdc_uac2/src/tusb_config.h
@@ -0,0 +1,174 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC               1
+#define CFG_TUD_MSC               0
+#define CFG_TUD_HID               0
+#define CFG_TUD_MIDI              0
+#define CFG_TUD_AUDIO             1
+#define CFG_TUD_VENDOR            0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                TUD_AUDIO_HEADSET_STEREO_DESC_LEN
+
+// How many formats are used, need to adjust USB descriptor if changed
+#define CFG_TUD_AUDIO_FUNC_1_N_FORMATS                               2
+
+// Audio format type I specifications
+#if defined(__RX__)
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         48000     // 16bit/48kHz is the best quality for Renesas RX
+#else
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000     // 24bit/96kHz is the best quality for full-speed, high-speed is needed beyond this
+#endif
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                           1
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                           1         // Changed
+
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX                  16
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX                  16
+
+#if defined(__RX__)
+// 8bit in 8bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          1
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX                  8
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX          1
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  8
+#else
+// 24bit in 32bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX                  24
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  24
+#endif
+
+// EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
+#define CFG_TUD_AUDIO_ENABLE_EP_IN                1
+
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN) // Maximum EP IN size for all AS alternate settings used
+
+// EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
+#define CFG_TUD_AUDIO_ENABLE_EP_OUT               1
+
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_OUT   TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_OUT   TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_OUT)
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_OUT) // Maximum EP IN size for all AS alternate settings used
+
+// Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	          2
+
+// Size of control request buffer
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ          64
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE                    64
+#define CFG_TUD_CDC_TX_BUFSIZE                    64
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/cdc_uac2/src/uac2_app.c b/examples/device/cdc_uac2/src/uac2_app.c
new file mode 100644
index 000000000..70b0949a9
--- /dev/null
+++ b/examples/device/cdc_uac2/src/uac2_app.c
@@ -0,0 +1,316 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+#include "common.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+
+// List of supported sample rates
+const uint32_t sample_rates[] = {44100, 48000};
+uint32_t current_sample_rate  = 44100;
+
+#define N_SAMPLE_RATES  TU_ARRAY_SIZE(sample_rates)
+
+uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];       // +1 for master channel 0
+int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];    // +1 for master channel 0
+
+// Buffer for microphone data
+int32_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ / 4];
+// Buffer for speaker data
+int32_t spk_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ / 4];
+// Speaker data size received in the last frame
+int spk_data_size;
+// Resolution per format
+const uint8_t resolutions_per_format[CFG_TUD_AUDIO_FUNC_1_N_FORMATS] = {CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX};
+// Current resolution, update on format change
+uint8_t current_resolution;
+
+// Helper for clock get requests
+static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+
+  if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+  {
+    if (request->bRequest == AUDIO_CS_REQ_CUR)
+    {
+      TU_LOG1("Clock get current freq %" PRIu32 "\r\n", current_sample_rate);
+
+      audio_control_cur_4_t curf = { (int32_t) tu_htole32(current_sample_rate) };
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
+    }
+    else if (request->bRequest == AUDIO_CS_REQ_RANGE)
+    {
+      audio_control_range_4_n_t(N_SAMPLE_RATES) rangef =
+      {
+        .wNumSubRanges = tu_htole16(N_SAMPLE_RATES)
+      };
+      TU_LOG1("Clock get %d freq ranges\r\n", N_SAMPLE_RATES);
+      for(uint8_t i = 0; i < N_SAMPLE_RATES; i++)
+      {
+        rangef.subrange[i].bMin = (int32_t) sample_rates[i];
+        rangef.subrange[i].bMax = (int32_t) sample_rates[i];
+        rangef.subrange[i].bRes = 0;
+        TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+      }
+
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
+    }
+  }
+  else if (request->bControlSelector == AUDIO_CS_CTRL_CLK_VALID &&
+           request->bRequest == AUDIO_CS_REQ_CUR)
+  {
+    audio_control_cur_1_t cur_valid = { .bCur = 1 };
+    TU_LOG1("Clock get is valid %u\r\n", cur_valid.bCur);
+    return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_valid, sizeof(cur_valid));
+  }
+  TU_LOG1("Clock get request not supported, entity = %u, selector = %u, request = %u\r\n",
+          request->bEntityID, request->bControlSelector, request->bRequest);
+  return false;
+}
+
+// Helper for clock set requests
+static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+  (void)rhport;
+
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+  TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+  if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t));
+
+    current_sample_rate = (uint32_t) ((audio_control_cur_4_t const *)buf)->bCur;
+
+    TU_LOG1("Clock set current freq: %" PRIu32 "\r\n", current_sample_rate);
+
+    return true;
+  }
+  else
+  {
+    TU_LOG1("Clock set request not supported, entity = %u, selector = %u, request = %u\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+    return false;
+  }
+}
+
+// Helper for feature unit get requests
+static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+
+  if (request->bControlSelector == AUDIO_FU_CTRL_MUTE && request->bRequest == AUDIO_CS_REQ_CUR)
+  {
+    audio_control_cur_1_t mute1 = { .bCur = mute[request->bChannelNumber] };
+    TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
+    return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
+  }
+  else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+  {
+    if (request->bRequest == AUDIO_CS_REQ_RANGE)
+    {
+      audio_control_range_2_n_t(1) range_vol = {
+        .wNumSubRanges = tu_htole16(1),
+        .subrange[0] = { .bMin = tu_htole16(-VOLUME_CTRL_50_DB), tu_htole16(VOLUME_CTRL_0_DB), tu_htole16(256) }
+      };
+      TU_LOG1("Get channel %u volume range (%d, %d, %u) dB\r\n", request->bChannelNumber,
+              range_vol.subrange[0].bMin / 256, range_vol.subrange[0].bMax / 256, range_vol.subrange[0].bRes / 256);
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &range_vol, sizeof(range_vol));
+    }
+    else if (request->bRequest == AUDIO_CS_REQ_CUR)
+    {
+      audio_control_cur_2_t cur_vol = { .bCur = tu_htole16(volume[request->bChannelNumber]) };
+      TU_LOG1("Get channel %u volume %d dB\r\n", request->bChannelNumber, cur_vol.bCur / 256);
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_vol, sizeof(cur_vol));
+    }
+  }
+  TU_LOG1("Feature unit get request not supported, entity = %u, selector = %u, request = %u\r\n",
+          request->bEntityID, request->bControlSelector, request->bRequest);
+
+  return false;
+}
+
+// Helper for feature unit set requests
+static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+  (void)rhport;
+
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+  TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+  if (request->bControlSelector == AUDIO_FU_CTRL_MUTE)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_1_t));
+
+    mute[request->bChannelNumber] = ((audio_control_cur_1_t const *)buf)->bCur;
+
+    TU_LOG1("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
+
+    return true;
+  }
+  else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_2_t));
+
+    volume[request->bChannelNumber] = ((audio_control_cur_2_t const *)buf)->bCur;
+
+    TU_LOG1("Set channel %d volume: %d dB\r\n", request->bChannelNumber, volume[request->bChannelNumber] / 256);
+
+    return true;
+  }
+  else
+  {
+    TU_LOG1("Feature unit set request not supported, entity = %u, selector = %u, request = %u\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+    return false;
+  }
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request)
+{
+  audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+  if (request->bEntityID == UAC2_ENTITY_CLOCK)
+    return tud_audio_clock_get_request(rhport, request);
+  if (request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT)
+    return tud_audio_feature_unit_get_request(rhport, request);
+  else
+  {
+    TU_LOG1("Get request not handled, entity = %d, selector = %d, request = %d\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+  }
+  return false;
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request, uint8_t *buf)
+{
+  audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+  if (request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT)
+    return tud_audio_feature_unit_set_request(rhport, request, buf);
+  if (request->bEntityID == UAC2_ENTITY_CLOCK)
+    return tud_audio_clock_set_request(rhport, request, buf);
+  TU_LOG1("Set request not handled, entity = %d, selector = %d, request = %d\r\n",
+          request->bEntityID, request->bControlSelector, request->bRequest);
+
+  return false;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void)rhport;
+
+  uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+  uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+  if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt == 0) {
+    // Audio streaming stop
+    blink_interval_ms = BLINK_MOUNTED;
+  }
+
+  return true;
+}
+
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void)rhport;
+  uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+  uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+  TU_LOG2("Set interface %d alt %d\r\n", itf, alt);
+  if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt != 0) {
+    // Audio streaming start
+    blink_interval_ms = BLINK_STREAMING;
+  }
+
+  // Clear buffer when streaming format is changed
+  spk_data_size = 0;
+  if(alt != 0)
+  {
+    current_resolution = resolutions_per_format[alt-1];
+  }
+
+  return true;
+}
+
+bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting)
+{
+  (void)rhport;
+  (void)func_id;
+  (void)ep_out;
+  (void)cur_alt_setting;
+
+  spk_data_size = tud_audio_read(spk_buf, n_bytes_received);
+  tud_audio_write(spk_buf, n_bytes_received);
+
+  return true;
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void)rhport;
+  (void)itf;
+  (void)ep_in;
+  (void)cur_alt_setting;
+
+  // This callback could be used to fill microphone data separately
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if (board_millis() - start_ms < blink_interval_ms) return;
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state;
+}
diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c
new file mode 100644
index 000000000..9f7255d8a
--- /dev/null
+++ b/examples/device/cdc_uac2/src/usb_descriptors.c
@@ -0,0 +1,206 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]     AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+    _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0200,
+
+    // Use Interface Association Descriptor (IAD)
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+  return (uint8_t const *)&desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+#define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_HEADSET_STEREO_DESC_LEN + CFG_TUD_CDC * TUD_CDC_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO_IN    0x03
+  #define EPNUM_AUDIO_OUT   0x03
+
+  #define EPNUM_CDC_NOTIF   0x84
+  #define EPNUM_CDC_OUT     0x05
+  #define EPNUM_CDC_IN      0x85
+
+#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+  // ISO endpoints for NRF5x are fixed to 0x08 (0x88)
+  #define EPNUM_AUDIO_IN    0x08
+  #define EPNUM_AUDIO_OUT   0x08
+
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x02
+
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x04
+  #define EPNUM_CDC_IN      0x85
+
+#else
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x01
+
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x04
+  #define EPNUM_CDC_IN      0x84
+#endif
+
+uint8_t const desc_configuration[] =
+{
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO_OUT, EPNUM_AUDIO_IN | 0x80),
+
+    // CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 6, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64)
+};
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void)index; // for multiple configurations
+  return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] =
+{
+  (const char[]) { 0x09, 0x04 },  // 0: is supported language is English (0x0409)
+  "TinyUSB",                      // 1: Manufacturer
+  "TinyUSB headset",              // 2: Product
+  NULL,                           // 3: Serials will use unique ID if possible
+  "TinyUSB Speakers",             // 4: Audio Interface
+  "TinyUSB Microphone",           // 5: Audio Interface
+  "TinyUSB CDC",                  // 6: Audio Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/device/cdc_uac2/src/usb_descriptors.h b/examples/device/cdc_uac2/src/usb_descriptors.h
new file mode 100644
index 000000000..736feeefe
--- /dev/null
+++ b/examples/device/cdc_uac2/src/usb_descriptors.h
@@ -0,0 +1,158 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenbreg
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+// #include "tusb.h"
+
+// Unit numbers are arbitrary selected
+#define UAC2_ENTITY_CLOCK               0x04
+// Speaker path
+#define UAC2_ENTITY_SPK_INPUT_TERMINAL  0x01
+#define UAC2_ENTITY_SPK_FEATURE_UNIT    0x02
+#define UAC2_ENTITY_SPK_OUTPUT_TERMINAL 0x03
+// Microphone path
+#define UAC2_ENTITY_MIC_INPUT_TERMINAL  0x11
+#define UAC2_ENTITY_MIC_OUTPUT_TERMINAL 0x13
+
+enum
+{
+  ITF_NUM_AUDIO_CONTROL = 0,
+  ITF_NUM_AUDIO_STREAMING_SPK,
+  ITF_NUM_AUDIO_STREAMING_MIC,
+  ITF_NUM_CDC,
+  ITF_NUM_CDC_DATA,
+  ITF_NUM_TOTAL
+};
+
+#define TUD_AUDIO_HEADSET_STEREO_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+    + TUD_AUDIO_DESC_STD_AC_LEN\
+    + TUD_AUDIO_DESC_CS_AC_LEN\
+    + TUD_AUDIO_DESC_CLK_SRC_LEN\
+    + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN\
+    + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 1, Alternate 2 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 2, Alternate 0 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 2, Alternate 1 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 2, Alternate 2 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
+
+#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \
+    /* Standard Interface Association Descriptor (IAD) */\
+    TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ 3, /*_stridx*/ 0x00),\
+    /* Standard AC Interface Descriptor(4.7.1) */\
+    TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+    /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+    TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_HEADSET, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+    /* Clock Source Descriptor(4.7.2.1) */\
+    TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ 3, /*_ctrl*/ 7, /*_assocTerm*/ 0x00,  /*_stridx*/ 0x00),    \
+    /* Input Terminal Descriptor(4.7.2.4) */\
+    TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
+    /* Feature Unit Descriptor(4.7.2.8) */\
+    TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL(/*_unitid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_srcid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrlch0master*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch2*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00),\
+    /* Output Terminal Descriptor(4.7.2.5) */\
+    TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_OUT_HEADPHONES, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+    /* Input Terminal Descriptor(4.7.2.4) */\
+    TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
+    /* Output Terminal Descriptor(4.7.2.5) */\
+    TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+    /* Standard AS Interface Descriptor(4.9.1) */\
+    /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x05),\
+    /* Standard AS Interface Descriptor(4.9.1) */\
+    /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+    /* Interface 1, Alternate 2 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+    /* Standard AS Interface Descriptor(4.9.1) */\
+    /* Interface 2, Alternate 0 - default alternate setting with 0 bandwidth */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x04),\
+    /* Standard AS Interface Descriptor(4.9.1) */\
+    /* Interface 2, Alternate 1 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
+    /* Interface 2, Alternate 2 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
+
+#endif
diff --git a/examples/device/dfu/CMakeLists.txt b/examples/device/dfu/CMakeLists.txt
index acaa54198..3da8ee3df 100644
--- a/examples/device/dfu/CMakeLists.txt
+++ b/examples/device/dfu/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/dfu/Makefile b/examples/device/dfu/Makefile
index 69b633fea..52a24cdb0 100644
--- a/examples/device/dfu/Makefile
+++ b/examples/device/dfu/Makefile
@@ -1,12 +1,14 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
 	$(TOP)/hw \
 
 # Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE = \
+	src/main.c \
+	src/usb_descriptors.c
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/dfu/skip.txt b/examples/device/dfu/skip.txt
index 9ac346bad..9dde06c30 100644
--- a/examples/device/dfu/skip.txt
+++ b/examples/device/dfu/skip.txt
@@ -1,2 +1,3 @@
 mcu:TM4C123
 mcu:BCM2835
+family:espressif
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 6bb183819..af9e99857 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -42,7 +42,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
@@ -75,15 +75,21 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
     tud_task(); // tinyusb device task
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -114,7 +120,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 51a0d09f5..fd469aaf2 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "class/dfu/dfu_device.h"
 
@@ -116,56 +117,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "FLASH",                       // 4: DFU Partition 1
   "EEPROM",                      // 5: DFU Partition 2
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
-
   size_t chr_count;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }
-  else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    const char* str = string_desc_arr[index];
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) {
-      chr_count = 31;
-    }
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t)((((uint16_t)TUSB_DESC_STRING) << 8 ) | (2u*chr_count + 2u));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt
index abc4d91da..3da8ee3df 100644
--- a/examples/device/dfu_runtime/CMakeLists.txt
+++ b/examples/device/dfu_runtime/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/dfu_runtime/Makefile b/examples/device/dfu_runtime/Makefile
index 69b633fea..1b4d398cf 100644
--- a/examples/device/dfu_runtime/Makefile
+++ b/examples/device/dfu_runtime/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 55b380353..4740c18c4 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -31,7 +31,7 @@
  *
  * $ dfu-util -e
  *
- * This will send DETTACH command to put device into bootloader. Since this example
+ * This will send DETACH command to put device into bootloader. Since this example
  * is minimal, it doesn't actually go into DFU mode but rather change the LED blinking
  * pattern to fast rate as indicator.
  */
@@ -40,7 +40,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
@@ -70,15 +70,21 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
     tud_task(); // tinyusb device task
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -109,7 +115,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 // Invoked on DFU_DETACH request to reboot to the bootloader
diff --git a/examples/device/dfu_runtime/src/usb_descriptors.c b/examples/device/dfu_runtime/src/usb_descriptors.c
index 1b0a60551..7ac53d255 100644
--- a/examples/device/dfu_runtime/src/usb_descriptors.c
+++ b/examples/device/dfu_runtime/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "class/dfu/dfu_rt_device.h"
 
@@ -112,55 +113,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB DFU runtime",         // 4: DFU runtime
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
-
   size_t chr_count;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }
-  else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    const char* str = string_desc_arr[index];
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) {
-      chr_count = 31;
-    }
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt
index fa6e83b7e..8a62d6ba2 100644
--- a/examples/device/dynamic_configuration/CMakeLists.txt
+++ b/examples/device/dynamic_configuration/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
@@ -24,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/dynamic_configuration/Makefile b/examples/device/dynamic_configuration/Makefile
index 69b633fea..1b4d398cf 100644
--- a/examples/device/dynamic_configuration/Makefile
+++ b/examples/device/dynamic_configuration/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/dynamic_configuration/skip.txt b/examples/device/dynamic_configuration/skip.txt
index d844feae8..b6252e405 100644
--- a/examples/device/dynamic_configuration/skip.txt
+++ b/examples/device/dynamic_configuration/skip.txt
@@ -1 +1,3 @@
-mcu:SAMD11
\ No newline at end of file
+mcu:SAMD11
+family:espressif
+board:ch32v203g_r0_1v0
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 33a603343..32ff58232 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
@@ -57,7 +57,15 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
@@ -66,8 +74,6 @@ int main(void)
     cdc_task();
     midi_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -98,7 +104,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 
diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c
index e8cb03fdd..10c3ac6fe 100644
--- a/examples/device/dynamic_configuration/src/msc_disk.c
+++ b/examples/device/dynamic_configuration/src/msc_disk.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 457f774d0..0a2049288 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,8 +23,8 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
-#include "bsp/board.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
  * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
@@ -132,8 +132,8 @@ enum
   #define EPNUM_1_MSC_OUT     0x02
   #define EPNUM_1_MSC_IN      0x82
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
-  // SAMG doesn't support a same endpoint number with different direction IN and OUT
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_0_CDC_NOTIF   0x81
   #define EPNUM_0_CDC_OUT     0x02
@@ -170,7 +170,7 @@ uint8_t const desc_configuration_0[] =
 };
 
 
-uint8_t const desc_configuraiton_1[] =
+uint8_t const desc_configuration_1[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_1_NUM_TOTAL, 0, CONFIG_1_TOTAL_LEN, 0x00, 100),
@@ -186,58 +186,70 @@ uint8_t const desc_configuraiton_1[] =
 uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 {
   (void) index; // for multiple configurations
-  return mode ? desc_configuraiton_1 : desc_configuration_0;
+  return mode ? desc_configuration_1 : desc_configuration_0;
 }
 
 //--------------------------------------------------------------------+
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt
index abc4d91da..3da8ee3df 100644
--- a/examples/device/hid_boot_interface/CMakeLists.txt
+++ b/examples/device/hid_boot_interface/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_boot_interface/Makefile b/examples/device/hid_boot_interface/Makefile
index c6a9c5b21..52a24cdb0 100644
--- a/examples/device/hid_boot_interface/Makefile
+++ b/examples/device/hid_boot_interface/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -9,7 +8,7 @@ INC += \
 EXAMPLE_SOURCE = \
 	src/main.c \
 	src/usb_descriptors.c
-	
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 71afa3f46..570e4e801 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -57,7 +57,15 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
@@ -98,7 +106,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
@@ -157,11 +165,11 @@ void hid_task(void)
       {
         uint8_t const report_id   = 0;
         uint8_t const button_mask = 0;
-        uint8_t const veritical   = 0;
-        uint8_t const horizontal  = 0;
+        int8_t  const vertical    = 0;
+        int8_t  const horizontal  = 0;
         int8_t  const delta       = 5;
 
-        tud_hid_n_mouse_report(ITF_NUM_MOUSE, report_id, button_mask, delta, delta, veritical, horizontal);
+        tud_hid_n_mouse_report(ITF_NUM_MOUSE, report_id, button_mask, delta, delta, vertical, horizontal);
       }
     }
   }
@@ -175,13 +183,13 @@ void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol)
   (void) protocol;
 
   // nothing to do since we use the same compatible boot report for both Boot and Report mode.
-  // TOOD set a indicator for user
+  // TODO set a indicator for user
 }
 
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) instance;
   (void) report;
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.c b/examples/device/hid_boot_interface/src/usb_descriptors.c
index a0d7e9f15..d68ef16d9 100644
--- a/examples/device/hid_boot_interface/src/usb_descriptors.c
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -130,51 +131,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.h b/examples/device/hid_boot_interface/src/usb_descriptors.h
index 57cf0e2c0..6fee9e223 100644
--- a/examples/device/hid_boot_interface/src/usb_descriptors.h
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt
index abc4d91da..3da8ee3df 100644
--- a/examples/device/hid_composite/CMakeLists.txt
+++ b/examples/device/hid_composite/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_composite/Makefile b/examples/device/hid_composite/Makefile
index 69b633fea..1b4d398cf 100644
--- a/examples/device/hid_composite/Makefile
+++ b/examples/device/hid_composite/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index f7d76cfc7..a58107b6f 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #include "usb_descriptors.h"
@@ -58,7 +58,15 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
@@ -67,8 +75,6 @@ int main(void)
 
     hid_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -99,7 +105,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
@@ -191,11 +197,43 @@ static void send_hid_report(uint8_t report_id, uint32_t btn)
       }
     }
     break;
-
     default: break;
   }
 }
 
+/* use this to send stylus touch signal through USB. */
+static void send_stylus_touch(uint16_t x, uint16_t y, bool state)
+{
+  // skip if hid is not ready yet
+  if ( !tud_hid_ready() ) return;
+
+  static bool has_stylus_pen = false;
+
+  hid_stylus_report_t report =
+  {
+    .attr = 0,
+    .x = 0,
+    .y = 0
+  };
+
+  report.x = x;
+  report.y = y;
+
+  if (state)
+  {
+    report.attr = STYLUS_ATTR_TIP_SWITCH | STYLUS_ATTR_IN_RANGE;
+    tud_hid_report(REPORT_ID_STYLUS_PEN, &report, sizeof(report));
+
+    has_stylus_pen = true;
+  }else
+  {
+    report.attr = 0;
+    if (has_stylus_pen) tud_hid_report(REPORT_ID_STYLUS_PEN, &report, sizeof(report));
+    has_stylus_pen = false;
+  }
+
+}
+
 // Every 10ms, we will sent 1 report for each HID profile (keyboard, mouse etc ..)
 // tud_hid_report_complete_cb() is used to send the next report after previous one is complete
 void hid_task(void)
@@ -203,6 +241,14 @@ void hid_task(void)
   // Poll every 10ms
   const uint32_t interval_ms = 10;
   static uint32_t start_ms = 0;
+  static uint32_t touch_ms = 0;
+  static bool touch_state = false;
+
+  if (board_millis() - touch_ms < 100) {
+    touch_ms = board_millis();
+    send_stylus_touch(0, 0, touch_state = !touch_state);
+    return;
+  }
 
   if ( board_millis() - start_ms < interval_ms) return; // not enough time
   start_ms += interval_ms;
@@ -225,7 +271,7 @@ void hid_task(void)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) instance;
   (void) len;
diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c
index 2988baee2..15c6e1f73 100644
--- a/examples/device/hid_composite/src/usb_descriptors.c
+++ b/examples/device/hid_composite/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -78,6 +79,7 @@ uint8_t const desc_hid_report[] =
 {
   TUD_HID_REPORT_DESC_KEYBOARD( HID_REPORT_ID(REPORT_ID_KEYBOARD         )),
   TUD_HID_REPORT_DESC_MOUSE   ( HID_REPORT_ID(REPORT_ID_MOUSE            )),
+  TUD_HID_REPORT_DESC_STYLUS_PEN( HID_REPORT_ID(REPORT_ID_STYLUS_PEN     )),
   TUD_HID_REPORT_DESC_CONSUMER( HID_REPORT_ID(REPORT_ID_CONSUMER_CONTROL )),
   TUD_HID_REPORT_DESC_GAMEPAD ( HID_REPORT_ID(REPORT_ID_GAMEPAD          ))
 };
@@ -177,51 +179,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_composite/src/usb_descriptors.h b/examples/device/hid_composite/src/usb_descriptors.h
index ca8925ad9..18d31172b 100644
--- a/examples/device/hid_composite/src/usb_descriptors.h
+++ b/examples/device/hid_composite/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -29,6 +29,7 @@ enum
 {
   REPORT_ID_KEYBOARD = 1,
   REPORT_ID_MOUSE,
+  REPORT_ID_STYLUS_PEN,
   REPORT_ID_CONSUMER_CONTROL,
   REPORT_ID_GAMEPAD,
   REPORT_ID_COUNT
diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt
index ed734b954..6ce9e72fe 100644
--- a/examples/device/hid_composite_freertos/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/CMakeLists.txt
@@ -1,17 +1,33 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
-# use BOARD-Directory name for project id
-get_filename_component(PROJECT ${CMAKE_CURRENT_SOURCE_DIR} NAME)
-set(PROJECT ${BOARD}-${PROJECT})
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
-# TOP is absolute path to root directory of TinyUSB git repo
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-# Check for -DFAMILY=
-if(FAMILY MATCHES "^esp32s[2-3]")
-  include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
-  project(${PROJECT})
-else()
-  message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
 endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index 6c8c43ddd..bd625b345 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -1,37 +1,15 @@
-DEPS_SUBMODULES += lib/FreeRTOS-Kernel
-
-include ../../../tools/top.mk
-include ../../make.mk
-
-FREERTOS_SRC = lib/FreeRTOS-Kernel
+RTOS = freertos
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
-	src/FreeRTOSConfig \
 	$(TOP)/hw \
-	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)	
 
 # Example source
 EXAMPLE_SOURCE = \
-	src/freertos_hook.c \
 	src/main.c \
 	src/usb_descriptors.c
-	
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# FreeRTOS source, all files in port folder
-SRC_C += \
-	$(FREERTOS_SRC)/list.c \
-	$(FREERTOS_SRC)/queue.c \
-	$(FREERTOS_SRC)/tasks.c \
-	$(FREERTOS_SRC)/timers.c \
-	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
-
-# Suppress FreeRTOS warnings
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
-
-# FreeRTOS (lto + Os) linker issue
-LDFLAGS += -Wl,--undefined=vTaskSwitchContext
-
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt
index 1ee51a9d4..650bf355b 100644
--- a/examples/device/hid_composite_freertos/skip.txt
+++ b/examples/device/hid_composite_freertos/skip.txt
@@ -1,11 +1,16 @@
+mcu:CH32V103
+mcu:CH32V20X
+mcu:CH32V307
 mcu:CXD56
 mcu:F1C100S
 mcu:GD32VF103
+mcu:MCXA15
 mcu:MKL25ZXX
 mcu:MSP430x5xx
 mcu:RP2040
 mcu:SAMD11
 mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
 family:broadcom_32bit
-family:broadcom_64bit
\ No newline at end of file
+family:broadcom_64bit
diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt
index 25da8fcd7..6d912854f 100644
--- a/examples/device/hid_composite_freertos/src/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt
@@ -1,35 +1,3 @@
 idf_component_register(SRCS "main.c" "usb_descriptors.c"
                     INCLUDE_DIRS "."
-                    REQUIRES freertos soc)
-
-file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
-
-if(EXISTS ${board_cmake})
-    include(${board_cmake})
-endif()
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/hw"
-  "${TOP}/src"
-)
-
-target_compile_definitions(${COMPONENT_TARGET} PUBLIC
-  ESP_PLATFORM
-)
-
-target_sources(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/src/tusb.c"
-  "${TOP}/src/common/tusb_fifo.c"
-  "${TOP}/src/device/usbd.c"
-  "${TOP}/src/device/usbd_control.c"
-  "${TOP}/src/class/cdc/cdc_device.c"
-  "${TOP}/src/class/dfu/dfu_rt_device.c"
-  "${TOP}/src/class/hid/hid_device.c"
-  "${TOP}/src/class/midi/midi_device.c"
-  "${TOP}/src/class/msc/msc_device.c"
-  "${TOP}/src/class/net/ecm_rndis_device.c"
-  "${TOP}/src/class/net/ncm_device.c"
-  "${TOP}/src/class/usbtmc/usbtmc_device.c"
-  "${TOP}/src/class/vendor/vendor_device.c"
-  "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c"
-)
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/hid_composite_freertos/src/freertos_hook.c b/examples/device/hid_composite_freertos/src/freertos_hook.c
deleted file mode 100644
index ab885947c..000000000
--- a/examples/device/hid_composite_freertos/src/freertos_hook.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "FreeRTOS.h"
-#include "task.h"
-#include "common/tusb_common.h"
-
-
-void vApplicationMallocFailedHook(void)
-{
-  taskDISABLE_INTERRUPTS();
-  TU_ASSERT(false, );
-}
-
-void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName)
-{
-  (void) pxTask;
-  (void) pcTaskName;
-
-  taskDISABLE_INTERRUPTS();
-  TU_ASSERT(false, );
-}
-
-/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an
- * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
- * used by the Idle task. */
-void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
-{
-  /* If the buffers to be provided to the Idle task are declared inside this
-   * function then they must be declared static - otherwise they will be allocated on
-   * the stack and so not exists after this function exits. */
-  static StaticTask_t xIdleTaskTCB;
-  static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
-
-  /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
-    state will be stored. */
-  *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
-
-  /* Pass out the array that will be used as the Idle task's stack. */
-  *ppxIdleTaskStackBuffer = uxIdleTaskStack;
-
-  /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
-    Note that, as the array is necessarily of type StackType_t,
-    configMINIMAL_STACK_SIZE is specified in words, not bytes. */
-  *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
-}
-
-/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
- * application must provide an implementation of vApplicationGetTimerTaskMemory()
- * to provide the memory that is used by the Timer service task. */
-void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
-{
-  /* If the buffers to be provided to the Timer task are declared inside this
-   * function then they must be declared static - otherwise they will be allocated on
-   * the stack and so not exists after this function exits. */
-  static StaticTask_t xTimerTaskTCB;
-  static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
-
-  /* Pass out a pointer to the StaticTask_t structure in which the Timer
-    task's state will be stored. */
-  *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
-
-  /* Pass out the array that will be used as the Timer task's stack. */
-  *ppxTimerTaskStackBuffer = uxTimerTaskStack;
-
-  /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
-    Note that, as the array is necessarily of type StackType_t,
-    configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
-  *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
-}
-
-#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X
-#include "iodefine.h"
-void vApplicationSetupTimerInterrupt(void)
-{
-  /* Enable CMT0 */
-  SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
-  MSTP(CMT0)       = 0;
-  SYSTEM.PRCR.WORD = (0xA5u<<8);
-
-  CMT0.CMCNT      = 0;
-  CMT0.CMCOR      = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
-  CMT0.CMCR.WORD  = TU_BIT(6) | 2;
-  IR(CMT0, CMI0)  = 0;
-  IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY;
-  IEN(CMT0, CMI0) = 1;
-  CMT.CMSTR0.BIT.STR0 = 1;
-}
-#endif
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index b67c10937..30c0331ef 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,11 +27,11 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUSB_MCU_VENDOR_ESPRESSIF
   // ESP-IDF need "freertos/" prefix in include path.
   // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
@@ -53,6 +53,8 @@
   #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
+#define HID_STACK_SZIE      configMINIMAL_STACK_SIZE
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
@@ -68,19 +70,18 @@ enum  {
   BLINK_SUSPENDED = 2500,
 };
 
-// static timer
+// static timer & task
+#if configSUPPORT_STATIC_ALLOCATION
 StaticTimer_t blinky_tmdef;
-TimerHandle_t blinky_tm;
 
-// static task
 StackType_t  usb_device_stack[USBD_STACK_SIZE];
 StaticTask_t usb_device_taskdef;
 
-// static task for hid
-#define HID_STACK_SZIE      configMINIMAL_STACK_SIZE
 StackType_t  hid_stack[HID_STACK_SZIE];
 StaticTask_t hid_taskdef;
+#endif
 
+TimerHandle_t blinky_tm;
 
 void led_blinky_cb(TimerHandle_t xTimer);
 void usb_device_task(void* param);
@@ -94,25 +95,32 @@ int main(void)
 {
   board_init();
 
+#if configSUPPORT_STATIC_ALLOCATION
   // soft timer for blinky
   blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
-  xTimerStart(blinky_tm, 0);
 
   // Create a task for tinyusb device stack
-  (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
 
   // Create HID task
-  (void) xTaskCreateStatic( hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef);
+  xTaskCreateStatic(hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef);
+#else
+  blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
+  xTaskCreate(hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+#endif
+
+  xTimerStart(blinky_tm, 0);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if !TUSB_MCU_VENDOR_ESPRESSIF
   vTaskStartScheduler();
 #endif
 
   return 0;
 }
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUSB_MCU_VENDOR_ESPRESSIF
 void app_main(void)
 {
   main();
@@ -128,7 +136,15 @@ void usb_device_task(void* param)
   // init device stack on configured roothub port
   // This should be called after scheduler/kernel is started.
   // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   // RTOS forever loop
   while (1)
@@ -168,7 +184,14 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+  if (tud_mounted())
+  {
+    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+  }
+  else
+  {
+    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -294,7 +317,7 @@ void hid_task(void* param)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) instance;
   (void) len;
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 935ae9453..6ec38b95c 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -54,10 +54,12 @@
 #endif
 
 // This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS           OPT_OS_FREERTOS
+#endif
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUSB_MCU_VENDOR_ESPRESSIF
 #define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c
index 4df12d3db..85820de55 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.c
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -175,51 +176,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.h b/examples/device/hid_composite_freertos/src/usb_descriptors.h
index ca8925ad9..e733d31dd 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.h
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt
index abc4d91da..3da8ee3df 100644
--- a/examples/device/hid_generic_inout/CMakeLists.txt
+++ b/examples/device/hid_generic_inout/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_generic_inout/Makefile b/examples/device/hid_generic_inout/Makefile
index 69b633fea..1b4d398cf 100644
--- a/examples/device/hid_generic_inout/Makefile
+++ b/examples/device/hid_generic_inout/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_generic_inout/hid_test.js b/examples/device/hid_generic_inout/hid_test.js
index daa958fd5..16bc723e2 100644
--- a/examples/device/hid_generic_inout/hid_test.js
+++ b/examples/device/hid_generic_inout/hid_test.js
@@ -48,7 +48,7 @@ if( deviceInfo ) {
 
 
 function anySupportedBoard(d) {
-	
+
 	for (var key in boards) {
 	    if (boards.hasOwnProperty(key)) {
 	        if (isDevice(boards[key],d)) {
@@ -65,4 +65,3 @@ function isDevice(board,d){
 	// product id 0xff is matches all
 	return d.vendorId==board[0] && (d.productId==board[1] || board[1] == 0xFFFF);
 }
-
diff --git a/examples/device/hid_generic_inout/hid_test.py b/examples/device/hid_generic_inout/hid_test.py
old mode 100644
new mode 100755
index 21fd3f421..3aaca9d2c
--- a/examples/device/hid_generic_inout/hid_test.py
+++ b/examples/device/hid_generic_inout/hid_test.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
 # Install python3 HID package https://pypi.org/project/hid/
 import hid
 
@@ -13,8 +14,8 @@ for vid in  USB_VID:
         if dev:
             while True:
                 # Get input from console and encode to UTF8 for array of chars.
-                # hid generic inout is single report therefore by HIDAPI requirement
-                # it must be preceeded with 0x00 as dummy reportID
+                # hid generic in/out is single report therefore by HIDAPI requirement
+                # it must be preceded, with 0x00 as dummy reportID
                 str_out = b'\x00'
                 str_out += input("Send text to HID Device : ").encode('utf-8')
                 dev.write(str_out)
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 5b7daf118..73f51002d 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* This example demonstrate HID Generic raw Input & Output.
@@ -81,15 +81,21 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
     tud_task(); // tinyusb device task
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -120,7 +126,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c
index c2b4792c8..64f6d17ae 100644
--- a/examples/device/hid_generic_inout/src/usb_descriptors.c
+++ b/examples/device/hid_generic_inout/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -103,7 +104,7 @@ uint8_t const desc_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-  // Interface number, string index, protocol, report descriptor len, EP In & Out address, size & polling interval
+  // Interface number, string index, protocol, report descriptor len, EP Out & In address, size & polling interval
   TUD_HID_INOUT_DESCRIPTOR(ITF_NUM_HID, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, 0x80 | EPNUM_HID, CFG_TUD_HID_EP_BUFSIZE, 10)
 };
 
@@ -120,51 +121,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt
index abc4d91da..3da8ee3df 100644
--- a/examples/device/hid_multiple_interface/CMakeLists.txt
+++ b/examples/device/hid_multiple_interface/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_multiple_interface/Makefile b/examples/device/hid_multiple_interface/Makefile
index 69b633fea..1b4d398cf 100644
--- a/examples/device/hid_multiple_interface/Makefile
+++ b/examples/device/hid_multiple_interface/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 29ba74398..92c7e8332 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
@@ -62,7 +62,15 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
@@ -71,8 +79,6 @@ int main(void)
 
     hid_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -103,7 +109,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/hid_multiple_interface/src/usb_descriptors.c b/examples/device/hid_multiple_interface/src/usb_descriptors.c
index 42471a961..86f567e8e 100644
--- a/examples/device/hid_multiple_interface/src/usb_descriptors.c
+++ b/examples/device/hid_multiple_interface/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -136,53 +137,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 },  // 0: is supported language is English (0x0409)
   "TinyUSB",                      // 1: Manufacturer
   "TinyUSB Device",               // 2: Product
-  "123456",                       // 3: Serials, should use chip ID
+  NULL,                           // 3: Serials will use unique ID if possible
   "Keyboard Interface",           // 4: Interface 1 String
   "Mouse Interface",              // 5: Interface 2 String
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt
index abc4d91da..6a7e68c3d 100644
--- a/examples/device/midi_test/CMakeLists.txt
+++ b/examples/device/midi_test/CMakeLists.txt
@@ -1,28 +1,33 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/midi_test/Makefile b/examples/device/midi_test/Makefile
index 5a455078e..7fa475da5 100644
--- a/examples/device/midi_test/Makefile
+++ b/examples/device/midi_test/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
   src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 3310348bd..e5c47bdb2 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* This MIDI example send sequence of note (on/off) repeatedly. To test on PC, you need to install
@@ -58,22 +58,25 @@ void led_blinking_task(void);
 void midi_task(void);
 
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
 
-  while (1)
-  {
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  while (1) {
     tud_task(); // tinyusb device task
     led_blinking_task();
     midi_task();
   }
-
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -81,30 +84,26 @@ int main(void)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
-  blink_interval_ms = BLINK_MOUNTED;
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
@@ -115,8 +114,7 @@ void tud_resume_cb(void)
 uint32_t note_pos = 0;
 
 // Store example melody as an array of note values
-uint8_t note_sequence[] =
-{
+const uint8_t note_sequence[] = {
   74,78,81,86,90,93,98,102,57,61,66,69,73,78,81,85,88,92,97,100,97,92,88,85,81,78,
   74,69,66,62,57,62,66,69,74,78,81,86,90,93,97,102,97,93,90,85,81,78,73,68,64,61,
   56,61,64,68,74,78,81,86,90,93,98,102
@@ -132,11 +130,15 @@ void midi_task(void)
   // The MIDI interface always creates input and output port/jack descriptors
   // regardless of these being used or not. Therefore incoming traffic should be read
   // (possibly just discarded) to avoid the sender blocking in IO
-  uint8_t packet[4];
-  while ( tud_midi_available() ) tud_midi_packet_read(packet);
+  while (tud_midi_available()) {
+    uint8_t packet[4];
+    tud_midi_packet_read(packet);
+  }
 
   // send note periodically
-  if (board_millis() - start_ms < 286) return; // not enough time
+  if (board_millis() - start_ms < 286) {
+    return; // not enough time
+  }
   start_ms += 286;
 
   // Previous positions in the note sequence.
@@ -144,7 +146,9 @@ void midi_task(void)
 
   // If we currently are at position 0, set the
   // previous position to the last note in the sequence.
-  if (previous < 0) previous = sizeof(note_sequence) - 1;
+  if (previous < 0) {
+    previous = sizeof(note_sequence) - 1;
+  }
 
   // Send Note On for current position at full velocity (127) on channel 1.
   uint8_t note_on[3] = { 0x90 | channel, note_sequence[note_pos], 127 };
@@ -158,7 +162,9 @@ void midi_task(void)
   note_pos++;
 
   // If we are at the end of the sequence, start over.
-  if (note_pos >= sizeof(note_sequence)) note_pos = 0;
+  if (note_pos >= sizeof(note_sequence)) {
+    note_pos = 0;
+  }
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c
index c84a873b1..384742ae8 100644
--- a/examples/device/midi_test/src/usb_descriptors.c
+++ b/examples/device/midi_test/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,13 +23,14 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
  * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
  *
  * Auto ProductID layout's Bitmap:
- *   [MSB]       MIDI | HID | MSC | CDC          [LSB]
+ *   [MSB]         HID | MSC | CDC          [LSB]
  */
 #define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
@@ -38,8 +39,7 @@
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
+tusb_desc_device_t const desc_device = {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = 0x0200,
@@ -61,18 +61,13 @@ tusb_desc_device_t const desc_device =
 
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
+uint8_t const * tud_descriptor_device_cb(void) {
   return (uint8_t const *) &desc_device;
 }
-
-
 //--------------------------------------------------------------------+
 // Configuration Descriptor
 //--------------------------------------------------------------------+
-
-enum
-{
+enum {
   ITF_NUM_MIDI = 0,
   ITF_NUM_MIDI_STREAMING,
   ITF_NUM_TOTAL
@@ -83,19 +78,27 @@ enum
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
-  #define EPNUM_MIDI_OUT   0x02
-  #define EPNUM_MIDI_IN   0x02
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
-  // On Bridgetek FT9xx endpoint numbers must be unique...
-  #define EPNUM_MIDI_OUT   0x02
-  #define EPNUM_MIDI_IN   0x03
+  #define EPNUM_MIDI_OUT  0x02
+  #define EPNUM_MIDI_IN   0x82
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_MIDI_OUT  0x02
+  #define EPNUM_MIDI_IN   0x81
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_MIDI_OUT  0x01
+  #define EPNUM_MIDI_IN   0x82
+
 #else
-  #define EPNUM_MIDI_OUT   0x01
-  #define EPNUM_MIDI_IN   0x01
+  #define EPNUM_MIDI_OUT  0x01
+  #define EPNUM_MIDI_IN   0x81
 #endif
 
-uint8_t const desc_fs_configuration[] =
-{
+uint8_t const desc_fs_configuration[] = {
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
@@ -104,8 +107,7 @@ uint8_t const desc_fs_configuration[] =
 };
 
 #if TUD_OPT_HIGH_SPEED
-uint8_t const desc_hs_configuration[] =
-{
+uint8_t const desc_hs_configuration[] = {
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
@@ -117,8 +119,7 @@ uint8_t const desc_hs_configuration[] =
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
 
 #if TUD_OPT_HIGH_SPEED
@@ -133,51 +134,66 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
-{
+char const *string_desc_arr[] = {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) {
+        return NULL;
+      }
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      const size_t max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) {
+        chr_count = max_count;
+      }
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/midi_test_freertos/CMakeLists.txt b/examples/device/midi_test_freertos/CMakeLists.txt
new file mode 100644
index 000000000..6ce9e72fe
--- /dev/null
+++ b/examples/device/midi_test_freertos/CMakeLists.txt
@@ -0,0 +1,33 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/midi_test_freertos/Makefile b/examples/device/midi_test_freertos/Makefile
new file mode 100644
index 000000000..26cd83486
--- /dev/null
+++ b/examples/device/midi_test_freertos/Makefile
@@ -0,0 +1,15 @@
+RTOS = freertos
+include ../../build_system/make/make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+  src/main.c \
+  src/usb_descriptors.c \
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/midi_test_freertos/skip.txt b/examples/device/midi_test_freertos/skip.txt
new file mode 100644
index 000000000..650bf355b
--- /dev/null
+++ b/examples/device/midi_test_freertos/skip.txt
@@ -0,0 +1,16 @@
+mcu:CH32V103
+mcu:CH32V20X
+mcu:CH32V307
+mcu:CXD56
+mcu:F1C100S
+mcu:GD32VF103
+mcu:MCXA15
+mcu:MKL25ZXX
+mcu:MSP430x5xx
+mcu:RP2040
+mcu:SAMD11
+mcu:SAMX7X
+mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
+family:broadcom_32bit
+family:broadcom_64bit
diff --git a/examples/device/midi_test_freertos/src/CMakeLists.txt b/examples/device/midi_test_freertos/src/CMakeLists.txt
new file mode 100644
index 000000000..9bd427c89
--- /dev/null
+++ b/examples/device/midi_test_freertos/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS main.c usb_descriptors.c
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/midi_test_freertos/src/main.c b/examples/device/midi_test_freertos/src/main.c
new file mode 100644
index 000000000..dbe89080c
--- /dev/null
+++ b/examples/device/midi_test_freertos/src/main.c
@@ -0,0 +1,239 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+/* This MIDI example send sequence of note (on/off) repeatedly. To test on PC, you need to install
+ * synth software and midi connection management software. On
+ * - Linux (Ubuntu): install qsynth, qjackctl. Then connect TinyUSB output port to FLUID Synth input port
+ * - Windows: install MIDI-OX
+ * - MacOS: SimpleSynth
+ */
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+  #define USBD_STACK_SIZE     4096
+#else
+  // Increase stack size when debug log is enabled
+  #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+#define MIDI_STACK_SIZE     configMINIMAL_STACK_SIZE
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t  usb_device_stack[USBD_STACK_SIZE];
+StaticTask_t usb_device_taskdef;
+
+StackType_t  midi_stack[MIDI_STACK_SIZE];
+StaticTask_t midi_taskdef;
+#endif
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+void usb_device_task(void *param);
+void led_blinking_task(void* param);
+void midi_task(void* param);
+
+//--------------------------------------------------------------------+
+// Main
+//--------------------------------------------------------------------+
+int main(void) {
+  board_init();
+
+#if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+  xTaskCreateStatic(midi_task, "midi", MIDI_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, midi_stack, &midi_taskdef);
+#else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(midi_task, "midi", MIDI_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, NULL);
+#endif
+
+#if !TUSB_MCU_VENDOR_ESPRESSIF
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+  vTaskStartScheduler();
+#endif
+
+  return 0;
+}
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+void app_main(void) {
+  main();
+}
+#endif
+
+// USB Device Driver task
+// This top level thread process all usb events and invoke callbacks
+void usb_device_task(void *param) {
+  (void) param;
+
+  // init device stack on configured roothub port
+  // This should be called after scheduler/kernel is started.
+  // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  // RTOS forever loop
+  while (1) {
+    // put this thread to waiting state until there is new events
+    tud_task();
+  }
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void) {
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void) {
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en) {
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// MIDI Task
+//--------------------------------------------------------------------+
+
+// Store example melody as an array of note values
+const uint8_t note_sequence[] = {
+  74,78,81,86,90,93,98,102,57,61,66,69,73,78,81,85,88,92,97,100,97,92,88,85,81,78,
+  74,69,66,62,57,62,66,69,74,78,81,86,90,93,97,102,97,93,90,85,81,78,73,68,64,61,
+  56,61,64,68,74,78,81,86,90,93,98,102
+};
+
+void midi_task(void* param) {
+  (void) param;
+
+  const uint8_t cable_num = 0; // MIDI jack associated with USB endpoint
+  const uint8_t channel   = 0; // 0 for channel 1
+
+  // Variable that holds the current position in the sequence.
+  uint32_t note_pos = 0;
+
+  while (1) {
+    // send note periodically
+    vTaskDelay(286  / portTICK_PERIOD_MS);
+
+    // Previous positions in the note sequence.
+    int previous = (int) (note_pos - 1);
+
+    // If we currently are at position 0, set the
+    // previous position to the last note in the sequence.
+    if (previous < 0) {
+      previous = sizeof(note_sequence) - 1;
+    }
+
+    // Send Note On for current position at full velocity (127) on channel 1.
+    uint8_t note_on[3] = { 0x90 | channel, note_sequence[note_pos], 127 };
+    tud_midi_stream_write(cable_num, note_on, 3);
+
+    // Send Note Off for previous note.
+    uint8_t note_off[3] = { 0x80 | channel, note_sequence[previous], 0};
+    tud_midi_stream_write(cable_num, note_off, 3);
+
+    // Increment position
+    note_pos++;
+
+    // If we are at the end of the sequence, start over.
+    if (note_pos >= sizeof(note_sequence)) {
+      note_pos = 0;
+    }
+
+    // The MIDI interface always creates input and output port/jack descriptors
+    // regardless of these being used or not. Therefore incoming traffic should be read
+    // (possibly just discarded) to avoid the sender blocking in IO
+    while (tud_midi_available()) {
+      uint8_t packet[4];
+      tud_midi_packet_read(packet);
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void* param) {
+  (void) param;
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  while (1) {
+    // Blink every interval ms
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    start_ms += blink_interval_ms;
+
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
+}
diff --git a/examples/device/midi_test_freertos/src/tusb_config.h b/examples/device/midi_test_freertos/src/tusb_config.h
new file mode 100644
index 000000000..0ffdc37fb
--- /dev/null
+++ b/examples/device/midi_test_freertos/src/tusb_config.h
@@ -0,0 +1,108 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_FREERTOS
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC               0
+#define CFG_TUD_MSC               0
+#define CFG_TUD_HID               0
+#define CFG_TUD_MIDI              1
+#define CFG_TUD_VENDOR            0
+
+// MIDI FIFO size of TX and RX
+#define CFG_TUD_MIDI_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_MIDI_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/midi_test_freertos/src/usb_descriptors.c b/examples/device/midi_test_freertos/src/usb_descriptors.c
new file mode 100644
index 000000000..384742ae8
--- /dev/null
+++ b/examples/device/midi_test_freertos/src/usb_descriptors.c
@@ -0,0 +1,199 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+                           _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device = {
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0200,
+    .bDeviceClass       = 0x00,
+    .bDeviceSubClass    = 0x00,
+    .bDeviceProtocol    = 0x00,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void) {
+  return (uint8_t const *) &desc_device;
+}
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+enum {
+  ITF_NUM_MIDI = 0,
+  ITF_NUM_MIDI_STREAMING,
+  ITF_NUM_TOTAL
+};
+
+#define CONFIG_TOTAL_LEN  (TUD_CONFIG_DESC_LEN + TUD_MIDI_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_MIDI_OUT  0x02
+  #define EPNUM_MIDI_IN   0x82
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_MIDI_OUT  0x02
+  #define EPNUM_MIDI_IN   0x81
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_MIDI_OUT  0x01
+  #define EPNUM_MIDI_IN   0x82
+
+#else
+  #define EPNUM_MIDI_OUT  0x01
+  #define EPNUM_MIDI_IN   0x81
+#endif
+
+uint8_t const desc_fs_configuration[] = {
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+  // Interface number, string index, EP Out & EP In address, EP size
+  TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI_OUT, (0x80 | EPNUM_MIDI_IN), 64)
+};
+
+#if TUD_OPT_HIGH_SPEED
+uint8_t const desc_hs_configuration[] = {
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+  // Interface number, string index, EP Out & EP In address, EP size
+  TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI_OUT, (0x80 | EPNUM_MIDI_IN), 512)
+};
+#endif
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index) {
+  (void) index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_hs_configuration : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] = {
+  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+  "TinyUSB",                     // 1: Manufacturer
+  "TinyUSB Device",              // 2: Product
+  NULL,                          // 3: Serials will use unique ID if possible
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+      if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) {
+        return NULL;
+      }
+
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      const size_t max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) {
+        chr_count = max_count;
+      }
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt
index 9e834ae21..3955bfb49 100644
--- a/examples/device/msc_dual_lun/CMakeLists.txt
+++ b/examples/device/msc_dual_lun/CMakeLists.txt
@@ -1,29 +1,39 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
-add_executable(${PROJECT})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+if (RTOS STREQUAL zephyr)
+  set(EXE_NAME app)
+else()
+  set(EXE_NAME ${PROJECT})
+  add_executable(${EXE_NAME})
+endif()
 
 # Example source
-target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk_dual.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+target_sources(${EXE_NAME} PRIVATE
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk_dual.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
-target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+target_include_directories(${EXE_NAME} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${EXE_NAME} ${RTOS})
diff --git a/examples/device/msc_dual_lun/Makefile b/examples/device/msc_dual_lun/Makefile
index 5a455078e..7fa475da5 100644
--- a/examples/device/msc_dual_lun/Makefile
+++ b/examples/device/msc_dual_lun/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
   src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/msc_dual_lun/prj.conf b/examples/device/msc_dual_lun/prj.conf
new file mode 100644
index 000000000..2f5139d9d
--- /dev/null
+++ b/examples/device/msc_dual_lun/prj.conf
@@ -0,0 +1,6 @@
+CONFIG_GPIO=y
+CONFIG_FPU=y
+CONFIG_NO_OPTIMIZATIONS=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_NRFX_POWER=y
+CONFIG_NRFX_UARTE0=y
diff --git a/examples/device/msc_dual_lun/skip.txt b/examples/device/msc_dual_lun/skip.txt
index 3549c702a..a9e3a99b1 100644
--- a/examples/device/msc_dual_lun/skip.txt
+++ b/examples/device/msc_dual_lun/skip.txt
@@ -1,2 +1,3 @@
 mcu:SAMD11
-mcu:MKL25ZXX
\ No newline at end of file
+mcu:MKL25ZXX
+family:espressif
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index 96790d20c..012095dca 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
@@ -39,7 +39,7 @@
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
-enum  {
+enum {
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
@@ -50,20 +50,24 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 void led_blinking_task(void);
 
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
 
-  while (1)
-  {
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  while (1) {
     tud_task(); // tinyusb device task
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -71,42 +75,37 @@ int main(void)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
-  blink_interval_ms = BLINK_MOUNTED;
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index 2b773b43b..b44b77c6c 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
@@ -34,9 +34,13 @@
 // Some MCU doesn't have enough 8KB SRAM to store the whole disk
 // We will use Flash as read-only disk with board that has
 // CFG_EXAMPLE_MSC_READONLY defined
+#if defined(CFG_EXAMPLE_MSC_READONLY) || defined(CFG_EXAMPLE_MSC_DUAL_READONLY)
+  #define MSC_CONST const
+#else
+  #define MSC_CONST
+#endif
 
-enum
-{
+enum {
   DISK_BLOCK_NUM  = 16, // 8KB is the smallest size that windows allow to mount
   DISK_BLOCK_SIZE = 512
 };
@@ -51,10 +55,7 @@ If you find any bugs or get any questions, feel free to file an\r\n\
 issue at github.com/hathach/tinyusb"
 
 
-#ifdef CFG_EXAMPLE_MSC_READONLY
-const
-#endif
-uint8_t msc_disk0[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
+MSC_CONST uint8_t msc_disk0[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
 {
   //------------- Block0: Boot Sector -------------//
   // byte_per_sector    = DISK_BLOCK_SIZE; fat12_sector_num_16  = DISK_BLOCK_NUM;
@@ -132,10 +133,7 @@ uint8_t msc_disk0[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
 If you find any bugs or get any questions, feel free to file an\r\n\
 issue at github.com/hathach/tinyusb"
 
-#ifdef CFG_EXAMPLE_MSC_READONLY
-const
-#endif
-uint8_t msc_disk1[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
+MSC_CONST uint8_t msc_disk1[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
 {
   //------------- Block0: Boot Sector -------------//
   // byte_per_sector    = DISK_BLOCK_SIZE; fat12_sector_num_16  = DISK_BLOCK_NUM;
@@ -206,15 +204,13 @@ uint8_t msc_disk1[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
 };
 
 // Invoked to determine max LUN
-uint8_t tud_msc_get_maxlun_cb(void)
-{
+uint8_t tud_msc_get_maxlun_cb(void) {
   return 2; // dual LUN
 }
 
 // Invoked when received SCSI_CMD_INQUIRY
 // Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively
-void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4])
-{
+void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) {
   (void) lun; // use same ID for both LUNs
 
   const char vid[] = "TinyUSB";
@@ -228,8 +224,7 @@ void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16
 
 // Invoked when received Test Unit Ready command.
 // return true allowing host to read/write this LUN e.g SD card inserted
-bool tud_msc_test_unit_ready_cb(uint8_t lun)
-{
+bool tud_msc_test_unit_ready_cb(uint8_t lun) {
   if ( lun == 1 && board_button_read() ) return false;
 
   return true; // RAM disk is always ready
@@ -237,8 +232,7 @@ bool tud_msc_test_unit_ready_cb(uint8_t lun)
 
 // Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size
 // Application update block count and block size
-void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_size)
-{
+void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_size) {
   (void) lun;
 
   *block_count = DISK_BLOCK_NUM;
@@ -248,18 +242,14 @@ void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_siz
 // Invoked when received Start Stop Unit command
 // - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage
 // - Start = 1 : active mode, if load_eject = 1 : load disk storage
-bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject)
-{
+bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject) {
   (void) lun;
   (void) power_condition;
 
-  if ( load_eject )
-  {
-    if (start)
-    {
+  if (load_eject) {
+    if (start) {
       // load disk storage
-    }else
-    {
+    } else {
       // unload disk storage
     }
   }
@@ -269,10 +259,9 @@ bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, boo
 
 // Callback invoked when received READ10 command.
 // Copy disk's data to buffer (up to bufsize) and return number of copied bytes.
-int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize)
-{
+int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize) {
   // out of ramdisk
-  if ( lba >= DISK_BLOCK_NUM ) return -1;
+  if (lba >= DISK_BLOCK_NUM) return -1;
 
   uint8_t const* addr = (lun ? msc_disk1[lba] : msc_disk0[lba]) + offset;
   memcpy(buffer, addr, bufsize);
@@ -280,11 +269,10 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
   return (int32_t) bufsize;
 }
 
-bool tud_msc_is_writable_cb (uint8_t lun)
-{
+bool tud_msc_is_writable_cb(uint8_t lun) {
   (void) lun;
 
-#ifdef CFG_EXAMPLE_MSC_READONLY
+#if defined(CFG_EXAMPLE_MSC_READONLY) || defined(CFG_EXAMPLE_MSC_DUAL_READONLY)
   return false;
 #else
   return true;
@@ -293,16 +281,18 @@ bool tud_msc_is_writable_cb (uint8_t lun)
 
 // Callback invoked when received WRITE10 command.
 // Process data in buffer to disk's storage and return number of written bytes
-int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize)
-{
+int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize) {
   // out of ramdisk
-  if ( lba >= DISK_BLOCK_NUM ) return -1;
+  if (lba >= DISK_BLOCK_NUM) return -1;
 
-#ifndef CFG_EXAMPLE_MSC_READONLY
+#if defined(CFG_EXAMPLE_MSC_READONLY) || defined(CFG_EXAMPLE_MSC_DUAL_READONLY)
+  (void) lun;
+  (void) lba;
+  (void) offset;
+  (void) buffer;
+#else
   uint8_t* addr = (lun ? msc_disk1[lba] : msc_disk0[lba])  + offset;
   memcpy(addr, buffer, bufsize);
-#else
-  (void) lun; (void) lba; (void) offset; (void) buffer;
 #endif
 
   return (int32_t) bufsize;
@@ -310,38 +300,30 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
 
 // Callback invoked when received an SCSI command not in built-in list below
 // - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE
-// - READ10 and WRITE10 has their own callbacks
-int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize)
-{
-  // read10 & write10 has their own callback and MUST not be handled here
-
+// - READ10 and WRITE10 has their own callbacks (MUST not be handled here)
+int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize) {
   void const* response = NULL;
   int32_t resplen = 0;
 
   // most scsi handled is input
   bool in_xfer = true;
 
-  switch (scsi_cmd[0])
-  {
+  switch (scsi_cmd[0]) {
     default:
       // Set Sense = Invalid Command Operation
       tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
 
       // negative means error -> tinyusb could stall and/or response with failed status
-      resplen = -1;
-    break;
+      return -1;
   }
 
   // return resplen must not larger than bufsize
-  if ( resplen > bufsize ) resplen = bufsize;
+  if (resplen > bufsize) resplen = bufsize;
 
-  if ( response && (resplen > 0) )
-  {
-    if(in_xfer)
-    {
+  if (response && (resplen > 0)) {
+    if (in_xfer) {
       memcpy(buffer, response, (size_t) resplen);
-    }else
-    {
+    } else {
       // SCSI output
     }
   }
diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c
index 68a671c91..efb9a966d 100644
--- a/examples/device/msc_dual_lun/src/usb_descriptors.c
+++ b/examples/device/msc_dual_lun/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -84,11 +85,17 @@ enum
   #define EPNUM_MSC_OUT   0x02
   #define EPNUM_MSC_IN    0x82
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
-  // SAMG doesn't support a same endpoint number with different direction IN and OUT
-  //  e.g EP1 OUT & EP1 IN cannot exist together
-  #define EPNUM_MSC_OUT   0x01
-  #define EPNUM_MSC_IN    0x82
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_MSC_OUT  0x02
+  #define EPNUM_MSC_IN   0x81
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_MSC_OUT  0x01
+  #define EPNUM_MSC_IN   0x82
 
 #else
   #define EPNUM_MSC_OUT   0x01
@@ -135,51 +142,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456789012",                // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 9fe1a325e..87b92f4dc 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -1,83 +1,101 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
+include(${CMAKE_CURRENT_LIST_DIR}/../../../hw/bsp/family_support.cmake)
 
-if (EXISTS ${TOP}/lib/lwip/src)
-    include(${TOP}/hw/bsp/family_support.cmake)
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-    # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
-    family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+# Prefer the tinyusb lwip
+set(LWIP ${TOP}/lib/lwip)
 
-    project(${PROJECT})
+# If we can't find one from tinyusb then check cmake var before giving up
+if (NOT EXISTS ${LWIP}/src)
+  set(LWIP ${TINYUSB_LWIP_PATH})
+endif()
 
-    # Checks this example is valid for the family and initializes the project
-    family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+if (NOT EXISTS ${LWIP}/src)
+  family_example_missing_dependency(${PROJECT} "lib/lwip")
+  return()
+endif()
 
-    add_executable(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
-    # Example source
-    target_sources(${PROJECT} PUBLIC
-            ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-            ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-            )
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
-    # Example include
-    target_include_directories(${PROJECT} PUBLIC
-            ${CMAKE_CURRENT_SOURCE_DIR}/src
-            ${TOP}/lib/lwip/src/include
-            ${TOP}/lib/lwip/src/include/ipv4
-            ${TOP}/lib/lwip/src/include/lwip/apps
-            ${TOP}/lib/networking
-            )
+add_executable(${PROJECT})
 
-    target_sources(${PROJECT} PUBLIC
-            ${TOP}/lib/lwip/src/core/altcp.c
-            ${TOP}/lib/lwip/src/core/altcp_alloc.c
-            ${TOP}/lib/lwip/src/core/altcp_tcp.c
-            ${TOP}/lib/lwip/src/core/def.c
-            ${TOP}/lib/lwip/src/core/dns.c
-            ${TOP}/lib/lwip/src/core/inet_chksum.c
-            ${TOP}/lib/lwip/src/core/init.c
-            ${TOP}/lib/lwip/src/core/ip.c
-            ${TOP}/lib/lwip/src/core/mem.c
-            ${TOP}/lib/lwip/src/core/memp.c
-            ${TOP}/lib/lwip/src/core/netif.c
-            ${TOP}/lib/lwip/src/core/pbuf.c
-            ${TOP}/lib/lwip/src/core/raw.c
-            ${TOP}/lib/lwip/src/core/stats.c
-            ${TOP}/lib/lwip/src/core/sys.c
-            ${TOP}/lib/lwip/src/core/tcp.c
-            ${TOP}/lib/lwip/src/core/tcp_in.c
-            ${TOP}/lib/lwip/src/core/tcp_out.c
-            ${TOP}/lib/lwip/src/core/timeouts.c
-            ${TOP}/lib/lwip/src/core/udp.c
-            ${TOP}/lib/lwip/src/core/ipv4/autoip.c
-            ${TOP}/lib/lwip/src/core/ipv4/dhcp.c
-            ${TOP}/lib/lwip/src/core/ipv4/etharp.c
-            ${TOP}/lib/lwip/src/core/ipv4/icmp.c
-            ${TOP}/lib/lwip/src/core/ipv4/igmp.c
-            ${TOP}/lib/lwip/src/core/ipv4/ip4.c
-            ${TOP}/lib/lwip/src/core/ipv4/ip4_addr.c
-            ${TOP}/lib/lwip/src/core/ipv4/ip4_frag.c
-            ${TOP}/lib/lwip/src/netif/ethernet.c
-            ${TOP}/lib/lwip/src/netif/slipif.c
-            ${TOP}/lib/lwip/src/apps/http/httpd.c
-            ${TOP}/lib/lwip/src/apps/http/fs.c
-            ${TOP}/lib/networking/dhserver.c
-            ${TOP}/lib/networking/dnserver.c
-            ${TOP}/lib/networking/rndis_reports.c
-            )
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}/src/main.c
+  ${CMAKE_CURRENT_LIST_DIR}/src/usb_descriptors.c
+  )
 
-    # due to warnings from other net source, we need to prevent error from some of the warnings options
-    target_compile_options(${PROJECT} PUBLIC
-        -Wno-error=null-dereference
-        -Wno-error=conversion
-        -Wno-error=sign-conversion
-        -Wno-error=sign-compare
-        )
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}/src
+  ${LWIP}/src/include
+  ${LWIP}/src/include/ipv4
+  ${LWIP}/src/include/lwip/apps
+  ${TOP}/lib/networking
+  )
 
-    # Configure compilation flags and libraries for the example... see the corresponding function
-    # in hw/bsp/FAMILY/family.cmake for details.
-    family_configure_device_example(${PROJECT})
-endif()
\ No newline at end of file
+# lib/networking sources
+target_sources(${PROJECT} PUBLIC
+  ${TOP}/lib/networking/dhserver.c
+  ${TOP}/lib/networking/dnserver.c
+  ${TOP}/lib/networking/rndis_reports.c
+  )
+
+# lwip sources
+target_sources(${PROJECT} PUBLIC
+  ${LWIP}/src/core/altcp.c
+  ${LWIP}/src/core/altcp_alloc.c
+  ${LWIP}/src/core/altcp_tcp.c
+  ${LWIP}/src/core/def.c
+  ${LWIP}/src/core/dns.c
+  ${LWIP}/src/core/inet_chksum.c
+  ${LWIP}/src/core/init.c
+  ${LWIP}/src/core/ip.c
+  ${LWIP}/src/core/mem.c
+  ${LWIP}/src/core/memp.c
+  ${LWIP}/src/core/netif.c
+  ${LWIP}/src/core/pbuf.c
+  ${LWIP}/src/core/raw.c
+  ${LWIP}/src/core/stats.c
+  ${LWIP}/src/core/sys.c
+  ${LWIP}/src/core/tcp.c
+  ${LWIP}/src/core/tcp_in.c
+  ${LWIP}/src/core/tcp_out.c
+  ${LWIP}/src/core/timeouts.c
+  ${LWIP}/src/core/udp.c
+  ${LWIP}/src/core/ipv4/autoip.c
+  ${LWIP}/src/core/ipv4/dhcp.c
+  ${LWIP}/src/core/ipv4/etharp.c
+  ${LWIP}/src/core/ipv4/icmp.c
+  ${LWIP}/src/core/ipv4/igmp.c
+  ${LWIP}/src/core/ipv4/ip4.c
+  ${LWIP}/src/core/ipv4/ip4_addr.c
+  ${LWIP}/src/core/ipv4/ip4_frag.c
+  ${LWIP}/src/netif/ethernet.c
+  ${LWIP}/src/netif/slipif.c
+  ${LWIP}/src/apps/http/httpd.c
+  ${LWIP}/src/apps/http/fs.c
+  ${LWIP}/src/apps/lwiperf/lwiperf.c
+  )
+
+# due to warnings from other net source, we need to prevent error from some of the warnings options
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+  target_compile_options(${PROJECT} PUBLIC
+    -Wno-error=null-dereference
+    -Wno-error=conversion
+    -Wno-error=sign-conversion
+    -Wno-error=sign-compare
+    )
+elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+
+endif ()
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index 881866a56..141532466 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -1,10 +1,9 @@
 DEPS_SUBMODULES += lib/lwip
 
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 # suppress warning caused by lwip
-CFLAGS += \
+CFLAGS_GCC += \
   -Wno-error=null-dereference \
   -Wno-error=unused-parameter \
   -Wno-error=unused-variable
@@ -64,8 +63,9 @@ SRC_C += \
   lib/lwip/src/netif/slipif.c \
   lib/lwip/src/apps/http/httpd.c \
   lib/lwip/src/apps/http/fs.c \
+  lib/lwip/src/apps/lwiperf/lwiperf.c \
   lib/networking/dhserver.c \
   lib/networking/dnserver.c \
   lib/networking/rndis_reports.c
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt
index 68761b058..5ebe71612 100644
--- a/examples/device/net_lwip_webserver/skip.txt
+++ b/examples/device/net_lwip_webserver/skip.txt
@@ -1,10 +1,19 @@
+mcu:CH32V103
+mcu:CH32V20X
 mcu:LPC11UXX
 mcu:LPC13XX
+mcu:LPC15XX
+mcu:MCXA15
 mcu:MSP430x5xx
 mcu:NUC121
 mcu:SAMD11
 mcu:STM32L0
-mcu:MKL25ZXX
+mcu:STM32F0
+mcu:KINETIS_KL
 family:broadcom_64bit
 family:broadcom_32bit
-board:curiosity_nano
\ No newline at end of file
+family:espressif
+board:curiosity_nano
+board:frdm_kl25z
+# lpc55 has weird error 'ncm_interface' causes a section type conflict with 'ntb_parameters'
+family:lpc55
diff --git a/examples/device/net_lwip_webserver/src/arch/bpstruct.h b/examples/device/net_lwip_webserver/src/arch/bpstruct.h
new file mode 100644
index 000000000..74ead358f
--- /dev/null
+++ b/examples/device/net_lwip_webserver/src/arch/bpstruct.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#if defined(__ICCARM__)
+#pragma pack(1)
+#endif
diff --git a/examples/device/net_lwip_webserver/src/arch/cc.h b/examples/device/net_lwip_webserver/src/arch/cc.h
index 56a0cacf7..9f30b91cb 100644
--- a/examples/device/net_lwip_webserver/src/arch/cc.h
+++ b/examples/device/net_lwip_webserver/src/arch/cc.h
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
@@ -11,21 +11,21 @@
  *    this list of conditions and the following disclaimer in the documentation
  *    and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
+ *    derived from this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  * OF SUCH DAMAGE.
  *
  * This file is part of the lwIP TCP/IP stack.
- * 
+ *
  * Author: Adam Dunkels <adam@sics.se>
  *
  */
@@ -42,7 +42,7 @@ typedef int sys_prot_t;
 #if defined (__ICCARM__)
 
 #define PACK_STRUCT_BEGIN
-#define PACK_STRUCT_STRUCT 
+#define PACK_STRUCT_STRUCT
 #define PACK_STRUCT_END
 #define PACK_STRUCT_FIELD(x) x
 #define PACK_STRUCT_USE_INCLUDES
@@ -50,7 +50,7 @@ typedef int sys_prot_t;
 #elif defined (__CC_ARM)
 
 #define PACK_STRUCT_BEGIN __packed
-#define PACK_STRUCT_STRUCT 
+#define PACK_STRUCT_STRUCT
 #define PACK_STRUCT_END
 #define PACK_STRUCT_FIELD(x) x
 
diff --git a/examples/device/net_lwip_webserver/src/arch/epstruct.h b/examples/device/net_lwip_webserver/src/arch/epstruct.h
new file mode 100644
index 000000000..f6390959e
--- /dev/null
+++ b/examples/device/net_lwip_webserver/src/arch/epstruct.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#if defined(__ICCARM__)
+#pragma pack()
+#endif
diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h
index a215017c7..41e8f0d67 100644
--- a/examples/device/net_lwip_webserver/src/lwipopts.h
+++ b/examples/device/net_lwip_webserver/src/lwipopts.h
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
@@ -11,21 +11,21 @@
  *    this list of conditions and the following disclaimer in the documentation
  *    and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
+ *    derived from this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  * OF SUCH DAMAGE.
  *
  * This file is part of the lwIP TCP/IP stack.
- * 
+ *
  * Author: Simon Goldschmidt
  *
  */
@@ -48,8 +48,8 @@
 #define LWIP_IP_ACCEPT_UDP_PORT(p)      ((p) == PP_NTOHS(67))
 
 #define TCP_MSS                         (1500 /*mtu*/ - 20 /*iphdr*/ - 20 /*tcphhr*/)
-#define TCP_SND_BUF                     (2 * TCP_MSS)
-#define TCP_WND                         (TCP_MSS)
+#define TCP_SND_BUF                     (4 * TCP_MSS)
+#define TCP_WND                         (4 * TCP_MSS)
 
 #define ETHARP_SUPPORT_STATIC_ENTRIES   1
 
@@ -59,7 +59,7 @@
 
 #define LWIP_SINGLE_NETIF               1
 
-#define PBUF_POOL_SIZE                  2
+#define PBUF_POOL_SIZE                  4
 
 #define HTTPD_USE_CUSTOM_FSDATA         0
 
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 33b4d38b6..36f402332 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Peter Lawrence
@@ -39,21 +39,26 @@ and likely their manufacturer has not tested such functionality.  Some code work
 The smartphone may only have an ECM driver, but refuse to automatically pick ECM (unlike the OSes above);
 try modifying ./examples/devices/net_lwip_webserver/usb_descriptors.c so that CONFIG_ID_ECM is default.
 
-The smartphone may be artificially picky about which Ethernet MAC address to recognize; if this happens, 
+The smartphone may be artificially picky about which Ethernet MAC address to recognize; if this happens,
 try changing the first byte of tud_network_mac_address[] below from 0x02 to 0x00 (clearing bit 1).
 */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #include "dhserver.h"
 #include "dnserver.h"
+#include "httpd.h"
+#include "lwip/ethip6.h"
 #include "lwip/init.h"
 #include "lwip/timeouts.h"
-#include "lwip/ethip6.h"
-#include "httpd.h"
 
-#define INIT_IP4(a,b,c,d) { PP_HTONL(LWIP_MAKEU32(a,b,c,d)) }
+#ifdef INCLUDE_IPERF
+  #include "lwip/apps/lwiperf.h"
+#endif
+
+#define INIT_IP4(a, b, c, d) \
+  { PP_HTONL(LWIP_MAKEU32(a, b, c, d)) }
 
 /* lwip context */
 static struct netif netif_data;
@@ -64,44 +69,40 @@ static struct pbuf *received_frame;
 /* this is used by this code, ./class/net/net_driver.c, and usb_descriptors.c */
 /* ideally speaking, this should be generated from the hardware's unique ID (if available) */
 /* it is suggested that the first byte is 0x02 to indicate a link-local address */
-const uint8_t tud_network_mac_address[6] = {0x02,0x02,0x84,0x6A,0x96,0x00};
+uint8_t tud_network_mac_address[6] = {0x02, 0x02, 0x84, 0x6A, 0x96, 0x00};
 
 /* network parameters of this MCU */
-static const ip4_addr_t ipaddr  = INIT_IP4(192, 168, 7, 1);
+static const ip4_addr_t ipaddr = INIT_IP4(192, 168, 7, 1);
 static const ip4_addr_t netmask = INIT_IP4(255, 255, 255, 0);
 static const ip4_addr_t gateway = INIT_IP4(0, 0, 0, 0);
 
 /* database IP addresses that can be offered to the host; this must be in RAM to store assigned MAC addresses */
-static dhcp_entry_t entries[] =
-{
-    /* mac ip address                          lease time */
-    { {0}, INIT_IP4(192, 168, 7, 2), 24 * 60 * 60 },
-    { {0}, INIT_IP4(192, 168, 7, 3), 24 * 60 * 60 },
-    { {0}, INIT_IP4(192, 168, 7, 4), 24 * 60 * 60 },
+static dhcp_entry_t entries[] = {
+    /* mac ip address               lease time */
+    {{0}, INIT_IP4(192, 168, 7, 2), 24 * 60 * 60},
+    {{0}, INIT_IP4(192, 168, 7, 3), 24 * 60 * 60},
+    {{0}, INIT_IP4(192, 168, 7, 4), 24 * 60 * 60},
 };
 
-static const dhcp_config_t dhcp_config =
-{
-    .router = INIT_IP4(0, 0, 0, 0),            /* router address (if any) */
-    .port = 67,                                /* listen port */
-    .dns = INIT_IP4(192, 168, 7, 1),           /* dns server (if any) */
-    "usb",                                     /* dns suffix */
-    TU_ARRAY_SIZE(entries),                    /* num entry */
-    entries                                    /* entries */
+static const dhcp_config_t dhcp_config = {
+    .router = INIT_IP4(0, 0, 0, 0),  /* router address (if any) */
+    .port = 67,                      /* listen port */
+    .dns = INIT_IP4(192, 168, 7, 1), /* dns server (if any) */
+    "usb",                           /* dns suffix */
+    TU_ARRAY_SIZE(entries),          /* num entry */
+    entries                          /* entries */
 };
-static err_t linkoutput_fn(struct netif *netif, struct pbuf *p)
-{
-  (void)netif;
 
-  for (;;)
-  {
+static err_t linkoutput_fn(struct netif *netif, struct pbuf *p) {
+  (void) netif;
+
+  for (;;) {
     /* if TinyUSB isn't ready, we must signal back to lwip that there is nothing we can do */
     if (!tud_ready())
       return ERR_USE;
 
     /* if the network driver can accept another packet, we make it happen */
-    if (tud_network_can_xmit(p->tot_len))
-    {
+    if (tud_network_can_xmit(p->tot_len)) {
       tud_network_xmit(p, 0 /* unused for this example */);
       return ERR_OK;
     }
@@ -111,20 +112,17 @@ static err_t linkoutput_fn(struct netif *netif, struct pbuf *p)
   }
 }
 
-static err_t ip4_output_fn(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr)
-{
+static err_t ip4_output_fn(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr) {
   return etharp_output(netif, p, addr);
 }
 
 #if LWIP_IPV6
-static err_t ip6_output_fn(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr)
-{
+static err_t ip6_output_fn(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr) {
   return ethip6_output(netif, p, addr);
 }
 #endif
 
-static err_t netif_init_cb(struct netif *netif)
-{
+static err_t netif_init_cb(struct netif *netif) {
   LWIP_ASSERT("netif != NULL", (netif != NULL));
   netif->mtu = CFG_TUD_NET_MTU;
   netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_UP;
@@ -139,8 +137,7 @@ static err_t netif_init_cb(struct netif *netif)
   return ERR_OK;
 }
 
-static void init_lwip(void)
-{
+static void init_lwip(void) {
   struct netif *netif = &netif_data;
 
   lwip_init();
@@ -158,28 +155,23 @@ static void init_lwip(void)
 }
 
 /* handle any DNS requests from dns-server */
-bool dns_query_proc(const char *name, ip4_addr_t *addr)
-{
-  if (0 == strcmp(name, "tiny.usb"))
-  {
+bool dns_query_proc(const char *name, ip4_addr_t *addr) {
+  if (0 == strcmp(name, "tiny.usb")) {
     *addr = ipaddr;
     return true;
   }
   return false;
 }
 
-bool tud_network_recv_cb(const uint8_t *src, uint16_t size)
-{
-  /* this shouldn't happen, but if we get another packet before 
+bool tud_network_recv_cb(const uint8_t *src, uint16_t size) {
+  /* this shouldn't happen, but if we get another packet before
   parsing the previous, we must signal our inability to accept it */
   if (received_frame) return false;
 
-  if (size)
-  {
+  if (size) {
     struct pbuf *p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL);
 
-    if (p)
-    {
+    if (p) {
       /* pbuf_alloc() has already initialized struct; all we need to do is copy the data */
       memcpy(p->payload, src, size);
 
@@ -191,22 +183,24 @@ bool tud_network_recv_cb(const uint8_t *src, uint16_t size)
   return true;
 }
 
-uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg)
-{
-  struct pbuf *p = (struct pbuf *)ref;
+uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg) {
+  struct pbuf *p = (struct pbuf *) ref;
 
-  (void)arg; /* unused for this example */
+  (void) arg; /* unused for this example */
 
   return pbuf_copy_partial(p, dst, p->tot_len, 0);
 }
 
-static void service_traffic(void)
-{
+static void service_traffic(void) {
   /* handle any packet received by tud_network_recv_cb() */
-  if (received_frame)
-  {
-    ethernet_input(received_frame, &netif_data);
-    pbuf_free(received_frame);
+  if (received_frame) {
+    // Surrender ownership of our pbuf unless there was an error
+    // Only call pbuf_free if not Ok else it will panic with "pbuf_free: p->ref > 0"
+    // or steal it from whatever took ownership of it with undefined consequences.
+    // See: https://savannah.nongnu.org/patch/index.php?10121
+    if (ethernet_input(received_frame, &netif_data)!=ERR_OK) {
+        pbuf_free(received_frame);
+    }
     received_frame = NULL;
     tud_network_recv_renew();
   }
@@ -214,23 +208,28 @@ static void service_traffic(void)
   sys_check_timeouts();
 }
 
-void tud_network_init_cb(void)
-{
+void tud_network_init_cb(void) {
   /* if the network is re-initializing and we have a leftover packet, we must do a cleanup */
-  if (received_frame)
-  {
+  if (received_frame) {
     pbuf_free(received_frame);
     received_frame = NULL;
   }
 }
 
-int main(void)
-{
+int main(void) {
   /* initialize TinyUSB */
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   /* initialize lwip, dhcp-server, dns-server, and http */
   init_lwip();
@@ -239,8 +238,12 @@ int main(void)
   while (dnserv_init(IP_ADDR_ANY, 53, dns_query_proc) != ERR_OK);
   httpd_init();
 
-  while (1)
-  {
+#ifdef INCLUDE_IPERF
+  // test with: iperf -c 192.168.7.1 -e -i 1 -M 5000 -l 8192 -r
+  lwiperf_start_tcp_server_default(NULL, NULL);
+#endif
+
+  while (1) {
     tud_task();
     service_traffic();
   }
@@ -249,17 +252,14 @@ int main(void)
 }
 
 /* lwip has provision for using a mutex, when applicable */
-sys_prot_t sys_arch_protect(void)
-{
+sys_prot_t sys_arch_protect(void) {
   return 0;
 }
-void sys_arch_unprotect(sys_prot_t pval)
-{
-  (void)pval;
+void sys_arch_unprotect(sys_prot_t pval) {
+  (void) pval;
 }
 
 /* lwip needs a millisecond time source, and the TinyUSB board support code has one available */
-uint32_t sys_now(void)
-{
+uint32_t sys_now(void) {
   return board_millis();
 }
diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h
index fe72ecdfe..22082fc81 100644
--- a/examples/device/net_lwip_webserver/src/tusb_config.h
+++ b/examples/device/net_lwip_webserver/src/tusb_config.h
@@ -27,21 +27,23 @@
 #define _TUSB_CONFIG_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "lwipopts.h"
+
 //--------------------------------------------------------------------+
 // Board Specific Configuration
 //--------------------------------------------------------------------+
 
 // RHPort number used for device can be defined by board.mk, default to port 0
 #ifndef BOARD_TUD_RHPORT
-#define BOARD_TUD_RHPORT      0
+  #define BOARD_TUD_RHPORT 0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 #ifndef BOARD_TUD_MAX_SPEED
-#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+  #define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
 #endif
 
 //--------------------------------------------------------------------
@@ -50,22 +52,22 @@
 
 // defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-#error CFG_TUSB_MCU must be defined
+  #error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS           OPT_OS_NONE
+  #define CFG_TUSB_OS OPT_OS_NONE
 #endif
 
 #ifndef CFG_TUSB_DEBUG
-#define CFG_TUSB_DEBUG        0
+  #define CFG_TUSB_DEBUG 0
 #endif
 
 // Enable Device stack
-#define CFG_TUD_ENABLED       1
+#define CFG_TUD_ENABLED 1
 
 // Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -75,11 +77,47 @@
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
 #ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+  #define CFG_TUSB_MEM_SECTION
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
+  #define CFG_TUSB_MEM_ALIGN __attribute__((aligned(4)))
+#endif
+
+// Use different configurations to test all net devices (also due to resource limitations)
+#if TU_CHECK_MCU(OPT_MCU_LPC15XX, OPT_MCU_LPC40XX, OPT_MCU_LPC51UXX, OPT_MCU_LPC54)
+  #define USE_ECM 1
+#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAML21, OPT_MCU_SAML22)
+  #define USE_ECM 1
+#elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1)
+  #define USE_ECM 1
+#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002)
+  #define USE_ECM 1
+#else
+  #define USE_ECM 0
+  #define INCLUDE_IPERF
+#endif
+
+//--------------------------------------------------------------------
+// NCM CLASS CONFIGURATION, SEE "ncm.h" FOR PERFORMANCE TUNING
+//--------------------------------------------------------------------
+
+// Must be >> MTU
+// Can be set to 2048 without impact
+#define CFG_TUD_NCM_IN_NTB_MAX_SIZE (2 * TCP_MSS + 100)
+
+// Must be >> MTU
+// Can be set to smaller values if wNtbOutMaxDatagrams==1
+#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE (2 * TCP_MSS + 100)
+
+// Number of NCM transfer blocks for reception side
+#ifndef CFG_TUD_NCM_OUT_NTB_N
+  #define CFG_TUD_NCM_OUT_NTB_N 1
+#endif
+
+// Number of NCM transfer blocks for transmission side
+#ifndef CFG_TUD_NCM_IN_NTB_N
+  #define CFG_TUD_NCM_IN_NTB_N 1
 #endif
 
 //--------------------------------------------------------------------
@@ -87,18 +125,18 @@
 //--------------------------------------------------------------------
 
 #ifndef CFG_TUD_ENDPOINT0_SIZE
-#define CFG_TUD_ENDPOINT0_SIZE    64
+  #define CFG_TUD_ENDPOINT0_SIZE 64
 #endif
 
 //------------- CLASS -------------//
 
 // Network class has 2 drivers: ECM/RNDIS and NCM.
 // Only one of the drivers can be enabled
-#define CFG_TUD_ECM_RNDIS     1
-#define CFG_TUD_NCM           (1-CFG_TUD_ECM_RNDIS)
+#define CFG_TUD_ECM_RNDIS     USE_ECM
+#define CFG_TUD_NCM           (1 - CFG_TUD_ECM_RNDIS)
 
 #ifdef __cplusplus
- }
+}
 #endif
 
 #endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index bee51790a..cd800f521 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -71,13 +72,16 @@ tusb_desc_device_t const desc_device =
 {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
+#if CFG_TUD_NCM
+    .bcdUSB             = 0x0201,
+#else
     .bcdUSB             = 0x0200,
-
+#endif
     // Use Interface Association Descriptor (IAD) device class
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
     .bDeviceProtocol    = MISC_PROTOCOL_IAD,
-    
+
     .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
     .idVendor           = 0xCafe,
@@ -112,8 +116,15 @@ uint8_t const * tud_descriptor_device_cb(void)
   #define EPNUM_NET_OUT     0x02
   #define EPNUM_NET_IN      0x82
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
-  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_NET_NOTIF   0x83
+  #define EPNUM_NET_OUT     0x02
+  #define EPNUM_NET_IN      0x81
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_NET_NOTIF   0x81
   #define EPNUM_NET_OUT     0x02
@@ -180,6 +191,110 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
   return (index < CONFIG_ID_COUNT) ? configuration_arr[index] : NULL;
 }
 
+#if CFG_TUD_NCM
+//--------------------------------------------------------------------+
+// BOS Descriptor
+//--------------------------------------------------------------------+
+
+/* Used to automatically load the NCM driver on Windows 10, otherwise manual driver install is needed.
+   Associate NCM interface with WINNCM driver. */
+
+/* Microsoft OS 2.0 registry property descriptor
+Per MS requirements https://msdn.microsoft.com/en-us/library/windows/hardware/hh450799(v=vs.85).aspx
+device should create DeviceInterfaceGUIDs. It can be done by driver and
+in case of real PnP solution device should expose MS "Microsoft OS 2.0
+registry property descriptor". Such descriptor can insert any record
+into Windows registry per device/configuration/interface. In our case it
+will insert "DeviceInterfaceGUIDs" multistring property.
+
+GUID is freshly generated and should be OK to use.
+
+https://developers.google.com/web/fundamentals/native-hardware/build-for-webusb/
+(Section Microsoft OS compatibility descriptors)
+*/
+
+#define BOS_TOTAL_LEN      (TUD_BOS_DESC_LEN + TUD_BOS_MICROSOFT_OS_DESC_LEN)
+
+#define MS_OS_20_DESC_LEN  0xB2
+
+// BOS Descriptor is required for webUSB
+uint8_t const desc_bos[] =
+{
+  // total length, number of device caps
+  TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 1),
+
+  // Microsoft OS 2.0 descriptor
+  TUD_BOS_MS_OS_20_DESCRIPTOR(MS_OS_20_DESC_LEN, 1)
+};
+
+uint8_t const * tud_descriptor_bos_cb(void)
+{
+  return desc_bos;
+}
+
+uint8_t const desc_ms_os_20[] =
+{
+  // Set header: length, type, windows version, total length
+  U16_TO_U8S_LE(0x000A), U16_TO_U8S_LE(MS_OS_20_SET_HEADER_DESCRIPTOR), U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(MS_OS_20_DESC_LEN),
+
+  // Configuration subset header: length, type, configuration index, reserved, configuration total length
+  U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_CONFIGURATION), 0, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN-0x0A),
+
+  // Function Subset header: length, type, first interface, reserved, subset length
+  U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_FUNCTION), ITF_NUM_CDC, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN-0x0A-0x08),
+
+  // MS OS 2.0 Compatible ID descriptor: length, type, compatible ID, sub compatible ID
+  U16_TO_U8S_LE(0x0014), U16_TO_U8S_LE(MS_OS_20_FEATURE_COMPATBLE_ID), 'W', 'I', 'N', 'N', 'C', 'M', 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // sub-compatible
+
+  // MS OS 2.0 Registry property descriptor: length, type
+  U16_TO_U8S_LE(MS_OS_20_DESC_LEN-0x0A-0x08-0x08-0x14), U16_TO_U8S_LE(MS_OS_20_FEATURE_REG_PROPERTY),
+  U16_TO_U8S_LE(0x0007), U16_TO_U8S_LE(0x002A), // wPropertyDataType, wPropertyNameLength and PropertyName "DeviceInterfaceGUIDs\0" in UTF-16
+  'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00,
+  'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, 0x00, 0x00,
+  U16_TO_U8S_LE(0x0050), // wPropertyDataLength
+	//bPropertyData: {12345678-0D08-43FD-8B3E-127CA8AFFF9D}
+  '{', 0x00, '1', 0x00, '2', 0x00, '3', 0x00, '4', 0x00, '5', 0x00, '6', 0x00, '7', 0x00, '8', 0x00, '-', 0x00,
+  '0', 0x00, 'D', 0x00, '0', 0x00, '8', 0x00, '-', 0x00, '4', 0x00, '3', 0x00, 'F', 0x00, 'D', 0x00, '-', 0x00,
+  '8', 0x00, 'B', 0x00, '3', 0x00, 'E', 0x00, '-', 0x00, '1', 0x00, '2', 0x00, '7', 0x00, 'C', 0x00, 'A', 0x00,
+  '8', 0x00, 'A', 0x00, 'F', 0x00, 'F', 0x00, 'F', 0x00, '9', 0x00, 'D', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+TU_VERIFY_STATIC(sizeof(desc_ms_os_20) == MS_OS_20_DESC_LEN, "Incorrect size");
+
+// Invoked when a control transfer occurred on an interface of this class
+// Driver response accordingly to the request and the transfer stage (setup/data/ack)
+// return false to stall control endpoint (e.g unsupported request)
+bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) {
+  // nothing to with DATA & ACK stage
+  if (stage != CONTROL_STAGE_SETUP) return true;
+
+  switch (request->bmRequestType_bit.type) {
+    case TUSB_REQ_TYPE_VENDOR:
+      switch (request->bRequest) {
+        case 1:
+          if (request->wIndex == 7) {
+            // Get Microsoft OS 2.0 compatible descriptor
+            uint16_t total_len;
+            memcpy(&total_len, desc_ms_os_20 + 8, 2);
+
+            return tud_control_xfer(rhport, request, (void*)(uintptr_t)desc_ms_os_20, total_len);
+          } else {
+            return false;
+          }
+
+        default: break;
+      }
+      break;
+
+    default: break;
+  }
+
+  // stall unknown request
+  return false;
+}
+
+#endif
 //--------------------------------------------------------------------+
 // String Descriptors
 //--------------------------------------------------------------------+
@@ -190,55 +305,56 @@ static char const* string_desc_arr [] =
   [STRID_LANGID]       = (const char[]) { 0x09, 0x04 }, // supported language is English (0x0409)
   [STRID_MANUFACTURER] = "TinyUSB",                     // Manufacturer
   [STRID_PRODUCT]      = "TinyUSB Device",              // Product
-  [STRID_SERIAL]       = "123456",                      // Serial
+  [STRID_SERIAL]       = NULL,                          // Serials will use unique ID if possible
   [STRID_INTERFACE]    = "TinyUSB Network Interface"    // Interface Description
 
   // STRID_MAC index is handled separately
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
-
   unsigned int chr_count = 0;
 
-  if (STRID_LANGID == index)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[STRID_LANGID], 2);
-    chr_count = 1;
-  }
-  else if (STRID_MAC == index)
-  {
-    // Convert MAC address into UTF-16
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-    for (unsigned i=0; i<sizeof(tud_network_mac_address); i++)
-    {
-      _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 4) & 0xf];
-      _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 0) & 0xf];
-    }
-  }
-  else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    case STRID_MAC:
+      // Convert MAC address into UTF-16
+      for (unsigned i=0; i<sizeof(tud_network_mac_address); i++) {
+        _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 4) & 0xf];
+        _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 0) & 0xf];
+      }
+      break;
 
-    const char* str = string_desc_arr[index];
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > (TU_ARRAY_SIZE(_desc_str) - 1)) chr_count = TU_ARRAY_SIZE(_desc_str) - 1;
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Convert ASCII string into UTF-16
-    for (unsigned int i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt
index abc4d91da..ced98a909 100644
--- a/examples/device/uac2_headset/CMakeLists.txt
+++ b/examples/device/uac2_headset/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
@@ -23,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/uac2_headset/Makefile b/examples/device/uac2_headset/Makefile
index 5a455078e..7fa475da5 100644
--- a/examples/device/uac2_headset/Makefile
+++ b/examples/device/uac2_headset/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
   src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/uac2_headset/skip.txt b/examples/device/uac2_headset/skip.txt
index 70d8e8838..a2a76af0e 100644
--- a/examples/device/uac2_headset/skip.txt
+++ b/examples/device/uac2_headset/skip.txt
@@ -5,3 +5,4 @@ mcu:SAMD11
 mcu:SAME5X
 mcu:SAMG
 board:stm32l052dap52
+family:espressif
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 003dc2a74..6b2ab0973 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenberg
@@ -26,7 +26,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -35,11 +35,7 @@
 //--------------------------------------------------------------------+
 
 // List of supported sample rates
-#if defined(__RX__)
-  const uint32_t sample_rates[] = {44100, 48000};
-#else
-  const uint32_t sample_rates[] = {44100, 48000, 88200, 96000};
-#endif
+const uint32_t sample_rates[] = {44100, 48000};
 
 uint32_t current_sample_rate  = 44100;
 
@@ -79,8 +75,8 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
 // Audio controls
 // Current states
-int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];       // +1 for master channel 0
-int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];    // +1 for master channel 0
+int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];       // +1 for master channel 0
+int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];    // +1 for master channel 0
 
 // Buffer for microphone data
 int32_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ / 4];
@@ -96,6 +92,7 @@ uint8_t current_resolution;
 
 void led_blinking_task(void);
 void audio_task(void);
+void audio_control_task(void);
 
 /*------------- MAIN -------------*/
 int main(void)
@@ -103,7 +100,15 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   TU_LOG1("Headset running\r\n");
 
@@ -111,10 +116,9 @@ int main(void)
   {
     tud_task(); // TinyUSB device task
     audio_task();
+    audio_control_task();
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -145,7 +149,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 // Helper for clock get requests
@@ -157,7 +161,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
   {
     if (request->bRequest == AUDIO_CS_REQ_CUR)
     {
-      TU_LOG1("Clock get current freq %lu\r\n", current_sample_rate);
+      TU_LOG1("Clock get current freq %" PRIu32 "\r\n", current_sample_rate);
 
       audio_control_cur_4_t curf = { (int32_t) tu_htole32(current_sample_rate) };
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
@@ -176,7 +180,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
         rangef.subrange[i].bRes = 0;
         TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
       }
-      
+
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
     }
   }
@@ -206,7 +210,7 @@ static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t
 
     current_sample_rate = (uint32_t) ((audio_control_cur_4_t const *)buf)->bCur;
 
-    TU_LOG1("Clock set current freq: %ld\r\n", current_sample_rate);
+    TU_LOG1("Clock set current freq: %" PRIu32 "\r\n", current_sample_rate);
 
     return true;
   }
@@ -229,7 +233,7 @@ static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_req
     TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
     return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
   }
-  else if (UAC2_ENTITY_SPK_FEATURE_UNIT && request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+  else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
   {
     if (request->bRequest == AUDIO_CS_REQ_RANGE)
     {
@@ -426,6 +430,45 @@ void audio_task(void)
   }
 }
 
+void audio_control_task(void)
+{
+  // Press on-board button to control volume
+  // Open host volume control, volume should switch between 10% and 100%
+
+  // Poll every 50ms
+  const uint32_t interval_ms = 50;
+  static uint32_t start_ms = 0;
+  static uint32_t btn_prev = 0;
+
+  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  start_ms += interval_ms;
+
+  uint32_t btn = board_button_read();
+
+  if (!btn_prev && btn)
+  {
+    // Adjust volume between 0dB (100%) and -30dB (10%)
+    for (int i = 0; i < CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1; i++)
+    {
+      volume[i] = volume[i] == 0 ? -VOLUME_CTRL_30_DB : 0;
+    }
+
+    // 6.1 Interrupt Data Message
+    const audio_interrupt_data_t data = {
+      .bInfo = 0,                                       // Class-specific interrupt, originated from an interface
+      .bAttribute = AUDIO_CS_REQ_CUR,                   // Caused by current settings
+      .wValue_cn_or_mcn = 0,                            // CH0: master volume
+      .wValue_cs = AUDIO_FU_CTRL_VOLUME,                // Volume change
+      .wIndex_ep_or_int = 0,                            // From the interface itself
+      .wIndex_entity_id = UAC2_ENTITY_SPK_FEATURE_UNIT, // From feature unit
+    };
+
+    tud_audio_int_write(&data);
+  }
+
+  btn_prev = btn;
+}
+
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index 1a3e23e95..c921a37ae 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -105,17 +105,18 @@ extern "C" {
 // AUDIO CLASS DRIVER CONFIGURATION
 //--------------------------------------------------------------------
 
+// Allow volume controlled by on-baord button
+#define CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP                            1
+
 #define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                TUD_AUDIO_HEADSET_STEREO_DESC_LEN
 
 // How many formats are used, need to adjust USB descriptor if changed
 #define CFG_TUD_AUDIO_FUNC_1_N_FORMATS                               2
 
 // Audio format type I specifications
-#if defined(__RX__)
-#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         48000     // 16bit/48kHz is the best quality for Renesas RX
-#else
-#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000     // 24bit/96kHz is the best quality for full-speed, high-speed is needed beyond this
-#endif
+/* 24bit/48kHz is the best quality for headset or 24bit/96kHz for 2ch speaker,
+   high-speed is needed beyond this */
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         48000
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                           1
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                           2
 
@@ -145,17 +146,17 @@ extern "C" {
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
 
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)*2
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)*4
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN) // Maximum EP IN size for all AS alternate settings used
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_OUT               1
 
-#define CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
-#define CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_OUT   TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_OUT   TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
 
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT)*2
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT) // Maximum EP IN size for all AS alternate settings used
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_OUT)*2
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_OUT) // Maximum EP IN size for all AS alternate settings used
 
 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
 #define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	          2
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 10f5cbd27..bc9160d5e 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Ha Thach (tinyusb.org)
@@ -24,6 +24,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -46,7 +47,7 @@ tusb_desc_device_t const desc_device =
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = 0x0200,
 
-    // Use Interface Association Descriptor (IAD) for CDC
+    // Use Interface Association Descriptor (IAD) for Audio
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
@@ -81,30 +82,41 @@ uint8_t const * tud_descriptor_device_cb(void)
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
   #define EPNUM_AUDIO_IN    0x03
   #define EPNUM_AUDIO_OUT   0x03
+  #define EPNUM_AUDIO_INT   0x01
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  // #define EPNUM_AUDIO_IN    0x01
+  // #define EPNUM_AUDIO_OUT   0x02
+  // #define EPNUM_AUDIO_INT   0x03
 
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
   // ISO endpoints for NRF5x are fixed to 0x08 (0x88)
   #define EPNUM_AUDIO_IN    0x08
   #define EPNUM_AUDIO_OUT   0x08
+  #define EPNUM_AUDIO_INT   0x01
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
-  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_AUDIO_IN    0x01
   #define EPNUM_AUDIO_OUT   0x02
+  #define EPNUM_AUDIO_INT   0x03
 
 #else
   #define EPNUM_AUDIO_IN    0x01
   #define EPNUM_AUDIO_OUT   0x01
+  #define EPNUM_AUDIO_INT   0x02
 #endif
 
 uint8_t const desc_configuration[] =
 {
-    // Interface count, string index, total length, attribute, power in mA
+    // Config number, interface count, string index, total length, attribute, power in mA
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
-    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO_OUT, EPNUM_AUDIO_IN | 0x80)
+    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO_OUT, EPNUM_AUDIO_IN | 0x80, EPNUM_AUDIO_INT | 0x80)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
@@ -120,52 +132,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 },  // 0: is supported language is English (0x0409)
   "TinyUSB",                      // 1: Manufacturer
   "TinyUSB headset",              // 2: Product
-  "000001",                       // 3: Serials, should use chip ID
+  NULL,                           // 3: Serials will use unique ID if possible
   "TinyUSB Speakers",             // 4: Audio Interface
   "TinyUSB Microphone",           // 5: Audio Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
-  (void)langid;
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if (index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }
-  else
-  {
-    // Convert ASCII string into UTF-16
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if (!(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0]))) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if (chr_count > 31) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    for (uint8_t i = 0; i < chr_count; i++)
-    {
-      _desc_str[1 + i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 342b4fac1..da0da83e8 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenbreg
@@ -55,9 +55,10 @@ enum
     + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
     + TUD_AUDIO_DESC_INPUT_TERM_LEN\
     + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_STD_AC_INT_EP_LEN\
     /* Interface 1, Alternate 0 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
-    /* Interface 1, Alternate 0 */\
+    /* Interface 1, Alternate 1 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
@@ -84,11 +85,11 @@ enum
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
 
-#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \
+#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin, _epint) \
     /* Standard Interface Association Descriptor (IAD) */\
-    TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ 3, /*_stridx*/ 0x00),\
+    TUD_AUDIO_DESC_IAD(/*_firstitf*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ ITF_NUM_TOTAL, /*_stridx*/ 0x00),\
     /* Standard AC Interface Descriptor(4.7.1) */\
-    TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+    TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_nEPs*/ 0x01, /*_stridx*/ _stridx),\
     /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
     TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_HEADSET, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
     /* Clock Source Descriptor(4.7.2.1) */\
@@ -103,6 +104,8 @@ enum
     TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
     /* Output Terminal Descriptor(4.7.2.5) */\
     TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+    /* Standard AC Interrupt Endpoint Descriptor(4.8.2.1) */\
+    TUD_AUDIO_DESC_STD_AC_INT_EP(/*_ep*/ _epint, /*_interval*/ 0x01), \
     /* Standard AS Interface Descriptor(4.9.1) */\
     /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
     TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x05),\
@@ -114,7 +117,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ADAPTIVE | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Interface 1, Alternate 2 - alternate interface for data streaming */\
@@ -124,7 +127,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ADAPTIVE | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Standard AS Interface Descriptor(4.9.1) */\
@@ -138,7 +141,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
     /* Interface 2, Alternate 2 - alternate interface for data streaming */\
@@ -148,7 +151,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
diff --git a/examples/device/uac2_speaker_fb/CMakeLists.txt b/examples/device/uac2_speaker_fb/CMakeLists.txt
new file mode 100644
index 000000000..0ed3db646
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/CMakeLists.txt
@@ -0,0 +1,34 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/quirk_os_guessing.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/uac2_speaker_fb/Makefile b/examples/device/uac2_speaker_fb/Makefile
new file mode 100644
index 000000000..7fa475da5
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/Makefile
@@ -0,0 +1,11 @@
+include ../../build_system/make/make.mk
+
+INC += \
+  src \
+  $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/uac2_speaker_fb/skip.txt b/examples/device/uac2_speaker_fb/skip.txt
new file mode 100644
index 000000000..234f1ebed
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/skip.txt
@@ -0,0 +1,8 @@
+mcu:LPC11UXX
+mcu:LPC13XX
+mcu:NUC121
+mcu:SAMD11
+mcu:SAME5X
+mcu:SAMG
+board:stm32l052dap52
+family:broadcom_64bit
diff --git a/examples/device/uac2_speaker_fb/src/audio_debug.py b/examples/device/uac2_speaker_fb/src/audio_debug.py
new file mode 100755
index 000000000..05b49baf6
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/audio_debug.py
@@ -0,0 +1,70 @@
+#!/usr/bin/env python3
+# Install python3 HID package https://pypi.org/project/hid/
+# Install python3 matplotlib package https://pypi.org/project/matplotlib/
+
+from ctypes import *
+try:
+    import hid
+    import matplotlib.pyplot as plt
+    import matplotlib.animation as animation
+except:
+    print("Missing import, please try 'pip install hid matplotlib' or consult your OS's python package manager.")
+
+# Example must be compiled with CFG_AUDIO_DEBUG=1
+VID = 0xcafe
+PID = 0x4014
+
+CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX = 2
+
+class audio_debug_info_t (Structure):
+    _fields_ = [("sample_rate", c_uint32),
+                ("alt_settings", c_uint8),
+                ("mute", (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1) * c_int8),
+                ("volume", (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1) * c_int16),
+                ("fifo_size", c_uint16),
+                ("fifo_count", c_uint16),
+                ("fifo_count_avg", c_uint16)
+                ]
+
+dev = hid.Device(VID, PID)
+
+if dev:
+    # Create figure for plotting
+    fig = plt.figure()
+    ax = fig.add_subplot(1, 1, 1)
+    fifo_avg = []
+    fifo_cnt = []
+    # This function is called periodically from FuncAnimation
+    def animate(i):
+        info = None
+        for i in range(30):
+            try:
+                str_in = dev.read(64, 50)
+                info = audio_debug_info_t.from_buffer_copy(str_in)
+
+                global fifo_avg
+                global fifo_cnt
+                fifo_avg.append(info.fifo_count_avg)
+                fifo_cnt.append(info.fifo_count)
+            except:
+                exit(1)
+        # Limit to 1000 items
+        fifo_avg = fifo_avg[-1000:]
+        fifo_cnt = fifo_cnt[-1000:]
+
+        if info is not None:
+            # Draw x and y lists
+            ax.clear()
+            ax.plot(fifo_cnt, label='FIFO count')
+            ax.plot(fifo_avg, label='FIFO average')
+            ax.legend()
+            ax.set_ylim(bottom=0, top=info.fifo_size)
+
+            # Format plot
+            plt.title('FIFO information')
+            plt.grid()
+
+            print(f'Sample rate:{info.sample_rate} | Alt settings:{info.alt_settings} | Volume:{info.volume[:]}')
+
+    ani = animation.FuncAnimation(fig, animate, interval=10)
+    plt.show()
diff --git a/examples/device/uac2_speaker_fb/src/common_types.h b/examples/device/uac2_speaker_fb/src/common_types.h
new file mode 100644
index 000000000..174e26671
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/common_types.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _COMMON_TYPES_H_
+#define _COMMON_TYPES_H_
+
+enum
+{
+  ITF_NUM_AUDIO_CONTROL = 0,
+  ITF_NUM_AUDIO_STREAMING,
+#if CFG_AUDIO_DEBUG
+  ITF_NUM_DEBUG,
+#endif
+  ITF_NUM_TOTAL
+};
+
+#if CFG_AUDIO_DEBUG
+typedef struct
+  {
+    uint32_t sample_rate;
+    uint8_t alt_settings;
+    int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];
+    int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];
+    uint16_t fifo_size;
+    uint16_t fifo_count;
+    uint16_t fifo_count_avg;
+  } audio_debug_info_t;
+#endif
+
+#endif
diff --git a/examples/device/uac2_speaker_fb/src/main.c b/examples/device/uac2_speaker_fb/src/main.c
new file mode 100644
index 000000000..ea5a2941d
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/main.c
@@ -0,0 +1,509 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+#include "common_types.h"
+
+#ifdef CFG_QUIRK_OS_GUESSING
+#include "quirk_os_guessing.h"
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+
+// List of supported sample rates
+#if defined(__RX__)
+  const uint32_t sample_rates[] = {44100, 48000};
+#else
+  const uint32_t sample_rates[] = {44100, 48000, 88200, 96000};
+#endif
+
+uint32_t current_sample_rate  = 44100;
+
+#define N_SAMPLE_RATES  TU_ARRAY_SIZE(sample_rates)
+
+/* Blink pattern
+ * - 25 ms   : streaming data
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum
+{
+  BLINK_STREAMING = 25,
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+enum
+{
+  VOLUME_CTRL_0_DB = 0,
+  VOLUME_CTRL_10_DB = 2560,
+  VOLUME_CTRL_20_DB = 5120,
+  VOLUME_CTRL_30_DB = 7680,
+  VOLUME_CTRL_40_DB = 10240,
+  VOLUME_CTRL_50_DB = 12800,
+  VOLUME_CTRL_60_DB = 15360,
+  VOLUME_CTRL_70_DB = 17920,
+  VOLUME_CTRL_80_DB = 20480,
+  VOLUME_CTRL_90_DB = 23040,
+  VOLUME_CTRL_100_DB = 25600,
+  VOLUME_CTRL_SILENCE = 0x8000,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];       // +1 for master channel 0
+int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];    // +1 for master channel 0
+
+// Buffer for speaker data
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ/2];
+
+void led_blinking_task(void);
+void audio_task(void);
+
+#if CFG_AUDIO_DEBUG
+void audio_debug_task(void);
+uint8_t current_alt_settings;
+uint16_t fifo_count;
+uint32_t fifo_count_avg;
+#endif
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  // init device stack on configured roothub port
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  TU_LOG1("Speaker running\r\n");
+
+  while (1)
+  {
+    tud_task(); // TinyUSB device task
+    led_blinking_task();
+#if CFG_AUDIO_DEBUG
+    audio_debug_task();
+#endif
+    audio_task();
+  }
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+  (void)remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Helper for clock get requests
+static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+
+  if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+  {
+    if (request->bRequest == AUDIO_CS_REQ_CUR)
+    {
+      TU_LOG1("Clock get current freq %lu\r\n", current_sample_rate);
+
+      audio_control_cur_4_t curf = { (int32_t) tu_htole32(current_sample_rate) };
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
+    }
+    else if (request->bRequest == AUDIO_CS_REQ_RANGE)
+    {
+      audio_control_range_4_n_t(N_SAMPLE_RATES) rangef =
+      {
+        .wNumSubRanges = tu_htole16(N_SAMPLE_RATES)
+      };
+      TU_LOG1("Clock get %d freq ranges\r\n", N_SAMPLE_RATES);
+      for(uint8_t i = 0; i < N_SAMPLE_RATES; i++)
+      {
+        rangef.subrange[i].bMin = (int32_t) sample_rates[i];
+        rangef.subrange[i].bMax = (int32_t) sample_rates[i];
+        rangef.subrange[i].bRes = 0;
+        TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+      }
+
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
+    }
+  }
+  else if (request->bControlSelector == AUDIO_CS_CTRL_CLK_VALID &&
+           request->bRequest == AUDIO_CS_REQ_CUR)
+  {
+    audio_control_cur_1_t cur_valid = { .bCur = 1 };
+    TU_LOG1("Clock get is valid %u\r\n", cur_valid.bCur);
+    return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_valid, sizeof(cur_valid));
+  }
+  TU_LOG1("Clock get request not supported, entity = %u, selector = %u, request = %u\r\n",
+          request->bEntityID, request->bControlSelector, request->bRequest);
+  return false;
+}
+
+// Helper for clock set requests
+static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+  (void)rhport;
+
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+  TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+  if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t));
+
+    current_sample_rate = (uint32_t) ((audio_control_cur_4_t const *)buf)->bCur;
+
+    TU_LOG1("Clock set current freq: %ld\r\n", current_sample_rate);
+
+    return true;
+  }
+  else
+  {
+    TU_LOG1("Clock set request not supported, entity = %u, selector = %u, request = %u\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+    return false;
+  }
+}
+
+// Helper for feature unit get requests
+static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_FEATURE_UNIT);
+
+  if (request->bControlSelector == AUDIO_FU_CTRL_MUTE && request->bRequest == AUDIO_CS_REQ_CUR)
+  {
+    audio_control_cur_1_t mute1 = { .bCur = mute[request->bChannelNumber] };
+    TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
+    return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
+  }
+  else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+  {
+    if (request->bRequest == AUDIO_CS_REQ_RANGE)
+    {
+      audio_control_range_2_n_t(1) range_vol = {
+        .wNumSubRanges = tu_htole16(1),
+        .subrange[0] = { .bMin = tu_htole16(-VOLUME_CTRL_50_DB), tu_htole16(VOLUME_CTRL_0_DB), tu_htole16(256) }
+      };
+      TU_LOG1("Get channel %u volume range (%d, %d, %u) dB\r\n", request->bChannelNumber,
+              range_vol.subrange[0].bMin / 256, range_vol.subrange[0].bMax / 256, range_vol.subrange[0].bRes / 256);
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &range_vol, sizeof(range_vol));
+    }
+    else if (request->bRequest == AUDIO_CS_REQ_CUR)
+    {
+      audio_control_cur_2_t cur_vol = { .bCur = tu_htole16(volume[request->bChannelNumber]) };
+      TU_LOG1("Get channel %u volume %d dB\r\n", request->bChannelNumber, cur_vol.bCur / 256);
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_vol, sizeof(cur_vol));
+    }
+  }
+  TU_LOG1("Feature unit get request not supported, entity = %u, selector = %u, request = %u\r\n",
+          request->bEntityID, request->bControlSelector, request->bRequest);
+
+  return false;
+}
+
+// Helper for feature unit set requests
+static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+  (void)rhport;
+
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_FEATURE_UNIT);
+  TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+  if (request->bControlSelector == AUDIO_FU_CTRL_MUTE)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_1_t));
+
+    mute[request->bChannelNumber] = ((audio_control_cur_1_t const *)buf)->bCur;
+
+    TU_LOG1("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
+
+    return true;
+  }
+  else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_2_t));
+
+    volume[request->bChannelNumber] = ((audio_control_cur_2_t const *)buf)->bCur;
+
+    TU_LOG1("Set channel %d volume: %d dB\r\n", request->bChannelNumber, volume[request->bChannelNumber] / 256);
+
+    return true;
+  }
+  else
+  {
+    TU_LOG1("Feature unit set request not supported, entity = %u, selector = %u, request = %u\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+    return false;
+  }
+}
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request)
+{
+  audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+  if (request->bEntityID == UAC2_ENTITY_CLOCK)
+    return tud_audio_clock_get_request(rhport, request);
+  if (request->bEntityID == UAC2_ENTITY_FEATURE_UNIT)
+    return tud_audio_feature_unit_get_request(rhport, request);
+  else
+  {
+    TU_LOG1("Get request not handled, entity = %d, selector = %d, request = %d\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+  }
+  return false;
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request, uint8_t *buf)
+{
+  audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+  if (request->bEntityID == UAC2_ENTITY_FEATURE_UNIT)
+    return tud_audio_feature_unit_set_request(rhport, request, buf);
+  if (request->bEntityID == UAC2_ENTITY_CLOCK)
+    return tud_audio_clock_set_request(rhport, request, buf);
+  TU_LOG1("Set request not handled, entity = %d, selector = %d, request = %d\r\n",
+          request->bEntityID, request->bControlSelector, request->bRequest);
+
+  return false;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void)rhport;
+
+  uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+  uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+  if (ITF_NUM_AUDIO_STREAMING == itf && alt == 0)
+      blink_interval_ms = BLINK_MOUNTED;
+
+  return true;
+}
+
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void)rhport;
+  uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+  uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+  TU_LOG2("Set interface %d alt %d\r\n", itf, alt);
+  if (ITF_NUM_AUDIO_STREAMING == itf && alt != 0)
+      blink_interval_ms = BLINK_STREAMING;
+
+#if CFG_AUDIO_DEBUG
+  current_alt_settings = alt;
+#endif
+
+  return true;
+}
+
+void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param)
+{
+  (void)func_id;
+  (void)alt_itf;
+  // Set feedback method to fifo counting
+  feedback_param->method = AUDIO_FEEDBACK_METHOD_FIFO_COUNT;
+  feedback_param->sample_freq = current_sample_rate;
+}
+
+#if CFG_AUDIO_DEBUG
+bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting)
+{
+  (void)rhport;
+  (void)n_bytes_received;
+  (void)func_id;
+  (void)ep_out;
+  (void)cur_alt_setting;
+
+  fifo_count = tud_audio_available();
+  // Same averaging method used in UAC2 class
+  fifo_count_avg = (uint32_t)(((uint64_t)fifo_count_avg * 63  + ((uint32_t)fifo_count << 16)) >> 6);
+
+  return true;
+}
+#endif
+
+#if CFG_QUIRK_OS_GUESSING
+bool tud_audio_feedback_format_correction_cb(uint8_t func_id)
+{
+  (void)func_id;
+  if(tud_speed_get() == TUSB_SPEED_FULL && quirk_os_guessing_get() == QUIRK_OS_GUESSING_OSX) {
+    return true;
+  } else {
+    return false;
+  }
+}
+#endif
+//--------------------------------------------------------------------+
+// AUDIO Task
+//--------------------------------------------------------------------+
+
+void audio_task(void)
+{
+  // Replace audio_task() with your I2S transmit callback.
+  // Here we simulate a callback called every 1ms.
+  static uint32_t start_ms = 0;
+  uint32_t curr_ms = board_millis();
+  if ( start_ms == curr_ms ) return; // not enough time
+  start_ms = curr_ms;
+
+  uint16_t length = (uint16_t) (current_sample_rate/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX);
+
+  if (current_sample_rate == 44100 && (curr_ms % 10 == 0))
+  {
+    // Take one more sample every 10 cycles, to have a average reading speed of 44.1
+    // This correction is not needed in real world cases
+    length += CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX;
+  } else
+  if (current_sample_rate == 88200 && (curr_ms % 5 == 0))
+  {
+    // Take one more sample every 5 cycles, to have a average reading speed of 88.2
+    // This correction is not needed in real world cases
+    length += CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX;
+  }
+
+  tud_audio_read(i2s_dummy_buffer, length);
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if (board_millis() - start_ms < blink_interval_ms) return;
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state;
+}
+
+#if CFG_AUDIO_DEBUG
+//--------------------------------------------------------------------+
+// HID interface for audio debug
+//--------------------------------------------------------------------+
+// Every 1ms, we will sent 1 debug information report
+void audio_debug_task(void)
+{
+  static uint32_t start_ms = 0;
+  uint32_t curr_ms = board_millis();
+  if ( start_ms == curr_ms ) return; // not enough time
+  start_ms = curr_ms;
+
+  audio_debug_info_t debug_info;
+  debug_info.sample_rate    = current_sample_rate;
+  debug_info.alt_settings   = current_alt_settings;
+  debug_info.fifo_size      = CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ;
+  debug_info.fifo_count     = fifo_count;
+  debug_info.fifo_count_avg = (uint16_t) (fifo_count_avg >> 16);
+  for (int i = 0; i < CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1; i++)
+  {
+    debug_info.mute[i] = mute[i];
+    debug_info.volume[i] = volume[i];
+  }
+
+  if(tud_hid_ready())
+    tud_hid_report(0, &debug_info, sizeof(debug_info));
+}
+
+// Invoked when received GET_REPORT control request
+// Unused here
+uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen)
+{
+  // TODO not Implemented
+  (void) itf;
+  (void) report_id;
+  (void) report_type;
+  (void) buffer;
+  (void) reqlen;
+
+  return 0;
+}
+
+// Invoked when received SET_REPORT control request or
+// Unused here
+void tud_hid_set_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
+{
+  // This example doesn't use multiple report and report ID
+  (void) itf;
+  (void) report_id;
+  (void) report_type;
+  (void) buffer;
+  (void) bufsize;
+}
+
+#endif
diff --git a/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c
new file mode 100644
index 000000000..965bbd6cf
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c
@@ -0,0 +1,90 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "quirk_os_guessing.h"
+
+static tusb_desc_type_t desc_req_buf[2];
+static int desc_req_idx = 0;
+
+// Place at the start of tud_descriptor_device_cb()
+void quirk_os_guessing_desc_device_cb() {
+  desc_req_idx = 0;
+}
+
+// Place at the start of tud_descriptor_configuration_cb()
+void quirk_os_guessing_desc_configuration_cb() {
+  // Skip redundant request
+  if (desc_req_idx == 0 || (desc_req_idx == 1 && desc_req_buf[0] != TUSB_DESC_CONFIGURATION)) {
+    desc_req_buf[desc_req_idx++] = TUSB_DESC_CONFIGURATION;
+  }
+}
+
+// Place at the start of tud_descriptor_bos_cb()
+void quirk_os_guessing_desc_bos_cb() {
+  // Skip redundant request
+  if (desc_req_idx == 0 || (desc_req_idx == 1 && desc_req_buf[0] != TUSB_DESC_BOS)) {
+    desc_req_buf[desc_req_idx++] = TUSB_DESC_BOS;
+  }
+}
+
+// Place at the start of tud_descriptor_string_cb()
+void quirk_os_guessing_desc_string_cb() {
+  // Skip redundant request
+  if (desc_req_idx == 0 || (desc_req_idx == 1 && desc_req_buf[0] != TUSB_DESC_STRING)) {
+    desc_req_buf[desc_req_idx++] = TUSB_DESC_STRING;
+  }
+}
+
+// Each OS request descriptors differently:
+// Windows 10 - 11
+//    Device Desc
+//    Config Desc
+//    BOS    Desc
+//    String Desc
+// Linux 3.16 - 6.8
+//    Device Desc
+//    BOS    Desc
+//    Config Desc
+//    String Desc
+// OS X Ventura - Sonoma
+//    Device Desc
+//    String Desc
+//    Config Desc || BOS    Desc
+//    BOS    Desc || Config Desc
+quirk_os_guessing_t quirk_os_guessing_get(void) {
+  if (desc_req_idx < 2) {
+    return QUIRK_OS_GUESSING_UNKNOWN;
+  }
+
+  if (desc_req_buf[0] == TUSB_DESC_BOS && desc_req_buf[1] == TUSB_DESC_CONFIGURATION) {
+    return QUIRK_OS_GUESSING_LINUX;
+  } else if (desc_req_buf[0] == TUSB_DESC_CONFIGURATION && desc_req_buf[1] == TUSB_DESC_BOS) {
+    return QUIRK_OS_GUESSING_WINDOWS;
+  } else if (desc_req_buf[0] == TUSB_DESC_STRING && (desc_req_buf[1] == TUSB_DESC_BOS || desc_req_buf[1] == TUSB_DESC_CONFIGURATION)) {
+    return QUIRK_OS_GUESSING_OSX;
+  }
+
+  return QUIRK_OS_GUESSING_UNKNOWN;
+}
diff --git a/examples/device/uac2_speaker_fb/src/quirk_os_guessing.h b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.h
new file mode 100644
index 000000000..1120355c9
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.h
@@ -0,0 +1,75 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _QUIRK_OS_GUESSING_H_
+#define _QUIRK_OS_GUESSING_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "tusb.h"
+
+//================================== !!! WARNING !!! ====================================
+// This quirk operate out of USB specification in order to workaround specific issues.
+// It may not work on your platform.
+//=======================================================================================
+//
+// Prerequisites:
+// - Set USB version to at least 2.01 in Device Descriptor
+// - Has a valid BOS Descriptor, refer to webusb_serial example
+//
+// Attention:
+//   Windows detection result comes out after Configuration Descriptor request,
+//   meaning it will be too late to do descriptor adjustment. It's advised to make
+//   Windows as default configuration and adjust to other OS accordingly.
+
+typedef enum {
+  QUIRK_OS_GUESSING_UNKNOWN,
+  QUIRK_OS_GUESSING_LINUX,
+  QUIRK_OS_GUESSING_OSX,
+  QUIRK_OS_GUESSING_WINDOWS,
+} quirk_os_guessing_t;
+
+// Get Host OS type
+quirk_os_guessing_t quirk_os_guessing_get(void);
+
+// Place at the start of tud_descriptor_device_cb()
+void quirk_os_guessing_desc_device_cb(void);
+
+// Place at the start of tud_descriptor_configuration_cb()
+void quirk_os_guessing_desc_configuration_cb(void);
+
+// Place at the start of tud_descriptor_bos_cb()
+void quirk_os_guessing_desc_bos_cb(void);
+
+// Place at the start of tud_descriptor_string_cb()
+void quirk_os_guessing_desc_string_cb(void);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _QUIRK_OS_GUESSING_H_ */
diff --git a/examples/device/uac2_speaker_fb/src/tusb_config.h b/examples/device/uac2_speaker_fb/src/tusb_config.h
new file mode 100644
index 000000000..fd4925c7f
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/tusb_config.h
@@ -0,0 +1,168 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+// It's recommended to disable debug unless for control requests debugging,
+// as the extra time needed will impact data stream !
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
+/* (Needed for Full-Speed only)
+ * Enable host OS guessing to workaround UAC2 compatibility issues between Windows and OS X
+ * The default configuration only support Windows and Linux, enable this option for OS X
+ * support. Otherwise if you don't need Windows support you can make OS X's configuration as
+ * default.
+ */
+#define CFG_QUIRK_OS_GUESSING   1
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+// Expose audio class debug information via HID interface
+#ifndef CFG_AUDIO_DEBUG
+#define CFG_AUDIO_DEBUG           1
+#endif
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+#define CFG_TUD_HID_EP_BUFSIZE    64
+
+//------------- CLASS -------------//
+#define CFG_TUD_AUDIO             1
+
+#if CFG_AUDIO_DEBUG
+#define CFG_TUD_HID               1
+#else
+#define CFG_TUD_HID               0
+#endif
+
+#define CFG_TUD_CDC               0
+#define CFG_TUD_MSC               0
+#define CFG_TUD_MIDI              0
+#define CFG_TUD_VENDOR            0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                TUD_AUDIO_SPEAKER_STEREO_FB_DESC_LEN
+
+// Enable if Full-Speed on OSX, also set feedback EP size to 3
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION              0
+
+// Audio format type I specifications
+#if defined(__RX__)
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         48000
+#else
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000
+#endif
+
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                           2
+
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX                   2
+#define CFG_TUD_AUDIO_FUNC_1_RESOLUTION_RX                           16
+
+// EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
+#define CFG_TUD_AUDIO_ENABLE_EP_OUT                                  1
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX // Example read FIFO every 1ms, so it should be 8 times larger for HS device
+
+// Enable feedback EP
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP                             1
+
+// Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	                             1
+
+// Size of control request buffer
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ	                         64
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/uac2_speaker_fb/src/usb_descriptors.c b/examples/device/uac2_speaker_fb/src/usb_descriptors.c
new file mode 100644
index 000000000..ee1b92225
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/usb_descriptors.c
@@ -0,0 +1,288 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+#include "common_types.h"
+
+#ifdef CFG_QUIRK_OS_GUESSING
+#include "quirk_os_guessing.h"
+#endif
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]     AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+    _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0201,
+
+    // Use Interface Association Descriptor (IAD) for Audio
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+#if CFG_QUIRK_OS_GUESSING
+  quirk_os_guessing_desc_device_cb();
+#endif
+  return (uint8_t const *)&desc_device;
+}
+
+#if CFG_AUDIO_DEBUG
+//--------------------------------------------------------------------+
+// HID Report Descriptor
+//--------------------------------------------------------------------+
+
+uint8_t const desc_hid_report[] =
+{
+  HID_USAGE_PAGE_N ( HID_USAGE_PAGE_VENDOR, 2   ),\
+  HID_USAGE        ( 0x01                       ),\
+  HID_COLLECTION   ( HID_COLLECTION_APPLICATION ),\
+  HID_USAGE       ( 0x02                                   ),\
+  HID_LOGICAL_MIN ( 0x00                                   ),\
+  HID_LOGICAL_MAX_N ( 0xff, 2                              ),\
+  HID_REPORT_SIZE ( 8                                      ),\
+  HID_REPORT_COUNT( sizeof(audio_debug_info_t)             ),\
+  HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+  HID_COLLECTION_END
+};
+
+// Invoked when received GET HID REPORT DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_hid_descriptor_report_cb(uint8_t itf)
+{
+  (void) itf;
+  return desc_hid_report;
+}
+#endif
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+#if CFG_AUDIO_DEBUG
+  #define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + TUD_AUDIO_SPEAKER_STEREO_FB_DESC_LEN + TUD_HID_DESC_LEN)
+#else
+  #define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + TUD_AUDIO_SPEAKER_STEREO_FB_DESC_LEN)
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO_FB    0x03
+  #define EPNUM_AUDIO_OUT   0x03
+  #define EPNUM_DEBUG       0x04
+
+#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+  // ISO endpoints for NRF5x are fixed to 0x08 (0x88)
+  #define EPNUM_AUDIO_FB    0x08
+  #define EPNUM_AUDIO_OUT   0x08
+  #define EPNUM_DEBUG       0x01
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_AUDIO_FB    0x01
+  #define EPNUM_AUDIO_OUT   0x02
+  #define EPNUM_DEBUG       0x03
+
+#else
+  #define EPNUM_AUDIO_FB    0x01
+  #define EPNUM_AUDIO_OUT   0x01
+  #define EPNUM_DEBUG       0x02
+#endif
+
+uint8_t const desc_configuration_default[] =
+{
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, byte per sample, bit per sample, EP Out, EP size, EP feedback, feedback EP size,
+    TUD_AUDIO_SPEAKER_STEREO_FB_DESCRIPTOR(0, 4, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_RESOLUTION_RX, EPNUM_AUDIO_OUT, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX, EPNUM_AUDIO_FB | 0x80, 4),
+
+#if CFG_AUDIO_DEBUG
+    // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval
+    TUD_HID_DESCRIPTOR(ITF_NUM_DEBUG, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_DEBUG | 0x80, CFG_TUD_HID_EP_BUFSIZE, 7)
+#endif
+};
+
+#if CFG_QUIRK_OS_GUESSING
+// OS X needs 3 bytes feedback endpoint on FS
+uint8_t const desc_configuration_osx_fs[] =
+{
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, byte per sample, bit per sample, EP Out, EP size, EP feedback, feedback EP size,
+    TUD_AUDIO_SPEAKER_STEREO_FB_DESCRIPTOR(0, 4, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_RESOLUTION_RX, EPNUM_AUDIO_OUT, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX, EPNUM_AUDIO_FB | 0x80, 3),
+
+#if CFG_AUDIO_DEBUG
+    // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval
+    TUD_HID_DESCRIPTOR(ITF_NUM_DEBUG, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_DEBUG | 0x80, CFG_TUD_HID_EP_BUFSIZE, 7)
+#endif
+};
+#endif
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void)index; // for multiple configurations
+
+#if CFG_QUIRK_OS_GUESSING
+  quirk_os_guessing_desc_configuration_cb();
+  if(tud_speed_get() == TUSB_SPEED_FULL && quirk_os_guessing_get() == QUIRK_OS_GUESSING_OSX) {
+    return desc_configuration_osx_fs;
+  }
+#endif
+  return desc_configuration_default;
+}
+
+//--------------------------------------------------------------------+
+// BOS Descriptor, required for OS guessing quirk
+//--------------------------------------------------------------------+
+
+#define TUD_BOS_USB20_EXT_DESC_LEN  7
+
+#define BOS_TOTAL_LEN      (TUD_BOS_DESC_LEN + TUD_BOS_USB20_EXT_DESC_LEN)
+
+// BOS Descriptor is required for webUSB
+uint8_t const desc_bos[] =
+{
+  // total length, number of device caps
+  TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 1),
+
+  // USB 2.0 Extension Descriptor
+  0x07, TUSB_DESC_DEVICE_CAPABILITY, DEVICE_CAPABILITY_USB20_EXTENSION, 0x00, 0x00, 0x00,0x00
+};
+
+uint8_t const * tud_descriptor_bos_cb(void)
+{
+#if CFG_QUIRK_OS_GUESSING
+  quirk_os_guessing_desc_bos_cb();
+#endif
+  return desc_bos;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] =
+{
+  (const char[]) { 0x09, 0x04 },  // 0: is supported language is English (0x0409)
+  "TinyUSB",                      // 1: Manufacturer
+  "TinyUSB Speaker",              // 2: Product
+  NULL,                           // 3: Serials will use unique ID if possible
+  "UAC2 Speaker",                 // 4: Audio Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+#if CFG_QUIRK_OS_GUESSING
+  quirk_os_guessing_desc_string_cb();
+#endif
+
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/device/uac2_speaker_fb/src/usb_descriptors.h b/examples/device/uac2_speaker_fb/src/usb_descriptors.h
new file mode 100644
index 000000000..9511bf797
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/usb_descriptors.h
@@ -0,0 +1,82 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+// Defined in TUD_AUDIO_SPEAKER_STEREO_FB_DESCRIPTOR
+#define UAC2_ENTITY_CLOCK               0x04
+#define UAC2_ENTITY_INPUT_TERMINAL      0x01
+#define UAC2_ENTITY_FEATURE_UNIT        0x02
+#define UAC2_ENTITY_OUTPUT_TERMINAL     0x03
+
+#define TUD_AUDIO_SPEAKER_STEREO_FB_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+  + TUD_AUDIO_DESC_STD_AC_LEN\
+  + TUD_AUDIO_DESC_CS_AC_LEN\
+  + TUD_AUDIO_DESC_CLK_SRC_LEN\
+  + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+  + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+  + TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN\
+  + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+  + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+  + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+  + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+  + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+  + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+  + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN)
+
+#define TUD_AUDIO_SPEAKER_STEREO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epoutsize, _epfb, _epfbsize) \
+  /* Standard Interface Association Descriptor (IAD) */\
+  TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  /* Standard AC Interface Descriptor(4.7.1) */\
+  TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+  /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+  TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_DESKTOP_SPEAKER, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+  /* Clock Source Descriptor(4.7.2.1) */\
+  TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_PRO_CLK, /*_ctrl*/ (AUDIO_CTRL_RW << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01,  /*_stridx*/ 0x00),\
+  /* Input Terminal Descriptor(4.7.2.4) */\
+  TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
+  /* Output Terminal Descriptor(4.7.2.5) */\
+  TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_OUT_DESKTOP_SPEAKER, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+  /* Feature Unit Descriptor(4.7.2.8) */\
+  TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch2*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS,/*_stridx*/ 0x00),\
+  /* Standard AS Interface Descriptor(4.9.1) */\
+  /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+  TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
+  /* Standard AS Interface Descriptor(4.9.1) */\
+  /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+  TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x01, /*_nEPs*/ 0x02, /*_stridx*/ 0x00),\
+  /* Class-Specific AS Interface Descriptor(4.9.2) */\
+  TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x01, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+  /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+  TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
+  /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
+  /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+  TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+  /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
+  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_epsize*/ _epfbsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 4 : 1)\
+
+#endif
diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt
index c49603c26..d2deb72d5 100644
--- a/examples/device/usbtmc/CMakeLists.txt
+++ b/examples/device/usbtmc/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
@@ -24,6 +29,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/usbtmc/Makefile b/examples/device/usbtmc/Makefile
index 69b633fea..1b4d398cf 100644
--- a/examples/device/usbtmc/Makefile
+++ b/examples/device/usbtmc/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/usbtmc/skip.txt b/examples/device/usbtmc/skip.txt
index a43106cf0..ccff857ac 100644
--- a/examples/device/usbtmc/skip.txt
+++ b/examples/device/usbtmc/skip.txt
@@ -1 +1,2 @@
 mcu:BCM2835
+family:espressif
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 6945d8743..aa7902a15 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usbtmc_app.h"
 //--------------------------------------------------------------------+
@@ -55,7 +55,15 @@ int main(void)
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
@@ -63,8 +71,6 @@ int main(void)
     led_blinking_task();
     usbtmc_app_task_iter();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -95,7 +101,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/usbtmc/src/usb_descriptors.c b/examples/device/usbtmc/src/usb_descriptors.c
index ff682ff97..85acd990a 100644
--- a/examples/device/usbtmc/src/usb_descriptors.c
+++ b/examples/device/usbtmc/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "class/usbtmc/usbtmc.h"
 #include "class/usbtmc/usbtmc_device.h"
@@ -37,7 +38,7 @@
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
                            _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
 
-#define USB_VID   0xCafe
+#define USB_VID   0xcafe
 #define USB_BCD   0x0200
 
 //--------------------------------------------------------------------+
@@ -47,8 +48,8 @@ tusb_desc_device_t const desc_device =
 {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
-    .bcdUSB             = 0x0200,
-    .bDeviceClass       = 0x00,
+    .bcdUSB             = USB_BCD,
+    .bDeviceClass       = TUSB_CLASS_UNSPECIFIED,
     .bDeviceSubClass    = 0x00,
     .bDeviceProtocol    = 0x00,
 
@@ -56,7 +57,7 @@ tusb_desc_device_t const desc_device =
 
     .idVendor           = USB_VID,
     .idProduct          = USB_PID,
-    .bcdDevice          = USB_BCD,
+    .bcdDevice          = 0x0100,
 
     .iManufacturer      = 0x01,
     .iProduct           = 0x02,
@@ -111,17 +112,6 @@ enum
 
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_USBTMC_DESC_LEN)
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
-  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
-  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
-  // Note: since CDC EP ( 1 & 2), HID (4) are spot-on, thus we only need to force
-  // endpoint number for MSC to 5
-  #define EPNUM_MSC   0x05
-#else
-  #define EPNUM_MSC   0x03
-#endif
-
-
 uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
@@ -150,7 +140,7 @@ tusb_desc_device_qualifier_t const desc_device_qualifier =
   .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
   .bcdUSB             = USB_BCD,
 
-  .bDeviceClass       = 0x00,
+  .bDeviceClass       = TUSB_CLASS_UNSPECIFIED,
   .bDeviceSubClass    = 0x00,
   .bDeviceProtocol    = 0x00,
 
@@ -188,55 +178,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB USBTMC",              // 4: USBTMC
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
-
   size_t chr_count;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }
-  else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    const char* str = string_desc_arr[index];
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) {
-      chr_count = 31;
-    }
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t)((((uint16_t)TUSB_DESC_STRING) << 8 ) | (2u*chr_count + 2u));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index 8f87a6dca..fb25982c7 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -23,10 +23,10 @@
  *
  */
 
-#include <strings.h>
+#include <string.h>
 #include <stdlib.h>     /* atoi */
 #include "tusb.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "main.h"
 
 #if (CFG_TUD_USBTMC_ENABLE_488)
@@ -88,14 +88,6 @@ static size_t buffer_tx_ix; // for transmitting using multiple transfers
 static uint8_t buffer[225]; // A few packets long should be enough.
 
 
-static usbtmc_msg_dev_dep_msg_in_header_t rspMsg = {
-    .bmTransferAttributes =
-    {
-      .EOM = 1,
-      .UsingTermChar = 0
-    }
-};
-
 void tud_usbtmc_open_cb(uint8_t interface_id)
 {
   (void)interface_id;
@@ -148,11 +140,14 @@ bool tud_usbtmc_msg_data_cb(void *data, size_t len, bool transfer_complete)
   queryState = transfer_complete;
   idnQuery = 0;
 
-  if(transfer_complete && (len >=4) && !strncasecmp("*idn?",data,4))
+  if ( transfer_complete && (len >= 4) &&
+       (!strncmp("*idn?", data, 4) || !strncmp("*IDN?", data, 4)) )
   {
     idnQuery = 1;
   }
-  if(transfer_complete && !strncasecmp("delay ",data,5))
+
+  if ( transfer_complete &&
+       (!strncmp("delay ", data, 5) || !strncmp("DELAY ", data, 5)) )
   {
     queryState = 0;
     int d = atoi((char*)data + 5);
@@ -184,9 +179,6 @@ static unsigned int msgReqLen;
 
 bool tud_usbtmc_msgBulkIn_request_cb(usbtmc_msg_request_dev_dep_in const * request)
 {
-  rspMsg.header.MsgID = request->header.MsgID,
-  rspMsg.header.bTag = request->header.bTag,
-  rspMsg.header.bTagInverse = request->header.bTagInverse;
   msgReqLen = request->TransferSize;
 
 #ifdef xDEBUG
@@ -250,7 +242,6 @@ void usbtmc_app_task_iter(void) {
     break;
   default:
     TU_ASSERT(false,);
-    return;
   }
 }
 
diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py
old mode 100644
new mode 100755
index c4e5ad2b9..ca65daf97
--- a/examples/device/usbtmc/visaQuery.py
+++ b/examples/device/usbtmc/visaQuery.py
@@ -36,8 +36,8 @@ def test_trig():
 	time.sleep(0.3) # SRQ may have some delay
 	assert (inst.read_stb() & 0x40), "SRQ not set after 0.3 seconds"
 	assert (inst.read_stb() == 0)
-	
-	
+
+
 def test_mav():
 	inst.write("delay 50")
 	inst.read_stb() # clear STB
@@ -45,15 +45,15 @@ def test_mav():
 	inst.write("123")
 	time.sleep(0.3)
 	assert (inst.read_stb() & 0x10), "MAV not set after 0.5 seconds"
-	
+
 	rsp = inst.read()
 	assert(rsp == "123\r\n")
-	
-	
+
+
 def test_srq():
 	assert (inst.read_stb() == 0)
 	inst.write("123")
-	
+
 	#inst.enable_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE)
 	#waitrsp = inst.wait_on_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, 5000)
 	#inst.discard_events(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE)
@@ -64,7 +64,7 @@ def test_srq():
 	assert (stb == 0x50),msg
 
 	assert (inst.read_stb() == 0x10), "SRQ set at second read!"
-	
+
 	rsp = inst.read()
 	assert(rsp == "123\r\n")
 
@@ -110,7 +110,7 @@ def test_abort_in():
 	inst.timeout = 800
 	y = inst.read()
 	assert(y == "xxx\r\n")
-	
+
 def test_indicate():
 	# perform indicator pulse
 	usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM)
@@ -120,8 +120,8 @@ def test_indicate():
 		assert(retv == b'\x01')
 	else:
 		assert((retv[1] == pyvisa.constants.StatusCode(0)) and (retv[0] == b'\x01')), f"indicator pulse failed: retv={retv}"
-	
-	
+
+
 def test_multi_read():
 	old_chunk_size = inst.chunk_size
 	longstr = "0123456789abcdefghijklmnopqrstuvwxyz" * 10
@@ -133,7 +133,7 @@ def test_multi_read():
 	y = inst.read()
 	assert (x + "\r\n" == y)
 	#inst.chunk_size = old_chunk_size
-	
+
 def test_stall_ep0():
 	usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM)
 	inst.read_stb()
@@ -143,7 +143,7 @@ def test_stall_ep0():
 		assert(False)
 	except pyvisa.VisaIOError:
 		pass
-	
+
 	assert (inst.read_stb() == 0)
 
 
@@ -153,7 +153,7 @@ print(reslist)
 
 if (len(reslist) == 0):
     sys.exit()
-	
+
 inst = rm.open_resource(reslist[0]);
 inst.timeout = 3000
 
diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt
index b92a2b804..90788fa60 100644
--- a/examples/device/video_capture/CMakeLists.txt
+++ b/examples/device/video_capture/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 if (FORCE_READONLY)
@@ -29,6 +34,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
 )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/video_capture/Makefile b/examples/device/video_capture/Makefile
index fda66bcc1..d698a848d 100644
--- a/examples/device/video_capture/Makefile
+++ b/examples/device/video_capture/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 ifeq ($(DISABLE_MJPEG),1)
 CFLAGS += -DCFG_EXAMPLE_VIDEO_DISABLE_MJPEG
@@ -16,4 +15,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/video_capture/skip.txt b/examples/device/video_capture/skip.txt
index 5898664a2..50302c544 100644
--- a/examples/device/video_capture/skip.txt
+++ b/examples/device/video_capture/skip.txt
@@ -1,3 +1,6 @@
+mcu:CH32V103
+mcu:CH32V20X
+mcu:MCXA15
 mcu:MSP430x5xx
 mcu:NUC121
 mcu:SAMD11
diff --git a/examples/device/video_capture/src/CMakeLists.txt b/examples/device/video_capture/src/CMakeLists.txt
new file mode 100644
index 000000000..cef2b46ee
--- /dev/null
+++ b/examples/device/video_capture/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c" "usb_descriptors.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h
index 0398428b3..ac372cb16 100644
--- a/examples/device/video_capture/src/images.h
+++ b/examples/device/video_capture/src/images.h
@@ -1,4 +1,5 @@
-#if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
+#if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+// uncopmressed frame
 static const unsigned char frame_buffer[128 * (96 + 1) * 2] = {
   /* 0 */
   0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
@@ -1650,8 +1651,10 @@ static const unsigned char frame_buffer[128 * (96 + 1) * 2] = {
   0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
   0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
 };
+
 #else
 
+// mpeg compressed data (not CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
 #define color_bar_0_jpg_len  511
 #define color_bar_1_jpg_len  512
 #define color_bar_2_jpg_len  511
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 3ceebe821..04d4af4e5 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -40,7 +40,7 @@
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
-enum  {
+enum {
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
@@ -48,26 +48,42 @@ enum  {
 
 static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
-void led_blinking_task(void);
-void video_task(void);
+void led_blinking_task(void* param);
+void usb_device_task(void *param);
+void video_task(void* param);
 
-/*------------- MAIN -------------*/
-int main(void)
-{
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+void freertos_init_task(void);
+#endif
+
+
+//--------------------------------------------------------------------+
+// Main
+//--------------------------------------------------------------------+
+int main(void) {
   board_init();
 
+  // If using FreeRTOS: create blinky, tinyusb device, video task
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  freertos_init_task();
+#else
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
 
-  while (1)
-  {
-    tud_task(); // tinyusb device task
-    led_blinking_task();
-
-    video_task();
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
   }
 
-  return 0;
+  while (1) {
+    tud_task(); // tinyusb device task
+    led_blinking_task(NULL);
+    video_task(NULL);
+  }
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -75,33 +91,28 @@ int main(void)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
-  blink_interval_ms = BLINK_MOUNTED;
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
-
 //--------------------------------------------------------------------+
 // USB Video
 //--------------------------------------------------------------------+
@@ -109,11 +120,12 @@ static unsigned frame_num = 0;
 static unsigned tx_busy = 0;
 static unsigned interval_ms = 1000 / FRAME_RATE;
 
-/* YUY2 frame buffer */
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
+// For mcus that does not have enough SRAM for frame buffer, we use fixed frame data.
+// To further reduce the size, we use MJPEG format instead of YUY2.
 #include "images.h"
 
-# if !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
+#if !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
 static struct {
   uint32_t       size;
   uint8_t const *buffer;
@@ -127,29 +139,30 @@ static struct {
   {color_bar_6_jpg_len, color_bar_6_jpg},
   {color_bar_7_jpg_len, color_bar_7_jpg},
 };
-# endif
+#endif
 
 #else
+
+// YUY2 frame buffer
 static uint8_t frame_buffer[FRAME_WIDTH * FRAME_HEIGHT * 16 / 8];
-static void fill_color_bar(uint8_t *buffer, unsigned start_position)
-{
-  /* EBU color bars
-   * See also https://stackoverflow.com/questions/6939422 */
+
+static void fill_color_bar(uint8_t* buffer, unsigned start_position) {
+  /* EBU color bars: https://stackoverflow.com/questions/6939422 */
   static uint8_t const bar_color[8][4] = {
-    /*  Y,   U,   Y,   V */
-    { 235, 128, 235, 128}, /* 100% White */
-    { 219,  16, 219, 138}, /* Yellow */
-    { 188, 154, 188,  16}, /* Cyan */
-    { 173,  42, 173,  26}, /* Green */
-    {  78, 214,  78, 230}, /* Magenta */
-    {  63, 102,  63, 240}, /* Red */
-    {  32, 240,  32, 118}, /* Blue */
-    {  16, 128,  16, 128}, /* Black */
+      /*  Y,   U,   Y,   V */
+      { 235, 128, 235, 128}, /* 100% White */
+      { 219,  16, 219, 138}, /* Yellow */
+      { 188, 154, 188,  16}, /* Cyan */
+      { 173,  42, 173,  26}, /* Green */
+      {  78, 214,  78, 230}, /* Magenta */
+      {  63, 102,  63, 240}, /* Red */
+      {  32, 240,  32, 118}, /* Blue */
+      {  16, 128,  16, 128}, /* Black */
   };
-  uint8_t *p;
+  uint8_t* p;
 
   /* Generate the 1st line */
-  uint8_t *end = &buffer[FRAME_WIDTH * 2];
+  uint8_t* end = &buffer[FRAME_WIDTH * 2];
   unsigned idx = (FRAME_WIDTH / 2 - 1) - (start_position % (FRAME_WIDTH / 2));
   p = &buffer[idx * 4];
   for (unsigned i = 0; i < 8; ++i) {
@@ -161,6 +174,7 @@ static void fill_color_bar(uint8_t *buffer, unsigned start_position)
       }
     }
   }
+
   /* Duplicate the 1st line to the others */
   p = &buffer[FRAME_WIDTH * 2];
   for (unsigned i = 1; i < FRAME_HEIGHT; ++i) {
@@ -168,32 +182,33 @@ static void fill_color_bar(uint8_t *buffer, unsigned start_position)
     p += FRAME_WIDTH * 2;
   }
 }
+
 #endif
 
-void video_task(void)
-{
+static void video_send_frame(void) {
   static unsigned start_ms = 0;
   static unsigned already_sent = 0;
 
   if (!tud_video_n_streaming(0, 0)) {
-    already_sent  = 0;
-    frame_num     = 0;
+    already_sent = 0;
+    frame_num = 0;
     return;
   }
 
   if (!already_sent) {
     already_sent = 1;
+    tx_busy = 1;
     start_ms = board_millis();
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
+    #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
     tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
                            FRAME_WIDTH * FRAME_HEIGHT * 16/8);
-# else
+    #else
     tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
-# endif
+    #endif
 #else
     fill_color_bar(frame_buffer, frame_num);
-    tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+    tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8);
 #endif
   }
 
@@ -201,49 +216,144 @@ void video_task(void)
   if (cur - start_ms < interval_ms) return; // not enough time
   if (tx_busy) return;
   start_ms += interval_ms;
+  tx_busy = 1;
 
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
+  #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
   tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
                          FRAME_WIDTH * FRAME_HEIGHT * 16/8);
-# else
+  #else
   tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
-# endif
+  #endif
 #else
   fill_color_bar(frame_buffer, frame_num);
-  tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+  tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8);
 #endif
 }
 
-void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
-{
-  (void)ctl_idx; (void)stm_idx;
+
+void video_task(void* param) {
+  (void) param;
+
+  while(1) {
+    video_send_frame();
+
+    #if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(interval_ms / portTICK_PERIOD_MS);
+    #else
+    return;
+    #endif
+  }
+}
+
+void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) {
+  (void) ctl_idx;
+  (void) stm_idx;
   tx_busy = 0;
   /* flip buffer */
   ++frame_num;
 }
 
 int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
-			video_probe_and_commit_control_t const *parameters)
-{
-  (void)ctl_idx; (void)stm_idx;
+                        video_probe_and_commit_control_t const* parameters) {
+  (void) ctl_idx;
+  (void) stm_idx;
   /* convert unit to ms from 100 ns */
   interval_ms = parameters->dwFrameInterval / 10000;
   return VIDEO_ERROR_NONE;
 }
 
 //--------------------------------------------------------------------+
-// BLINKING TASK
+// Blinking Task
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void* param) {
+  (void) param;
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
-  // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
-  start_ms += blink_interval_ms;
+  while (1) {
+    #if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    #else
+    if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+    #endif
 
-  board_led_write(led_state);
-  led_state = 1 - led_state; // toggle
+    start_ms += blink_interval_ms;
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
 }
+
+//--------------------------------------------------------------------+
+// FreeRTOS
+//--------------------------------------------------------------------+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+#define VIDEO_STACK_SIZE    (configMINIMAL_STACK_SIZE*4)
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+  #define USBD_STACK_SIZE     4096
+  int main(void);
+  void app_main(void) {
+    main();
+  }
+#else
+  // Increase stack size when debug log is enabled
+  #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t  usb_device_stack[USBD_STACK_SIZE];
+StaticTask_t usb_device_taskdef;
+
+StackType_t  video_stack[VIDEO_STACK_SIZE];
+StaticTask_t video_taskdef;
+#endif
+
+// USB Device Driver task
+// This top level thread process all usb events and invoke callbacks
+void usb_device_task(void *param) {
+  (void) param;
+
+  // init device stack on configured roothub port
+  // This should be called after scheduler/kernel is started.
+  // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  // RTOS forever loop
+  while (1) {
+    // put this thread to waiting state until there is new events
+    tud_task();
+  }
+}
+
+void freertos_init_task(void) {
+  #if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+  xTaskCreateStatic(video_task, "cdc", VIDEO_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, video_stack, &video_taskdef);
+  #else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(video_task, "video", VIDEO_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
+  #endif
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+  #if !TUSB_MCU_VENDOR_ESPRESSIF
+  vTaskStartScheduler();
+  #endif
+}
+#endif
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index e567ba669..6dbd6f2a5 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -57,6 +57,11 @@
 #define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
+// Espressif IDF requires "freertos/" prefix in include path
+#if TUSB_MCU_VENDOR_ESPRESSIF
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
 #ifndef CFG_TUSB_DEBUG
 #define CFG_TUSB_DEBUG        0
 #endif
@@ -97,9 +102,15 @@
 // The number of video streaming interfaces
 #define CFG_TUD_VIDEO_STREAMING  1
 
-// video streaming endpoint size
+// video streaming endpoint buffer size
 #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE  256
 
+// use bulk endpoint for streaming interface
+ #define CFG_TUD_VIDEO_STREAMING_BULK 0
+
+//#define CFG_EXAMPLE_VIDEO_READONLY
+//#define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 499ee311c..b3e19b0f0 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -36,14 +37,36 @@
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
     _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VIDEO, 5) | _PID_MAP(VENDOR, 6) )
 
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+  STRID_UVC_CONTROL,
+  STRID_UVC_STREAMING,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr[] = {
+    (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                     // 1: Manufacturer
+    "TinyUSB Device",              // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "UVC Control",                 // 4: UVC Interface
+    "UVC Streaming",               // 5: UVC Interface
+};
+
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
+tusb_desc_device_t const desc_device = {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
-    .bcdUSB             = 0x0200,
+    .bcdUSB             = USB_BCD,
 
     // Use Interface Association Descriptor (IAD) for Video
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
@@ -53,124 +76,411 @@ tusb_desc_device_t const desc_device =
 
     .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-    .idVendor           = 0xCafe,
+    .idVendor           = USB_VID,
     .idProduct          = USB_PID,
     .bcdDevice          = 0x0100,
 
-    .iManufacturer      = 0x01,
-    .iProduct           = 0x02,
-    .iSerialNumber      = 0x03,
+    .iManufacturer      = STRID_MANUFACTURER,
+    .iProduct           = STRID_PRODUCT,
+    .iSerialNumber      = STRID_SERIAL,
 
     .bNumConfigurations = 0x01
 };
 
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
-  return (uint8_t const *) &desc_device;
+uint8_t const* tud_descriptor_device_cb(void) {
+  return (uint8_t const*) &desc_device;
 }
 
 //--------------------------------------------------------------------+
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
-#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN)
-#else
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN)
-#endif
+/* Time stamp base clock. It is a deprecated parameter. */
+#define UVC_CLOCK_FREQUENCY    27000000
 
+/* video capture path */
+#define UVC_ENTITY_CAP_INPUT_TERMINAL  0x01
+#define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02
+
+enum {
+  ITF_NUM_VIDEO_CONTROL,
+  ITF_NUM_VIDEO_STREAMING,
+  ITF_NUM_TOTAL
+};
+
+// Select appropriate endpoint number
 #if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
-  #define EPNUM_VIDEO_IN    0x83
-
+  #define EPNUM_VIDEO_IN    (CFG_TUD_VIDEO_STREAMING_BULK ? 0x82 : 0x83)
 #elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // nRF5x ISO can only be endpoint 8
-  #define EPNUM_VIDEO_IN    0x88
-
+  #define EPNUM_VIDEO_IN    (CFG_TUD_VIDEO_STREAMING_BULK ? 0x81 : 0x88)
+#elif TU_CHECK_MCU(OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX32690, OPT_MCU_MAX78002)
+  #define EPNUM_VIDEO_IN    0x81
 #else
   #define EPNUM_VIDEO_IN    0x81
-
 #endif
 
-uint8_t const desc_fs_configuration[] =
-{
-  // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
-  // IAD for Video Control
 #if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(4, EPNUM_VIDEO_IN,
-                                     FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                     CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+  #define USE_MJPEG 1
 #else
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(4, EPNUM_VIDEO_IN,
-                                       FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                       CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+  #define USE_MJPEG 0
 #endif
+
+#define USE_ISO_STREAMING (!CFG_TUD_VIDEO_STREAMING_BULK)
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_interface_t itf;
+  tusb_desc_video_control_header_1itf_t header;
+  tusb_desc_video_control_camera_terminal_t camera_terminal;
+  tusb_desc_video_control_output_terminal_t output_terminal;
+} uvc_control_desc_t;
+
+/* Windows support YUY2 and NV12
+ * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_interface_t itf;
+  tusb_desc_video_streaming_input_header_1byte_t header;
+
+#if USE_MJPEG
+  tusb_desc_video_format_mjpeg_t format;
+  tusb_desc_video_frame_mjpeg_continuous_t frame;
+#else
+  tusb_desc_video_format_uncompressed_t format;
+  tusb_desc_video_frame_uncompressed_continuous_t frame;
+#endif
+
+  tusb_desc_video_streaming_color_matching_t color;
+
+#if USE_ISO_STREAMING
+  // For ISO streaming, USB spec requires to alternate interface
+  tusb_desc_interface_t itf_alt;
+#endif
+
+  tusb_desc_endpoint_t ep;
+} uvc_streaming_desc_t;
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_configuration_t config;
+  tusb_desc_interface_assoc_t iad;
+  uvc_control_desc_t video_control;
+  uvc_streaming_desc_t video_streaming;
+} uvc_cfg_desc_t;
+
+const uvc_cfg_desc_t desc_fs_configuration = {
+    .config = {
+        .bLength = sizeof(tusb_desc_configuration_t),
+        .bDescriptorType = TUSB_DESC_CONFIGURATION,
+
+        .wTotalLength = sizeof(uvc_cfg_desc_t),
+        .bNumInterfaces = ITF_NUM_TOTAL,
+        .bConfigurationValue = 1,
+        .iConfiguration = 0,
+        .bmAttributes =  TU_BIT(7),
+        .bMaxPower = 100 / 2
+    },
+    .iad = {
+        .bLength = sizeof(tusb_desc_interface_assoc_t),
+        .bDescriptorType = TUSB_DESC_INTERFACE_ASSOCIATION,
+
+        .bFirstInterface = ITF_NUM_VIDEO_CONTROL,
+        .bInterfaceCount = 2,
+        .bFunctionClass = TUSB_CLASS_VIDEO,
+        .bFunctionSubClass = VIDEO_SUBCLASS_INTERFACE_COLLECTION,
+        .bFunctionProtocol = VIDEO_ITF_PROTOCOL_UNDEFINED,
+        .iFunction = 0
+    },
+
+    .video_control = {
+        .itf = {
+            .bLength = sizeof(tusb_desc_interface_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE,
+
+            .bInterfaceNumber = ITF_NUM_VIDEO_CONTROL,
+            .bAlternateSetting = 0,
+            .bNumEndpoints = 0,
+            .bInterfaceClass = TUSB_CLASS_VIDEO,
+            .bInterfaceSubClass = VIDEO_SUBCLASS_CONTROL,
+            .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+            .iInterface = STRID_UVC_CONTROL
+        },
+        .header = {
+            .bLength = sizeof(tusb_desc_video_control_header_1itf_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VC_HEADER,
+
+            .bcdUVC = VIDEO_BCD_1_50,
+            .wTotalLength = sizeof(uvc_control_desc_t) - sizeof(tusb_desc_interface_t), // CS VC descriptors only
+            .dwClockFrequency = UVC_CLOCK_FREQUENCY,
+            .bInCollection = 1,
+            .baInterfaceNr = { ITF_NUM_VIDEO_STREAMING }
+        },
+        .camera_terminal = {
+            .bLength = sizeof(tusb_desc_video_control_camera_terminal_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VC_INPUT_TERMINAL,
+
+            .bTerminalID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+            .wTerminalType = VIDEO_ITT_CAMERA,
+            .bAssocTerminal = 0,
+            .iTerminal = 0,
+            .wObjectiveFocalLengthMin = 0,
+            .wObjectiveFocalLengthMax = 0,
+            .wOcularFocalLength = 0,
+            .bControlSize = 3,
+            .bmControls = { 0, 0, 0 }
+        },
+        .output_terminal = {
+            .bLength = sizeof(tusb_desc_video_control_output_terminal_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VC_OUTPUT_TERMINAL,
+
+            .bTerminalID = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+            .wTerminalType = VIDEO_TT_STREAMING,
+            .bAssocTerminal = 0,
+            .bSourceID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+            .iTerminal = 0
+        }
+    },
+
+    .video_streaming = {
+        .itf = {
+            .bLength = sizeof(tusb_desc_interface_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE,
+
+            .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING,
+            .bAlternateSetting = 0,
+            .bNumEndpoints = CFG_TUD_VIDEO_STREAMING_BULK, // bulk 1, iso 0
+            .bInterfaceClass = TUSB_CLASS_VIDEO,
+            .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING,
+            .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+            .iInterface = STRID_UVC_STREAMING
+        },
+        .header = {
+            .bLength = sizeof(tusb_desc_video_streaming_input_header_1byte_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_INPUT_HEADER,
+
+            .bNumFormats = 1,
+            .wTotalLength = sizeof(uvc_streaming_desc_t) - sizeof(tusb_desc_interface_t)
+                - sizeof(tusb_desc_endpoint_t) - (USE_ISO_STREAMING ? sizeof(tusb_desc_interface_t) : 0) , // CS VS descriptors only
+            .bEndpointAddress = EPNUM_VIDEO_IN,
+            .bmInfo = 0,
+            .bTerminalLink = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+            .bStillCaptureMethod = 0,
+            .bTriggerSupport = 0,
+            .bTriggerUsage = 0,
+            .bControlSize = 1,
+            .bmaControls = { 0 }
+        },
+        .format = {
+#if USE_MJPEG
+            .bLength = sizeof(tusb_desc_video_format_mjpeg_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_MJPEG,
+            .bFormatIndex = 1, // 1-based index
+            .bNumFrameDescriptors = 1,
+            .bmFlags = 0,
+#else
+            .bLength = sizeof(tusb_desc_video_format_uncompressed_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED,
+            .bFormatIndex = 1, // 1-based index
+            .bNumFrameDescriptors = 1,
+            .guidFormat = { TUD_VIDEO_GUID_YUY2 },
+            .bBitsPerPixel = 16,
+#endif
+            .bDefaultFrameIndex = 1,
+            .bAspectRatioX = 0,
+            .bAspectRatioY = 0,
+            .bmInterlaceFlags = 0,
+            .bCopyProtect = 0
+        },
+        .frame = {
+#if USE_MJPEG
+            .bLength = sizeof(tusb_desc_video_frame_mjpeg_continuous_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_MJPEG,
+#else
+            .bLength = sizeof(tusb_desc_video_frame_uncompressed_continuous_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED,
+#endif
+            .bFrameIndex = 1, // 1-based index
+            .bmCapabilities = 0,
+            .wWidth = FRAME_WIDTH,
+            .wHeight = FRAME_HEIGHT,
+            .dwMinBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * 1,
+            .dwMaxBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * FRAME_RATE,
+            .dwMaxVideoFrameBufferSize = FRAME_WIDTH * FRAME_HEIGHT * 16 / 8,
+            .dwDefaultFrameInterval = 10000000 / FRAME_RATE,
+            .bFrameIntervalType = 0, // continuous
+            .dwFrameInterval = {
+                10000000 / FRAME_RATE, // min
+                10000000, // max
+                10000000 / FRAME_RATE // step
+            }
+        },
+        .color = {
+            .bLength = sizeof(tusb_desc_video_streaming_color_matching_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_COLORFORMAT,
+
+            .bColorPrimaries = VIDEO_COLOR_PRIMARIES_BT709,
+            .bTransferCharacteristics = VIDEO_COLOR_XFER_CH_BT709,
+            .bMatrixCoefficients = VIDEO_COLOR_COEF_SMPTE170M
+        },
+
+#if USE_ISO_STREAMING
+        .itf_alt = {
+            .bLength = sizeof(tusb_desc_interface_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE,
+
+            .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING,
+            .bAlternateSetting = 1,
+            .bNumEndpoints = 1,
+            .bInterfaceClass = TUSB_CLASS_VIDEO,
+            .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING,
+            .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+            .iInterface = STRID_UVC_STREAMING
+        },
+#endif
+
+        .ep = {
+            .bLength = sizeof(tusb_desc_endpoint_t),
+            .bDescriptorType = TUSB_DESC_ENDPOINT,
+
+            .bEndpointAddress = EPNUM_VIDEO_IN,
+            .bmAttributes = {
+                .xfer = CFG_TUD_VIDEO_STREAMING_BULK ? TUSB_XFER_BULK : TUSB_XFER_ISOCHRONOUS,
+                .sync = CFG_TUD_VIDEO_STREAMING_BULK ? 0 : 1 // asynchronous
+            },
+            .wMaxPacketSize = CFG_TUD_VIDEO_STREAMING_BULK ? 64 : CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE,
+            .bInterval = 1
+        }
+    }
 };
 
+#if TUD_OPT_HIGH_SPEED
+uvc_cfg_desc_t desc_hs_configuration;
+
+static uint8_t * get_hs_configuration_desc(void) {
+  static bool init = false;
+
+  if (!init) {
+    desc_hs_configuration = desc_fs_configuration;
+    // change endpoint bulk size to 512 if bulk streaming
+    if (CFG_TUD_VIDEO_STREAMING_BULK) {
+      desc_hs_configuration.video_streaming.ep.wMaxPacketSize = 512;
+    }
+  }
+  init = true;
+
+  return (uint8_t *) &desc_hs_configuration;
+}
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = USB_BCD,
+
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void) index; // for multiple configurations
+  // if link speed is high return fullspeed config, and vice versa
+  if (tud_speed_get() == TUSB_SPEED_HIGH) {
+    return (uint8_t const*) &desc_fs_configuration;
+  } else {
+    return get_hs_configuration_desc();
+  }
+}
+#endif // highspeed
+
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
 
-  return desc_fs_configuration;
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  if (tud_speed_get() == TUSB_SPEED_HIGH) {
+    return get_hs_configuration_desc();
+  } else
+#endif
+  {
+    return (uint8_t const*) &desc_fs_configuration;
+  }
 }
 
 //--------------------------------------------------------------------+
 // String Descriptors
 //--------------------------------------------------------------------+
 
-// array of pointer to string descriptors
-char const* string_desc_arr [] =
-{
-  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
-  "TinyUSB",                     // 1: Manufacturer
-  "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
-  "TinyUSB UVC",                 // 4: UVC Interface
-};
-
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch (index) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if (index >= sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char* str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if (chr_count > max_count) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for (size_t i = 0; i < chr_count; i++) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index f1ed3c8e9..12d41b2f3 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenbreg
@@ -27,21 +27,11 @@
 #ifndef _USB_DESCRIPTORS_H_
 #define _USB_DESCRIPTORS_H_
 
-/* Time stamp base clock. It is a deprecated parameter. */
-#define UVC_CLOCK_FREQUENCY    27000000
-/* video capture path */
-#define UVC_ENTITY_CAP_INPUT_TERMINAL  0x01
-#define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02
-
 #define FRAME_WIDTH   128
 #define FRAME_HEIGHT  96
 #define FRAME_RATE    10
 
-enum {
-  ITF_NUM_VIDEO_CONTROL,
-  ITF_NUM_VIDEO_STREAMING,
-  ITF_NUM_TOTAL
-};
+// NOTE: descriptor template is not used but leave here as reference
 
 #define TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN (\
     TUD_VIDEO_DESC_IAD_LEN\
@@ -79,6 +69,38 @@ enum {
     + 7/* Endpoint */\
   )
 
+#define TUD_VIDEO_CAPTURE_DESC_UNCOMPR_BULK_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+    + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+    + 7/* Endpoint */\
+  )
+
+#define TUD_VIDEO_CAPTURE_DESC_MJPEG_BULK_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+    + TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+    + 7/* Endpoint */\
+  )
+
 /* Windows support YUY2 and NV12
  * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
 
@@ -94,23 +116,17 @@ enum {
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
-  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                  \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
-        /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
@@ -120,7 +136,7 @@ enum {
         /* Video stream frame format */ \
         TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
             _width * _height * 16, _width * _height * 16 * _fps, \
-            _width * _height * 16, \
+            _width * _height * 16 / 8, \
             (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
         TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
   /* VS alt 1 */\
@@ -131,23 +147,17 @@ enum {
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
-  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
-        /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
@@ -165,4 +175,64 @@ enum {
     /* EP */ \
     TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
 
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */\
+        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16 / 8, \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+        TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                     \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, UVC_ENTITY_CAP_INPUT_TERMINAL, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_MJPEG(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bmFlags*/0, /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16 / 8, \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+        /* EP */ \
+        TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
+
+
 #endif
diff --git a/examples/device/video_capture_2ch/CMakeLists.txt b/examples/device/video_capture_2ch/CMakeLists.txt
new file mode 100644
index 000000000..90788fa60
--- /dev/null
+++ b/examples/device/video_capture_2ch/CMakeLists.txt
@@ -0,0 +1,39 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+if (FORCE_READONLY)
+target_compile_definitions(${PROJECT} PRIVATE
+  CFG_EXAMPLE_VIDEO_READONLY
+)
+endif()
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+)
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+)
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/video_capture_2ch/Makefile b/examples/device/video_capture_2ch/Makefile
new file mode 100644
index 000000000..d698a848d
--- /dev/null
+++ b/examples/device/video_capture_2ch/Makefile
@@ -0,0 +1,18 @@
+include ../../build_system/make/make.mk
+
+ifeq ($(DISABLE_MJPEG),1)
+CFLAGS += -DCFG_EXAMPLE_VIDEO_DISABLE_MJPEG
+endif
+ifeq ($(FORCE_READONLY),1)
+CFLAGS += -DCFG_EXAMPLE_VIDEO_READONLY
+endif
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/video_capture_2ch/skip.txt b/examples/device/video_capture_2ch/skip.txt
new file mode 100644
index 000000000..0f6508226
--- /dev/null
+++ b/examples/device/video_capture_2ch/skip.txt
@@ -0,0 +1,19 @@
+mcu:MSP430x5xx
+mcu:NUC121
+mcu:SAMD11
+mcu:GD32VF103
+mcu:CH32V103
+mcu:CH32V20X
+mcu:CH32V307
+mcu:STM32L0
+mcu:MCXA15
+family:espressif
+board:curiosity_nano
+board:kuiic
+board:frdm_k32l2b
+board:lpcxpresso11u68
+board:stm32f303disco
+board:stm32l412nucleo
+board:ek_tm4c123gxl
+board:uno_r4
+board:ra4m1_ek
diff --git a/examples/device/video_capture_2ch/src/CMakeLists.txt b/examples/device/video_capture_2ch/src/CMakeLists.txt
new file mode 100644
index 000000000..cef2b46ee
--- /dev/null
+++ b/examples/device/video_capture_2ch/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c" "usb_descriptors.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/video_capture_2ch/src/images.h b/examples/device/video_capture_2ch/src/images.h
new file mode 100644
index 000000000..f0badd074
--- /dev/null
+++ b/examples/device/video_capture_2ch/src/images.h
@@ -0,0 +1,1934 @@
+#if defined(CFG_EXAMPLE_VIDEO_READONLY)
+//--------------------------------------------------------------------+
+// YUY2 Uncompressed Frame (fixed)
+//--------------------------------------------------------------------+
+static const unsigned char framebuf_yuy2_readonly[128 * (96 + 1) * 2] = {
+  /* 0 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 1 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 2 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 3 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 4 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 5 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 6 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 7 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 8 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 9 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 10 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 11 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 12 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 13 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 14 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 15 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 16 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 17 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 18 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 19 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 20 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 21 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 22 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 23 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 24 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 25 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 26 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 27 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 28 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 29 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 30 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 31 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 32 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 33 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 34 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 35 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 36 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 37 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 38 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 39 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 40 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 41 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 42 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 43 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 44 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 45 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 46 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 47 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 48 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 49 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 50 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 51 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 52 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 53 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 54 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 55 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 56 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 57 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 58 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 59 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 60 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 61 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 62 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 63 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 64 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 65 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 66 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 67 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 68 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 69 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 70 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 71 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 72 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 73 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 74 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 75 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 76 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 77 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 78 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 79 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 80 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 81 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 82 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 83 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 84 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 85 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 86 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 87 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 88 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 89 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 90 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 91 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 92 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 93 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 94 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 95 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 96 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+};
+
+#endif
+
+//--------------------------------------------------------------------+
+// MPEG Compressed Frame (fixed)
+//--------------------------------------------------------------------+
+
+unsigned char color_bar_0_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x92, 0x8a, 0x00,
+  0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
+  0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
+  0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
+  0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
+  0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
+  0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
+  0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00,
+  0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
+  0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
+  0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
+  0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
+  0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
+  0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
+  0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00,
+  0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
+  0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
+  0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
+  0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
+  0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
+  0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
+  0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0xff, 0xd9
+};
+unsigned char color_bar_1_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x7d, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94,
+  0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51,
+  0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63,
+  0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45,
+  0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84,
+  0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94,
+  0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51,
+  0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63,
+  0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45,
+  0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84,
+  0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94,
+  0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51,
+  0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63,
+  0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45,
+  0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84,
+  0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x7f, 0xff, 0xd9
+};
+unsigned char color_bar_2_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x75, 0x14, 0xcc,
+  0xc4, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94,
+  0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18,
+  0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51,
+  0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61,
+  0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25,
+  0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c,
+  0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94,
+  0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18,
+  0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51,
+  0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61,
+  0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25,
+  0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c,
+  0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94,
+  0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18,
+  0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51,
+  0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61,
+  0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25,
+  0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x33, 0xff, 0xd9
+};
+unsigned char color_bar_3_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x5a, 0x2a, 0x08,
+  0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a,
+  0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c,
+  0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac,
+  0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4,
+  0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9,
+  0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12,
+  0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63,
+  0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a,
+  0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c,
+  0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac,
+  0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4,
+  0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9,
+  0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12,
+  0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63,
+  0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a,
+  0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c,
+  0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac,
+  0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4,
+  0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9,
+  0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12,
+  0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x91, 0xff, 0xd9
+};
+unsigned char color_bar_4_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x4a, 0x2a, 0xcb,
+  0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56,
+  0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62,
+  0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4,
+  0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09,
+  0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31,
+  0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5,
+  0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36,
+  0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56,
+  0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62,
+  0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4,
+  0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09,
+  0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31,
+  0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5,
+  0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36,
+  0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56,
+  0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62,
+  0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4,
+  0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09,
+  0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31,
+  0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5,
+  0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x9f, 0xff, 0xd9
+};
+unsigned char color_bar_5_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x6d, 0x14, 0x8d,
+  0x04, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15,
+  0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56,
+  0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65,
+  0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c,
+  0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28,
+  0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15,
+  0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56,
+  0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65,
+  0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c,
+  0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28,
+  0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15,
+  0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56,
+  0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65,
+  0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c,
+  0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28,
+  0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x7f, 0xff, 0xd9
+};
+unsigned char color_bar_6_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x65, 0x15, 0xa0,
+  0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15,
+  0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19,
+  0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b,
+  0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a,
+  0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45,
+  0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c,
+  0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15,
+  0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19,
+  0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b,
+  0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a,
+  0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45,
+  0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c,
+  0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15,
+  0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19,
+  0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b,
+  0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a,
+  0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45,
+  0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x33, 0xff, 0xd9
+};
+unsigned char color_bar_7_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x8e, 0x8a, 0x00,
+  0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad,
+  0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25,
+  0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3,
+  0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2,
+  0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6,
+  0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a,
+  0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c,
+  0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad,
+  0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25,
+  0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3,
+  0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2,
+  0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6,
+  0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a,
+  0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c,
+  0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad,
+  0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25,
+  0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3,
+  0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2,
+  0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6,
+  0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a,
+  0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x47, 0xff, 0xd9
+};
diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c
new file mode 100644
index 000000000..245e7abb8
--- /dev/null
+++ b/examples/device/video_capture_2ch/src/main.c
@@ -0,0 +1,367 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+void led_blinking_task(void* param);
+void usb_device_task(void *param);
+void video_task(void* param);
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+void freertos_init_task(void);
+#endif
+
+
+//--------------------------------------------------------------------+
+// Main
+//--------------------------------------------------------------------+
+int main(void) {
+  board_init();
+
+  // If using FreeRTOS: create blinky, tinyusb device, video task
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  freertos_init_task();
+#else
+  // init device stack on configured roothub port
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  while (1) {
+    tud_task(); // tinyusb device task
+    led_blinking_task(NULL);
+    video_task(NULL);
+  }
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void) {
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void) {
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en) {
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// USB Video
+//--------------------------------------------------------------------+
+#define FRAMEBUF_SIZE (FRAME_WIDTH * FRAME_HEIGHT * 16 / 8)
+
+static unsigned frame_num[CFG_TUD_VIDEO_STREAMING] = {1};
+static unsigned tx_busy = 0;
+static unsigned interval_ms[CFG_TUD_VIDEO_STREAMING] = {1000 / FRAME_RATE};
+
+// For mcus that does not have enough SRAM for frame buffer, we use fixed frame data.
+// To further reduce the size, we use MJPEG format instead of YUY2.
+#include "images.h"
+
+static struct {
+  uint32_t       size;
+  uint8_t const *buffer;
+} const framebuf_mjpeg[] = {
+    {sizeof(color_bar_0_jpg), color_bar_0_jpg},
+    {sizeof(color_bar_1_jpg), color_bar_1_jpg},
+    {sizeof(color_bar_2_jpg), color_bar_2_jpg},
+    {sizeof(color_bar_3_jpg), color_bar_3_jpg},
+    {sizeof(color_bar_4_jpg), color_bar_4_jpg},
+    {sizeof(color_bar_5_jpg), color_bar_5_jpg},
+    {sizeof(color_bar_6_jpg), color_bar_6_jpg},
+    {sizeof(color_bar_7_jpg), color_bar_7_jpg},
+};
+
+#if !defined(CFG_EXAMPLE_VIDEO_READONLY)
+// YUY2 frame buffer
+static uint8_t framebuf_yuy2[FRAMEBUF_SIZE];
+
+static void fill_color_bar(uint8_t* buffer, unsigned start_position) {
+  /* EBU color bars: https://stackoverflow.com/questions/6939422 */
+  static uint8_t const bar_color[8][4] = {
+      /*  Y,   U,   Y,   V */
+      { 235, 128, 235, 128}, /* 100% White */
+      { 219,  16, 219, 138}, /* Yellow */
+      { 188, 154, 188,  16}, /* Cyan */
+      { 173,  42, 173,  26}, /* Green */
+      {  78, 214,  78, 230}, /* Magenta */
+      {  63, 102,  63, 240}, /* Red */
+      {  32, 240,  32, 118}, /* Blue */
+      {  16, 128,  16, 128}, /* Black */
+  };
+  uint8_t* p;
+
+  /* Generate the 1st line */
+  uint8_t* end = &buffer[FRAME_WIDTH * 2];
+  unsigned idx = (FRAME_WIDTH / 2 - 1) - (start_position % (FRAME_WIDTH / 2));
+  p = &buffer[idx * 4];
+  for (unsigned i = 0; i < 8; ++i) {
+    for (int j = 0; j < FRAME_WIDTH / (2 * 8); ++j) {
+      memcpy(p, &bar_color[i], 4);
+      p += 4;
+      if (end <= p) {
+        p = buffer;
+      }
+    }
+  }
+
+  /* Duplicate the 1st line to the others */
+  p = &buffer[FRAME_WIDTH * 2];
+  for (unsigned i = 1; i < FRAME_HEIGHT; ++i) {
+    memcpy(p, buffer, FRAME_WIDTH * 2);
+    p += FRAME_WIDTH * 2;
+  }
+}
+#endif
+
+size_t get_framebuf(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, size_t fnum, void **fb) {
+  uint32_t idx = ctl_idx + stm_idx;
+
+  if (idx == 0) {
+    // stream 0 use uncompressed YUY2 frame
+    #if defined(CFG_EXAMPLE_VIDEO_READONLY)
+    *fb = (void*)(uintptr_t ) &framebuf_yuy2_readonly[(fnum % (FRAME_WIDTH / 2)) * 4];
+    #else
+    fill_color_bar(framebuf_yuy2, frame_num[idx]);
+    *fb = framebuf_yuy2;
+    #endif
+
+    return FRAMEBUF_SIZE;
+  }else {
+    // stream 1 use MJPEG frame
+    size_t const bar_id = fnum & 0x7;
+
+    *fb = (void*)(uintptr_t) framebuf_mjpeg[bar_id].buffer;
+    return framebuf_mjpeg[bar_id].size;
+  }
+}
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+void video_send_frame(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) {
+  static unsigned start_ms[CFG_TUD_VIDEO_STREAMING] = {0, };
+  static unsigned already_sent = 0;
+
+  uint32_t idx = ctl_idx + stm_idx;
+  if (!tud_video_n_streaming(ctl_idx, stm_idx)) {
+    already_sent &= ~(1u << idx);
+    frame_num[idx] = 0;
+    return;
+  }
+  void* fp;
+  size_t fb_size;
+
+  if (!(already_sent & (1u << idx))) {
+    already_sent |= 1u << idx;
+    tx_busy |= 1u << idx;
+    start_ms[idx] = board_millis();
+
+    fb_size = get_framebuf(ctl_idx, stm_idx, frame_num[idx], &fp);
+    tud_video_n_frame_xfer(ctl_idx, stm_idx, fp, fb_size);
+  }
+
+  unsigned cur = board_millis();
+  if (cur - start_ms[idx] < interval_ms[idx]) return; // not enough time
+  if (tx_busy & (1u << idx)) return;
+  start_ms[idx] += interval_ms[idx];
+  tx_busy |= 1u << idx;
+
+  fb_size = get_framebuf(ctl_idx, stm_idx, frame_num[idx], &fp);
+  tud_video_n_frame_xfer(ctl_idx, stm_idx, fp, fb_size);
+}
+
+
+void video_task(void* param) {
+  (void) param;
+
+  while(1) {
+    video_send_frame(0, 0);
+    video_send_frame(1, 0);
+
+    #if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(interval_ms[0] / portTICK_PERIOD_MS);
+    #else
+    return;
+    #endif
+  }
+}
+
+void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) {
+  uint32_t idx = ctl_idx + stm_idx;
+  tx_busy &= ~(1u << idx);
+  /* flip buffer */
+  ++frame_num[idx];
+}
+
+int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
+                        video_probe_and_commit_control_t const* parameters) {
+  uint32_t idx = ctl_idx + stm_idx;
+  /* convert unit to ms from 100 ns */
+  interval_ms[idx] = parameters->dwFrameInterval / 10000;
+  return VIDEO_ERROR_NONE;
+}
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void* param) {
+  (void) param;
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  while (1) {
+    #if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    #else
+    if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+    #endif
+
+    start_ms += blink_interval_ms;
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
+}
+
+//--------------------------------------------------------------------+
+// FreeRTOS
+//--------------------------------------------------------------------+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+#define VIDEO_STACK_SIZE    (configMINIMAL_STACK_SIZE*4)
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+  #define USBD_STACK_SIZE     4096
+  int main(void);
+  void app_main(void) {
+    main();
+  }
+#else
+  // Increase stack size when debug log is enabled
+  #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t  usb_device_stack[USBD_STACK_SIZE];
+StaticTask_t usb_device_taskdef;
+
+StackType_t  video_stack[VIDEO_STACK_SIZE];
+StaticTask_t video_taskdef;
+#endif
+
+// USB Device Driver task
+// This top level thread process all usb events and invoke callbacks
+void usb_device_task(void *param) {
+  (void) param;
+
+  // init device stack on configured roothub port
+  // This should be called after scheduler/kernel is started.
+  // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  // RTOS forever loop
+  while (1) {
+    // put this thread to waiting state until there is new events
+    tud_task();
+  }
+}
+
+void freertos_init_task(void) {
+  #if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+  xTaskCreateStatic(video_task, "cdc", VIDEO_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, video_stack, &video_taskdef);
+  #else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(video_task, "video", VIDEO_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
+  #endif
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+  #if !TUSB_MCU_VENDOR_ESPRESSIF
+  vTaskStartScheduler();
+  #endif
+}
+#endif
diff --git a/examples/device/video_capture_2ch/src/tusb_config.h b/examples/device/video_capture_2ch/src/tusb_config.h
new file mode 100644
index 000000000..91775a327
--- /dev/null
+++ b/examples/device/video_capture_2ch/src/tusb_config.h
@@ -0,0 +1,120 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TUSB_MCU_VENDOR_ESPRESSIF
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+// The number of video control interfaces
+#define CFG_TUD_VIDEO            2
+
+// The number of video streaming interfaces
+#define CFG_TUD_VIDEO_STREAMING  2
+
+// video streaming endpoint buffer size
+#define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE  256
+
+// use bulk endpoint for streaming interface
+#define CFG_TUD_VIDEO_STREAMING_BULK 1
+
+//#define CFG_EXAMPLE_VIDEO_READONLY
+//#define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG
+
+#define CFG_TUD_VIDEO_LOG_LEVEL 1
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/video_capture_2ch/src/usb_descriptors.c b/examples/device/video_capture_2ch/src/usb_descriptors.c
new file mode 100644
index 000000000..e78e452fc
--- /dev/null
+++ b/examples/device/video_capture_2ch/src/usb_descriptors.c
@@ -0,0 +1,653 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]  VIDEO | AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+    _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VIDEO, 5) | _PID_MAP(VENDOR, 6) )
+
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+  STRID_UVC_CONTROL_1,
+  STRID_UVC_STREAMING_1,
+  STRID_UVC_CONTROL_2,
+  STRID_UVC_STREAMING_2,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr[] = {
+    (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                   // 1: Manufacturer
+    "TinyUSB Device",            // 2: Product
+    NULL,                        // 3: Serials will use unique ID if possible
+    "UVC Control 1",             // 4: UVC Interface 1
+    "UVC Streaming 1",           // 5: UVC Interface 1
+    "UVC Control 2",             // 6: UVC Interface 2
+    "UVC Streaming 2",           // 7: UVC Interface 2
+
+};
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device = {
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = USB_BCD,
+
+    // Use Interface Association Descriptor (IAD) for Video
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = USB_VID,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = STRID_MANUFACTURER,
+    .iProduct           = STRID_PRODUCT,
+    .iSerialNumber      = STRID_SERIAL,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const* tud_descriptor_device_cb(void) {
+  return (uint8_t const*) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+/* Time stamp base clock. It is a deprecated parameter. */
+#define UVC_CLOCK_FREQUENCY    27000000
+
+/* video capture path */
+#define UVC_ENTITY_CAP_INPUT_TERMINAL  0x01
+#define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02
+
+enum {
+  ITF_NUM_VIDEO_CONTROL_1,
+  ITF_NUM_VIDEO_STREAMING_1,
+  ITF_NUM_VIDEO_CONTROL_2,
+  ITF_NUM_VIDEO_STREAMING_2,
+  ITF_NUM_TOTAL
+};
+
+#define EPNUM_VIDEO_IN_1    0x81
+#define EPNUM_VIDEO_IN_2    0x82
+
+#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+  #define USE_MJPEG 1
+#else
+  #define USE_MJPEG 0
+#endif
+
+#define USE_ISO_STREAMING (!CFG_TUD_VIDEO_STREAMING_BULK)
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_interface_t itf;
+  tusb_desc_video_control_header_1itf_t header;
+  tusb_desc_video_control_camera_terminal_t camera_terminal;
+  tusb_desc_video_control_output_terminal_t output_terminal;
+} uvc_control_desc_t;
+
+/* Windows support YUY2 and NV12
+ * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_interface_t itf;
+  tusb_desc_video_streaming_input_header_1byte_t header;
+  tusb_desc_video_format_uncompressed_t format;
+  tusb_desc_video_frame_uncompressed_continuous_t frame;
+  tusb_desc_video_streaming_color_matching_t color;
+
+#if USE_ISO_STREAMING
+  // For ISO streaming, USB spec requires to alternate interface
+  tusb_desc_interface_t itf_alt;
+#endif
+
+  tusb_desc_endpoint_t ep;
+} uvc_streaming_yuy2_desc_t;
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_interface_t itf;
+  tusb_desc_video_streaming_input_header_1byte_t header;
+  tusb_desc_video_format_mjpeg_t format;
+  tusb_desc_video_frame_mjpeg_continuous_t frame;
+  tusb_desc_video_streaming_color_matching_t color;
+
+#if USE_ISO_STREAMING
+  // For ISO streaming, USB spec requires to alternate interface
+  tusb_desc_interface_t itf_alt;
+#endif
+
+  tusb_desc_endpoint_t ep;
+} uvc_streaming_mpeg_desc_t;
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_configuration_t config;
+
+  struct TU_ATTR_PACKED {
+    tusb_desc_interface_assoc_t iad;
+    uvc_control_desc_t video_control;
+    uvc_streaming_yuy2_desc_t video_streaming;
+  } uvc_yuy2;
+
+  struct TU_ATTR_PACKED {
+    tusb_desc_interface_assoc_t iad;
+    uvc_control_desc_t video_control;
+    uvc_streaming_mpeg_desc_t video_streaming;
+  } uvc_mpeg;
+} uvc_cfg_desc_t;
+
+const uvc_cfg_desc_t desc_fs_configuration = {
+    .config = {
+        .bLength = sizeof(tusb_desc_configuration_t),
+        .bDescriptorType = TUSB_DESC_CONFIGURATION,
+
+        .wTotalLength = sizeof(uvc_cfg_desc_t),
+        .bNumInterfaces = ITF_NUM_TOTAL,
+        .bConfigurationValue = 1,
+        .iConfiguration = 0,
+        .bmAttributes =  TU_BIT(7),
+        .bMaxPower = 100 / 2
+    },
+    //------------- Stream 0: YUY2 -------------//
+    .uvc_yuy2 = {
+        .iad = {
+            .bLength = sizeof(tusb_desc_interface_assoc_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE_ASSOCIATION,
+
+            .bFirstInterface = ITF_NUM_VIDEO_CONTROL_1,
+            .bInterfaceCount = 2,
+            .bFunctionClass = TUSB_CLASS_VIDEO,
+            .bFunctionSubClass = VIDEO_SUBCLASS_INTERFACE_COLLECTION,
+            .bFunctionProtocol = VIDEO_ITF_PROTOCOL_UNDEFINED,
+            .iFunction = 0
+        },
+        .video_control = {
+            .itf = {
+                .bLength = sizeof(tusb_desc_interface_t),
+                .bDescriptorType = TUSB_DESC_INTERFACE,
+
+                .bInterfaceNumber = ITF_NUM_VIDEO_CONTROL_1,
+                .bAlternateSetting = 0,
+                .bNumEndpoints = 0,
+                .bInterfaceClass = TUSB_CLASS_VIDEO,
+                .bInterfaceSubClass = VIDEO_SUBCLASS_CONTROL,
+                .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+                .iInterface = STRID_UVC_CONTROL_1
+            },
+            .header = {
+                .bLength = sizeof(tusb_desc_video_control_header_1itf_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VC_HEADER,
+
+                .bcdUVC = VIDEO_BCD_1_50,
+                .wTotalLength = sizeof(uvc_control_desc_t) - sizeof(tusb_desc_interface_t), // CS VC descriptors only
+                .dwClockFrequency = UVC_CLOCK_FREQUENCY,
+                .bInCollection = 1,
+                .baInterfaceNr = {ITF_NUM_VIDEO_STREAMING_1}
+            },
+            .camera_terminal = {
+                .bLength = sizeof(tusb_desc_video_control_camera_terminal_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VC_INPUT_TERMINAL,
+
+                .bTerminalID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+                .wTerminalType = VIDEO_ITT_CAMERA,
+                .bAssocTerminal = 0,
+                .iTerminal = 0,
+                .wObjectiveFocalLengthMin = 0,
+                .wObjectiveFocalLengthMax = 0,
+                .wOcularFocalLength = 0,
+                .bControlSize = 3,
+                .bmControls = {0, 0, 0}
+            },
+            .output_terminal = {
+                .bLength = sizeof(tusb_desc_video_control_output_terminal_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VC_OUTPUT_TERMINAL,
+
+                .bTerminalID = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+                .wTerminalType = VIDEO_TT_STREAMING,
+                .bAssocTerminal = 0,
+                .bSourceID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+                .iTerminal = 0
+            }
+        },
+
+        .video_streaming = {
+            .itf = {
+                .bLength = sizeof(tusb_desc_interface_t),
+                .bDescriptorType = TUSB_DESC_INTERFACE,
+
+                .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING_1,
+                .bAlternateSetting = 0,
+                .bNumEndpoints = CFG_TUD_VIDEO_STREAMING_BULK, // bulk 1, iso 0
+                .bInterfaceClass = TUSB_CLASS_VIDEO,
+                .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING,
+                .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+                .iInterface = STRID_UVC_STREAMING_1
+            },
+            .header = {
+                .bLength = sizeof(tusb_desc_video_streaming_input_header_1byte_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VS_INPUT_HEADER,
+
+                .bNumFormats = 1,
+                .wTotalLength = sizeof(uvc_streaming_yuy2_desc_t) - sizeof(tusb_desc_interface_t)
+                                - sizeof(tusb_desc_endpoint_t) -
+                                (USE_ISO_STREAMING ? sizeof(tusb_desc_interface_t) : 0), // CS VS descriptors only
+                .bEndpointAddress = EPNUM_VIDEO_IN_1,
+                .bmInfo = 0,
+                .bTerminalLink = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+                .bStillCaptureMethod = 0,
+                .bTriggerSupport = 0,
+                .bTriggerUsage = 0,
+                .bControlSize = 1,
+                .bmaControls = {0}
+            },
+            .format = {
+                .bLength = sizeof(tusb_desc_video_format_uncompressed_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED,
+                .bFormatIndex = 1, // 1-based index
+                .bNumFrameDescriptors = 1,
+                .guidFormat = {TUD_VIDEO_GUID_YUY2},
+                .bBitsPerPixel = 16,
+                .bDefaultFrameIndex = 1,
+                .bAspectRatioX = 0,
+                .bAspectRatioY = 0,
+                .bmInterlaceFlags = 0,
+                .bCopyProtect = 0
+            },
+            .frame = {
+                .bLength = sizeof(tusb_desc_video_frame_uncompressed_continuous_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED,
+                .bFrameIndex = 1, // 1-based index
+                .bmCapabilities = 0,
+                .wWidth = FRAME_WIDTH,
+                .wHeight = FRAME_HEIGHT,
+                .dwMinBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * 1,
+                .dwMaxBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * FRAME_RATE,
+                .dwMaxVideoFrameBufferSize = FRAME_WIDTH * FRAME_HEIGHT * 16 / 8,
+                .dwDefaultFrameInterval = 10000000 / FRAME_RATE,
+                .bFrameIntervalType = 0, // continuous
+                .dwFrameInterval = {
+                    10000000 / FRAME_RATE, // min
+                    10000000, // max
+                    10000000 / FRAME_RATE // step
+                }
+            },
+            .color = {
+                .bLength = sizeof(tusb_desc_video_streaming_color_matching_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VS_COLORFORMAT,
+
+                .bColorPrimaries = VIDEO_COLOR_PRIMARIES_BT709,
+                .bTransferCharacteristics = VIDEO_COLOR_XFER_CH_BT709,
+                .bMatrixCoefficients = VIDEO_COLOR_COEF_SMPTE170M
+            },
+
+#if USE_ISO_STREAMING
+            .itf_alt = {
+                .bLength = sizeof(tusb_desc_interface_t),
+                .bDescriptorType = TUSB_DESC_INTERFACE,
+
+                .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING_1,
+                .bAlternateSetting = 1,
+                .bNumEndpoints = 1,
+                .bInterfaceClass = TUSB_CLASS_VIDEO,
+                .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING,
+                .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+                .iInterface = STRID_UVC_STREAMING_1
+            },
+#endif
+            .ep = {
+                .bLength = sizeof(tusb_desc_endpoint_t),
+                .bDescriptorType = TUSB_DESC_ENDPOINT,
+
+                .bEndpointAddress = EPNUM_VIDEO_IN_1,
+                .bmAttributes = {
+                    .xfer = CFG_TUD_VIDEO_STREAMING_BULK ? TUSB_XFER_BULK : TUSB_XFER_ISOCHRONOUS,
+                    .sync = CFG_TUD_VIDEO_STREAMING_BULK ? 0 : 1 // asynchronous
+                },
+                .wMaxPacketSize = CFG_TUD_VIDEO_STREAMING_BULK ? 64 : CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE,
+                .bInterval = 1
+            }
+        }
+    },
+      //------------- Stream 1: MPEG -------------//
+    .uvc_mpeg = {
+        .iad = {
+            .bLength = sizeof(tusb_desc_interface_assoc_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE_ASSOCIATION,
+
+            .bFirstInterface = ITF_NUM_VIDEO_CONTROL_2,
+            .bInterfaceCount = 2,
+            .bFunctionClass = TUSB_CLASS_VIDEO,
+            .bFunctionSubClass = VIDEO_SUBCLASS_INTERFACE_COLLECTION,
+            .bFunctionProtocol = VIDEO_ITF_PROTOCOL_UNDEFINED,
+            .iFunction = 0
+        },
+
+        .video_control = {
+            .itf = {
+                .bLength = sizeof(tusb_desc_interface_t),
+                .bDescriptorType = TUSB_DESC_INTERFACE,
+
+                .bInterfaceNumber = ITF_NUM_VIDEO_CONTROL_2,
+                .bAlternateSetting = 0,
+                .bNumEndpoints = 0,
+                .bInterfaceClass = TUSB_CLASS_VIDEO,
+                .bInterfaceSubClass = VIDEO_SUBCLASS_CONTROL,
+                .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+                .iInterface = STRID_UVC_CONTROL_2
+            },
+            .header = {
+                .bLength = sizeof(tusb_desc_video_control_header_1itf_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VC_HEADER,
+
+                .bcdUVC = VIDEO_BCD_1_50,
+                .wTotalLength = sizeof(uvc_control_desc_t) - sizeof(tusb_desc_interface_t), // CS VC descriptors only
+                .dwClockFrequency = UVC_CLOCK_FREQUENCY,
+                .bInCollection = 1,
+                .baInterfaceNr = { ITF_NUM_VIDEO_STREAMING_2 }
+            },
+            .camera_terminal = {
+                .bLength = sizeof(tusb_desc_video_control_camera_terminal_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VC_INPUT_TERMINAL,
+
+                .bTerminalID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+                .wTerminalType = VIDEO_ITT_CAMERA,
+                .bAssocTerminal = 0,
+                .iTerminal = 0,
+                .wObjectiveFocalLengthMin = 0,
+                .wObjectiveFocalLengthMax = 0,
+                .wOcularFocalLength = 0,
+                .bControlSize = 3,
+                .bmControls = { 0, 0, 0 }
+            },
+            .output_terminal = {
+                .bLength = sizeof(tusb_desc_video_control_output_terminal_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VC_OUTPUT_TERMINAL,
+
+                .bTerminalID = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+                .wTerminalType = VIDEO_TT_STREAMING,
+                .bAssocTerminal = 0,
+                .bSourceID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+                .iTerminal = 0
+            }
+        },
+
+        .video_streaming = {
+            .itf = {
+                .bLength = sizeof(tusb_desc_interface_t),
+                .bDescriptorType = TUSB_DESC_INTERFACE,
+
+                .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING_2,
+                .bAlternateSetting = 0,
+                .bNumEndpoints = CFG_TUD_VIDEO_STREAMING_BULK, // bulk 1, iso 0
+                .bInterfaceClass = TUSB_CLASS_VIDEO,
+                .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING,
+                .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+                .iInterface = STRID_UVC_STREAMING_2
+            },
+            .header = {
+                .bLength = sizeof(tusb_desc_video_streaming_input_header_1byte_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VS_INPUT_HEADER,
+
+                .bNumFormats = 1,
+                .wTotalLength = sizeof(uvc_streaming_mpeg_desc_t) - sizeof(tusb_desc_interface_t)
+                                - sizeof(tusb_desc_endpoint_t) - (USE_ISO_STREAMING ? sizeof(tusb_desc_interface_t) : 0) , // CS VS descriptors only
+                .bEndpointAddress = EPNUM_VIDEO_IN_2,
+                .bmInfo = 0,
+                .bTerminalLink = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+                .bStillCaptureMethod = 0,
+                .bTriggerSupport = 0,
+                .bTriggerUsage = 0,
+                .bControlSize = 1,
+                .bmaControls = { 0 }
+            },
+            .format = {
+                .bLength = sizeof(tusb_desc_video_format_mjpeg_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_MJPEG,
+                .bFormatIndex = 1, // 1-based index
+                .bNumFrameDescriptors = 1,
+                .bmFlags = 0,
+                .bDefaultFrameIndex = 1,
+                .bAspectRatioX = 0,
+                .bAspectRatioY = 0,
+                .bmInterlaceFlags = 0,
+                .bCopyProtect = 0
+            },
+            .frame = {
+                .bLength = sizeof(tusb_desc_video_frame_mjpeg_continuous_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_MJPEG,
+                .bFrameIndex = 1, // 1-based index
+                .bmCapabilities = 0,
+                .wWidth = FRAME_WIDTH,
+                .wHeight = FRAME_HEIGHT,
+                .dwMinBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * 1,
+                .dwMaxBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * FRAME_RATE,
+                .dwMaxVideoFrameBufferSize = FRAME_WIDTH * FRAME_HEIGHT * 16 / 8,
+                .dwDefaultFrameInterval = 10000000 / FRAME_RATE,
+                .bFrameIntervalType = 0, // continuous
+                .dwFrameInterval = {
+                    10000000 / FRAME_RATE, // min
+                    10000000, // max
+                    10000000 / FRAME_RATE // step
+                }
+            },
+            .color = {
+                .bLength = sizeof(tusb_desc_video_streaming_color_matching_t),
+                .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+                .bDescriptorSubType = VIDEO_CS_ITF_VS_COLORFORMAT,
+
+                .bColorPrimaries = VIDEO_COLOR_PRIMARIES_BT709,
+                .bTransferCharacteristics = VIDEO_COLOR_XFER_CH_BT709,
+                .bMatrixCoefficients = VIDEO_COLOR_COEF_SMPTE170M
+            },
+
+#if USE_ISO_STREAMING
+            .itf_alt = {
+                .bLength = sizeof(tusb_desc_interface_t),
+                .bDescriptorType = TUSB_DESC_INTERFACE,
+
+                .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING_2,
+                .bAlternateSetting = 1,
+                .bNumEndpoints = 1,
+                .bInterfaceClass = TUSB_CLASS_VIDEO,
+                .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING,
+                .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+                .iInterface = STRID_UVC_STREAMING_2
+            },
+#endif
+            .ep = {
+                .bLength = sizeof(tusb_desc_endpoint_t),
+                .bDescriptorType = TUSB_DESC_ENDPOINT,
+
+                .bEndpointAddress = EPNUM_VIDEO_IN_2,
+                .bmAttributes = {
+                    .xfer = CFG_TUD_VIDEO_STREAMING_BULK ? TUSB_XFER_BULK : TUSB_XFER_ISOCHRONOUS,
+                    .sync = CFG_TUD_VIDEO_STREAMING_BULK ? 0 : 1 // asynchronous
+                },
+                .wMaxPacketSize = CFG_TUD_VIDEO_STREAMING_BULK ? 64 : CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE,
+                .bInterval = 1
+            }
+        }
+    }
+};
+
+#if TUD_OPT_HIGH_SPEED
+uvc_cfg_desc_t desc_hs_configuration;
+
+static uint8_t * get_hs_configuration_desc(void) {
+  static bool init = false;
+
+  if (!init) {
+    desc_hs_configuration = desc_fs_configuration;
+    // change endpoint bulk size to 512 if bulk streaming
+    if (CFG_TUD_VIDEO_STREAMING_BULK) {
+      desc_hs_configuration.uvc_yuy2.video_streaming.ep.wMaxPacketSize = 512;
+      desc_hs_configuration.uvc_mpeg.video_streaming.ep.wMaxPacketSize = 512;
+    }
+  }
+  init = true;
+
+  return (uint8_t *) &desc_hs_configuration;
+}
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = USB_BCD,
+
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void) index; // for multiple configurations
+  // if link speed is high return fullspeed config, and vice versa
+  if (tud_speed_get() == TUSB_SPEED_HIGH) {
+    return (uint8_t const*) &desc_fs_configuration;
+  } else {
+    return get_hs_configuration_desc();
+  }
+}
+#endif // highspeed
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
+  (void) index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  if (tud_speed_get() == TUSB_SPEED_HIGH) {
+    return get_hs_configuration_desc();
+  } else
+#endif
+  {
+    return (uint8_t const*) &desc_fs_configuration;
+  }
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+  switch (index) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+      if (index >= sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) return NULL;
+
+      const char* str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if (chr_count > max_count) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for (size_t i = 0; i < chr_count; i++) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/device/video_capture_2ch/src/usb_descriptors.h b/examples/device/video_capture_2ch/src/usb_descriptors.h
new file mode 100644
index 000000000..12d41b2f3
--- /dev/null
+++ b/examples/device/video_capture_2ch/src/usb_descriptors.h
@@ -0,0 +1,238 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenbreg
+ * Copyright (c) 2021 Koji KITAYAMA
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+#define FRAME_WIDTH   128
+#define FRAME_HEIGHT  96
+#define FRAME_RATE    10
+
+// NOTE: descriptor template is not used but leave here as reference
+
+#define TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+    + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+    /* Interface 1, Alternate 1 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + 7/* Endpoint */\
+  )
+
+#define TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+    + TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+    /* Interface 1, Alternate 1 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + 7/* Endpoint */\
+  )
+
+#define TUD_VIDEO_CAPTURE_DESC_UNCOMPR_BULK_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+    + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+    + 7/* Endpoint */\
+  )
+
+#define TUD_VIDEO_CAPTURE_DESC_MJPEG_BULK_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+    + TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+    + 7/* Endpoint */\
+  )
+
+/* Windows support YUY2 and NV12
+ * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
+
+#define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_YUY2, 16, _frmidx, _asrx, _asry, _interlace, _cp)
+#define TUD_VIDEO_DESC_CS_VS_FMT_NV12(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_NV12, 12, _frmidx, _asrx, _asry, _interlace, _cp)
+#define TUD_VIDEO_DESC_CS_VS_FMT_M420(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_M420, 12, _frmidx, _asrx, _asry, _interlace, _cp)
+#define TUD_VIDEO_DESC_CS_VS_FMT_I420(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_I420, 12, _frmidx, _asrx, _asry, _interlace, _cp)
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(_stridx, _epin, _width, _height, _fps, _epsize) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                  \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16 / 8, \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+  /* VS alt 1 */\
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 1, 1, _stridx), \
+    /* EP */ \
+    TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(_stridx, _epin, _width, _height, _fps, _epsize) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_MJPEG(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bmFlags*/0, /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16 / 8, \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+  /* VS alt 1 */\
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 1, 1, _stridx), \
+    /* EP */ \
+    TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
+
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */\
+        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16 / 8, \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+        TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                     \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, UVC_ENTITY_CAP_INPUT_TERMINAL, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_MJPEG(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bmFlags*/0, /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16 / 8, \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+        /* EP */ \
+        TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
+
+
+#endif
diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt
index abc4d91da..ced98a909 100644
--- a/examples/device/webusb_serial/CMakeLists.txt
+++ b/examples/device/webusb_serial/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
@@ -23,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/webusb_serial/Makefile b/examples/device/webusb_serial/Makefile
index 5a455078e..7fa475da5 100644
--- a/examples/device/webusb_serial/Makefile
+++ b/examples/device/webusb_serial/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
   src \
@@ -9,4 +8,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index 604d30a83..d189af91f 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -47,7 +47,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -73,8 +73,7 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
 #define URL  "example.tinyusb.org/webusb-serial/index.html"
 
-const tusb_desc_webusb_url_t desc_url =
-{
+const tusb_desc_webusb_url_t desc_url = {
   .bLength         = 3 + sizeof(URL) - 1,
   .bDescriptorType = 3, // WEBUSB URL type
   .bScheme         = 1, // 0: http, 1: https
@@ -86,45 +85,44 @@ static bool web_serial_connected = false;
 //------------- prototypes -------------//
 void led_blinking_task(void);
 void cdc_task(void);
-void webserial_task(void);
 
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   // init device stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
 
-  while (1)
-  {
-    tud_task(); // tinyusb device task
-    cdc_task();
-    webserial_task();
-    led_blinking_task();
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
   }
 
-  return 0;
+  while (1) {
+    tud_task(); // tinyusb device task
+    cdc_task();
+    led_blinking_task();
+  }
 }
 
 // send characters to both CDC and WebUSB
-void echo_all(uint8_t buf[], uint32_t count)
-{
+void echo_all(const uint8_t buf[], uint32_t count) {
   // echo to web serial
-  if ( web_serial_connected )
-  {
+  if (web_serial_connected) {
     tud_vendor_write(buf, count);
-    tud_vendor_flush();
+    tud_vendor_write_flush();
   }
 
   // echo to cdc
-  if ( tud_cdc_connected() )
-  {
-    for(uint32_t i=0; i<count; i++)
-    {
+  if (tud_cdc_connected()) {
+    for (uint32_t i = 0; i < count; i++) {
       tud_cdc_write_char(buf[i]);
-
-      if ( buf[i] == '\r' ) tud_cdc_write_char('\n');
+      if (buf[i] == '\r') {
+        tud_cdc_write_char('\n');
+      }
     }
     tud_cdc_write_flush();
   }
@@ -135,30 +133,26 @@ void echo_all(uint8_t buf[], uint32_t count)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
-  (void) remote_wakeup_en;
+void tud_suspend_cb(bool remote_wakeup_en) {
+  (void)remote_wakeup_en;
   blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
-  blink_interval_ms = BLINK_MOUNTED;
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
@@ -168,61 +162,53 @@ void tud_resume_cb(void)
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
+bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) {
   // nothing to with DATA & ACK stage
   if (stage != CONTROL_STAGE_SETUP) return true;
 
-  switch (request->bmRequestType_bit.type)
-  {
+  switch (request->bmRequestType_bit.type) {
     case TUSB_REQ_TYPE_VENDOR:
-      switch (request->bRequest)
-      {
+      switch (request->bRequest) {
         case VENDOR_REQUEST_WEBUSB:
           // match vendor request in BOS descriptor
           // Get landing page url
-          return tud_control_xfer(rhport, request, (void*)(uintptr_t) &desc_url, desc_url.bLength);
+          return tud_control_xfer(rhport, request, (void*)(uintptr_t)&desc_url, desc_url.bLength);
 
         case VENDOR_REQUEST_MICROSOFT:
-          if ( request->wIndex == 7 )
-          {
+          if (request->wIndex == 7) {
             // Get Microsoft OS 2.0 compatible descriptor
             uint16_t total_len;
-            memcpy(&total_len, desc_ms_os_20+8, 2);
+            memcpy(&total_len, desc_ms_os_20 + 8, 2);
 
-            return tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_ms_os_20, total_len);
-          }else
-          {
+            return tud_control_xfer(rhport, request, (void*)(uintptr_t)desc_ms_os_20, total_len);
+          } else {
             return false;
           }
 
         default: break;
       }
-    break;
+      break;
 
     case TUSB_REQ_TYPE_CLASS:
-      if (request->bRequest == 0x22)
-      {
+      if (request->bRequest == 0x22) {
         // Webserial simulate the CDC_REQUEST_SET_CONTROL_LINE_STATE (0x22) to connect and disconnect.
         web_serial_connected = (request->wValue != 0);
 
         // Always lit LED if connected
-        if ( web_serial_connected )
-        {
+        if (web_serial_connected) {
           board_led_write(true);
           blink_interval_ms = BLINK_ALWAYS_ON;
 
           tud_vendor_write_str("\r\nWebUSB interface connected\r\n");
-          tud_vendor_flush();
-        }else
-        {
+          tud_vendor_write_flush();
+        } else {
           blink_interval_ms = BLINK_MOUNTED;
         }
 
         // response with status OK
         return tud_control_status(rhport, request);
       }
-    break;
+      break;
 
     default: break;
   }
@@ -231,32 +217,24 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
   return false;
 }
 
-void webserial_task(void)
-{
-  if ( web_serial_connected )
-  {
-    if ( tud_vendor_available() )
-    {
-      uint8_t buf[64];
-      uint32_t count = tud_vendor_read(buf, sizeof(buf));
+void tud_vendor_rx_cb(uint8_t itf, uint8_t const* buffer, uint16_t bufsize) {
+  (void) itf;
 
-      // echo back to both web serial and cdc
-      echo_all(buf, count);
-    }
-  }
+  echo_all(buffer, bufsize);
+
+  // if using RX buffered is enabled, we need to flush the buffer to make room for new data
+  #if CFG_TUD_VENDOR_RX_BUFSIZE > 0
+  tud_vendor_read_flush();
+  #endif
 }
 
-
 //--------------------------------------------------------------------+
 // USB CDC
 //--------------------------------------------------------------------+
-void cdc_task(void)
-{
-  if ( tud_cdc_connected() )
-  {
+void cdc_task(void) {
+  if (tud_cdc_connected()) {
     // connected and there are data available
-    if ( tud_cdc_available() )
-    {
+    if (tud_cdc_available()) {
       uint8_t buf[64];
 
       uint32_t count = tud_cdc_read(buf, sizeof(buf));
@@ -268,34 +246,30 @@ void cdc_task(void)
 }
 
 // Invoked when cdc when line state changed e.g connected/disconnected
-void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
-{
-  (void) itf;
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) {
+  (void)itf;
 
   // connected
-  if ( dtr && rts )
-  {
+  if (dtr && rts) {
     // print initial message when connected
     tud_cdc_write_str("\r\nTinyUSB WebUSB device example\r\n");
   }
 }
 
 // Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
-  (void) itf;
+void tud_cdc_rx_cb(uint8_t itf) {
+  (void)itf;
 }
 
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/device/webusb_serial/src/tusb_config.h b/examples/device/webusb_serial/src/tusb_config.h
index fde732b9e..b86ad3752 100644
--- a/examples/device/webusb_serial/src/tusb_config.h
+++ b/examples/device/webusb_serial/src/tusb_config.h
@@ -102,7 +102,7 @@
 #define CFG_TUD_CDC_TX_BUFSIZE    (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 // Vendor FIFO size of TX and RX
-// If not configured vendor endpoints will not be buffered
+// If zero: vendor endpoints will not be buffered
 #define CFG_TUD_VENDOR_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 #define CFG_TUD_VENDOR_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c
index cafe2c22b..2b69a5b56 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.c
+++ b/examples/device/webusb_serial/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -86,22 +87,40 @@ enum
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
-  #define EPNUM_CDC_IN     2
-  #define EPNUM_CDC_OUT    2
-  #define EPNUM_VENDOR_IN  5
-  #define EPNUM_VENDOR_OUT 5
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
-  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+  #define EPNUM_CDC_NOTIF  0x81
+  #define EPNUM_CDC_OUT    0x02
+  #define EPNUM_CDC_IN     0x82
+
+  #define EPNUM_VENDOR_OUT 0x05
+  #define EPNUM_VENDOR_IN  0x85
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x81
+
+  #define EPNUM_VENDOR_OUT  0x05
+  #define EPNUM_VENDOR_IN   0x84
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
   //    e.g EP1 OUT & EP1 IN cannot exist together
-  #define EPNUM_CDC_IN     2
-  #define EPNUM_CDC_OUT    3
-  #define EPNUM_VENDOR_IN  4
-  #define EPNUM_VENDOR_OUT 5
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+
+  #define EPNUM_VENDOR_OUT  0x04
+  #define EPNUM_VENDOR_IN   0x85
+
 #else
-  #define EPNUM_CDC_IN     2
-  #define EPNUM_CDC_OUT    2
-  #define EPNUM_VENDOR_IN  3
-  #define EPNUM_VENDOR_OUT 3
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+
+  #define EPNUM_VENDOR_OUT  0x03
+  #define EPNUM_VENDOR_IN   0x83
 #endif
 
 uint8_t const desc_configuration[] =
@@ -110,7 +129,7 @@ uint8_t const desc_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, 0x81, 8, EPNUM_CDC_OUT, 0x80 | EPNUM_CDC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64),
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, 0x80 | EPNUM_CDC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64),
 
   // Interface number, string index, EP Out & IN address, EP size
   TUD_VENDOR_DESCRIPTOR(ITF_NUM_VENDOR, 5, EPNUM_VENDOR_OUT, 0x80 | EPNUM_VENDOR_IN, TUD_OPT_HIGH_SPEED ? 512 : 64)
@@ -200,53 +219,65 @@ TU_VERIFY_STATIC(sizeof(desc_ms_os_20) == MS_OS_20_DESC_LEN, "Incorrect size");
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB CDC",                 // 4: CDC Interface
   "TinyUSB WebUSB"               // 5: Vendor Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/webusb_serial/src/usb_descriptors.h b/examples/device/webusb_serial/src/usb_descriptors.h
index 19f1ff3f3..a1c4a2cf1 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.h
+++ b/examples/device/webusb_serial/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt
index d2f9a42f0..c5e3ffce4 100644
--- a/examples/dual/CMakeLists.txt
+++ b/examples/dual/CMakeLists.txt
@@ -1,12 +1,14 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
-project(tinyusb_dual_examples)
+project(tinyusb_dual_examples C CXX ASM)
 family_initialize_project(tinyusb_dual_examples ${CMAKE_CURRENT_LIST_DIR})
+
 if (FAMILY STREQUAL "rp2040" AND NOT TARGET tinyusb_pico_pio_usb)
-    message("Skipping dual host/device mode examples as Pico-PIO-USB is not available")
-else()
-    # family_add_subdirectory will filter what to actually add based on selected FAMILY
-    family_add_subdirectory(host_hid_to_device_cdc)
-endif()
+  message("Skipping dual host/device mode examples as Pico-PIO-USB is not available")
+else ()
+  # family_add_subdirectory will filter what to actually add based on selected FAMILY
+  family_add_subdirectory(host_hid_to_device_cdc)
+  family_add_subdirectory(host_info_to_device_cdc)
+endif ()
diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index 724d1e119..6ae5b5766 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -1,11 +1,11 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
@@ -14,27 +14,29 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_dual_usb_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_dual_usb_example(${PROJECT} noos)
 
 # due to warnings from Pico-PIO-USB
-target_compile_options(${PROJECT} PUBLIC
-        -Wno-error=shadow
-        -Wno-error=cast-align
-        -Wno-error=cast-qual
-        -Wno-error=redundant-decls
-        -Wno-error=sign-conversion
-        -Wno-error=conversion
-        -Wno-error=sign-compare
-        -Wno-error=unused-function
-        )
+if (FAMILY STREQUAL rp2040)
+  target_compile_options(${PROJECT} PUBLIC
+    -Wno-error=shadow
+    -Wno-error=cast-align
+    -Wno-error=cast-qual
+    -Wno-error=redundant-decls
+    -Wno-error=sign-conversion
+    -Wno-error=conversion
+    -Wno-error=sign-compare
+    -Wno-error=unused-function
+    )
+endif ()
diff --git a/examples/dual/host_hid_to_device_cdc/Makefile b/examples/dual/host_hid_to_device_cdc/Makefile
index 3fe9b0888..474ae9814 100644
--- a/examples/dual/host_hid_to_device_cdc/Makefile
+++ b/examples/dual/host_hid_to_device_cdc/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -9,11 +8,11 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
+CFLAGS_GCC += -Wno-error=cast-align -Wno-error=null-dereference
 
 SRC_C += \
 	src/class/hid/hid_host.c \
 	src/host/hub.c \
 	src/host/usbh.c
 
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt
index 6ee8e3fde..3f40b4e7c 100644
--- a/examples/dual/host_hid_to_device_cdc/only.txt
+++ b/examples/dual/host_hid_to_device_cdc/only.txt
@@ -1,3 +1,9 @@
 board:mimxrt1060_evk
 board:mimxrt1064_evk
+board:mcb1800
 mcu:RP2040
+mcu:ra6m5
+mcu:MAX3421
+mcu:STM32F4
+mcu:STM32F7
+mcu:STM32H7
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index bd7870274..633f7a6ac 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -30,7 +30,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
@@ -55,14 +55,14 @@ const uint8_t colemak[128] = {
 };
 #endif
 
-static uint8_t const keycode2ascii[128][2] =  { HID_KEYCODE_TO_ASCII };
+static uint8_t const keycode2ascii[128][2] = {HID_KEYCODE_TO_ASCII};
 
 /* Blink pattern
  * - 250 ms  : device not mounted
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
-enum  {
+enum {
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
@@ -73,18 +73,29 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 void led_blinking_task(void);
 
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   printf("TinyUSB Host HID <-> Device CDC Example\r\n");
 
   // init device and host stack on configured roothub port
-  tud_init(BOARD_TUD_RHPORT);
-  tuh_init(BOARD_TUH_RHPORT);
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
 
-  while (1)
-  {
+  tusb_rhport_init_t host_init = {
+    .role = TUSB_ROLE_HOST,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUH_RHPORT, &host_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  while (1) {
     tud_task(); // tinyusb device task
     tuh_task(); // tinyusb host task
     led_blinking_task();
@@ -98,35 +109,30 @@ int main(void)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
-  blink_interval_ms = BLINK_MOUNTED;
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 // Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
+void tud_cdc_rx_cb(uint8_t itf) {
   (void) itf;
 
   char buf[64];
@@ -145,38 +151,36 @@ void tud_cdc_rx_cb(uint8_t itf)
 // can be used to parse common/simple enough descriptor.
 // Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
 // therefore report_desc = NULL, desc_len = 0
-void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
-{
-  (void)desc_report;
-  (void)desc_len;
+void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len) {
+  (void) desc_report;
+  (void) desc_len;
 
   // Interface protocol (hid_interface_protocol_enum_t)
-  const char* protocol_str[] = { "None", "Keyboard", "Mouse" };
+  const char* protocol_str[] = {"None", "Keyboard", "Mouse"};
   uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
 
   uint16_t vid, pid;
   tuh_vid_pid_get(dev_addr, &vid, &pid);
 
   char tempbuf[256];
-  int count = sprintf(tempbuf, "[%04x:%04x][%u] HID Interface%u, Protocol = %s\r\n", vid, pid, dev_addr, instance, protocol_str[itf_protocol]);
+  int count = sprintf(
+      tempbuf, "[%04x:%04x][%u] HID Interface%u, Protocol = %s\r\n", vid, pid, dev_addr, instance,
+      protocol_str[itf_protocol]);
 
   tud_cdc_write(tempbuf, (uint32_t) count);
   tud_cdc_write_flush();
 
   // Receive report from boot keyboard & mouse only
   // tuh_hid_report_received_cb() will be invoked when report is available
-  if (itf_protocol == HID_ITF_PROTOCOL_KEYBOARD || itf_protocol == HID_ITF_PROTOCOL_MOUSE)
-  {
-    if ( !tuh_hid_receive_report(dev_addr, instance) )
-    {
+  if (itf_protocol == HID_ITF_PROTOCOL_KEYBOARD || itf_protocol == HID_ITF_PROTOCOL_MOUSE) {
+    if (!tuh_hid_receive_report(dev_addr, instance)) {
       tud_cdc_write_str("Error: cannot request report\r\n");
     }
   }
 }
 
 // Invoked when device with hid interface is un-mounted
-void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
-{
+void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) {
   char tempbuf[256];
   int count = sprintf(tempbuf, "[%u] HID Interface%u is unmounted\r\n", dev_addr, instance);
   tud_cdc_write(tempbuf, (uint32_t) count);
@@ -184,11 +188,9 @@ void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 }
 
 // look up new key in previous keys
-static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode)
-{
-  for(uint8_t i=0; i<6; i++)
-  {
-    if (report->keycode[i] == keycode)  return true;
+static inline bool find_key_in_report(hid_keyboard_report_t const* report, uint8_t keycode) {
+  for (uint8_t i = 0; i < 6; i++) {
+    if (report->keycode[i] == keycode) return true;
   }
 
   return false;
@@ -196,22 +198,17 @@ static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8
 
 
 // convert hid keycode to ascii and print via usb device CDC (ignore non-printable)
-static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const *report)
-{
+static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const* report) {
   (void) dev_addr;
-  static hid_keyboard_report_t prev_report = { 0, 0, {0} }; // previous report to check key released
+  static hid_keyboard_report_t prev_report = {0, 0, {0}}; // previous report to check key released
   bool flush = false;
 
-  for(uint8_t i=0; i<6; i++)
-  {
+  for (uint8_t i = 0; i < 6; i++) {
     uint8_t keycode = report->keycode[i];
-    if ( keycode )
-    {
-      if ( find_key_in_report(&prev_report, keycode) )
-      {
+    if (keycode) {
+      if (find_key_in_report(&prev_report, keycode)) {
         // exist in previous report means the current key is holding
-      }else
-      {
+      } else {
         // not existed in previous report means the current key is pressed
 
         // remap the key code for Colemak layout
@@ -223,8 +220,7 @@ static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const *re
         bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
         uint8_t ch = keycode2ascii[keycode][is_shift ? 1 : 0];
 
-        if (ch)
-        {
+        if (ch) {
           if (ch == '\n') tud_cdc_write("\r", 1);
           tud_cdc_write(&ch, 1);
           flush = true;
@@ -240,13 +236,12 @@ static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const *re
 }
 
 // send mouse report to usb device CDC
-static void process_mouse_report(uint8_t dev_addr, hid_mouse_report_t const * report)
-{
+static void process_mouse_report(uint8_t dev_addr, hid_mouse_report_t const* report) {
   //------------- button state  -------------//
   //uint8_t button_changed_mask = report->buttons ^ prev_report.buttons;
-  char l = report->buttons & MOUSE_BUTTON_LEFT   ? 'L' : '-';
+  char l = report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-';
   char m = report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-';
-  char r = report->buttons & MOUSE_BUTTON_RIGHT  ? 'R' : '-';
+  char r = report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-';
 
   char tempbuf[32];
   int count = sprintf(tempbuf, "[%u] %c%c%c %d %d %d\r\n", dev_addr, l, m, r, report->x, report->y, report->wheel);
@@ -256,27 +251,25 @@ static void process_mouse_report(uint8_t dev_addr, hid_mouse_report_t const * re
 }
 
 // Invoked when received report from device via interrupt endpoint
-void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
-{
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len) {
   (void) len;
   uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
 
-  switch(itf_protocol)
-  {
+  switch (itf_protocol) {
     case HID_ITF_PROTOCOL_KEYBOARD:
-      process_kbd_report(dev_addr, (hid_keyboard_report_t const*) report );
-    break;
+      process_kbd_report(dev_addr, (hid_keyboard_report_t const*) report);
+      break;
 
     case HID_ITF_PROTOCOL_MOUSE:
-      process_mouse_report(dev_addr, (hid_mouse_report_t const*) report );
-    break;
+      process_mouse_report(dev_addr, (hid_mouse_report_t const*) report);
+      break;
 
-    default: break;
+    default:
+      break;
   }
 
   // continue to request to receive report
-  if ( !tuh_hid_receive_report(dev_addr, instance) )
-  {
+  if (!tuh_hid_receive_report(dev_addr, instance)) {
     tud_cdc_write_str("Error: cannot request report\r\n");
   }
 }
@@ -284,13 +277,12 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t cons
 //--------------------------------------------------------------------+
 // Blinking Task
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
index f749bd712..2843e0b83 100644
--- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
+++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef _TUSB_CONFIG_H_
-#define _TUSB_CONFIG_H_
+#ifndef TUSB_CONFIG_H_
+#define TUSB_CONFIG_H_
 
 #ifdef __cplusplus
  extern "C" {
@@ -84,10 +84,6 @@
 #define CFG_TUH_RPI_PIO_USB   1
 #endif
 
-
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -95,12 +91,12 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUD_MEM_SECTION
+#define CFG_TUD_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
+#ifndef CFG_TUD_MEM_ALIGN
+#define CFG_TUD_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
@@ -128,11 +124,19 @@
 // Size of buffer to hold descriptors and other data used for enumeration
 #define CFG_TUH_ENUMERATION_BUFSIZE 256
 
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN           __attribute__ ((aligned(4)))
+#endif
+
 #define CFG_TUH_HUB                 1
 // max device support (excluding hub device)
 #define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
 
-#define CFG_TUH_HID                  4
+#define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX)
 #define CFG_TUH_HID_EPIN_BUFSIZE    64
 #define CFG_TUH_HID_EPOUT_BUFSIZE   64
 
@@ -140,4 +144,4 @@
  }
 #endif
 
-#endif /* _TUSB_CONFIG_H_ */
+#endif
diff --git a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
index 6b0a89127..9d57737fb 100644
--- a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
+++ b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -41,44 +42,41 @@
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
-  .bLength            = sizeof(tusb_desc_device_t),
-  .bDescriptorType    = TUSB_DESC_DEVICE,
-  .bcdUSB             = USB_BCD,
+tusb_desc_device_t const desc_device = {
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = USB_BCD,
 
-  // Use Interface Association Descriptor (IAD) for CDC
-  // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
-  .bDeviceClass       = TUSB_CLASS_MISC,
-  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
-  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    // Use Interface Association Descriptor (IAD) for CDC
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
 
-  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-  .idVendor           = USB_VID,
-  .idProduct          = USB_PID,
-  .bcdDevice          = 0x0100,
+    .idVendor           = USB_VID,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
 
-  .iManufacturer      = 0x01,
-  .iProduct           = 0x02,
-  .iSerialNumber      = 0x03,
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
 
-  .bNumConfigurations = 0x01
+    .bNumConfigurations = 0x01
 };
 
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
-  return (uint8_t const *) &desc_device;
+uint8_t const* tud_descriptor_device_cb(void) {
+  return (uint8_t const*) &desc_device;
 }
 
 //--------------------------------------------------------------------+
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
-enum
-{
+enum {
   ITF_NUM_CDC = 0,
   ITF_NUM_CDC_DATA,
   ITF_NUM_TOTAL
@@ -91,7 +89,7 @@ enum
   #define EPNUM_CDC_OUT     0x02
   #define EPNUM_CDC_IN      0x82
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
   // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_NOTIF   0x81
@@ -108,7 +106,7 @@ enum
   #define EPNUM_CDC_IN      0x81
 
 #elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
-  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+// FT9XX doesn't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_NOTIF   0x81
   #define EPNUM_CDC_OUT     0x02
@@ -124,21 +122,19 @@ enum
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
 
 // full speed configuration
-uint8_t const desc_fs_configuration[] =
-{
-  // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+    // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
 };
 
 #if TUD_OPT_HIGH_SPEED
 // Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
 
 // high speed configuration
-uint8_t const desc_hs_configuration[] =
-{
+uint8_t const desc_hs_configuration[] = {
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
@@ -150,8 +146,7 @@ uint8_t const desc_hs_configuration[] =
 uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
 
 // device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
-tusb_desc_device_qualifier_t const desc_device_qualifier =
-{
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
   .bLength            = sizeof(tusb_desc_device_qualifier_t),
   .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
   .bcdUSB             = USB_BCD,
@@ -169,16 +164,14 @@ tusb_desc_device_qualifier_t const desc_device_qualifier =
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
 // device_qualifier descriptor describes information about a high-speed capable device that would
 // change if the device were operating at the other speed. If not highspeed capable stall this request.
-uint8_t const* tud_descriptor_device_qualifier_cb(void)
-{
+uint8_t const* tud_descriptor_device_qualifier_cb(void) {
   return (uint8_t const*) &desc_device_qualifier;
 }
 
 // Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 // Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
-uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
-{
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
 
   // if link speed is high return fullspeed config, and vice versa
@@ -198,8 +191,7 @@ uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
 
 #if TUD_OPT_HIGH_SPEED
@@ -214,52 +206,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
-// array of pointer to string descriptors
-char const* string_desc_arr [] =
-{
-  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
-  "TinyUSB",                     // 1: Manufacturer
-  "TinyUSB Device",              // 2: Product
-  "123456789012",                // 3: Serials, should use chip ID
-  "TinyUSB CDC",                 // 4: CDC Interface
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
 };
 
-static uint16_t _desc_str[32];
+// array of pointer to string descriptors
+char const* string_desc_arr[] = {
+    (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                     // 1: Manufacturer
+    "TinyUSB Device",              // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "TinyUSB CDC",                 // 4: CDC Interface
+};
+
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch (index) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char* str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if (chr_count > max_count) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for (size_t i = 0; i < chr_count; i++) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/dual/host_info_to_device_cdc/CMakeLists.txt b/examples/dual/host_info_to_device_cdc/CMakeLists.txt
new file mode 100644
index 000000000..6ae5b5766
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/CMakeLists.txt
@@ -0,0 +1,42 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_dual_usb_example(${PROJECT} noos)
+
+# due to warnings from Pico-PIO-USB
+if (FAMILY STREQUAL rp2040)
+  target_compile_options(${PROJECT} PUBLIC
+    -Wno-error=shadow
+    -Wno-error=cast-align
+    -Wno-error=cast-qual
+    -Wno-error=redundant-decls
+    -Wno-error=sign-conversion
+    -Wno-error=conversion
+    -Wno-error=sign-compare
+    -Wno-error=unused-function
+    )
+endif ()
diff --git a/examples/dual/host_info_to_device_cdc/Makefile b/examples/dual/host_info_to_device_cdc/Makefile
new file mode 100644
index 000000000..083c9169a
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/Makefile
@@ -0,0 +1,17 @@
+include ../../build_system/make/make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+CFLAGS_GCC += -Wno-error=cast-align -Wno-error=null-dereference
+
+SRC_C += \
+	src/host/hub.c \
+	src/host/usbh.c
+
+include ../../build_system/make/rules.mk
diff --git a/examples/dual/host_info_to_device_cdc/only.txt b/examples/dual/host_info_to_device_cdc/only.txt
new file mode 100644
index 000000000..3f40b4e7c
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/only.txt
@@ -0,0 +1,9 @@
+board:mimxrt1060_evk
+board:mimxrt1064_evk
+board:mcb1800
+mcu:RP2040
+mcu:ra6m5
+mcu:MAX3421
+mcu:STM32F4
+mcu:STM32F7
+mcu:STM32H7
diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c
new file mode 100644
index 000000000..668808db2
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/src/main.c
@@ -0,0 +1,302 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* Host example will get device descriptors of attached devices and print it out via device cdc as follows:
+ *    Device 1: ID 046d:c52f SN 11223344
+      Device Descriptor:
+        bLength             18
+        bDescriptorType     1
+        bcdUSB              0200
+        bDeviceClass        0
+        bDeviceSubClass     0
+        bDeviceProtocol     0
+        bMaxPacketSize0     8
+        idVendor            0x046d
+        idProduct           0xc52f
+        bcdDevice           2200
+        iManufacturer       1     Logitech
+        iProduct            2     USB Receiver
+        iSerialNumber       0
+        bNumConfigurations  1
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+// Language ID: English
+#define LANGUAGE_ID 0x0409
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+static bool is_print[CFG_TUH_DEVICE_MAX+1] = { 0 };
+
+static void print_utf16(uint16_t *temp_buf, size_t buf_len);
+void led_blinking_task(void);
+void cdc_task(void);
+
+/*------------- MAIN -------------*/
+int main(void) {
+  board_init();
+
+  printf("TinyUSB Host Information -> Device CDC Example\r\n");
+
+  // init device and host stack on configured roothub port
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+  tusb_rhport_init_t host_init = {
+    .role = TUSB_ROLE_HOST,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUH_RHPORT, &host_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  while (1) {
+    tud_task(); // tinyusb device task
+    tuh_task(); // tinyusb host task
+    cdc_task();
+    led_blinking_task();
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device CDC
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void) {
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void) {
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en) {
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void) {
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+#if 1
+#define cdc_printf(...)                          \
+  do {                                           \
+    char _tempbuf[256];                          \
+    int count = sprintf(_tempbuf, __VA_ARGS__);  \
+    tud_cdc_write(_tempbuf, (uint32_t) count);   \
+    tud_cdc_write_flush();                       \
+    tud_task();                                  \
+  } while(0)
+#endif
+
+//#define cdc_printf printf
+
+void print_device_info(uint8_t daddr) {
+  tusb_desc_device_t desc_device;
+  uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc_device, 18);
+  if (XFER_RESULT_SUCCESS != xfer_result) {
+    tud_cdc_write_str("Failed to get device descriptor\r\n");
+    return;
+  }
+
+  // Get String descriptor using Sync API
+  uint16_t serial[64];
+  uint16_t buf[128];
+
+  cdc_printf("Device %u: ID %04x:%04x SN ", daddr, desc_device.idVendor, desc_device.idProduct);
+  xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, serial, sizeof(serial));
+  if (XFER_RESULT_SUCCESS != xfer_result) {
+    serial[0] = 'n';
+    serial[1] = '/';
+    serial[2] = 'a';
+    serial[3] = 0;
+  }
+  print_utf16(serial, TU_ARRAY_SIZE(serial));
+  tud_cdc_write_str("\r\n");
+
+  cdc_printf("Device Descriptor:\r\n");
+  cdc_printf("  bLength             %u\r\n"     , desc_device.bLength);
+  cdc_printf("  bDescriptorType     %u\r\n"     , desc_device.bDescriptorType);
+  cdc_printf("  bcdUSB              %04x\r\n"   , desc_device.bcdUSB);
+  cdc_printf("  bDeviceClass        %u\r\n"     , desc_device.bDeviceClass);
+  cdc_printf("  bDeviceSubClass     %u\r\n"     , desc_device.bDeviceSubClass);
+  cdc_printf("  bDeviceProtocol     %u\r\n"     , desc_device.bDeviceProtocol);
+  cdc_printf("  bMaxPacketSize0     %u\r\n"     , desc_device.bMaxPacketSize0);
+  cdc_printf("  idVendor            0x%04x\r\n" , desc_device.idVendor);
+  cdc_printf("  idProduct           0x%04x\r\n" , desc_device.idProduct);
+  cdc_printf("  bcdDevice           %04x\r\n"   , desc_device.bcdDevice);
+
+  cdc_printf("  iManufacturer       %u     "     , desc_device.iManufacturer);
+  xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
+  if (XFER_RESULT_SUCCESS == xfer_result ) {
+    print_utf16(buf, TU_ARRAY_SIZE(buf));
+  }
+  tud_cdc_write_str("\r\n");
+
+  cdc_printf("  iProduct            %u     "     , desc_device.iProduct);
+  xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
+  if (XFER_RESULT_SUCCESS == xfer_result) {
+    print_utf16(buf, TU_ARRAY_SIZE(buf));
+  }
+  tud_cdc_write_str("\r\n");
+
+  cdc_printf("  iSerialNumber       %u     "     , desc_device.iSerialNumber);
+  tud_cdc_write_str((char*)serial); // serial is already to UTF-8
+  tud_cdc_write_str("\r\n");
+
+  cdc_printf("  bNumConfigurations  %u\r\n"     , desc_device.bNumConfigurations);
+}
+
+void cdc_task(void) {
+  if (tud_cdc_connected()) {
+    for (uint8_t daddr = 1; daddr <= CFG_TUH_DEVICE_MAX; daddr++) {
+      if (tuh_mounted(daddr)) {
+        if (is_print[daddr]) {
+          is_print[daddr] = false;
+          print_device_info(daddr);
+          tud_cdc_write_flush();
+        }
+      }
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// Host Get device information
+//--------------------------------------------------------------------+
+void tuh_mount_cb(uint8_t daddr) {
+  printf("mounted device %u\r\n", daddr);
+  is_print[daddr] = true;
+}
+
+void tuh_umount_cb(uint8_t daddr) {
+  printf("unmounted device %u\r\n", daddr);
+  is_print[daddr] = false;
+}
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void) {
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
+
+//--------------------------------------------------------------------+
+// String Descriptor Helper
+//--------------------------------------------------------------------+
+
+static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, uint8_t *utf8, size_t utf8_len) {
+  // TODO: Check for runover.
+  (void)utf8_len;
+  // Get the UTF-16 length out of the data itself.
+
+  for (size_t i = 0; i < utf16_len; i++) {
+    uint16_t chr = utf16[i];
+    if (chr < 0x80) {
+      *utf8++ = chr & 0xffu;
+    } else if (chr < 0x800) {
+      *utf8++ = (uint8_t)(0xC0 | (chr >> 6 & 0x1F));
+      *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
+    } else {
+      // TODO: Verify surrogate.
+      *utf8++ = (uint8_t)(0xE0 | (chr >> 12 & 0x0F));
+      *utf8++ = (uint8_t)(0x80 | (chr >> 6 & 0x3F));
+      *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
+    }
+    // TODO: Handle UTF-16 code points that take two entries.
+  }
+}
+
+// Count how many bytes a utf-16-le encoded string will take in utf-8.
+static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
+  size_t total_bytes = 0;
+  for (size_t i = 0; i < len; i++) {
+    uint16_t chr = buf[i];
+    if (chr < 0x80) {
+      total_bytes += 1;
+    } else if (chr < 0x800) {
+      total_bytes += 2;
+    } else {
+      total_bytes += 3;
+    }
+    // TODO: Handle UTF-16 code points that take two entries.
+  }
+  return (int) total_bytes;
+}
+
+static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
+  if ((temp_buf[0] & 0xff) == 0) return;  // empty
+  size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
+  size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
+  _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
+  ((uint8_t*) temp_buf)[utf8_len] = '\0';
+
+  tud_cdc_write(temp_buf, utf8_len);
+  tud_cdc_write_flush();
+  tud_task();
+}
diff --git a/examples/dual/host_info_to_device_cdc/src/tusb_config.h b/examples/dual/host_info_to_device_cdc/src/tusb_config.h
new file mode 100644
index 000000000..bb47fbf4a
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/src/tusb_config.h
@@ -0,0 +1,143 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef TUSB_CONFIG_H_
+#define TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+// RHPort number used for host can be defined by board.mk, default to port 1
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      1
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack, Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_ENABLED       1
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+// Enable Host stack, Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_ENABLED       1
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+// Use pico-pio-usb as host controller for raspberry rp2040
+#define CFG_TUH_RPI_PIO_USB   1
+#endif
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUD_MEM_SECTION
+#define CFG_TUD_MEM_SECTION
+#endif
+
+#ifndef CFG_TUD_MEM_ALIGN
+#define CFG_TUD_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC              1
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+//--------------------------------------------------------------------
+// HOST CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN           __attribute__ ((aligned(4)))
+#endif
+
+#define CFG_TUH_HUB                 1
+// max device support (excluding hub device)
+#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/examples/dual/host_info_to_device_cdc/src/usb_descriptors.c b/examples/dual/host_info_to_device_cdc/src/usb_descriptors.c
new file mode 100644
index 000000000..9d57737fb
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/src/usb_descriptors.c
@@ -0,0 +1,268 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+                           _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
+
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device = {
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = USB_BCD,
+
+    // Use Interface Association Descriptor (IAD) for CDC
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = USB_VID,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const* tud_descriptor_device_cb(void) {
+  return (uint8_t const*) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum {
+  ITF_NUM_CDC = 0,
+  ITF_NUM_CDC_DATA,
+  ITF_NUM_TOTAL
+};
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
+  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x81
+
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+// FT9XX doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+
+#else
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+
+#endif
+
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+
+// full speed configuration
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
+
+// high speed configuration
+uint8_t const desc_hs_configuration[] = {
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+  .bLength            = sizeof(tusb_desc_device_qualifier_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+  .bcdUSB             = USB_BCD,
+
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bNumConfigurations = 0x01,
+  .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void) index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
+  (void) index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_hs_configuration : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr[] = {
+    (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                     // 1: Manufacturer
+    "TinyUSB Device",              // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "TinyUSB CDC",                 // 4: CDC Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+  switch (index) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+      if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) return NULL;
+
+      const char* str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if (chr_count > max_count) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for (size_t i = 0; i < chr_count; i++) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt
index 025b4670c..2783dd84e 100644
--- a/examples/host/CMakeLists.txt
+++ b/examples/host/CMakeLists.txt
@@ -1,13 +1,15 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
-project(tinyusb_host_examples)
+project(tinyusb_host_examples C CXX ASM)
 family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
 
 # family_add_subdirectory will filter what to actually add based on selected FAMILY
 family_add_subdirectory(bare_api)
 family_add_subdirectory(cdc_msc_hid)
+family_add_subdirectory(cdc_msc_hid_freertos)
+family_add_subdirectory(device_info)
 family_add_subdirectory(hid_controller)
 family_add_subdirectory(midi_rx)
 family_add_subdirectory(msc_file_explorer)
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index bc04b01a7..0efe84b60 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
@@ -22,9 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
-
-# For rp2040, un-comment to enable pico-pio-usb
-# family_add_pico_pio_usb(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/bare_api/Makefile b/examples/host/bare_api/Makefile
index 84555a889..0235e08c3 100644
--- a/examples/host/bare_api/Makefile
+++ b/examples/host/bare_api/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -11,14 +10,4 @@ EXAMPLE_SOURCE += \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index fa9c14857..95f9f1d82 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -1,11 +1,17 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
+mcu:STM32F4
+mcu:STM32F7
+mcu:STM32H7
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 51cab2de0..f582f4f5a 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,17 +23,14 @@
  *
  */
 
-/* This example current worked and tested with following controller
- * - Sony DualShock 4 [CUH-ZCT2x] VID = 0x054c, PID = 0x09cc
- */
-
 
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
+#include "class/hid/hid.h"
 
 // English
 #define LANGUAGE_ID 0x0409
@@ -65,7 +62,15 @@ int main(void)
   printf("TinyUSB Bare API Example\r\n");
 
   // init host stack on configured roothub port
-  tuh_init(BOARD_TUH_RHPORT);
+  tusb_rhport_init_t host_init = {
+    .role = TUSB_ROLE_HOST,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUH_RHPORT, &host_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
@@ -410,10 +415,11 @@ static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
 }
 
 static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
+    if ((temp_buf[0] & 0xff) == 0) return;  // empty
     size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
     size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
     _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
     ((uint8_t*) temp_buf)[utf8_len] = '\0';
 
-    printf((char*)temp_buf);
+    printf("%s", (char*)temp_buf);
 }
diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index ed0aaf7da..fab233be0 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,29 +23,15 @@
  *
  */
 
-#ifndef _TUSB_CONFIG_H_
-#define _TUSB_CONFIG_H_
+#ifndef TUSB_CONFIG_H_
+#define TUSB_CONFIG_H_
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Board Specific Configuration
-//--------------------------------------------------------------------+
-
-// RHPort number used for host can be defined by board.mk, default to port 0
-#ifndef BOARD_TUH_RHPORT
-#define BOARD_TUH_RHPORT      0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUH_MAX_SPEED
-#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
@@ -61,12 +47,6 @@
 #define CFG_TUSB_DEBUG        0
 #endif
 
-// Enable Host stack
-#define CFG_TUH_ENABLED       1
-
-// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -74,16 +54,48 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
-// CONFIGURATION
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Driver Configuration
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
@@ -94,7 +106,7 @@
 
 // max device support (excluding hub device)
 // 1 hub typically has 4 ports
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
 
 // Max endpoint per device
 #define CFG_TUH_ENDPOINT_MAX        8
@@ -106,4 +118,4 @@
  }
 #endif
 
-#endif /* _TUSB_CONFIG_H_ */
+#endif
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 5b44ef217..e8928cda5 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -1,44 +1,35 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
-
-# For rp2040, un-comment to enable pico-pio-usb
-family_add_pico_pio_usb(${PROJECT})
-
-# due to warnings from Pico-PIO-USB
-target_compile_options(${PROJECT} PUBLIC
-        -Wno-error=shadow
-        -Wno-error=cast-align
-        -Wno-error=cast-qual
-        -Wno-error=redundant-decls
-        -Wno-error=sign-conversion
-        -Wno-error=conversion
-        -Wno-error=sign-compare
-        -Wno-error=unused-function
-        )
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index ad28076a0..213c02f9c 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -7,20 +6,11 @@ INC += \
 
 # Example source
 EXAMPLE_SOURCE = \
-	src/hid_app.c \
+  src/cdc_app.c \
+  src/hid_app.c \
   src/main.c \
   src/msc_app.c \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index fa9c14857..95f9f1d82 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -1,11 +1,17 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
+mcu:STM32F4
+mcu:STM32F7
+mcu:STM32H7
diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
new file mode 100644
index 000000000..4a13f8b27
--- /dev/null
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -0,0 +1,109 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb.h"
+#include "bsp/board_api.h"
+
+size_t get_console_inputs(uint8_t* buf, size_t bufsize) {
+  size_t count = 0;
+  while (count < bufsize) {
+    int ch = board_getchar();
+    if (ch <= 0) break;
+
+    buf[count] = (uint8_t) ch;
+    count++;
+  }
+
+  return count;
+}
+
+void cdc_app_task(void) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
+
+  uint32_t count = get_console_inputs(buf, bufsize);
+  buf[count] = 0;
+
+  // loop over all mounted interfaces
+  for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
+    if (tuh_cdc_mounted(idx)) {
+      // console --> cdc interfaces
+      if (count) {
+        tuh_cdc_write(idx, buf, count);
+        tuh_cdc_write_flush(idx);
+      }
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when received new data
+void tuh_cdc_rx_cb(uint8_t idx) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
+
+  // forward cdc interfaces -> console
+  uint32_t count = tuh_cdc_read(idx, buf, bufsize);
+  buf[count] = 0;
+
+  printf("%s", (char*) buf);
+}
+
+// Invoked when a device with CDC interface is mounted
+// idx is index of cdc interface in the internal pool.
+void tuh_cdc_mount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = {0};
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr,
+         itf_info.desc.bInterfaceNumber);
+
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+  // If CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined, line coding will be set by tinyusb stack
+  // while eneumerating new cdc device
+  cdc_line_coding_t line_coding = {0};
+  if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
+    printf("  Baudrate: %" PRIu32 ", Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
+    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
+  }
+#else
+  // Set Line Coding upon mounted
+  cdc_line_coding_t new_line_coding = { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 };
+  tuh_cdc_set_line_coding(idx, &new_line_coding, NULL, 0);
+#endif
+}
+
+// Invoked when a device with CDC interface is unmounted
+void tuh_cdc_umount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = {0};
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr,
+         itf_info.desc.bInterfaceNumber);
+}
diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index 11437c2b4..3f98ec89f 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
@@ -130,13 +130,12 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t cons
 //--------------------------------------------------------------------+
 
 // look up new key in previous keys
-static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode)
-{
-  for(uint8_t i=0; i<6; i++)
-  {
-    if (report->keycode[i] == keycode)  return true;
+static inline bool find_key_in_report(hid_keyboard_report_t const* report, uint8_t keycode) {
+  for (uint8_t i = 0; i < 6; i++) {
+    if (report->keycode[i] == keycode) {
+      return true;
+    }
   }
-
   return false;
 }
 
@@ -160,7 +159,9 @@ static void process_kbd_report(hid_keyboard_report_t const *report)
         putchar(ch);
         if ( ch == '\r' ) putchar('\n'); // added new line for enter key
 
+        #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
         fflush(stdout); // flush right away, else nanolib will wait for newline
+        #endif
       }
     }
     // TODO example skips key released
@@ -233,6 +234,7 @@ static void process_mouse_report(hid_mouse_report_t const * report)
 static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) dev_addr;
+  (void) len;
 
   uint8_t const rpt_count = hid_info[instance].report_count;
   tuh_hid_report_info_t* rpt_info_arr = hid_info[instance].report_info;
@@ -247,7 +249,7 @@ static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t c
     // Composite report, 1st byte is report ID, data starts from 2nd byte
     uint8_t const rpt_id = report[0];
 
-    // Find report id in the arrray
+    // Find report id in the array
     for(uint8_t i=0; i<rpt_count; i++)
     {
       if (rpt_id == rpt_info_arr[i].report_id )
@@ -263,7 +265,7 @@ static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t c
 
   if (!rpt_info)
   {
-    printf("Couldn't find the report info for this report !\r\n");
+    printf("Couldn't find report info !\r\n");
     return;
   }
 
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index d26e41e8d..71257c0fe 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,75 +27,65 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
 void led_blinking_task(void);
-
-extern void cdc_task(void);
+extern void cdc_app_task(void);
 extern void hid_app_task(void);
 
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+// API to read/rite MAX3421's register. Implemented by TinyUSB
+extern uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
+extern bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
+#endif
+
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   printf("TinyUSB Host CDC MSC HID Example\r\n");
 
   // init host stack on configured roothub port
-  tuh_init(BOARD_TUH_RHPORT);
+  tusb_rhport_init_t host_init = {
+    .role = TUSB_ROLE_HOST,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUH_RHPORT, &host_init);
 
-  while (1)
-  {
-    // tinyusb host task
-    tuh_task();
-    led_blinking_task();
-
-    cdc_task();
-    hid_app_task();
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
   }
 
-  return 0;
-}
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+  // FeatherWing MAX3421E use MAX3421E's GPIO0 for VBUS enable
+  enum { IOPINS1_ADDR  = 20u << 3, /* 0xA0 */ };
+  tuh_max3421_reg_write(BOARD_TUH_RHPORT, IOPINS1_ADDR, 0x01, false);
+#endif
 
-//--------------------------------------------------------------------+
-// USB CDC
-//--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION static char serial_in_buffer[64] = { 0 };
-
-// invoked ISR context
-void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes)
-{
-  (void) event;
-  (void) pipe_id;
-  (void) xferred_bytes;
-
-  printf(serial_in_buffer);
-  tu_memclr(serial_in_buffer, sizeof(serial_in_buffer));
-
-  tuh_cdc_receive(dev_addr, serial_in_buffer, sizeof(serial_in_buffer), true); // waiting for next data
-}
-
-void cdc_task(void)
-{
+  while (1) {
+    // tinyusb host task
+    tuh_task();
 
+    led_blinking_task();
+    cdc_app_task();
+    hid_app_task();
+  }
 }
 
 //--------------------------------------------------------------------+
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
 
-void tuh_mount_cb(uint8_t dev_addr)
-{
+void tuh_mount_cb(uint8_t dev_addr) {
   // application set-up
   printf("A device with address %d is mounted\r\n", dev_addr);
 }
 
-void tuh_umount_cb(uint8_t dev_addr)
-{
+void tuh_umount_cb(uint8_t dev_addr) {
   // application tear-down
   printf("A device with address %d is unmounted \r\n", dev_addr);
 }
@@ -104,15 +94,14 @@ void tuh_umount_cb(uint8_t dev_addr)
 //--------------------------------------------------------------------+
 // Blinking Task
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
   const uint32_t interval_ms = 1000;
   static uint32_t start_ms = 0;
 
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  if (board_millis() - start_ms < interval_ms) return; // not enough time
   start_ms += interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c
index 80a5eab6f..1d7e18e6e 100644
--- a/examples/host/cdc_msc_hid/src/msc_app.c
+++ b/examples/host/cdc_msc_hid/src/msc_app.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -30,8 +30,11 @@
 //--------------------------------------------------------------------+
 static scsi_inquiry_resp_t inquiry_resp;
 
-bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
 {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
+
   if (csw->status != 0)
   {
     printf("Inquiry failed\r\n");
@@ -45,8 +48,8 @@ bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const
   uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
   uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
 
-  printf("Disk Size: %lu MB\r\n", block_count / ((1024*1024)/block_size));
-  printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
+  printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024*1024)/block_size));
+  printf("Block Count = %" PRIu32 ", Block Size: %" PRIu32 "\r\n", block_count, block_size);
 
   return true;
 }
@@ -57,47 +60,11 @@ void tuh_msc_mount_cb(uint8_t dev_addr)
   printf("A MassStorage device is mounted\r\n");
 
   uint8_t const lun = 0;
-  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb);
-//
-//  //------------- file system (only 1 LUN support) -------------//
-//  uint8_t phy_disk = dev_addr-1;
-//  disk_initialize(phy_disk);
-//
-//  if ( disk_is_ready(phy_disk) )
-//  {
-//    if ( f_mount(phy_disk, &fatfs[phy_disk]) != FR_OK )
-//    {
-//      puts("mount failed");
-//      return;
-//    }
-//
-//    f_chdrive(phy_disk); // change to newly mounted drive
-//    f_chdir("/"); // root as current dir
-//
-//    cli_init();
-//  }
+  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0);
 }
 
 void tuh_msc_umount_cb(uint8_t dev_addr)
 {
   (void) dev_addr;
   printf("A MassStorage device is unmounted\r\n");
-
-//  uint8_t phy_disk = dev_addr-1;
-//
-//  f_mount(phy_disk, NULL); // unmount disk
-//  disk_deinitialize(phy_disk);
-//
-//  if ( phy_disk == f_get_current_drive() )
-//  { // active drive is unplugged --> change to other drive
-//    for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
-//    {
-//      if ( disk_is_ready(i) )
-//      {
-//        f_chdrive(i);
-//        cli_init(); // refractor, rename
-//      }
-//    }
-//  }
 }
-
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index c515405cb..a59a0ffb9 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -30,28 +30,8 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Board Specific Configuration
-//--------------------------------------------------------------------+
-
-#if CFG_TUSB_MCU == OPT_MCU_RP2040
-// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   0
-#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-#endif
-
-// RHPort number used for host can be defined by board.mk, default to port 0
-#ifndef BOARD_TUH_RHPORT
-#define BOARD_TUH_RHPORT      0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUH_MAX_SPEED
-#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
@@ -67,12 +47,6 @@
 #define CFG_TUSB_DEBUG        0
 #endif
 
-// Enable Host stack
-#define CFG_TUH_ENABLED       1
-
-// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -80,34 +54,80 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
-// CONFIGURATION
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Driver Configuration
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
 #define CFG_TUH_ENUMERATION_BUFSIZE 256
 
 #define CFG_TUH_HUB                 1 // number of supported hubs
-#define CFG_TUH_CDC                 1
-#define CFG_TUH_HID                 4 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_CDC                 1 // CDC ACM
+#define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CH34X           1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
 
-// max device support (excluding hub device)
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
 
 //------------- HID -------------//
 #define CFG_TUH_HID_EPIN_BUFSIZE    64
 #define CFG_TUH_HID_EPOUT_BUFSIZE   64
 
+//------------- CDC -------------//
+
+// Set Line Control state on enumeration/mounted:
+// DTR ( bit 0), RTS (bit 1)
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+
+// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
+// bit rate = 115200, 1 stop bit, no parity, 8 bit data width
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/examples/host/cdc_msc_hid_freertos/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt
new file mode 100644
index 000000000..78b2784fe
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt
@@ -0,0 +1,35 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} freertos)
diff --git a/examples/host/cdc_msc_hid_freertos/Makefile b/examples/host/cdc_msc_hid_freertos/Makefile
new file mode 100644
index 000000000..178341f81
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/Makefile
@@ -0,0 +1,17 @@
+RTOS = freertos
+include ../../build_system/make/make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE = \
+  src/cdc_app.c \
+  src/hid_app.c \
+  src/main.c \
+  src/msc_app.c \
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt
new file mode 100644
index 000000000..e3ae25260
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/only.txt
@@ -0,0 +1,15 @@
+mcu:ESP32P4
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MIMXRT1XXX
+mcu:MIMXRT10XX
+mcu:MIMXRT11XX
+mcu:MSP432E4
+mcu:RX65X
+mcu:MAX3421
+mcu:STM32F4
+mcu:STM32F7
+mcu:STM32H7
diff --git a/examples/host/cdc_msc_hid_freertos/skip.txt b/examples/host/cdc_msc_hid_freertos/skip.txt
new file mode 100644
index 000000000..2ba4438fd
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/skip.txt
@@ -0,0 +1 @@
+mcu:RP2040
diff --git a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
new file mode 100644
index 000000000..6f057c106
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
@@ -0,0 +1,6 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "cdc_app.c" "hid_app.c" "main.c" "msc_app.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
+
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
new file mode 100644
index 000000000..7cbe1e03a
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -0,0 +1,131 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb.h"
+#include "bsp/board_api.h"
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+  #define CDC_STACK_SZIE      2048
+#else
+  #define CDC_STACK_SZIE     (3*configMINIMAL_STACK_SIZE/2)
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t  cdc_stack[CDC_STACK_SZIE];
+StaticTask_t cdc_taskdef;
+#endif
+
+static void cdc_app_task(void* param);
+
+void cdc_app_init(void) {
+  #if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+  #else
+  xTaskCreate(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+  #endif
+}
+
+// helper
+size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
+  size_t count = 0;
+  while (count < bufsize) {
+    int ch = board_getchar();
+    if (ch <= 0) break;
+
+    buf[count] = (uint8_t) ch;
+    count++;
+  }
+
+  return count;
+}
+
+static void cdc_app_task(void* param) {
+  (void) param;
+
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
+
+  while (1) {
+    uint32_t count = get_console_inputs(buf, bufsize);
+    buf[count] = 0;
+
+    if (count) {
+      // loop over all mounted interfaces
+      for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
+        if (tuh_cdc_mounted(idx)) {
+          // console --> cdc interfaces
+          tuh_cdc_write(idx, buf, count);
+          tuh_cdc_write_flush(idx);
+        }
+      }
+    }
+
+    vTaskDelay(1);
+  }
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when received new data
+void tuh_cdc_rx_cb(uint8_t idx) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
+
+  // forward cdc interfaces -> console
+  uint32_t count = tuh_cdc_read(idx, buf, bufsize);
+  buf[count] = 0;
+
+  printf("%s", (char *) buf);
+}
+
+void tuh_cdc_mount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = { 0 };
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+  // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
+  // otherwise you need to call tuh_cdc_set_line_coding() first
+  cdc_line_coding_t line_coding = { 0 };
+  if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
+    printf("  Baudrate: %" PRIu32 ", Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
+    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
+  }
+#endif
+}
+
+void tuh_cdc_umount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = { 0 };
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/hid_app.c b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
new file mode 100644
index 000000000..9ea5c1be0
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
@@ -0,0 +1,267 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+// If your host terminal support ansi escape code such as TeraTerm
+// it can be use to simulate mouse cursor movement within terminal
+#define USE_ANSI_ESCAPE   0
+
+#define MAX_REPORT  4
+
+static uint8_t const keycode2ascii[128][2] = { HID_KEYCODE_TO_ASCII };
+
+// Each HID instance can has multiple reports
+static struct {
+  uint8_t report_count;
+  tuh_hid_report_info_t report_info[MAX_REPORT];
+} hid_info[CFG_TUH_HID];
+
+static void process_kbd_report(hid_keyboard_report_t const *report);
+static void process_mouse_report(hid_mouse_report_t const *report);
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len);
+
+void hid_app_init(void) {
+  // nothing to do
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device with hid interface is mounted
+// Report descriptor is also available for use. tuh_hid_parse_report_descriptor()
+// can be used to parse common/simple enough descriptor.
+// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
+// therefore report_desc = NULL, desc_len = 0
+void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *desc_report, uint16_t desc_len) {
+  printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
+
+  // Interface protocol (hid_interface_protocol_enum_t)
+  const char *protocol_str[] = { "None", "Keyboard", "Mouse" };
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
+  printf("HID Interface Protocol = %s\r\n", protocol_str[itf_protocol]);
+
+  // By default host stack will use activate boot protocol on supported interface.
+  // Therefore for this simple example, we only need to parse generic report descriptor (with built-in parser)
+  if (itf_protocol == HID_ITF_PROTOCOL_NONE) {
+    hid_info[instance].report_count = tuh_hid_parse_report_descriptor(hid_info[instance].report_info, MAX_REPORT,
+                                                                      desc_report, desc_len);
+    printf("HID has %u reports \r\n", hid_info[instance].report_count);
+  }
+
+  // request to receive report
+  // tuh_hid_report_received_cb() will be invoked when report is available
+  if (!tuh_hid_receive_report(dev_addr, instance)) {
+    printf("Error: cannot request to receive report\r\n");
+  }
+}
+
+// Invoked when device with hid interface is un-mounted
+void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) {
+  printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+}
+
+// Invoked when received report from device via interrupt endpoint
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) {
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
+  switch (itf_protocol) {
+    case HID_ITF_PROTOCOL_KEYBOARD:
+      TU_LOG2("HID receive boot keyboard report\r\n");
+      process_kbd_report((hid_keyboard_report_t const *) report);
+      break;
+
+    case HID_ITF_PROTOCOL_MOUSE:
+      TU_LOG2("HID receive boot mouse report\r\n");
+      process_mouse_report((hid_mouse_report_t const *) report);
+      break;
+
+    default:
+      // Generic report requires matching ReportID and contents with previous parsed report info
+      process_generic_report(dev_addr, instance, report, len);
+      break;
+  }
+
+  // continue to request to receive report
+  if (!tuh_hid_receive_report(dev_addr, instance)) {
+    printf("Error: cannot request to receive report\r\n");
+  }
+}
+
+//--------------------------------------------------------------------+
+// Keyboard
+//--------------------------------------------------------------------+
+
+// look up new key in previous keys
+static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode) {
+  for (uint8_t i = 0; i < 6; i++) {
+    if (report->keycode[i] == keycode) return true;
+  }
+
+  return false;
+}
+
+static void process_kbd_report(hid_keyboard_report_t const *report) {
+  static hid_keyboard_report_t prev_report = { 0, 0, { 0 } }; // previous report to check key released
+
+  //------------- example code ignore control (non-printable) key affects -------------//
+  for (uint8_t i = 0; i < 6; i++) {
+    if (report->keycode[i]) {
+      if (find_key_in_report(&prev_report, report->keycode[i])) {
+        // exist in previous report means the current key is holding
+      } else {
+        // not existed in previous report means the current key is pressed
+        bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
+        uint8_t ch = keycode2ascii[report->keycode[i]][is_shift ? 1 : 0];
+        putchar(ch);
+        if (ch == '\r') putchar('\n'); // added new line for enter key
+
+        #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
+        fflush(stdout); // flush right away, else nanolib will wait for newline
+        #endif
+      }
+    }
+    // TODO example skips key released
+  }
+
+  prev_report = *report;
+}
+
+//--------------------------------------------------------------------+
+// Mouse
+//--------------------------------------------------------------------+
+
+void cursor_movement(int8_t x, int8_t y, int8_t wheel) {
+#if USE_ANSI_ESCAPE
+  // Move X using ansi escape
+  if ( x < 0) {
+    printf(ANSI_CURSOR_BACKWARD(%d), (-x)); // move left
+  }else if ( x > 0) {
+    printf(ANSI_CURSOR_FORWARD(%d), x); // move right
+  }
+
+  // Move Y using ansi escape
+  if ( y < 0) {
+    printf(ANSI_CURSOR_UP(%d), (-y)); // move up
+  }else if ( y > 0) {
+    printf(ANSI_CURSOR_DOWN(%d), y); // move down
+  }
+
+  // Scroll using ansi escape
+  if (wheel < 0) {
+    printf(ANSI_SCROLL_UP(%d), (-wheel)); // scroll up
+  }else if (wheel > 0) {
+    printf(ANSI_SCROLL_DOWN(%d), wheel); // scroll down
+  }
+
+  printf("\r\n");
+#else
+  printf("(%d %d %d)\r\n", x, y, wheel);
+#endif
+}
+
+static void process_mouse_report(hid_mouse_report_t const *report) {
+  static hid_mouse_report_t prev_report = { 0 };
+
+  //------------- button state  -------------//
+  uint8_t button_changed_mask = report->buttons ^ prev_report.buttons;
+  if (button_changed_mask & report->buttons) {
+    printf(" %c%c%c ",
+           report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-',
+           report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-',
+           report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-');
+  }
+
+  //------------- cursor movement -------------//
+  cursor_movement(report->x, report->y, report->wheel);
+}
+
+//--------------------------------------------------------------------+
+// Generic Report
+//--------------------------------------------------------------------+
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) {
+  (void) dev_addr;
+
+  uint8_t const rpt_count = hid_info[instance].report_count;
+  tuh_hid_report_info_t *rpt_info_arr = hid_info[instance].report_info;
+  tuh_hid_report_info_t *rpt_info = NULL;
+
+  if (rpt_count == 1 && rpt_info_arr[0].report_id == 0) {
+    // Simple report without report ID as 1st byte
+    rpt_info = &rpt_info_arr[0];
+  } else {
+    // Composite report, 1st byte is report ID, data starts from 2nd byte
+    uint8_t const rpt_id = report[0];
+
+    // Find report id in the array
+    for (uint8_t i = 0; i < rpt_count; i++) {
+      if (rpt_id == rpt_info_arr[i].report_id) {
+        rpt_info = &rpt_info_arr[i];
+        break;
+      }
+    }
+
+    report++;
+    len--;
+  }
+
+  if (!rpt_info) {
+    printf("Couldn't find report info !\r\n");
+    return;
+  }
+
+  // For complete list of Usage Page & Usage checkout src/class/hid/hid.h. For examples:
+  // - Keyboard                     : Desktop, Keyboard
+  // - Mouse                        : Desktop, Mouse
+  // - Gamepad                      : Desktop, Gamepad
+  // - Consumer Control (Media Key) : Consumer, Consumer Control
+  // - System Control (Power key)   : Desktop, System Control
+  // - Generic (vendor)             : 0xFFxx, xx
+  if (rpt_info->usage_page == HID_USAGE_PAGE_DESKTOP) {
+    switch (rpt_info->usage) {
+      case HID_USAGE_DESKTOP_KEYBOARD:
+        TU_LOG1("HID receive keyboard report\r\n");
+        // Assume keyboard follow boot report layout
+        process_kbd_report((hid_keyboard_report_t const *) report);
+        break;
+
+      case HID_USAGE_DESKTOP_MOUSE:
+        TU_LOG1("HID receive mouse report\r\n");
+        // Assume mouse follow boot report layout
+        process_mouse_report((hid_mouse_report_t const *) report);
+        break;
+
+      default:
+        break;
+    }
+  }
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
new file mode 100644
index 000000000..10d1b120b
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -0,0 +1,171 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+  #define USBH_STACK_SIZE     4096
+#else
+  // Increase stack size when debug log is enabled
+  #define USBH_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+// static timer & task
+#if configSUPPORT_STATIC_ALLOCATION
+StaticTimer_t blinky_tmdef;
+
+StackType_t  usb_host_stack[USBH_STACK_SIZE];
+StaticTask_t usb_host_taskdef;
+#endif
+
+TimerHandle_t blinky_tm;
+
+static void led_blinky_cb(TimerHandle_t xTimer);
+static void usb_host_task(void* param);
+
+extern void cdc_app_init(void);
+extern void hid_app_init(void);
+extern void msc_app_init(void);
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+// API to read/rite MAX3421's register. Implemented by TinyUSB
+extern uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
+extern bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
+#endif
+
+/*------------- MAIN -------------*/
+int main(void) {
+  board_init();
+
+  printf("TinyUSB Host CDC MSC HID with FreeRTOS Example\r\n");
+
+  // Create soft timer for blinky, task for tinyusb stack
+#if configSUPPORT_STATIC_ALLOCATION
+  blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
+  xTaskCreateStatic(usb_host_task, "usbh", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_host_stack, &usb_host_taskdef);
+#else
+  blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
+  xTaskCreate(usb_host_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
+#endif
+
+  xTimerStart(blinky_tm, 0);
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+#if !TUSB_MCU_VENDOR_ESPRESSIF
+  vTaskStartScheduler();
+#endif
+
+  return 0;
+}
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+void app_main(void) {
+  main();
+}
+#endif
+
+// USB Host task
+// This top level thread process all usb events and invoke callbacks
+static void usb_host_task(void *param) {
+  (void) param;
+
+  // init host stack on configured roothub port
+  tusb_rhport_init_t host_init = {
+    .role = TUSB_ROLE_HOST,
+    .speed = TUSB_SPEED_AUTO
+  };
+
+  if (!tusb_init(BOARD_TUH_RHPORT, &host_init)) {
+    printf("Failed to init USB Host Stack\r\n");
+    vTaskSuspend(NULL);
+  }
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+  // FeatherWing MAX3421E use MAX3421E's GPIO0 for VBUS enable
+  enum { IOPINS1_ADDR  = 20u << 3, /* 0xA0 */ };
+  tuh_max3421_reg_write(BOARD_TUH_RHPORT, IOPINS1_ADDR, 0x01, false);
+#endif
+
+  cdc_app_init();
+  hid_app_init();
+  msc_app_init();
+
+  // RTOS forever loop
+  while (1) {
+    // put this thread to waiting state until there is new events
+    tuh_task();
+
+    // following code only run if tuh_task() process at least 1 event
+  }
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+void tuh_mount_cb(uint8_t dev_addr) {
+  // application set-up
+  printf("A device with address %d is mounted\r\n", dev_addr);
+}
+
+void tuh_umount_cb(uint8_t dev_addr) {
+  // application tear-down
+  printf("A device with address %d is unmounted \r\n", dev_addr);
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+static void led_blinky_cb(TimerHandle_t xTimer) {
+  (void) xTimer;
+  static bool led_state = false;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/msc_app.c b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
new file mode 100644
index 000000000..6b9cdab85
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
@@ -0,0 +1,70 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+// define the buffer to be place in USB/DMA memory with correct alignment/cache line size
+CFG_TUH_MEM_SECTION static struct {
+  TUH_EPBUF_TYPE_DEF(scsi_inquiry_resp_t, inquiry);
+} scsi_resp;
+
+void msc_app_init(void) {
+  // nothing to do
+}
+
+bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) {
+  msc_cbw_t const *cbw = cb_data->cbw;
+  msc_csw_t const *csw = cb_data->csw;
+
+  if (csw->status != 0) {
+    printf("Inquiry failed\r\n");
+    return false;
+  }
+
+  // Print out Vendor ID, Product ID and Rev
+  printf("%.8s %.16s rev %.4s\r\n", scsi_resp.inquiry.vendor_id, scsi_resp.inquiry.product_id, scsi_resp.inquiry.product_rev);
+
+  // Get capacity of device
+  uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
+  uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
+
+  printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024 * 1024) / block_size));
+  printf("Block Count = %" PRIu32 ", Block Size: %" PRIu32 "\r\n", block_count, block_size);
+
+  return true;
+}
+
+//------------- IMPLEMENTATION -------------//
+void tuh_msc_mount_cb(uint8_t dev_addr) {
+  printf("A MassStorage device is mounted\r\n");
+
+  uint8_t const lun = 0;
+  tuh_msc_inquiry(dev_addr, lun, &scsi_resp.inquiry, inquiry_complete_cb, 0);
+}
+
+void tuh_msc_umount_cb(uint8_t dev_addr) {
+  (void) dev_addr;
+  printf("A MassStorage device is unmounted\r\n");
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
new file mode 100644
index 000000000..02de4197b
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -0,0 +1,140 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_FREERTOS
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TUSB_MCU_VENDOR_ESPRESSIF
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Driver Configuration
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB                 1 // number of supported hubs
+#define CFG_TUH_CDC                 1 // CDC ACM
+#define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CH34X           1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_MSC                 1
+#define CFG_TUH_VENDOR              0
+
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
+
+//------------- HID -------------//
+#define CFG_TUH_HID_EPIN_BUFSIZE    64
+#define CFG_TUH_HID_EPOUT_BUFSIZE   64
+
+//------------- CDC -------------//
+
+// Set Line Control state on enumeration/mounted:
+// DTR ( bit 0), RTS (bit 1)
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+
+// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
+// bit rate = 115200, 1 stop bit, no parity, 8 bit data width
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/host/device_info/CMakeLists.txt b/examples/host/device_info/CMakeLists.txt
new file mode 100644
index 000000000..33953233d
--- /dev/null
+++ b/examples/host/device_info/CMakeLists.txt
@@ -0,0 +1,32 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/device_info/Makefile b/examples/host/device_info/Makefile
new file mode 100644
index 000000000..0235e08c3
--- /dev/null
+++ b/examples/host/device_info/Makefile
@@ -0,0 +1,13 @@
+include ../../build_system/make/make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+	src/main.c
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt
new file mode 100644
index 000000000..b6f87f423
--- /dev/null
+++ b/examples/host/device_info/only.txt
@@ -0,0 +1,20 @@
+mcu:ESP32S2
+mcu:ESP32S3
+mcu:ESP32P4
+mcu:KINETIS_KL
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MAX3421
+mcu:MIMXRT1XXX
+mcu:MIMXRT10XX
+mcu:MIMXRT11XX
+mcu:MSP432E4
+mcu:RP2040
+mcu:RX65X
+mcu:RAXXX
+mcu:STM32F4
+mcu:STM32F7
+mcu:STM32H7
diff --git a/examples/host/device_info/src/CMakeLists.txt b/examples/host/device_info/src/CMakeLists.txt
new file mode 100644
index 000000000..1908a32c3
--- /dev/null
+++ b/examples/host/device_info/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c
new file mode 100644
index 000000000..775968c16
--- /dev/null
+++ b/examples/host/device_info/src/main.c
@@ -0,0 +1,308 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* Host example will get device descriptors of attached devices and print it out via uart/rtt (logger) as follows:
+ *    Device 1: ID 046d:c52f SN 11223344
+      Device Descriptor:
+        bLength             18
+        bDescriptorType     1
+        bcdUSB              0200
+        bDeviceClass        0
+        bDeviceSubClass     0
+        bDeviceProtocol     0
+        bMaxPacketSize0     8
+        idVendor            0x046d
+        idProduct           0xc52f
+        bcdDevice           2200
+        iManufacturer       1     Logitech
+        iProduct            2     USB Receiver
+        iSerialNumber       0
+        bNumConfigurations  1
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+// English
+#define LANGUAGE_ID 0x0409
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+enum {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Declare for buffer for usb transfer, may need to be in USB/DMA section and
+// multiple of dcache line size if dcache is enabled (for some ports).
+CFG_TUH_MEM_SECTION struct {
+  TUH_EPBUF_TYPE_DEF(tusb_desc_device_t, device);
+  TUH_EPBUF_DEF(serial, 64*sizeof(uint16_t));
+  TUH_EPBUF_DEF(buf, 128*sizeof(uint16_t));
+} desc;
+
+void led_blinking_task(void* param);
+static void print_utf16(uint16_t* temp_buf, size_t buf_len);
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+void init_freertos_task(void);
+#endif
+
+//--------------------------------------------------------------------
+// Main
+//--------------------------------------------------------------------
+void init_tinyusb(void) {
+  // init host stack on configured roothub port
+  tusb_rhport_init_t host_init = {
+    .role = TUSB_ROLE_HOST,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUH_RHPORT, &host_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+}
+
+int main(void) {
+  board_init();
+  printf("TinyUSB Device Info Example\r\n");
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  init_freertos_task();
+#else
+  init_tinyusb();
+  while (1) {
+    tuh_task();     // tinyusb host task
+    led_blinking_task(NULL);
+  }
+  return 0;
+#endif
+}
+
+/*------------- TinyUSB Callbacks -------------*/
+
+// Invoked when device is mounted (configured)
+void tuh_mount_cb(uint8_t daddr) {
+  blink_interval_ms = BLINK_MOUNTED;
+
+  // Get Device Descriptor
+  uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc.device, 18);
+  if (XFER_RESULT_SUCCESS != xfer_result) {
+    printf("Failed to get device descriptor\r\n");
+    return;
+  }
+
+  printf("Device %u: ID %04x:%04x SN ", daddr, desc.device.idVendor, desc.device.idProduct);
+  xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, desc.serial, sizeof(desc.serial));
+  if (XFER_RESULT_SUCCESS != xfer_result) {
+    uint16_t* serial = (uint16_t*)(uintptr_t) desc.serial;
+    serial[0] = 'n';
+    serial[1] = '/';
+    serial[2] = 'a';
+    serial[3] = 0;
+  }
+  print_utf16((uint16_t*)(uintptr_t) desc.serial, sizeof(desc.serial)/2);
+  printf("\r\n");
+
+  printf("Device Descriptor:\r\n");
+  printf("  bLength             %u\r\n", desc.device.bLength);
+  printf("  bDescriptorType     %u\r\n", desc.device.bDescriptorType);
+  printf("  bcdUSB              %04x\r\n", desc.device.bcdUSB);
+  printf("  bDeviceClass        %u\r\n", desc.device.bDeviceClass);
+  printf("  bDeviceSubClass     %u\r\n", desc.device.bDeviceSubClass);
+  printf("  bDeviceProtocol     %u\r\n", desc.device.bDeviceProtocol);
+  printf("  bMaxPacketSize0     %u\r\n", desc.device.bMaxPacketSize0);
+  printf("  idVendor            0x%04x\r\n", desc.device.idVendor);
+  printf("  idProduct           0x%04x\r\n", desc.device.idProduct);
+  printf("  bcdDevice           %04x\r\n", desc.device.bcdDevice);
+
+  // Get String descriptor using Sync API
+
+  printf("  iManufacturer       %u     ", desc.device.iManufacturer);
+  xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf));
+  if (XFER_RESULT_SUCCESS == xfer_result) {
+    print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2);
+  }
+  printf("\r\n");
+
+  printf("  iProduct            %u     ", desc.device.iProduct);
+  xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf));
+  if (XFER_RESULT_SUCCESS == xfer_result) {
+    print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2);
+  }
+  printf("\r\n");
+
+  printf("  iSerialNumber       %u     ", desc.device.iSerialNumber);
+  printf((char*)desc.serial); // serial is already to UTF-8
+  printf("\r\n");
+
+  printf("  bNumConfigurations  %u\r\n", desc.device.bNumConfigurations);
+}
+
+// Invoked when device is unmounted (bus reset/unplugged)
+void tuh_umount_cb(uint8_t daddr) {
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+  printf("Device removed, address = %d\r\n", daddr);
+}
+
+//--------------------------------------------------------------------+
+// String Descriptor Helper
+//--------------------------------------------------------------------+
+
+static void _convert_utf16le_to_utf8(const uint16_t* utf16, size_t utf16_len, uint8_t* utf8, size_t utf8_len) {
+  // TODO: Check for runover.
+  (void) utf8_len;
+  // Get the UTF-16 length out of the data itself.
+
+  for (size_t i = 0; i < utf16_len; i++) {
+    uint16_t chr = utf16[i];
+    if (chr < 0x80) {
+      *utf8++ = chr & 0xffu;
+    } else if (chr < 0x800) {
+      *utf8++ = (uint8_t) (0xC0 | (chr >> 6 & 0x1F));
+      *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F));
+    } else {
+      // TODO: Verify surrogate.
+      *utf8++ = (uint8_t) (0xE0 | (chr >> 12 & 0x0F));
+      *utf8++ = (uint8_t) (0x80 | (chr >> 6 & 0x3F));
+      *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F));
+    }
+    // TODO: Handle UTF-16 code points that take two entries.
+  }
+}
+
+// Count how many bytes a utf-16-le encoded string will take in utf-8.
+static int _count_utf8_bytes(const uint16_t* buf, size_t len) {
+  size_t total_bytes = 0;
+  for (size_t i = 0; i < len; i++) {
+    uint16_t chr = buf[i];
+    if (chr < 0x80) {
+      total_bytes += 1;
+    } else if (chr < 0x800) {
+      total_bytes += 2;
+    } else {
+      total_bytes += 3;
+    }
+    // TODO: Handle UTF-16 code points that take two entries.
+  }
+  return (int) total_bytes;
+}
+
+static void print_utf16(uint16_t* temp_buf, size_t buf_len) {
+  if ((temp_buf[0] & 0xff) == 0) return;  // empty
+  size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
+  size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
+  _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t*) temp_buf, sizeof(uint16_t) * buf_len);
+  ((uint8_t*) temp_buf)[utf8_len] = '\0';
+
+  printf("%s", (char*) temp_buf);
+}
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void* param) {
+  (void) param;
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  while (1) {
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+#else
+    if (board_millis() - start_ms < blink_interval_ms) {
+      return; // not enough time
+    }
+#endif
+
+    start_ms += blink_interval_ms;
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
+}
+
+//--------------------------------------------------------------------+
+// FreeRTOS
+//--------------------------------------------------------------------+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+  #define USB_STACK_SIZE     4096
+#else
+  // Increase stack size when debug log is enabled
+  #define USB_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t  usb_stack[USB_STACK_SIZE];
+StaticTask_t usb_taskdef;
+#endif
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+void app_main(void) {
+  main();
+}
+#endif
+
+void usb_host_task(void *param) {
+  (void) param;
+  init_tinyusb();
+  while (1) {
+    tuh_task();
+  }
+}
+
+void init_freertos_task(void) {
+#if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+  xTaskCreateStatic(usb_host_task, "usbh", USB_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_stack, &usb_taskdef);
+#else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_host_task, "usbh", USB_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+#endif
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+#if !TUSB_MCU_VENDOR_ESPRESSIF
+  vTaskStartScheduler();
+#endif
+}
+
+#endif
diff --git a/examples/host/device_info/src/tusb_config.h b/examples/host/device_info/src/tusb_config.h
new file mode 100644
index 000000000..5190b5b1f
--- /dev/null
+++ b/examples/host/device_info/src/tusb_config.h
@@ -0,0 +1,120 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef TUSB_CONFIG_H_
+#define TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TUSB_MCU_VENDOR_ESPRESSIF
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Driver Configuration
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+// only hub class is enabled
+#define CFG_TUH_HUB                 1
+
+// max device support (excluding hub device)
+// 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index 6153d399a..fb5faf210 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -1,31 +1,33 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
-
-# For rp2040, un-comment to enable pico-pio-usb
-# family_add_pico_pio_usb(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index e7fbd741f..1377f1f90 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 INC += \
 	src \
@@ -12,14 +11,4 @@ EXAMPLE_SOURCE += \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index fa9c14857..95f9f1d82 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -1,11 +1,17 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
+mcu:STM32F4
+mcu:STM32F7
+mcu:STM32H7
diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index 75c91400e..6ffe0b6d4 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* From https://www.kernel.org/doc/html/latest/input/gamepad.html
@@ -91,9 +91,8 @@ typedef struct TU_ATTR_PACKED
     uint8_t counter : 6; // +1 each report
   };
 
-  // comment out since not used by this example
-  // uint8_t l2_trigger; // 0 released, 0xff fully pressed
-  // uint8_t r2_trigger; // as above
+  uint8_t l2_trigger; // 0 released, 0xff fully pressed
+  uint8_t r2_trigger; // as above
 
   //  uint16_t timestamp;
   //  uint8_t  battery;
@@ -105,15 +104,54 @@ typedef struct TU_ATTR_PACKED
 
 } sony_ds4_report_t;
 
+typedef struct TU_ATTR_PACKED {
+  // First 16 bits set what data is pertinent in this structure (1 = set; 0 = not set)
+  uint8_t set_rumble : 1;
+  uint8_t set_led : 1;
+  uint8_t set_led_blink : 1;
+  uint8_t set_ext_write : 1;
+  uint8_t set_left_volume : 1;
+  uint8_t set_right_volume : 1;
+  uint8_t set_mic_volume : 1;
+  uint8_t set_speaker_volume : 1;
+  uint8_t set_flags2;
+
+  uint8_t reserved;
+
+  uint8_t motor_right;
+  uint8_t motor_left;
+
+  uint8_t lightbar_red;
+  uint8_t lightbar_green;
+  uint8_t lightbar_blue;
+  uint8_t lightbar_blink_on;
+  uint8_t lightbar_blink_off;
+
+  uint8_t ext_data[8];
+
+  uint8_t volume_left;
+  uint8_t volume_right;
+  uint8_t volume_mic;
+  uint8_t volume_speaker;
+
+  uint8_t other[9];
+} sony_ds4_output_report_t;
+
+static bool ds4_mounted = false;
+static uint8_t ds4_dev_addr = 0;
+static uint8_t ds4_instance = 0;
+static uint8_t motor_left = 0;
+static uint8_t motor_right = 0;
+
 // check if device is Sony DualShock 4
 static inline bool is_sony_ds4(uint8_t dev_addr)
 {
   uint16_t vid, pid;
   tuh_vid_pid_get(dev_addr, &vid, &pid);
 
-  return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 
-           || (vid == 0x0f0d && pid == 0x005e)                 // Hori FC4 
-           || (vid == 0x0f0d && pid == 0x00ee)                 // Hori PS4 Mini (PS4-099U) 
+  return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4
+           || (vid == 0x0f0d && pid == 0x005e)                 // Hori FC4
+           || (vid == 0x0f0d && pid == 0x00ee)                 // Hori PS4 Mini (PS4-099U)
            || (vid == 0x1f4f && pid == 0x1002)                 // ASW GG xrd controller
          );
 }
@@ -124,7 +162,23 @@ static inline bool is_sony_ds4(uint8_t dev_addr)
 
 void hid_app_task(void)
 {
-  // nothing to do
+  if (ds4_mounted)
+  {
+    const uint32_t interval_ms = 200;
+    static uint32_t start_ms = 0;
+
+    uint32_t current_time_ms = board_millis();
+    if ( current_time_ms - start_ms >= interval_ms)
+    {
+      start_ms = current_time_ms;
+
+      sony_ds4_output_report_t output_report = {0};
+      output_report.set_rumble = 1;
+      output_report.motor_left = motor_left;
+      output_report.motor_right = motor_right;
+      tuh_hid_send_report(ds4_dev_addr, ds4_instance, 5, &output_report, sizeof(output_report));
+    }
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -149,6 +203,14 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
   // Sony DualShock 4 [CUH-ZCT2x]
   if ( is_sony_ds4(dev_addr) )
   {
+    if (!ds4_mounted)
+    {
+      ds4_dev_addr = dev_addr;
+      ds4_instance = instance;
+      motor_left = 0;
+      motor_right = 0;
+      ds4_mounted = true;
+    }
     // request to receive report
     // tuh_hid_report_received_cb() will be invoked when report is available
     if ( !tuh_hid_receive_report(dev_addr, instance) )
@@ -162,6 +224,10 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
 void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 {
   printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+  if (ds4_mounted && ds4_dev_addr == dev_addr && ds4_instance == instance)
+  {
+    ds4_mounted = false;
+  }
 }
 
 // check if different than 2
@@ -179,14 +245,15 @@ bool diff_report(sony_ds4_report_t const* rpt1, sony_ds4_report_t const* rpt2)
   result = diff_than_2(rpt1->x, rpt2->x) || diff_than_2(rpt1->y , rpt2->y ) ||
            diff_than_2(rpt1->z, rpt2->z) || diff_than_2(rpt1->rz, rpt2->rz);
 
-  // check the reset with mem compare
-  result |= memcmp(&rpt1->rz + 1, &rpt2->rz + 1, sizeof(sony_ds4_report_t)-4);
+  // check the rest with mem compare
+  result |= memcmp(&rpt1->rz + 1, &rpt2->rz + 1, sizeof(sony_ds4_report_t)-6);
 
   return result;
 }
 
 void process_sony_ds4(uint8_t const* report, uint16_t len)
 {
+  (void)len;
   const char* dpad_str[] = { "N", "NE", "E", "SE", "S", "SW", "W", "NW", "none" };
 
   // previous report used to compare for changes
@@ -234,6 +301,10 @@ void process_sony_ds4(uint8_t const* report, uint16_t len)
       printf("\r\n");
     }
 
+    // The left and right triggers control the intensity of the left and right rumble motors
+    motor_left = ds4_report.l2_trigger;
+    motor_right = ds4_report.r2_trigger;
+
     prev_report = ds4_report;
   }
 }
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index 299a3ff10..ba12774bd 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -32,7 +32,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
@@ -52,7 +52,15 @@ int main(void)
   printf("Note: Events only displayed for explicit supported controllers\r\n");
 
   // init host stack on configured roothub port
-  tuh_init(BOARD_TUH_RHPORT);
+  tusb_rhport_init_t host_init = {
+    .role = TUSB_ROLE_HOST,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUH_RHPORT, &host_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
   while (1)
   {
@@ -68,8 +76,6 @@ int main(void)
     hid_app_task();
 #endif
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index 475b9ca8f..3ac591d8f 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -30,22 +30,8 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Board Specific Configuration
-//--------------------------------------------------------------------+
-
-// RHPort number used for host can be defined by board.mk, default to port 0
-#ifndef BOARD_TUH_RHPORT
-#define BOARD_TUH_RHPORT      0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUH_MAX_SPEED
-#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
@@ -61,12 +47,6 @@
 #define CFG_TUSB_DEBUG        0
 #endif
 
-// Enable Host stack
-#define CFG_TUH_ENABLED       1
-
-// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -74,16 +54,48 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
-// CONFIGURATION
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Driver Configuration
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
@@ -91,13 +103,12 @@
 
 #define CFG_TUH_HUB                 0
 #define CFG_TUH_CDC                 0
-#define CFG_TUH_HID                 4 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 0
 #define CFG_TUH_VENDOR              0
 
-// max device support (excluding hub device)
-// 1 hub typically has 4 ports
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
 
 //------------- HID -------------//
 
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 5d443ea9b..5ac75c04a 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -1,48 +1,47 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.20)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
-        ${TOP}/lib/fatfs/source/ff.c
-        ${TOP}/lib/fatfs/source/ffsystem.c
-        ${TOP}/lib/fatfs/source/ffunicode.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+  ${TOP}/lib/fatfs/source/ff.c
+  ${TOP}/lib/fatfs/source/ffsystem.c
+  ${TOP}/lib/fatfs/source/ffunicode.c
+  )
+
+# Suppress warnings on fatfs
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+  set_source_files_properties(
+    ${TOP}/lib/fatfs/source/ff.c
+    PROPERTIES
+    COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual"
+    )
+endif ()
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        ${TOP}/lib/fatfs/source
-        ${TOP}/lib/embedded-cli
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  ${TOP}/lib/fatfs/source
+  ${TOP}/lib/embedded-cli
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
-
-# For rp2040, un-comment to enable pico-pio-usb
-family_add_pico_pio_usb(${PROJECT})
-
-# due to warnings from Pico-PIO-USB and fatfs
-target_compile_options(${PROJECT} PUBLIC
-        -Wno-error=shadow
-        -Wno-error=cast-align
-        -Wno-error=cast-qual
-        -Wno-error=redundant-decls
-        -Wno-error=sign-conversion
-        -Wno-error=conversion
-        -Wno-error=sign-compare
-        -Wno-error=unused-function
-        )
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile
index de2f9c01c..c7d6a7cae 100644
--- a/examples/host/msc_file_explorer/Makefile
+++ b/examples/host/msc_file_explorer/Makefile
@@ -1,5 +1,4 @@
-include ../../../tools/top.mk
-include ../../make.mk
+include ../../build_system/make/make.mk
 
 FATFS_PATH = lib/fatfs/source
 
@@ -25,14 +24,4 @@ SRC_C += \
 # suppress warning caused by fatfs
 CFLAGS += -Wno-error=cast-qual
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
-include ../../rules.mk
+include ../../build_system/make/rules.mk
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
index fa9c14857..95f9f1d82 100644
--- a/examples/host/msc_file_explorer/only.txt
+++ b/examples/host/msc_file_explorer/only.txt
@@ -1,11 +1,17 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
+mcu:STM32F4
+mcu:STM32F7
+mcu:STM32H7
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index ab2cfd498..8197c3c8d 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,35 +23,72 @@
  *
  */
 
+/* Example to show how to navigate mass storage device with built-in command line.
+ * Type help for list of supported commands and syntax (mostly linux commands)
+
+ > help
+ * help
+        Print list of commands
+ * cat
+        Usage: cat [FILE]...
+        Concatenate FILE(s) to standard output..
+ * cd
+        Usage: cd [DIR]...
+        Change the current directory to DIR.
+ * cp
+        Usage: cp SOURCE DEST
+        Copy SOURCE to DEST.
+ * ls
+        Usage: ls [DIR]...
+        List information about the FILEs (the current directory by default).
+ * pwd
+        Usage: pwd
+        Print the name of the current working directory.
+ * mkdir
+        Usage: mkdir DIR...
+        Create the DIRECTORY(ies), if they do not already exist..
+ * mv
+        Usage: mv SOURCE DEST...
+        Rename SOURCE to DEST.
+ * rm
+        Usage: rm [FILE]...
+        Remove (unlink) the FILE(s).
+ */
+
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
+#include "msc_app.h"
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
 void led_blinking_task(void);
 
-// from msc_app.c
-extern bool msc_app_init(void);
-extern void msc_app_task(void);
-
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   printf("TinyUSB Host MassStorage Explorer Example\r\n");
 
   // init host stack on configured roothub port
-  tuh_init(BOARD_TUH_RHPORT);
+  tusb_rhport_init_t host_init = {
+    .role = TUSB_ROLE_HOST,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_TUH_RHPORT, &host_init);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   msc_app_init();
 
-  while (1)
-  {
+  while (1) {
     // tinyusb host task
     tuh_task();
 
@@ -66,28 +103,25 @@ int main(void)
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
 
-void tuh_mount_cb(uint8_t dev_addr)
-{
+void tuh_mount_cb(uint8_t dev_addr) {
   (void) dev_addr;
 }
 
-void tuh_umount_cb(uint8_t dev_addr)
-{
+void tuh_umount_cb(uint8_t dev_addr) {
   (void) dev_addr;
 }
 
 //--------------------------------------------------------------------+
 // Blinking Task
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
   const uint32_t interval_ms = 1000;
   static uint32_t start_ms = 0;
 
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  if (board_millis() - start_ms < interval_ms) return; // not enough time
   start_ms += interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index aa193f3ce..226c870ea 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
 
 #include <ctype.h>
 #include "tusb.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include "ff.h"
 #include "diskio.h"
@@ -53,7 +53,11 @@ static CLI_UINT cli_buffer[BYTES_TO_CLI_UINTS(CLI_BUFFER_SIZE)];
 static FATFS fatfs[CFG_TUH_DEVICE_MAX]; // for simplicity only support 1 LUN per device
 static volatile bool _disk_busy[CFG_TUH_DEVICE_MAX];
 
-static scsi_inquiry_resp_t inquiry_resp;
+// define the buffer to be place in USB/DMA memory with correct alignment/cache line size
+CFG_TUH_MEM_SECTION static struct {
+  TUH_EPBUF_TYPE_DEF(scsi_inquiry_resp_t, inquiry);
+} scsi_resp;
+
 
 //--------------------------------------------------------------------+
 //
@@ -63,10 +67,15 @@ bool cli_init(void);
 
 bool msc_app_init(void)
 {
-  for(size_t i=0; i<CFG_TUH_DEVICE_MAX; i++) _disk_busy[i] = false;
+  for(size_t i=0; i<CFG_TUH_DEVICE_MAX; i++) {
+    _disk_busy[i] = false;
+  }
 
   // disable stdout buffered for echoing typing command
+  #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
   setbuf(stdout, NULL);
+  #endif
+
   cli_init();
 
   return true;
@@ -74,7 +83,9 @@ bool msc_app_init(void)
 
 void msc_app_task(void)
 {
-  if (!_cli) return;
+  if (!_cli) {
+    return;
+  }
 
   int ch = board_getchar();
   if ( ch > 0 )
@@ -92,9 +103,10 @@ void msc_app_task(void)
 //
 //--------------------------------------------------------------------+
 
+static bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
 
-bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
-{
   if (csw->status != 0)
   {
     printf("Inquiry failed\r\n");
@@ -102,13 +114,13 @@ bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const
   }
 
   // Print out Vendor ID, Product ID and Rev
-  printf("%.8s %.16s rev %.4s\r\n", inquiry_resp.vendor_id, inquiry_resp.product_id, inquiry_resp.product_rev);
+  printf("%.8s %.16s rev %.4s\r\n", scsi_resp.inquiry.vendor_id, scsi_resp.inquiry.product_id, scsi_resp.inquiry.product_rev);
 
   // Get capacity of device
   uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
   uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
 
-  printf("Disk Size: %lu MB\r\n", block_count / ((1024*1024)/block_size));
+  printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024*1024)/block_size));
   // printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
 
   // For simplicity: we only mount 1 LUN per device
@@ -140,7 +152,7 @@ void tuh_msc_mount_cb(uint8_t dev_addr)
   printf("A MassStorage device is mounted\r\n");
 
   uint8_t const lun = 0;
-  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb);
+  tuh_msc_inquiry(dev_addr, lun, &scsi_resp.inquiry, inquiry_complete_cb, 0);
 }
 
 void tuh_msc_umount_cb(uint8_t dev_addr)
@@ -178,9 +190,9 @@ static void wait_for_disk_io(BYTE pdrv)
   }
 }
 
-static bool disk_io_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+static bool disk_io_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
 {
-  (void) dev_addr; (void) cbw; (void) csw;
+  (void) dev_addr; (void) cb_data;
   _disk_busy[dev_addr-1] = false;
   return true;
 }
@@ -212,7 +224,7 @@ DRESULT disk_read (
 	uint8_t const lun = 0;
 
 	_disk_busy[pdrv] = true;
-	tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete);
+	tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0);
 	wait_for_disk_io(pdrv);
 
 	return RES_OK;
@@ -231,7 +243,7 @@ DRESULT disk_write (
 	uint8_t const lun = 0;
 
 	_disk_busy[pdrv] = true;
-	tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete);
+	tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0);
 	wait_for_disk_io(pdrv);
 
 	return RES_OK;
@@ -285,18 +297,11 @@ void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context);
 
-void cli_write_char(EmbeddedCli *cli, char c)
-{
+static void cli_write_char(EmbeddedCli *cli, char c) {
   (void) cli;
   putchar((int) c);
 }
 
-void cli_cmd_unknown(EmbeddedCli *cli, CliCommand *command)
-{
-  (void) cli;
-  printf("%s: command not found\r\n", command->name);
-}
-
 bool cli_init(void)
 {
   EmbeddedCliConfig *config = embeddedCliDefaultConfig();
@@ -410,7 +415,7 @@ void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context)
       {
         for(UINT c = 0; c < count; c++)
         {
-          const char ch = buf[c];
+          const uint8_t ch = buf[c];
           if (isprint(ch) || iscntrl(ch))
           {
             putchar(ch);
@@ -535,10 +540,10 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
         printf("%-40s", fno.fname);
         if (fno.fsize < 1024)
         {
-          printf("%lu B\r\n", fno.fsize);
+          printf("%" PRIu32 " B\r\n", fno.fsize);
         }else
         {
-          printf("%lu KB\r\n", fno.fsize / 1024);
+          printf("%" PRIu32 " KB\r\n", fno.fsize / 1024);
         }
       }
     }
diff --git a/src/portable/mentor/musb/musb_msp432e.h b/examples/host/msc_file_explorer/src/msc_app.h
similarity index 85%
rename from src/portable/mentor/musb/musb_msp432e.h
rename to examples/host/msc_file_explorer/src/msc_app.h
index fce21de88..3ba03d0dc 100644
--- a/src/portable/mentor/musb/musb_msp432e.h
+++ b/examples/host/msc_file_explorer/src/msc_app.h
@@ -1,7 +1,7 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ * Copyright (c) 2025 Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -23,18 +23,13 @@
  *
  * This file is part of the TinyUSB stack.
  */
+#ifndef MSC_APP_H
+#define MSC_APP_H
 
-#ifndef _TUSB_MUSB_MSP432E_H_
-#define _TUSB_MUSB_MSP432E_H_
+#include <stdbool.h>
 
-#ifdef __cplusplus
- extern "C" {
-#endif
+bool msc_app_init(void);
+void msc_app_task(void);
 
-#include "msp.h"
-
-#ifdef __cplusplus
- }
-#endif
 
 #endif
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index ddf8368f4..c798b4383 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -30,28 +30,8 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Board Specific Configuration
-//--------------------------------------------------------------------+
-
-#if CFG_TUSB_MCU == OPT_MCU_RP2040
-// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   0
-#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-#endif
-
-// RHPort number used for host can be defined by board.mk, default to port 0
-#ifndef BOARD_TUH_RHPORT
-#define BOARD_TUH_RHPORT      0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUH_MAX_SPEED
-#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
@@ -67,12 +47,6 @@
 #define CFG_TUSB_DEBUG        0
 #endif
 
-// Enable Host stack
-#define CFG_TUH_ENABLED       1
-
-// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -80,16 +54,48 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
-// CONFIGURATION
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Driver Configuration
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
@@ -101,8 +107,8 @@
 #define CFG_TUH_HID                 0 // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_VENDOR              0
 
-// max device support (excluding hub device)
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
 
 //------------- MSC -------------//
 #define CFG_TUH_MSC_MAXLUN    4 // typical for most card reader
diff --git a/examples/make.mk b/examples/make.mk
deleted file mode 100644
index 73a39a8fe..000000000
--- a/examples/make.mk
+++ /dev/null
@@ -1,140 +0,0 @@
-# ---------------------------------------
-# Common make definition for all examples
-# ---------------------------------------
-
-# Build directory
-BUILD := _build/$(BOARD)
-
-PROJECT := $(notdir $(CURDIR))
-BIN := $(TOP)/_bin/$(BOARD)/$(notdir $(CURDIR))
-
-# Handy check parameter function
-check_defined = \
-    $(strip $(foreach 1,$1, \
-    $(call __check_defined,$1,$(strip $(value 2)))))
-__check_defined = \
-    $(if $(value $1),, \
-    $(error Undefined make flag: $1$(if $2, ($2))))
-
-#-------------- Select the board to build for. ------------
-
-# Board without family
-ifneq ($(wildcard $(TOP)/hw/bsp/$(BOARD)/board.mk),)
-BOARD_PATH := hw/bsp/$(BOARD)
-FAMILY :=
-endif
-
-# Board within family
-ifeq ($(BOARD_PATH),)
-  BOARD_PATH := $(subst $(TOP)/,,$(wildcard $(TOP)/hw/bsp/*/boards/$(BOARD)))
-  FAMILY := $(word 3, $(subst /, ,$(BOARD_PATH)))
-  FAMILY_PATH = hw/bsp/$(FAMILY)
-endif
-
-ifeq ($(BOARD_PATH),)
-  $(info You must provide a BOARD parameter with 'BOARD=')
-  $(error Invalid BOARD specified)
-endif
-
-ifeq ($(FAMILY),)
-  include $(TOP)/hw/bsp/$(BOARD)/board.mk
-else
-  # Include Family and Board specific defs
-  include $(TOP)/$(FAMILY_PATH)/family.mk
-
-  SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(FAMILY_PATH)/*.c))
-endif
-
-
-#-------------- Cross Compiler  ------------
-# Can be set by board, default to ARM GCC
-CROSS_COMPILE ?= arm-none-eabi-
-# Allow for -Os to be changed by board makefiles in case -Os is not allowed
-CFLAGS_OPTIMIZED ?= -Os
-
-CC = $(CROSS_COMPILE)gcc
-CXX = $(CROSS_COMPILE)g++
-GDB = $(CROSS_COMPILE)gdb
-OBJCOPY = $(CROSS_COMPILE)objcopy
-SIZE = $(CROSS_COMPILE)size
-MKDIR = mkdir
-
-ifeq ($(CMDEXE),1)
-  CP = copy
-  RM = del
-  PYTHON = python
-else
-  SED = sed
-  CP = cp
-  RM = rm
-  PYTHON = python3
-endif
-
-#-------------- Source files and compiler flags --------------
-
-# Include all source C in family & board folder
-SRC_C += hw/bsp/board.c
-SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(BOARD_PATH)/*.c))
-
-INC   += $(TOP)/$(FAMILY_PATH)
-
-# Compiler Flags
-CFLAGS += \
-  -ggdb \
-  -fdata-sections \
-  -ffunction-sections \
-  -fsingle-precision-constant \
-  -fno-strict-aliasing \
-  -Wall \
-  -Wextra \
-  -Werror \
-  -Wfatal-errors \
-  -Wdouble-promotion \
-  -Wstrict-prototypes \
-  -Wstrict-overflow \
-  -Werror-implicit-function-declaration \
-  -Wfloat-equal \
-  -Wundef \
-  -Wshadow \
-  -Wwrite-strings \
-  -Wsign-compare \
-  -Wmissing-format-attribute \
-  -Wunreachable-code \
-  -Wcast-align \
-  -Wcast-function-type \
-  -Wcast-qual \
-  -Wnull-dereference \
-  -Wuninitialized \
-  -Wunused \
-  -Wredundant-decls
-
-# conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion
-#  -Wconversion
-  
-# Debugging/Optimization
-ifeq ($(DEBUG), 1)
-  CFLAGS += -O0
-  NO_LTO = 1
-else
-  CFLAGS += $(CFLAGS_OPTIMIZED)
-endif
-
-# Log level is mapped to TUSB DEBUG option
-ifneq ($(LOG),)
-  CMAKE_DEFSYM +=	-DLOG=$(LOG)
-  CFLAGS += -DCFG_TUSB_DEBUG=$(LOG)
-endif
-
-# Logger: default is uart, can be set to rtt or swo
-ifneq ($(LOGGER),)
-	CMAKE_DEFSYM +=	-DLOGGER=$(LOGGER)
-endif
-
-ifeq ($(LOGGER),rtt)
-  CFLAGS += -DLOGGER_RTT -DSEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
-  RTT_SRC = lib/SEGGER_RTT
-  INC   += $(TOP)/$(RTT_SRC)/RTT
-  SRC_C += $(RTT_SRC)/RTT/SEGGER_RTT.c
-else ifeq ($(LOGGER),swo)
-  CFLAGS += -DLOGGER_SWO
-endif
diff --git a/examples/typec/CMakeLists.txt b/examples/typec/CMakeLists.txt
new file mode 100644
index 000000000..24c25908a
--- /dev/null
+++ b/examples/typec/CMakeLists.txt
@@ -0,0 +1,9 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
+
+project(tinyusb_host_examples C CXX ASM)
+family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
+
+# family_add_subdirectory will filter what to actually add based on selected FAMILY
+family_add_subdirectory(power_delivery)
diff --git a/examples/typec/power_delivery/CMakeLists.txt b/examples/typec/power_delivery/CMakeLists.txt
new file mode 100644
index 000000000..837b4996a
--- /dev/null
+++ b/examples/typec/power_delivery/CMakeLists.txt
@@ -0,0 +1,32 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/typec/power_delivery/Makefile b/examples/typec/power_delivery/Makefile
new file mode 100644
index 000000000..7fa475da5
--- /dev/null
+++ b/examples/typec/power_delivery/Makefile
@@ -0,0 +1,11 @@
+include ../../build_system/make/make.mk
+
+INC += \
+  src \
+  $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/typec/power_delivery/only.txt b/examples/typec/power_delivery/only.txt
new file mode 100644
index 000000000..657aeaac5
--- /dev/null
+++ b/examples/typec/power_delivery/only.txt
@@ -0,0 +1 @@
+mcu:STM32G4
diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
new file mode 100644
index 000000000..068dbbeb1
--- /dev/null
+++ b/examples/typec/power_delivery/src/main.c
@@ -0,0 +1,193 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+
+// Voltage and current for selecting PDO
+// DANGEROUS: Please make sure your board can withstand the voltage and current
+// defined here. Otherwise, you may damage your board, smoke can come out
+#define VOLTAGE_MAX_MV       5000 // maximum voltage in mV
+#define CURRENT_MAX_MA       500  // maximum current in mA
+#define CURRENT_OPERATING_MA 100  // operating current in mA
+
+/* Blink pattern
+ * - 250 ms  : button is not pressed
+ * - 1000 ms : button is pressed (and hold)
+ */
+enum  {
+  BLINK_PRESSED = 250,
+  BLINK_UNPRESSED = 1000
+};
+
+static uint32_t blink_interval_ms = BLINK_UNPRESSED;
+
+void led_blinking_task(void);
+
+#define HELLO_STR   "Hello from TinyUSB\r\n"
+
+int main(void)
+{
+  board_init();
+  board_led_write(true);
+
+  tuc_init(0, TUSB_TYPEC_PORT_SNK);
+
+  while (1) {
+    led_blinking_task();
+
+    // tinyusb typec task
+    tuc_task();
+  }
+}
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+void app_main(void)
+{
+  main();
+}
+#endif
+
+//--------------------------------------------------------------------+
+// TypeC PD callbacks
+//--------------------------------------------------------------------+
+
+bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end) {
+  switch (header->msg_type) {
+    case PD_DATA_SOURCE_CAP: {
+      printf("PD Source Capabilities\r\n");
+      // Examine source capability and select a suitable PDO (starting from 1 with safe5v)
+      uint8_t selected_pos = 1;
+
+      for(size_t i=0; i<header->n_data_obj; i++) {
+        TU_VERIFY(dobj < p_end);
+        uint32_t const pdo = tu_le32toh(tu_unaligned_read32(dobj));
+
+        switch ((pdo >> 30) & 0x03ul) {
+          case PD_PDO_TYPE_FIXED: {
+            pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo;
+            uint32_t const voltage_mv = fixed->voltage_50mv*50;
+            uint32_t const current_ma = fixed->current_max_10ma*10;
+            printf("[Fixed] %"PRIu32" mV %"PRIu32" mA\r\n", voltage_mv, current_ma);
+
+            if (voltage_mv <= VOLTAGE_MAX_MV && current_ma >= CURRENT_MAX_MA) {
+              // Found a suitable PDO
+              selected_pos = i+1;
+            }
+
+            break;
+          }
+
+          case PD_PDO_TYPE_BATTERY:
+            break;
+
+          case PD_PDO_TYPE_VARIABLE:
+            break;
+
+          case PD_PDO_TYPE_APDO:
+            break;
+        }
+
+        dobj += 4;
+      }
+
+      //------------- Response with selected PDO -------------//
+      // Be careful and make sure your board can withstand the selected PDO
+      // voltage other than safe5v e.g 12v or 20v
+
+      printf("Selected PDO %u\r\n", selected_pos);
+
+      // Send request with selected PDO position as response to Source Cap
+      pd_rdo_fixed_variable_t rdo = {
+          .current_extremum_10ma = 50, // max 500mA
+          .current_operate_10ma = 30, // 300mA
+          .reserved = 0,
+          .epr_mode_capable = 0,
+          .unchunked_ext_msg_support = 0,
+          .no_usb_suspend = 0,
+          .usb_comm_capable = 1,
+          .capability_mismatch = 0,
+          .give_back_flag = 0, // exteremum is max
+          .object_position = selected_pos,
+      };
+      tuc_msg_request(rhport, &rdo);
+
+      break;
+    }
+
+    default: break;
+  }
+
+  return true;
+}
+
+bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header) {
+  (void) rhport;
+  switch (header->msg_type) {
+    case PD_CTRL_ACCEPT:
+      printf("PD Request Accepted\r\n");
+      // preparing for power transition
+      break;
+
+    case PD_CTRL_REJECT:
+      printf("PD Request Rejected\r\n");
+      // try to negotiate further power
+      break;
+
+    case PD_CTRL_PS_READY:
+      printf("PD Power Ready\r\n");
+      // Source is ready to supply power
+      break;
+
+    default:
+      break;
+  }
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/typec/power_delivery/src/tusb_config.h b/examples/typec/power_delivery/src/tusb_config.h
new file mode 100644
index 000000000..f7cb3cc04
--- /dev/null
+++ b/examples/typec/power_delivery/src/tusb_config.h
@@ -0,0 +1,83 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+  #error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+  #define CFG_TUSB_OS               OPT_OS_NONE
+#endif
+
+#define CFG_TUD_ENABLED   0
+#define CFG_TUH_ENABLED   0
+
+// Enable TYPEC stack
+#define CFG_TUC_ENABLED   1
+
+
+// special example that doesn't enable device or host stack
+// This can cause some TinyUSB API missing, this define hack to allow us to fill those API
+// to pass the compilation process
+#if CFG_TUD_ENABLED == 0
+#define tud_int_handler(x)
+#endif
+
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/west.yml b/examples/west.yml
new file mode 100644
index 000000000..0683f6861
--- /dev/null
+++ b/examples/west.yml
@@ -0,0 +1,12 @@
+manifest:
+  remotes:
+    - name: zephyrproject-rtos
+      url-base: https://github.com/zephyrproject-rtos
+  projects:
+    - name: zephyr
+      remote: zephyrproject-rtos
+      revision: main
+      path: zephyr
+      import: true
+  self:
+    path: .
diff --git a/hw/bsp/ansi_escape.h b/hw/bsp/ansi_escape.h
index 35342cfe5..15af2f3ab 100644
--- a/hw/bsp/ansi_escape.h
+++ b/hw/bsp/ansi_escape.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
  */
 
 /** \ingroup group_board
- *  \defgroup group_ansi_esc ANSI Esacpe Code
+ *  \defgroup group_ansi_esc ANSI Escape Code
  *  @{ */
 
 #ifndef _TUSB_ANSI_ESC_CODE_H_
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 7e96735bd..0e0fa4ac6 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -23,62 +23,15 @@
  *
  */
 
-#include "board.h"
-
-#if 0
-#define LED_PHASE_MAX   8
-
-static struct
-{
-  uint32_t phase[LED_PHASE_MAX];
-  uint8_t phase_count;
-
-  bool led_state;
-  uint8_t current_phase;
-  uint32_t current_ms;
-}led_pattern;
-
-void board_led_pattern(uint32_t const phase_ms[], uint8_t count)
-{
-  memcpy(led_pattern.phase, phase_ms, 4*count);
-  led_pattern.phase_count = count;
-
-  // reset with 1st phase is on
-  led_pattern.current_ms = board_millis();
-  led_pattern.current_phase = 0;
-  led_pattern.led_state = true;
-  board_led_on();
-}
-
-void board_led_task(void)
-{
-  if ( led_pattern.phase_count == 0 ) return;
-
-  uint32_t const duration = led_pattern.phase[led_pattern.current_phase];
-
-  // return if not enough time
-  if (board_millis() - led_pattern.current_ms < duration) return;
-
-  led_pattern.led_state = !led_pattern.led_state;
-  board_led_write(led_pattern.led_state);
-
-  led_pattern.current_ms += duration;
-  led_pattern.current_phase++;
-
-  if (led_pattern.current_phase == led_pattern.phase_count)
-  {
-    led_pattern.current_phase = 0;
-    led_pattern.led_state = true;
-    board_led_on();
-  }
-}
-#endif
+#include "board_api.h"
 
 //--------------------------------------------------------------------+
 // newlib read()/write() retarget
 //--------------------------------------------------------------------+
-
-#if defined(__MSP430__) || defined(__RX__)
+#ifdef __ICCARM__
+  #define sys_write   __write
+  #define sys_read    __read
+#elif defined(__MSP430__) || defined(__RX__)
   #define sys_write   write
   #define sys_read    read
 #else
@@ -86,6 +39,9 @@ void board_led_task(void)
   #define sys_read    _read
 #endif
 
+int sys_write(int fhdl, const char *buf, size_t count) TU_ATTR_USED;
+int sys_read(int fhdl, char *buf, size_t count) TU_ATTR_USED;
+
 #if defined(LOGGER_RTT)
 // Logging with RTT
 
@@ -93,15 +49,13 @@ void board_led_task(void)
 #if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM)
 #include "SEGGER_RTT.h"
 
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+int sys_write(int fhdl, const char *buf, size_t count) {
   (void) fhdl;
-  SEGGER_RTT_Write(0, (const char*) buf, (int) count);
-  return count;
+  SEGGER_RTT_Write(0, (const char *) buf, (int) count);
+  return (int) count;
 }
 
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+int sys_read(int fhdl, char *buf, size_t count) {
   (void) fhdl;
   int rd = (int) SEGGER_RTT_Read(0, buf, count);
   return (rd > 0) ? rd : -1;
@@ -110,23 +64,19 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 #endif
 
 #elif defined(LOGGER_SWO)
-// Logging with SWO for ARM Cortex
-
-#include "board_mcu.h"
-
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+// Logging with SWO for ARM Cortex-M
+int sys_write (int fhdl, const char *buf, size_t count) {
   (void) fhdl;
   uint8_t const* buf8 = (uint8_t const*) buf;
-  for(size_t i=0; i<count; i++)
-  {
+
+  for(size_t i=0; i<count; i++) {
     ITM_SendChar(buf8[i]);
   }
-  return count;
+
+  return (int) count;
 }
 
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+int sys_read (int fhdl, char *buf, size_t count) {
   (void) fhdl;
   (void) buf;
   (void) count;
@@ -136,14 +86,12 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 #else
 
 // Default logging with on-board UART
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+int sys_write (int fhdl, const char *buf, size_t count) {
   (void) fhdl;
   return board_uart_write(buf, (int) count);
 }
 
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+int sys_read (int fhdl, char *buf, size_t count) {
   (void) fhdl;
   int rd = board_uart_read((uint8_t*) buf, (int) count);
   return (rd > 0) ? rd : -1;
@@ -151,8 +99,132 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 
 #endif
 
-int board_getchar(void)
-{
-  char c;
-  return ( sys_read(0, &c, 1) > 0 ) ? (int) c : (-1);
+//int _close(int fhdl) {
+//  (void) fhdl;
+//  return 0;
+//}
+
+//int _fstat(int file, struct stat *st) {
+//  memset(st, 0, sizeof(*st));
+//  st->st_mode = S_IFCHR;
+//}
+
+// Clang use picolibc
+#if defined(__clang__)
+static int cl_putc(char c, FILE *f) {
+  (void) f;
+  return sys_write(0, &c, 1);
 }
+
+static int cl_getc(FILE* f) {
+  (void) f;
+  char c;
+  return sys_read(0, &c, 1) > 0 ? c : -1;
+}
+
+static FILE __stdio = FDEV_SETUP_STREAM(cl_putc, cl_getc, NULL, _FDEV_SETUP_RW);
+FILE *const stdin = &__stdio;
+__strong_reference(stdin, stdout);
+__strong_reference(stdin, stderr);
+#endif
+
+//--------------------------------------------------------------------+
+// Board API
+//--------------------------------------------------------------------+
+int board_getchar(void) {
+  char c;
+  return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
+}
+
+
+uint32_t tusb_time_millis_api(void) {
+  return board_millis();
+}
+
+//--------------------------------------------------------------------
+// FreeRTOS hooks
+//--------------------------------------------------------------------
+#if CFG_TUSB_OS == OPT_OS_FREERTOS && !TUSB_MCU_VENDOR_ESPRESSIF
+#include "FreeRTOS.h"
+#include "task.h"
+
+void vApplicationMallocFailedHook(void) {
+  taskDISABLE_INTERRUPTS();
+  TU_ASSERT(false, );
+}
+
+void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) {
+  (void) pxTask;
+  (void) pcTaskName;
+
+  taskDISABLE_INTERRUPTS();
+  TU_ASSERT(false, );
+}
+
+/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+ * used by the Idle task. */
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) {
+  /* If the buffers to be provided to the Idle task are declared inside this
+   * function then they must be declared static - otherwise they will be allocated on
+   * the stack and so not exists after this function exits. */
+  static StaticTask_t xIdleTaskTCB;
+  static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+  /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
+    state will be stored. */
+  *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+  /* Pass out the array that will be used as the Idle task's stack. */
+  *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+  /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+    Note that, as the array is necessarily of type StackType_t,
+    configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+  *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+
+/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
+ * application must provide an implementation of vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Timer service task. */
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) {
+  /* If the buffers to be provided to the Timer task are declared inside this
+   * function then they must be declared static - otherwise they will be allocated on
+   * the stack and so not exists after this function exits. */
+  static StaticTask_t xTimerTaskTCB;
+  static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
+
+  /* Pass out a pointer to the StaticTask_t structure in which the Timer
+    task's state will be stored. */
+  *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+  /* Pass out the array that will be used as the Timer task's stack. */
+  *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+  /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+    Note that, as the array is necessarily of type StackType_t,
+    configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
+  *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
+
+#if CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
+#include "iodefine.h"
+void vApplicationSetupTimerInterrupt(void) {
+  /* Enable CMT0 */
+  unsigned short oldPRCR = SYSTEM.PRCR.WORD;
+  SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
+  MSTP(CMT0)       = 0;
+  SYSTEM.PRCR.WORD = (0xA5u<<8) | oldPRCR;
+
+  CMT0.CMCNT      = 0;
+  CMT0.CMCOR      = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
+  CMT0.CMCR.WORD  = TU_BIT(6) | 2;
+  IR(CMT0, CMI0)  = 0;
+  IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY;
+  IEN(CMT0, CMI0) = 1;
+  CMT.CMSTR0.BIT.STR0 = 1;
+}
+#endif
+
+
+#endif
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
deleted file mode 100644
index 0a10294d0..000000000
--- a/hw/bsp/board.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup group_demo
- * \defgroup group_board Boards Abstraction Layer
- *  @{ */
-
-#ifndef _BSP_BOARD_H_
-#define _BSP_BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "ansi_escape.h"
-#include "tusb.h"
-
-// Define the default baudrate
-#ifndef CFG_BOARD_UART_BAUDRATE
-#define CFG_BOARD_UART_BAUDRATE 115200   ///< Default baud rate
-#endif
-
-//--------------------------------------------------------------------+
-// Board Porting API
-// For simplicity, only one LED and one Button are used
-//--------------------------------------------------------------------+
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void);
-
-// Turn LED on or off
-void board_led_write(bool state);
-
-// Control led pattern using phase duration in ms.
-// For each phase, LED is toggle then repeated, board_led_task() is required to be called
-//void board_led_pattern(uint32_t const phase_ms[], uint8_t count);
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void);
-
-// Get characters from UART
-// Return number of read bytes
-int board_uart_read(uint8_t* buf, int len);
-
-// Send characters to UART
-// Return number of sent bytes
-int board_uart_write(void const * buf, int len);
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // Get current milliseconds, must be implemented when no RTOS is used
-  uint32_t board_millis(void);
-
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  static inline uint32_t board_millis(void)
-  {
-    return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ );
-  }
-
-#elif CFG_TUSB_OS == OPT_OS_MYNEWT
-  static inline uint32_t board_millis(void)
-  {
-    return os_time_ticks_to_ms32( os_time_get() );
-  }
-
-#elif CFG_TUSB_OS == OPT_OS_PICO
-  #include "pico/time.h"
-  static inline uint32_t board_millis(void)
-  {
-    return to_ms_since_boot(get_absolute_time());
-  }
-
-#elif CFG_TUSB_OS == OPT_OS_RTTHREAD
-  static inline uint32_t board_millis(void)
-  {
-    return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND);
-  }
-
-#else
-  #error "board_millis() is not implemented for this OS"
-#endif
-
-//--------------------------------------------------------------------+
-// Helper functions
-//--------------------------------------------------------------------+
-static inline void board_led_on(void)
-{
-  board_led_write(true);
-}
-
-static inline void board_led_off(void)
-{
-  board_led_write(false);
-}
-
-// TODO remove
-static inline void board_delay(uint32_t ms)
-{
-  uint32_t start_ms = board_millis();
-  while (board_millis() - start_ms < ms)
-  {
-    #if CFG_TUD_ENABLED
-    // take chance to run usb background
-    tud_task();
-    #endif
-  }
-}
-
-// stdio getchar() is blocking, this is non-blocking version
-int board_getchar(void);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _BSP_BOARD_H_ */
-
-/** @} */
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
new file mode 100644
index 000000000..9cdbbf0d3
--- /dev/null
+++ b/hw/bsp/board_api.h
@@ -0,0 +1,203 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_API_H_
+#define BOARD_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include "tusb.h"
+
+#if CFG_TUSB_OS == OPT_OS_ZEPHYR
+  #include <zephyr/kernel.h>
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  #if TUSB_MCU_VENDOR_ESPRESSIF
+    // ESP-IDF need "freertos/" prefix in include path.
+    // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+    #include "freertos/FreeRTOS.h"
+    #include "freertos/semphr.h"
+    #include "freertos/queue.h"
+    #include "freertos/task.h"
+    #include "freertos/timers.h"
+  #else
+    #include "FreeRTOS.h"
+    #include "semphr.h"
+    #include "queue.h"
+    #include "task.h"
+    #include "timers.h"
+  #endif
+#endif
+
+// Define the default baudrate
+#ifndef CFG_BOARD_UART_BAUDRATE
+#define CFG_BOARD_UART_BAUDRATE 115200   ///< Default baud rate
+#endif
+
+//--------------------------------------------------------------------+
+// Board Porting API
+// For simplicity, only one LED and one Button are used
+//--------------------------------------------------------------------+
+
+// Initialize on-board peripherals : led, button, uart and USB
+void board_init(void);
+
+// Init board after tinyusb is initialized
+void board_init_after_tusb(void) TU_ATTR_WEAK;
+
+// Jump to bootloader
+void board_reset_to_bootloader(void) TU_ATTR_WEAK;
+
+// Turn LED on or off
+void board_led_write(bool state);
+
+// Control led pattern using phase duration in ms.
+// For each phase, LED is toggle then repeated, board_led_task() is required to be called
+//void board_led_pattern(uint32_t const phase_ms[], uint8_t count);
+
+// Get the current state of button
+// a '1' means active (pressed), a '0' means inactive.
+uint32_t board_button_read(void);
+
+// Get board unique ID for USB serial number. Return number of bytes. Note max_len is typically 16
+TU_ATTR_WEAK size_t board_get_unique_id(uint8_t id[], size_t max_len);
+
+// Get characters from UART. Return number of read bytes
+int board_uart_read(uint8_t *buf, int len);
+
+// Send characters to UART. Return number of sent bytes
+int board_uart_write(void const *buf, int len);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+// Get current milliseconds, must be implemented when no RTOS is used
+uint32_t board_millis(void);
+
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+static inline uint32_t board_millis(void) {
+  return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ );
+}
+
+#elif CFG_TUSB_OS == OPT_OS_MYNEWT
+static inline uint32_t board_millis(void) {
+  return os_time_ticks_to_ms32( os_time_get() );
+}
+
+#elif CFG_TUSB_OS == OPT_OS_PICO
+#include "pico/time.h"
+static inline uint32_t board_millis(void) {
+  return to_ms_since_boot(get_absolute_time());
+}
+
+#elif CFG_TUSB_OS == OPT_OS_RTTHREAD
+static inline uint32_t board_millis(void) {
+  return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND);
+}
+
+#elif CFG_TUSB_OS == OPT_OS_CUSTOM
+// Implement your own board_millis() in any of .c file
+uint32_t board_millis(void);
+
+#elif CFG_TUSB_OS == OPT_OS_ZEPHYR
+static inline uint32_t board_millis(void) {
+  return k_uptime_get_32();
+}
+#else
+  #error "board_millis() is not implemented for this OS"
+#endif
+
+//--------------------------------------------------------------------+
+// Helper functions
+//--------------------------------------------------------------------+
+static inline void board_led_on(void) {
+  board_led_write(true);
+}
+
+static inline void board_led_off(void) {
+  board_led_write(false);
+}
+
+// Get USB Serial number string from unique ID if available. Return number of character.
+// Input is string descriptor from index 1 (index 0 is type + len)
+static inline size_t board_usb_get_serial(uint16_t desc_str1[], size_t max_chars) {
+  uint8_t uid[16] TU_ATTR_ALIGNED(4);
+  size_t uid_len;
+
+  // TODO work with make, but not working with esp32s3 cmake
+  if ( board_get_unique_id ) {
+    uid_len = board_get_unique_id(uid, sizeof(uid));
+  }else {
+    // fixed serial string is 01234567889ABCDEF
+    uint32_t* uid32 = (uint32_t*) (uintptr_t) uid;
+    uid32[0] = 0x67452301;
+    uid32[1] = 0xEFCDAB89;
+    uid_len = 8;
+  }
+
+  if ( uid_len > max_chars / 2 ) uid_len = max_chars / 2;
+
+  for ( size_t i = 0; i < uid_len; i++ ) {
+    for ( size_t j = 0; j < 2; j++ ) {
+      const char nibble_to_hex[16] = {
+          '0', '1', '2', '3', '4', '5', '6', '7',
+          '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
+      };
+      uint8_t const nibble = (uid[i] >> (j * 4)) & 0xf;
+      desc_str1[i * 2 + (1 - j)] = nibble_to_hex[nibble]; // UTF-16-LE
+    }
+  }
+
+  return 2 * uid_len;
+}
+
+// TODO remove
+static inline void board_delay(uint32_t ms) {
+  uint32_t start_ms = board_millis();
+  while ( board_millis() - start_ms < ms ) {
+    // take chance to run usb background
+    #if CFG_TUD_ENABLED
+    tud_task();
+    #endif
+
+    #if CFG_TUH_ENABLED
+    tuh_task();
+    #endif
+  }
+}
+
+// stdio getchar() is blocking, this is non-blocking version
+int board_getchar(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
deleted file mode 100644
index 18f071a22..000000000
--- a/hw/bsp/board_mcu.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_MCU_H_
-#define BOARD_MCU_H_
-
-#include "tusb_option.h"
-
-//--------------------------------------------------------------------+
-// Low Level MCU header include. Example should be
-// platform independent and mostly doesn't need to include this file.
-// However there are still certain situation where this file is needed:
-// - FreeRTOSConfig.h to set up correct clock and NVIC interrupts for ARM Cortex
-// - SWO logging for Cortex M with ITM_SendChar() / ITM_ReceiveChar()
-//--------------------------------------------------------------------+
-
-// Include order follows OPT_MCU_ number
-#if   CFG_TUSB_MCU == OPT_MCU_LPC11UXX   || CFG_TUSB_MCU == OPT_MCU_LPC13XX    || \
-      CFG_TUSB_MCU == OPT_MCU_LPC15XX    || CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || \
-      CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC18XX    || \
-      CFG_TUSB_MCU == OPT_MCU_LPC40XX    || CFG_TUSB_MCU == OPT_MCU_LPC43XX
-  #include "chip.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
-      CFG_TUSB_MCU == OPT_MCU_LPC55XX  || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX || \
-      CFG_TUSB_MCU == OPT_MCU_K32L2BXX
-  #include "fsl_device_registers.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
-  #include "nrf.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
-      CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
-      CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
-  #include "sam.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
-  #undef LITTLE_ENDIAN // hack to suppress "LITTLE_ENDIAN" redefined
-  #include "sam.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F0
-  #include "stm32f0xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
-  #include "stm32f1xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F2
-  #include "stm32f2xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
-  #include "stm32f3xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F4
-  #include "stm32f4xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
-  #include "stm32f7xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
-  #include "stm32g4xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32H7
-  #include "stm32h7xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
-  #include "stm32l0xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
-  #include "stm32l1xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
-  #include "stm32l4xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
-  #include "stm32wbxx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
-  #include "stm32u5xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_CXD56
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx
-  #include "msp430.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4
-  #include "msp.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  #include "fsl_device_registers.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_NUC120
-  #include "NUC100Series.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_NUC121 || CFG_TUSB_MCU == OPT_MCU_NUC126
-  #include "NuMicro.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_NUC505
-  #include "NUC505Series.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_ESP32S2
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_ESP32S3
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_DA1469X
-  #include "DA1469xAB.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_RP2040
-  #include "pico.h"
-  
-#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG
-  #include "em_device.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
-  #include "gd32vf103.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_MM32F327X
-  #include "mm32_device.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_XMC4000
-  #include "xmc_device.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_TM4C123
-  #include "TM4C123.h"
-
-#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
-  // no header needed
-
-#else
-  #error "Missing MCU header"
-#endif
-
-
-#endif /* BOARD_MCU_H_ */
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake
new file mode 100644
index 000000000..616a83fe2
--- /dev/null
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake
@@ -0,0 +1,8 @@
+set(CMAKE_SYSTEM_CPU arm1176jzf-s CACHE INTERNAL "System Processor")
+#set(SUFFIX "")
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    BCM_VERSION=2835
+    )
+endfunction()
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h
similarity index 92%
rename from hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
rename to hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h
index c7940c56e..40a9dd198 100644
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Raspberry Pi Zero
+   url: https://www.raspberrypi.org/products/raspberry-pi-zero/
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,11 +36,6 @@
  extern "C" {
 #endif
 
-#define NEOPIXEL_PIN          48
-
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk
new file mode 100644
index 000000000..7a248ed24
--- /dev/null
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk
@@ -0,0 +1,5 @@
+CPU_CORE = arm1176jzf-s
+CFLAGS += -DBCM_VERSION=2835 \
+          -DCFG_TUSB_MCU=OPT_MCU_BCM2835
+
+SUFFIX =
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
deleted file mode 100644
index 52e9e45c4..000000000
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-CFLAGS += -mcpu=arm1176jzf-s \
-          -DBCM_VERSION=2835 \
-          -DCFG_TUSB_MCU=OPT_MCU_BCM2835
-
-SUFFIX = 
diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c
index f7a11fb49..f8f3b0b70 100644
--- a/hw/bsp/broadcom_32bit/family.c
+++ b/hw/bsp/broadcom_32bit/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,9 +24,20 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+/* metadata:
+   manufacturer: Raspberry Pi
+*/
+
+#include "bsp/board_api.h"
 #include "board.h"
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
 #include "broadcom/cpu.h"
 #include "broadcom/gpio.h"
 #include "broadcom/interrupts.h"
@@ -34,6 +45,10 @@
 #include "broadcom/caches.h"
 #include "broadcom/vcmailbox.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 // LED
 #define LED_PIN               18
 #define LED_STATE_ON          1
@@ -44,8 +59,7 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -56,8 +70,7 @@ void USB_IRQHandler(void)
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
-void board_init(void)
-{
+void board_init(void) {
   setup_mmu_flat_map();
   init_caches();
 
@@ -97,24 +110,21 @@ void board_init(void)
   BP_EnableIRQs();
 }
 
-void board_led_write(bool state)
-{
-  gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return 0;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
   for (int i = 0; i < len; i++) {
     const char* cbuf = buf;
     while (!UART1->STAT_b.TX_READY) {}
@@ -127,30 +137,27 @@ int board_uart_write(void const * buf, int len)
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 
-void TIMER_1_IRQHandler(void)
-{
+void TIMER_1_IRQHandler(void) {
   system_ticks++;
   SYSTMR->C1 += 977;
   SYSTMR->CS_b.M1 = 1;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
   // asm("bkpt");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 
 }
diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake
new file mode 100644
index 000000000..5e57d8b1e
--- /dev/null
+++ b/hw/bsp/broadcom_32bit/family.cmake
@@ -0,0 +1,110 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/broadcom)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS BCM2835 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/broadcom/link.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  set(STARTUP_FILE_GNU ${SDK_DIR}/broadcom/boot.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/broadcom/gen/interrupt_handlers.c
+    ${SDK_DIR}/broadcom/gpio.c
+    ${SDK_DIR}/broadcom/interrupts.c
+    ${SDK_DIR}/broadcom/mmu.c
+    ${SDK_DIR}/broadcom/caches.c
+    ${SDK_DIR}/broadcom/vcmailbox.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC
+    -O0
+    -ffreestanding
+    -mgeneral-regs-only
+    -fno-exceptions
+    -std=c17
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      "LINKER:--entry=_start"
+      --specs=nosys.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      "LINKER:--entry=_start"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_BCM2835)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk
index cf68e21ee..a282e9961 100644
--- a/hw/bsp/broadcom_32bit/family.mk
+++ b/hw/bsp/broadcom_32bit/family.mk
@@ -1,5 +1,4 @@
 MCU_DIR = hw/mcu/broadcom
-DEPS_SUBMODULES += $(MCU_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
@@ -20,6 +19,8 @@ CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
 	$(MCU_DIR)/broadcom/gen/interrupt_handlers.c \
 	$(MCU_DIR)/broadcom/gpio.c \
 	$(MCU_DIR)/broadcom/interrupts.c \
@@ -27,15 +28,13 @@ SRC_C += \
 	$(MCU_DIR)/broadcom/caches.c \
 	$(MCU_DIR)/broadcom/vcmailbox.c
 
-SKIP_NANOLIB = 1
-
 LD_FILE = $(MCU_DIR)/broadcom/link$(SUFFIX).ld
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(MCU_DIR)
 
-SRC_S += $(MCU_DIR)/broadcom/boot$(SUFFIX).S
+SRC_S += $(MCU_DIR)/broadcom/boot$(SUFFIX).s
 
 $(BUILD)/kernel$(SUFFIX).img: $(BUILD)/$(PROJECT).elf
 	$(OBJCOPY) -O binary $^ $@
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake
new file mode 100644
index 000000000..6f1fc0225
--- /dev/null
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake
@@ -0,0 +1,5 @@
+set(CMAKE_SYSTEM_CPU cortex-a72 CACHE INTERNAL "System Processor")
+set(BCM_VERSION 2711)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
index 1d3565d5c..cadad2b27 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Raspberry CM4
+   url: https://www.raspberrypi.org/products/compute-module-4
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
index 5706b8318..702f10137 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
@@ -1,3 +1,3 @@
-CFLAGS += -mcpu=cortex-a72 \
-          -DBCM_VERSION=2711 \
+CPU_CORE = cortex-a72
+CFLAGS += -DBCM_VERSION=2711 \
           -DCFG_TUSB_MCU=OPT_MCU_BCM2711
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake
new file mode 100644
index 000000000..80747363a
--- /dev/null
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake
@@ -0,0 +1,5 @@
+set(CMAKE_SYSTEM_CPU cortex-a53 CACHE INTERNAL "System Processor")
+set(BCM_VERSION 2837)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h
similarity index 92%
rename from hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
rename to hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h
index 49a2474bc..e6caa0294 100644
--- a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Raspberry Zero2
+   url: https://www.raspberrypi.org/products/raspberry-pi-zero-2-w
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,11 +36,6 @@
  extern "C" {
 #endif
 
-#define NEOPIXEL_PIN          45
-
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.mk
new file mode 100644
index 000000000..da3fe17bc
--- /dev/null
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.mk
@@ -0,0 +1,3 @@
+CPU_CORE = cortex-a53
+CFLAGS += -DBCM_VERSION=2837 \
+          -DCFG_TUSB_MCU=OPT_MCU_BCM2837
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
deleted file mode 100644
index 3060b0571..000000000
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-CFLAGS += -mcpu=cortex-a53 \
-          -DBCM_VERSION=2837 \
-          -DCFG_TUSB_MCU=OPT_MCU_BCM2837
diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c
index f7a11fb49..f8f3b0b70 100644
--- a/hw/bsp/broadcom_64bit/family.c
+++ b/hw/bsp/broadcom_64bit/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,9 +24,20 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+/* metadata:
+   manufacturer: Raspberry Pi
+*/
+
+#include "bsp/board_api.h"
 #include "board.h"
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
 #include "broadcom/cpu.h"
 #include "broadcom/gpio.h"
 #include "broadcom/interrupts.h"
@@ -34,6 +45,10 @@
 #include "broadcom/caches.h"
 #include "broadcom/vcmailbox.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 // LED
 #define LED_PIN               18
 #define LED_STATE_ON          1
@@ -44,8 +59,7 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -56,8 +70,7 @@ void USB_IRQHandler(void)
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
-void board_init(void)
-{
+void board_init(void) {
   setup_mmu_flat_map();
   init_caches();
 
@@ -97,24 +110,21 @@ void board_init(void)
   BP_EnableIRQs();
 }
 
-void board_led_write(bool state)
-{
-  gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return 0;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
   for (int i = 0; i < len; i++) {
     const char* cbuf = buf;
     while (!UART1->STAT_b.TX_READY) {}
@@ -127,30 +137,27 @@ int board_uart_write(void const * buf, int len)
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 
-void TIMER_1_IRQHandler(void)
-{
+void TIMER_1_IRQHandler(void) {
   system_ticks++;
   SYSTMR->C1 += 977;
   SYSTMR->CS_b.M1 = 1;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
   // asm("bkpt");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 
 }
diff --git a/hw/bsp/broadcom_64bit/family.cmake b/hw/bsp/broadcom_64bit/family.cmake
new file mode 100644
index 000000000..1a088c2c0
--- /dev/null
+++ b/hw/bsp/broadcom_64bit/family.cmake
@@ -0,0 +1,117 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/broadcom)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/aarch64_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS BCM2711 BCM2835 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/broadcom/link8.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  set(STARTUP_FILE_GNU ${SDK_DIR}/broadcom/boot8.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/broadcom/gen/interrupt_handlers.c
+    ${SDK_DIR}/broadcom/gpio.c
+    ${SDK_DIR}/broadcom/interrupts.c
+    ${SDK_DIR}/broadcom/mmu.c
+    ${SDK_DIR}/broadcom/caches.c
+    ${SDK_DIR}/broadcom/vcmailbox.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC
+    -O0
+    -ffreestanding
+    -mgeneral-regs-only
+    -fno-exceptions
+    -std=c17
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    BCM_VERSION=${BCM_VERSION}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}
+    ${CMSIS_5}/CMSIS/Core_A/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+#    target_compile_options(${BOARD_TARGET} PUBLIC
+#      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      "LINKER:--entry=_start"
+      --specs=nosys.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      "LINKER:--entry=_start"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_BCM${BCM_VERSION})
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/broadcom_64bit/family.mk b/hw/bsp/broadcom_64bit/family.mk
index 97af6d64a..37d381f9f 100644
--- a/hw/bsp/broadcom_64bit/family.mk
+++ b/hw/bsp/broadcom_64bit/family.mk
@@ -1,6 +1,4 @@
 MCU_DIR = hw/mcu/broadcom
-DEPS_SUBMODULES += $(MCU_DIR)
-
 include $(TOP)/$(BOARD_PATH)/board.mk
 
 CFLAGS += \
@@ -9,6 +7,7 @@ CFLAGS += \
 	-ffreestanding \
 	-nostdlib \
 	-nostartfiles \
+	--specs=nosys.specs \
 	-mgeneral-regs-only \
 	-std=c17
 
@@ -19,6 +18,8 @@ CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
 	$(MCU_DIR)/broadcom/gen/interrupt_handlers.c \
 	$(MCU_DIR)/broadcom/gpio.c \
 	$(MCU_DIR)/broadcom/interrupts.c \
@@ -26,8 +27,6 @@ SRC_C += \
 	$(MCU_DIR)/broadcom/caches.c \
 	$(MCU_DIR)/broadcom/vcmailbox.c
 
-SKIP_NANOLIB = 1
-
 LD_FILE = $(MCU_DIR)/broadcom/link8.ld
 
 INC += \
@@ -35,7 +34,7 @@ INC += \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
 
-SRC_S += $(MCU_DIR)/broadcom/boot8.S
+SRC_S += $(MCU_DIR)/broadcom/boot8.s
 
 $(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
 	$(OBJCOPY) -O binary $^ $@
diff --git a/hw/bsp/brtmm90x/boards/mm900evxb/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
index 57936fda5..623033c2c 100644
--- a/hw/bsp/brtmm90x/boards/mm900evxb/board.h
+++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
@@ -24,24 +24,61 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: MM900EVxB
+   url: https://brtchip.com/product/mm900ev1b
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
-// Note: This definition file covers all MM900EV1B, MM900EV2B, and MM900EV3B boards.
+// Note: This definition file covers all MM900EV1B, MM900EV2B, MM900EV3B,
+// MM900EV-Lite boards.
 // Each of these boards has an FT900 device.
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-#define GPIO_UART0_TX 48
-#define GPIO_UART0_RX 49
-#define GPIO_ETH_LED0 61
-#define GPIO_ETH_LED1 62
-#define GPIO_REMOTE_WAKEUP_PIN 18
-#define USBD_VBUS_DTC_PIN 3
+// UART to use on this board.
+#ifndef BOARD_UART
+#define BOARD_UART UART0
+#endif
 
-#define GPIO_REMOTE_WAKEUP
+// UART is on connector CN1.
+#ifndef BOARD_GPIO_UART0_TX
+#define BOARD_GPIO_UART0_TX 48 // Pin 4 of CN1.
+#endif
+#ifndef BOARD_GPIO_UART0_RX
+#define BOARD_GPIO_UART0_RX 49 // Pin 6 of CN1.
+#endif
+
+// LED is connected to pins 17 (signal) and 15 (GND) of CN1.
+#ifndef BOARD_GPIO_LED
+#define BOARD_GPIO_LED 35
+#endif
+#ifndef BOARD_GPIO_LED_STATE_ON
+#define BOARD_GPIO_LED_STATE_ON 1
+#endif
+// Button is connected to pins 13 (signal) and 15 (GND) of CN1.
+#ifndef BOARD_GPIO_BUTTON
+#define BOARD_GPIO_BUTTON 56
+#endif
+// Button is pulled up and grounded for active.
+#ifndef BOARD_GPIO_BUTTON_STATE_ACTIVE
+#define BOARD_GPIO_BUTTON_STATE_ACTIVE 0
+#endif
+
+// Enable the Remote Wakeup signalling.
+// Remote wakeup is wired to pin 40 of CN1.
+#ifndef BOARD_GPIO_REMOTE_WAKEUP
+#define BOARD_GPIO_REMOTE_WAKEUP 18
+#endif
+
+// USB VBus signal is connected directly to the FT900.
+#ifndef BOARD_USBD_VBUS_DTC_PIN
+#define BOARD_USBD_VBUS_DTC_PIN 3
+#endif
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 6b3c1f56c..15ff4b8ee 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright 2021 Bridgetek Pte Ltd
@@ -24,18 +24,22 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+/* metadata:
+   manufacturer: Bridgetek
+*/
+
+#include "bsp/board_api.h"
 #include "board.h"
 
-#include <registers/ft900_registers.h>
 #include <ft900.h>
+#include <registers/ft900_registers.h>
 
 #if CFG_TUD_ENABLED
-int8_t board_ft90x_vbus(void); // Board specific implementation of VBUS detection for USB device.
-extern void ft90x_usbd_pm_ISR(uint16_t pmcfg); // Interrupt handler for USB device power management
+int8_t board_ft9xx_vbus(void); // Board specific implementation of VBUS detection for USB device.
+extern void ft9xx_usbd_pm_ISR(uint16_t pmcfg); // Interrupt handler for USB device power management
 #endif
 
-#ifdef GPIO_REMOTE_WAKEUP
+#ifdef BOARD_GPIO_REMOTE_WAKEUP
 void gpio_ISR(void);
 #endif
 void timer_ISR(void);
@@ -49,12 +53,17 @@ void board_pm_ISR(void);
 void board_init(void)
 {
 	sys_reset_all();
+
     // Enable the UART Device.
     sys_enable(sys_device_uart0);
-    // Set UART0 GPIO functions to UART0_TXD and UART0_RXD.
-    gpio_function(GPIO_UART0_TX, pad_uart0_txd); /* UART0 TXD */
-    gpio_function(GPIO_UART0_RX, pad_uart0_rxd); /* UART0 RXD */
-    uart_open(UART0,                             /* Device */
+    // Set BOARD_UART GPIO function pins for TXD and RXD.
+#ifdef BOARD_GPIO_UART_TX
+    gpio_function(BOARD_GPIO_UART_TX, pad_uart0_txd); /* UART0 TXD */
+#endif
+#ifdef BOARD_GPIO_UART_RX
+    gpio_function(BOARD_GPIO_UART_RX, pad_uart0_rxd); /* UART0 RXD */
+#endif
+    uart_open(BOARD_UART,                             /* Device */
               1,                                 /* Prescaler = 1 */
               UART_DIVIDER_19200_BAUD,           /* Divider = 1302 */
               uart_data_bits_8,                  /* No. Data Bits */
@@ -64,12 +73,17 @@ void board_init(void)
     // Use sizeof to avoid pulling in strlen unnecessarily.
     board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG));
 
-#if 0
-    // Ethernet LEDs
-    gpio_function(GPIO_ETH_LED0, pad_gpio4); /* ETH LED0 */
-    gpio_dir(GPIO_ETH_LED0, pad_dir_open_drain);
-    gpio_function(GPIO_ETH_LED1, pad_gpio5); /* ETH LED1 */
-    gpio_dir(GPIO_ETH_LED1, pad_dir_output);
+#ifdef BOARD_GPIO_LED
+    gpio_function(BOARD_GPIO_LED, pad_func_0);
+    gpio_idrive(BOARD_GPIO_LED, pad_drive_12mA);
+    gpio_dir(BOARD_GPIO_LED, pad_dir_output);
+#endif
+
+#ifdef BOARD_GPIO_BUTTON
+    gpio_function(BOARD_GPIO_BUTTON, pad_func_0);
+    // Pull up if active low. Down if active high.
+    gpio_pull(BOARD_GPIO_BUTTON, (BOARD_GPIO_BUTTON_STATE_ACTIVE == 0)?pad_pull_pullup:pad_pull_pulldown);
+    gpio_dir(BOARD_GPIO_BUTTON, pad_dir_input);
 #endif
 
 	sys_enable(sys_device_timer_wdt);
@@ -82,26 +96,26 @@ void board_init(void)
 
     // Setup VBUS detect GPIO. If the device is connected then this
     // will set the MASK_SYS_PMCFG_DEV_DETECT_EN bit in PMCFG.
-    gpio_interrupt_disable(USBD_VBUS_DTC_PIN);
-    gpio_function(USBD_VBUS_DTC_PIN, pad_vbus_dtc);
-    gpio_pull(USBD_VBUS_DTC_PIN, pad_pull_pulldown);
-    gpio_dir(USBD_VBUS_DTC_PIN, pad_dir_input);
+    gpio_interrupt_disable(BOARD_USBD_VBUS_DTC_PIN);
+    gpio_function(BOARD_USBD_VBUS_DTC_PIN, pad_vbus_dtc);
+    gpio_pull(BOARD_USBD_VBUS_DTC_PIN, pad_pull_pulldown);
+    gpio_dir(BOARD_USBD_VBUS_DTC_PIN, pad_dir_input);
 
     interrupt_attach(interrupt_0, (int8_t)interrupt_0, board_pm_ISR);
 
-#ifdef GPIO_REMOTE_WAKEUP
-    //Configuring GPIO pin to wakeup.
+#ifdef BOARD_GPIO_REMOTE_WAKEUP
+    // Configuring GPIO pin to wakeup.
     // Set up the wakeup pin.
-    gpio_dir(GPIO_REMOTE_WAKEUP_PIN, pad_dir_input);
-    gpio_pull(GPIO_REMOTE_WAKEUP_PIN, pad_pull_pullup);
+    gpio_dir(BOARD_GPIO_REMOTE_WAKEUP, pad_dir_input);
+    gpio_pull(BOARD_GPIO_REMOTE_WAKEUP, pad_pull_pullup);
 
     // Attach an interrupt handler.
     interrupt_attach(interrupt_gpio, (uint8_t)interrupt_gpio, gpio_ISR);
-    gpio_interrupt_enable(GPIO_REMOTE_WAKEUP_PIN, gpio_int_edge_falling);
+    gpio_interrupt_enable(BOARD_GPIO_REMOTE_WAKEUP, gpio_int_edge_falling);
 #endif
 
-	uart_disable_interrupt(UART0, uart_interrupt_tx);
-	uart_disable_interrupt(UART0, uart_interrupt_rx);
+	uart_disable_interrupt(BOARD_UART, uart_interrupt_tx);
+	uart_disable_interrupt(BOARD_UART, uart_interrupt_rx);
 
     // Enable all peripheral interrupts.
     interrupt_enable_globally();
@@ -117,10 +131,10 @@ void timer_ISR(void)
     }
 }
 
-#ifdef GPIO_REMOTE_WAKEUP
+#ifdef BOARD_GPIO_REMOTE_WAKEUP
 void gpio_ISR(void)
 {
-    if (gpio_is_interrupted(GPIO_REMOTE_WAKEUP_PIN))
+    if (gpio_is_interrupted(BOARD_GPIO_REMOTE_WAKEUP))
     {
     }
 }
@@ -153,16 +167,16 @@ void board_pm_ISR(void)
     )
     {
 #if CFG_TUD_ENABLED
-        ft90x_usbd_pm_ISR(pmcfg);
+        ft9xx_usbd_pm_ISR(pmcfg);
 #endif
     }
 #endif
 }
 
 #if CFG_TUD_ENABLED
-int8_t board_ft90x_vbus(void)
+int8_t board_ft9xx_vbus(void)
 {
-	return gpio_read(USBD_VBUS_DTC_PIN);
+	return gpio_read(BOARD_USBD_VBUS_DTC_PIN);
 }
 #endif
 
@@ -173,20 +187,33 @@ int8_t board_ft90x_vbus(void)
 // Turn LED on or off
 void board_led_write(bool state)
 {
-    gpio_write(GPIO_ETH_LED0, state);
+#ifdef BOARD_GPIO_LED
+    gpio_write(BOARD_GPIO_LED, (state == 0)?(BOARD_GPIO_LED_STATE_ON?0:1):BOARD_GPIO_LED_STATE_ON);
+#endif
 }
 
 // Get the current state of button
 // a '1' means active (pressed), a '0' means inactive.
 uint32_t board_button_read(void)
 {
-    return 0;
+    uint32_t state = 0;
+#ifdef BOARD_GPIO_BUTTON
+    state = (gpio_read(BOARD_GPIO_BUTTON) == BOARD_GPIO_BUTTON_STATE_ACTIVE)?1:0;
+#endif
+    return state;
 }
 
 // Get characters from UART
 int board_uart_read(uint8_t *buf, int len)
 {
-    int r = uart_readn(UART0, (uint8_t *)buf, len);
+    int r = 0;
+
+#ifdef BOARD_UART
+    if (uart_rx_has_data(BOARD_UART))
+    {
+        r = uart_readn(BOARD_UART, (uint8_t *)buf, len);
+    }
+#endif
 
     return r;
 }
@@ -194,10 +221,14 @@ int board_uart_read(uint8_t *buf, int len)
 // Send characters to UART
 int board_uart_write(void const *buf, int len)
 {
+    int r = 0;
+
+#ifdef BOARD_UART
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wcast-qual" // uart_writen does not have const for buffer parameter.
-    int r = uart_writen(UART0, (uint8_t *)((const void *)buf), len);
+    r = uart_writen(BOARD_UART, (uint8_t *)((const void *)buf), len);
 #pragma GCC diagnostic pop
+#endif
 
     return r;
 }
@@ -206,10 +237,24 @@ int board_uart_write(void const *buf, int len)
 uint32_t board_millis(void)
 {
     uint32_t safe_ms;
-    
+
     CRITICAL_SECTION_BEGIN
     safe_ms = timer_ms;
     CRITICAL_SECTION_END
 
     return safe_ms;
 }
+
+// Restart the program
+// Called in the event of a watchdog timeout
+void chip_reboot(void)
+{
+    // SOFT reset
+    __asm__("call 0");
+ #if 0
+    // HARD reset
+    // Initiates data transfer from Flash Memory to Data Memory (DBG_CMDF2D3)
+    // followed by a system reboot
+ 	dbg_memory_copy(0xfe, 0, 0, 255);
+#endif
+}
diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index 3933f15cc..6df0bfdfe 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -3,12 +3,12 @@ CROSS_COMPILE = ft32-elf-
 SKIP_NANOLIB = 1
 
 # Set to use FT90X prebuilt libraries.
-FT90X_PREBUILT_LIBS = 0
-ifeq ($(FT90X_PREBUILT_LIBS),1)
-# If the FT90X toolchain is installed on Windows systems then the SDK 
+FT9XX_PREBUILT_LIBS = 0
+ifeq ($(FT9XX_PREBUILT_LIBS),1)
+# If the FT90X toolchain is installed on Windows systems then the SDK
 # include files and prebuilt libraries are at: %FT90X_TOOLCHAIN%/hardware
 FT9XX_SDK = $(FT90X_TOOLCHAIN)/hardware
-INC += $(FT9XX_SDK)/include
+INC += "$(FT9XX_SDK)/include"
 else
 # The submodule BRTSG-FOSS/ft90x-sdk contains header files and source
 # code for the Bridgetek SDK. This can be used instead of the prebuilt
@@ -16,7 +16,7 @@ else
 DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/ft90x-sdk
 # The SDK can be used to load specific files from the Bridgetek SDK.
 FT9XX_SDK = hw/mcu/bridgetek/ft9xx/ft90x-sdk/Source
-INC += $(TOP)/$(FT9XX_SDK)/include
+INC += "$(TOP)/$(FT9XX_SDK)/include"
 endif
 
 # Add include files which are within the TinyUSB directory structure.
@@ -32,12 +32,12 @@ CFLAGS += \
 	-ffunction-sections \
 	-DCFG_TUSB_MCU=OPT_MCU_FT90X
 
+# Maximum USB device speed supported by the board
+CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
 # lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration
 CFLAGS += -Wno-error=shadow
 
-# Add include files outside the TinyUSB structure that are added manually.
-CFLAGS += -I"$(FT9XX_SDK)/include"
-
 # Set Linker flags.
 LD_FILE = hw/mcu/bridgetek/ft9xx/scripts/ldscript.ld
 LDFLAGS += $(addprefix -L,$(LDINC)) \
@@ -45,10 +45,10 @@ LDFLAGS += $(addprefix -L,$(LDINC)) \
 	-Wl,-lc
 
 # Additional Source files for FT90X.
-SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c 
+SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c
 
 # Linker library.
-ifneq ($(FT90X_PREBUILT_LIBS),1)
+ifneq ($(FT9XX_PREBUILT_LIBS),1)
 # Optionally add in files from the Bridgetek SDK instead of the prebuilt
 # library. These are the minimum required.
 SRC_C += $(FT9XX_SDK)/src/sys.c
diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h
new file mode 100644
index 000000000..b855804a9
--- /dev/null
+++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h
@@ -0,0 +1,64 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* metadata:
+   name: CH32F205r-r0
+   url: https://github.com/openwch/ch32f20x
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED: need to wire pin LED1 to PC0 in the P1 header
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_Pin_1
+#define LED_STATE_ON          0
+#define LED_CLOCK_EN()        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// Button: need to wire pin KEY to PC1 in the P1 header
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_Pin_0
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_CLOCK_EN()     RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// UART
+#define UART_DEV              USART2
+#define UART_DEV_IRQn         USART2_IRQn
+#define UART_DEV_IRQHandler   USART2_IRQHandler
+#define UART_DEV_GPIO_PORT    GPIOA
+#define UART_DEV_TX_PIN       GPIO_Pin_2
+#define UART_DEV_CLK_EN()     do {                                                      \
+                                RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);   \
+                                RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);  \
+                              } while(0)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk
new file mode 100644
index 000000000..f0e9bf30f
--- /dev/null
+++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk
@@ -0,0 +1,7 @@
+LD_FILE = $(FAMILY_PATH)/ch32f205.ld
+
+SRC_S += \
+	$(FAMILY_PATH)/startup_gcc_ch32f20x_d8c.s
+
+CFLAGS += \
+	-DCH32F20x_D8C
diff --git a/hw/bsp/ch32f20x/ch32f205.ld b/hw/bsp/ch32f20x/ch32f205.ld
new file mode 100644
index 000000000..7c8d04cc5
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f205.ld
@@ -0,0 +1,111 @@
+ENTRY(Reset_Handler)
+
+_Min_Heap_Size = 0x200;
+_Min_Stack_Size = 0x400;
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+SECTIONS
+{
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))
+    . = ALIGN(4);
+  } >FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    _stext = .;
+    *(.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+    _etext = .;
+  } >FLASH
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+  .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+  _sidata = LOADADDR(.data);
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;
+    *(.data)
+    *(.data*)
+    . = ALIGN(4);
+    _edata = .;
+  } >RAM AT> FLASH
+  . = ALIGN(4);
+  .bss :
+  {
+    _sbss = .;
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    _ebss = .;
+    __bss_end__ = _ebss;
+  } >RAM
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    __HeapStart = .;
+    . = . + _Min_Heap_Size;
+    __HeapEnd = .;
+    __StackLimit = .;
+    . = . + _Min_Stack_Size;
+    __StackTop = .;
+    . = ALIGN(4);
+  } >RAM
+_estack = __StackTop;
+_sstack = __StackLimit;
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/ch32f20x/ch32f20x_conf.h b/hw/bsp/ch32f20x/ch32f20x_conf.h
new file mode 100644
index 000000000..05199ff95
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f20x_conf.h
@@ -0,0 +1,39 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f20x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/08/08
+ * Description        : Library configuration file.
+ *********************************************************************************
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * Attention: This software (modified or not) and binary are used for
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
+ *******************************************************************************/
+#ifndef __CH32F20x_CONF_H
+#define __CH32F20x_CONF_H
+
+#include "ch32f20x_adc.h"
+#include "ch32f20x_bkp.h"
+#include "ch32f20x_can.h"
+#include "ch32f20x_crc.h"
+#include "ch32f20x_dac.h"
+#include "ch32f20x_dbgmcu.h"
+#include "ch32f20x_dma.h"
+#include "ch32f20x_exti.h"
+#include "ch32f20x_flash.h"
+#include "ch32f20x_fsmc.h"
+#include "ch32f20x_gpio.h"
+#include "ch32f20x_i2c.h"
+#include "ch32f20x_iwdg.h"
+#include "ch32f20x_pwr.h"
+#include "ch32f20x_rcc.h"
+#include "ch32f20x_rtc.h"
+#include "ch32f20x_sdio.h"
+#include "ch32f20x_spi.h"
+#include "ch32f20x_tim.h"
+#include "ch32f20x_usart.h"
+#include "ch32f20x_wwdg.h"
+#include "ch32f20x_it.h"
+#include "ch32f20x_misc.h"
+
+#endif /* __CH32F20x_CONF_H */
diff --git a/hw/bsp/ch32f20x/ch32f20x_it.c b/hw/bsp/ch32f20x/ch32f20x_it.c
new file mode 100644
index 000000000..94e28e380
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f20x_it.c
@@ -0,0 +1,35 @@
+#include "ch32f20x_it.h"
+
+#include "ch32f20x.h"
+
+/* -------------------------------------------------------------------------- */
+
+void NMI_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void MemManage_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void BusFault_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void UsageFault_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void DebugMon_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
diff --git a/hw/bsp/ch32f20x/ch32f20x_it.h b/hw/bsp/ch32f20x/ch32f20x_it.h
new file mode 100644
index 000000000..34f3bbf96
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f20x_it.h
@@ -0,0 +1,25 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32f20x_it.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/08/08
+* Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32F20xIT_H
+#define __CH32F20xIT_H
+
+#include "ch32f20x.h"
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+
+
+#endif /* __CH32F20xIT_H */
diff --git a/hw/bsp/ch32f20x/core_cm3.h b/hw/bsp/ch32f20x/core_cm3.h
new file mode 100644
index 000000000..c35a4eec3
--- /dev/null
+++ b/hw/bsp/ch32f20x/core_cm3.h
@@ -0,0 +1,11 @@
+/* There is core_cm3.h wrapper just to avoid warnings from CMSIS headers */
+/* if you want use original file add to make file:
+    INC += \
+        $(TOP)/$(CH32F20X_SDK_SRC)/CMSIS
+*/
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+
+#include <../../CMSIS/core_cm3.h>
+
+#pragma GCC diagnostic pop
diff --git a/hw/bsp/ch32f20x/debug_uart.c b/hw/bsp/ch32f20x/debug_uart.c
new file mode 100644
index 000000000..a595eb6f7
--- /dev/null
+++ b/hw/bsp/ch32f20x/debug_uart.c
@@ -0,0 +1,105 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#include <ch32f20x.h>
+
+#include "board.h"
+#include "debug_uart.h"
+
+#define UART_RINGBUFFER_SIZE_TX 64
+#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
+
+static char tx_buf[UART_RINGBUFFER_SIZE_TX];
+static unsigned int tx_produce = 0;
+static volatile unsigned int tx_consume = 0;
+
+void UART_DEV_IRQHandler(void)
+{
+  if(USART_GetITStatus(UART_DEV, USART_IT_TC) != RESET) {
+    USART_ClearITPendingBit(UART_DEV, USART_IT_TC);
+
+    if(tx_consume != tx_produce) {
+      USART_SendData(UART_DEV, tx_buf[tx_consume]);
+      tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
+    }
+  }
+}
+
+void uart_write(char c)
+{
+  unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
+
+  NVIC_DisableIRQ(UART_DEV_IRQn);
+  if((tx_consume != tx_produce) || (USART_GetFlagStatus(UART_DEV, USART_FLAG_TXE) == RESET)) {
+    tx_buf[tx_produce] = c;
+    tx_produce = tx_produce_next;
+  } else {
+    USART_SendData(UART_DEV, c);
+  }
+  NVIC_EnableIRQ(UART_DEV_IRQn);
+}
+
+void uart_sync(void)
+{
+  while(tx_consume != tx_produce) {
+    //Waiting for transfer complete
+  }
+}
+
+void usart_printf_init(uint32_t baudrate)
+{
+  tx_produce = 0;
+  tx_consume = 0;
+
+  UART_DEV_CLK_EN();
+
+  GPIO_InitTypeDef gpio_config = {
+    .GPIO_Pin = UART_DEV_TX_PIN,
+    .GPIO_Speed = GPIO_Speed_50MHz,
+    .GPIO_Mode = GPIO_Mode_AF_PP,
+  };
+  GPIO_Init(UART_DEV_GPIO_PORT, &gpio_config);
+
+  USART_InitTypeDef uart_config = {
+    .USART_BaudRate = baudrate,
+    .USART_WordLength = USART_WordLength_8b,
+    .USART_StopBits = USART_StopBits_1,
+    .USART_Parity = USART_Parity_No,
+    .USART_HardwareFlowControl = USART_HardwareFlowControl_None,
+    .USART_Mode = USART_Mode_Tx,
+  };
+
+  USART_Init(UART_DEV, &uart_config);
+  USART_ITConfig(UART_DEV, USART_IT_TC, ENABLE);
+  USART_Cmd(UART_DEV, ENABLE);
+
+  NVIC_InitTypeDef nvic_config = {
+    .NVIC_IRQChannel = UART_DEV_IRQn,
+    .NVIC_IRQChannelPreemptionPriority = 1,
+    .NVIC_IRQChannelSubPriority = 3,
+    .NVIC_IRQChannelCmd = ENABLE,
+  };
+  NVIC_Init(&nvic_config);
+}
diff --git a/hw/bsp/ch32f20x/debug_uart.h b/hw/bsp/ch32f20x/debug_uart.h
new file mode 100644
index 000000000..10284cf6f
--- /dev/null
+++ b/hw/bsp/ch32f20x/debug_uart.h
@@ -0,0 +1,31 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+
+void uart_write(char c);
+void uart_sync(void);
+void usart_printf_init(uint32_t baudrate);
diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/ch32f20x/family.c
similarity index 52%
rename from hw/bsp/da14695_dk_usb/da14695_dk_usb.c
rename to hw/bsp/ch32f20x/family.c
index a4d996810..7fef71d47 100644
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ b/hw/bsp/ch32f20x/family.c
@@ -1,7 +1,7 @@
-/* 
+/*
  * The MIT License (MIT)
  *
- * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2023 Denis Krasutski
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,104 +24,77 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
-#include <hal/hal_gpio.h>
-#include <mcu/mcu.h>
+/* metadata:
+   manufacturer: WCH
+*/
+
+#include "stdio.h"
+#include "debug_uart.h"
+
+#include "ch32f20x.h"
+
+#include "bsp/board_api.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
+
+void USBHS_IRQHandler(void)
 {
   tud_int_handler(0);
 }
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
+void board_init(void) {
 
-#define LED_PIN         33 // P1.1
-#define LED_STATE_ON    1
-#define LED_STATE_OFF   (1-LED_STATE_ON)
+  /* Disable interrupts during init */
+  __disable_irq();
 
-#define BUTTON_PIN      6
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
 
-void UnhandledIRQ(void)
-{
-  CRG_TOP->SYS_CTRL_REG = 0x80;
-  __BKPT(1);
-  while(1);
-}
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USBHS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
 
-// DA146xx driver function that must be called whenever VBUS changes.
-extern void tusb_vbus_changed(bool present);
+	usart_printf_init(115200);
+
+  // USB HS Clock config
+  RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
+  RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
+  RCC_USBHSConfig(RCC_USBPLL_Div2);
+  RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M);
+  RCC_USBHSPHYPLLALIVEcmd(ENABLE);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE);
 
-void board_init(void)
-{
   // LED
-  hal_gpio_init_out(LED_PIN, LED_STATE_ON);
-
-  hal_gpio_init_out(1, 0);
-  hal_gpio_init_out(2, 0);
-  hal_gpio_init_out(3, 0);
-  hal_gpio_init_out(4, 0);
-  hal_gpio_init_out(5, 0);
+  LED_CLOCK_EN();
+  GPIO_InitTypeDef led_pin_config = {
+    .GPIO_Pin = LED_PIN,
+    .GPIO_Mode = GPIO_Mode_Out_OD,
+    .GPIO_Speed = GPIO_Speed_50MHz,
+  };
+  GPIO_Init(LED_PORT, &led_pin_config);
 
   // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_DOWN);
+  BUTTON_CLOCK_EN();
+  GPIO_InitTypeDef button_pin_config = {
+    .GPIO_Pin = BUTTON_PIN,
+    .GPIO_Mode = GPIO_Mode_IPU,
+    .GPIO_Speed = GPIO_Speed_50MHz,
+  };
+  GPIO_Init(BUTTON_PORT, &button_pin_config);
 
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUD_ENABLED
-  // This board is USB powered there is no need to monitor
-  // VBUS line.  Notify driver that VBUS is present.
-  tusb_vbus_changed(true);
-
-  /* Setup USB IRQ */
-  NVIC_SetPriority(USB_IRQn, 2);
-  NVIC_EnableIRQ(USB_IRQn);
-
-  /* Use PLL96 / 2 clock not HCLK */
-  CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk;
-
-  mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
-  mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  hal_gpio_write(LED_PIN, state ? LED_STATE_ON : LED_STATE_OFF);
-}
-
-uint32_t board_button_read(void)
-{
-  // button is active HIGH
-  return hal_gpio_read(BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void)buf;
-  (void)len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void)buf;
-  (void)len;
-
-  return 0;
+  /* Enable interrupts globally */
+  __enable_irq();
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
+
 volatile uint32_t system_ticks = 0;
+
 void SysTick_Handler(void)
 {
   system_ticks++;
@@ -131,4 +104,42 @@ uint32_t board_millis(void)
 {
   return system_ticks;
 }
+
 #endif
+
+void HardFault_Handler(void)
+{
+  __asm("BKPT #0\n");
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_WriteBit(LED_PORT, LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+  int txsize = len;
+  while ( txsize-- )
+  {
+    uart_write(*(uint8_t const*) buf);
+    buf++;
+  }
+  return len;
+}
diff --git a/hw/bsp/ch32f20x/family.mk b/hw/bsp/ch32f20x/family.mk
new file mode 100644
index 000000000..c08451b9c
--- /dev/null
+++ b/hw/bsp/ch32f20x/family.mk
@@ -0,0 +1,30 @@
+# Submodules
+CH32F20X_SDK = hw/mcu/wch/ch32f20x
+DEPS_SUBMODULES += $(CH32F20X_SDK)
+
+# WCH-SDK paths
+CH32F20X_SDK_SRC = $(CH32F20X_SDK)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m3
+
+CFLAGS += \
+	-DCFG_TUSB_MCU=OPT_MCU_CH32F20X \
+	-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+SRC_C += \
+	src/portable/wch/dcd_ch32_usbhs.c \
+	$(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_gpio.c \
+	$(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_misc.c \
+	$(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_rcc.c \
+	$(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_usart.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(CH32F20X_SDK_SRC)/StdPeriphDriver/inc
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
+
+flash: flash-stlink
diff --git a/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s b/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s
new file mode 100644
index 000000000..2ecac2ac1
--- /dev/null
+++ b/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file      startup_gcc_ch32f20x_d8c.s
+  * @author    Denis Krasutski
+  * @brief     CH32F205 Devices vector table
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+.syntax unified
+.cpu cortex-m3
+.thumb
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+
+.section  .text.Reset_Handler
+.weak  Reset_Handler
+.type  Reset_Handler, %function
+Reset_Handler:
+  /* set stack pointer */
+  ldr   sp, =_estack
+  /* Call the clock system initialization function.*/
+  bl  SystemInit
+  /* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+
+  /* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+  /* Call static constructors */
+  bl __libc_init_array
+  /* Call the application's entry point.*/
+  bl  main
+  bx  lr
+  .size  Reset_Handler, .-Reset_Handler
+
+.section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+  .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+/*******************************************************************************
+ External Interrupts
+*******************************************************************************/
+.word     WWDG_IRQHandler
+.word     PVD_IRQHandler
+.word     TAMPER_IRQHandler
+.word     RTC_IRQHandler
+.word     FLASH_IRQHandler
+.word     RCC_IRQHandler
+.word     EXTI0_IRQHandler
+.word     EXTI1_IRQHandler
+.word     EXTI2_IRQHandler
+.word     EXTI3_IRQHandler
+.word     EXTI4_IRQHandler
+.word     DMA1_Channel1_IRQHandler
+.word     DMA1_Channel2_IRQHandler
+.word     DMA1_Channel3_IRQHandler
+.word     DMA1_Channel4_IRQHandler
+.word     DMA1_Channel5_IRQHandler
+.word     DMA1_Channel6_IRQHandler
+.word     DMA1_Channel7_IRQHandler
+.word     ADC1_2_IRQHandler
+.word     USB_HP_CAN1_TX_IRQHandler
+.word     USB_LP_CAN1_RX0_IRQHandler
+.word     CAN1_RX1_IRQHandler
+.word     CAN1_SCE_IRQHandler
+.word     EXTI9_5_IRQHandler
+.word     TIM1_BRK_IRQHandler
+.word     TIM1_UP_IRQHandler
+.word     TIM1_TRG_COM_IRQHandler
+.word     TIM1_CC_IRQHandler
+.word     TIM2_IRQHandler
+.word     TIM3_IRQHandler
+.word     TIM4_IRQHandler
+.word     I2C1_EV_IRQHandler
+.word     I2C1_ER_IRQHandler
+.word     I2C2_EV_IRQHandler
+.word     I2C2_ER_IRQHandler
+.word     SPI1_IRQHandler
+.word     SPI2_IRQHandler
+.word     USART1_IRQHandler
+.word     USART2_IRQHandler
+.word     USART3_IRQHandler
+.word     EXTI15_10_IRQHandler
+.word     RTCAlarm_IRQHandler
+.word     0
+.word     TIM8_BRK_IRQHandler
+.word     TIM8_UP_IRQHandler
+.word     TIM8_TRG_COM_IRQHandler
+.word     TIM8_CC_IRQHandler
+.word     RNG_IRQHandler
+.word     FSMC_IRQHandler
+.word     SDIO_IRQHandler
+.word     TIM5_IRQHandler
+.word     SPI3_IRQHandler
+.word     UART4_IRQHandler
+.word     UART5_IRQHandler
+.word     TIM6_IRQHandler
+.word     TIM7_IRQHandler
+.word     DMA2_Channel1_IRQHandler
+.word     DMA2_Channel2_IRQHandler
+.word     DMA2_Channel3_IRQHandler
+.word     DMA2_Channel4_IRQHandler
+.word     DMA2_Channel5_IRQHandler
+.word     ETH_IRQHandler
+.word     ETH_WKUP_IRQHandler
+.word     CAN2_TX_IRQHandler
+.word     CAN2_RX0_IRQHandler
+.word     CAN2_RX1_IRQHandler
+.word     CAN2_SCE_IRQHandler
+.word     OTG_FS_IRQHandler
+.word     USBHSWakeup_IRQHandler
+.word     USBHS_IRQHandler
+.word     DVP_IRQHandler
+.word     UART6_IRQHandler
+.word     UART7_IRQHandler
+.word     UART8_IRQHandler
+.word     TIM9_BRK_IRQHandler
+.word     TIM9_UP_IRQHandler
+.word     TIM9_TRG_COM_IRQHandler
+.word     TIM9_CC_IRQHandler
+.word     TIM10_BRK_IRQHandler
+.word     TIM10_UP_IRQHandler
+.word     TIM10_TRG_COM_IRQHandler
+.word     TIM10_CC_IRQHandler
+.word     DMA2_Channel6_IRQHandler
+.word     DMA2_Channel7_IRQHandler
+.word     DMA2_Channel8_IRQHandler
+.word     DMA2_Channel9_IRQHandler
+.word     DMA2_Channel10_IRQHandler
+.word     DMA2_Channel11_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases
+*
+*******************************************************************************/
+.weak NMI_Handler
+.thumb_set NMI_Handler,Default_Handler
+
+.weak HardFault_Handler
+.thumb_set HardFault_Handler,Default_Handler
+
+.weak MemManage_Handler
+.thumb_set MemManage_Handler,Default_Handler
+
+.weak BusFault_Handler
+.thumb_set BusFault_Handler,Default_Handler
+
+.weak UsageFault_Handler
+.thumb_set UsageFault_Handler,Default_Handler
+
+.weak SVC_Handler
+.thumb_set SVC_Handler,Default_Handler
+
+.weak DebugMon_Handler
+.thumb_set DebugMon_Handler,Default_Handler
+
+.weak PendSV_Handler
+.thumb_set PendSV_Handler,Default_Handler
+
+.weak SysTick_Handler
+.thumb_set SysTick_Handler,Default_Handler
+
+.weak WWDG_IRQHandler
+.thumb_set WWDG_IRQHandler,Default_Handler
+
+.weak PVD_IRQHandler
+.thumb_set PVD_IRQHandler,Default_Handler
+
+.weak TAMPER_IRQHandler
+.thumb_set TAMPER_IRQHandler,Default_Handler
+
+.weak RTC_IRQHandler
+.thumb_set RTC_IRQHandler,Default_Handler
+
+.weak FLASH_IRQHandler
+.thumb_set FLASH_IRQHandler,Default_Handler
+
+.weak RCC_IRQHandler
+.thumb_set RCC_IRQHandler,Default_Handler
+
+.weak EXTI0_IRQHandler
+.thumb_set EXTI0_IRQHandler,Default_Handler
+
+.weak EXTI1_IRQHandler
+.thumb_set EXTI1_IRQHandler,Default_Handler
+
+.weak EXTI2_IRQHandler
+.thumb_set EXTI2_IRQHandler,Default_Handler
+
+.weak EXTI3_IRQHandler
+.thumb_set EXTI3_IRQHandler,Default_Handler
+
+.weak EXTI4_IRQHandler
+.thumb_set EXTI4_IRQHandler,Default_Handler
+
+.weak DMA1_Channel1_IRQHandler
+.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+.weak DMA1_Channel2_IRQHandler
+.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+.weak DMA1_Channel3_IRQHandler
+.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+.weak DMA1_Channel4_IRQHandler
+.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+.weak DMA1_Channel5_IRQHandler
+.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+.weak DMA1_Channel6_IRQHandler
+.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+.weak DMA1_Channel7_IRQHandler
+.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+.weak ADC1_2_IRQHandler
+.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+.weak USB_HP_CAN1_TX_IRQHandler
+.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+.weak USB_LP_CAN1_RX0_IRQHandler
+.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+.weak CAN1_RX1_IRQHandler
+.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+.weak CAN1_SCE_IRQHandler
+.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+.weak EXTI9_5_IRQHandler
+.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+.weak TIM1_BRK_IRQHandler
+.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+.weak TIM1_UP_IRQHandler
+.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+.weak TIM1_TRG_COM_IRQHandler
+.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM1_CC_IRQHandler
+.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+.weak TIM2_IRQHandler
+.thumb_set TIM2_IRQHandler,Default_Handler
+
+.weak TIM3_IRQHandler
+.thumb_set TIM3_IRQHandler,Default_Handler
+
+.weak TIM4_IRQHandler
+.thumb_set TIM4_IRQHandler,Default_Handler
+
+.weak I2C1_EV_IRQHandler
+.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+.weak I2C1_ER_IRQHandler
+.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+.weak I2C2_EV_IRQHandler
+.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+.weak I2C2_ER_IRQHandler
+.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+.weak SPI1_IRQHandler
+.thumb_set SPI1_IRQHandler,Default_Handler
+
+.weak SPI2_IRQHandler
+.thumb_set SPI2_IRQHandler,Default_Handler
+
+.weak USART1_IRQHandler
+.thumb_set USART1_IRQHandler,Default_Handler
+
+.weak USART2_IRQHandler
+.thumb_set USART2_IRQHandler,Default_Handler
+
+.weak USART3_IRQHandler
+.thumb_set USART3_IRQHandler,Default_Handler
+
+.weak EXTI15_10_IRQHandler
+.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+.weak RTCAlarm_IRQHandler
+.thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+.weak TIM8_BRK_IRQHandler
+.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+.weak TIM8_UP_IRQHandler
+.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+.weak TIM8_TRG_COM_IRQHandler
+.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM8_CC_IRQHandler
+.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+.weak RNG_IRQHandler
+.thumb_set RNG_IRQHandler,Default_Handler
+
+.weak FSMC_IRQHandler
+.thumb_set FSMC_IRQHandler,Default_Handler
+
+.weak SDIO_IRQHandler
+.thumb_set SDIO_IRQHandler,Default_Handler
+
+.weak TIM5_IRQHandler
+.thumb_set TIM5_IRQHandler,Default_Handler
+
+.weak SPI3_IRQHandler
+.thumb_set SPI3_IRQHandler,Default_Handler
+
+.weak UART4_IRQHandler
+.thumb_set UART4_IRQHandler,Default_Handler
+
+.weak UART5_IRQHandler
+.thumb_set UART5_IRQHandler,Default_Handler
+
+.weak TIM6_IRQHandler
+.thumb_set TIM6_IRQHandler,Default_Handler
+
+.weak TIM7_IRQHandler
+.thumb_set TIM7_IRQHandler,Default_Handler
+
+.weak DMA2_Channel1_IRQHandler
+.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+.weak DMA2_Channel2_IRQHandler
+.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+.weak DMA2_Channel3_IRQHandler
+.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+.weak DMA2_Channel4_IRQHandler
+.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+.weak DMA2_Channel5_IRQHandler
+.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+.weak ETH_IRQHandler
+.thumb_set ETH_IRQHandler,Default_Handler
+
+.weak ETH_WKUP_IRQHandler
+.thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+.weak CAN2_TX_IRQHandler
+.thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+.weak CAN2_RX0_IRQHandler
+.thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+.weak CAN2_RX1_IRQHandler
+.thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+.weak CAN2_SCE_IRQHandler
+.thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+.weak OTG_FS_IRQHandler
+.thumb_set OTG_FS_IRQHandler,Default_Handler
+
+.weak USBHSWakeup_IRQHandler
+.thumb_set USBHSWakeup_IRQHandler,Default_Handler
+
+.weak USBHS_IRQHandler
+.thumb_set USBHS_IRQHandler,Default_Handler
+
+.weak DVP_IRQHandler
+.thumb_set DVP_IRQHandler,Default_Handler
+
+.weak UART6_IRQHandler
+.thumb_set UART6_IRQHandler,Default_Handler
+
+.weak UART7_IRQHandler
+.thumb_set UART7_IRQHandler,Default_Handler
+
+.weak UART8_IRQHandler
+.thumb_set UART8_IRQHandler,Default_Handler
+
+.weak TIM9_BRK_IRQHandler
+.thumb_set TIM9_BRK_IRQHandler,Default_Handler
+
+.weak TIM9_UP_IRQHandler
+.thumb_set TIM9_UP_IRQHandler,Default_Handler
+
+.weak TIM9_TRG_COM_IRQHandler
+.thumb_set TIM9_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM9_CC_IRQHandler
+.thumb_set TIM9_CC_IRQHandler,Default_Handler
+
+.weak TIM10_BRK_IRQHandler
+.thumb_set TIM10_BRK_IRQHandler,Default_Handler
+
+.weak TIM10_UP_IRQHandler
+.thumb_set TIM10_UP_IRQHandler,Default_Handler
+
+.weak TIM10_TRG_COM_IRQHandler
+.thumb_set TIM10_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM10_CC_IRQHandler
+.thumb_set TIM10_CC_IRQHandler,Default_Handler
+
+.weak DMA2_Channel6_IRQHandler
+.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+.weak DMA2_Channel7_IRQHandler
+.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+.weak DMA2_Channel8_IRQHandler
+.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
+
+.weak DMA2_Channel9_IRQHandler
+.thumb_set DMA2_Channel9_IRQHandler,Default_Handler
+
+.weak DMA2_Channel10_IRQHandler
+.thumb_set DMA2_Channel10_IRQHandler,Default_Handler
+
+.weak DMA2_Channel11_IRQHandler
+.thumb_set DMA2_Channel11_IRQHandler,Default_Handler
diff --git a/hw/bsp/ch32f20x/system_ch32f20x.c b/hw/bsp/ch32f20x/system_ch32f20x.c
new file mode 100644
index 000000000..0a59b9287
--- /dev/null
+++ b/hw/bsp/ch32f20x/system_ch32f20x.c
@@ -0,0 +1,1122 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32f20x.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/08/08
+* Description        : CH32F20x Device Peripheral Access Layer System Source File.
+*                      For CH32F208 HSE = 32Mhz
+*                      For others   HSE = 8Mhz
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32f20x.h"
+
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source.
+*/
+
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+#define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+
+/* Uncomment the following line if you need to relocate your vector Table in Internal SRAM */
+/* #define VECT_TAB_SRAM */
+
+/* Vector Table base offset field This value must be a multiple of 0x200 */
+#define VECT_TAB_OFFSET  0x0
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* system_private_function_proto_types */
+static void SetSysClock( void );
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit( void )
+{
+    RCC->CTLR |= ( uint32_t )0x00000001;
+
+#ifdef CH32F20x_D8C
+    RCC->CFGR0 &= ( uint32_t )0xF8FF0000;
+#else
+    RCC->CFGR0 &= ( uint32_t )0xF0FF0000;
+#endif
+
+    RCC->CTLR &= ( uint32_t )0xFEF6FFFF;
+    RCC->CTLR &= ( uint32_t )0xFFFBFFFF;
+    RCC->CFGR0 &= ( uint32_t )0xFF80FFFF;
+#ifdef CH32F20x_D8C
+    RCC->CTLR &= ( uint32_t )0xEBFFFFFF;
+    RCC->INTR = 0x00FF0000;
+    RCC->CFGR2 = 0x00000000;
+#else
+    RCC->INTR = 0x009F0000;
+#endif
+
+    SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate( void )
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+	  uint8_t Pll_6_5 = 0;
+
+#if defined (CH32F20x_D8C)
+   	uint8_t Pll2mull = 0;
+
+#endif
+
+    tmp = RCC->CFGR0 & RCC_SWS;
+
+    switch( tmp )
+    {
+        case 0x00:
+            SystemCoreClock = HSI_VALUE;
+            break;
+        case 0x04:
+            SystemCoreClock = HSE_VALUE;
+            break;
+        case 0x08:
+            pllmull = RCC->CFGR0 & RCC_PLLMULL;
+            pllsource = RCC->CFGR0 & RCC_PLLSRC;
+            pllmull = ( pllmull >> 18 ) + 2;
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+            if( pllmull == 17 )
+            {
+                pllmull = 18;
+            }
+#else
+            if( pllmull == 2 )
+            {
+                pllmull = 18;
+            }
+            if( pllmull == 15 )
+            {
+                pllmull = 13;  /* *6.5 */
+                Pll_6_5 = 1;
+            }
+            if( pllmull == 16 )
+            {
+                pllmull = 15;
+            }
+            if( pllmull == 17 )
+            {
+                pllmull = 16;
+            }
+#endif
+
+            if( pllsource == 0x00 )
+            {
+								if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) SystemCoreClock = HSI_VALUE * pllmull;
+								else SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+            }
+            else
+            {
+#if defined (CH32F20x_D8C)
+	          if(RCC->CFGR2 & (1<<16)){ /* PLL2 */
+              SystemCoreClock = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1);  /* PREDIV2 */
+
+              Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8);
+
+              if(Pll2mull == 0) SystemCoreClock = (SystemCoreClock * 5)>>1;
+              else if(Pll2mull == 1) SystemCoreClock = (SystemCoreClock * 25)>>1;
+              else if(Pll2mull == 15) SystemCoreClock = SystemCoreClock * 20;
+              else  SystemCoreClock = SystemCoreClock * (Pll2mull + 2);
+
+              SystemCoreClock = SystemCoreClock/((RCC->CFGR2 & 0xF) + 1);  /* PREDIV1 */
+          }
+          else{/* HSE */
+              SystemCoreClock = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1);  /* PREDIV1 */
+          }
+
+          SystemCoreClock = SystemCoreClock * pllmull;
+#else
+
+#if defined (CH32F20x_D8W)
+								if((RCC->CFGR0 & (3<<22)) == (3<<22))
+								{
+									SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+								}
+								else
+#endif
+                if( ( RCC->CFGR0 & RCC_PLLXTPRE ) != ( uint32_t )RESET )
+                {
+#ifdef CH32F20x_D8W
+                    SystemCoreClock = ( ( HSE_VALUE >> 2 ) >> 1 ) * pllmull;
+#else
+                    SystemCoreClock = ( HSE_VALUE >> 1 ) * pllmull;
+#endif
+                }
+                else
+                {
+#ifdef CH32F20x_D8W
+                    SystemCoreClock = ( HSE_VALUE >> 2 ) * pllmull;
+#else
+                    SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+
+                }
+#endif
+            }
+
+            if( Pll_6_5 == 1 ) SystemCoreClock = ( SystemCoreClock / 2 );
+
+            break;
+        default:
+            SystemCoreClock = HSI_VALUE;
+            break;
+    }
+
+    tmp = AHBPrescTable[( ( RCC->CFGR0 & RCC_HPRE ) >> 4 )];
+    SystemCoreClock >>= tmp;
+}
+
+
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock( void )
+{
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+
+    /* If none of the define above is enabled, the HSI is used as System clock
+     * source (default after reset)
+    */
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV1;
+
+         /* Select HSE as system clock source
+          *   CH32F20x_D6 (HSE=8Mhz)
+          *   CH32F20x_D8 (HSE=8Mhz)
+          *   CH32F20x_D8W (HSE=32Mhz)
+          */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_HSE;
+
+        /* Wait till HSE is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x04 )
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8Mhz)
+         *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8Mhz)
+         *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz(HSE=32Mhz)
+         */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8Mhz)
+         *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8Mhz)
+         *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz(HSE=32Mhz)
+         */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+         /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8Mhz)
+          *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8Mhz)
+          *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz(HSE=32Mhz)
+          */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+                                    RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8Mhz)
+         *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8Mhz)
+         *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz(HSE=32Mhz)
+         */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+                                    RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if defined (CH32F20x_D8W)
+		RCC->CFGR0 |= (uint32_t)(3<<22);
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+     /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8Mhz)
+      *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8Mhz)
+      *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz(HSE=32Mhz)
+      */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8Mhz)
+         *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8Mhz)
+         *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz(HSE=32Mhz)
+         */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+                                    RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 7 = 56 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15_EXTEN );
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+
+#endif
diff --git a/hw/bsp/ch32f20x/system_ch32f20x.h b/hw/bsp/ch32f20x/system_ch32f20x.h
new file mode 100644
index 000000000..cf2f5328b
--- /dev/null
+++ b/hw/bsp/ch32f20x/system_ch32f20x.h
@@ -0,0 +1,25 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32f20x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/08/08
+* Description        : CH32F20x Device Peripheral Access Layer System Header File.
+*******************************************************************************/
+#ifndef __SYSTEM_CH32F20x_H
+#define __SYSTEM_CH32F20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32F20x_SYSTEM_H */
diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.cmake b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.cmake
new file mode 100644
index 000000000..f6e47ba30
--- /dev/null
+++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.cmake
@@ -0,0 +1,8 @@
+set(LD_FLASH_SIZE 64K)
+set(LD_RAM_SIZE 20K)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_DUAL_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h
new file mode 100644
index 000000000..1fde4244c
--- /dev/null
+++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h
@@ -0,0 +1,25 @@
+/* metadata:
+   name: CH32V103R-R1-1v1
+   url: https://github.com/openwch/ch32v103/tree/main/SCHPCB/CH32V103R-R1-1v1
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT       GPIOA
+#define LED_PIN        GPIO_Pin_10
+#define LED_STATE_ON   0
+
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_Pin_1
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk
new file mode 100644
index 000000000..e594f42a7
--- /dev/null
+++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk
@@ -0,0 +1,5 @@
+CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
+
+LDFLAGS += \
+  -Wl,--defsym=__FLASH_SIZE=64K \
+  -Wl,--defsym=__RAM_SIZE=20K \
diff --git a/hw/bsp/ch32v10x/ch32v10x_conf.h b/hw/bsp/ch32v10x/ch32v10x_conf.h
new file mode 100644
index 000000000..939c0fbde
--- /dev/null
+++ b/hw/bsp/ch32v10x/ch32v10x_conf.h
@@ -0,0 +1,37 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V10x_CONF_H
+#define __CH32V10x_CONF_H
+
+#include "ch32v10x_adc.h"
+#include "ch32v10x_bkp.h"
+#include "ch32v10x_crc.h"
+#include "ch32v10x_dbgmcu.h"
+#include "ch32v10x_dma.h"
+#include "ch32v10x_exti.h"
+#include "ch32v10x_flash.h"
+#include "ch32v10x_gpio.h"
+#include "ch32v10x_i2c.h"
+#include "ch32v10x_iwdg.h"
+#include "ch32v10x_pwr.h"
+#include "ch32v10x_rcc.h"
+#include "ch32v10x_rtc.h"
+#include "ch32v10x_spi.h"
+#include "ch32v10x_tim.h"
+#include "ch32v10x_usart.h"
+#include "ch32v10x_wwdg.h"
+#include "ch32v10x_usb.h"
+#include "ch32v10x_usb_host.h"
+#include "ch32v10x_it.h"
+#include "ch32v10x_misc.h"
+
+#endif /* __CH32V10x_CONF_H */
diff --git a/hw/bsp/ch32v10x/ch32v10x_it.h b/hw/bsp/ch32v10x/ch32v10x_it.h
new file mode 100644
index 000000000..13afc2412
--- /dev/null
+++ b/hw/bsp/ch32v10x/ch32v10x_it.h
@@ -0,0 +1,15 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2022/08/20
+ * Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V10x_IT_H
+#define __CH32V10x_IT_H
+
+#endif /* __CH32V10x_IT_H */
diff --git a/hw/bsp/ch32v10x/family.c b/hw/bsp/ch32v10x/family.c
new file mode 100644
index 000000000..f25102494
--- /dev/null
+++ b/hw/bsp/ch32v10x/family.c
@@ -0,0 +1,152 @@
+/* metadata:
+   manufacturer: WCH
+*/
+
+#include <stdio.h>
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#include "ch32v10x.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+__attribute__((interrupt)) __attribute__((used))
+void USBHD_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBFS
+  tud_int_handler(0);
+  #endif
+}
+
+__attribute__((interrupt)) __attribute__((used))
+void USBWakeUp_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBFS
+  tud_int_handler(0);
+  #endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+__attribute__((interrupt)) __attribute__((used))
+void SysTick_Handler(void) {
+  SysTick->CNTL0 = SysTick->CNTL1 = SysTick->CNTL2 = SysTick->CNTL3 = 0;
+  SysTick->CNTH0 = SysTick->CNTH1 = SysTick->CNTH2 = SysTick->CNTH3 = 0;
+  system_ticks++;
+}
+
+uint32_t SysTick_Config(uint32_t ticks) {
+  NVIC_EnableIRQ(SysTicK_IRQn);
+  SysTick->CTLR = 0;
+  SysTick->CNTL0 = SysTick->CNTL1 = SysTick->CNTL2 = SysTick->CNTL3 = 0;
+  SysTick->CNTH0 = SysTick->CNTH1 = SysTick->CNTH2 = SysTick->CNTH3 = 0;
+
+  SysTick->CMPLR0 = (u8)(ticks & 0xFF);
+  SysTick->CMPLR1 = (u8)(ticks >> 8);
+  SysTick->CMPLR2 = (u8)(ticks >> 16);
+  SysTick->CMPLR3 = (u8)(ticks >> 24);
+
+  SysTick->CMPHR0 = SysTick->CMPHR1 = SysTick->CMPHR2 =   SysTick->CMPHR3 = 0;
+  SysTick->CTLR = 1;
+  return 0;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void board_init(void) {
+  __disable_irq();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+  EXTEN->EXTEN_CTR |= EXTEN_USBFS_IO_EN;
+  uint8_t usb_div;
+  switch (SystemCoreClock) {
+    case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break;
+    case 72000000: usb_div = RCC_USBCLKSource_PLLCLK_1Div5; break;
+    default: TU_ASSERT(0,); break;
+  }
+  RCC_USBCLKConfig(usb_div);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBFS, ENABLE);
+
+  #ifdef LED_PIN
+  GPIO_InitTypeDef led_init = {
+      .GPIO_Pin = LED_PIN,
+      .GPIO_Mode = GPIO_Mode_Out_OD,
+      .GPIO_Speed = GPIO_Speed_50MHz,
+  };
+  GPIO_Init(LED_PORT, &led_init);
+  #endif
+
+  #ifdef BUTTON_PIN
+  GPIO_InitTypeDef button_init = {
+      .GPIO_Pin = BUTTON_PIN,
+      .GPIO_Mode = GPIO_Mode_IPU,
+      .GPIO_Speed = GPIO_Speed_50MHz,
+  };
+  GPIO_Init(BUTTON_PORT, &button_init);
+  #endif
+
+  // UART TX is PA9
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+  GPIO_InitTypeDef usart_init = {
+    .GPIO_Pin = GPIO_Pin_9,
+    .GPIO_Speed = GPIO_Speed_50MHz,
+    .GPIO_Mode = GPIO_Mode_AF_PP,
+  };
+  GPIO_Init(GPIOA, &usart_init);
+
+  USART_InitTypeDef usart = {
+    .USART_BaudRate = 115200,
+    .USART_WordLength = USART_WordLength_8b,
+    .USART_StopBits = USART_StopBits_1,
+    .USART_Parity = USART_Parity_No,
+    .USART_Mode = USART_Mode_Tx,
+    .USART_HardwareFlowControl = USART_HardwareFlowControl_None,
+  };
+  USART_Init(USART1, &usart);
+  USART_Cmd(USART1, ENABLE);
+
+  __enable_irq();
+
+  board_led_write(true);
+}
+
+void board_led_write(bool state) {
+  GPIO_WriteBit(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+  const char *bufc = (const char *) buf;
+  for (int i = 0; i < len; i++) {
+    while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+    USART_SendData(USART1, *bufc++);
+  }
+
+  return len;
+}
diff --git a/hw/bsp/ch32v10x/family.cmake b/hw/bsp/ch32v10x/family.cmake
new file mode 100644
index 000000000..a73898050
--- /dev/null
+++ b/hw/bsp/ch32v10x/family.cmake
@@ -0,0 +1,116 @@
+include_guard()
+
+#set(UF2_FAMILY_ID 0x699b62ec)
+set(CH32_FAMILY ch32v10x)
+set(SDK_DIR ${TOP}/hw/mcu/wch/ch32v103)
+set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS CH32V103 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${CH32_FAMILY}.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_SRC_DIR}/Core/core_riscv.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_SRC_DIR}/Core
+    ${SDK_SRC_DIR}/Peripheral/inc
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -mcmodel=medany
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE}
+      -Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE}
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_CH32V103)
+
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_openocd_wch(${TARGET})
+
+  #family_add_uf2(${TARGET} ${UF2_FAMILY_ID})
+  #family_flash_uf2(${TARGET} ${UF2_FAMILY_ID})
+endfunction()
diff --git a/hw/bsp/ch32v10x/family.mk b/hw/bsp/ch32v10x/family.mk
new file mode 100644
index 000000000..d96d5012e
--- /dev/null
+++ b/hw/bsp/ch32v10x/family.mk
@@ -0,0 +1,53 @@
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-
+
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
+
+CH32_FAMILY = ch32v10x
+SDK_DIR = hw/mcu/wch/ch32v103
+SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= rv32imac-ilp32
+
+# Port0 use FSDev, Port1 use USBFS
+PORT ?= 0
+
+CFLAGS += \
+	-mcmodel=medany \
+	-ffat-lto-objects \
+	-flto \
+	-DCFG_TUSB_MCU=OPT_MCU_CH32V103
+
+# https://github.com/openwch/ch32v20x/pull/12
+CFLAGS += -Wno-error=strict-prototypes
+
+LDFLAGS_GCC += \
+	-nostdlib -nostartfiles \
+	--specs=nosys.specs --specs=nano.specs \
+
+LD_FILE = $(FAMILY_PATH)/linker/${CH32_FAMILY}.ld
+
+SRC_C += \
+	src/portable/wch/dcd_ch32_usbfs.c \
+	$(SDK_SRC_DIR)/Core/core_riscv.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c \
+
+SRC_S += $(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}.S
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(SDK_SRC_DIR)/Core \
+	$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc \
+
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
+
+OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
+flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v10x/linker/ch32v10x.ld b/hw/bsp/ch32v10x/linker/ch32v10x.ld
new file mode 100644
index 000000000..cd5c8dc17
--- /dev/null
+++ b/hw/bsp/ch32v10x/linker/ch32v10x.ld
@@ -0,0 +1,165 @@
+/* Define default values if not already defined */
+__FLASH_SIZE = DEFINED(__flash_size) ? __flash_size : 64K;
+__RAM_SIZE = DEFINED(__ram_size) ? __ram_size : 20K;
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __FLASH_SIZE
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __RAM_SIZE
+}
+
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+SECTIONS
+{
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+  } >FLASH AT>FLASH
+
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH
+
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH
+
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH
+
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH
+
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH
+
+	.dlalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+		*(.sdata2.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+    } >RAM
+
+}
diff --git a/hw/bsp/ch32v10x/system_ch32v10x.c b/hw/bsp/ch32v10x/system_ch32v10x.c
new file mode 100644
index 000000000..b083b83b4
--- /dev/null
+++ b/hw/bsp/ch32v10x/system_ch32v10x.c
@@ -0,0 +1,600 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v10x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : CH32V10x Device Peripheral Access Layer System Source File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v10x.h"
+
+/*
+ * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+ * reset the HSI is used as SYSCLK source).
+ * If none of the define below is enabled, the HSI is used as System clock source.
+ */
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+#define SYSCLK_FREQ_72MHz_HSE  72000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* ch32v10x_system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit(void)
+{
+    RCC->CTLR |= (uint32_t)0x00000001;
+    RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+    RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+    RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+    RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+    RCC->INTR = 0x009F0000;
+    SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate(void)
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+    tmp = RCC->CFGR0 & RCC_SWS;
+
+    switch(tmp)
+    {
+        case 0x00:
+            SystemCoreClock = HSI_VALUE;
+            break;
+        case 0x04:
+            SystemCoreClock = HSE_VALUE;
+            break;
+        case 0x08:
+            pllmull = RCC->CFGR0 & RCC_PLLMULL;
+            pllsource = RCC->CFGR0 & RCC_PLLSRC;
+            pllmull = (pllmull >> 18) + 2;
+            if(pllsource == 0x00)
+            {
+                if( EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE )
+                {
+                    SystemCoreClock = ( HSI_VALUE ) * pllmull;
+                }
+                else
+                {
+                    SystemCoreClock = ( HSI_VALUE >> 1 ) * pllmull;
+                }
+            }
+            else
+            {
+                if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+                {
+                    SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+                }
+                else
+                {
+                    SystemCoreClock = HSE_VALUE * pllmull;
+                }
+            }
+            break;
+        default:
+            SystemCoreClock = HSI_VALUE;
+            break;
+    }
+
+    tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+    SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+    //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+
+#endif
+
+    /* If none of the define above is enabled, the HSI is used as System clock
+     * source (default after reset)
+     */
+}
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+        /* Flash 0 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+        /* Select HSE as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
+
+        /* Wait till HSE is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 1 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 2 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7);
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 2 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* Enable Prefetch Buffer */
+    FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+    FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* Enable Prefetch Buffer */
+    FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+    FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 56 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* Enable Prefetch Buffer */
+    FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+    FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#endif
diff --git a/hw/bsp/ch32v10x/system_ch32v10x.h b/hw/bsp/ch32v10x/system_ch32v10x.h
new file mode 100644
index 000000000..d15624520
--- /dev/null
+++ b/hw/bsp/ch32v10x/system_ch32v10x.h
@@ -0,0 +1,29 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v10x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : CH32V10x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_CH32V10x_H
+#define __SYSTEM_CH32V10x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V10x_SYSTEM_H */
diff --git a/hw/bsp/ch32v10x/wch-riscv.cfg b/hw/bsp/ch32v10x/wch-riscv.cfg
new file mode 100644
index 000000000..aa35aa9c5
--- /dev/null
+++ b/hw/bsp/ch32v10x/wch-riscv.cfg
@@ -0,0 +1,17 @@
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake
new file mode 100644
index 000000000..4aae6bdc2
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT D6)
+
+# 64KB zero-wait, 224KB total flash
+#set(LD_FLASH_SIZE 64K)
+set(LD_FLASH_SIZE 224K)
+set(LD_RAM_SIZE 20K)
+
+# set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${CH32_FAMILY}_tinyuf2.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    SYSCLK_FREQ_144MHz_HSE=144000000
+    CFG_EXAMPLE_MSC_DUAL_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
new file mode 100644
index 000000000..256958088
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
@@ -0,0 +1,26 @@
+/* metadata:
+   name: CH32V203C-R0-1v0
+   url: https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT       GPIOA
+#define LED_PIN        GPIO_Pin_0
+#define LED_STATE_ON   0
+
+#define UART_DEV        USART1
+#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+#define UART_TX_PIN     GPIO_Pin_9
+#define UART_RX_PIN     GPIO_Pin_10
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk
new file mode 100644
index 000000000..bdd15f737
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = D6
+
+CFLAGS += \
+  -DSYSCLK_FREQ_144MHz_HSE=144000000 \
+  -DCH32_FLASH_ENHANCE_READ_MODE=1 \
+  -DCFG_EXAMPLE_MSC_DUAL_READONLY \
+
+# 64KB zero-wait, 224KB total flash
+LDFLAGS += \
+  -Wl,--defsym=__FLASH_SIZE=224K \
+  -Wl,--defsym=__RAM_SIZE=20K \
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake
new file mode 100644
index 000000000..ecb8b378f
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT D6)
+
+# 32KB zero-wait, 224KB total flash
+#set(LD_FLASH_SIZE 32K)
+set(LD_FLASH_SIZE 224K)
+set(LD_RAM_SIZE 10K)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    SYSCLK_FREQ_144MHz_HSI=144000000
+    CFG_EXAMPLE_MSC_DUAL_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h
new file mode 100644
index 000000000..827226d80
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h
@@ -0,0 +1,26 @@
+/* metadata:
+   name: CH32V203G-R0-1v0
+   url: https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT       GPIOA
+#define LED_PIN        GPIO_Pin_0
+#define LED_STATE_ON   0
+
+#define UART_DEV        USART2
+#define UART_CLOCK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE)
+#define UART_TX_PIN     GPIO_Pin_2
+#define UART_RX_PIN     GPIO_Pin_3
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk
new file mode 100644
index 000000000..f71f53478
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = D6
+
+CFLAGS += \
+  -DSYSCLK_FREQ_144MHz_HSI=144000000 \
+  -DCH32_FLASH_ENHANCE_READ_MODE=1 \
+  -DCFG_EXAMPLE_MSC_DUAL_READONLY \
+
+# 32KB zero-wait, 224KB total flash
+LDFLAGS += \
+  -Wl,--defsym=__FLASH_SIZE=224K \
+  -Wl,--defsym=__RAM_SIZE=10K \
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake b/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
new file mode 100644
index 000000000..6c7712cdd
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT D6)
+
+# 64KB zero-wait, 224KB total flash
+set(LD_FLASH_SIZE 64K)
+#set(LD_FLASH_SIZE 224K)
+set(LD_RAM_SIZE 20K)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    SYSCLK_FREQ_144MHz_HSE=144000000
+    CFG_EXAMPLE_MSC_DUAL_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
new file mode 100644
index 000000000..f02fceced
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
@@ -0,0 +1,26 @@
+/* metadata:
+   name: nanoCH32V203
+   url: https://github.com/wuxx/nanoCH32V203
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT       GPIOA
+#define LED_PIN        GPIO_Pin_15
+#define LED_STATE_ON   0
+
+#define UART_DEV        USART1
+#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+#define UART_TX_PIN     GPIO_Pin_9
+#define UART_RX_PIN     GPIO_Pin_10
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk b/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk
new file mode 100644
index 000000000..362aace47
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = D6
+
+CFLAGS += \
+  -DSYSCLK_FREQ_144MHz_HSE=144000000 \
+	-DCH32_FLASH_ENHANCE_READ_MODE=1 \
+  -DCFG_EXAMPLE_MSC_DUAL_READONLY \
+
+# 64KB zero-wait , 224KB total flash
+LDFLAGS += \
+  -Wl,--defsym=__FLASH_SIZE=224K \
+  -Wl,--defsym=__RAM_SIZE=20K \
diff --git a/hw/bsp/ch32v20x/ch32v20x_conf.h b/hw/bsp/ch32v20x/ch32v20x_conf.h
new file mode 100644
index 000000000..949297fe6
--- /dev/null
+++ b/hw/bsp/ch32v20x/ch32v20x_conf.h
@@ -0,0 +1,36 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_CONF_H
+#define __CH32V20x_CONF_H
+
+#include "ch32v20x_adc.h"
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_can.h"
+#include "ch32v20x_crc.h"
+#include "ch32v20x_dbgmcu.h"
+#include "ch32v20x_dma.h"
+#include "ch32v20x_exti.h"
+#include "ch32v20x_flash.h"
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_iwdg.h"
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+#include "ch32v20x_rtc.h"
+#include "ch32v20x_spi.h"
+#include "ch32v20x_tim.h"
+#include "ch32v20x_usart.h"
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_it.h"
+#include "ch32v20x_misc.h"
+
+#endif /* __CH32V20x_CONF_H */
diff --git a/hw/bsp/ch32v20x/ch32v20x_it.h b/hw/bsp/ch32v20x/ch32v20x_it.h
new file mode 100644
index 000000000..e49c61ae2
--- /dev/null
+++ b/hw/bsp/ch32v20x/ch32v20x_it.h
@@ -0,0 +1,15 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_IT_H
+#define __CH32V20x_IT_H
+
+#endif /* __CH32V20x_IT_H */
diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c
new file mode 100644
index 000000000..5f52d9447
--- /dev/null
+++ b/hw/bsp/ch32v20x/family.c
@@ -0,0 +1,213 @@
+/* metadata:
+manufacturer: WCH
+*/
+
+#include <stdio.h>
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#include "ch32v20x.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+/* CH32v203 depending on variants can support 2 USB IPs: FSDEV and USBFS.
+ * By default, we use FSDEV, but you can explicitly select by define:
+ * - CFG_TUD_WCH_USBIP_FSDEV
+ * - CFG_TUD_WCH_USBIP_USBFS
+ */
+
+// USBFS
+__attribute__((interrupt)) __attribute__((used))
+void USBHD_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBFS
+  tud_int_handler(0);
+  #endif
+}
+
+__attribute__((interrupt)) __attribute__((used))
+void USBHDWakeUp_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBFS
+  tud_int_handler(0);
+  #endif
+}
+
+// USBD (fsdev)
+__attribute__((interrupt)) __attribute__((used))
+void USB_LP_CAN1_RX0_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_FSDEV
+  tud_int_handler(0);
+  #endif
+}
+
+__attribute__((interrupt)) __attribute__((used))
+void USB_HP_CAN1_TX_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_FSDEV
+  tud_int_handler(0);
+  #endif
+
+}
+
+__attribute__((interrupt)) __attribute__((used))
+void USBWakeUp_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_FSDEV
+  tud_int_handler(0);
+  #endif
+}
+
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+__attribute__((interrupt))
+void SysTick_Handler(void) {
+  SysTick->SR = 0;
+  system_ticks++;
+}
+
+uint32_t SysTick_Config(uint32_t ticks) {
+  NVIC_EnableIRQ(SysTicK_IRQn);
+  SysTick->CTLR = 0;
+  SysTick->SR = 0;
+  SysTick->CNT = 0;
+  SysTick->CMP = ticks - 1;
+  SysTick->CTLR = 0xF;
+  return 0;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void board_init(void) {
+  __disable_irq();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+  GPIO_InitTypeDef GPIO_InitStructure = {
+    .GPIO_Pin = LED_PIN,
+    .GPIO_Mode = GPIO_Mode_Out_OD,
+    .GPIO_Speed = GPIO_Speed_10MHz,
+  };
+  GPIO_Init(LED_PORT, &GPIO_InitStructure);
+
+#ifdef UART_DEV
+  UART_CLOCK_EN();
+  GPIO_InitTypeDef usart_init = {
+    .GPIO_Pin = UART_TX_PIN,
+    .GPIO_Speed = GPIO_Speed_50MHz,
+    .GPIO_Mode = GPIO_Mode_AF_PP,
+  };
+  GPIO_Init(GPIOA, &usart_init);
+
+  USART_InitTypeDef usart = {
+    .USART_BaudRate = 115200,
+    .USART_WordLength = USART_WordLength_8b,
+    .USART_StopBits = USART_StopBits_1,
+    .USART_Parity = USART_Parity_No,
+    .USART_Mode = USART_Mode_Tx,
+    .USART_HardwareFlowControl = USART_HardwareFlowControl_None,
+  };
+  USART_Init(UART_DEV, &usart);
+  USART_Cmd(UART_DEV, ENABLE);
+#endif
+
+  // USB init
+  uint8_t usb_div;
+  switch (SystemCoreClock) {
+    case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break;
+    case 96000000: usb_div = RCC_USBCLKSource_PLLCLK_Div2; break;
+    case 144000000: usb_div = RCC_USBCLKSource_PLLCLK_Div3; break;
+    default: TU_ASSERT(0,); break;
+  }
+  RCC_USBCLKConfig(usb_div);
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);  // FSDEV
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); // USB FS
+
+  __enable_irq();
+}
+
+void board_reset_to_bootloader(void) {
+//   board_led_write(true);
+//
+//   __disable_irq();
+//
+// #if CFG_TUD_ENABLED
+//   tud_deinit(0);
+//   RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, ENABLE);
+//   RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, DISABLE);
+// #endif
+//
+//   SysTick->CTLR = 0;
+//   for (int i = WWDG_IRQn; i< DMA1_Channel8_IRQn; i++) {
+//     NVIC_DisableIRQ(i);
+//   }
+//
+//   __enable_irq();
+//
+//   // define function pointer to BOOT ROM address
+//   void (*bootloader_entry)(void) = (void (*)(void))0x1FFF8000;
+//
+//   bootloader_entry();
+//
+//   board_led_write(false);
+
+  // while(1) { }
+}
+
+void board_led_write(bool state) {
+  GPIO_WriteBit(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  return false;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t* ch32_uuid = ((volatile uint32_t*) 0x1FFFF7E8UL);
+  uint32_t* serial_32 = (uint32_t*) (uintptr_t) id;
+  serial_32[0] = ch32_uuid[0];
+  serial_32[1] = ch32_uuid[1];
+  serial_32[2] = ch32_uuid[2];
+
+  return 12;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
+  const char *bufc = (const char *) buf;
+  for (int i = 0; i < len; i++) {
+    while (USART_GetFlagStatus(UART_DEV, USART_FLAG_TC) == RESET);
+    USART_SendData(UART_DEV, *bufc++);
+  }
+#else
+  (void) buf; (void) len;
+#endif
+
+  return len;
+}
+
+//--------------------------------------------------------------------
+// Neopixel
+//--------------------------------------------------------------------
diff --git a/hw/bsp/ch32v20x/family.cmake b/hw/bsp/ch32v20x/family.cmake
new file mode 100644
index 000000000..a5976e0ea
--- /dev/null
+++ b/hw/bsp/ch32v20x/family.cmake
@@ -0,0 +1,143 @@
+include_guard()
+
+set(UF2_FAMILY_ID 0x699b62ec)
+set(CH32_FAMILY ch32v20x)
+set(SDK_DIR ${TOP}/hw/mcu/wch/${CH32_FAMILY})
+set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS CH32V20X CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
+
+# Port0 use FSDev, Port1 use USBFS
+if (NOT DEFINED PORT)
+  set(PORT 0)
+endif()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${CH32_FAMILY}.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}_${MCU_VARIANT}.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_SRC_DIR}/Core/core_riscv.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_flash.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_SRC_DIR}/Core
+    ${SDK_SRC_DIR}/Peripheral/inc
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CH32V20x_${MCU_VARIANT}
+    )
+
+  if (PORT EQUAL 0)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_TUD_WCH_USBIP_FSDEV=1
+      )
+  elseif (PORT EQUAL 1)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_TUD_WCH_USBIP_USBFS=1
+      )
+  else()
+    message(FATAL_ERROR "Invalid PORT ${PORT}")
+  endif()
+
+  update_board(${BOARD_TARGET})
+
+  if (LD_FLASH_SIZE STREQUAL 224K)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CH32_FLASH_ENHANCE_READ_MODE=1
+      )
+  endif()
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -mcmodel=medany
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      -Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE}
+      -Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE}
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for CH32v")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_CH32V20X)
+
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_openocd_wch(${TARGET})
+  family_flash_wlink_rs(${TARGET})
+
+  #family_add_uf2(${TARGET} ${UF2_FAMILY_ID})
+  #family_flash_uf2(${TARGET} ${UF2_FAMILY_ID})
+endfunction()
diff --git a/hw/bsp/ch32v20x/family.mk b/hw/bsp/ch32v20x/family.mk
new file mode 100644
index 000000000..08761dc0d
--- /dev/null
+++ b/hw/bsp/ch32v20x/family.mk
@@ -0,0 +1,64 @@
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-
+
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
+
+CH32_FAMILY = ch32v20x
+SDK_DIR = hw/mcu/wch/ch32v20x
+SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= rv32imac-ilp32
+
+# Port0 use FSDev, Port1 use USBFS
+PORT ?= 0
+
+CFLAGS += \
+	-mcmodel=medany \
+	-ffat-lto-objects \
+	-flto \
+	-DCH32V20x_${MCU_VARIANT} \
+	-DCFG_TUSB_MCU=OPT_MCU_CH32V20X
+
+# https://github.com/openwch/ch32v20x/pull/12
+CFLAGS += -Wno-error=strict-prototypes
+
+ifeq ($(PORT),0)
+  $(info "Using FSDEV driver")
+  CFLAGS += -DCFG_TUD_WCH_USBIP_FSDEV=1
+else
+  $(info "Using USBFS driver")
+  CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1
+endif
+
+LDFLAGS_GCC += \
+	-nostdlib -nostartfiles \
+	--specs=nosys.specs --specs=nano.specs \
+
+LD_FILE = $(FAMILY_PATH)/linker/${CH32_FAMILY}.ld
+
+SRC_C += \
+	src/portable/wch/dcd_ch32_usbfs.c \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	$(SDK_SRC_DIR)/Core/core_riscv.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c \
+
+SRC_S += $(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}_${MCU_VARIANT}.S
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(SDK_SRC_DIR)/Core \
+	$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc \
+
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
+
+OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
+flash: flash-wlink-rs
+#flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v20x/linker/ch32v20x.ld b/hw/bsp/ch32v20x/linker/ch32v20x.ld
new file mode 100644
index 000000000..f84808b0d
--- /dev/null
+++ b/hw/bsp/ch32v20x/linker/ch32v20x.ld
@@ -0,0 +1,164 @@
+/* Define default values if not already defined */
+__flash_size = DEFINED(__FLASH_SIZE) ? __FLASH_SIZE : 64K;
+__ram_size = DEFINED(__RAM_SIZE) ? __RAM_SIZE : 20K;
+__stack_size = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2048;
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __flash_size
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __ram_size
+}
+
+ENTRY( _start )
+
+PROVIDE( _stack_size = __stack_size );
+
+SECTIONS
+{
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+  } >FLASH AT>FLASH
+
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH
+
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH
+
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH
+
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH
+
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH
+
+	.dlalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+		*(.sdata2.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+    } >RAM
+
+}
diff --git a/hw/bsp/ch32v20x/system_ch32v20x.c b/hw/bsp/ch32v20x/system_ch32v20x.c
new file mode 100644
index 000000000..d32ee8d17
--- /dev/null
+++ b/hw/bsp/ch32v20x/system_ch32v20x.c
@@ -0,0 +1,986 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Source File.
+ *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ *                      For HSE = 8Mhz (other CH32V203x)
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x.h"
+
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source.
+*/
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+// #define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+// #define SYSCLK_FREQ_72MHz_HSE  72000000
+// #define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  // Enable Flash enhance read mode for full 224KB
+#if defined(CH32_FLASH_ENHANCE_READ_MODE) && CH32_FLASH_ENHANCE_READ_MODE == 1
+  FLASH->KEYR = 0x45670123; // FLASH_Unlock_Fast();
+  FLASH->KEYR = 0xCDEF89AB;
+
+  FLASH->CTLR |= (1 << 24); // Enhanced Read Mode
+
+  FLASH->CTLR |= (1 << 15); // FLASH_Lock_Fast();
+#endif
+
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;
+  SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if(pllmull == 17) pllmull = 18;
+
+      if (pllsource == 0x00)
+      {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              SystemCoreClock = HSI_VALUE * pllmull;
+          }
+          else{
+              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+          }
+      }
+      else
+      {
+#if defined (CH32V20x_D8W)
+        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+        {
+          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+        }
+        else
+#endif
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+        }
+        else
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+          SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset)
+	*/
+}
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+    /* Select HSE as system clock source
+     *  CH32V20x_D6 (HSE=8MHZ)
+     *  CH32V20x_D8 (HSE=32MHZ)
+     *  CH32V20x_D8W (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  {
+		/* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+		 */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+		/*
+		 * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+		 */
+  }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+		/*
+		 * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+		 */
+  }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+		/*
+		 * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+		 */
+  }
+}
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+#if defined (CH32V20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(3<<22);
+        /* HCLK = SYSCLK/2 */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
+         *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
+         *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
+         */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                          RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#endif
diff --git a/hw/bsp/ch32v20x/system_ch32v20x.h b/hw/bsp/ch32v20x/system_ch32v20x.h
new file mode 100644
index 000000000..eec7ccb15
--- /dev/null
+++ b/hw/bsp/ch32v20x/system_ch32v20x.h
@@ -0,0 +1,29 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_ch32v20x_H
+#define __SYSTEM_ch32v20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V20x_SYSTEM_H */
diff --git a/hw/bsp/ch32v20x/wch-riscv.cfg b/hw/bsp/ch32v20x/wch-riscv.cfg
new file mode 100644
index 000000000..aa35aa9c5
--- /dev/null
+++ b/hw/bsp/ch32v20x/wch-riscv.cfg
@@ -0,0 +1,17 @@
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake
new file mode 100644
index 000000000..9f5682042
--- /dev/null
+++ b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake
@@ -0,0 +1,4 @@
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC
+#    )
+endfunction()
diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
new file mode 100644
index 000000000..491347034
--- /dev/null
+++ b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
@@ -0,0 +1,55 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* metadata:
+   name: CH32V307V-R1-1v0
+   url: https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED: need to wire pin LED1 to PC0 in the J3 header
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_Pin_0
+#define LED_STATE_ON          0
+#define LED_CLOCK_EN()        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// Button: need to wire pin KEY to PC1 in the J3 header
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_Pin_1
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_CLOCK_EN()     do { } while(0) // same as LED clock, no need to do anything
+
+// TODO UART port
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk
new file mode 100644
index 000000000..4e91d8938
--- /dev/null
+++ b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk
@@ -0,0 +1 @@
+LD_FILE = $(FAMILY_PATH)/ch32v307.ld
diff --git a/hw/bsp/ch32v307/ch32v307.ld b/hw/bsp/ch32v307/ch32v307.ld
new file mode 100644
index 000000000..55bd10cd0
--- /dev/null
+++ b/hw/bsp/ch32v307/ch32v307.ld
@@ -0,0 +1,167 @@
+ENTRY( _start )
+
+__stack_size = 4096;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+
+SECTIONS
+{
+
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+  } >FLASH AT>FLASH
+
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH
+
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH
+
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH
+
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH
+
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH
+
+	.dlalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+		*(.sdata2.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+        __freertos_irq_stack_top = .;
+    } >RAM
+
+}
diff --git a/hw/bsp/ch32v307/ch32v30x_conf.h b/hw/bsp/ch32v307/ch32v30x_conf.h
new file mode 100644
index 000000000..0b86ad390
--- /dev/null
+++ b/hw/bsp/ch32v307/ch32v30x_conf.h
@@ -0,0 +1,38 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_conf.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Library configuration file.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_CONF_H
+#define __CH32V30x_CONF_H
+
+#include "ch32v30x_adc.h"
+#include "ch32v30x_bkp.h"
+#include "ch32v30x_can.h"
+#include "ch32v30x_crc.h"
+#include "ch32v30x_dac.h"
+#include "ch32v30x_dbgmcu.h"
+#include "ch32v30x_dma.h"
+#include "ch32v30x_exti.h"
+#include "ch32v30x_flash.h"
+#include "ch32v30x_fsmc.h"
+#include "ch32v30x_gpio.h"
+#include "ch32v30x_i2c.h"
+#include "ch32v30x_iwdg.h"
+#include "ch32v30x_pwr.h"
+#include "ch32v30x_rcc.h"
+#include "ch32v30x_rtc.h"
+#include "ch32v30x_sdio.h"
+#include "ch32v30x_spi.h"
+#include "ch32v30x_tim.h"
+#include "ch32v30x_usart.h"
+#include "ch32v30x_wwdg.h"
+#include "ch32v30x_it.h"
+#include "ch32v30x_misc.h"
+
+
+#endif /* __CH32V30x_CONF_H */
diff --git a/hw/bsp/ch32v307/ch32v30x_it.c b/hw/bsp/ch32v307/ch32v30x_it.c
new file mode 100644
index 000000000..c329c5613
--- /dev/null
+++ b/hw/bsp/ch32v307/ch32v30x_it.c
@@ -0,0 +1,47 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Main Interrupt Service Routines.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_it.h"
+
+void NMI_Handler(void) __attribute__((naked));
+void HardFault_Handler(void) __attribute__((naked));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handle(void){
+      __asm volatile ("call NMI_Handler_impl; mret");
+}
+
+__attribute__((used)) void NMI_Handler_impl(void)
+{
+
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void){
+      __asm volatile ("call HardFault_Handler_impl; mret");
+}
+
+__attribute__((used)) void HardFault_Handler_impl(void)
+{
+  while (1)
+  {
+  }
+}
diff --git a/hw/bsp/ch32v307/ch32v30x_it.h b/hw/bsp/ch32v307/ch32v30x_it.h
new file mode 100644
index 000000000..f3977a8be
--- /dev/null
+++ b/hw/bsp/ch32v307/ch32v30x_it.h
@@ -0,0 +1,16 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains the headers of the interrupt handlers.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_IT_H
+#define __CH32V30x_IT_H
+
+// #include "debug.h"
+
+
+#endif /* __CH32V30x_IT_H */
diff --git a/hw/bsp/ch32v307/debug_uart.c b/hw/bsp/ch32v307/debug_uart.c
new file mode 100644
index 000000000..2fd3a9d64
--- /dev/null
+++ b/hw/bsp/ch32v307/debug_uart.c
@@ -0,0 +1,119 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "debug_uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#include <ch32v30x.h>
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#define UART_RINGBUFFER_SIZE_TX 128
+#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
+
+static char tx_buf[UART_RINGBUFFER_SIZE_TX];
+static unsigned int tx_produce;
+static volatile unsigned int tx_consume;
+
+void USART1_IRQHandler(void) __attribute__((naked));
+void USART1_IRQHandler(void) {
+      __asm volatile ("call USART1_IRQHandler_impl; mret");
+}
+
+__attribute__((used)) void USART1_IRQHandler_impl(void)
+{
+	if(USART_GetITStatus(USART1, USART_IT_TC) != RESET)
+    {
+        USART_ClearITPendingBit(USART1, USART_IT_TC);
+
+		if(tx_consume != tx_produce) {
+			USART_SendData(USART1, tx_buf[tx_consume]);
+			tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
+		}
+    }
+
+}
+
+void uart_write(char c)
+{
+	unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
+
+    NVIC_DisableIRQ(USART1_IRQn);
+    if((tx_consume != tx_produce) || (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)) {
+		tx_buf[tx_produce] = c;
+		tx_produce = tx_produce_next;
+	} else {
+		USART_SendData(USART1, c);
+	}
+    NVIC_EnableIRQ(USART1_IRQn);
+}
+
+
+void uart_sync(void)
+{
+	while(tx_consume != tx_produce);
+}
+
+
+void usart_printf_init(uint32_t baudrate)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  USART_InitTypeDef USART_InitStructure;
+
+  tx_produce = 0;
+  tx_consume = 0;
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  USART_InitStructure.USART_BaudRate = baudrate;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Tx;
+
+  USART_Init(USART1, &USART_InitStructure);
+  USART_ITConfig(USART1, USART_IT_TC, ENABLE);
+  USART_Cmd(USART1, ENABLE);
+
+  NVIC_InitTypeDef NVIC_InitStructure = { 0 };
+  NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+}
diff --git a/hw/bsp/ch32v307/debug_uart.h b/hw/bsp/ch32v307/debug_uart.h
new file mode 100644
index 000000000..a7e070585
--- /dev/null
+++ b/hw/bsp/ch32v307/debug_uart.h
@@ -0,0 +1,31 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+
+void uart_write(char c);
+void uart_sync(void);
+void usart_printf_init(uint32_t baudrate);
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
new file mode 100644
index 000000000..48eb8a38c
--- /dev/null
+++ b/hw/bsp/ch32v307/family.c
@@ -0,0 +1,195 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: WCH
+*/
+
+#include "stdio.h"
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#include "debug_uart.h"
+#include "ch32v30x.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+// TODO maybe having FS as port0, HS as port1
+
+__attribute__((interrupt)) void USBHS_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBHS
+  tud_int_handler(0);
+  #endif
+}
+
+__attribute__((interrupt)) void OTG_FS_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBFS
+  tud_int_handler(0);
+  #endif
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+uint32_t SysTick_Config(uint32_t ticks) {
+  NVIC_EnableIRQ(SysTicK_IRQn);
+  SysTick->CTLR = 0;
+  SysTick->SR = 0;
+  SysTick->CNT = 0;
+  SysTick->CMP = ticks - 1;
+  SysTick->CTLR = 0xF;
+  return 0;
+}
+
+void board_init(void) {
+
+  /* Disable interrupts during init */
+  __disable_irq();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+  usart_printf_init(CFG_BOARD_UART_BAUDRATE);
+
+#ifdef CH32V30x_D8C
+  // v305/v307: Highspeed USB
+  RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
+  RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
+  RCC_USBHSConfig(RCC_USBPLL_Div2);
+  RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M);
+  RCC_USBHSPHYPLLALIVEcmd(ENABLE);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE);
+#endif
+
+  // Fullspeed USB
+  uint8_t otg_div;
+  switch (SystemCoreClock) {
+    case 48000000:  otg_div = RCC_OTGFSCLKSource_PLLCLK_Div1; break;
+    case 96000000:  otg_div = RCC_OTGFSCLKSource_PLLCLK_Div2; break;
+    case 144000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div3; break;
+    default: TU_ASSERT(0,); break;
+  }
+  RCC_OTGFSCLKConfig(otg_div);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE);
+
+  GPIO_InitTypeDef GPIO_InitStructure = {0};
+
+  // LED
+  LED_CLOCK_EN();
+  GPIO_InitStructure.GPIO_Pin = LED_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(LED_PORT, &GPIO_InitStructure);
+
+  // Button
+  BUTTON_CLOCK_EN();
+  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(BUTTON_PORT, &GPIO_InitStructure);
+
+  /* Enable interrupts globally */
+  __enable_irq();
+
+  board_delay(2);
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+__attribute__((interrupt)) void SysTick_Handler(void) {
+  SysTick->SR = 0;
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+#endif
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_WriteBit(LED_PORT, LED_PIN, state);
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  int txsize = len;
+  const char* bufc = (const char*) buf;
+  while (txsize--) {
+    uart_write(*bufc++);
+  }
+  uart_sync();
+  return len;
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief  Reports the name of the source file and the source line number
+ *         where the assert_param error has occurred.
+ * @param  file: pointer to the source file name
+ * @param  line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(char* file, uint32_t line) {
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line
+     number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line)
+   */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/hw/bsp/ch32v307/family.cmake b/hw/bsp/ch32v307/family.cmake
new file mode 100644
index 000000000..446e850c5
--- /dev/null
+++ b/hw/bsp/ch32v307/family.cmake
@@ -0,0 +1,128 @@
+include_guard()
+
+set(CH32_FAMILY ch32v30x)
+set(SDK_DIR ${TOP}/hw/mcu/wch/ch32v307)
+set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS CH32V307 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
+
+# default to highspeed, used to select USBFS / USBHS driver
+if (NOT DEFINED SPEED)
+  set(SPEED high)
+endif()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/ch32v307.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}_D8C.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_SRC_DIR}/Core/core_riscv.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${CH32_FAMILY}_it.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_SRC_DIR}/Core
+    ${SDK_SRC_DIR}/Peripheral/inc
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    )
+  if (SPEED STREQUAL high)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_TUD_WCH_USBIP_USBHS=1
+#      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      )
+  else ()
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_TUD_WCH_USBIP_USBFS=1
+      )
+  endif ()
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -msmall-data-limit=8
+      -mno-save-restore
+      -fmessage-length=0
+      -fsigned-char
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/debug_uart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_CH32V307)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/wch/dcd_ch32_usbhs.c
+    ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_openocd_wch(${TARGET})
+endfunction()
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
new file mode 100644
index 000000000..bf2732106
--- /dev/null
+++ b/hw/bsp/ch32v307/family.mk
@@ -0,0 +1,64 @@
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-
+
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
+
+CH32_FAMILY = ch32v30x
+SDK_DIR = hw/mcu/wch/ch32v307
+SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= rv32imac-ilp32
+
+# default to use high speed port, unless specified in board.mk or command line
+SPEED ?= high
+
+CFLAGS += \
+	-flto \
+	-msmall-data-limit=8 \
+	-mno-save-restore \
+	-fmessage-length=0 \
+	-fsigned-char \
+	-DCFG_TUSB_MCU=OPT_MCU_CH32V307 \
+
+# https://github.com/openwch/ch32v307/pull/90
+CFLAGS += -Wno-error=strict-prototypes
+
+ifeq ($(SPEED),high)
+  $(info "Using USBHS driver for HighSpeed mode")
+  CFLAGS += -DCFG_TUD_WCH_USBIP_USBHS=1
+else
+  $(info "Using USBFS driver for FullSpeed mode")
+  CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1
+endif
+
+LDFLAGS_GCC += \
+	-nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
+
+SRC_C += \
+	src/portable/wch/dcd_ch32_usbhs.c \
+	src/portable/wch/dcd_ch32_usbfs.c \
+	$(SDK_SRC_DIR)/Core/core_riscv.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c
+
+SRC_S += \
+	$(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}_D8C.S
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(SDK_SRC_DIR)/Core \
+	$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
+
+OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
+flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v307/system_ch32v30x.c b/hw/bsp/ch32v307/system_ch32v30x.c
new file mode 100644
index 000000000..23f783df4
--- /dev/null
+++ b/hw/bsp/ch32v307/system_ch32v30x.c
@@ -0,0 +1,776 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Source File.
+*                      For HSE = 8Mhz
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*********************************************************************************/
+#include "ch32v30x.h"
+
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source.
+*/
+// #define SYSCLK_FREQ_HSE    HSE_VALUE
+/* #define SYSCLK_FREQ_24MHz  24000000  */
+//#define SYSCLK_FREQ_48MHz  48000000
+/* #define SYSCLK_FREQ_56MHz  56000000  */
+//#define SYSCLK_FREQ_72MHz  72000000
+//#define SYSCLK_FREQ_96MHz  96000000
+//#define SYSCLK_FREQ_120MHz  120000000
+#define SYSCLK_FREQ_144MHz  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;          /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /* System Clock Frequency (Core Clock) */
+
+#elif defined SYSCLK_FREQ_96MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz;        /* System Clock Frequency (Core Clock) */
+
+#else /* HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;                /* System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+
+#elif defined SYSCLK_FREQ_96MHz
+  static void SetSysClockTo96(void);
+#elif defined SYSCLK_FREQ_120MHz
+  static void SetSysClockTo120(void);
+#elif defined SYSCLK_FREQ_144MHz
+  static void SetSysClockTo144(void);
+
+#endif
+
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+
+#ifdef CH32V30x_D8C
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR0 &= (uint32_t)0xF0FF0000;
+#endif
+
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+
+#ifdef CH32V30x_D8C
+  RCC->CTLR &= (uint32_t)0xEBFFFFFF;
+  RCC->INTR = 0x00FF0000;
+  RCC->CFGR2 = 0x00000000;
+#else
+  RCC->INTR = 0x009F0000;
+#endif
+  SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+#ifdef CH32V30x_D8
+          if(pllmull == 17) pllmull = 18;
+#else
+          if(pllmull == 2) pllmull = 18;
+          if(pllmull == 15){
+              pllmull = 13;  /* *6.5 */
+              Pll_6_5 = 1;
+          }
+          if(pllmull == 16) pllmull = 15;
+          if(pllmull == 17) pllmull = 16;
+#endif
+
+      if (pllsource == 0x00)
+      {
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#elif defined SYSCLK_FREQ_96MHz
+  SetSysClockTo96();
+#elif defined SYSCLK_FREQ_120MHz
+  SetSysClockTo120();
+#elif defined SYSCLK_FREQ_144MHz
+  SetSysClockTo144();
+
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset)
+    */
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+    /* Select HSE as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  {
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_24MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo24
+ *
+ * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN);
+#endif
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo48
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo56
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo72
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo96
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo120
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_144MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo144
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#endif
diff --git a/hw/bsp/ch32v307/system_ch32v30x.h b/hw/bsp/ch32v307/system_ch32v30x.h
new file mode 100644
index 000000000..ad81058c7
--- /dev/null
+++ b/hw/bsp/ch32v307/system_ch32v30x.h
@@ -0,0 +1,27 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Header File.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __SYSTEM_CH32V30x_H
+#define __SYSTEM_CH32V30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V30x_SYSTEM_H */
diff --git a/hw/bsp/ch32v307/wch-riscv.cfg b/hw/bsp/ch32v307/wch-riscv.cfg
new file mode 100644
index 000000000..aa35aa9c5
--- /dev/null
+++ b/hw/bsp/ch32v307/wch-riscv.cfg
@@ -0,0 +1,17 @@
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk
deleted file mode 100644
index b7796b9d8..000000000
--- a/hw/bsp/d5035_01/board.mk
+++ /dev/null
@@ -1,61 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-HWREV ?= 1
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mlong-calls \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__SAME51J19A__ \
-  -DCONF_CPU_FREQUENCY=80000000 \
-  -DCONF_GCLK_USB_FREQUENCY=48000000 \
-  -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
-  -DD5035_01=1 \
-  -DBOARD_NAME="\"D5035-01\"" \
-  -DSVC_Handler=SVCall_Handler \
-  -DHWREV=$(HWREV)
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
-
-SRC_C += \
-  src/portable/microchip/samd/dcd_samd.c \
-  hw/mcu/microchip/same51/gcc/gcc/startup_same51.c \
-  hw/mcu/microchip/same51/gcc/system_same51.c
-
-ifdef SYSCALLS
-ifneq ($(SYSCALLS),0)
-  SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
-endif
-endif
-
-ifdef LOG
-ifneq ($(LOG),0)
-  SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
-endif
-endif
-
-INC += \
-	$(TOP)/hw/mcu/microchip/same51/ \
-	$(TOP)/hw/mcu/microchip/same51/config \
-	$(TOP)/hw/mcu/microchip/same51/include \
-	$(TOP)/hw/mcu/microchip/same51/hal/include \
-	$(TOP)/hw/mcu/microchip/same51/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/same51/hpl/port \
-	$(TOP)/hw/mcu/microchip/same51/hri \
-	$(TOP)/hw/mcu/microchip/same51/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAME51J19
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/d5035_01/d5035_01.c b/hw/bsp/d5035_01/d5035_01.c
deleted file mode 100644
index f356851f7..000000000
--- a/hw/bsp/d5035_01/d5035_01.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Jean Gressmann <jean@0x42.de>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include <sam.h>
-#include "bsp/board.h"
-
-#include <hal/include/hal_gpio.h>
-
-#if CONF_CPU_FREQUENCY != 80000000
-#	error "CONF_CPU_FREQUENCY" must 80000000
-#endif
-
-#if CONF_GCLK_USB_FREQUENCY != 48000000
-#	error "CONF_GCLK_USB_FREQUENCY" must 48000000
-#endif
-
-#if !defined(HWREV)
-#	error Define "HWREV"
-#endif
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_0_Handler (void)
-{
-	tud_int_handler(0);
-}
-
-void USB_1_Handler (void)
-{
-	tud_int_handler(0);
-}
-
-void USB_2_Handler (void)
-{
-	tud_int_handler(0);
-}
-
-void USB_3_Handler (void)
-{
-	tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define LED_PIN PIN_PA02
-
-#if HWREV < 3
-# define BOARD_SERCOM SERCOM5
-#else
-# define BOARD_SERCOM SERCOM0
-#endif
-
-static inline void init_clock(void)
-{
-	/* AUTOWS is enabled by default in REG_NVMCTRL_CTRLA - no need to change the number of wait states when changing the core clock */
-#if HWREV == 1
-	/* configure XOSC1 for a 16MHz crystal connected to XIN1/XOUT1 */
-	OSCCTRL->XOSCCTRL[1].reg =
-		OSCCTRL_XOSCCTRL_STARTUP(6) |    // 1,953 ms
-		OSCCTRL_XOSCCTRL_RUNSTDBY |
-		OSCCTRL_XOSCCTRL_ENALC |
-		OSCCTRL_XOSCCTRL_IMULT(4) |
-		OSCCTRL_XOSCCTRL_IPTAT(3) |
-		OSCCTRL_XOSCCTRL_XTALEN |
-		OSCCTRL_XOSCCTRL_ENABLE;
-	while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
-
-	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 8, input = XOSC1 */
-	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
-	OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
-
-	OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 16, input = XOSC1 */
-	OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
-	OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
-#else // HWREV >= 1
-	/* configure XOSC0 for a 16MHz crystal connected to XIN0/XOUT0 */
-	OSCCTRL->XOSCCTRL[0].reg =
-		OSCCTRL_XOSCCTRL_STARTUP(6) |    // 1,953 ms
-		OSCCTRL_XOSCCTRL_RUNSTDBY |
-		OSCCTRL_XOSCCTRL_ENALC |
-		OSCCTRL_XOSCCTRL_IMULT(4) |
-		OSCCTRL_XOSCCTRL_IPTAT(3) |
-		OSCCTRL_XOSCCTRL_XTALEN |
-		OSCCTRL_XOSCCTRL_ENABLE;
-	while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
-
-	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 8, input = XOSC1 */
-	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
-	OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
-
-	OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 16, input = XOSC1 */
-	OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
-	OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
-#endif // HWREV
-
-	/* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
-	GCLK->GENCTRL[0].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DPLL0 |  /* DPLL0 */
-		GCLK_GENCTRL_IDC ;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
-
-	/* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */
-	GCLK->GENCTRL[1].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DPLL1 |
-		GCLK_GENCTRL_IDC ;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */
-
-	/* configure clock-generator 2 to use DPLL0 as source -> for use with SERCOM */
-	GCLK->GENCTRL[2].reg =
-		GCLK_GENCTRL_DIV(1) |	/* 80MHz */
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DPLL0 |
-		GCLK_GENCTRL_IDC ;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
-}
-
-static inline void uart_init(void)
-{
-#if HWREV < 3
-	/* configure SERCOM5 on PB02 */
-	PORT->Group[1].WRCONFIG.reg =
-		PORT_WRCONFIG_WRPINCFG |
-		PORT_WRCONFIG_WRPMUX |
-		PORT_WRCONFIG_PMUX(3) |    /* function D */
-		PORT_WRCONFIG_DRVSTR |
-		PORT_WRCONFIG_PINMASK(0x0004) | /* PB02 */
-		PORT_WRCONFIG_PMUXEN;
-
-	MCLK->APBDMASK.bit.SERCOM5_ = 1;
-	GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
-
-	SERCOM5->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
-	while(SERCOM5->USART.SYNCBUSY.bit.ENABLE);
-
-	SERCOM5->USART.CTRLA.reg  =  /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
-		SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
-//    SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
-		SERCOM_USART_CTRLA_DORD | /* LSB first */
-		SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
-		SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
-		SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
-
-	SERCOM5->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
-		SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
-	SERCOM5->USART.CTRLC.reg = 0x00;
-	// 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
-	SERCOM5->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
-
-//  SERCOM5->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
-	SERCOM5->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
-	while(SERCOM5->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
-#else
-/* configure SERCOM0 on PA08 */
-	PORT->Group[0].WRCONFIG.reg =
-		PORT_WRCONFIG_WRPINCFG |
-		PORT_WRCONFIG_WRPMUX |
-		PORT_WRCONFIG_PMUX(2) |    /* function C */
-		PORT_WRCONFIG_DRVSTR |
-		PORT_WRCONFIG_PINMASK(0x0100) | /* PA08 */
-		PORT_WRCONFIG_PMUXEN;
-
-	MCLK->APBAMASK.bit.SERCOM0_ = 1;
-	GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
-
-	SERCOM0->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
-	while(SERCOM0->USART.SYNCBUSY.bit.ENABLE);
-
-	SERCOM0->USART.CTRLA.reg  =  /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
-		SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
-//    SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
-		SERCOM_USART_CTRLA_DORD | /* LSB first */
-		SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
-		SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
-		SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
-
-	SERCOM0->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
-		SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
-	SERCOM0->USART.CTRLC.reg = 0x00;
-	// 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
-	SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
-
-//  SERCOM0->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
-	SERCOM0->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
-	while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
-#endif
-}
-
-static inline void uart_send_buffer(uint8_t const *text, size_t len)
-{
-	for (size_t i = 0; i < len; ++i) {
-		BOARD_SERCOM->USART.DATA.reg = text[i];
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
-	}
-}
-
-static inline void uart_send_str(const char* text)
-{
-	while (*text) {
-		BOARD_SERCOM->USART.DATA.reg = *text++;
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
-	}
-}
-
-
-void board_init(void)
-{
-	init_clock();
-
-	SystemCoreClock = CONF_CPU_FREQUENCY;
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-	SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-#endif
-
-	uart_init();
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " UART initialized\n");
-	tu_printf(BOARD_NAME " reset cause %#02x\n", RSTC->RCAUSE.reg);
-#endif
-
-	// Led init
-	gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(LED_PIN, 0);
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " LED pin configured\n");
-#endif
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-	// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-	NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-
-#if CFG_TUD_ENABLED
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " USB device enabled\n");
-#endif
-
-	/* USB clock init
-	 * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-	 * for low speed and full speed operation. */
-	hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
-	hri_mclk_set_AHBMASK_USB_bit(MCLK);
-	hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
-	// USB pin init
-	gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(PIN_PA24, false);
-	gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-	gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(PIN_PA25, false);
-	gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-	gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
-	gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
-
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " USB device configured\n");
-#endif
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-	gpio_set_pin_level(LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-	// this board has no button
-	return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-	(void) buf; (void) len;
-	return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-	if (len < 0) {
-		uart_send_str(buf);
-	} else {
-		uart_send_buffer(buf, len);
-	}
-	return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void)
-{
-	system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-	return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/hw/bsp/da14695_dk_usb/board.mk b/hw/bsp/da14695_dk_usb/board.mk
deleted file mode 100644
index e969c79c2..000000000
--- a/hw/bsp/da14695_dk_usb/board.mk
+++ /dev/null
@@ -1,55 +0,0 @@
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mthumb-interwork \
-  -mabi=aapcs \
-  -mcpu=cortex-m33+nodsp \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
-  -nostdlib \
-  -DCORE_M33 \
-  -DCFG_TUSB_MCU=OPT_MCU_DA1469X \
-  -DCFG_TUD_ENDPOINT0_SIZE=8\
-
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
-
-# While this is for da1469x chip, there is chance that da1468x chip family will also work
-SRC_C += \
-	src/portable/dialog/da146xx/dcd_da146xx.c \
-	$(MCU_FAMILY_DIR)/src/system_da1469x.c \
-	$(MCU_FAMILY_DIR)/src/da1469x_clock.c \
-	$(MCU_FAMILY_DIR)/src/hal_gpio.c \
-
-SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(MCU_FAMILY_DIR)/include \
-	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
-
-# For flash-jlink target
-JLINK_DEVICE = DA14695
-
-# flash using jlink but with some twists
-flash: flash-dialog
-
-flash-dialog: $(BUILD)/$(PROJECT).bin
-	@echo '#define SW_VERSION "v_1.0.0.1"' >$(BUILD)/version.h
-	@echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >>$(BUILD)/version.h
-	mkimage da1469x $(BUILD)/$(PROJECT).bin $(BUILD)/version.h $^.img
-	cp $(TOP)/hw/bsp/$(BOARD)/product_header.dump $(BUILD)/$(BOARD)-image.bin
-	cat $^.img >> $(BUILD)/$(BOARD)-image.bin
-	@echo r > $(BUILD)/$(BOARD).jlink
-	@echo halt >> $(BUILD)/$(BOARD).jlink
-	@echo loadfile $(BUILD)/$(BOARD)-image.bin 0x16000000 >> $(BUILD)/$(BOARD).jlink
-	@echo r >> $(BUILD)/$(BOARD).jlink
-	@echo go >> $(BUILD)/$(BOARD).jlink
-	@echo exit >> $(BUILD)/$(BOARD).jlink
-	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
-
diff --git a/hw/bsp/da1469x/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/da1469x/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..4d4379a6f
--- /dev/null
+++ b/hw/bsp/da1469x/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,150 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "DA1469xAB.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+#define configRUN_FREERTOS_SECURE_ONLY          1
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/da1469x/boards/da14695_dk_usb/board.cmake b/hw/bsp/da1469x/boards/da14695_dk_usb/board.cmake
new file mode 100644
index 000000000..f9ef2dc86
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da14695_dk_usb/board.cmake
@@ -0,0 +1,4 @@
+set(JLINK_DEVICE DA14695)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/da1469x/boards/da14695_dk_usb/board.h b/hw/bsp/da1469x/boards/da14695_dk_usb/board.h
new file mode 100644
index 000000000..c0810c2b6
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da14695_dk_usb/board.h
@@ -0,0 +1,15 @@
+/* metadata:
+   name: DA14695-00HQDEVKT-U
+   url: https://www.renesas.com/en/products/wireless-connectivity/bluetooth-low-energy/da14695-00hqdevkt-u-smartbond-da14695-bluetooth-low-energy-52-usb-development-kit
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PIN         33 // P1.1
+#define LED_STATE_ON    1
+
+#define BUTTON_PIN      6
+#define BUTTON_STATE_ACTIVE 1
+
+#endif
diff --git a/hw/bsp/da1469x/boards/da14695_dk_usb/board.mk b/hw/bsp/da1469x/boards/da14695_dk_usb/board.mk
new file mode 100644
index 000000000..1ca17ea00
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da14695_dk_usb/board.mk
@@ -0,0 +1 @@
+JLINK_DEVICE = DA14695
diff --git a/hw/bsp/da14695_dk_usb/syscfg/syscfg.h b/hw/bsp/da1469x/boards/da14695_dk_usb/syscfg/syscfg.h
similarity index 100%
rename from hw/bsp/da14695_dk_usb/syscfg/syscfg.h
rename to hw/bsp/da1469x/boards/da14695_dk_usb/syscfg/syscfg.h
diff --git a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.cmake b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.cmake
new file mode 100644
index 000000000..f6408b72b
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.cmake
@@ -0,0 +1,4 @@
+set(JLINK_DEVICE DA14699)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h
new file mode 100644
index 000000000..2b61e810e
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h
@@ -0,0 +1,17 @@
+/* metadata:
+   name: DA1469x Development Kit Pro
+   url: https://lpccs-docs.renesas.com/um-b-090-da1469x_getting_started/DA1469x_The_hardware/DA1469x_The_hardware.html
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PIN         33
+#define LED_STATE_ON    1
+
+#define BUTTON_PIN      6
+#define BUTTON_STATE_ACTIVE 0
+
+#define NEED_VBUS_MONITOR
+
+#endif
diff --git a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.mk b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.mk
new file mode 100644
index 000000000..40fe93b41
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.mk
@@ -0,0 +1,2 @@
+# For flash-jlink target
+JLINK_DEVICE = DA14699
diff --git a/hw/bsp/da1469x_dk_pro/syscfg/syscfg.h b/hw/bsp/da1469x/boards/da1469x_dk_pro/syscfg/syscfg.h
similarity index 100%
rename from hw/bsp/da1469x_dk_pro/syscfg/syscfg.h
rename to hw/bsp/da1469x/boards/da1469x_dk_pro/syscfg/syscfg.h
diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x/family.c
similarity index 79%
rename from hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
rename to hw/bsp/da1469x/family.c
index 13113fb95..a64ffce67 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ b/hw/bsp/da1469x/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenberg
@@ -24,25 +24,30 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+/* metadata:
+   manufacturer: Renesas
+*/
+
+#include "bsp/board_api.h"
+#include "board.h"
 #include <hal/hal_gpio.h>
 #include <mcu/mcu.h>
 
+#define LED_STATE_OFF   (1-LED_STATE_ON)
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-#if CFG_TUD_ENABLED
-// DA146xx driver function that must be called whenever VBUS changes
+// DA146xx driver function that must be called whenever VBUS changes.
 extern void tusb_vbus_changed(bool present);
 
+#if defined(NEED_VBUS_MONITOR) && CFG_TUD_ENABLED
 // VBUS change interrupt handler
-void VBUS_IRQHandler(void)
-{
+void VBUS_IRQHandler(void) {
   bool present = (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk) != 0;
   // Clear VBUS interrupt
   CRG_TOP->VBUS_IRQ_CLEAR_REG = 1;
@@ -54,22 +59,13 @@ void VBUS_IRQHandler(void)
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
-
-#define LED_PIN         33
-#define LED_STATE_ON    1
-#define LED_STATE_OFF   0
-
-#define BUTTON_PIN      6
-
-void UnhandledIRQ(void)
-{
+void UnhandledIRQ(void) {
   CRG_TOP->SYS_CTRL_REG = 0x80;
   __BKPT(1);
-  while(1);
+  while (1);
 }
 
-void board_init(void)
-{
+void board_init(void) {
   // LED
   hal_gpio_init_out(LED_PIN, LED_STATE_ON);
 
@@ -80,12 +76,13 @@ void board_init(void)
   hal_gpio_init_out(5, 0);
 
   // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_UP);
+  hal_gpio_init_in(BUTTON_PIN, BUTTON_STATE_ACTIVE ? HAL_GPIO_PULL_DOWN : HAL_GPIO_PULL_UP);
 
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
 #if CFG_TUD_ENABLED
+  #ifdef NEED_VBUS_MONITOR
   // Setup interrupt for both connect and disconnect
   CRG_TOP->VBUS_IRQ_MASK_REG = CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk |
                                CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk;
@@ -94,6 +91,10 @@ void board_init(void)
   // otherwise it could go unnoticed.
   NVIC_SetPendingIRQ(VBUS_IRQn);
   NVIC_EnableIRQ(VBUS_IRQn);
+  #else
+  // This board is USB powered there is no need to monitor VBUS line.  Notify driver that VBUS is present.
+  tusb_vbus_changed(true);
+  #endif
 
   /* Setup USB IRQ */
   NVIC_SetPriority(USB_IRQn, 2);
@@ -111,41 +112,35 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   hal_gpio_write(LED_PIN, state ? LED_STATE_ON : LED_STATE_OFF);
 }
 
-uint32_t board_button_read(void)
-{
-  // button is active LOW
-  return hal_gpio_read(BUTTON_PIN) ^ 1;
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == hal_gpio_read(BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void)buf;
-  (void)len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void)buf;
-  (void)len;
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
 
   return 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/da1469x/family.cmake b/hw/bsp/da1469x/family.cmake
new file mode 100644
index 000000000..20d6cbc44
--- /dev/null
+++ b/hw/bsp/da1469x/family.cmake
@@ -0,0 +1,140 @@
+include_guard()
+
+set(MCU_DIR ${TOP}/hw/mcu/dialog/da1469x)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(CMAKE_SYSTEM_CPU cortex-m33-nodsp CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(FAMILY_MCUS DA1469X CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/da1469x.ld)
+  endif ()
+
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/gcc_startup_da1469x.S)
+    set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${MCU_DIR}/src/system_da1469x.c
+    ${MCU_DIR}/src/da1469x_clock.c
+    ${MCU_DIR}/src/hal_gpio.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC -mthumb-interwork)
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CORE_M33
+    CFG_TUD_ENDPOINT0_SIZE=8
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    ${MCU_DIR}/include
+    ${MCU_DIR}/SDK_10.0.8.105/sdk/bsp/include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -L${NRFX_DIR}/mdk
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -L${NRFX_DIR}/mdk
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+
+function(family_flash_jlink_dialog TARGET)
+  set(JLINKEXE JLinkExe)
+  set(JLINK_IF swd)
+
+  # mkimage from sdk
+  set(MKIMAGE $ENV{HOME}/code/tinyusb-mcu-driver/dialog/SDK_10.0.8.105/binaries/mkimage)
+
+  file(GENERATE OUTPUT $<TARGET_FILE_DIR:${TARGET}>/version.h
+    CONTENT "#define SW_VERSION \"v_1.0.0.1\"
+#define SW_VERSION_DATE \"2024-07-17 17:55\""
+    )
+
+  file(GENERATE OUTPUT $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink
+    CONTENT "r
+halt
+loadfile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}-image.bin 0x16000000
+r
+go
+exit"
+  )
+
+  add_custom_target(${TARGET}-image
+    DEPENDS ${TARGET}
+    COMMAND ${MKIMAGE} da1469x $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin $<TARGET_FILE_DIR:${TARGET}>/version.h $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin.img
+    COMMAND cp ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/product_header.dump $<TARGET_FILE_DIR:${TARGET}>/${TARGET}-image.bin
+    COMMAND cat $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin.img >> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}-image.bin
+    )
+  add_custom_target(${TARGET}-jlink
+    DEPENDS ${TARGET}-image
+    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink
+    )
+endfunction()
+
+
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_DA1469X)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/dialog/da146xx/dcd_da146xx.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink_dialog(${TARGET})
+endfunction()
diff --git a/hw/bsp/da1469x/family.mk b/hw/bsp/da1469x/family.mk
new file mode 100644
index 000000000..f35fe2cb5
--- /dev/null
+++ b/hw/bsp/da1469x/family.mk
@@ -0,0 +1,62 @@
+MCU_DIR = hw/mcu/dialog/da1469x
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mthumb-interwork \
+  -mabi=aapcs \
+  -mcpu=cortex-m33+nodsp \
+  -mfloat-abi=hard \
+  -mfpu=fpv5-sp-d16 \
+  -DCORE_M33 \
+  -DCFG_TUSB_MCU=OPT_MCU_DA1469X \
+  -DCFG_TUD_ENDPOINT0_SIZE=8\
+
+LDFLAGS_GCC += \
+  -nostdlib \
+  --specs=nosys.specs --specs=nano.specs
+
+# All source paths should be relative to the top level.
+LD_FILE = $(FAMILY_PATH)/linker/da1469x.ld
+
+# While this is for da1469x chip, there is chance that da1468x chip family will also work
+SRC_C += \
+	src/portable/dialog/da146xx/dcd_da146xx.c \
+	${MCU_DIR}/src/system_da1469x.c \
+	${MCU_DIR}/src/da1469x_clock.c \
+	${MCU_DIR}/src/hal_gpio.c \
+
+SRC_S += $(FAMILY_PATH)/gcc_startup_da1469x.S
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/${MCU_DIR}/include \
+	$(TOP)/${MCU_DIR}/SDK_10.0.8.105/sdk/bsp/include
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
+
+# flash using jlink but with some twists
+flash: flash-dialog
+
+# SDK_BINARY_PATH is the path to the SDK binary files
+SDK_BINARY_PATH = $(HOME)/code/tinyusb-mcu-driver/dialog/SDK_10.0.8.105/binaries
+MKIMAGE = $(SDK_BINARY_PATH)/mkimage
+
+$(BUILD)/$(PROJECT)-image.bin: $(BUILD)/$(PROJECT).bin
+	@echo '#define SW_VERSION "v_1.0.0.1"' >$(BUILD)/version.h
+	@echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >> $(BUILD)/version.h
+	$(MKIMAGE) da1469x $^ $(BUILD)/version.h $^.img
+	cp $(TOP)/$(FAMILY_PATH)/product_header.dump $(BUILD)/$(PROJECT)-image.bin
+	cat $^.img >> $(BUILD)/$(PROJECT)-image.bin
+
+flash-dialog: $(BUILD)/$(PROJECT)-image.bin
+	@echo r > $(BUILD)/$(BOARD).jlink
+	@echo halt >> $(BUILD)/$(BOARD).jlink
+	@echo loadfile $^ 0x16000000 >> $(BUILD)/$(BOARD).jlink
+	@echo r >> $(BUILD)/$(BOARD).jlink
+	@echo go >> $(BUILD)/$(BOARD).jlink
+	@echo exit >> $(BUILD)/$(BOARD).jlink
+	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
diff --git a/hw/bsp/da14695_dk_usb/gcc_startup_da1469x.S b/hw/bsp/da1469x/gcc_startup_da1469x.S
similarity index 100%
rename from hw/bsp/da14695_dk_usb/gcc_startup_da1469x.S
rename to hw/bsp/da1469x/gcc_startup_da1469x.S
diff --git a/hw/bsp/da14695_dk_usb/da1469x.ld b/hw/bsp/da1469x/linker/da1469x.ld
similarity index 99%
rename from hw/bsp/da14695_dk_usb/da1469x.ld
rename to hw/bsp/da1469x/linker/da1469x.ld
index 96507d6e7..8cc1d9d99 100644
--- a/hw/bsp/da14695_dk_usb/da1469x.ld
+++ b/hw/bsp/da1469x/linker/da1469x.ld
@@ -242,4 +242,3 @@ SECTIONS
     /* Check that intvect is at the beginning of RAM */
     ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
 }
-
diff --git a/hw/bsp/da14695_dk_usb/product_header.dump b/hw/bsp/da1469x/product_header.dump
similarity index 100%
rename from hw/bsp/da14695_dk_usb/product_header.dump
rename to hw/bsp/da1469x/product_header.dump
diff --git a/hw/bsp/da1469x_dk_pro/board.mk b/hw/bsp/da1469x_dk_pro/board.mk
deleted file mode 100644
index 980fc422f..000000000
--- a/hw/bsp/da1469x_dk_pro/board.mk
+++ /dev/null
@@ -1,55 +0,0 @@
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mthumb-interwork \
-  -mabi=aapcs \
-  -mcpu=cortex-m33+nodsp \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
-  -nostdlib \
-  -DCORE_M33 \
-  -DCFG_TUSB_MCU=OPT_MCU_DA1469X \
-  -DCFG_TUD_ENDPOINT0_SIZE=8\
-
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
-
-# While this is for da1469x chip, there is chance that da1468x chip family will also work
-SRC_C += \
-	src/portable/dialog/da146xx/dcd_da146xx.c \
-	$(MCU_FAMILY_DIR)/src/system_da1469x.c \
-	$(MCU_FAMILY_DIR)/src/da1469x_clock.c \
-	$(MCU_FAMILY_DIR)/src/hal_gpio.c \
-
-SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(MCU_FAMILY_DIR)/include \
-	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
-
-# For flash-jlink target
-JLINK_DEVICE = DA14699
-
-# flash using jlink but with some twists
-flash: flash-dialog
-
-flash-dialog: $(BUILD)/$(PROJECT).bin
-	@echo '#define SW_VERSION "v_1.0.0.1"' >$(BUILD)/version.h
-	@echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >>$(BUILD)/version.h
-	mkimage da1469x $(BUILD)/$(PROJECT).bin $(BUILD)/version.h $^.img
-	cp $(TOP)/hw/bsp/$(BOARD)/product_header.dump $(BUILD)/$(BOARD)-image.bin
-	cat $^.img >> $(BUILD)/$(BOARD)-image.bin
-	@echo r > $(BUILD)/$(BOARD).jlink
-	@echo halt >> $(BUILD)/$(BOARD).jlink
-	@echo loadfile $(BUILD)/$(BOARD)-image.bin 0x16000000 >> $(BUILD)/$(BOARD).jlink
-	@echo r >> $(BUILD)/$(BOARD).jlink
-	@echo go >> $(BUILD)/$(BOARD).jlink
-	@echo exit >> $(BUILD)/$(BOARD).jlink
-	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
-
diff --git a/hw/bsp/da1469x_dk_pro/da1469x.ld b/hw/bsp/da1469x_dk_pro/da1469x.ld
deleted file mode 100644
index 96507d6e7..000000000
--- a/hw/bsp/da1469x_dk_pro/da1469x.ld
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-MEMORY
-{
-    /*
-     * Flash is remapped at 0x0 by 1st stage bootloader, but this is done with
-     * an offset derived from image header thus it is safer to use remapped
-     * address space at 0x0 instead of QSPI_M address space at 0x16000000.
-     * Bootloader partition is 32K, but 9K is currently reserved for product
-     * header (8K) and image header (1K).
-     * First 512 bytes of SYSRAM are remapped at 0x0 and used as ISR vector
-     * (there's no need to reallocate ISR vector) and thus cannot be used by
-     * application.
-     */
-
-    FLASH (r)  : ORIGIN = (0x00000000), LENGTH = (1024 * 1024)
-    RAM (rw)   : ORIGIN = (0x20000000), LENGTH = (512 * 1024)
-}
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __HeapBase
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __bssnz_start__
- *   __bssnz_end__
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    __text = .;
-
-    .text :
-    {
-        __isr_vector_start = .;
-        KEEP(*(.isr_vector))
-        /* ISR vector shall have exactly 512 bytes */
-        . = __isr_vector_start + 0x200;
-        __isr_vector_end = .;
-
-        *(.text)
-        *(.text.*)
-
-        *(.libcmac.rom)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        *(.eh_frame*)
-        . = ALIGN(4);
-    } > FLASH
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-        . = ALIGN(4);
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        . = ALIGN(4);
-    } > FLASH
-    __exidx_end = .;
-
-    .intvect :
-    {
-        . = ALIGN(4);
-        __intvect_start__ = .;
-        . = . + (__isr_vector_end - __isr_vector_start);
-        . = ALIGN(4);
-    } > RAM
-
-    .sleep_state (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(sleep_state)
-    } > RAM
-
-    /* This section will be zeroed by RTT package init */
-    .rtt (NOLOAD):
-    {
-        . = ALIGN(4);
-        *(.rtt)
-        . = ALIGN(4);
-    } > RAM
-
-    __text_ram_addr = LOADADDR(.text_ram);
-
-    .text_ram :
-    {
-        . = ALIGN(4);
-        __text_ram_start__ = .;
-        *(.text_ram*)
-        . = ALIGN(4);
-        __text_ram_end__ = .;
-    } > RAM AT > FLASH
-
-    __etext = LOADADDR(.data);
-
-    .data :
-    {
-        __data_start__ = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        *(.preinit_array)
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        *(SORT(.init_array.*))
-        *(.init_array)
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        *(SORT(.fini_array.*))
-        *(.fini_array)
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        *(.jcr)
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-    } > RAM AT > FLASH
-
-    .bssnz :
-    {
-        . = ALIGN(4);
-        __bssnz_start__ = .;
-        *(.bss.core.nz*)
-        . = ALIGN(4);
-        __bssnz_end__ = .;
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > RAM
-
-    .cmac (NOLOAD) :
-    {
-        . = ALIGN(0x400);
-        *(.libcmac.ram)
-    } > RAM
-
-    /* Heap starts after BSS */
-    . = ALIGN(8);
-    __HeapBase = .;
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    _ram_start = ORIGIN(RAM);
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Top of head is the bottom of the stack */
-    __HeapLimit = __StackLimit;
-    end = __HeapLimit;
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
-
-    /* Check that intvect is at the beginning of RAM */
-    ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
-}
-
diff --git a/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S b/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S
deleted file mode 100644
index d47fbcd97..000000000
--- a/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
- #include "syscfg/syscfg.h"
-
-    .syntax unified
-    .arch   armv7-m
-
-    .section .stack
-    .align  3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0xC00
-#endif
-    .equ    SYS_CTRL_REG,       0x50000024
-    .equ    CACHE_FLASH_REG,    0x100C0040
-    .equ    RESET_STAT_REG,     0x500000BC
-
-    .globl  __StackTop
-    .globl  __StackLimit
-__StackLimit:
-    .space  Stack_Size
-    .size   __StackLimit, . - __StackLimit
-__StackTop:
-    .size   __StackTop, . - __StackTop
-
-    .section .heap
-    .align  3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0
-#endif
-    .globl  __HeapBase
-    .globl  __HeapLimit
-__HeapBase:
-    .if     Heap_Size
-    .space  Heap_Size
-    .endif
-    .size   __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size   __HeapLimit, . - __HeapLimit
-
-    .section .isr_vector
-    .align 2
-    .globl  __isr_vector
-__isr_vector:
-    .long   __StackTop
-    .long   Reset_Handler
-    /* Cortex-M33 interrupts */
-    .long   NMI_Handler
-    .long   HardFault_Handler
-    .long   MemoryManagement_Handler
-    .long   BusFault_Handler
-    .long   UsageFault_Handler
-    .long   SecureFault_Handler
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   SVC_Handler
-    .long   DebugMonitor_Handler
-    .long   0                       /* Reserved */
-    .long   PendSV_Handler
-    .long   SysTick_Handler
-    /* DA1469x interrupts */
-    .long   SENSOR_NODE_IRQHandler
-    .long   DMA_IRQHandler
-    .long   CHARGER_STATE_IRQHandler
-    .long   CHARGER_ERROR_IRQHandler
-    .long   CMAC2SYS_IRQHandler
-    .long   UART_IRQHandler
-    .long   UART2_IRQHandler
-    .long   UART3_IRQHandler
-    .long   I2C_IRQHandler
-    .long   I2C2_IRQHandler
-    .long   SPI_IRQHandler
-    .long   SPI2_IRQHandler
-    .long   PCM_IRQHandler
-    .long   SRC_IN_IRQHandler
-    .long   SRC_OUT_IRQHandler
-    .long   USB_IRQHandler
-    .long   TIMER_IRQHandler
-    .long   TIMER2_IRQHandler
-    .long   RTC_IRQHandler
-    .long   KEY_WKUP_GPIO_IRQHandler
-    .long   PDC_IRQHandler
-    .long   VBUS_IRQHandler
-    .long   MRM_IRQHandler
-    .long   MOTOR_CONTROLLER_IRQHandler
-    .long   TRNG_IRQHandler
-    .long   DCDC_IRQHandler
-    .long   XTAL32M_RDY_IRQHandler
-    .long   ADC_IRQHandler
-    .long   ADC2_IRQHandler
-    .long   CRYPTO_IRQHandler
-    .long   CAPTIMER1_IRQHandler
-    .long   RFDIAG_IRQHandler
-    .long   LCD_CONTROLLER_IRQHandler
-    .long   PLL_LOCK_IRQHandler
-    .long   TIMER3_IRQHandler
-    .long   TIMER4_IRQHandler
-    .long   LRA_IRQHandler
-    .long   RTC_EVENT_IRQHandler
-    .long   GPIO_P0_IRQHandler
-    .long   GPIO_P1_IRQHandler
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .size   __isr_vector, . - __isr_vector
-
-    .text
-    .thumb
-    .thumb_func
-    .align 2
-    .globl Reset_Handler
-    .type  Reset_Handler, %function
-Reset_Handler:
- /* Make sure interrupt vector is remapped at 0x0 */
-    ldr     r1, =SYS_CTRL_REG
-    ldrh    r2, [r1, #0]
-    orrs    r2, r2, #8
-    strh    r2, [r1, #0]
-
-#if !MYNEWT_VAL(RAM_RESIDENT)
-/*
- * Flash is remapped at 0x0 with an offset, i.e. 0x0 does not correspond to
- * 0x16000000 but to start of an image on flash. This is calculated from product
- * header by 1st state bootloader and configured in CACHE_FLASH_REG. We need to
- * retrieve proper offset value for calculations later.
- */
-    ldr     r1, =CACHE_FLASH_REG
-    ldr     r4, [r1, #0]
-    mov     r2, r4
-    mov     r3, #0xFFFF
-    bic     r4, r4, r3      /* CACHE_FLASH_REG[FLASH_REGION_BASE] */
-    mov     r3, #0xFFF0
-    and     r2, r2, r3      /* CACHE_FLASH_REG[FLASH_REGION_OFFSET] */
-    lsr     r2, r2, #2
-    orr     r4, r4, r2
-
-/* Copy ISR vector from flash to RAM */
-    ldr     r1, =__isr_vector_start     /* src ptr */
-    ldr     r2, =__isr_vector_end       /* src end */
-    ldr     r3, =__intvect_start__      /* dst ptr */
-/* Make sure we copy from QSPIC address range, not from remapped range */
-    cmp     r1, r4
-    itt     lt
-    addlt   r1, r1, r4
-    addlt   r2, r2, r4
-.loop_isr_copy:
-    cmp     r1, r2
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r3], #4
-    blt     .loop_isr_copy
-
-/* Copy QSPI code from flash to RAM */
-    ldr     r1, =__text_ram_addr        /* src ptr */
-    ldr     r2, =__text_ram_start__     /* ptr */
-    ldr     r3, =__text_ram_end__       /* dst end */
-.loop_code_text_ram_copy:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt     .loop_code_text_ram_copy
-
-/* Copy data from flash to RAM */
-    ldr     r1, =__etext                /* src ptr */
-    ldr     r2, =__data_start__         /* dst ptr */
-    ldr     r3, =__data_end__           /* dst end */
-.loop_data_copy:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt     .loop_data_copy
-#endif
-
-/* Clear BSS */
-    movs    r0, 0
-    ldr     r1, =__bss_start__
-    ldr     r2, =__bss_end__
-.loop_bss_clear:
-    cmp     r1, r2
-    itt     lt
-    strlt   r0, [r1], #4
-    blt     .loop_bss_clear
-
-    ldr     r0, =__HeapBase
-    ldr     r1, =__HeapLimit
-/* Call static constructors */
-    bl __libc_init_array
-
-    bl      SystemInit
-    bl      main
-
-    .pool
-    .size   Reset_Handler, . - Reset_Handler
-
-/* Default interrupt handler */
-    .type   Default_Handler, %function
-Default_Handler:
-    ldr     r1, =SYS_CTRL_REG
-    ldrh    r2, [r1, #0]
-    orrs    r2, r2, #0x80   /* DEBUGGER_ENABLE */
-    strh    r2, [r1, #0]
-    b       .
-
-    .size   Default_Handler, . - Default_Handler
-
-/* Default handlers for all interrupts */
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    /* Cortex-M33 interrupts */
-    IRQ  NMI_Handler
-    IRQ  HardFault_Handler
-    IRQ  MemoryManagement_Handler
-    IRQ  BusFault_Handler
-    IRQ  UsageFault_Handler
-    IRQ  SecureFault_Handler
-    IRQ  SVC_Handler
-    IRQ  DebugMonitor_Handler
-    IRQ  PendSV_Handler
-    IRQ  SysTick_Handler
-    /* DA1469x interrupts */
-    IRQ  SENSOR_NODE_IRQHandler
-    IRQ  DMA_IRQHandler
-    IRQ  CHARGER_STATE_IRQHandler
-    IRQ  CHARGER_ERROR_IRQHandler
-    IRQ  CMAC2SYS_IRQHandler
-    IRQ  UART_IRQHandler
-    IRQ  UART2_IRQHandler
-    IRQ  UART3_IRQHandler
-    IRQ  I2C_IRQHandler
-    IRQ  I2C2_IRQHandler
-    IRQ  SPI_IRQHandler
-    IRQ  SPI2_IRQHandler
-    IRQ  PCM_IRQHandler
-    IRQ  SRC_IN_IRQHandler
-    IRQ  SRC_OUT_IRQHandler
-    IRQ  USB_IRQHandler
-    IRQ  TIMER_IRQHandler
-    IRQ  TIMER2_IRQHandler
-    IRQ  RTC_IRQHandler
-    IRQ  KEY_WKUP_GPIO_IRQHandler
-    IRQ  PDC_IRQHandler
-    IRQ  VBUS_IRQHandler
-    IRQ  MRM_IRQHandler
-    IRQ  MOTOR_CONTROLLER_IRQHandler
-    IRQ  TRNG_IRQHandler
-    IRQ  DCDC_IRQHandler
-    IRQ  XTAL32M_RDY_IRQHandler
-    IRQ  ADC_IRQHandler
-    IRQ  ADC2_IRQHandler
-    IRQ  CRYPTO_IRQHandler
-    IRQ  CAPTIMER1_IRQHandler
-    IRQ  RFDIAG_IRQHandler
-    IRQ  LCD_CONTROLLER_IRQHandler
-    IRQ  PLL_LOCK_IRQHandler
-    IRQ  TIMER3_IRQHandler
-    IRQ  TIMER4_IRQHandler
-    IRQ  LRA_IRQHandler
-    IRQ  RTC_EVENT_IRQHandler
-    IRQ  GPIO_P0_IRQHandler
-    IRQ  GPIO_P1_IRQHandler
-    IRQ  RESERVED40_IRQHandler
-    IRQ  RESERVED41_IRQHandler
-    IRQ  RESERVED42_IRQHandler
-    IRQ  RESERVED43_IRQHandler
-    IRQ  RESERVED44_IRQHandler
-    IRQ  RESERVED45_IRQHandler
-    IRQ  RESERVED46_IRQHandler
-    IRQ  RESERVED47_IRQHandler
-
-.end
diff --git a/hw/bsp/da1469x_dk_pro/product_header.dump b/hw/bsp/da1469x_dk_pro/product_header.dump
deleted file mode 100644
index ea4842242..000000000
Binary files a/hw/bsp/da1469x_dk_pro/product_header.dump and /dev/null differ
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
deleted file mode 100644
index 6f243c6a2..000000000
--- a/hw/bsp/ea4357/board.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib \
-  -DCORE_M4 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes  -Wno-error=cast-qual
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld
-
-SRC_C += \
-	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
-	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
-	src/portable/ehci/ehci.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
-	$(MCU_DIR)/src/chip_18xx_43xx.c \
-	$(MCU_DIR)/src/clock_18xx_43xx.c \
-	$(MCU_DIR)/src/gpio_18xx_43xx.c \
-	$(MCU_DIR)/src/sysinit_18xx_43xx.c \
-	$(MCU_DIR)/src/i2c_18xx_43xx.c \
-	$(MCU_DIR)/src/i2cm_18xx_43xx.c \
-	$(MCU_DIR)/src/uart_18xx_43xx.c \
-	$(MCU_DIR)/src/fpu_init.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc \
-	$(TOP)/$(MCU_DIR)/inc/config_43xx
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4357_M4
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/esp32s2/boards/CMakeLists.txt b/hw/bsp/esp32s2/boards/CMakeLists.txt
deleted file mode 100644
index c3c687a70..000000000
--- a/hw/bsp/esp32s2/boards/CMakeLists.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-idf_component_register(SRCS esp32s2.c
-                    INCLUDE_DIRS "." "${BOARD}"
-                    PRIV_REQUIRES "driver"
-                    REQUIRES freertos src led_strip)
-
-# Apply board specific content
-include("${BOARD}/board.cmake")
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/hw"
-  "${TOP}/src"  
-)
diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
deleted file mode 100644
index d33962676..000000000
--- a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: $ENV{IDF_TARGET}(${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
deleted file mode 100644
index d33962676..000000000
--- a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: $ENV{IDF_TARGET}(${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
deleted file mode 100644
index d5c17b9be..000000000
--- a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/esp32s2/boards/esp32s2.c
deleted file mode 100644
index a7ca82deb..000000000
--- a/hw/bsp/esp32s2/boards/esp32s2.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../../board.h"
-#include "board.h"
-
-#include "esp_rom_gpio.h"
-#include "hal/gpio_ll.h"
-#include "hal/usb_hal.h"
-#include "soc/usb_periph.h"
-
-#include "driver/rmt.h"
-
-#if ESP_IDF_VERSION_MAJOR > 4
-  #include "esp_private/periph_ctrl.h"
-#else
-  #include "driver/periph_ctrl.h"
-#endif
-
-#ifdef NEOPIXEL_PIN
-#include "led_strip.h"
-static led_strip_t *strip;
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-static void configure_pins(usb_hal_context_t *usb);
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
-
-#ifdef NEOPIXEL_PIN
-  #ifdef NEOPIXEL_POWER_PIN
-  gpio_reset_pin(NEOPIXEL_POWER_PIN);
-  gpio_set_direction(NEOPIXEL_POWER_PIN, GPIO_MODE_OUTPUT);
-  gpio_set_level(NEOPIXEL_POWER_PIN, NEOPIXEL_POWER_STATE);
-  #endif
-
-  // WS2812 Neopixel driver with RMT peripheral
-  rmt_config_t config = RMT_DEFAULT_CONFIG_TX(NEOPIXEL_PIN, RMT_CHANNEL_0);
-  config.clk_div = 2; // set counter clock to 40MHz
-
-  rmt_config(&config);
-  rmt_driver_install(config.channel, 0, 0);
-
-  led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel);
-  strip = led_strip_new_rmt_ws2812(&strip_config);
-  strip->clear(strip, 100); // off led
-#endif
-
-  // Button
-  esp_rom_gpio_pad_select_gpio(BUTTON_PIN);
-  gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
-  gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
-
-  // USB Controller Hal init
-  periph_module_reset(PERIPH_USB_MODULE);
-  periph_module_enable(PERIPH_USB_MODULE);
-
-  usb_hal_context_t hal = {
-    .use_external_phy = false // use built-in PHY
-  };
-  usb_hal_init(&hal);
-  configure_pins(&hal);
-}
-
-static void configure_pins(usb_hal_context_t *usb)
-{
-  /* usb_periph_iopins currently configures USB_OTG as USB Device.
-   * Introduce additional parameters in usb_hal_context_t when adding support
-   * for USB Host.
-   */
-  for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
-    if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
-      esp_rom_gpio_pad_select_gpio(iopin->pin);
-      if (iopin->is_output) {
-        esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
-      } else {
-        esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
-#if ESP_IDF_VERSION_MAJOR > 4
-        if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
-#else
-        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
-#endif
-        {
-          gpio_ll_input_enable(&GPIO, iopin->pin);
-        }
-      }
-      esp_rom_gpio_pad_unhold(iopin->pin);
-    }
-  }
-  if (!usb->use_external_phy) {
-    gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
-    gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
-  }
-}
-
-// Turn LED on or off
-void board_led_write(bool state)
-{
-#ifdef NEOPIXEL_PIN
-  strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
-  strip->refresh(strip, 100);
-#endif
-}
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
-  return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
-}
-
-// Get characters from UART
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-// Send characters to UART
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
deleted file mode 100644
index d5c17b9be..000000000
--- a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
deleted file mode 100644
index d5c17b9be..000000000
--- a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt b/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
deleted file mode 100644
index 6d0fcbc86..000000000
--- a/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-set(component_srcs "src/led_strip_rmt_ws2812.c")
-
-idf_component_register(SRCS "${component_srcs}"
-                       INCLUDE_DIRS "include"
-                       PRIV_INCLUDE_DIRS ""
-                       PRIV_REQUIRES "driver"
-                       REQUIRES "")
-
diff --git a/hw/bsp/esp32s2/components/led_strip/include/led_strip.h b/hw/bsp/esp32s2/components/led_strip/include/led_strip.h
deleted file mode 100644
index a9dffc325..000000000
--- a/hw/bsp/esp32s2/components/led_strip/include/led_strip.h
+++ /dev/null
@@ -1,126 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "esp_err.h"
-
-/**
-* @brief LED Strip Type
-*
-*/
-typedef struct led_strip_s led_strip_t;
-
-/**
-* @brief LED Strip Device Type
-*
-*/
-typedef void *led_strip_dev_t;
-
-/**
-* @brief Declare of LED Strip Type
-*
-*/
-struct led_strip_s {
-    /**
-    * @brief Set RGB for a specific pixel
-    *
-    * @param strip: LED strip
-    * @param index: index of pixel to set
-    * @param red: red part of color
-    * @param green: green part of color
-    * @param blue: blue part of color
-    *
-    * @return
-    *      - ESP_OK: Set RGB for a specific pixel successfully
-    *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
-    *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
-    */
-    esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
-
-    /**
-    * @brief Refresh memory colors to LEDs
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for refreshing task
-    *
-    * @return
-    *      - ESP_OK: Refresh successfully
-    *      - ESP_ERR_TIMEOUT: Refresh failed because of timeout
-    *      - ESP_FAIL: Refresh failed because some other error occurred
-    *
-    * @note:
-    *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
-    */
-    esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Clear LED strip (turn off all LEDs)
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for clearing task
-    *
-    * @return
-    *      - ESP_OK: Clear LEDs successfully
-    *      - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout
-    *      - ESP_FAIL: Clear LEDs failed because some other error occurred
-    */
-    esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Free LED strip resources
-    *
-    * @param strip: LED strip
-    *
-    * @return
-    *      - ESP_OK: Free resources successfully
-    *      - ESP_FAIL: Free resources failed because error occurred
-    */
-    esp_err_t (*del)(led_strip_t *strip);
-};
-
-/**
-* @brief LED Strip Configuration Type
-*
-*/
-typedef struct {
-    uint32_t max_leds;   /*!< Maximum LEDs in a single strip */
-    led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */
-} led_strip_config_t;
-
-/**
- * @brief Default configuration for LED strip
- *
- */
-#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \
-    {                                             \
-        .max_leds = number,                       \
-        .dev = dev_hdl,                           \
-    }
-
-/**
-* @brief Install a new ws2812 driver (based on RMT peripheral)
-*
-* @param config: LED strip configuration
-* @return
-*      LED strip instance or NULL
-*/
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c
deleted file mode 100644
index 025d3c590..000000000
--- a/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdlib.h>
-#include <string.h>
-#include <sys/cdefs.h>
-#include "esp_log.h"
-#include "esp_attr.h"
-#include "led_strip.h"
-#include "driver/rmt.h"
-
-static const char *TAG = "ws2812";
-#define STRIP_CHECK(a, str, goto_tag, ret_value, ...)                             \
-    do                                                                            \
-    {                                                                             \
-        if (!(a))                                                                 \
-        {                                                                         \
-            ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
-            ret = ret_value;                                                      \
-            goto goto_tag;                                                        \
-        }                                                                         \
-    } while (0)
-
-#define WS2812_T0H_NS (350)
-#define WS2812_T0L_NS (1000)
-#define WS2812_T1H_NS (1000)
-#define WS2812_T1L_NS (350)
-#define WS2812_RESET_US (280)
-
-static uint32_t ws2812_t0h_ticks = 0;
-static uint32_t ws2812_t1h_ticks = 0;
-static uint32_t ws2812_t0l_ticks = 0;
-static uint32_t ws2812_t1l_ticks = 0;
-
-typedef struct {
-    led_strip_t parent;
-    rmt_channel_t rmt_channel;
-    uint32_t strip_len;
-    uint8_t buffer[0];
-} ws2812_t;
-
-/**
- * @brief Conver RGB data to RMT format.
- *
- * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t)
- *
- * @param[in] src: source data, to converted to RMT format
- * @param[in] dest: place where to store the convert result
- * @param[in] src_size: size of source data
- * @param[in] wanted_num: number of RMT items that want to get
- * @param[out] translated_size: number of source data that got converted
- * @param[out] item_num: number of RMT items which are converted from source data
- */
-static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size,
-        size_t wanted_num, size_t *translated_size, size_t *item_num)
-{
-    if (src == NULL || dest == NULL) {
-        *translated_size = 0;
-        *item_num = 0;
-        return;
-    }
-    const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; //Logical 0
-    const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; //Logical 1
-    size_t size = 0;
-    size_t num = 0;
-    uint8_t *psrc = (uint8_t *)src;
-    rmt_item32_t *pdest = dest;
-    while (size < src_size && num < wanted_num) {
-        for (int i = 0; i < 8; i++) {
-            // MSB first
-            if (*psrc & (1 << (7 - i))) {
-                pdest->val =  bit1.val;
-            } else {
-                pdest->val =  bit0.val;
-            }
-            num++;
-            pdest++;
-        }
-        size++;
-        psrc++;
-    }
-    *translated_size = size;
-    *item_num = num;
-}
-
-static esp_err_t ws2812_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(index < ws2812->strip_len, "index out of the maximum number of leds", err, ESP_ERR_INVALID_ARG);
-    uint32_t start = index * 3;
-    // In thr order of GRB
-    ws2812->buffer[start + 0] = green & 0xFF;
-    ws2812->buffer[start + 1] = red & 0xFF;
-    ws2812->buffer[start + 2] = blue & 0xFF;
-    return ESP_OK;
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_refresh(led_strip_t *strip, uint32_t timeout_ms)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(rmt_write_sample(ws2812->rmt_channel, ws2812->buffer, ws2812->strip_len * 3, true) == ESP_OK,
-                "transmit RMT samples failed", err, ESP_FAIL);
-    return rmt_wait_tx_done(ws2812->rmt_channel, pdMS_TO_TICKS(timeout_ms));
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_clear(led_strip_t *strip, uint32_t timeout_ms)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    // Write zero to turn off all leds
-    memset(ws2812->buffer, 0, ws2812->strip_len * 3);
-    return ws2812_refresh(strip, timeout_ms);
-}
-
-static esp_err_t ws2812_del(led_strip_t *strip)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    free(ws2812);
-    return ESP_OK;
-}
-
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config)
-{
-    led_strip_t *ret = NULL;
-    STRIP_CHECK(config, "configuration can't be null", err, NULL);
-
-    // 24 bits per led
-    uint32_t ws2812_size = sizeof(ws2812_t) + config->max_leds * 3;
-    ws2812_t *ws2812 = calloc(1, ws2812_size);
-    STRIP_CHECK(ws2812, "request memory for ws2812 failed", err, NULL);
-
-    uint32_t counter_clk_hz = 0;
-    STRIP_CHECK(rmt_get_counter_clock((rmt_channel_t)config->dev, &counter_clk_hz) == ESP_OK,
-                "get rmt counter clock failed", err, NULL);
-    // ns -> ticks
-    float ratio = (float)counter_clk_hz / 1e9;
-    ws2812_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS);
-    ws2812_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS);
-    ws2812_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS);
-    ws2812_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS);
-
-    // set ws2812 to rmt adapter
-    rmt_translator_init((rmt_channel_t)config->dev, ws2812_rmt_adapter);
-
-    ws2812->rmt_channel = (rmt_channel_t)config->dev;
-    ws2812->strip_len = config->max_leds;
-
-    ws2812->parent.set_pixel = ws2812_set_pixel;
-    ws2812->parent.refresh = ws2812_refresh;
-    ws2812->parent.clear = ws2812_clear;
-    ws2812->parent.del = ws2812_del;
-
-    return &ws2812->parent;
-err:
-    return ret;
-}
diff --git a/hw/bsp/esp32s2/family.cmake b/hw/bsp/esp32s2/family.cmake
deleted file mode 100644
index f3d41d041..000000000
--- a/hw/bsp/esp32s2/family.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-cmake_minimum_required(VERSION 3.5)
-
-# Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2/boards" "${TOP}/hw/bsp/esp32s2/components")  
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-set(SUPPORTED_TARGETS esp32s2)
-set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/esp32s3/boards/CMakeLists.txt b/hw/bsp/esp32s3/boards/CMakeLists.txt
deleted file mode 100644
index e1b921ae9..000000000
--- a/hw/bsp/esp32s3/boards/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-idf_component_register(SRCS esp32s3.c
-                    INCLUDE_DIRS "." "${BOARD}"
-                    PRIV_REQUIRES "driver"
-                    REQUIRES freertos src led_strip)
-
-# Apply board specific content
-include("${BOARD}/board.cmake")
-
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
-  "${TOP}/hw"
-  "${TOP}/src"  
-)
diff --git a/hw/bsp/esp32s3/boards/esp32s3.c b/hw/bsp/esp32s3/boards/esp32s3.c
deleted file mode 100644
index a7ca82deb..000000000
--- a/hw/bsp/esp32s3/boards/esp32s3.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../../board.h"
-#include "board.h"
-
-#include "esp_rom_gpio.h"
-#include "hal/gpio_ll.h"
-#include "hal/usb_hal.h"
-#include "soc/usb_periph.h"
-
-#include "driver/rmt.h"
-
-#if ESP_IDF_VERSION_MAJOR > 4
-  #include "esp_private/periph_ctrl.h"
-#else
-  #include "driver/periph_ctrl.h"
-#endif
-
-#ifdef NEOPIXEL_PIN
-#include "led_strip.h"
-static led_strip_t *strip;
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-static void configure_pins(usb_hal_context_t *usb);
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
-
-#ifdef NEOPIXEL_PIN
-  #ifdef NEOPIXEL_POWER_PIN
-  gpio_reset_pin(NEOPIXEL_POWER_PIN);
-  gpio_set_direction(NEOPIXEL_POWER_PIN, GPIO_MODE_OUTPUT);
-  gpio_set_level(NEOPIXEL_POWER_PIN, NEOPIXEL_POWER_STATE);
-  #endif
-
-  // WS2812 Neopixel driver with RMT peripheral
-  rmt_config_t config = RMT_DEFAULT_CONFIG_TX(NEOPIXEL_PIN, RMT_CHANNEL_0);
-  config.clk_div = 2; // set counter clock to 40MHz
-
-  rmt_config(&config);
-  rmt_driver_install(config.channel, 0, 0);
-
-  led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel);
-  strip = led_strip_new_rmt_ws2812(&strip_config);
-  strip->clear(strip, 100); // off led
-#endif
-
-  // Button
-  esp_rom_gpio_pad_select_gpio(BUTTON_PIN);
-  gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
-  gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
-
-  // USB Controller Hal init
-  periph_module_reset(PERIPH_USB_MODULE);
-  periph_module_enable(PERIPH_USB_MODULE);
-
-  usb_hal_context_t hal = {
-    .use_external_phy = false // use built-in PHY
-  };
-  usb_hal_init(&hal);
-  configure_pins(&hal);
-}
-
-static void configure_pins(usb_hal_context_t *usb)
-{
-  /* usb_periph_iopins currently configures USB_OTG as USB Device.
-   * Introduce additional parameters in usb_hal_context_t when adding support
-   * for USB Host.
-   */
-  for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
-    if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
-      esp_rom_gpio_pad_select_gpio(iopin->pin);
-      if (iopin->is_output) {
-        esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
-      } else {
-        esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
-#if ESP_IDF_VERSION_MAJOR > 4
-        if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
-#else
-        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
-#endif
-        {
-          gpio_ll_input_enable(&GPIO, iopin->pin);
-        }
-      }
-      esp_rom_gpio_pad_unhold(iopin->pin);
-    }
-  }
-  if (!usb->use_external_phy) {
-    gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
-    gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
-  }
-}
-
-// Turn LED on or off
-void board_led_write(bool state)
-{
-#ifdef NEOPIXEL_PIN
-  strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
-  strip->refresh(strip, 100);
-#endif
-}
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
-  return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
-}
-
-// Get characters from UART
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-// Send characters to UART
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake b/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
deleted file mode 100644
index 8996ff9dc..000000000
--- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
deleted file mode 100644
index 8996ff9dc..000000000
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
deleted file mode 100644
index 8996ff9dc..000000000
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt b/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
deleted file mode 100644
index 6d0fcbc86..000000000
--- a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-set(component_srcs "src/led_strip_rmt_ws2812.c")
-
-idf_component_register(SRCS "${component_srcs}"
-                       INCLUDE_DIRS "include"
-                       PRIV_INCLUDE_DIRS ""
-                       PRIV_REQUIRES "driver"
-                       REQUIRES "")
-
diff --git a/hw/bsp/esp32s3/components/led_strip/include/led_strip.h b/hw/bsp/esp32s3/components/led_strip/include/led_strip.h
deleted file mode 100644
index a9dffc325..000000000
--- a/hw/bsp/esp32s3/components/led_strip/include/led_strip.h
+++ /dev/null
@@ -1,126 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "esp_err.h"
-
-/**
-* @brief LED Strip Type
-*
-*/
-typedef struct led_strip_s led_strip_t;
-
-/**
-* @brief LED Strip Device Type
-*
-*/
-typedef void *led_strip_dev_t;
-
-/**
-* @brief Declare of LED Strip Type
-*
-*/
-struct led_strip_s {
-    /**
-    * @brief Set RGB for a specific pixel
-    *
-    * @param strip: LED strip
-    * @param index: index of pixel to set
-    * @param red: red part of color
-    * @param green: green part of color
-    * @param blue: blue part of color
-    *
-    * @return
-    *      - ESP_OK: Set RGB for a specific pixel successfully
-    *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
-    *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
-    */
-    esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
-
-    /**
-    * @brief Refresh memory colors to LEDs
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for refreshing task
-    *
-    * @return
-    *      - ESP_OK: Refresh successfully
-    *      - ESP_ERR_TIMEOUT: Refresh failed because of timeout
-    *      - ESP_FAIL: Refresh failed because some other error occurred
-    *
-    * @note:
-    *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
-    */
-    esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Clear LED strip (turn off all LEDs)
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for clearing task
-    *
-    * @return
-    *      - ESP_OK: Clear LEDs successfully
-    *      - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout
-    *      - ESP_FAIL: Clear LEDs failed because some other error occurred
-    */
-    esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Free LED strip resources
-    *
-    * @param strip: LED strip
-    *
-    * @return
-    *      - ESP_OK: Free resources successfully
-    *      - ESP_FAIL: Free resources failed because error occurred
-    */
-    esp_err_t (*del)(led_strip_t *strip);
-};
-
-/**
-* @brief LED Strip Configuration Type
-*
-*/
-typedef struct {
-    uint32_t max_leds;   /*!< Maximum LEDs in a single strip */
-    led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */
-} led_strip_config_t;
-
-/**
- * @brief Default configuration for LED strip
- *
- */
-#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \
-    {                                             \
-        .max_leds = number,                       \
-        .dev = dev_hdl,                           \
-    }
-
-/**
-* @brief Install a new ws2812 driver (based on RMT peripheral)
-*
-* @param config: LED strip configuration
-* @return
-*      LED strip instance or NULL
-*/
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
deleted file mode 100644
index 025d3c590..000000000
--- a/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdlib.h>
-#include <string.h>
-#include <sys/cdefs.h>
-#include "esp_log.h"
-#include "esp_attr.h"
-#include "led_strip.h"
-#include "driver/rmt.h"
-
-static const char *TAG = "ws2812";
-#define STRIP_CHECK(a, str, goto_tag, ret_value, ...)                             \
-    do                                                                            \
-    {                                                                             \
-        if (!(a))                                                                 \
-        {                                                                         \
-            ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
-            ret = ret_value;                                                      \
-            goto goto_tag;                                                        \
-        }                                                                         \
-    } while (0)
-
-#define WS2812_T0H_NS (350)
-#define WS2812_T0L_NS (1000)
-#define WS2812_T1H_NS (1000)
-#define WS2812_T1L_NS (350)
-#define WS2812_RESET_US (280)
-
-static uint32_t ws2812_t0h_ticks = 0;
-static uint32_t ws2812_t1h_ticks = 0;
-static uint32_t ws2812_t0l_ticks = 0;
-static uint32_t ws2812_t1l_ticks = 0;
-
-typedef struct {
-    led_strip_t parent;
-    rmt_channel_t rmt_channel;
-    uint32_t strip_len;
-    uint8_t buffer[0];
-} ws2812_t;
-
-/**
- * @brief Conver RGB data to RMT format.
- *
- * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t)
- *
- * @param[in] src: source data, to converted to RMT format
- * @param[in] dest: place where to store the convert result
- * @param[in] src_size: size of source data
- * @param[in] wanted_num: number of RMT items that want to get
- * @param[out] translated_size: number of source data that got converted
- * @param[out] item_num: number of RMT items which are converted from source data
- */
-static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size,
-        size_t wanted_num, size_t *translated_size, size_t *item_num)
-{
-    if (src == NULL || dest == NULL) {
-        *translated_size = 0;
-        *item_num = 0;
-        return;
-    }
-    const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; //Logical 0
-    const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; //Logical 1
-    size_t size = 0;
-    size_t num = 0;
-    uint8_t *psrc = (uint8_t *)src;
-    rmt_item32_t *pdest = dest;
-    while (size < src_size && num < wanted_num) {
-        for (int i = 0; i < 8; i++) {
-            // MSB first
-            if (*psrc & (1 << (7 - i))) {
-                pdest->val =  bit1.val;
-            } else {
-                pdest->val =  bit0.val;
-            }
-            num++;
-            pdest++;
-        }
-        size++;
-        psrc++;
-    }
-    *translated_size = size;
-    *item_num = num;
-}
-
-static esp_err_t ws2812_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(index < ws2812->strip_len, "index out of the maximum number of leds", err, ESP_ERR_INVALID_ARG);
-    uint32_t start = index * 3;
-    // In thr order of GRB
-    ws2812->buffer[start + 0] = green & 0xFF;
-    ws2812->buffer[start + 1] = red & 0xFF;
-    ws2812->buffer[start + 2] = blue & 0xFF;
-    return ESP_OK;
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_refresh(led_strip_t *strip, uint32_t timeout_ms)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(rmt_write_sample(ws2812->rmt_channel, ws2812->buffer, ws2812->strip_len * 3, true) == ESP_OK,
-                "transmit RMT samples failed", err, ESP_FAIL);
-    return rmt_wait_tx_done(ws2812->rmt_channel, pdMS_TO_TICKS(timeout_ms));
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_clear(led_strip_t *strip, uint32_t timeout_ms)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    // Write zero to turn off all leds
-    memset(ws2812->buffer, 0, ws2812->strip_len * 3);
-    return ws2812_refresh(strip, timeout_ms);
-}
-
-static esp_err_t ws2812_del(led_strip_t *strip)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    free(ws2812);
-    return ESP_OK;
-}
-
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config)
-{
-    led_strip_t *ret = NULL;
-    STRIP_CHECK(config, "configuration can't be null", err, NULL);
-
-    // 24 bits per led
-    uint32_t ws2812_size = sizeof(ws2812_t) + config->max_leds * 3;
-    ws2812_t *ws2812 = calloc(1, ws2812_size);
-    STRIP_CHECK(ws2812, "request memory for ws2812 failed", err, NULL);
-
-    uint32_t counter_clk_hz = 0;
-    STRIP_CHECK(rmt_get_counter_clock((rmt_channel_t)config->dev, &counter_clk_hz) == ESP_OK,
-                "get rmt counter clock failed", err, NULL);
-    // ns -> ticks
-    float ratio = (float)counter_clk_hz / 1e9;
-    ws2812_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS);
-    ws2812_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS);
-    ws2812_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS);
-    ws2812_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS);
-
-    // set ws2812 to rmt adapter
-    rmt_translator_init((rmt_channel_t)config->dev, ws2812_rmt_adapter);
-
-    ws2812->rmt_channel = (rmt_channel_t)config->dev;
-    ws2812->strip_len = config->max_leds;
-
-    ws2812->parent.set_pixel = ws2812_set_pixel;
-    ws2812->parent.refresh = ws2812_refresh;
-    ws2812->parent.clear = ws2812_clear;
-    ws2812->parent.del = ws2812_del;
-
-    return &ws2812->parent;
-err:
-    return ret;
-}
diff --git a/hw/bsp/esp32s3/family.cmake b/hw/bsp/esp32s3/family.cmake
deleted file mode 100644
index 511dd58bb..000000000
--- a/hw/bsp/esp32s3/family.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-cmake_minimum_required(VERSION 3.5)
-
-# Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s3/boards" "${TOP}/hw/bsp/esp32s3/components")  
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-set(SUPPORTED_TARGETS esp32s3)
-set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/esp32s3/family.mk b/hw/bsp/esp32s3/family.mk
deleted file mode 100644
index cf153ffc2..000000000
--- a/hw/bsp/esp32s3/family.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#DEPS_SUBMODULES +=
-
-.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
-
-all:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) -DIDF_TARGET=esp32s3 build
-
-build: all
-
-clean:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean
-
-fullclean:
-	if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
-	if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
-
-flash bootloader-flash app-flash erase monitor dfu-flash dfu:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
-
-uf2: $(BUILD)/$(PROJECT).uf2
-
-UF2_FAMILY_ID = 0xc47e5767
-$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
-	@echo CREATE $@
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
-
diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt
new file mode 100644
index 000000000..434f77704
--- /dev/null
+++ b/hw/bsp/espressif/boards/CMakeLists.txt
@@ -0,0 +1,6 @@
+set(hw_dir "${CMAKE_CURRENT_LIST_DIR}/../../../")
+
+idf_component_register(SRCS family.c
+                    INCLUDE_DIRS "." ${BOARD} ${hw_dir}
+                    PRIV_REQUIRES driver usb
+                    REQUIRES led_strip src tinyusb_src)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake
new file mode 100644
index 000000000..84ea4940b
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h
new file mode 100644
index 000000000..15e5091f9
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h
@@ -0,0 +1,58 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Adafruit Feather ESP32 v2
+   url: https://www.adafruit.com/product/5400
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          0
+#define NEOPIXEL_POWER_PIN    2
+#define NEOPIXEL_POWER_STATE  1
+
+#define BUTTON_PIN            38
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI3_HOST
+#define MAX3421_SCK_PIN  5
+#define MAX3421_MOSI_PIN 19
+#define MAX3421_MISO_PIN 21
+#define MAX3421_CS_PIN   33
+#define MAX3421_INTR_PIN 15
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
new file mode 100644
index 000000000..0bbf5a013
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h
similarity index 83%
rename from hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
rename to hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h
index 43e00901d..0f607c755 100644
--- a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit Feather ESP32S2
+   url: https://www.adafruit.com/product/5000
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -38,6 +43,14 @@
 #define BUTTON_PIN            0
 #define BUTTON_STATE_ACTIVE   0
 
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   10
+#define MAX3421_INTR_PIN 9
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake
new file mode 100644
index 000000000..dd204f0a4
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h
new file mode 100644
index 000000000..35c268cf5
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h
@@ -0,0 +1,58 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Adafruit Feather ESP32S3
+   url: https://www.adafruit.com/product/5323
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          33
+#define NEOPIXEL_POWER_PIN    21
+#define NEOPIXEL_POWER_STATE  1
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   10
+#define MAX3421_INTR_PIN 9
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h
similarity index 93%
rename from hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
rename to hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h
index 16e30b685..b86089400 100644
--- a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
+++ b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit MagTag 2.9" Grayscale
+   url: https://www.adafruit.com/product/4800
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
new file mode 100644
index 000000000..0bbf5a013
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
new file mode 100644
index 000000000..bc45678f7
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Adafruit Metro ESP32-S2
+   url: https://www.adafruit.com/product/4775
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          45
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_addax_1/board.cmake b/hw/bsp/espressif/boards/espressif_addax_1/board.cmake
new file mode 100644
index 000000000..9bac46d64
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_addax_1/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.h b/hw/bsp/espressif/boards/espressif_addax_1/board.h
similarity index 96%
rename from hw/bsp/esp32s3/boards/espressif_addax_1/board.h
rename to hw/bsp/espressif/boards/espressif_addax_1/board.h
index fff24ba44..4a4a15e1b 100644
--- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.h
+++ b/hw/bsp/espressif/boards/espressif_addax_1/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Espresif Addax-1
+   url: n/a
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake
new file mode 100644
index 000000000..6a0060f9e
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32c3")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h
new file mode 100644
index 000000000..a03cb5052
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Espresif C3 DevKitC
+   url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c3/esp32-c3-devkitc-02/index.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          8
+
+#define BUTTON_PIN            9
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN  4
+#define MAX3421_MOSI_PIN 6
+#define MAX3421_MISO_PIN 5
+#define MAX3421_CS_PIN   10
+#define MAX3421_INTR_PIN 7
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake
new file mode 100644
index 000000000..9adaefb17
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32c6")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h
new file mode 100644
index 000000000..eedd36a89
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Espresif C6 DevKitC
+   url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitc-1/index.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          8
+
+#define BUTTON_PIN            9
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN  4
+#define MAX3421_MOSI_PIN 6
+#define MAX3421_MISO_PIN 5
+#define MAX3421_CS_PIN   10
+#define MAX3421_INTR_PIN 7
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake b/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
new file mode 100644
index 000000000..d49dc2af6
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
@@ -0,0 +1,57 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Espresif Kaluga 1
+   url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-kaluga-1/index.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// Note: need to insert jumper next to WS2812 pixel
+#define NEOPIXEL_PIN          45
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake
new file mode 100644
index 000000000..fe4db4fc1
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32p4")
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h
similarity index 77%
rename from hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
rename to hw/bsp/espressif/boards/espressif_p4_function_ev/board.h
index 01dd1f24f..6f3229b70 100644
--- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
+++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Espresif P4 Function EV
+   url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/index.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,19 +36,14 @@
  extern "C" {
 #endif
 
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
+// #define NEOPIXEL_PIN          48
 
-// LED
-#define LED_PIN               _PINNUM(0, 23)
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            _PINNUM(0, 18)
+#define BUTTON_PIN            35
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
-#define UART_RX_PIN           2
-#define UART_TX_PIN           3
+// For CI hardware test, to test both device and host on the same HS port with help of
+#define HIL_DEVICE_HOST_MUX_PIN  47
+#define HIL_DEVICE_STATE         1
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
new file mode 100644
index 000000000..9c197591f
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
@@ -0,0 +1,50 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Espresif S2 DevKitC
+   url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-devkitc-1/index.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// Note: On the production version (v1.2) WS2812 is connected to GPIO 18,
+// however earlier revision v1.1 WS2812 is connected to GPIO 17
+#define NEOPIXEL_PIN          18
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
new file mode 100644
index 000000000..9bac46d64
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
new file mode 100644
index 000000000..6d7a94668
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Espresif S3 DevKitC
+   url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitc-1/index.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          48
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  39
+#define MAX3421_MOSI_PIN 42
+#define MAX3421_MISO_PIN 21
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
new file mode 100644
index 000000000..9bac46d64
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
new file mode 100644
index 000000000..d01fdbe5b
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Espresif S3 DevKitM
+   url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitm-1/index.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          48
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  39
+#define MAX3421_MOSI_PIN 42
+#define MAX3421_MISO_PIN 21
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_saola_1/board.cmake b/hw/bsp/espressif/boards/espressif_saola_1/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_saola_1/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.h b/hw/bsp/espressif/boards/espressif_saola_1/board.h
similarity index 91%
rename from hw/bsp/esp32s2/boards/espressif_saola_1/board.h
rename to hw/bsp/espressif/boards/espressif_saola_1/board.h
index f450b9a8b..ea369f19c 100644
--- a/hw/bsp/esp32s2/boards/espressif_saola_1/board.h
+++ b/hw/bsp/espressif/boards/espressif_saola_1/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Espresif S2 Saola 1
+   url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-saola-1/index.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
new file mode 100644
index 000000000..2f9ecfe4d
--- /dev/null
+++ b/hw/bsp/espressif/boards/family.c
@@ -0,0 +1,342 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: Espressif
+*/
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+#include "esp_rom_gpio.h"
+#include "esp_mac.h"
+#include "hal/gpio_ll.h"
+
+#include "driver/gpio.h"
+#include "driver/uart.h"
+#include "esp_private/periph_ctrl.h"
+
+#ifdef NEOPIXEL_PIN
+#include "led_strip.h"
+static led_strip_handle_t led_strip;
+#endif
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+#include "driver/spi_master.h"
+static void max3421_init(void);
+#endif
+
+static bool usb_init(void);
+
+//--------------------------------------------------------------------+
+// Implementation
+//--------------------------------------------------------------------+
+
+// Initialize on-board peripherals : led, button, uart and USB
+void board_init(void) {
+#ifdef NEOPIXEL_PIN
+  #ifdef NEOPIXEL_POWER_PIN
+  gpio_reset_pin(NEOPIXEL_POWER_PIN);
+  gpio_set_direction(NEOPIXEL_POWER_PIN, GPIO_MODE_OUTPUT);
+  gpio_set_level(NEOPIXEL_POWER_PIN, NEOPIXEL_POWER_STATE);
+  #endif
+
+  // WS2812 Neopixel driver with RMT peripheral
+  led_strip_rmt_config_t rmt_config = {
+      .clk_src = RMT_CLK_SRC_DEFAULT, // different clock source can lead to different power consumption
+      .resolution_hz = 10 * 1000 * 1000,  // RMT counter clock frequency, default = 10 Mhz
+      .flags.with_dma = false,        // DMA feature is available on ESP target like ESP32-S3
+  };
+
+  led_strip_config_t strip_config = {
+      .strip_gpio_num = NEOPIXEL_PIN,           // The GPIO that connected to the LED strip's data line
+      .max_leds = 1,                            // The number of LEDs in the strip,
+      .led_pixel_format = LED_PIXEL_FORMAT_GRB, // Pixel format of your LED strip
+      .led_model = LED_MODEL_WS2812,            // LED strip model
+      .flags.invert_out = false,                // whether to invert the output signal
+  };
+
+  ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip));
+  led_strip_clear(led_strip); // off
+#endif
+
+  // Button
+  esp_rom_gpio_pad_select_gpio(BUTTON_PIN);
+  gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
+  gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4)
+  usb_init();
+#endif
+
+#ifdef HIL_DEVICE_HOST_MUX_PIN
+  gpio_reset_pin(HIL_DEVICE_HOST_MUX_PIN);
+  gpio_set_direction(HIL_DEVICE_HOST_MUX_PIN, GPIO_MODE_OUTPUT);
+  gpio_set_level(HIL_DEVICE_HOST_MUX_PIN, CFG_TUD_ENABLED ? HIL_DEVICE_STATE : (1-HIL_DEVICE_STATE));
+#endif
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+  max3421_init();
+#endif
+}
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+
+#endif
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  // use factory default MAC as serial ID
+  esp_efuse_mac_get_default(id);
+  return 6;
+}
+
+void board_led_write(bool state) {
+#ifdef NEOPIXEL_PIN
+  led_strip_set_pixel(led_strip, 0, state ? 0x08 : 0x00, 0x00, 0x00);
+  led_strip_refresh(led_strip);
+#endif
+}
+
+// Get the current state of button
+// a '1' means active (pressed), a '0' means inactive.
+uint32_t board_button_read(void) {
+  return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
+}
+
+// Get characters from UART
+int board_uart_read(uint8_t* buf, int len) {
+  for (int i=0; i<len; i++) {
+    int c = getchar();
+    if (c == EOF) {
+      return i;
+    }
+    buf[i] = (uint8_t) c;
+  }
+  return len;
+}
+
+// Send characters to UART
+int board_uart_write(void const* buf, int len) {
+  for (int i = 0; i < len; i++) {
+    putchar(((char*) buf)[i]);
+  }
+  return len;
+}
+
+int board_getchar(void) {
+  return getchar();
+}
+
+//--------------------------------------------------------------------
+// PHY Init
+//--------------------------------------------------------------------
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4)
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 3, 0)
+
+#include "esp_private/usb_phy.h"
+#include "soc/usb_pins.h"
+
+static usb_phy_handle_t phy_hdl;
+
+bool usb_init(void) {
+  // Configure USB PHY
+  usb_phy_config_t phy_conf = {
+    .controller = USB_PHY_CTRL_OTG,
+    .target = USB_PHY_TARGET_INT,
+
+    // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver
+#if CFG_TUD_ENABLED
+    .otg_mode = USB_OTG_MODE_DEVICE,
+#elif CFG_TUH_ENABLED
+    .otg_mode = USB_OTG_MODE_HOST,
+#endif
+    // https://github.com/hathach/tinyusb/issues/2943#issuecomment-2601888322
+    // Set speed to undefined (auto-detect) to avoid timinng/racing issue with S3 with host such as macOS
+    .otg_speed = USB_PHY_SPEED_UNDEFINED,
+  };
+
+  usb_new_phy(&phy_conf, &phy_hdl);
+
+  return true;
+}
+
+#else
+
+#include "esp_private/usb_phy.h"
+#include "hal/usb_hal.h"
+#include "soc/usb_periph.h"
+
+static void configure_pins(usb_hal_context_t* usb) {
+  /* usb_periph_iopins currently configures USB_OTG as USB Device.
+   * Introduce additional parameters in usb_hal_context_t when adding support
+   * for USB Host. */
+  for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
+    if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
+      esp_rom_gpio_pad_select_gpio(iopin->pin);
+      if (iopin->is_output) {
+        esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
+      } else {
+        esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
+        if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT)) {
+          gpio_ll_input_enable(&GPIO, iopin->pin);
+        }
+      }
+      esp_rom_gpio_pad_unhold(iopin->pin);
+    }
+  }
+
+  if (!usb->use_external_phy) {
+    gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
+    gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
+  }
+}
+
+bool usb_init(void) {
+  // USB Controller Hal init
+  periph_module_reset(PERIPH_USB_MODULE);
+  periph_module_enable(PERIPH_USB_MODULE);
+
+  usb_hal_context_t hal = {
+    .use_external_phy = false // use built-in PHY
+  };
+
+  usb_hal_init(&hal);
+  configure_pins(&hal);
+
+  return true;
+}
+
+#endif
+#endif
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+static spi_device_handle_t max3421_spi;
+SemaphoreHandle_t max3421_intr_sem;
+
+static void IRAM_ATTR max3421_isr_handler(void* arg) {
+  (void) arg; // arg is gpio num
+
+  BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+  xSemaphoreGiveFromISR(max3421_intr_sem, &xHigherPriorityTaskWoken);
+  if (xHigherPriorityTaskWoken) {
+    portYIELD_FROM_ISR();
+  }
+}
+
+static void max3421_intr_task(void* param) {
+  (void) param;
+
+  while (1) {
+    xSemaphoreTake(max3421_intr_sem, portMAX_DELAY);
+    tuh_int_handler(BOARD_TUH_RHPORT, false);
+  }
+}
+
+static void max3421_init(void) {
+  // CS pin
+  gpio_set_direction(MAX3421_CS_PIN, GPIO_MODE_OUTPUT);
+  gpio_set_level(MAX3421_CS_PIN, 1);
+
+  // SPI
+  spi_bus_config_t buscfg = {
+      .miso_io_num = MAX3421_MISO_PIN,
+      .mosi_io_num = MAX3421_MOSI_PIN,
+      .sclk_io_num = MAX3421_SCK_PIN,
+      .quadwp_io_num = -1,
+      .quadhd_io_num = -1,
+      .data4_io_num = -1,
+      .data5_io_num = -1,
+      .data6_io_num = -1,
+      .data7_io_num = -1,
+      .max_transfer_sz = 1024
+  };
+  ESP_ERROR_CHECK(spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
+
+  spi_device_interface_config_t max3421_cfg = {
+      .mode = 0,
+      .clock_speed_hz = 20000000, // S2/S3 can work with 26 Mhz, but esp32 seems only work up to 20 Mhz
+      .spics_io_num = -1, // manual control CS
+      .queue_size = 1
+  };
+  ESP_ERROR_CHECK(spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi));
+
+  // Interrupt pin
+  max3421_intr_sem = xSemaphoreCreateBinary();
+  xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES - 2, NULL);
+
+  gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
+  gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
+
+  gpio_install_isr_service(0);
+  gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL);
+}
+
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+  if (enabled) {
+    gpio_intr_enable(MAX3421_INTR_PIN);
+  } else {
+    gpio_intr_disable(MAX3421_INTR_PIN);
+  }
+}
+
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  gpio_set_level(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+  (void) rhport;
+
+  if (tx_buf == NULL) {
+    // fifo read, transmit rx_buf as dummy
+    tx_buf = rx_buf;
+  }
+
+  // length in bits
+  size_t const len_bits = xfer_bytes << 3;
+
+  spi_transaction_t xact = {
+      .length = len_bits,
+      .rxlength = rx_buf ? len_bits : 0,
+      .tx_buffer = tx_buf,
+      .rx_buffer = rx_buf
+  };
+
+  ESP_ERROR_CHECK(spi_device_transmit(max3421_spi, &xact));
+  return true;
+}
+
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/CHANGELOG.md b/hw/bsp/espressif/components/led_strip/CHANGELOG.md
new file mode 100644
index 000000000..51c0cd30c
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/CHANGELOG.md
@@ -0,0 +1,38 @@
+## 2.5.0
+
+- Enabled support for IDF4.4 and above
+  - with RMT backend only
+- Added API `led_strip_set_pixel_hsv`
+
+## 2.4.0
+
+- Support configurable SPI mode to control leds
+  - recommend enabling DMA when using SPI mode
+
+## 2.3.0
+
+- Support configurable RMT channel size by setting `mem_block_symbols`
+
+## 2.2.0
+
+- Support for 4 components RGBW leds (SK6812):
+  - in led_strip_config_t new fields
+      led_pixel_format, controlling byte format (LED_PIXEL_FORMAT_GRB, LED_PIXEL_FORMAT_GRBW)
+      led_model, used to configure bit timing (LED_MODEL_WS2812, LED_MODEL_SK6812)
+  - new API led_strip_set_pixel_rgbw
+  - new interface type set_pixel_rgbw
+
+## 2.1.0
+
+- Support DMA feature, which offloads the CPU by a lot when it comes to drive a bunch of LEDs
+- Support various RMT clock sources
+- Acquire and release the power management lock before and after each refresh
+- New driver flag: `invert_out` which can invert the led control signal by hardware
+
+## 2.0.0
+
+- Reimplemented the driver using the new RMT driver (`driver/rmt_tx.h`)
+
+## 1.0.0
+
+- Initial driver version, based on the legacy RMT driver (`driver/rmt.h`)
diff --git a/hw/bsp/espressif/components/led_strip/CMakeLists.txt b/hw/bsp/espressif/components/led_strip/CMakeLists.txt
new file mode 100644
index 000000000..15de610cc
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/CMakeLists.txt
@@ -0,0 +1,22 @@
+include($ENV{IDF_PATH}/tools/cmake/version.cmake)
+
+set(srcs "src/led_strip_api.c")
+
+if("${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}" VERSION_GREATER_EQUAL "5.0")
+    if(CONFIG_SOC_RMT_SUPPORTED)
+        list(APPEND srcs "src/led_strip_rmt_dev.c" "src/led_strip_rmt_encoder.c")
+    endif()
+else()
+    list(APPEND srcs "src/led_strip_rmt_dev_idf4.c")
+endif()
+
+# the SPI backend driver relies on something that was added in IDF 5.1
+if("${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}" VERSION_GREATER_EQUAL "5.1")
+    if(CONFIG_SOC_GPSPI_SUPPORTED)
+        list(APPEND srcs "src/led_strip_spi_dev.c")
+    endif()
+endif()
+
+idf_component_register(SRCS ${srcs}
+                       INCLUDE_DIRS "include" "interface"
+                       REQUIRES "driver")
diff --git a/hw/bsp/espressif/components/led_strip/LICENSE b/hw/bsp/espressif/components/led_strip/LICENSE
new file mode 100644
index 000000000..d64569567
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/LICENSE
@@ -0,0 +1,202 @@
+
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diff --git a/hw/bsp/espressif/components/led_strip/README.md b/hw/bsp/espressif/components/led_strip/README.md
new file mode 100644
index 000000000..543d29642
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/README.md
@@ -0,0 +1,97 @@
+# LED Strip Driver
+
+[![Component Registry](https://components.espressif.com/components/espressif/led_strip/badge.svg)](https://components.espressif.com/components/espressif/led_strip)
+
+This driver is designed for addressable LEDs like [WS2812](http://www.world-semi.com/Certifications/WS2812B.html), where each LED is controlled by a single data line.
+
+## Backend Controllers
+
+### The [RMT](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/rmt.html) Peripheral
+
+This is the most economical way to drive the LEDs because it only consumes one RMT channel, leaving other channels free to use. However, the memory usage increases dramatically with the number of LEDs. If the RMT hardware can't be assist by DMA, the driver will going into interrupt very frequently, thus result in a high CPU usage. What's worse, if the RMT interrupt is delayed or not serviced in time (e.g. if Wi-Fi interrupt happens on the same CPU core), the RMT transaction will be corrupted and the LEDs will display incorrect colors. If you want to use RMT to drive a large number of LEDs, you'd better to enable the DMA feature if possible [^1].
+
+#### Allocate LED Strip Object with RMT Backend
+
+```c
+#define BLINK_GPIO 0
+
+led_strip_handle_t led_strip;
+
+/* LED strip initialization with the GPIO and pixels number*/
+led_strip_config_t strip_config = {
+    .strip_gpio_num = BLINK_GPIO, // The GPIO that connected to the LED strip's data line
+    .max_leds = 1, // The number of LEDs in the strip,
+    .led_pixel_format = LED_PIXEL_FORMAT_GRB, // Pixel format of your LED strip
+    .led_model = LED_MODEL_WS2812, // LED strip model
+    .flags.invert_out = false, // whether to invert the output signal (useful when your hardware has a level inverter)
+};
+
+led_strip_rmt_config_t rmt_config = {
+#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 0, 0)
+    .rmt_channel = 0,
+#else
+    .clk_src = RMT_CLK_SRC_DEFAULT, // different clock source can lead to different power consumption
+    .resolution_hz = 10 * 1000 * 1000, // 10MHz
+    .flags.with_dma = false, // whether to enable the DMA feature
+#endif
+};
+ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip));
+```
+
+You can create multiple LED strip objects with different GPIOs and pixel numbers. The backend driver will automatically allocate the RMT channel for you if there is more available.
+
+### The [SPI](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/spi_master.html) Peripheral
+
+SPI peripheral can also be used to generate the timing required by the LED strip. However this backend is not as economical as the RMT one, because it will take up the whole **bus**, unlike the RMT just takes one **channel**. You **CAN'T** connect other devices to the same SPI bus if it's been used by the led_strip, because the led_strip doesn't have the concept of "Chip Select".
+
+Please note, the SPI backend has a dependency of **ESP-IDF >= 5.1**
+
+#### Allocate LED Strip Object with SPI Backend
+
+```c
+#define BLINK_GPIO 0
+
+led_strip_handle_t led_strip;
+
+/* LED strip initialization with the GPIO and pixels number*/
+led_strip_config_t strip_config = {
+    .strip_gpio_num = BLINK_GPIO, // The GPIO that connected to the LED strip's data line
+    .max_leds = 1, // The number of LEDs in the strip,
+    .led_pixel_format = LED_PIXEL_FORMAT_GRB, // Pixel format of your LED strip
+    .led_model = LED_MODEL_WS2812, // LED strip model
+    .flags.invert_out = false, // whether to invert the output signal (useful when your hardware has a level inverter)
+};
+
+led_strip_spi_config_t spi_config = {
+    .clk_src = SPI_CLK_SRC_DEFAULT, // different clock source can lead to different power consumption
+    .flags.with_dma = true, // Using DMA can improve performance and help drive more LEDs
+    .spi_bus = SPI2_HOST,   // SPI bus ID
+};
+ESP_ERROR_CHECK(led_strip_new_spi_device(&strip_config, &spi_config, &led_strip));
+```
+
+The number of LED strip objects can be created depends on how many free SPI buses are free to use in your project.
+
+## FAQ
+
+* Which led_strip backend should I choose?
+  * It depends on your application requirement and target chip's ability.
+
+    ```mermaid
+    flowchart LR
+    A{Is RMT supported?}
+    A --> |No| B[SPI backend]
+    B --> C{Does the led strip has \n a larger number of LEDs?}
+    C --> |No| D[Don't have to enable the DMA of the backend]
+    C --> |Yes| E[Enable the DMA of the backend]
+    A --> |Yes| F{Does the led strip has \n a larger number of LEDs?}
+    F --> |Yes| G{Does RMT support DMA?}
+    G --> |Yes| E
+    G --> |No| B
+    F --> |No| H[RMT backend] --> D
+    ```
+
+* How to set the brightness of the LED strip?
+  * You can tune the brightness by scaling the value of each R-G-B element with a **same** factor. But pay attention to the overflow of the value.
+
+[^1]: The RMT DMA feature is not available on all ESP chips. Please check the data sheet before using it.
diff --git a/hw/bsp/espressif/components/led_strip/api.md b/hw/bsp/espressif/components/led_strip/api.md
new file mode 100644
index 000000000..6581d6604
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/api.md
@@ -0,0 +1,454 @@
+# API Reference
+
+## Header files
+
+- [include/led_strip.h](#file-includeled_striph)
+- [include/led_strip_rmt.h](#file-includeled_strip_rmth)
+- [include/led_strip_spi.h](#file-includeled_strip_spih)
+- [include/led_strip_types.h](#file-includeled_strip_typesh)
+- [interface/led_strip_interface.h](#file-interfaceled_strip_interfaceh)
+
+## File include/led_strip.h
+
+## Functions
+
+| Type | Name |
+| ---: | :--- |
+|  esp\_err\_t | [**led\_strip\_clear**](#function-led_strip_clear) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip) <br>_Clear LED strip (turn off all LEDs)_ |
+|  esp\_err\_t | [**led\_strip\_del**](#function-led_strip_del) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip) <br>_Free LED strip resources._ |
+|  esp\_err\_t | [**led\_strip\_refresh**](#function-led_strip_refresh) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip) <br>_Refresh memory colors to LEDs._ |
+|  esp\_err\_t | [**led\_strip\_set\_pixel**](#function-led_strip_set_pixel) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip, uint32\_t index, uint32\_t red, uint32\_t green, uint32\_t blue) <br>_Set RGB for a specific pixel._ |
+|  esp\_err\_t | [**led\_strip\_set\_pixel\_hsv**](#function-led_strip_set_pixel_hsv) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip, uint32\_t index, uint16\_t hue, uint8\_t saturation, uint8\_t value) <br>_Set HSV for a specific pixel._ |
+|  esp\_err\_t | [**led\_strip\_set\_pixel\_rgbw**](#function-led_strip_set_pixel_rgbw) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip, uint32\_t index, uint32\_t red, uint32\_t green, uint32\_t blue, uint32\_t white) <br>_Set RGBW for a specific pixel._ |
+
+## Functions Documentation
+
+### function `led_strip_clear`
+
+_Clear LED strip (turn off all LEDs)_
+
+```c
+esp_err_t led_strip_clear (
+    led_strip_handle_t strip
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+
+**Returns:**
+
+- ESP\_OK: Clear LEDs successfully
+- ESP\_FAIL: Clear LEDs failed because some other error occurred
+
+### function `led_strip_del`
+
+_Free LED strip resources._
+
+```c
+esp_err_t led_strip_del (
+    led_strip_handle_t strip
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+
+**Returns:**
+
+- ESP\_OK: Free resources successfully
+- ESP\_FAIL: Free resources failed because error occurred
+
+### function `led_strip_refresh`
+
+_Refresh memory colors to LEDs._
+
+```c
+esp_err_t led_strip_refresh (
+    led_strip_handle_t strip
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+
+**Returns:**
+
+- ESP\_OK: Refresh successfully
+- ESP\_FAIL: Refresh failed because some other error occurred
+
+**Note:**
+
+: After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
+
+### function `led_strip_set_pixel`
+
+_Set RGB for a specific pixel._
+
+```c
+esp_err_t led_strip_set_pixel (
+    led_strip_handle_t strip,
+    uint32_t index,
+    uint32_t red,
+    uint32_t green,
+    uint32_t blue
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `red` red part of color
+- `green` green part of color
+- `blue` blue part of color
+
+**Returns:**
+
+- ESP\_OK: Set RGB for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set RGB for a specific pixel failed because of invalid parameters
+- ESP\_FAIL: Set RGB for a specific pixel failed because other error occurred
+
+### function `led_strip_set_pixel_hsv`
+
+_Set HSV for a specific pixel._
+
+```c
+esp_err_t led_strip_set_pixel_hsv (
+    led_strip_handle_t strip,
+    uint32_t index,
+    uint16_t hue,
+    uint8_t saturation,
+    uint8_t value
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `hue` hue part of color (0 - 360)
+- `saturation` saturation part of color (0 - 255)
+- `value` value part of color (0 - 255)
+
+**Returns:**
+
+- ESP\_OK: Set HSV color for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set HSV color for a specific pixel failed because of an invalid argument
+- ESP\_FAIL: Set HSV color for a specific pixel failed because other error occurred
+
+### function `led_strip_set_pixel_rgbw`
+
+_Set RGBW for a specific pixel._
+
+```c
+esp_err_t led_strip_set_pixel_rgbw (
+    led_strip_handle_t strip,
+    uint32_t index,
+    uint32_t red,
+    uint32_t green,
+    uint32_t blue,
+    uint32_t white
+)
+```
+
+**Note:**
+
+Only call this function if your led strip does have the white component (e.g. SK6812-RGBW)
+
+**Note:**
+
+Also see `led_strip_set_pixel` if you only want to specify the RGB part of the color and bypass the white component
+
+**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `red` red part of color
+- `green` green part of color
+- `blue` blue part of color
+- `white` separate white component
+
+**Returns:**
+
+- ESP\_OK: Set RGBW color for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set RGBW color for a specific pixel failed because of an invalid argument
+- ESP\_FAIL: Set RGBW color for a specific pixel failed because other error occurred
+
+## File include/led_strip_rmt.h
+
+## Structures and Types
+
+| Type | Name |
+| ---: | :--- |
+| struct | [**led\_strip\_rmt\_config\_t**](#struct-led_strip_rmt_config_t) <br>_LED Strip RMT specific configuration._ |
+
+## Functions
+
+| Type | Name |
+| ---: | :--- |
+|  esp\_err\_t | [**led\_strip\_new\_rmt\_device**](#function-led_strip_new_rmt_device) (const [**led\_strip\_config\_t**](#struct-led_strip_config_t) \*led\_config, const [**led\_strip\_rmt\_config\_t**](#struct-led_strip_rmt_config_t) \*rmt\_config, [**led\_strip\_handle\_t**](#struct-led_strip_t) \*ret\_strip) <br>_Create LED strip based on RMT TX channel._ |
+
+## Structures and Types Documentation
+
+### struct `led_strip_rmt_config_t`
+
+_LED Strip RMT specific configuration._
+
+Variables:
+
+- rmt\_clock\_source\_t clk_src  <br>RMT clock source
+
+- struct [**led\_strip\_rmt\_config\_t**](#struct-led_strip_rmt_config_t) flags  <br>Extra driver flags
+
+- size\_t mem_block_symbols  <br>How many RMT symbols can one RMT channel hold at one time. Set to 0 will fallback to use the default size.
+
+- uint32\_t resolution_hz  <br>RMT tick resolution, if set to zero, a default resolution (10MHz) will be applied
+
+- uint32\_t with_dma  <br>Use DMA to transmit data
+
+## Functions Documentation
+
+### function `led_strip_new_rmt_device`
+
+_Create LED strip based on RMT TX channel._
+
+```c
+esp_err_t led_strip_new_rmt_device (
+    const led_strip_config_t *led_config,
+    const led_strip_rmt_config_t *rmt_config,
+    led_strip_handle_t *ret_strip
+)
+```
+
+**Parameters:**
+
+- `led_config` LED strip configuration
+- `rmt_config` RMT specific configuration
+- `ret_strip` Returned LED strip handle
+
+**Returns:**
+
+- ESP\_OK: create LED strip handle successfully
+- ESP\_ERR\_INVALID\_ARG: create LED strip handle failed because of invalid argument
+- ESP\_ERR\_NO\_MEM: create LED strip handle failed because of out of memory
+- ESP\_FAIL: create LED strip handle failed because some other error
+
+## File include/led_strip_spi.h
+
+## Structures and Types
+
+| Type | Name |
+| ---: | :--- |
+| struct | [**led\_strip\_spi\_config\_t**](#struct-led_strip_spi_config_t) <br>_LED Strip SPI specific configuration._ |
+
+## Functions
+
+| Type | Name |
+| ---: | :--- |
+|  esp\_err\_t | [**led\_strip\_new\_spi\_device**](#function-led_strip_new_spi_device) (const [**led\_strip\_config\_t**](#struct-led_strip_config_t) \*led\_config, const [**led\_strip\_spi\_config\_t**](#struct-led_strip_spi_config_t) \*spi\_config, [**led\_strip\_handle\_t**](#struct-led_strip_t) \*ret\_strip) <br>_Create LED strip based on SPI MOSI channel._ |
+
+## Structures and Types Documentation
+
+### struct `led_strip_spi_config_t`
+
+_LED Strip SPI specific configuration._
+
+Variables:
+
+- spi\_clock\_source\_t clk_src  <br>SPI clock source
+
+- struct [**led\_strip\_spi\_config\_t**](#struct-led_strip_spi_config_t) flags  <br>Extra driver flags
+
+- spi\_host\_device\_t spi_bus  <br>SPI bus ID. Which buses are available depends on the specific chip
+
+- uint32\_t with_dma  <br>Use DMA to transmit data
+
+## Functions Documentation
+
+### function `led_strip_new_spi_device`
+
+_Create LED strip based on SPI MOSI channel._
+
+```c
+esp_err_t led_strip_new_spi_device (
+    const led_strip_config_t *led_config,
+    const led_strip_spi_config_t *spi_config,
+    led_strip_handle_t *ret_strip
+)
+```
+
+**Note:**
+
+Although only the MOSI line is used for generating the signal, the whole SPI bus can't be used for other purposes.
+
+**Parameters:**
+
+- `led_config` LED strip configuration
+- `spi_config` SPI specific configuration
+- `ret_strip` Returned LED strip handle
+
+**Returns:**
+
+- ESP\_OK: create LED strip handle successfully
+- ESP\_ERR\_INVALID\_ARG: create LED strip handle failed because of invalid argument
+- ESP\_ERR\_NOT\_SUPPORTED: create LED strip handle failed because of unsupported configuration
+- ESP\_ERR\_NO\_MEM: create LED strip handle failed because of out of memory
+- ESP\_FAIL: create LED strip handle failed because some other error
+
+## File include/led_strip_types.h
+
+## Structures and Types
+
+| Type | Name |
+| ---: | :--- |
+| enum  | [**led\_model\_t**](#enum-led_model_t)  <br>_LED strip model._ |
+| enum  | [**led\_pixel\_format\_t**](#enum-led_pixel_format_t)  <br>_LED strip pixel format._ |
+| struct | [**led\_strip\_config\_t**](#struct-led_strip_config_t) <br>_LED Strip Configuration._ |
+| typedef struct [**led\_strip\_t**](#struct-led_strip_t) \* | [**led\_strip\_handle\_t**](#typedef-led_strip_handle_t)  <br>_LED strip handle._ |
+
+## Structures and Types Documentation
+
+### enum `led_model_t`
+
+_LED strip model._
+
+```c
+enum led_model_t {
+    LED_MODEL_WS2812,
+    LED_MODEL_SK6812,
+    LED_MODEL_INVALID
+};
+```
+
+**Note:**
+
+Different led model may have different timing parameters, so we need to distinguish them.
+
+### enum `led_pixel_format_t`
+
+_LED strip pixel format._
+
+```c
+enum led_pixel_format_t {
+    LED_PIXEL_FORMAT_GRB,
+    LED_PIXEL_FORMAT_GRBW,
+    LED_PIXEL_FORMAT_INVALID
+};
+```
+
+### struct `led_strip_config_t`
+
+_LED Strip Configuration._
+
+Variables:
+
+- struct [**led\_strip\_config\_t**](#struct-led_strip_config_t) flags  <br>Extra driver flags
+
+- uint32\_t invert_out  <br>Invert output signal
+
+- led\_model\_t led_model  <br>LED model
+
+- led\_pixel\_format\_t led_pixel_format  <br>LED pixel format
+
+- uint32\_t max_leds  <br>Maximum LEDs in a single strip
+
+- int strip_gpio_num  <br>GPIO number that used by LED strip
+
+### typedef `led_strip_handle_t`
+
+_LED strip handle._
+
+```c
+typedef struct led_strip_t* led_strip_handle_t;
+```
+
+## File interface/led_strip_interface.h
+
+## Structures and Types
+
+| Type | Name |
+| ---: | :--- |
+| struct | [**led\_strip\_t**](#struct-led_strip_t) <br>_LED strip interface definition._ |
+| typedef struct [**led\_strip\_t**](#struct-led_strip_t) | [**led\_strip\_t**](#typedef-led_strip_t)  <br> |
+
+## Structures and Types Documentation
+
+### struct `led_strip_t`
+
+_LED strip interface definition._
+
+Variables:
+
+- esp\_err\_t(\* clear  <br>_Clear LED strip (turn off all LEDs)_<br>**Parameters:**
+
+- `strip` LED strip
+- `timeout_ms` timeout value for clearing task
+
+**Returns:**
+
+- ESP\_OK: Clear LEDs successfully
+- ESP\_FAIL: Clear LEDs failed because some other error occurred
+
+- esp\_err\_t(\* del  <br>_Free LED strip resources._<br>**Parameters:**
+
+- `strip` LED strip
+
+**Returns:**
+
+- ESP\_OK: Free resources successfully
+- ESP\_FAIL: Free resources failed because error occurred
+
+- esp\_err\_t(\* refresh  <br>_Refresh memory colors to LEDs._<br>**Parameters:**
+
+- `strip` LED strip
+- `timeout_ms` timeout value for refreshing task
+
+**Returns:**
+
+- ESP\_OK: Refresh successfully
+- ESP\_FAIL: Refresh failed because some other error occurred
+
+**Note:**
+
+: After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
+
+- esp\_err\_t(\* set_pixel  <br>_Set RGB for a specific pixel._<br>**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `red` red part of color
+- `green` green part of color
+- `blue` blue part of color
+
+**Returns:**
+
+- ESP\_OK: Set RGB for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set RGB for a specific pixel failed because of invalid parameters
+- ESP\_FAIL: Set RGB for a specific pixel failed because other error occurred
+
+- esp\_err\_t(\* set_pixel_rgbw  <br>_Set RGBW for a specific pixel. Similar to_ `set_pixel`_but also set the white component._<br>**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `red` red part of color
+- `green` green part of color
+- `blue` blue part of color
+- `white` separate white component
+
+**Returns:**
+
+- ESP\_OK: Set RGBW color for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set RGBW color for a specific pixel failed because of an invalid argument
+- ESP\_FAIL: Set RGBW color for a specific pixel failed because other error occurred
+
+### typedef `led_strip_t`
+
+```c
+typedef struct led_strip_t led_strip_t;
+```
+
+Type of LED strip
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/CMakeLists.txt b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/CMakeLists.txt
new file mode 100644
index 000000000..923c46310
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/CMakeLists.txt
@@ -0,0 +1,9 @@
+# For more information about build system see
+# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html
+# The following five lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+set(IDF_TARGET "esp32s3")
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(led_strip_rmt_ws2812)
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/README.md b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/README.md
new file mode 100644
index 000000000..ad52235d5
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/README.md
@@ -0,0 +1,31 @@
+# LED Strip Example (RMT backend + WS2812)
+
+This example demonstrates how to blink the WS2812 LED using the [led_strip](https://components.espressif.com/component/espressif/led_strip) component.
+
+## How to Use Example
+
+### Hardware Required
+
+* A development board with Espressif SoC
+* A USB cable for Power supply and programming
+* WS2812 LED strip
+
+### Configure the Example
+
+Before project configuration and build, be sure to set the correct chip target using `idf.py set-target <chip_name>`. Then assign the proper GPIO in the [source file](main/led_strip_rmt_ws2812_main.c). If your led strip has multiple LEDs, don't forget update the number.
+
+### Build and Flash
+
+Run `idf.py -p PORT build flash monitor` to build, flash and monitor the project.
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects.
+
+## Example Output
+
+```text
+I (299) gpio: GPIO[8]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
+I (309) example: Created LED strip object with RMT backend
+I (309) example: Start blinking LED strip
+```
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/CMakeLists.txt b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/CMakeLists.txt
new file mode 100644
index 000000000..37b9c1458
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "led_strip_rmt_ws2812_main.c"
+                       INCLUDE_DIRS ".")
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/idf_component.yml b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/idf_component.yml
new file mode 100644
index 000000000..916c366c7
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/idf_component.yml
@@ -0,0 +1,5 @@
+## IDF Component Manager Manifest File
+dependencies:
+  espressif/led_strip:
+    version: '^2'
+    override_path: '../../../'
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/led_strip_rmt_ws2812_main.c b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/led_strip_rmt_ws2812_main.c
new file mode 100644
index 000000000..4b20a5958
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/led_strip_rmt_ws2812_main.c
@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include <stdio.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "led_strip.h"
+#include "esp_log.h"
+#include "esp_err.h"
+
+// GPIO assignment
+#define LED_STRIP_BLINK_GPIO  48
+// Numbers of the LED in the strip
+#define LED_STRIP_LED_NUMBERS 1
+// 10MHz resolution, 1 tick = 0.1us (led strip needs a high resolution)
+#define LED_STRIP_RMT_RES_HZ  (10 * 1000 * 1000)
+
+static const char *TAG = "example";
+
+led_strip_handle_t configure_led(void)
+{
+    // LED strip general initialization, according to your led board design
+    led_strip_config_t strip_config = {
+        .strip_gpio_num = LED_STRIP_BLINK_GPIO,   // The GPIO that connected to the LED strip's data line
+        .max_leds = LED_STRIP_LED_NUMBERS,        // The number of LEDs in the strip,
+        .led_pixel_format = LED_PIXEL_FORMAT_GRB, // Pixel format of your LED strip
+        .led_model = LED_MODEL_WS2812,            // LED strip model
+        .flags.invert_out = false,                // whether to invert the output signal
+    };
+
+    // LED strip backend configuration: RMT
+    led_strip_rmt_config_t rmt_config = {
+#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 0, 0)
+        .rmt_channel = 0,
+#else
+        .clk_src = RMT_CLK_SRC_DEFAULT,        // different clock source can lead to different power consumption
+        .resolution_hz = LED_STRIP_RMT_RES_HZ, // RMT counter clock frequency
+        .flags.with_dma = false,               // DMA feature is available on ESP target like ESP32-S3
+#endif
+    };
+
+    // LED Strip object handle
+    led_strip_handle_t led_strip;
+    ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip));
+    ESP_LOGI(TAG, "Created LED strip object with RMT backend");
+    return led_strip;
+}
+
+void app_main(void)
+{
+    led_strip_handle_t led_strip = configure_led();
+    bool led_on_off = false;
+
+    ESP_LOGI(TAG, "Start blinking LED strip");
+    while (1) {
+        if (led_on_off) {
+            /* Set the LED pixel using RGB from 0 (0%) to 255 (100%) for each color */
+            for (int i = 0; i < LED_STRIP_LED_NUMBERS; i++) {
+                ESP_ERROR_CHECK(led_strip_set_pixel(led_strip, i, 5, 5, 5));
+            }
+            /* Refresh the strip to send data */
+            ESP_ERROR_CHECK(led_strip_refresh(led_strip));
+            ESP_LOGI(TAG, "LED ON!");
+        } else {
+            /* Set all LED off to clear all pixels */
+            ESP_ERROR_CHECK(led_strip_clear(led_strip));
+            ESP_LOGI(TAG, "LED OFF!");
+        }
+
+        led_on_off = !led_on_off;
+        vTaskDelay(pdMS_TO_TICKS(500));
+    }
+}
diff --git a/hw/bsp/espressif/components/led_strip/idf_component.yml b/hw/bsp/espressif/components/led_strip/idf_component.yml
new file mode 100644
index 000000000..1fd9b83ee
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/idf_component.yml
@@ -0,0 +1,5 @@
+version: "2.5.2"
+description: Driver for Addressable LED Strip (WS2812, etc)
+url: https://github.com/espressif/idf-extra-components/tree/master/led_strip
+dependencies:
+  idf: ">=4.4"
diff --git a/hw/bsp/espressif/components/led_strip/include/led_strip.h b/hw/bsp/espressif/components/led_strip/include/led_strip.h
new file mode 100644
index 000000000..38711744a
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/include/led_strip.h
@@ -0,0 +1,111 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "led_strip_rmt.h"
+#include "esp_idf_version.h"
+
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 0)
+#include "led_strip_spi.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set RGB for a specific pixel
+ *
+ * @param strip: LED strip
+ * @param index: index of pixel to set
+ * @param red: red part of color
+ * @param green: green part of color
+ * @param blue: blue part of color
+ *
+ * @return
+ *      - ESP_OK: Set RGB for a specific pixel successfully
+ *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
+ *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
+ */
+esp_err_t led_strip_set_pixel(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
+
+/**
+ * @brief Set RGBW for a specific pixel
+ *
+ * @note Only call this function if your led strip does have the white component (e.g. SK6812-RGBW)
+ * @note Also see `led_strip_set_pixel` if you only want to specify the RGB part of the color and bypass the white component
+ *
+ * @param strip: LED strip
+ * @param index: index of pixel to set
+ * @param red: red part of color
+ * @param green: green part of color
+ * @param blue: blue part of color
+ * @param white: separate white component
+ *
+ * @return
+ *      - ESP_OK: Set RGBW color for a specific pixel successfully
+ *      - ESP_ERR_INVALID_ARG: Set RGBW color for a specific pixel failed because of an invalid argument
+ *      - ESP_FAIL: Set RGBW color for a specific pixel failed because other error occurred
+ */
+esp_err_t led_strip_set_pixel_rgbw(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white);
+
+/**
+ * @brief Set HSV for a specific pixel
+ *
+ * @param strip: LED strip
+ * @param index: index of pixel to set
+ * @param hue: hue part of color (0 - 360)
+ * @param saturation: saturation part of color (0 - 255)
+ * @param value: value part of color (0 - 255)
+ *
+ * @return
+ *      - ESP_OK: Set HSV color for a specific pixel successfully
+ *      - ESP_ERR_INVALID_ARG: Set HSV color for a specific pixel failed because of an invalid argument
+ *      - ESP_FAIL: Set HSV color for a specific pixel failed because other error occurred
+ */
+esp_err_t led_strip_set_pixel_hsv(led_strip_handle_t strip, uint32_t index, uint16_t hue, uint8_t saturation, uint8_t value);
+
+/**
+ * @brief Refresh memory colors to LEDs
+ *
+ * @param strip: LED strip
+ *
+ * @return
+ *      - ESP_OK: Refresh successfully
+ *      - ESP_FAIL: Refresh failed because some other error occurred
+ *
+ * @note:
+ *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
+ */
+esp_err_t led_strip_refresh(led_strip_handle_t strip);
+
+/**
+ * @brief Clear LED strip (turn off all LEDs)
+ *
+ * @param strip: LED strip
+ *
+ * @return
+ *      - ESP_OK: Clear LEDs successfully
+ *      - ESP_FAIL: Clear LEDs failed because some other error occurred
+ */
+esp_err_t led_strip_clear(led_strip_handle_t strip);
+
+/**
+ * @brief Free LED strip resources
+ *
+ * @param strip: LED strip
+ *
+ * @return
+ *      - ESP_OK: Free resources successfully
+ *      - ESP_FAIL: Free resources failed because error occurred
+ */
+esp_err_t led_strip_del(led_strip_handle_t strip);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/include/led_strip_rmt.h b/hw/bsp/espressif/components/led_strip/include/led_strip_rmt.h
new file mode 100644
index 000000000..b575aeaba
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/include/led_strip_rmt.h
@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "led_strip_types.h"
+#include "esp_idf_version.h"
+
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0)
+#include "driver/rmt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LED Strip RMT specific configuration
+ */
+typedef struct {
+#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 0, 0)
+    uint8_t rmt_channel;        /*!< Specify the channel number, the legacy RMT driver doesn't support channel allocator */
+#else // new driver supports specify the clock source and clock resolution
+    rmt_clock_source_t clk_src; /*!< RMT clock source */
+    uint32_t resolution_hz;     /*!< RMT tick resolution, if set to zero, a default resolution (10MHz) will be applied */
+#endif
+    size_t mem_block_symbols;   /*!< How many RMT symbols can one RMT channel hold at one time. Set to 0 will fallback to use the default size. */
+    struct {
+        uint32_t with_dma: 1;   /*!< Use DMA to transmit data */
+    } flags;                    /*!< Extra driver flags */
+} led_strip_rmt_config_t;
+
+/**
+ * @brief Create LED strip based on RMT TX channel
+ *
+ * @param led_config LED strip configuration
+ * @param rmt_config RMT specific configuration
+ * @param ret_strip Returned LED strip handle
+ * @return
+ *      - ESP_OK: create LED strip handle successfully
+ *      - ESP_ERR_INVALID_ARG: create LED strip handle failed because of invalid argument
+ *      - ESP_ERR_NO_MEM: create LED strip handle failed because of out of memory
+ *      - ESP_FAIL: create LED strip handle failed because some other error
+ */
+esp_err_t led_strip_new_rmt_device(const led_strip_config_t *led_config, const led_strip_rmt_config_t *rmt_config, led_strip_handle_t *ret_strip);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/include/led_strip_spi.h b/hw/bsp/espressif/components/led_strip/include/led_strip_spi.h
new file mode 100644
index 000000000..eb3524936
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/include/led_strip_spi.h
@@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/spi_master.h"
+#include "led_strip_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LED Strip SPI specific configuration
+ */
+typedef struct {
+    spi_clock_source_t clk_src; /*!< SPI clock source */
+    spi_host_device_t spi_bus;  /*!< SPI bus ID. Which buses are available depends on the specific chip */
+    struct {
+        uint32_t with_dma: 1;   /*!< Use DMA to transmit data */
+    } flags;                    /*!< Extra driver flags */
+} led_strip_spi_config_t;
+
+/**
+ * @brief Create LED strip based on SPI MOSI channel
+ * @note Although only the MOSI line is used for generating the signal, the whole SPI bus can't be used for other purposes.
+ *
+ * @param led_config LED strip configuration
+ * @param spi_config SPI specific configuration
+ * @param ret_strip Returned LED strip handle
+ * @return
+ *      - ESP_OK: create LED strip handle successfully
+ *      - ESP_ERR_INVALID_ARG: create LED strip handle failed because of invalid argument
+ *      - ESP_ERR_NOT_SUPPORTED: create LED strip handle failed because of unsupported configuration
+ *      - ESP_ERR_NO_MEM: create LED strip handle failed because of out of memory
+ *      - ESP_FAIL: create LED strip handle failed because some other error
+ */
+esp_err_t led_strip_new_spi_device(const led_strip_config_t *led_config, const led_strip_spi_config_t *spi_config, led_strip_handle_t *ret_strip);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/include/led_strip_types.h b/hw/bsp/espressif/components/led_strip/include/led_strip_types.h
new file mode 100644
index 000000000..691f0bc39
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/include/led_strip_types.h
@@ -0,0 +1,54 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LED strip pixel format
+ */
+typedef enum {
+    LED_PIXEL_FORMAT_GRB,    /*!< Pixel format: GRB */
+    LED_PIXEL_FORMAT_GRBW,   /*!< Pixel format: GRBW */
+    LED_PIXEL_FORMAT_INVALID /*!< Invalid pixel format */
+} led_pixel_format_t;
+
+/**
+ * @brief LED strip model
+ * @note Different led model may have different timing parameters, so we need to distinguish them.
+ */
+typedef enum {
+    LED_MODEL_WS2812, /*!< LED strip model: WS2812 */
+    LED_MODEL_SK6812, /*!< LED strip model: SK6812 */
+    LED_MODEL_INVALID /*!< Invalid LED strip model */
+} led_model_t;
+
+/**
+ * @brief LED strip handle
+ */
+typedef struct led_strip_t *led_strip_handle_t;
+
+/**
+ * @brief LED Strip Configuration
+ */
+typedef struct {
+    int strip_gpio_num;      /*!< GPIO number that used by LED strip */
+    uint32_t max_leds;       /*!< Maximum LEDs in a single strip */
+    led_pixel_format_t led_pixel_format; /*!< LED pixel format */
+    led_model_t led_model;   /*!< LED model */
+
+    struct {
+        uint32_t invert_out: 1; /*!< Invert output signal */
+    } flags;                    /*!< Extra driver flags */
+} led_strip_config_t;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/interface/led_strip_interface.h b/hw/bsp/espressif/components/led_strip/interface/led_strip_interface.h
new file mode 100644
index 000000000..3de4c2715
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/interface/led_strip_interface.h
@@ -0,0 +1,95 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct led_strip_t led_strip_t; /*!< Type of LED strip */
+
+/**
+ * @brief LED strip interface definition
+ */
+struct led_strip_t {
+    /**
+     * @brief Set RGB for a specific pixel
+     *
+     * @param strip: LED strip
+     * @param index: index of pixel to set
+     * @param red: red part of color
+     * @param green: green part of color
+     * @param blue: blue part of color
+     *
+     * @return
+     *      - ESP_OK: Set RGB for a specific pixel successfully
+     *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
+     *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
+     */
+    esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
+
+    /**
+     * @brief Set RGBW for a specific pixel. Similar to `set_pixel` but also set the white component
+     *
+     * @param strip: LED strip
+     * @param index: index of pixel to set
+     * @param red: red part of color
+     * @param green: green part of color
+     * @param blue: blue part of color
+     * @param white: separate white component
+     *
+     * @return
+     *      - ESP_OK: Set RGBW color for a specific pixel successfully
+     *      - ESP_ERR_INVALID_ARG: Set RGBW color for a specific pixel failed because of an invalid argument
+     *      - ESP_FAIL: Set RGBW color for a specific pixel failed because other error occurred
+     */
+    esp_err_t (*set_pixel_rgbw)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white);
+
+    /**
+     * @brief Refresh memory colors to LEDs
+     *
+     * @param strip: LED strip
+     * @param timeout_ms: timeout value for refreshing task
+     *
+     * @return
+     *      - ESP_OK: Refresh successfully
+     *      - ESP_FAIL: Refresh failed because some other error occurred
+     *
+     * @note:
+     *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
+     */
+    esp_err_t (*refresh)(led_strip_t *strip);
+
+    /**
+     * @brief Clear LED strip (turn off all LEDs)
+     *
+     * @param strip: LED strip
+     * @param timeout_ms: timeout value for clearing task
+     *
+     * @return
+     *      - ESP_OK: Clear LEDs successfully
+     *      - ESP_FAIL: Clear LEDs failed because some other error occurred
+     */
+    esp_err_t (*clear)(led_strip_t *strip);
+
+    /**
+     * @brief Free LED strip resources
+     *
+     * @param strip: LED strip
+     *
+     * @return
+     *      - ESP_OK: Free resources successfully
+     *      - ESP_FAIL: Free resources failed because error occurred
+     */
+    esp_err_t (*del)(led_strip_t *strip);
+};
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_api.c b/hw/bsp/espressif/components/led_strip/src/led_strip_api.c
new file mode 100644
index 000000000..6eb86b8f1
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_api.c
@@ -0,0 +1,94 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_log.h"
+#include "esp_check.h"
+#include "led_strip.h"
+#include "led_strip_interface.h"
+
+static const char *TAG = "led_strip";
+
+esp_err_t led_strip_set_pixel(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->set_pixel(strip, index, red, green, blue);
+}
+
+esp_err_t led_strip_set_pixel_hsv(led_strip_handle_t strip, uint32_t index, uint16_t hue, uint8_t saturation, uint8_t value)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+
+    uint32_t red = 0;
+    uint32_t green = 0;
+    uint32_t blue = 0;
+
+    uint32_t rgb_max = value;
+    uint32_t rgb_min = rgb_max * (255 - saturation) / 255.0f;
+
+    uint32_t i = hue / 60;
+    uint32_t diff = hue % 60;
+
+    // RGB adjustment amount by hue
+    uint32_t rgb_adj = (rgb_max - rgb_min) * diff / 60;
+
+    switch (i) {
+    case 0:
+        red = rgb_max;
+        green = rgb_min + rgb_adj;
+        blue = rgb_min;
+        break;
+    case 1:
+        red = rgb_max - rgb_adj;
+        green = rgb_max;
+        blue = rgb_min;
+        break;
+    case 2:
+        red = rgb_min;
+        green = rgb_max;
+        blue = rgb_min + rgb_adj;
+        break;
+    case 3:
+        red = rgb_min;
+        green = rgb_max - rgb_adj;
+        blue = rgb_max;
+        break;
+    case 4:
+        red = rgb_min + rgb_adj;
+        green = rgb_min;
+        blue = rgb_max;
+        break;
+    default:
+        red = rgb_max;
+        green = rgb_min;
+        blue = rgb_max - rgb_adj;
+        break;
+    }
+
+    return strip->set_pixel(strip, index, red, green, blue);
+}
+
+esp_err_t led_strip_set_pixel_rgbw(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->set_pixel_rgbw(strip, index, red, green, blue, white);
+}
+
+esp_err_t led_strip_refresh(led_strip_handle_t strip)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->refresh(strip);
+}
+
+esp_err_t led_strip_clear(led_strip_handle_t strip)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->clear(strip);
+}
+
+esp_err_t led_strip_del(led_strip_handle_t strip)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->del(strip);
+}
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev.c b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev.c
new file mode 100644
index 000000000..1cbf0e45a
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev.c
@@ -0,0 +1,164 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <sys/cdefs.h>
+#include "esp_log.h"
+#include "esp_check.h"
+#include "driver/rmt_tx.h"
+#include "led_strip.h"
+#include "led_strip_interface.h"
+#include "led_strip_rmt_encoder.h"
+
+#define LED_STRIP_RMT_DEFAULT_RESOLUTION 10000000 // 10MHz resolution
+#define LED_STRIP_RMT_DEFAULT_TRANS_QUEUE_SIZE 4
+// the memory size of each RMT channel, in words (4 bytes)
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+#define LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS 64
+#else
+#define LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS 48
+#endif
+
+static const char *TAG = "led_strip_rmt";
+
+typedef struct {
+    led_strip_t base;
+    rmt_channel_handle_t rmt_chan;
+    rmt_encoder_handle_t strip_encoder;
+    uint32_t strip_len;
+    uint8_t bytes_per_pixel;
+    uint8_t pixel_buf[];
+} led_strip_rmt_obj;
+
+static esp_err_t led_strip_rmt_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_FALSE(index < rmt_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of maximum number of LEDs");
+    uint32_t start = index * rmt_strip->bytes_per_pixel;
+    // In thr order of GRB, as LED strip like WS2812 sends out pixels in this order
+    rmt_strip->pixel_buf[start + 0] = green & 0xFF;
+    rmt_strip->pixel_buf[start + 1] = red & 0xFF;
+    rmt_strip->pixel_buf[start + 2] = blue & 0xFF;
+    if (rmt_strip->bytes_per_pixel > 3) {
+        rmt_strip->pixel_buf[start + 3] = 0;
+    }
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_set_pixel_rgbw(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_FALSE(index < rmt_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of maximum number of LEDs");
+    ESP_RETURN_ON_FALSE(rmt_strip->bytes_per_pixel == 4, ESP_ERR_INVALID_ARG, TAG, "wrong LED pixel format, expected 4 bytes per pixel");
+    uint8_t *buf_start = rmt_strip->pixel_buf + index * 4;
+    // SK6812 component order is GRBW
+    *buf_start = green & 0xFF;
+    *++buf_start = red & 0xFF;
+    *++buf_start = blue & 0xFF;
+    *++buf_start = white & 0xFF;
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_refresh(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    rmt_transmit_config_t tx_conf = {
+        .loop_count = 0,
+    };
+
+    ESP_RETURN_ON_ERROR(rmt_enable(rmt_strip->rmt_chan), TAG, "enable RMT channel failed");
+    ESP_RETURN_ON_ERROR(rmt_transmit(rmt_strip->rmt_chan, rmt_strip->strip_encoder, rmt_strip->pixel_buf,
+                                     rmt_strip->strip_len * rmt_strip->bytes_per_pixel, &tx_conf), TAG, "transmit pixels by RMT failed");
+    ESP_RETURN_ON_ERROR(rmt_tx_wait_all_done(rmt_strip->rmt_chan, -1), TAG, "flush RMT channel failed");
+    ESP_RETURN_ON_ERROR(rmt_disable(rmt_strip->rmt_chan), TAG, "disable RMT channel failed");
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_clear(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    // Write zero to turn off all leds
+    memset(rmt_strip->pixel_buf, 0, rmt_strip->strip_len * rmt_strip->bytes_per_pixel);
+    return led_strip_rmt_refresh(strip);
+}
+
+static esp_err_t led_strip_rmt_del(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_ERROR(rmt_del_channel(rmt_strip->rmt_chan), TAG, "delete RMT channel failed");
+    ESP_RETURN_ON_ERROR(rmt_del_encoder(rmt_strip->strip_encoder), TAG, "delete strip encoder failed");
+    free(rmt_strip);
+    return ESP_OK;
+}
+
+esp_err_t led_strip_new_rmt_device(const led_strip_config_t *led_config, const led_strip_rmt_config_t *rmt_config, led_strip_handle_t *ret_strip)
+{
+    led_strip_rmt_obj *rmt_strip = NULL;
+    esp_err_t ret = ESP_OK;
+    ESP_GOTO_ON_FALSE(led_config && rmt_config && ret_strip, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
+    ESP_GOTO_ON_FALSE(led_config->led_pixel_format < LED_PIXEL_FORMAT_INVALID, ESP_ERR_INVALID_ARG, err, TAG, "invalid led_pixel_format");
+    uint8_t bytes_per_pixel = 3;
+    if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRBW) {
+        bytes_per_pixel = 4;
+    } else if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRB) {
+        bytes_per_pixel = 3;
+    } else {
+        assert(false);
+    }
+    rmt_strip = calloc(1, sizeof(led_strip_rmt_obj) + led_config->max_leds * bytes_per_pixel);
+    ESP_GOTO_ON_FALSE(rmt_strip, ESP_ERR_NO_MEM, err, TAG, "no mem for rmt strip");
+    uint32_t resolution = rmt_config->resolution_hz ? rmt_config->resolution_hz : LED_STRIP_RMT_DEFAULT_RESOLUTION;
+
+    // for backward compatibility, if the user does not set the clk_src, use the default value
+    rmt_clock_source_t clk_src = RMT_CLK_SRC_DEFAULT;
+    if (rmt_config->clk_src) {
+        clk_src = rmt_config->clk_src;
+    }
+    size_t mem_block_symbols = LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS;
+    // override the default value if the user sets it
+    if (rmt_config->mem_block_symbols) {
+        mem_block_symbols = rmt_config->mem_block_symbols;
+    }
+    rmt_tx_channel_config_t rmt_chan_config = {
+        .clk_src = clk_src,
+        .gpio_num = led_config->strip_gpio_num,
+        .mem_block_symbols = mem_block_symbols,
+        .resolution_hz = resolution,
+        .trans_queue_depth = LED_STRIP_RMT_DEFAULT_TRANS_QUEUE_SIZE,
+        .flags.with_dma = rmt_config->flags.with_dma,
+        .flags.invert_out = led_config->flags.invert_out,
+    };
+    ESP_GOTO_ON_ERROR(rmt_new_tx_channel(&rmt_chan_config, &rmt_strip->rmt_chan), err, TAG, "create RMT TX channel failed");
+
+    led_strip_encoder_config_t strip_encoder_conf = {
+        .resolution = resolution,
+        .led_model = led_config->led_model
+    };
+    ESP_GOTO_ON_ERROR(rmt_new_led_strip_encoder(&strip_encoder_conf, &rmt_strip->strip_encoder), err, TAG, "create LED strip encoder failed");
+
+
+    rmt_strip->bytes_per_pixel = bytes_per_pixel;
+    rmt_strip->strip_len = led_config->max_leds;
+    rmt_strip->base.set_pixel = led_strip_rmt_set_pixel;
+    rmt_strip->base.set_pixel_rgbw = led_strip_rmt_set_pixel_rgbw;
+    rmt_strip->base.refresh = led_strip_rmt_refresh;
+    rmt_strip->base.clear = led_strip_rmt_clear;
+    rmt_strip->base.del = led_strip_rmt_del;
+
+    *ret_strip = &rmt_strip->base;
+    return ESP_OK;
+err:
+    if (rmt_strip) {
+        if (rmt_strip->rmt_chan) {
+            rmt_del_channel(rmt_strip->rmt_chan);
+        }
+        if (rmt_strip->strip_encoder) {
+            rmt_del_encoder(rmt_strip->strip_encoder);
+        }
+        free(rmt_strip);
+    }
+    return ret;
+}
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev_idf4.c b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev_idf4.c
new file mode 100644
index 000000000..a1067cd7c
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev_idf4.c
@@ -0,0 +1,194 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <sys/cdefs.h>
+#include "esp_log.h"
+#include "esp_check.h"
+#include "driver/rmt.h"
+#include "led_strip.h"
+#include "led_strip_interface.h"
+
+static const char *TAG = "led_strip_rmt";
+
+#define WS2812_T0H_NS   (300)
+#define WS2812_T0L_NS   (900)
+#define WS2812_T1H_NS   (900)
+#define WS2812_T1L_NS   (300)
+
+#define SK6812_T0H_NS   (300)
+#define SK6812_T0L_NS   (900)
+#define SK6812_T1H_NS   (600)
+#define SK6812_T1L_NS   (600)
+
+#define LED_STRIP_RESET_MS (10)
+
+// the memory size of each RMT channel, in words (4 bytes)
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+#define LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS 64
+#else
+#define LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS 48
+#endif
+
+static uint32_t led_t0h_ticks = 0;
+static uint32_t led_t1h_ticks = 0;
+static uint32_t led_t0l_ticks = 0;
+static uint32_t led_t1l_ticks = 0;
+
+typedef struct {
+    led_strip_t base;
+    rmt_channel_t rmt_channel;
+    uint32_t strip_len;
+    uint8_t bytes_per_pixel;
+    uint8_t buffer[0];
+} led_strip_rmt_obj;
+
+static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size,
+        size_t wanted_num, size_t *translated_size, size_t *item_num)
+{
+    if (src == NULL || dest == NULL) {
+        *translated_size = 0;
+        *item_num = 0;
+        return;
+    }
+    const rmt_item32_t bit0 = {{{ led_t0h_ticks, 1, led_t0l_ticks, 0 }}}; //Logical 0
+    const rmt_item32_t bit1 = {{{ led_t1h_ticks, 1, led_t1l_ticks, 0 }}}; //Logical 1
+    size_t size = 0;
+    size_t num = 0;
+    uint8_t *psrc = (uint8_t *)src;
+    rmt_item32_t *pdest = dest;
+    while (size < src_size && num < wanted_num) {
+        for (int i = 0; i < 8; i++) {
+            // MSB first
+            if (*psrc & (1 << (7 - i))) {
+                pdest->val =  bit1.val;
+            } else {
+                pdest->val =  bit0.val;
+            }
+            num++;
+            pdest++;
+        }
+        size++;
+        psrc++;
+    }
+    *translated_size = size;
+    *item_num = num;
+}
+
+static esp_err_t led_strip_rmt_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_FALSE(index < rmt_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of the maximum number of leds");
+    uint32_t start = index * rmt_strip->bytes_per_pixel;
+    // In thr order of GRB
+    rmt_strip->buffer[start + 0] = green & 0xFF;
+    rmt_strip->buffer[start + 1] = red & 0xFF;
+    rmt_strip->buffer[start + 2] = blue & 0xFF;
+    if (rmt_strip->bytes_per_pixel > 3) {
+        rmt_strip->buffer[start + 3] = 0;
+    }
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_refresh(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_ERROR(rmt_write_sample(rmt_strip->rmt_channel, rmt_strip->buffer, rmt_strip->strip_len * rmt_strip->bytes_per_pixel, true), TAG,
+                        "transmit RMT samples failed");
+    vTaskDelay(pdMS_TO_TICKS(LED_STRIP_RESET_MS));
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_clear(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    // Write zero to turn off all LEDs
+    memset(rmt_strip->buffer, 0, rmt_strip->strip_len * rmt_strip->bytes_per_pixel);
+    return led_strip_rmt_refresh(strip);
+}
+
+static esp_err_t led_strip_rmt_del(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_ERROR(rmt_driver_uninstall(rmt_strip->rmt_channel), TAG, "uninstall RMT driver failed");
+    free(rmt_strip);
+    return ESP_OK;
+}
+
+esp_err_t led_strip_new_rmt_device(const led_strip_config_t *led_config, const led_strip_rmt_config_t *dev_config, led_strip_handle_t *ret_strip)
+{
+    led_strip_rmt_obj *rmt_strip = NULL;
+    esp_err_t ret = ESP_OK;
+    ESP_RETURN_ON_FALSE(led_config && dev_config && ret_strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    ESP_RETURN_ON_FALSE(led_config->led_pixel_format < LED_PIXEL_FORMAT_INVALID, ESP_ERR_INVALID_ARG, TAG, "invalid led_pixel_format");
+    ESP_RETURN_ON_FALSE(dev_config->flags.with_dma == 0, ESP_ERR_NOT_SUPPORTED, TAG, "DMA is not supported");
+
+    uint8_t bytes_per_pixel = 3;
+    if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRBW) {
+        bytes_per_pixel = 4;
+    } else if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRB) {
+        bytes_per_pixel = 3;
+    } else {
+        assert(false);
+    }
+
+    // allocate memory for led_strip object
+    rmt_strip = calloc(1, sizeof(led_strip_rmt_obj) + led_config->max_leds * bytes_per_pixel);
+    ESP_RETURN_ON_FALSE(rmt_strip, ESP_ERR_NO_MEM, TAG, "request memory for les_strip failed");
+
+    // install RMT channel driver
+    rmt_config_t config = RMT_DEFAULT_CONFIG_TX(led_config->strip_gpio_num, dev_config->rmt_channel);
+    // set the minimal clock division because the LED strip needs a high clock resolution
+    config.clk_div = 2;
+
+    uint8_t mem_block_num = 2;
+    // override the default value if the user specify the mem block size
+    if (dev_config->mem_block_symbols) {
+        mem_block_num = (dev_config->mem_block_symbols + LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS / 2) / LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS;
+    }
+    config.mem_block_num = mem_block_num;
+
+    ESP_GOTO_ON_ERROR(rmt_config(&config), err, TAG, "RMT config failed");
+    ESP_GOTO_ON_ERROR(rmt_driver_install(config.channel, 0, 0), err, TAG, "RMT install failed");
+
+    uint32_t counter_clk_hz = 0;
+    rmt_get_counter_clock((rmt_channel_t)dev_config->rmt_channel, &counter_clk_hz);
+    // ns -> ticks
+    float ratio = (float)counter_clk_hz / 1e9;
+    if (led_config->led_model == LED_MODEL_WS2812) {
+        led_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS);
+        led_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS);
+        led_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS);
+        led_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS);
+    } else if (led_config->led_model == LED_MODEL_SK6812) {
+        led_t0h_ticks = (uint32_t)(ratio * SK6812_T0H_NS);
+        led_t0l_ticks = (uint32_t)(ratio * SK6812_T0L_NS);
+        led_t1h_ticks = (uint32_t)(ratio * SK6812_T1H_NS);
+        led_t1l_ticks = (uint32_t)(ratio * SK6812_T1L_NS);
+    } else {
+        assert(false);
+    }
+
+    // adapter to translates the LES strip date frame into RMT symbols
+    rmt_translator_init((rmt_channel_t)dev_config->rmt_channel, ws2812_rmt_adapter);
+
+    rmt_strip->bytes_per_pixel = bytes_per_pixel;
+    rmt_strip->rmt_channel = (rmt_channel_t)dev_config->rmt_channel;
+    rmt_strip->strip_len = led_config->max_leds;
+    rmt_strip->base.set_pixel = led_strip_rmt_set_pixel;
+    rmt_strip->base.refresh = led_strip_rmt_refresh;
+    rmt_strip->base.clear = led_strip_rmt_clear;
+    rmt_strip->base.del = led_strip_rmt_del;
+
+    *ret_strip = &rmt_strip->base;
+    return ESP_OK;
+
+err:
+    if (rmt_strip) {
+        free(rmt_strip);
+    }
+    return ret;
+}
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.c b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.c
new file mode 100644
index 000000000..d352ac07f
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.c
@@ -0,0 +1,146 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_check.h"
+#include "led_strip_rmt_encoder.h"
+
+static const char *TAG = "led_rmt_encoder";
+
+typedef struct {
+    rmt_encoder_t base;
+    rmt_encoder_t *bytes_encoder;
+    rmt_encoder_t *copy_encoder;
+    int state;
+    rmt_symbol_word_t reset_code;
+} rmt_led_strip_encoder_t;
+
+static size_t rmt_encode_led_strip(rmt_encoder_t *encoder, rmt_channel_handle_t channel, const void *primary_data, size_t data_size, rmt_encode_state_t *ret_state)
+{
+    rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base);
+    rmt_encoder_handle_t bytes_encoder = led_encoder->bytes_encoder;
+    rmt_encoder_handle_t copy_encoder = led_encoder->copy_encoder;
+    rmt_encode_state_t session_state = 0;
+    rmt_encode_state_t state = 0;
+    size_t encoded_symbols = 0;
+    switch (led_encoder->state) {
+    case 0: // send RGB data
+        encoded_symbols += bytes_encoder->encode(bytes_encoder, channel, primary_data, data_size, &session_state);
+        if (session_state & RMT_ENCODING_COMPLETE) {
+            led_encoder->state = 1; // switch to next state when current encoding session finished
+        }
+        if (session_state & RMT_ENCODING_MEM_FULL) {
+            state |= RMT_ENCODING_MEM_FULL;
+            goto out; // yield if there's no free space for encoding artifacts
+        }
+    // fall-through
+    case 1: // send reset code
+        encoded_symbols += copy_encoder->encode(copy_encoder, channel, &led_encoder->reset_code,
+                                                sizeof(led_encoder->reset_code), &session_state);
+        if (session_state & RMT_ENCODING_COMPLETE) {
+            led_encoder->state = 0; // back to the initial encoding session
+            state |= RMT_ENCODING_COMPLETE;
+        }
+        if (session_state & RMT_ENCODING_MEM_FULL) {
+            state |= RMT_ENCODING_MEM_FULL;
+            goto out; // yield if there's no free space for encoding artifacts
+        }
+    }
+out:
+    *ret_state = state;
+    return encoded_symbols;
+}
+
+static esp_err_t rmt_del_led_strip_encoder(rmt_encoder_t *encoder)
+{
+    rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base);
+    rmt_del_encoder(led_encoder->bytes_encoder);
+    rmt_del_encoder(led_encoder->copy_encoder);
+    free(led_encoder);
+    return ESP_OK;
+}
+
+static esp_err_t rmt_led_strip_encoder_reset(rmt_encoder_t *encoder)
+{
+    rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base);
+    rmt_encoder_reset(led_encoder->bytes_encoder);
+    rmt_encoder_reset(led_encoder->copy_encoder);
+    led_encoder->state = 0;
+    return ESP_OK;
+}
+
+esp_err_t rmt_new_led_strip_encoder(const led_strip_encoder_config_t *config, rmt_encoder_handle_t *ret_encoder)
+{
+    esp_err_t ret = ESP_OK;
+    rmt_led_strip_encoder_t *led_encoder = NULL;
+    ESP_GOTO_ON_FALSE(config && ret_encoder, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
+    ESP_GOTO_ON_FALSE(config->led_model < LED_MODEL_INVALID, ESP_ERR_INVALID_ARG, err, TAG, "invalid led model");
+    led_encoder = calloc(1, sizeof(rmt_led_strip_encoder_t));
+    ESP_GOTO_ON_FALSE(led_encoder, ESP_ERR_NO_MEM, err, TAG, "no mem for led strip encoder");
+    led_encoder->base.encode = rmt_encode_led_strip;
+    led_encoder->base.del = rmt_del_led_strip_encoder;
+    led_encoder->base.reset = rmt_led_strip_encoder_reset;
+    rmt_bytes_encoder_config_t bytes_encoder_config;
+    if (config->led_model == LED_MODEL_SK6812) {
+        bytes_encoder_config = (rmt_bytes_encoder_config_t) {
+            .bit0 = {
+                .level0 = 1,
+                .duration0 = 0.3 * config->resolution / 1000000, // T0H=0.3us
+                .level1 = 0,
+                .duration1 = 0.9 * config->resolution / 1000000, // T0L=0.9us
+            },
+            .bit1 = {
+                .level0 = 1,
+                .duration0 = 0.6 * config->resolution / 1000000, // T1H=0.6us
+                .level1 = 0,
+                .duration1 = 0.6 * config->resolution / 1000000, // T1L=0.6us
+            },
+            .flags.msb_first = 1 // SK6812 transfer bit order: G7...G0R7...R0B7...B0(W7...W0)
+        };
+    } else if (config->led_model == LED_MODEL_WS2812) {
+        // different led strip might have its own timing requirements, following parameter is for WS2812
+        bytes_encoder_config = (rmt_bytes_encoder_config_t) {
+            .bit0 = {
+                .level0 = 1,
+                .duration0 = 0.3 * config->resolution / 1000000, // T0H=0.3us
+                .level1 = 0,
+                .duration1 = 0.9 * config->resolution / 1000000, // T0L=0.9us
+            },
+            .bit1 = {
+                .level0 = 1,
+                .duration0 = 0.9 * config->resolution / 1000000, // T1H=0.9us
+                .level1 = 0,
+                .duration1 = 0.3 * config->resolution / 1000000, // T1L=0.3us
+            },
+            .flags.msb_first = 1 // WS2812 transfer bit order: G7...G0R7...R0B7...B0
+        };
+    } else {
+        assert(false);
+    }
+    ESP_GOTO_ON_ERROR(rmt_new_bytes_encoder(&bytes_encoder_config, &led_encoder->bytes_encoder), err, TAG, "create bytes encoder failed");
+    rmt_copy_encoder_config_t copy_encoder_config = {};
+    ESP_GOTO_ON_ERROR(rmt_new_copy_encoder(&copy_encoder_config, &led_encoder->copy_encoder), err, TAG, "create copy encoder failed");
+
+    uint32_t reset_ticks = config->resolution / 1000000 * 50 / 2; // reset code duration defaults to 50us
+    led_encoder->reset_code = (rmt_symbol_word_t) {
+        .level0 = 0,
+        .duration0 = reset_ticks,
+        .level1 = 0,
+        .duration1 = reset_ticks,
+    };
+    *ret_encoder = &led_encoder->base;
+    return ESP_OK;
+err:
+    if (led_encoder) {
+        if (led_encoder->bytes_encoder) {
+            rmt_del_encoder(led_encoder->bytes_encoder);
+        }
+        if (led_encoder->copy_encoder) {
+            rmt_del_encoder(led_encoder->copy_encoder);
+        }
+        free(led_encoder);
+    }
+    return ret;
+}
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.h b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.h
new file mode 100644
index 000000000..ba71e60ab
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.h
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "driver/rmt_encoder.h"
+#include "led_strip_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Type of led strip encoder configuration
+ */
+typedef struct {
+    uint32_t resolution;   /*!< Encoder resolution, in Hz */
+    led_model_t led_model; /*!< LED model */
+} led_strip_encoder_config_t;
+
+/**
+ * @brief Create RMT encoder for encoding LED strip pixels into RMT symbols
+ *
+ * @param[in] config Encoder configuration
+ * @param[out] ret_encoder Returned encoder handle
+ * @return
+ *      - ESP_ERR_INVALID_ARG for any invalid arguments
+ *      - ESP_ERR_NO_MEM out of memory when creating led strip encoder
+ *      - ESP_OK if creating encoder successfully
+ */
+esp_err_t rmt_new_led_strip_encoder(const led_strip_encoder_config_t *config, rmt_encoder_handle_t *ret_encoder);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_spi_dev.c b/hw/bsp/espressif/components/led_strip/src/led_strip_spi_dev.c
new file mode 100644
index 000000000..12ea8fbf3
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_spi_dev.c
@@ -0,0 +1,209 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <sys/cdefs.h>
+#include "esp_log.h"
+#include "esp_check.h"
+#include "esp_rom_gpio.h"
+#include "soc/spi_periph.h"
+#include "led_strip.h"
+#include "led_strip_interface.h"
+#include "hal/spi_hal.h"
+
+#define LED_STRIP_SPI_DEFAULT_RESOLUTION (2.5 * 1000 * 1000) // 2.5MHz resolution
+#define LED_STRIP_SPI_DEFAULT_TRANS_QUEUE_SIZE 4
+
+#define SPI_BYTES_PER_COLOR_BYTE 3
+#define SPI_BITS_PER_COLOR_BYTE (SPI_BYTES_PER_COLOR_BYTE * 8)
+
+static const char *TAG = "led_strip_spi";
+
+typedef struct {
+    led_strip_t base;
+    spi_host_device_t spi_host;
+    spi_device_handle_t spi_device;
+    uint32_t strip_len;
+    uint8_t bytes_per_pixel;
+    uint8_t pixel_buf[];
+} led_strip_spi_obj;
+
+// please make sure to zero-initialize the buf before calling this function
+static void __led_strip_spi_bit(uint8_t data, uint8_t *buf)
+{
+    // Each color of 1 bit is represented by 3 bits of SPI, low_level:100 ,high_level:110
+    // So a color byte occupies 3 bytes of SPI.
+    *(buf + 2) |= data & BIT(0) ? BIT(2) | BIT(1) : BIT(2);
+    *(buf + 2) |= data & BIT(1) ? BIT(5) | BIT(4) : BIT(5);
+    *(buf + 2) |= data & BIT(2) ? BIT(7) : 0x00;
+    *(buf + 1) |= BIT(0);
+    *(buf + 1) |= data & BIT(3) ? BIT(3) | BIT(2) : BIT(3);
+    *(buf + 1) |= data & BIT(4) ? BIT(6) | BIT(5) : BIT(6);
+    *(buf + 0) |= data & BIT(5) ? BIT(1) | BIT(0) : BIT(1);
+    *(buf + 0) |= data & BIT(6) ? BIT(4) | BIT(3) : BIT(4);
+    *(buf + 0) |= data & BIT(7) ? BIT(7) | BIT(6) : BIT(7);
+}
+
+static esp_err_t led_strip_spi_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+    ESP_RETURN_ON_FALSE(index < spi_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of maximum number of LEDs");
+    // LED_PIXEL_FORMAT_GRB takes 72bits(9bytes)
+    uint32_t start = index * spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE;
+    memset(spi_strip->pixel_buf + start, 0, spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE);
+    __led_strip_spi_bit(green, &spi_strip->pixel_buf[start]);
+    __led_strip_spi_bit(red, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE]);
+    __led_strip_spi_bit(blue, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE * 2]);
+    if (spi_strip->bytes_per_pixel > 3) {
+        __led_strip_spi_bit(0, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE * 3]);
+    }
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_spi_set_pixel_rgbw(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+    ESP_RETURN_ON_FALSE(index < spi_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of maximum number of LEDs");
+    ESP_RETURN_ON_FALSE(spi_strip->bytes_per_pixel == 4, ESP_ERR_INVALID_ARG, TAG, "wrong LED pixel format, expected 4 bytes per pixel");
+    // LED_PIXEL_FORMAT_GRBW takes 96bits(12bytes)
+    uint32_t start = index * spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE;
+    // SK6812 component order is GRBW
+    memset(spi_strip->pixel_buf + start, 0, spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE);
+    __led_strip_spi_bit(green, &spi_strip->pixel_buf[start]);
+    __led_strip_spi_bit(red, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE]);
+    __led_strip_spi_bit(blue, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE * 2]);
+    __led_strip_spi_bit(white, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE * 3]);
+
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_spi_refresh(led_strip_t *strip)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+    spi_transaction_t tx_conf;
+    memset(&tx_conf, 0, sizeof(tx_conf));
+
+    tx_conf.length = spi_strip->strip_len * spi_strip->bytes_per_pixel * SPI_BITS_PER_COLOR_BYTE;
+    tx_conf.tx_buffer = spi_strip->pixel_buf;
+    tx_conf.rx_buffer = NULL;
+    ESP_RETURN_ON_ERROR(spi_device_transmit(spi_strip->spi_device, &tx_conf), TAG, "transmit pixels by SPI failed");
+
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_spi_clear(led_strip_t *strip)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+    //Write zero to turn off all leds
+    memset(spi_strip->pixel_buf, 0, spi_strip->strip_len * spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE);
+    uint8_t *buf = spi_strip->pixel_buf;
+    for (int index = 0; index < spi_strip->strip_len * spi_strip->bytes_per_pixel; index++) {
+        __led_strip_spi_bit(0, buf);
+        buf += SPI_BYTES_PER_COLOR_BYTE;
+    }
+
+    return led_strip_spi_refresh(strip);
+}
+
+static esp_err_t led_strip_spi_del(led_strip_t *strip)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+
+    ESP_RETURN_ON_ERROR(spi_bus_remove_device(spi_strip->spi_device), TAG, "delete spi device failed");
+    ESP_RETURN_ON_ERROR(spi_bus_free(spi_strip->spi_host), TAG, "free spi bus failed");
+
+    free(spi_strip);
+    return ESP_OK;
+}
+
+esp_err_t led_strip_new_spi_device(const led_strip_config_t *led_config, const led_strip_spi_config_t *spi_config, led_strip_handle_t *ret_strip)
+{
+    led_strip_spi_obj *spi_strip = NULL;
+    esp_err_t ret = ESP_OK;
+    ESP_GOTO_ON_FALSE(led_config && spi_config && ret_strip, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
+    ESP_GOTO_ON_FALSE(led_config->led_pixel_format < LED_PIXEL_FORMAT_INVALID, ESP_ERR_INVALID_ARG, err, TAG, "invalid led_pixel_format");
+    uint8_t bytes_per_pixel = 3;
+    if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRBW) {
+        bytes_per_pixel = 4;
+    } else if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRB) {
+        bytes_per_pixel = 3;
+    } else {
+        assert(false);
+    }
+    uint32_t mem_caps = MALLOC_CAP_DEFAULT;
+    if (spi_config->flags.with_dma) {
+        // DMA buffer must be placed in internal SRAM
+        mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA;
+    }
+    spi_strip = heap_caps_calloc(1, sizeof(led_strip_spi_obj) + led_config->max_leds * bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE, mem_caps);
+
+    ESP_GOTO_ON_FALSE(spi_strip, ESP_ERR_NO_MEM, err, TAG, "no mem for spi strip");
+
+    spi_strip->spi_host = spi_config->spi_bus;
+    // for backward compatibility, if the user does not set the clk_src, use the default value
+    spi_clock_source_t clk_src = SPI_CLK_SRC_DEFAULT;
+    if (spi_config->clk_src) {
+        clk_src = spi_config->clk_src;
+    }
+
+    spi_bus_config_t spi_bus_cfg = {
+        .mosi_io_num = led_config->strip_gpio_num,
+        //Only use MOSI to generate the signal, set -1 when other pins are not used.
+        .miso_io_num = -1,
+        .sclk_io_num = -1,
+        .quadwp_io_num = -1,
+        .quadhd_io_num = -1,
+        .max_transfer_sz = led_config->max_leds * bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE,
+    };
+    ESP_GOTO_ON_ERROR(spi_bus_initialize(spi_strip->spi_host, &spi_bus_cfg, spi_config->flags.with_dma ? SPI_DMA_CH_AUTO : SPI_DMA_DISABLED), err, TAG, "create SPI bus failed");
+
+    if (led_config->flags.invert_out == true) {
+        esp_rom_gpio_connect_out_signal(led_config->strip_gpio_num, spi_periph_signal[spi_strip->spi_host].spid_out, true, false);
+    }
+
+    spi_device_interface_config_t spi_dev_cfg = {
+        .clock_source = clk_src,
+        .command_bits = 0,
+        .address_bits = 0,
+        .dummy_bits = 0,
+        .clock_speed_hz = LED_STRIP_SPI_DEFAULT_RESOLUTION,
+        .mode = 0,
+        //set -1 when CS is not used
+        .spics_io_num = -1,
+        .queue_size = LED_STRIP_SPI_DEFAULT_TRANS_QUEUE_SIZE,
+    };
+
+    ESP_GOTO_ON_ERROR(spi_bus_add_device(spi_strip->spi_host, &spi_dev_cfg, &spi_strip->spi_device), err, TAG, "Failed to add spi device");
+
+    int clock_resolution_khz = 0;
+    spi_device_get_actual_freq(spi_strip->spi_device, &clock_resolution_khz);
+    // TODO: ideally we should decide the SPI_BYTES_PER_COLOR_BYTE by the real clock resolution
+    // But now, let's fixed the resolution, the downside is, we don't support a clock source whose frequency is not multiple of LED_STRIP_SPI_DEFAULT_RESOLUTION
+    ESP_GOTO_ON_FALSE(clock_resolution_khz == LED_STRIP_SPI_DEFAULT_RESOLUTION / 1000, ESP_ERR_NOT_SUPPORTED, err,
+                      TAG, "unsupported clock resolution:%dKHz", clock_resolution_khz);
+
+    spi_strip->bytes_per_pixel = bytes_per_pixel;
+    spi_strip->strip_len = led_config->max_leds;
+    spi_strip->base.set_pixel = led_strip_spi_set_pixel;
+    spi_strip->base.set_pixel_rgbw = led_strip_spi_set_pixel_rgbw;
+    spi_strip->base.refresh = led_strip_spi_refresh;
+    spi_strip->base.clear = led_strip_spi_clear;
+    spi_strip->base.del = led_strip_spi_del;
+
+    *ret_strip = &spi_strip->base;
+    return ESP_OK;
+err:
+    if (spi_strip) {
+        if (spi_strip->spi_device) {
+            spi_bus_remove_device(spi_strip->spi_device);
+        }
+        if (spi_strip->spi_host) {
+            spi_bus_free(spi_strip->spi_host);
+        }
+        free(spi_strip);
+    }
+    return ret;
+}
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
new file mode 100644
index 000000000..00e288bad
--- /dev/null
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -0,0 +1,84 @@
+idf_build_get_property(target IDF_TARGET)
+
+set(srcs)
+set(includes_public)
+set(compile_options)
+set(tusb_src "${CMAKE_CURRENT_SOURCE_DIR}/../../../../../src")
+
+string(TOUPPER OPT_MCU_${target} tusb_mcu)
+list(APPEND compile_definitions
+  CFG_TUSB_MCU=${tusb_mcu}
+  CFG_TUSB_OS=OPT_OS_FREERTOS
+  BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+  BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+  BOARD_TUH_RHPORT=${RHPORT_HOST}
+  BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+  )
+
+if (target STREQUAL esp32p4)
+  # P4 change alignment to 64 (DCache line size) for possible DMA configuration
+  list(APPEND compile_definitions
+    CFG_TUD_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
+    CFG_TUH_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
+    )
+endif ()
+
+list(APPEND srcs
+  # common
+  ${tusb_src}/tusb.c
+  ${tusb_src}/common/tusb_fifo.c
+  # device
+  ${tusb_src}/device/usbd.c
+  ${tusb_src}/device/usbd_control.c
+  ${tusb_src}/class/audio/audio_device.c
+  ${tusb_src}/class/cdc/cdc_device.c
+  ${tusb_src}/class/dfu/dfu_device.c
+  ${tusb_src}/class/dfu/dfu_rt_device.c
+  ${tusb_src}/class/hid/hid_device.c
+  ${tusb_src}/class/midi/midi_device.c
+  ${tusb_src}/class/msc/msc_device.c
+  ${tusb_src}/class/net/ecm_rndis_device.c
+  ${tusb_src}/class/net/ncm_device.c
+  ${tusb_src}/class/usbtmc/usbtmc_device.c
+  ${tusb_src}/class/vendor/vendor_device.c
+  ${tusb_src}/class/video/video_device.c
+  ${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c
+  ${tusb_src}/portable/synopsys/dwc2/hcd_dwc2.c
+  ${tusb_src}/portable/synopsys/dwc2/dwc2_common.c
+  # host
+  ${tusb_src}/host/usbh.c
+  ${tusb_src}/host/hub.c
+  ${tusb_src}/class/cdc/cdc_host.c
+  ${tusb_src}/class/hid/hid_host.c
+  ${tusb_src}/class/msc/msc_host.c
+  ${tusb_src}/class/vendor/vendor_host.c
+  )
+
+# use max3421 as host controller
+if (MAX3421_HOST STREQUAL "1")
+  list(APPEND srcs ${tusb_src}/portable/analog/max3421/hcd_max3421.c)
+  list(APPEND compile_definitions CFG_TUH_MAX3421=1)
+endif ()
+
+if (DEFINED LOG)
+  list(APPEND compile_definitions CFG_TUSB_DEBUG=${LOG})
+  if (LOG STREQUAL "4")
+    # no inline for debug level 4
+    list(APPEND compile_definitions TU_ATTR_ALWAYS_INLINE=)
+  endif ()
+endif()
+
+if(DEFINED CFLAGS_CLI)
+  separate_arguments(CFLAGS_CLI)
+  list(APPEND compile_definitions ${CFLAGS_CLI})
+endif()
+
+
+idf_component_register(SRCS ${srcs}
+  INCLUDE_DIRS ${tusb_src}
+  REQUIRES src
+  PRIV_REQUIRES esp_mm
+  )
+
+target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake
new file mode 100644
index 000000000..daa12cdb4
--- /dev/null
+++ b/hw/bsp/espressif/family.cmake
@@ -0,0 +1,39 @@
+cmake_minimum_required(VERSION 3.5)
+
+# Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
+include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
+string(TOUPPER ${IDF_TARGET} FAMILY_MCUS)
+
+# Device port default to Port1 for P4 (highspeed), Port0 for others (fullspeed)
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+if (NOT DEFINED RHPORT_DEVICE)
+  if (IDF_TARGET STREQUAL "esp32p4")
+    set(RHPORT_DEVICE 1)
+  else ()
+    set(RHPORT_DEVICE 0)
+  endif ()
+endif()
+
+if (NOT DEFINED RHPORT_HOST)
+  if (IDF_TARGET STREQUAL "esp32p4")
+    set(RHPORT_HOST 1)
+  else ()
+    set(RHPORT_HOST 0)
+  endif ()
+endif()
+
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
+# Add example src and bsp directories
+set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
+
+# set SDKCONFIG for each IDF Target
+set(SDKCONFIG ${CMAKE_SOURCE_DIR}/sdkconfig.${IDF_TARGET})
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/espressif/family.mk
similarity index 62%
rename from hw/bsp/esp32s2/family.mk
rename to hw/bsp/espressif/family.mk
index b95098e15..0dc21b8eb 100644
--- a/hw/bsp/esp32s2/family.mk
+++ b/hw/bsp/espressif/family.mk
@@ -1,9 +1,21 @@
 #DEPS_SUBMODULES +=
 
+UF2_FAMILY_ID_esp32s2 = 0xbfdd4eee
+UF2_FAMILY_ID_esp32s3 = 0xc47e5767
+
+BOARD_CMAKE := $(file < $(TOP)/$(BOARD_PATH)/board.cmake)
+ifneq ($(findstring esp32s2,$(BOARD_CMAKE)),)
+	IDF_TARGET = esp32s2
+else
+ifneq ($(findstring esp32s3,$(BOARD_CMAKE)),)
+	IDF_TARGET = esp32s3
+endif
+endif
+
 .PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
 
 all:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) -DIDF_TARGET=esp32s2 build
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) build
 
 build: all
 
@@ -17,8 +29,6 @@ clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-com
 
 uf2: $(BUILD)/$(PROJECT).uf2
 
-UF2_FAMILY_ID = 0xbfdd4eee
 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
 	@echo CREATE $@
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
-
+	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID_$(IDF_TARGET)) -b 0x0 -c -o $@ $^
diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md
index 4aa1e153b..86d454f8e 100644
--- a/hw/bsp/f1c100s/README.md
+++ b/hw/bsp/f1c100s/README.md
@@ -17,4 +17,4 @@ Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then re
 
 ## TODO
 
-* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT` high speed MCU check in examples (maybe we should extract the logic?)
\ No newline at end of file
+* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX` high speed MCU check in examples (maybe we should extract the logic?)
diff --git a/hw/bsp/f1c100s/board.h b/hw/bsp/f1c100s/board.h
deleted file mode 100644
index 238ac796d..000000000
--- a/hw/bsp/f1c100s/board.h
+++ /dev/null
@@ -1 +0,0 @@
-// Nothing valuable here
\ No newline at end of file
diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk
deleted file mode 100644
index 5fe26a9ea..000000000
--- a/hw/bsp/f1c100s/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/allwinner
-
-DEFINES += -D__ARM32_ARCH__=5 -D__ARM926EJS__
-
-CFLAGS += \
-  -ffreestanding \
-  -std=gnu99 \
-  -march=armv5te \
-  -mtune=arm926ej-s \
-  -mfloat-abi=soft \
-  -marm \
-  -mno-thumb-interwork \
-  -Wno-unused-parameter \
-  -Wno-float-equal \
-  -DCFG_TUSB_MCU=OPT_MCU_F1C100S \
-  -Wno-error=cast-align \
-  -Wno-error=address-of-packed-member \
-  $(DEFINES)
-
-LD_FILE = hw/mcu/allwinner/f1c100s/f1c100s.ld
-LDFLAGS += -nostdlib -lgcc
-MCU_DIR = hw/mcu/allwinner/f1c100s
-
-SRC_C += \
-	src/portable/sunxi/dcd_sunxi_musb.c \
-	$(MCU_DIR)/machine/sys-uart.c \
-	$(MCU_DIR)/machine/exception.c \
-	$(MCU_DIR)/machine/sys-clock.c \
-	$(MCU_DIR)/machine/sys-copyself.c \
-	$(MCU_DIR)/machine/sys-dram.c \
-	$(MCU_DIR)/machine/sys-mmu.c \
-	$(MCU_DIR)/machine/sys-spi-flash.c \
-	$(MCU_DIR)/machine/f1c100s-intc.c \
-	$(MCU_DIR)/lib/malloc.c \
-	$(MCU_DIR)/lib/printf.c 
-
-SRC_S += \
-  $(MCU_DIR)/machine/start.S \
-	$(MCU_DIR)/lib/memcpy.S \
-	$(MCU_DIR)/lib/memset.S
-
-INC += \
-	$(TOP)/$(MCU_DIR)/include \
-	$(TOP)/$(BOARD_PATH)
-
-# flash target using xfel
-flash: flash-xfel
-
-exec: $(BUILD)/$(PROJECT).bin
-	xfel ddr 
-	xfel write 0x80000000 $<
-	xfel exec 0x80000000
\ No newline at end of file
diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.cmake b/hw/bsp/f1c100s/boards/f1c100s/board.cmake
new file mode 100644
index 000000000..98ed56c57
--- /dev/null
+++ b/hw/bsp/f1c100s/boards/f1c100s/board.cmake
@@ -0,0 +1,3 @@
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.h b/hw/bsp/f1c100s/boards/f1c100s/board.h
new file mode 100644
index 000000000..44b78f8fb
--- /dev/null
+++ b/hw/bsp/f1c100s/boards/f1c100s/board.h
@@ -0,0 +1,11 @@
+/* metadata:
+   name: Lctech Pi F1C200s
+   url: https://linux-sunxi.org/Lctech_Pi_F1C200s
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+// Nothing valuable here
+
+#endif
diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.mk b/hw/bsp/f1c100s/boards/f1c100s/board.mk
new file mode 100644
index 000000000..be830bd8c
--- /dev/null
+++ b/hw/bsp/f1c100s/boards/f1c100s/board.mk
@@ -0,0 +1 @@
+# nothing to do
diff --git a/hw/bsp/f1c100s/f1c100s.c b/hw/bsp/f1c100s/family.c
similarity index 76%
rename from hw/bsp/f1c100s/f1c100s.c
rename to hw/bsp/f1c100s/family.c
index d45072ecb..9e864363f 100644
--- a/hw/bsp/f1c100s/f1c100s.c
+++ b/hw/bsp/f1c100s/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,11 +24,15 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Sunxi
+*/
+
 #include <stdint.h>
 #include <malloc.h>
 #include <irqflags.h>
 #include <f1c100s-irq.h>
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 extern void sys_uart_putc(char c);
@@ -39,10 +43,9 @@ extern void sys_uart_putc(char c);
 
 static void timer_init(void);
 
-void board_init(void)
-{
+void board_init(void) {
   arch_local_irq_disable();
-	do_init_mem_pool();
+  do_init_mem_pool();
   f1c100s_intc_init();
   timer_init();
   printf("Timer INIT done\n");
@@ -50,42 +53,38 @@ void board_init(void)
 }
 
 // No LED, no button
-void board_led_write(bool state)
-{
-
+void board_led_write(bool state) {
+  (void) state;
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return 0;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
   int txsize = len;
   while (txsize--) {
-    sys_uart_putc(*(uint8_t const*)buf);
+    sys_uart_putc(*(uint8_t const*) buf);
     buf++;
   }
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 
-static void timer_handler(void)
-{
-  volatile uint32_t *temp_addr = (uint32_t *)(0x01C20C00 + 0x04);
+static void timer_handler(void) {
+  volatile uint32_t* temp_addr = (uint32_t*) (0x01C20C00 + 0x04);
 
   /* clear timer */
   *temp_addr |= 0x01;
@@ -95,36 +94,37 @@ static void timer_handler(void)
 
 static void timer_init(void) {
   uint32_t temp;
-  volatile uint32_t *temp_addr;
+  volatile uint32_t* temp_addr;
 
   /* reload value */
   temp = 12000000 / 1000;
-  temp_addr = (uint32_t *)(0x01C20C00 + 0x14);
+  temp_addr = (uint32_t*) (0x01C20C00 + 0x14);
   *temp_addr = temp;
 
   /* continuous | /2 | 24Mhz |  reload*/
   temp = (0x00 << 7) | (0x01 << 4) | (0x01 << 2) | (0x00 << 1);
-  temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
+  temp_addr = (uint32_t*) (0x01C20C00 + 0x10);
   *temp_addr &= 0xffffff00;
   *temp_addr |= temp;
 
   /* open timer irq */
   temp = 0x01 << 0;
-  temp_addr = (uint32_t *)(0x01C20C00);
+  temp_addr = (uint32_t*) (0x01C20C00);
   *temp_addr |= temp;
 
   /* set init value */
-  temp_addr = (uint32_t *)(0x01C20C00 + 0x18);
+  temp_addr = (uint32_t*) (0x01C20C00 + 0x18);
   *temp_addr = 0;
 
   /* begin run timer */
   temp = 0x01 << 0;
-  temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
+  temp_addr = (uint32_t*) (0x01C20C00 + 0x10);
   *temp_addr |= temp;
 
   f1c100s_intc_set_isr(F1C100S_IRQ_TIMER0, timer_handler);
   f1c100s_intc_enable_irq(F1C100S_IRQ_TIMER0);
 }
-#else 
+
+#else
 static void timer_init(void) { }
 #endif
diff --git a/hw/bsp/f1c100s/family.cmake b/hw/bsp/f1c100s/family.cmake
new file mode 100644
index 000000000..211c6645c
--- /dev/null
+++ b/hw/bsp/f1c100s/family.cmake
@@ -0,0 +1,114 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/allwinner/f1c100s)
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU arm926ej-s CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS F1C100S CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/f1c100s.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/machine/start.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/lib/malloc.c
+    ${SDK_DIR}/lib/printf.c
+    ${SDK_DIR}/lib/memcpy.S
+    ${SDK_DIR}/lib/memset.S
+    ${SDK_DIR}/machine/sys-uart.c
+    ${SDK_DIR}/machine/exception.c
+    ${SDK_DIR}/machine/sys-clock.c
+    ${SDK_DIR}/machine/sys-copyself.c
+    ${SDK_DIR}/machine/sys-dram.c
+    ${SDK_DIR}/machine/sys-mmu.c
+    ${SDK_DIR}/machine/sys-spi-flash.c
+    ${SDK_DIR}/machine/f1c100s-intc.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __ARM32_ARCH__=5
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -lgcc
+      --specs=nosys.specs --specs=nano.specs
+      "LINKER:--defsym=__bss_end__=__bss_end"
+      "LINKER:--defsym=__bss_start__=__bss_start"
+      "LINKER:--defsym=end=__bss_end"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_F1C100S)
+  target_sources(${TARGET} PRIVATE
+    ${TOP}/src/portable/sunxi/dcd_sunxi_musb.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/f1c100s/family.mk b/hw/bsp/f1c100s/family.mk
new file mode 100644
index 000000000..be416e72e
--- /dev/null
+++ b/hw/bsp/f1c100s/family.mk
@@ -0,0 +1,58 @@
+SDK_DIR = hw/mcu/allwinner/f1c100s
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= arm926ej-s
+
+#CFLAGS += \
+#  -march=armv5te \
+#  -mtune=arm926ej-s \
+#  -mfloat-abi=soft \
+#  -marm \
+
+CFLAGS += \
+  -ffreestanding \
+  -std=gnu99 \
+  -mno-thumb-interwork \
+  -D__ARM32_ARCH__=5 \
+  -D__ARM926EJS__ \
+  -Wno-float-equal \
+  -Wno-unused-parameter \
+  -DCFG_TUSB_MCU=OPT_MCU_F1C100S \
+  -Wno-error=array-bounds \
+
+LD_FILE = ${SDK_DIR}/f1c100s.ld
+
+# TODO may skip nanolib
+LDFLAGS += \
+  -nostdlib -lgcc \
+  --specs=nosys.specs --specs=nano.specs \
+
+SRC_C += \
+	src/portable/sunxi/dcd_sunxi_musb.c \
+	${SDK_DIR}/machine/sys-uart.c \
+	${SDK_DIR}/machine/exception.c \
+	${SDK_DIR}/machine/sys-clock.c \
+	${SDK_DIR}/machine/sys-copyself.c \
+	${SDK_DIR}/machine/sys-dram.c \
+	${SDK_DIR}/machine/sys-mmu.c \
+	${SDK_DIR}/machine/sys-spi-flash.c \
+	${SDK_DIR}/machine/f1c100s-intc.c \
+	${SDK_DIR}/lib/malloc.c \
+	${SDK_DIR}/lib/printf.c
+
+SRC_S += \
+  ${SDK_DIR}/machine/start.S \
+	${SDK_DIR}/lib/memcpy.S \
+	${SDK_DIR}/lib/memset.S
+
+INC += \
+	$(TOP)/${SDK_DIR}/include \
+	$(TOP)/$(BOARD_PATH)
+
+# flash target using xfel
+flash: flash-xfel
+
+exec: $(BUILD)/$(PROJECT).bin
+	xfel ddr
+	xfel write 0x80000000 $<
+	xfel exec 0x80000000
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index c5311b63f..04d537376 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -1,142 +1,642 @@
-if (NOT TARGET _family_support_marker)
-    add_library(_family_support_marker INTERFACE)
+include_guard(GLOBAL)
 
-    if (NOT FAMILY)
-        message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
+include(CMakePrintHelpers)
+
+# TOP is path to root directory
+set(TOP "${CMAKE_CURRENT_LIST_DIR}/../..")
+get_filename_component(TOP ${TOP} ABSOLUTE)
+
+set(UF2CONV_PY ${TOP}/tools/uf2/utils/uf2conv.py)
+
+#-------------------------------------------------------------
+# RTOS
+#-------------------------------------------------------------
+if (NOT DEFINED RTOS)
+  set(RTOS noos)
+endif ()
+
+#-------------------------------------------------------------
+# Toolchain
+# Can be changed via -DTOOLCHAIN=gcc|iar or -DCMAKE_C_COMPILER=
+#-------------------------------------------------------------
+# Detect toolchain based on CMAKE_C_COMPILER
+if (DEFINED CMAKE_C_COMPILER)
+  string(FIND ${CMAKE_C_COMPILER} "iccarm" IS_IAR)
+  string(FIND ${CMAKE_C_COMPILER} "clang" IS_CLANG)
+  string(FIND ${CMAKE_C_COMPILER} "gcc" IS_GCC)
+
+  if (NOT IS_IAR EQUAL -1)
+    set(TOOLCHAIN iar)
+  elseif (NOT IS_CLANG EQUAL -1)
+    set(TOOLCHAIN clang)
+  elseif (NOT IS_GCC EQUAL -1)
+    set(TOOLCHAIN gcc)
+  endif ()
+endif ()
+
+if (NOT DEFINED TOOLCHAIN)
+  set(TOOLCHAIN gcc)
+endif ()
+
+#-------------------------------------------------------------
+# FAMILY and BOARD
+#-------------------------------------------------------------
+if (NOT DEFINED FAMILY)
+  if (NOT DEFINED BOARD)
+    message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, espressif).
+    You can do this via -DFAMILY=xxx on the cmake command line")
+  endif ()
+
+  # Find path contains BOARD
+  file(GLOB BOARD_PATH LIST_DIRECTORIES true
+    RELATIVE ${TOP}/hw/bsp
+    ${TOP}/hw/bsp/*/boards/${BOARD}
+    )
+  if (NOT BOARD_PATH)
+    message(FATAL_ERROR "Could not detect FAMILY from BOARD=${BOARD}")
+  endif ()
+
+  # replace / with ; so that we can get the first element as FAMILY
+  string(REPLACE "/" ";" BOARD_PATH ${BOARD_PATH})
+  list(GET BOARD_PATH 0 FAMILY)
+  set(FAMILY ${FAMILY} CACHE STRING "Board family")
+endif ()
+
+if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
+  message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
+endif()
+
+if (NOT FAMILY STREQUAL rp2040)
+  # enable LTO if supported skip rp2040
+  include(CheckIPOSupported)
+  check_ipo_supported(RESULT IPO_SUPPORTED)
+  cmake_print_variables(IPO_SUPPORTED)
+  if (IPO_SUPPORTED)
+    set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+  endif()
+endif()
+
+if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED)
+  set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1)
+endif()
+
+#----------------------------------
+# Zephyr
+#----------------------------------
+if (RTOS STREQUAL zephyr)
+  set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY})
+  set(ZEPHYR_BOARD_ALIASES ${CMAKE_CURRENT_LIST_DIR}/zephyr_board_aliases.cmake)
+  find_package(Zephyr REQUIRED HINTS ${TOP}/zephyr)
+endif ()
+
+#-------------------------------------------------------------
+# Functions
+#-------------------------------------------------------------
+
+# Filter example based on only.txt and skip.txt
+function(family_filter RESULT DIR)
+  get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
+
+  if (EXISTS "${DIR}/skip.txt")
+    file(STRINGS "${DIR}/skip.txt" SKIPS_LINES)
+    foreach(MCU IN LISTS FAMILY_MCUS)
+      # For each line in only.txt
+      foreach(_line ${SKIPS_LINES})
+        # If mcu:xxx exists for this mcu then skip
+        if (${_line} STREQUAL "mcu:${MCU}" OR ${_line} STREQUAL "board:${BOARD}" OR ${_line} STREQUAL "family:${FAMILY}")
+          set(${RESULT} 0 PARENT_SCOPE)
+          return()
+        endif()
+      endforeach()
+    endforeach()
+  endif ()
+
+  if (EXISTS "${DIR}/only.txt")
+    file(STRINGS "${DIR}/only.txt" ONLYS_LINES)
+    foreach(MCU IN LISTS FAMILY_MCUS)
+      # For each line in only.txt
+      foreach(_line ${ONLYS_LINES})
+        # If mcu:xxx exists for this mcu or board:xxx then include
+        if (${_line} STREQUAL "mcu:${MCU}" OR ${_line} STREQUAL "board:${BOARD}" OR ${_line} STREQUAL "family:${FAMILY}")
+          set(${RESULT} 1 PARENT_SCOPE)
+          return()
+        endif()
+      endforeach()
+    endforeach()
+
+    # Didn't find it in only file so don't build
+    set(${RESULT} 0 PARENT_SCOPE)
+  else()
+    # only.txt not exist so build
+    set(${RESULT} 1 PARENT_SCOPE)
+  endif()
+endfunction()
+
+function(family_add_subdirectory DIR)
+  family_filter(SHOULD_ADD "${DIR}")
+  if (SHOULD_ADD)
+    add_subdirectory(${DIR})
+  endif()
+endfunction()
+
+function(family_get_project_name OUTPUT_NAME DIR)
+  get_filename_component(SHORT_NAME ${DIR} NAME)
+  set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
+endfunction()
+
+function(family_initialize_project PROJECT DIR)
+  # set output suffix to .elf (skip espressif and rp2040)
+  if(NOT FAMILY STREQUAL "espressif" AND NOT FAMILY STREQUAL "rp2040")
+    set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE)
+  endif()
+
+  family_filter(ALLOWED "${DIR}")
+  if (NOT ALLOWED)
+    get_filename_component(SHORT_NAME ${DIR} NAME)
+    message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
+  endif()
+endfunction()
+
+#-------------------------------------------------------------
+# Common Target Configure
+# Most families use these settings except rp2040 and espressif
+#-------------------------------------------------------------
+
+# Add RTOS to example
+function(family_add_rtos TARGET RTOS)
+  if (RTOS STREQUAL "freertos")
+    if (NOT TARGET freertos_config)
+      add_library(freertos_config INTERFACE)
+      target_include_directories(freertos_config INTERFACE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig)
+      # add board definition to freertos_config mostly for SystemCoreClock
+      target_link_libraries(freertos_config INTERFACE board_${BOARD})
     endif()
 
-    if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
-        message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
+    if (NOT TARGET freertos_kernel)
+      add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
+    endif ()
+
+    target_link_libraries(${TARGET} PUBLIC freertos_kernel)
+    target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_FREERTOS)
+  elseif (RTOS STREQUAL "zephyr")
+    target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_ZEPHYR)
+    target_include_directories(${TARGET} PUBLIC ${ZEPHYR_BASE}/include)
+  endif ()
+endfunction()
+
+# Add common configuration to example
+function(family_configure_common TARGET RTOS)
+  family_add_rtos(${TARGET} ${RTOS})
+
+  # Add BOARD_${BOARD} define
+  string(TOUPPER ${BOARD} BOARD_UPPER)
+  string(REPLACE "-" "_" BOARD_UPPER ${BOARD_UPPER})
+  target_compile_definitions(${TARGET} PUBLIC
+    BOARD_${BOARD_UPPER}
+  )
+
+  # compile define from command line
+  if(DEFINED CFLAGS_CLI)
+    separate_arguments(CFLAGS_CLI)
+    target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI})
+  endif()
+
+  # ETM Trace option
+  if (TRACE_ETM STREQUAL "1")
+    target_compile_definitions(${TARGET} PUBLIC TRACE_ETM)
+  endif ()
+
+  # LOGGER option
+  if (DEFINED LOGGER)
+    target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER})
+    # Add segger rtt to example
+    if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
+      target_sources(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
+      target_include_directories(${TARGET}  PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
+#      target_compile_definitions(${TARGET}  PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
+    endif ()
+  endif ()
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_compile_options(${TARGET} PRIVATE
+      -Wall
+      -Wextra
+      #-Werror
+      -Wfatal-errors
+      -Wdouble-promotion
+      -Wstrict-prototypes
+      -Wstrict-overflow
+      -Werror-implicit-function-declaration
+      -Wfloat-equal
+      -Wundef
+      -Wshadow
+      -Wwrite-strings
+      -Wsign-compare
+      -Wmissing-format-attribute
+      -Wunreachable-code
+      -Wcast-align
+      -Wcast-function-type
+      -Wcast-qual
+      -Wnull-dereference
+      -Wuninitialized
+      -Wunused
+      -Wunused-function
+      -Wreturn-type
+      -Wredundant-decls
+      -Wmissing-prototypes
+      )
+    target_link_options(${TARGET} PUBLIC "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map")
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0
+      AND NO_WARN_RWX_SEGMENTS_SUPPORTED AND (NOT RTOS STREQUAL zephyr))
+      target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
+    endif ()
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${TARGET} PUBLIC "LINKER:--map=$<TARGET_FILE:${TARGET}>.map")
+  endif ()
+
+  # run size after build
+#  find_program(SIZE_EXE ${CMAKE_SIZE})
+#  if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND)
+#    add_custom_command(TARGET ${TARGET} POST_BUILD
+#      COMMAND ${SIZE_EXE} $<TARGET_FILE:${TARGET}>
+#      )
+#  endif ()
+endfunction()
+
+# Add tinyusb to target
+function(family_add_tinyusb TARGET OPT_MCU)
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  # Add TinyUSB sources, include and common define
+  tinyusb_target_add(${TARGET})
+
+  # path to tusb_config.h
+  target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src)
+
+  target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_MCU=${OPT_MCU})
+  if (DEFINED LOG)
+    target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_DEBUG=${LOG})
+    if (LOG STREQUAL "4") # no inline for debug level 4
+      target_compile_definitions(${TARGET} PUBLIC TU_ATTR_ALWAYS_INLINE=)
+    endif ()
+  endif()
+
+  # use max3421 as host controller
+  if (MAX3421_HOST STREQUAL "1")
+    target_compile_definitions(${TARGET} PUBLIC CFG_TUH_MAX3421=1)
+    target_sources(${TARGET} PUBLIC
+      ${TOP}/src/portable/analog/max3421/hcd_max3421.c
+      )
+  endif ()
+endfunction()
+
+# Add bin/hex output
+function(family_add_bin_hex TARGET)
+  if (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    add_custom_command(TARGET ${TARGET} POST_BUILD
+      COMMAND ${CMAKE_OBJCOPY} --bin $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
+      COMMAND ${CMAKE_OBJCOPY} --ihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
+      VERBATIM)
+  else()
+    add_custom_command(TARGET ${TARGET} POST_BUILD
+      COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
+      COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
+      VERBATIM)
+  endif()
+endfunction()
+
+# Add uf2 output
+function(family_add_uf2 TARGET FAMILY_ID)
+  set(BIN_FILE $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex)
+  add_custom_command(TARGET ${TARGET} POST_BUILD
+    COMMAND python ${UF2CONV_PY} -f ${FAMILY_ID} -c -o $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.uf2 ${BIN_FILE}
+    VERBATIM)
+endfunction()
+
+#-------------------------------------------------------
+# Example Target Configure (Default rule)
+# These function can be redefined in FAMILY/family.cmake
+#--------------------------------------------------------
+
+function(family_configure_example TARGET RTOS)
+  # empty function, should be redefined in FAMILY/family.cmake
+endfunction()
+
+# Configure device example with RTOS
+function(family_configure_device_example TARGET RTOS)
+  family_configure_example(${TARGET} ${RTOS})
+endfunction()
+
+# Configure host example with RTOS
+function(family_configure_host_example TARGET RTOS)
+  family_configure_example(${TARGET} ${RTOS})
+endfunction()
+
+# Configure host + device example with RTOS
+function(family_configure_dual_usb_example TARGET RTOS)
+  family_configure_example(${TARGET} ${RTOS})
+endfunction()
+
+function(family_example_missing_dependency TARGET DEPENDENCY)
+  message(WARNING "${DEPENDENCY} submodule needed by ${TARGET} not found, please run 'python tools/get_deps.py ${DEPENDENCY}' to fetch it")
+endfunction()
+
+#----------------------------------
+# RPI specific: refactor later
+#----------------------------------
+function(family_add_default_example_warnings TARGET)
+  target_compile_options(${TARGET} PUBLIC
+    -Wall
+    -Wextra
+    -Werror
+    -Wfatal-errors
+    -Wdouble-promotion
+    -Wfloat-equal
+    # FIXME commented out because of https://github.com/raspberrypi/pico-sdk/issues/1468
+    #-Wshadow
+    -Wwrite-strings
+    -Wsign-compare
+    -Wmissing-format-attribute
+    -Wunreachable-code
+    -Wcast-align
+    -Wcast-qual
+    -Wnull-dereference
+    -Wuninitialized
+    -Wunused
+    -Wredundant-decls
+    #-Wstrict-prototypes
+    #-Werror-implicit-function-declaration
+    #-Wundef
+    )
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED)
+      target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
     endif()
 
-    function(family_filter RESULT DIR)
-        get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
-
-        if (EXISTS "${DIR}/only.txt")
-            file(READ "${DIR}/only.txt" ONLYS)
-            # Replace newlines with semicolon so that it is treated as a list by CMake
-            string(REPLACE "\n" ";" ONLYS_LINES ${ONLYS})
-            # For each mcu
-            foreach(MCU IN LISTS FAMILY_MCUS)
-                # For each line in only.txt
-                foreach(_line ${ONLYS_LINES})
-                    # If mcu:xxx exists for this mcu then include
-                    if (${_line} STREQUAL "mcu:${MCU}")
-                        set(${RESULT} 1 PARENT_SCOPE)
-                        return()
-                    endif()
-                endforeach()
-            endforeach()
-
-            # Didn't find it in only file so don't build
-            set(${RESULT} 0 PARENT_SCOPE)
-
-        elseif (EXISTS "${DIR}/skip.txt")
-            file(READ "${DIR}/skip.txt" SKIPS)
-            # Replace newlines with semicolon so that it is treated as a list by CMake
-            string(REPLACE "\n" ";" SKIPS_LINES ${SKIPS})
-            # For each mcu
-            foreach(MCU IN LISTS FAMILY_MCUS)
-                # For each line in only.txt
-                foreach(_line ${SKIPS_LINES})
-                    # If mcu:xxx exists for this mcu then skip
-                    if (${_line} STREQUAL "mcu:${MCU}")
-                        set(${RESULT} 0 PARENT_SCOPE)
-                        return()
-                    endif()
-                endforeach()
-            endforeach()
-
-            # Didn't find in skip file so build
-            set(${RESULT} 1 PARENT_SCOPE)
-
-        else()
-
-            # Didn't find skip or only file so build
-            set(${RESULT} 1 PARENT_SCOPE)
-
-        endif()
-
-    endfunction()
-
-    function(family_add_subdirectory DIR)
-        family_filter(SHOULD_ADD "${DIR}")
-        if (SHOULD_ADD)
-            add_subdirectory(${DIR})
-        endif()
-    endfunction()
-
-    function(family_get_project_name OUTPUT_NAME DIR)
-        get_filename_component(SHORT_NAME ${DIR} NAME)
-        set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
-    endfunction()
-
-    function(family_initialize_project PROJECT DIR)
-        family_filter(ALLOWED "${DIR}")
-        if (NOT ALLOWED)
-            get_filename_component(SHORT_NAME ${DIR} NAME)
-            message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
-        endif()
-    endfunction()
-
-    function(family_add_default_example_warnings TARGET)
-        target_compile_options(${TARGET} PUBLIC
-                -Wall
-                -Wextra
-                -Werror
-                -Wfatal-errors
-                -Wdouble-promotion
-                -Wfloat-equal
-                -Wshadow
-                -Wwrite-strings
-                -Wsign-compare
-                -Wmissing-format-attribute
-                -Wunreachable-code
-                -Wcast-align
-                -Wcast-qual
-                -Wnull-dereference
-                -Wuninitialized
-                -Wunused
-                -Wredundant-decls
-                #-Wstrict-prototypes
-                #-Werror-implicit-function-declaration
-                #-Wundef
-                )
-
-        if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-            # GCC 10
-            if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
-                target_compile_options(${TARGET} PUBLIC -Wconversion)
-            endif()
-
-            # GCC 8
-            if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
-                target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
-            endif()
-
-            # GCC 6
-            if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0)
-                target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing)
-            endif()
-        endif()
-    endfunction()
-
-    # configure an executable target to link to tinyusb in device mode, and add the board implementation
-    function(family_configure_device_example TARGET)
-        # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
-    endfunction()
-
-    # configure an executable target to link to tinyusb in host mode, and add the board implementation
-    function(family_configure_host_example TARGET)
-        # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
-    endfunction()
-
-    include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
-
-    if (NOT FAMILY_MCUS)
-        set(FAMILY_MCUS ${FAMILY})
+    # GCC 10
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
+      target_compile_options(${TARGET} PUBLIC -Wconversion)
     endif()
 
-    # save it in case of re-inclusion
-    set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
-endif()
\ No newline at end of file
+    # GCC 8
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
+      target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
+    endif()
+
+    # GCC 6
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0)
+      target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing)
+    endif()
+  endif()
+endfunction()
+
+#----------------------------------
+# Flashing target
+#----------------------------------
+
+# Add flash jlink target
+function(family_flash_jlink TARGET)
+  if (NOT DEFINED JLINKEXE)
+    set(JLINKEXE JLinkExe)
+  endif ()
+
+  if (NOT DEFINED JLINK_IF)
+    set(JLINK_IF swd)
+  endif ()
+
+  if (NOT DEFINED JLINK_OPTION)
+    set(JLINK_OPTION "")
+  endif ()
+  separate_arguments(OPTION_LIST UNIX_COMMAND ${JLINK_OPTION})
+
+  if (RTOS STREQUAL zephyr)
+    set(BINARY_TARGET zephyr_final)
+    set(NAME_TARGET ${CMAKE_PROJECT_NAME})
+  else ()
+    set(BINARY_TARGET ${TARGET})
+    set(NAME_TARGET ${TARGET})
+  endif ()
+
+  file(GENERATE
+    OUTPUT $<TARGET_FILE_DIR:${BINARY_TARGET}>/${BINARY_TARGET}.jlink
+    CONTENT "halt
+loadfile $<TARGET_FILE:${BINARY_TARGET}>
+r
+go
+exit"
+    )
+
+  add_custom_target(${NAME_TARGET}-jlink
+    DEPENDS ${BINARY_TARGET}
+    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${BINARY_TARGET}>/${BINARY_TARGET}.jlink
+    VERBATIM
+    )
+endfunction()
+
+
+# Add flash stlink target
+function(family_flash_stlink TARGET)
+  if (NOT DEFINED STM32_PROGRAMMER_CLI)
+    set(STM32_PROGRAMMER_CLI STM32_Programmer_CLI)
+  endif ()
+
+  add_custom_target(${TARGET}-stlink
+    DEPENDS ${TARGET}
+    COMMAND ${STM32_PROGRAMMER_CLI} --connect port=swd --write $<TARGET_FILE:${TARGET}> --go
+    )
+endfunction()
+
+
+# Add flash st-flash target
+function(family_flash_stflash TARGET)
+  if (NOT DEFINED ST_FLASH)
+    set(ST_FLASH st-flash)
+  endif ()
+
+  add_custom_target(${TARGET}-stflash
+    DEPENDS ${TARGET}
+    COMMAND ${ST_FLASH} write $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin 0x8000000
+    )
+endfunction()
+
+
+# Add flash openocd target
+function(family_flash_openocd TARGET)
+  if (NOT DEFINED OPENOCD)
+    set(OPENOCD openocd)
+  endif ()
+
+  if (NOT DEFINED OPENOCD_OPTION2)
+    set(OPENOCD_OPTION2 "")
+  endif ()
+
+  separate_arguments(OPTION_LIST UNIX_COMMAND ${OPENOCD_OPTION})
+  separate_arguments(OPTION_LIST2 UNIX_COMMAND ${OPENOCD_OPTION2})
+
+  # note skip verify since it has issue with rp2040
+  add_custom_target(${TARGET}-openocd
+    DEPENDS ${TARGET}
+    COMMAND ${OPENOCD} -c "tcl_port disabled" -c "gdb_port disabled" ${OPTION_LIST} -c init -c halt -c "program $<TARGET_FILE:${TARGET}>" -c reset ${OPTION_LIST2} -c exit
+    VERBATIM
+    )
+endfunction()
+
+
+# Add flash openocd-wch target
+# compiled from https://github.com/hathach/riscv-openocd-wch or https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
+function(family_flash_openocd_wch TARGET)
+  if (NOT DEFINED OPENOCD)
+    set(OPENOCD $ENV{HOME}/app/riscv-openocd-wch/src/openocd)
+  endif ()
+
+  family_flash_openocd(${TARGET})
+endfunction()
+
+
+# Add flash openocd adi (Analog Devices) target
+# included with msdk or compiled from release branch of https://github.com/analogdevicesinc/openocd
+function(family_flash_openocd_adi TARGET)
+  if (DEFINED $ENV{MAXIM_PATH})
+    # use openocd from msdk
+    set(OPENOCD ENV{MAXIM_PATH}/Tools/OpenOCD/openocd)
+    set(OPENOCD_OPTION2 "-s ENV{MAXIM_PATH}/Tools/OpenOCD/scripts")
+  else()
+    # compiled from source
+    if (NOT DEFINED OPENOCD_ADI_PATH)
+      set(OPENOCD_ADI_PATH $ENV{HOME}/app/openocd_adi)
+    endif ()
+    set(OPENOCD ${OPENOCD_ADI_PATH}/src/openocd)
+    set(OPENOCD_OPTION2 "-s ${OPENOCD_ADI_PATH}/tcl")
+  endif ()
+
+  family_flash_openocd(${TARGET})
+endfunction()
+
+# Add flash with https://github.com/ch32-rs/wlink
+function(family_flash_wlink_rs TARGET)
+  if (NOT DEFINED WLINK_RS)
+    set(WLINK_RS wlink)
+  endif ()
+
+  add_custom_target(${TARGET}-wlink-rs
+    DEPENDS ${TARGET}
+    COMMAND ${WLINK_RS} flash $<TARGET_FILE:${TARGET}>
+    )
+endfunction()
+
+
+# Add flash pycod target
+function(family_flash_pyocd TARGET)
+  if (NOT DEFINED PYOC)
+    set(PYOCD pyocd)
+  endif ()
+
+  add_custom_target(${TARGET}-pyocd
+    DEPENDS ${TARGET}
+    COMMAND ${PYOCD} flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
+    )
+endfunction()
+
+
+# Flash with UF2
+function(family_flash_uf2 TARGET FAMILY_ID)
+  add_custom_target(${TARGET}-uf2
+    DEPENDS ${TARGET}
+    COMMAND python ${UF2CONV_PY} -f ${FAMILY_ID} --deploy $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.uf2
+    )
+endfunction()
+
+
+# Add flash teensy_cli target
+function(family_flash_teensy TARGET)
+  if (NOT DEFINED TEENSY_CLI)
+    set(TEENSY_CLI teensy_loader_cli)
+  endif ()
+
+  add_custom_target(${TARGET}-teensy
+    DEPENDS ${TARGET}
+    COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
+    COMMAND ${TEENSY_CLI} --mcu=${TEENSY_MCU} -w -s $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
+    )
+endfunction()
+
+
+# Add flash using NXP's LinkServer (redserver)
+# https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
+function(family_flash_nxplink TARGET)
+  if (NOT DEFINED LINKSERVER)
+    set(LINKSERVER LinkServer)
+  endif ()
+
+  # LinkServer has a bug that can only execute with full path otherwise it throws:
+  # realpath error: No such file or directory
+  execute_process(COMMAND which ${LINKSERVER} OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
+
+  add_custom_target(${TARGET}-nxplink
+    DEPENDS ${TARGET}
+    COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
+    )
+endfunction()
+
+
+function(family_flash_dfu_util TARGET OPTION)
+  if (NOT DEFINED DFU_UTIL)
+    set(DFU_UTIL dfu-util)
+  endif ()
+
+  add_custom_target(${TARGET}-dfu-util
+    DEPENDS ${TARGET}
+    COMMAND ${DFU_UTIL} -R -d ${DFU_UTIL_VID_PID} -a 0 -D $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
+    VERBATIM
+    )
+endfunction()
+
+function(family_flash_msp430flasher TARGET)
+  if (NOT DEFINED MSP430Flasher)
+    set(MSP430FLASHER MSP430Flasher)
+  endif ()
+
+  # set LD_LIBRARY_PATH to find libmsp430.so (directory containing MSP430Flasher)
+  find_program(MSP430FLASHER_PATH MSP430Flasher)
+  get_filename_component(MSP430FLASHER_PARENT_DIR "${MSP430FLASHER_PATH}" DIRECTORY)
+  add_custom_target(${TARGET}-msp430flasher
+    DEPENDS ${TARGET}
+    COMMAND ${CMAKE_COMMAND} -E env LD_LIBRARY_PATH=${MSP430FLASHER_PARENT_DIR}
+            ${MSP430FLASHER} -w $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex -z [VCC]
+    )
+endfunction()
+
+function(family_flash_uniflash TARGET)
+  if (NOT DEFINED DSLITE)
+    set(DSLITE dslite.sh)
+  endif ()
+
+  separate_arguments(OPTION_LIST UNIX_COMMAND ${UNIFLASH_OPTION})
+
+  add_custom_target(${TARGET}-uniflash
+    DEPENDS ${TARGET}
+    COMMAND ${DSLITE} ${UNIFLASH_OPTION} -f $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
+    VERBATIM
+    )
+endfunction()
+
+#----------------------------------
+# Family specific
+#----------------------------------
+
+# family specific: can override above functions
+include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
+
+if (NOT FAMILY_MCUS)
+  set(FAMILY_MCUS ${FAMILY})
+endif()
+
+# if use max3421 as host controller, expand FAMILY_MCUS to include max3421
+if (MAX3421_HOST STREQUAL "1")
+  set(FAMILY_MCUS ${FAMILY_MCUS} MAX3421)
+endif ()
+
+# save it in case of re-inclusion
+set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
diff --git a/hw/bsp/fomu/boards/fomu/board.cmake b/hw/bsp/fomu/boards/fomu/board.cmake
new file mode 100644
index 000000000..9f5682042
--- /dev/null
+++ b/hw/bsp/fomu/boards/fomu/board.cmake
@@ -0,0 +1,4 @@
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC
+#    )
+endfunction()
diff --git a/hw/bsp/fomu/boards/fomu/board.h b/hw/bsp/fomu/boards/fomu/board.h
index 666ba1d98..2651c823d 100644
--- a/hw/bsp/fomu/boards/fomu/board.h
+++ b/hw/bsp/fomu/boards/fomu/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: fomu
+   url: https://tomu.im/fomu.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/fomu/boards/fomu/board.mk b/hw/bsp/fomu/boards/fomu/board.mk
index 8ced11412..b5545c89a 100644
--- a/hw/bsp/fomu/boards/fomu/board.mk
+++ b/hw/bsp/fomu/boards/fomu/board.mk
@@ -1 +1 @@
-# place holder
\ No newline at end of file
+# place holder
diff --git a/hw/bsp/fomu/dfu.py b/hw/bsp/fomu/dfu.py
old mode 100644
new mode 100755
index 32479350c..8383852e3
--- a/hw/bsp/fomu/dfu.py
+++ b/hw/bsp/fomu/dfu.py
@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/env python3
 
 # Written by Antonio Galea - 2010/11/18
 # Updated for DFU 1.1 by Sean Cross - 2020/03/31
diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/family.c
similarity index 97%
rename from hw/bsp/fomu/fomu.c
rename to hw/bsp/fomu/family.c
index 33c630303..61943cb01 100644
--- a/hw/bsp/fomu/fomu.c
+++ b/hw/bsp/fomu/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,12 +24,17 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Tomu
+*/
+
 #include <stdint.h>
 #include <stdbool.h>
-#include "../board.h"
 #include "csr.h"
 #include "irq.h"
 
+#include "bsp/board_api.h"
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/fomu/family.cmake b/hw/bsp/fomu/family.cmake
new file mode 100644
index 000000000..639373695
--- /dev/null
+++ b/hw/bsp/fomu/family.cmake
@@ -0,0 +1,90 @@
+include_guard()
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU rv32i-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS VALENTYUSB_EPTRI CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/fomu.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/crt0-vexriscv.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_VALENTYUSB_EPTRI)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/valentyusb/eptri/dcd_eptri.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+endfunction()
diff --git a/hw/bsp/fomu/family.mk b/hw/bsp/fomu/family.mk
index 165535c6b..69a546964 100644
--- a/hw/bsp/fomu/family.mk
+++ b/hw/bsp/fomu/family.mk
@@ -1,12 +1,15 @@
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE = riscv-none-elf-
+
+CPU_CORE ?= rv32i-ilp32
+
 CFLAGS += \
   -flto \
-  -march=rv32i \
-  -mabi=ilp32 \
-  -nostdlib \
   -DCFG_TUSB_MCU=OPT_MCU_VALENTYUSB_EPTRI
 
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE = riscv-none-embed-
+LDFLAGS_GCC += \
+  -nostdlib \
+  --specs=nosys.specs --specs=nano.specs \
 
 # All source paths should be relative to the top level.
 LD_FILE = $(FAMILY_PATH)/fomu.ld
@@ -19,12 +22,12 @@ INC += \
 	$(TOP)/$(FAMILY_PATH)/include
 
 # For freeRTOS port source
-FREERTOS_PORT = RISC-V
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
 
 # flash using dfu-util
 $(BUILD)/$(PROJECT).dfu: $(BUILD)/$(PROJECT).bin
 	@echo "Create $@"
 	python $(TOP)/hw/bsp/$(BOARD)/dfu.py -b $^ -D 0x1209:0x5bf0 $@
-	
+
 flash: $(BUILD)/$(PROJECT).dfu
 	dfu-util -D $^
diff --git a/hw/bsp/fomu/fomu.ld b/hw/bsp/fomu/fomu.ld
index 13278d2ad..0b0cf2612 100644
--- a/hw/bsp/fomu/fomu.ld
+++ b/hw/bsp/fomu/fomu.ld
@@ -11,7 +11,7 @@ MEMORY {
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/fomu/include/hw/common.h b/hw/bsp/fomu/include/hw/common.h
index 6a97ca2e9..b902bc4f2 100644
--- a/hw/bsp/fomu/include/hw/common.h
+++ b/hw/bsp/fomu/include/hw/common.h
@@ -30,4 +30,4 @@ static inline uint32_t csr_readl(uint32_t addr)
 {
 	return *(volatile uint32_t *)addr;
 }
-#endif /* _HW_COMMON_H_ */
\ No newline at end of file
+#endif /* _HW_COMMON_H_ */
diff --git a/hw/bsp/fomu/include/irq.h b/hw/bsp/fomu/include/irq.h
index a82218907..dc96c228d 100644
--- a/hw/bsp/fomu/include/irq.h
+++ b/hw/bsp/fomu/include/irq.h
@@ -68,4 +68,4 @@ static inline unsigned int irq_pending(void)
 }
 #endif
 
-#endif /* __IRQ_H */
\ No newline at end of file
+#endif /* __IRQ_H */
diff --git a/hw/bsp/frdm_k32l2b/board.mk b/hw/bsp/frdm_k32l2b/board.mk
deleted file mode 100644
index a737eb360..000000000
--- a/hw/bsp/frdm_k32l2b/board.mk
+++ /dev/null
@@ -1,51 +0,0 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_K32L2B31VLH0A \
-  -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
-
-MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
-
-# All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
-
-SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	$(MCU_DIR)/system_K32L2B31A.c \
-	$(MCU_DIR)/project_template/clock_config.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
-	$(TOP)/$(SDK_DIR)/drivers/smc \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/gpio \
-	$(TOP)/$(SDK_DIR)/drivers/port \
-	$(TOP)/$(SDK_DIR)/drivers/lpuart \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(MCU_DIR)/project_template \
-
-SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = K32L2B
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
deleted file mode 100644
index 6a72d516b..000000000
--- a/hw/bsp/frdm_kl25z/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-SDK_DIR = hw/mcu/nxp/nxp_sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_MKL25Z128VLK4 \
-  -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \
-  -DCFG_EXAMPLE_VIDEO_READONLY
-
-LDFLAGS += \
-  -Wl,--defsym,__stack_size__=0x400 \
-  -Wl,--defsym,__heap_size__=0
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls
-
-MCU_DIR = $(SDK_DIR)/devices/MKL25Z4
-
-# All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld
-
-SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	src/portable/nxp/khci/hcd_khci.c \
-	$(MCU_DIR)/system_MKL25Z4.c \
-	$(MCU_DIR)/project_template/clock_config.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_gpio.c \
-	$(MCU_DIR)/drivers/fsl_lpsci.c
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(MCU_DIR)/project_template \
-
-SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = mkl25zl128
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.cmake b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.cmake
new file mode 100644
index 000000000..403ac08cf
--- /dev/null
+++ b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.cmake
@@ -0,0 +1,13 @@
+set(JLINK_DEVICE gd32vf103cbt6)
+
+set(SDK_BSP_DIR ${SOC_DIR}/Board/gd32vf103c_longan_nano)
+set(LD_FILE_GNU ${SDK_BSP_DIR}/Source/GCC/gcc_gd32vf103xb_flashxip.ld)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${SDK_BSP_DIR}/Source/gd32vf103c_longan_nano.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    ${SDK_BSP_DIR}/Include
+    )
+endfunction()
diff --git a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h
index fae7c40b7..cb564a340 100644
--- a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h
+++ b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h
@@ -1,3 +1,8 @@
+/* metadata:
+   name: Sipeed Longan Nano
+   url: https://longan.sipeed.com/en/
+*/
+
 #ifndef _NUCLEI_SDK_HAL_H
 #define _NUCLEI_SDK_HAL_H
 
diff --git a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
index 3b8944452..fc49b7317 100644
--- a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
+++ b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
@@ -10,4 +10,3 @@ INC += $(TOP)/$(LONGAN_NANO_SDK_BSP)/Include
 
 # Longan Nano 128k ROM 32k RAM
 JLINK_DEVICE = gd32vf103cbt6
-#JLINK_DEVICE = gd32vf103c8t6 # Longan Nano Lite 64k ROM 20k RAM
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index c20732302..9d15755fc 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -24,11 +24,15 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "board.h"
+/* metadata:
+   manufacturer: GigaDevice
+*/
+
 #include "drv_usb_hw.h"
 #include "drv_usb_dev.h"
 
-#include "../board.h"
+#include "bsp/board_api.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -44,7 +48,7 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
 
 // According to GD32VF103 user manual clock tree:
 // Systick clock = AHB clock / 4.
-#define TIMER_TICKS         ((SystemCoreClock / 4) / 1000) 
+#define TIMER_TICKS         ((SystemCoreClock / 4) / 1000)
 
 #define BUTTON_PORT         GPIOA
 #define BUTTON_PIN          GPIO_PIN_0
@@ -112,7 +116,7 @@ void board_init(void) {
   otg_core_regs->GCCFG &= ~GCCFG_VBUSIG;
 #endif
 
-  /* Enable interrupts globaly */
+  /* Enable interrupts globally */
   __enable_irq();
 }
 
@@ -120,7 +124,7 @@ void gd32vf103_reset(void) {
   /* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
    * register to generate a software reset request.
    * BUT instead two undocumented registers in the debug peripheral
-   * that allow issueing a software reset.
+   * that allow issuing a software reset.
    * https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h
    */
   DBG_KEY = DBG_KEY_UNLOCK;
diff --git a/hw/bsp/gd32vf103/family.cmake b/hw/bsp/gd32vf103/family.cmake
new file mode 100644
index 000000000..a47871b38
--- /dev/null
+++ b/hw/bsp/gd32vf103/family.cmake
@@ -0,0 +1,121 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/gd/nuclei-sdk)
+set(SOC_DIR ${SDK_DIR}/SoC/gd32vf103)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS GD32VF103 CACHE INTERNAL "")
+
+set(JLINK_IF jtag)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    message(FATAL_ERROR "LD_FILE_GNU is not defined")
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU
+      ${SOC_DIR}/Common/Source/GCC/startup_gd32vf103.S
+      ${SOC_DIR}/Common/Source/GCC/intexc_gd32vf103.S
+      )
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_gd32vf103.c
+    ${SOC_DIR}/Common/Source/Drivers/gd32vf103_rcu.c
+    ${SOC_DIR}/Common/Source/Drivers/gd32vf103_gpio.c
+    ${SOC_DIR}/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c
+    ${SOC_DIR}/Common/Source/Drivers/gd32vf103_usart.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/NMSIS/Core/Include
+    ${SOC_DIR}/Common/Include
+    ${SOC_DIR}/Common/Include/Usb
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    DOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -mcmodel=medlow
+      -mstrict-align
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    ${SOC_DIR}/Common/Source/Stubs/sbrk.c
+    ${SOC_DIR}/Common/Source/Stubs/close.c
+    ${SOC_DIR}/Common/Source/Stubs/isatty.c
+    ${SOC_DIR}/Common/Source/Stubs/fstat.c
+    ${SOC_DIR}/Common/Source/Stubs/lseek.c
+    ${SOC_DIR}/Common/Source/Stubs/read.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_GD32VF103)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index 49bacdf1b..75b3efb33 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -4,12 +4,11 @@
 # Toolchain from https://nucleisys.com/download.php
 #CROSS_COMPILE ?= riscv-nuclei-elf-
 
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE ?= riscv-none-embed-
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
 
 # Submodules
 NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
-DEPS_SUBMODULES += $(NUCLEI_SDK)
 
 # Nuclei-SDK paths
 GD32VF103_SDK_SOC = $(NUCLEI_SDK)/SoC/gd32vf103
@@ -18,12 +17,9 @@ LIBC_STUBS = $(GD32VF103_SDK_SOC)/Common/Source/Stubs
 STARTUP_ASM = $(GD32VF103_SDK_SOC)/Common/Source/GCC
 
 include $(TOP)/$(BOARD_PATH)/board.mk
-
-SKIP_NANOLIB = 1
+CPU_CORE ?= rv32imac-ilp32
 
 CFLAGS += \
-	-march=rv32imac \
-	-mabi=ilp32 \
 	-mcmodel=medlow \
 	-mstrict-align \
 	-nostdlib -nostartfiles \
@@ -35,16 +31,18 @@ CFLAGS += -Wno-error=unused-parameter
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
-	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
-	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
+	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \
+	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
 	$(LIBC_STUBS)/sbrk.c \
 	$(LIBC_STUBS)/close.c \
 	$(LIBC_STUBS)/isatty.c \
 	$(LIBC_STUBS)/fstat.c \
 	$(LIBC_STUBS)/lseek.c \
-	$(LIBC_STUBS)/read.c 
+	$(LIBC_STUBS)/read.c
 
 SRC_S += \
 	$(STARTUP_ASM)/startup_gd32vf103.S \
@@ -57,7 +55,7 @@ INC += \
 	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb
 
 # For freeRTOS port source
-FREERTOS_PORT = RISC-V
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
 
 # For flash-jlink target
 JLINK_IF = jtag
diff --git a/hw/bsp/gd32vf103/system_gd32vf103.c b/hw/bsp/gd32vf103/system_gd32vf103.c
index 29518a54a..200852abf 100644
--- a/hw/bsp/gd32vf103/system_gd32vf103.c
+++ b/hw/bsp/gd32vf103/system_gd32vf103.c
@@ -95,7 +95,7 @@ void SystemInit(void)
     /* reset the RCC clock configuration to the default reset state */
     /* enable IRC8M */
     RCU_CTL |= RCU_CTL_IRC8MEN;
-    
+
     /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */
     RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
                   RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL);
@@ -107,7 +107,7 @@ void SystemInit(void)
     RCU_CTL &= ~(RCU_CTL_HXTALBPS);
 
     /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */
-    
+
     RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
                   RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4);
     RCU_CFG1 = 0x00000000U;
@@ -141,12 +141,12 @@ void SystemCoreClockUpdate(void)
         case SEL_IRC8M:
             SystemCoreClock = IRC8M_VALUE;
             break;
-            
+
         /* HXTAL is selected as CK_SYS */
         case SEL_HXTAL:
             SystemCoreClock = HXTAL_VALUE;
             break;
-            
+
         /* PLL is selected as CK_SYS */
         case SEL_PLL:
             /* PLL clock source selection, HXTAL or IRC8M/2 */
@@ -313,7 +313,7 @@ static void system_clock_72m_hxtal(void)
     /* APB1 = AHB/2 */
     RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
 
-    /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ 
+    /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
     RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
     RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18);
 
@@ -574,7 +574,7 @@ void ECLIC_Init(void)
  * \param [in]  IRQn        NMI interrupt handler address
  * \param [in]  shv         \ref ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and \ref ECLIC_VECTOR_INTERRUPT is vector mode
  * \param [in]  trig_mode   see \ref ECLIC_TRIGGER_Type
- * \param [in]  lvl         interupt level
+ * \param [in]  lvl         interrupt level
  * \param [in]  priority    interrupt priority
  * \param [in]  handler     interrupt handler, if NULL, handler will not be installed
  * \return       -1 means invalid input parameter. 0 means successful.
diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..7152fda01
--- /dev/null
+++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake
new file mode 100644
index 000000000..99681ab12
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1011)
+
+set(JLINK_DEVICE MIMXRT1011xxx5A)
+set(PYOCD_TARGET mimxrt1010)
+set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1011DAE5A
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.h b/hw/bsp/imxrt/boards/metro_m7_1011/board.h
new file mode 100644
index 000000000..ccc4d6b9a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Adafruit Metro M7 1011
+   url: https://www.adafruit.com/product/5600
+*/
+
+#ifndef BOARD_M7_1011_H_
+#define BOARD_M7_1011_H_
+
+// required since iMXRT MCUX-SDK include this file for board size
+#define BOARD_FLASH_SIZE     (8*1024*1024)
+
+// LED: IOMUXC_GPIO_03_GPIOMUX_IO03
+#define LED_PORT            BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN             BOARD_INITPINS_USER_LED_CHANNEL
+#define LED_STATE_ON        1
+
+// D8 as button: GPIO8
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_PERIPHERAL
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_CHANNEL
+#define BUTTON_STATE_ACTIVE   0
+
+// UART: IOMUXC_GPIO_09_LPUART1_RXD, IOMUXC_GPIO_10_LPUART1_TXD
+#define UART_PORT             LPUART1
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
+
+#endif
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk
new file mode 100644
index 000000000..b845194c2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk
@@ -0,0 +1,17 @@
+CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
+MCU_VARIANT = MIMXRT1011
+
+# LD file with uf2
+LD_FILE = $(BOARD_PATH)/$(BOARD).ld
+
+# For flash-jlink target
+JLINK_DEVICE = MIMXRT1011xxx5A
+
+# For flash-pyocd target
+PYOCD_TARGET = mimxrt1010
+
+# flash using pyocd
+flash: flash-uf2
+flash-uf2: $(BUILD)/$(PROJECT).uf2
+	@echo copying $<
+	@$(CP) $< /media/$(USER)/METROM7BOOT
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c
new file mode 100644
index 000000000..d5c93222c
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c
@@ -0,0 +1,340 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v12.0
+processor: MIMXRT1011xxxxx
+package_id: MIMXRT1011DAE5A
+mcu_data: ksdk2_0
+processor_version: 14.0.0
+board: MIMXRT1010-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY_CLK.outFreq, value: 480 MHz}
+settings:
+- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5'}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
+- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+    CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
+#endif
+    /* Disable ADC_ACLK_EN clock gate. */
+    CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
+    /* Set ADC_ACLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
+    /* Set Pll3 SW clock source to use the USB1 PLL output. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Set safe value of the AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
+    /* Set periph clock2 clock source to use the PLL3_SW_CLK. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h
new file mode 100644
index 000000000..cc627cf6a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h
@@ -0,0 +1,97 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK                40000000UL     /* Clock consumers of ADC_ALT_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL        /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL            /* Clock consumers of CLKO1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL            /* Clock consumers of CLKO2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL      /* Clock consumers of CLK_1M output : EWM, RTWDOG */
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL     /* Clock consumers of CLK_24M output : GPT1, GPT2 */
+#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT              500000000UL    /* Clock consumers of CORE_CLK_ROOT output : ARM, FLEXSPI */
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL    /* Clock consumers of ENET_500M_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL     /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           132000000UL    /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL     /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL     /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL    /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AIPSTZ1, AIPSTZ2, AOI, ARM, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, OCOTP, PWM1, RTWDOG, SAI1, SAI3, SNVS, SPDIF, SRC, TEMPMON, TRNG, USB, WDOG1, WDOG2, XBARA */
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL     /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL    /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL     /* Clock consumers of MQS_MCLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL     /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL     /* Clock consumers of SAI1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL     /* Clock consumers of SAI1_MCLK1 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL     /* Clock consumers of SAI1_MCLK2 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL     /* Clock consumers of SAI1_MCLK3 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL     /* Clock consumers of SAI3_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL     /* Clock consumers of SAI3_MCLK1 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL            /* Clock consumers of SAI3_MCLK2 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL     /* Clock consumers of SAI3_MCLK3 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL     /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL            /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL    /* Clock consumers of TRACE_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL     /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */
+#define BOARD_BOOTCLOCKRUN_USBPHY_CLK                 480000000UL    /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.c b/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.c
new file mode 100644
index 000000000..2d869b56e
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.c
@@ -0,0 +1,91 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v14.0
+processor: MIMXRT1011xxxxx
+package_id: MIMXRT1011DAE5A
+mcu_data: ksdk2_0
+processor_version: 14.0.0
+board: MIMXRT1010-EVK
+external_user_signals: {}
+pin_labels:
+- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: GPIO_11}
+- {pin_num: '10', pin_signal: GPIO_03, label: 'SAI1_RXD0/U10[16]', identifier: LED;USER_LED}
+- {pin_num: '4', pin_signal: GPIO_08, label: 'SAI1_MCLK/U10[11]', identifier: USER_BUTTON}
+power_domains: {NVCC_GPIO: '3.3'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09}
+  - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10}
+  - {pin_num: '10', peripheral: GPIO1, signal: 'gpiomux_io, 03', pin_signal: GPIO_03, identifier: USER_LED, direction: OUTPUT}
+  - {pin_num: '4', peripheral: GPIO1, signal: 'gpiomux_io, 08', pin_signal: GPIO_08, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_100K_Ohm}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  /* GPIO configuration of USER_LED on GPIO_03 (pin 10) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_03 (pin 10) */
+  GPIO_PinInit(GPIO1, 3U, &USER_LED_config);
+
+  /* GPIO configuration of USER_BUTTON on GPIO_08 (pin 4) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_08 (pin 4) */
+  GPIO_PinInit(GPIO1, 8U, &USER_BUTTON_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_03_GPIOMUX_IO03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_08_GPIOMUX_IO08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U);
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_08_GPIOMUX_IO08, 0xB0A0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.h b/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.h
new file mode 100644
index 000000000..5a6603cbe
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/pin_mux.h
@@ -0,0 +1,81 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x08U /*!< Select GPIO1 or GPIO2: affected bits mask */
+
+/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_RXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_RXD_SIGNAL                                      RXD   /*!< Signal name */
+
+/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_TXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_TXD_SIGNAL                                      TXD   /*!< Signal name */
+
+/* GPIO_03 (number 10), SAI1_RXD0/U10[16] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO1   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                gpiomux_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                       3U   /*!< Signal channel */
+
+/* GPIO_08 (number 4), SAI1_MCLK/U10[11] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO1   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                             gpiomux_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    8U   /*!< Signal channel */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.c b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.c
new file mode 100644
index 000000000..752a65629
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkmimxrt1010_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf")))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig =
+        {
+            .tag              = FLEXSPI_CFG_BLK_TAG,
+            .version          = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+            .csHoldTime       = 3u,
+            .csSetupTime      = 3u,
+            .sflashPadType    = kSerialFlash_4Pads,
+            .serialClkFreq    = kFlexSpiSerialClk_100MHz,
+            .sflashA1Size     = 16u * 1024u * 1024u,
+            .lookupTable =
+                {
+                    // Read LUTs
+                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 24),
+                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+                },
+        },
+    .pageSize           = 256u,
+    .sectorSize         = 4u * 1024u,
+    .blockSize          = 64u * 1024u,
+    .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.h b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.h
new file mode 100644
index 000000000..bb5a64448
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* FLEXSPI memory config block related definitions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related definitions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_75MHz  = 4,
+    kFlexSpiSerialClk_80MHz  = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_120MHz = 7,
+    kFlexSpiSerialClk_133MHz = 8,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad  = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
+#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld
new file mode 100644
index 000000000..960fc6891
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld
@@ -0,0 +1,270 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1011CAE4A
+**                          MIMXRT1011DAE5A
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    IMXRT1010RM Rev.0, 09/2019
+**     Version:             rev. 1.0, 2019-08-01
+**     Build:               b210709
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2021 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_flash_config        (RX)  : ORIGIN = 0x60000400, LENGTH = 0x00000C00
+  m_ivt                 (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
+
+  m_interrupts          (RX)  : ORIGIN = 0x6000C000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400)
+  m_qacode              (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00008000
+  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00010000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  __NCACHE_REGION_START = ORIGIN(m_data2);
+  __NCACHE_REGION_SIZE  = 0;
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    __FLASH_BASE = .;
+    KEEP(* (.boot_hdr.conf))     /* flash config section */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
+
+  .ivt : AT(ivt_begin)
+  {
+    . = ALIGN(4);
+    KEEP(* (.boot_hdr.ivt))           /* ivt section */
+    KEEP(* (.boot_hdr.boot_data))     /* boot section */
+    KEEP(* (.boot_hdr.dcd_data))      /* dcd section */
+    . = ALIGN(4);
+  } > m_ivt
+
+  /* The startup code goes first into internal RAM */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    __Vectors = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  /* The program code and other data goes into internal RAM */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(m_usb_dma_init_data)
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    *(DataQuickAccess)       /* quick access data section */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
+
+  .ram_function : AT(__ram_function_flash_start)
+  {
+    . = ALIGN(32);
+    __ram_function_start__ = .;
+    *(CodeQuickAccess)
+    . = ALIGN(128);
+    __ram_function_end__ = .;
+  } > m_qacode
+
+  __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
+  .ncache.init : AT(__NDATA_ROM)
+  {
+    __noncachedata_start__ = .;   /* create a global symbol at ncache data start */
+    *(NonCacheable.init)
+    . = ALIGN(4);
+    __noncachedata_init_end__ = .;   /* create a global symbol at initialized ncache data end */
+  } > m_data
+  . = __noncachedata_init_end__;
+  .ncache :
+  {
+    *(NonCacheable)
+    . = ALIGN(4);
+    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
+  } > m_data
+
+  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(m_usb_dma_noninit_data)
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex
new file mode 100644
index 000000000..ef551731a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex
@@ -0,0 +1,400 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_14 http://mcuxpresso.nxp.com/XSD/mex_configuration_14.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="14" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_14" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1011xxxxx</processor>
+      <package>MIMXRT1011DAE5A</package>
+      <board>MIMXRT1010-EVK</board>
+      <board_revision>A</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="14.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>14.0.0</processor_version>
+            <pin_labels>
+               <pin_label pin_num="1" pin_signal="GPIO_11" label="GPIO_11" identifier="GPIO_11"/>
+               <pin_label pin_num="10" pin_signal="GPIO_03" label="SAI1_RXD0/U10[16]" identifier="LED;USER_LED"/>
+               <pin_label pin_num="4" pin_signal="GPIO_08" label="SAI1_MCLK/U10[11]" identifier="USER_BUTTON"/>
+            </pin_labels>
+            <external_user_signals>
+               <routingDetailsColumns/>
+               <properties/>
+            </external_user_signals>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="GPIO1" description="Peripheral GPIO1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/>
+                  <pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/>
+                  <pin peripheral="GPIO1" signal="gpiomux_io, 03" pin_num="10" pin_signal="GPIO_03">
+                     <pin_features>
+                        <pin_feature name="identifier" value="USER_LED"/>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpiomux_io, 08" pin_num="4" pin_signal="GPIO_08">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>14.0.0</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/>
+                  <setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
+                     </config_set>
+                     <config_set name="interrupt_vector"/>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                        <setting name="enable_irq_comb_16_31" value="false"/>
+                        <struct name="gpio_interrupt_comb_16_31">
+                           <setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="2a54e709-5718-4b89-8b7b-71cefb418658" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="27e43a4b-bddb-4db2-8f6b-3f6a73008a27" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="c946fe99-5d76-4cca-8be0-dea3c7861b68" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="c18a4299-93be-44e8-b563-3985b3e264c5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="6149366a-a07f-40a7-8909-00ba459085a7" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="15cc4d18-2002-44a4-b7e7-f681a046f26c" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake
new file mode 100644
index 000000000..99681ab12
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1011)
+
+set(JLINK_DEVICE MIMXRT1011xxx5A)
+set(PYOCD_TARGET mimxrt1010)
+set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1011DAE5A
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h
new file mode 100644
index 000000000..04d5b01b5
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Adafruit Metro M7 1011 SD
+   url: https://www.adafruit.com/product/5600
+*/
+
+#ifndef BOARD_METRO_M7_1011_SD_H_
+#define BOARD_METRO_M7_1011_SD_H_
+
+// required since iMXRT MCUX-SDK include this file for board size
+#define BOARD_FLASH_SIZE     (8*1024*1024)
+
+// LED: IOMUXC_GPIO_03_GPIOMUX_IO03
+#define LED_PORT            BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN             BOARD_INITPINS_USER_LED_CHANNEL
+#define LED_STATE_ON        1
+
+// D8 as button: GPIO8
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_PERIPHERAL
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_CHANNEL
+#define BUTTON_STATE_ACTIVE   0
+
+// UART: IOMUXC_GPIO_09_LPUART1_RXD, IOMUXC_GPIO_10_LPUART1_TXD
+#define UART_PORT             LPUART1
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
+
+#endif
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk
new file mode 100644
index 000000000..b845194c2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk
@@ -0,0 +1,17 @@
+CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
+MCU_VARIANT = MIMXRT1011
+
+# LD file with uf2
+LD_FILE = $(BOARD_PATH)/$(BOARD).ld
+
+# For flash-jlink target
+JLINK_DEVICE = MIMXRT1011xxx5A
+
+# For flash-pyocd target
+PYOCD_TARGET = mimxrt1010
+
+# flash using pyocd
+flash: flash-uf2
+flash-uf2: $(BUILD)/$(PROJECT).uf2
+	@echo copying $<
+	@$(CP) $< /media/$(USER)/METROM7BOOT
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c
new file mode 100644
index 000000000..1b28b668a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c
@@ -0,0 +1,340 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1011xxxxx
+package_id: MIMXRT1011DAE5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1010-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY_CLK.outFreq, value: 480 MHz}
+settings:
+- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5'}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
+- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+    CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
+#endif
+    /* Disable ADC_ACLK_EN clock gate. */
+    CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
+    /* Set ADC_ACLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
+    /* Set Pll3 SW clock source to use the USB1 PLL output. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Set safe value of the AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
+    /* Set periph clock2 clock source to use the PLL3_SW_CLK. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.h
new file mode 100644
index 000000000..119fd94bd
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.h
@@ -0,0 +1,97 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK                40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT              500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY_CLK                 480000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.c b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.c
new file mode 100644
index 000000000..aa38e02dc
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.c
@@ -0,0 +1,108 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1011xxxxx
+package_id: MIMXRT1011DAE5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1010-EVK
+external_user_signals: {}
+pin_labels:
+- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: GPIO_11}
+- {pin_num: '70', pin_signal: GPIO_SD_05}
+- {pin_num: '10', pin_signal: GPIO_03, label: 'SAI1_RXD0/U10[16]', identifier: LED;USER_LED}
+- {pin_num: '4', pin_signal: GPIO_08, label: 'SAI1_MCLK/U10[11]', identifier: USER_BUTTON}
+- {pin_num: '79', pin_signal: GPIO_13, label: 'USB_OTG1_ID/J9[4]/Q9[2]', identifier: TRACE1}
+power_domains: {NVCC_GPIO: '3.3'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09}
+  - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10}
+  - {pin_num: '10', peripheral: GPIO1, signal: 'gpiomux_io, 03', pin_signal: GPIO_03, identifier: USER_LED, direction: OUTPUT}
+  - {pin_num: '79', peripheral: ARM, signal: 'TRACE, 1', pin_signal: GPIO_13, speed: MHZ_200}
+  - {pin_num: '80', peripheral: ARM, signal: 'TRACE, 2', pin_signal: GPIO_12, speed: MHZ_200}
+  - {pin_num: '58', peripheral: ARM, signal: arm_trace_clk, pin_signal: GPIO_AD_02, speed: MHZ_200}
+  - {pin_num: '1', peripheral: ARM, signal: 'TRACE, 3', pin_signal: GPIO_11, speed: MHZ_200}
+  - {pin_num: '60', peripheral: ARM, signal: 'TRACE, 0', pin_signal: GPIO_AD_00, speed: MHZ_200}
+  - {pin_num: '4', peripheral: GPIO1, signal: 'gpiomux_io, 08', pin_signal: GPIO_08, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_100K_Ohm}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  /* GPIO configuration of USER_LED on GPIO_03 (pin 10) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_03 (pin 10) */
+  GPIO_PinInit(GPIO1, 3U, &USER_LED_config);
+
+  /* GPIO configuration of USER_BUTTON on GPIO_08 (pin 4) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_08 (pin 4) */
+  GPIO_PinInit(GPIO1, 8U, &USER_BUTTON_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_03_GPIOMUX_IO03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_08_GPIOMUX_IO08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U);
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_08_GPIOMUX_IO08, 0xB0A0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_11_ARM_TRACE3, 0x10E0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_12_ARM_TRACE2, 0x10E0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_13_ARM_TRACE1, 0x10E0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0x10E0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0x10E0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.h
new file mode 100644
index 000000000..42c256745
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.h
@@ -0,0 +1,110 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x08U /*!< Select GPIO1 or GPIO2: affected bits mask */
+
+/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_RXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_RXD_SIGNAL                                      RXD   /*!< Signal name */
+
+/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_TXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_TXD_SIGNAL                                      TXD   /*!< Signal name */
+
+/* GPIO_03 (number 10), SAI1_RXD0/U10[16] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO1   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                gpiomux_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                       3U   /*!< Signal channel */
+
+/* GPIO_13 (number 79), USB_OTG1_ID/J9[4]/Q9[2] */
+/* Routed pin properties */
+#define BOARD_INITPINS_TRACE1_PERIPHERAL                                     ARM   /*!< Peripheral name */
+#define BOARD_INITPINS_TRACE1_SIGNAL                                       TRACE   /*!< Signal name */
+#define BOARD_INITPINS_TRACE1_CHANNEL                                         1U   /*!< Signal channel */
+
+/* GPIO_12 (number 80), USB_OTG1_OC/U7[A2] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USB_OTG1_OC_PERIPHERAL                                ARM   /*!< Peripheral name */
+#define BOARD_INITPINS_USB_OTG1_OC_SIGNAL                                  TRACE   /*!< Signal name */
+#define BOARD_INITPINS_USB_OTG1_OC_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_AD_02 (number 58), ADC12_2/J26[12]/J56[16] */
+/* Routed pin properties */
+#define BOARD_INITPINS_ADC12_2_PERIPHERAL                                    ARM   /*!< Peripheral name */
+#define BOARD_INITPINS_ADC12_2_SIGNAL                              arm_trace_clk   /*!< Signal name */
+
+/* GPIO_11 (number 1), GPIO_11 */
+/* Routed pin properties */
+#define BOARD_INITPINS_GPIO_11_PERIPHERAL                                    ARM   /*!< Peripheral name */
+#define BOARD_INITPINS_GPIO_11_SIGNAL                                      TRACE   /*!< Signal name */
+#define BOARD_INITPINS_GPIO_11_CHANNEL                                        3U   /*!< Signal channel */
+
+/* GPIO_AD_00 (number 60), USB_OTG1_PWR */
+/* Routed pin properties */
+#define BOARD_INITPINS_USB_OTG1_PWR_PERIPHERAL                               ARM   /*!< Peripheral name */
+#define BOARD_INITPINS_USB_OTG1_PWR_SIGNAL                                 TRACE   /*!< Signal name */
+#define BOARD_INITPINS_USB_OTG1_PWR_CHANNEL                                   0U   /*!< Signal channel */
+
+/* GPIO_08 (number 4), SAI1_MCLK/U10[11] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO1   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                             gpiomux_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    8U   /*!< Signal channel */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c b/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c
new file mode 100644
index 000000000..752a65629
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkmimxrt1010_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf")))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig =
+        {
+            .tag              = FLEXSPI_CFG_BLK_TAG,
+            .version          = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+            .csHoldTime       = 3u,
+            .csSetupTime      = 3u,
+            .sflashPadType    = kSerialFlash_4Pads,
+            .serialClkFreq    = kFlexSpiSerialClk_100MHz,
+            .sflashA1Size     = 16u * 1024u * 1024u,
+            .lookupTable =
+                {
+                    // Read LUTs
+                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 24),
+                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+                },
+        },
+    .pageSize           = 256u,
+    .sectorSize         = 4u * 1024u,
+    .blockSize          = 64u * 1024u,
+    .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.h
new file mode 100644
index 000000000..bb5a64448
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* FLEXSPI memory config block related definitions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related definitions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_75MHz  = 4,
+    kFlexSpiSerialClk_80MHz  = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_120MHz = 7,
+    kFlexSpiSerialClk_133MHz = 8,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad  = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
+#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.ld b/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.ld
new file mode 100644
index 000000000..960fc6891
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.ld
@@ -0,0 +1,270 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1011CAE4A
+**                          MIMXRT1011DAE5A
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    IMXRT1010RM Rev.0, 09/2019
+**     Version:             rev. 1.0, 2019-08-01
+**     Build:               b210709
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2021 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_flash_config        (RX)  : ORIGIN = 0x60000400, LENGTH = 0x00000C00
+  m_ivt                 (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
+
+  m_interrupts          (RX)  : ORIGIN = 0x6000C000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400)
+  m_qacode              (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00008000
+  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00010000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  __NCACHE_REGION_START = ORIGIN(m_data2);
+  __NCACHE_REGION_SIZE  = 0;
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    __FLASH_BASE = .;
+    KEEP(* (.boot_hdr.conf))     /* flash config section */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
+
+  .ivt : AT(ivt_begin)
+  {
+    . = ALIGN(4);
+    KEEP(* (.boot_hdr.ivt))           /* ivt section */
+    KEEP(* (.boot_hdr.boot_data))     /* boot section */
+    KEEP(* (.boot_hdr.dcd_data))      /* dcd section */
+    . = ALIGN(4);
+  } > m_ivt
+
+  /* The startup code goes first into internal RAM */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    __Vectors = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  /* The program code and other data goes into internal RAM */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(m_usb_dma_init_data)
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    *(DataQuickAccess)       /* quick access data section */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
+
+  .ram_function : AT(__ram_function_flash_start)
+  {
+    . = ALIGN(32);
+    __ram_function_start__ = .;
+    *(CodeQuickAccess)
+    . = ALIGN(128);
+    __ram_function_end__ = .;
+  } > m_qacode
+
+  __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
+  .ncache.init : AT(__NDATA_ROM)
+  {
+    __noncachedata_start__ = .;   /* create a global symbol at ncache data start */
+    *(NonCacheable.init)
+    . = ALIGN(4);
+    __noncachedata_init_end__ = .;   /* create a global symbol at initialized ncache data end */
+  } > m_data
+  . = __noncachedata_init_end__;
+  .ncache :
+  {
+    *(NonCacheable)
+    . = ALIGN(4);
+    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
+  } > m_data
+
+  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(m_usb_dma_noninit_data)
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex b/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex
new file mode 100644
index 000000000..7aab59a68
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex
@@ -0,0 +1,431 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1011xxxxx</processor>
+      <package>MIMXRT1011DAE5A</package>
+      <board>MIMXRT1010-EVK</board>
+      <board_revision>A</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="1" pin_signal="GPIO_11" label="GPIO_11" identifier="GPIO_11"/>
+               <pin_label pin_num="70" pin_signal="GPIO_SD_05" label=""/>
+               <pin_label pin_num="10" pin_signal="GPIO_03" label="SAI1_RXD0/U10[16]" identifier="LED;USER_LED"/>
+               <pin_label pin_num="4" pin_signal="GPIO_08" label="SAI1_MCLK/U10[11]" identifier="USER_BUTTON"/>
+               <pin_label pin_num="79" pin_signal="GPIO_13" label="USB_OTG1_ID/J9[4]/Q9[2]" identifier="TRACE1"/>
+            </pin_labels>
+            <external_user_signals>
+               <properties/>
+            </external_user_signals>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="GPIO1" description="Peripheral GPIO1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/>
+                  <pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/>
+                  <pin peripheral="GPIO1" signal="gpiomux_io, 03" pin_num="10" pin_signal="GPIO_03">
+                     <pin_features>
+                        <pin_feature name="identifier" value="USER_LED"/>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ARM" signal="TRACE, 1" pin_num="79" pin_signal="GPIO_13">
+                     <pin_features>
+                        <pin_feature name="speed" value="MHZ_200"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ARM" signal="TRACE, 2" pin_num="80" pin_signal="GPIO_12">
+                     <pin_features>
+                        <pin_feature name="speed" value="MHZ_200"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ARM" signal="arm_trace_clk" pin_num="58" pin_signal="GPIO_AD_02">
+                     <pin_features>
+                        <pin_feature name="speed" value="MHZ_200"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ARM" signal="TRACE, 3" pin_num="1" pin_signal="GPIO_11">
+                     <pin_features>
+                        <pin_feature name="speed" value="MHZ_200"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ARM" signal="TRACE, 0" pin_num="60" pin_signal="GPIO_AD_00">
+                     <pin_features>
+                        <pin_feature name="speed" value="MHZ_200"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpiomux_io, 08" pin_num="4" pin_signal="GPIO_08">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/>
+                  <setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
+                     </config_set>
+                     <config_set name="interrupt_vector"/>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                        <setting name="enable_irq_comb_16_31" value="false"/>
+                        <struct name="gpio_interrupt_comb_16_31">
+                           <setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="2a54e709-5718-4b89-8b7b-71cefb418658" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="27e43a4b-bddb-4db2-8f6b-3f6a73008a27" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="c946fe99-5d76-4cca-8be0-dea3c7861b68" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="c18a4299-93be-44e8-b563-3985b3e264c5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="6149366a-a07f-40a7-8909-00ba459085a7" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="15cc4d18-2002-44a4-b7e7-f681a046f26c" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/ozone/metro_m7_1011_sd.jdebug b/hw/bsp/imxrt/boards/metro_m7_1011_sd/ozone/metro_m7_1011_sd.jdebug
new file mode 100644
index 000000000..90f9b77e5
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/ozone/metro_m7_1011_sd.jdebug
@@ -0,0 +1,215 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTraceTiming (50, 50, 50, 50);
+  Project.SetDevice ("MIMXRT1011xxx4A");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("20 MHz");
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd");
+  Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd");
+  Project.AddSvdFile ("./MIMXRT1011.svd");
+
+
+  // timing delay for trace pins in pico seconds, default is 2 nano seconds
+
+	File.Open ("../../../../../../examples/cmake-build-metro-m7-1011-sd/device/cdc_msc/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging a RAM program on a Cortex-M target device
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  Exec.Reset();
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//
+//    Util.Log("Resetting Program.");
+//
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+
+void BeforeTargetConnect (void) {
+  //
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+  //
+  //Project.SetJLinkScript("./ST_STM32H743_Traceconfig.pex");
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
new file mode 100644
index 000000000..99681ab12
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1011)
+
+set(JLINK_DEVICE MIMXRT1011xxx5A)
+set(PYOCD_TARGET mimxrt1010)
+set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1011DAE5A
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
index 4f21b52fa..6b9ec0ae1 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -24,30 +24,29 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: i.MX RT1010 Evaluation Kit
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1010-evaluation-kit:MIMXRT1010-EVK
+*/
 
-#ifndef BOARD_H_
-#define BOARD_H_
+#ifndef BOARD_MIMXRT1010_EVK_H_
+#define BOARD_MIMXRT1010_EVK_H_
 
-#include "fsl_device_registers.h"
-
-// required since iMX RT10xx SDK include this file for board size
+// required since iMXRT MCUX-SDK include this file for board size
 #define BOARD_FLASH_SIZE (0x1000000U)
 
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_11_GPIOMUX_IO11
-#define LED_PORT              GPIO1
-#define LED_PIN               11
+// LED: IOMUXC_GPIO_11_GPIOMUX_IO11
+#define LED_PORT              BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN               BOARD_INITPINS_USER_LED_CHANNEL
 #define LED_STATE_ON          0
 
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_GPIO_SD_05_GPIO2_IO05
-#define BUTTON_PORT           GPIO2
-#define BUTTON_PIN            5
+// SW8 button: IOMUXC_GPIO_SD_05_GPIO2_IO05
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_GPIO
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_GPIO_PIN
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
+// UART: IOMUXC_GPIO_09_LPUART1_RXD, IOMUXC_GPIO_10_LPUART1_TXD
 #define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_09_LPUART1_RXD
-#define UART_TX_PINMUX        IOMUXC_GPIO_10_LPUART1_TXD
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
 
-#endif /* BOARD_H_ */
+#endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
index 17dc01cd9..488a56fdc 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
@@ -2,7 +2,7 @@ CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
 MCU_VARIANT = MIMXRT1011
 
 # For flash-jlink target
-JLINK_DEVICE = MIMXRT1011DAE5A
+JLINK_DEVICE = MIMXRT1011xxx5A
 
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1010
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c
new file mode 100644
index 000000000..1b28b668a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c
@@ -0,0 +1,340 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1011xxxxx
+package_id: MIMXRT1011DAE5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1010-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY_CLK.outFreq, value: 480 MHz}
+settings:
+- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5'}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
+- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+    CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
+#endif
+    /* Disable ADC_ACLK_EN clock gate. */
+    CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
+    /* Set ADC_ACLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
+    /* Set Pll3 SW clock source to use the USB1 PLL output. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Set safe value of the AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
+    /* Set periph clock2 clock source to use the PLL3_SW_CLK. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h
new file mode 100644
index 000000000..119fd94bd
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h
@@ -0,0 +1,97 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK                40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT              500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY_CLK                 480000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/pin_mux.c
new file mode 100644
index 000000000..b960191d1
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/pin_mux.c
@@ -0,0 +1,89 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1011xxxxx
+package_id: MIMXRT1011DAE5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1010-EVK
+external_user_signals: {}
+pin_labels:
+- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: LED;USERLED;USER_LED}
+power_domains: {NVCC_GPIO: '3.3'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '70', peripheral: GPIO2, signal: 'gpio_io, 05', pin_signal: GPIO_SD_05, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm}
+  - {pin_num: '1', peripheral: GPIO1, signal: 'gpiomux_io, 11', pin_signal: GPIO_11, identifier: USER_LED, direction: OUTPUT}
+  - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09}
+  - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  /* GPIO configuration of USER_LED on GPIO_11 (pin 1) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_11 (pin 1) */
+  GPIO_PinInit(GPIO1, 11U, &USER_LED_config);
+
+  /* GPIO configuration of USER_BUTTON on GPIO_SD_05 (pin 70) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_SD_05 (pin 70) */
+  GPIO_PinInit(GPIO2, 5U, &USER_BUTTON_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0U);
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0x70A0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/pin_mux.h
new file mode 100644
index 000000000..0c980150a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/pin_mux.h
@@ -0,0 +1,89 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x0820U /*!< Select GPIO1 or GPIO2: affected bits mask */
+
+/* GPIO_SD_05 (number 70), USER_BUTTON */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO2   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    5U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                    GPIO2   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN                                   5U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK                      (1U << 5U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_BUTTON_PORT                                    GPIO2   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_PIN                                        5U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_BUTTON_PIN_MASK                           (1U << 5U)   /*!< PORT pin mask */
+
+/* GPIO_11 (number 1), GPIO_11 */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO1   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                gpiomux_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                      11U   /*!< Signal channel */
+
+/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_RXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_RXD_SIGNAL                                      RXD   /*!< Signal name */
+
+/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_TXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_TXD_SIGNAL                                      TXD   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h
index 4be2760be..bb5a64448 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -123,7 +123,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -184,7 +184,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -252,7 +252,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex b/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex
new file mode 100644
index 000000000..701f3e9c3
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex
@@ -0,0 +1,397 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1011xxxxx</processor>
+      <package>MIMXRT1011DAE5A</package>
+      <board>MIMXRT1010-EVK</board>
+      <board_revision>A</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="1" pin_signal="GPIO_11" label="GPIO_11" identifier="LED;USERLED;USER_LED"/>
+            </pin_labels>
+            <external_user_signals>
+               <properties/>
+            </external_user_signals>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_47K_Ohm"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpiomux_io, 11" pin_num="1" pin_signal="GPIO_11">
+                     <pin_features>
+                        <pin_feature name="identifier" value="USER_LED"/>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/>
+                  <pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/>
+                  <setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
+                     </config_set>
+                     <config_set name="interrupt_vector"/>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                        <setting name="enable_irq_comb_16_31" value="false"/>
+                        <struct name="gpio_interrupt_comb_16_31">
+                           <setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="2a54e709-5718-4b89-8b7b-71cefb418658" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="27e43a4b-bddb-4db2-8f6b-3f6a73008a27" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="c946fe99-5d76-4cca-8be0-dea3c7861b68" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="c18a4299-93be-44e8-b563-3985b3e264c5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="6149366a-a07f-40a7-8909-00ba459085a7" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="15cc4d18-2002-44a4-b7e7-f681a046f26c" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake
new file mode 100644
index 000000000..becad46d4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1015)
+
+set(JLINK_DEVICE MIMXRT1015DAF5A)
+set(PYOCD_TARGET mimxrt1015)
+set(NXPLINK_DEVICE MIMXRT1015xxxxx:EVK-MIMXRT1015)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1015_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1015DAF5A
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
index 932ce7fd7..e2ec4e627 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -24,28 +24,33 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: i.MX RT1015 Evaluation Kit
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1015-EVK
+*/
 
-#ifndef BOARD_H_
-#define BOARD_H_
+#ifndef BOARD_MIMXRT1015_EVK_H_
+#define BOARD_MIMXRT1015_EVK_H_
 
-// required since iMX RT10xx SDK include this file for board size
+// required since iMXRT MCUX-SDK include this file for board size
 #define BOARD_FLASH_SIZE (0x1000000U)
 
 // LED
 #define LED_PINMUX            IOMUXC_GPIO_SD_B1_01_GPIO3_IO21
-#define LED_PORT              GPIO3
-#define LED_PIN               21
+#define LED_PORT              BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN               BOARD_INITPINS_USER_LED_CHANNEL
 #define LED_STATE_ON          0
 
 // SW8 button
 #define BUTTON_PINMUX         IOMUXC_GPIO_EMC_09_GPIO2_IO09
-#define BUTTON_PORT           GPIO2
-#define BUTTON_PIN            9
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_GPIO
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_GPIO_PIN
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
 #define UART_PORT             LPUART1
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
 #define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_07_LPUART1_RX
 #define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_06_LPUART1_TX
 
-#endif /* BOARD_H_ */
+#endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
new file mode 100644
index 000000000..ae1aa7fb1
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
@@ -0,0 +1,357 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1015xxxxx
+package_id: MIMXRT1015DAF5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1015-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2160/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
+- {id: CCM.CLKO2_SEL.sel, value: CCM.LPI2C_CLK_ROOT}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
+- {id: CCM.SEMC_PODF.scale, value: '2'}
+- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 2);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(6);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
new file mode 100644
index 000000000..2acdb16a7
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
@@ -0,0 +1,100 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           196363636UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             117333333UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c
new file mode 100644
index 000000000..97224a332
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c
@@ -0,0 +1,118 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1015xxxxx
+package_id: MIMXRT1015DAF5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1015-EVK
+external_user_signals: {}
+pin_labels:
+- {pin_num: '21', pin_signal: GPIO_SD_B1_01, label: GPIO SD_B1_01, identifier: USER_LED}
+power_domains: {NVCC_GPIO: '3.3'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '1', peripheral: GPIO2, signal: 'gpio_io, 09', pin_signal: GPIO_EMC_09, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm}
+  - {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, pull_up_down_config: Pull_Down_100K_Ohm}
+  - {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
+  - {pin_num: '21', peripheral: GPIO3, signal: 'gpio_io, 21', pin_signal: GPIO_SD_B1_01, direction: OUTPUT}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  /* GPIO configuration of USER_BUTTON on GPIO_EMC_09 (pin 1) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_EMC_09 (pin 1) */
+  GPIO_PinInit(GPIO2, 9U, &USER_BUTTON_config);
+
+  /* GPIO configuration of USER_LED on GPIO_SD_B1_01 (pin 21) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_SD_B1_01 (pin 21) */
+  GPIO_PinInit(GPIO3, 21U, &USER_LED_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_GPIO3_IO21, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0x70B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitQSPIPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '12', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
+  - {pin_num: '11', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
+  - {pin_num: '9', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10}
+  - {pin_num: '10', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09}
+  - {pin_num: '13', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06}
+  - {pin_num: '8', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitQSPIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitQSPIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h
new file mode 100644
index 000000000..c9cbe3b72
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h
@@ -0,0 +1,133 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* GPIO_EMC_09 (number 1), USER_BUTTON */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO2   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    9U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                    GPIO2   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN                                   9U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK                      (1U << 9U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_BUTTON_PORT                                    GPIO2   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_PIN                                        9U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_BUTTON_PIN_MASK                           (1U << 9U)   /*!< PORT pin mask */
+
+/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_RXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_RXD_SIGNAL                                       RX   /*!< Signal name */
+
+/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_TXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_TXD_SIGNAL                                       TX   /*!< Signal name */
+
+/* GPIO_SD_B1_01 (number 21), GPIO SD_B1_01 */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO3   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                   gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                      21U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_GPIO                                       GPIO3   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN                                     21U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                        (1U << 21U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_LED_PORT                                       GPIO3   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_PIN                                          21U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_LED_PIN_MASK                             (1U << 21U)   /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+/* GPIO_SD_B1_07 (number 12), FlexSPI_CLK_A/U13[6] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL                     FLEXSPI_A_SCLK   /*!< Signal name */
+
+/* GPIO_SD_B1_08 (number 11), FlexSPI_D0_A/U13[5] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL                   FLEXSPI_A_DATA0   /*!< Signal name */
+
+/* GPIO_SD_B1_10 (number 9), FlexSPI_D1_A/U13[2] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL                   FLEXSPI_A_DATA1   /*!< Signal name */
+
+/* GPIO_SD_B1_09 (number 10), FlexSPI_D2_A/U13[3] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL                   FLEXSPI_A_DATA2   /*!< Signal name */
+
+/* GPIO_SD_B1_06 (number 13), FlexSPI_D3_A/U13[7] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL                   FLEXSPI_A_DATA3   /*!< Signal name */
+
+/* GPIO_SD_B1_11 (number 8), FlexSPI_SS0/U13[1] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL                    FLEXSPI_A_SS0_B   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitQSPIPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h
index 94af5a115..f1415aeec 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
new file mode 100644
index 000000000..88265d32e
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
@@ -0,0 +1,448 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1015xxxxx</processor>
+      <package>MIMXRT1015DAF5A</package>
+      <board>MIMXRT1015-EVK</board>
+      <board_revision>B</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="21" pin_signal="GPIO_SD_B1_01" label="GPIO SD_B1_01" identifier="USER_LED"/>
+            </pin_labels>
+            <external_user_signals>
+               <properties/>
+            </external_user_signals>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO2" signal="gpio_io, 09" pin_num="1" pin_signal="GPIO_EMC_09">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_47K_Ohm"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07">
+                     <pin_features>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06"/>
+                  <pin peripheral="GPIO3" signal="gpio_io, 21" pin_num="21" pin_signal="GPIO_SD_B1_01">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="12" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="11" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="9" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="10" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="13" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="8" pin_signal="GPIO_SD_B1_11"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="2160/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="352/3 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.CLKO2_SEL.sel" value="CCM.LPI2C_CLK_ROOT" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="2" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>N/A</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="57fc488c-a9f7-4a03-8ab3-5d2a3fd16a50" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="DEBUG_UART" uuid="600d7aee-5a2d-4373-9763-ce007b981c15" type="lpuart" type_id="lpuart_bebe3e12b6ec22bbd14199038f2bf459" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="COMBO_SENSOR" uuid="96f9e552-25e5-434a-9454-5cf9e614733d" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_LED" uuid="5592aac0-ced9-4284-88a8-bbeb5083a92f" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO3" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO3_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                        <setting name="enable_irq_comb_16_31" value="false"/>
+                        <struct name="gpio_interrupt_comb_16_31">
+                           <setting name="IRQn" value="GPIO3_Combined_16_31_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_BUTTON" uuid="e7774953-3606-41b8-8b72-6e09025369e0" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                        <setting name="enable_irq_comb_16_31" value="false"/>
+                        <struct name="gpio_interrupt_comb_16_31">
+                           <setting name="IRQn" value="GPIO2_Combined_16_31_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="0329fbca-00e5-4ec4-9f79-3cb65a7b267a" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="59cf1b09-8396-4bf9-bed6-03d5457c292f" type_id="system_54b53072540eeeb8f8e9343e71f28176">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="7d589e9f-7522-408c-b7c8-42770920766f" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="e9da5e16-1f55-49be-87ec-af8cfd4a4105" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="9dc7a034-9408-4852-9990-a713693635ee" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="28ec81a8-d7ea-4363-9330-20b877c481f6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="774dd0a0-63ed-4846-b9d7-dfd082d810e3" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="77cd333e-4adc-4c6e-8b18-bbe349d78182" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>N/A</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
new file mode 100644
index 000000000..39c94147c
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT MIMXRT1021)
+
+set(JLINK_DEVICE MIMXRT1021xxx5A)
+set(PYOCD_TARGET mimxrt1020)
+set(NXPLINK_DEVICE MIMXRT1021xxxxx:EVK-MIMXRT1020)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1020_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1021DAG5A
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
index 56ed5855b..3f9c97e11 100644
--- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -24,28 +24,29 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: i.MX RT1020 Evaluation Kit
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1020-EVK
+*/
 
-#ifndef BOARD_H_
-#define BOARD_H_
+#ifndef BOARD_MIMXRT1020_EVK_H_
+#define BOARD_MIMXRT1020_EVK_H_
 
-// required since iMX RT10xx SDK include this file for board size
+// required since iMXRT MCUX-SDK include this file for board size
 #define BOARD_FLASH_SIZE (0x800000U)
 
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_05_GPIO1_IO05
-#define LED_PORT              GPIO1
-#define LED_PIN               5
+// LED: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05
+#define LED_PORT              BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN               BOARD_INITPINS_USER_LED_CHANNEL
 #define LED_STATE_ON          0
 
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
-#define BUTTON_PORT           GPIO5
-#define BUTTON_PIN            0
+// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_GPIO
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_GPIO_PIN
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
+// UART: IOMUXC_GPIO_AD_B0_07_LPUART1_RX, IOMUXC_GPIO_AD_B0_06_LPUART1_TX
 #define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_07_LPUART1_RX
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_06_LPUART1_TX
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
 
-#endif /* BOARD_H_ */
+#endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
index b15da1b67..e269c8ac5 100644
--- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
@@ -2,7 +2,7 @@ CFLAGS += -DCPU_MIMXRT1021DAG5A
 MCU_VARIANT = MIMXRT1021
 
 # For flash-jlink target
-JLINK_DEVICE = MIMXRT1021DAG5A
+JLINK_DEVICE = MIMXRT1021xxx5A
 
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1020
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c
new file mode 100644
index 000000000..764042928
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c
@@ -0,0 +1,421 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1021xxxxx
+package_id: MIMXRT1021DAG5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1020-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
+- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput = false,                 /* Disable the PLL providing the ENET 125MHz reference clock */
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .enableClkOutput25M = false,              /* Disable the PLL providing the ENET 25MHz reference clock */
+        .loopDivider = 1,                         /* Set frequency of ethernet reference clock to 50 MHz */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
+#endif
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+    /* Backward compatibility for original bitfield name */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h
new file mode 100644
index 000000000..d678a4f66
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h
@@ -0,0 +1,108 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           0UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              62500000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            176000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            176000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/pin_mux.c
new file mode 100644
index 000000000..07d910c2c
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/pin_mux.c
@@ -0,0 +1,342 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1021xxxxx
+package_id: MIMXRT1021DAG5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1020-EVK
+external_user_signals: {}
+pin_labels:
+- {pin_num: '52', pin_signal: WAKEUP, label: USER_BUTTON, identifier: USER_BUTTON}
+- {pin_num: '106', pin_signal: GPIO_AD_B0_05, label: 'JTAG_nTRST/J16[3]/USER_LED/J17[5]', identifier: USER_LED}
+power_domains: {NVCC_GPIO: '3.3'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '52', peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
+  - {pin_num: '106', peripheral: GPIO1, signal: 'gpio_io, 05', pin_signal: GPIO_AD_B0_05, direction: OUTPUT, pull_keeper_select: Keeper}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+  CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+  /* GPIO configuration of USER_LED on GPIO_AD_B0_05 (pin 106) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_B0_05 (pin 106) */
+  GPIO_PinInit(GPIO1, 5U, &USER_LED_config);
+
+  /* GPIO configuration of USER_BUTTON on WAKEUP (pin 52) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on WAKEUP (pin 52) */
+  GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0x50A0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07}
+  - {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSDRAMPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '142', peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_16}
+  - {pin_num: '141', peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_17}
+  - {pin_num: '140', peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_18}
+  - {pin_num: '139', peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_19}
+  - {pin_num: '138', peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_20}
+  - {pin_num: '136', peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_22}
+  - {pin_num: '137', peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_21}
+  - {pin_num: '133', peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_23}
+  - {pin_num: '132', peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_24}
+  - {pin_num: '131', peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_25}
+  - {pin_num: '143', peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_15}
+  - {pin_num: '130', peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_26}
+  - {pin_num: '129', peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_27}
+  - {pin_num: '2', peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_13}
+  - {pin_num: '1', peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_14}
+  - {pin_num: '7', peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_10}
+  - {pin_num: '127', peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_29}
+  - {pin_num: '126', peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_30}
+  - {pin_num: '3', peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_12}
+  - {pin_num: '8', peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_09}
+  - {pin_num: '4', peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_11}
+  - {pin_num: '128', peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_28}
+  - {pin_num: '125', peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_31}
+  - {pin_num: '9', peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
+  - {pin_num: '117', peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_39}
+  - {pin_num: '118', peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_38}
+  - {pin_num: '119', peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_37}
+  - {pin_num: '120', peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_36}
+  - {pin_num: '122', peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_34}
+  - {pin_num: '121', peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_35}
+  - {pin_num: '123', peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_33}
+  - {pin_num: '124', peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_32}
+  - {pin_num: '10', peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
+  - {pin_num: '12', peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
+  - {pin_num: '13', peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
+  - {pin_num: '14', peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
+  - {pin_num: '15', peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
+  - {pin_num: '16', peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
+  - {pin_num: '17', peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
+  - {pin_num: '18', peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSDRAMPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSDRAMPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_WE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_CAS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_RAS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_CS0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_BA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_BA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_ADDR05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_ADDR06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_ADDR08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_ADDR09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_ADDR11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_ADDR12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_DQS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CKE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DM01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA13, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DATA14, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DATA15, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCANPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '32', peripheral: CAN1, signal: RX, pin_signal: GPIO_SD_B1_01}
+  - {pin_num: '33', peripheral: CAN1, signal: TX, pin_signal: GPIO_SD_B1_00}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCANPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCANPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitENETPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '97', peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_AD_B0_11}
+  - {pin_num: '84', peripheral: GPIO1, signal: 'gpio_io, 22', pin_signal: GPIO_AD_B1_06}
+  - {pin_num: '107', peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
+  - {pin_num: '100', peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_AD_B0_08}
+  - {pin_num: '95', peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_AD_B0_13}
+  - {pin_num: '93', peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_AD_B0_15}
+  - {pin_num: '94', peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_AD_B0_14}
+  - {pin_num: '96', peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_AD_B0_12}
+  - {pin_num: '99', peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_AD_B0_09}
+  - {pin_num: '98', peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_AD_B0_10}
+  - {pin_num: '116', peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_40}
+  - {pin_num: '115', peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_41}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitENETPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitENETPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSDHCPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '45', peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_03}
+  - {pin_num: '46', peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_02}
+  - {pin_num: '43', peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_04}
+  - {pin_num: '42', peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_05}
+  - {pin_num: '48', peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_00}
+  - {pin_num: '47', peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_01}
+  - {pin_num: '41', peripheral: GPIO3, signal: 'gpio_io, 19', pin_signal: GPIO_SD_B0_06}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSDHCPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUSDHCPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_CMD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_06_GPIO3_IO19, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitQSPIPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '24', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
+  - {pin_num: '23', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
+  - {pin_num: '21', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10}
+  - {pin_num: '22', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09}
+  - {pin_num: '25', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06}
+  - {pin_num: '19', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitQSPIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitQSPIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/pin_mux.h
new file mode 100644
index 000000000..4155c56ec
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/pin_mux.h
@@ -0,0 +1,542 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* WAKEUP (number 52), USER_BUTTON */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO5   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    0U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                    GPIO5   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN                                   0U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK                      (1U << 0U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_BUTTON_PORT                                    GPIO5   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_PIN                                        0U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_BUTTON_PIN_MASK                           (1U << 0U)   /*!< PORT pin mask */
+
+/* GPIO_AD_B0_05 (number 106), JTAG_nTRST/J16[3]/USER_LED/J17[5] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO1   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                   gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                       5U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_GPIO                                       GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN                                      5U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                         (1U << 5U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_LED_PORT                                       GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_PIN                                           5U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_LED_PIN_MASK                              (1U << 5U)   /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+/* GPIO_AD_B0_07 (number 101), UART1_RXD/J17[4] */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL                             RX   /*!< Signal name */
+
+/* GPIO_AD_B0_06 (number 105), UART1_TXD/J17[6] */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL                             TX   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void);
+
+/* GPIO_EMC_16 (number 142), SEMC_A0/U14[23]/BOOT_MODE[0] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL                                   0U   /*!< Signal channel */
+
+/* GPIO_EMC_17 (number 141), SEMC_A1/U14[24]/BOOT_MODE[1] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL                                   1U   /*!< Signal channel */
+
+/* GPIO_EMC_18 (number 140), SEMC_A2/U14[25]/BT_CFG[0] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL                                   2U   /*!< Signal channel */
+
+/* GPIO_EMC_19 (number 139), SEMC_A3/U14[26]/BT_CFG[1] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL                                   3U   /*!< Signal channel */
+
+/* GPIO_EMC_20 (number 138), SEMC_A4/U14[29]/BT_CFG[2] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL                                   4U   /*!< Signal channel */
+
+/* GPIO_EMC_22 (number 136), SEMC_A6/U14[31]/BT_CFG[4] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL                                   6U   /*!< Signal channel */
+
+/* GPIO_EMC_21 (number 137), SEMC_A5/U14[30]/BT_CFG[3] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL                                   5U   /*!< Signal channel */
+
+/* GPIO_EMC_23 (number 133), SEMC_A7/U14[32]/BT_CFG[5] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL                                   7U   /*!< Signal channel */
+
+/* GPIO_EMC_24 (number 132), SEMC_A8/U14[33]/BT_CFG[6] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL                                   8U   /*!< Signal channel */
+
+/* GPIO_EMC_25 (number 131), SEMC_A9/U14[34]/BT_CFG[7] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL                                   9U   /*!< Signal channel */
+
+/* GPIO_EMC_15 (number 143), SEMC_A10/U14[22] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL                                 10U   /*!< Signal channel */
+
+/* GPIO_EMC_26 (number 130), SEMC_A11/U14[35]/BT_CFG[8] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL                                 11U   /*!< Signal channel */
+
+/* GPIO_EMC_27 (number 129), SEMC_A12/U14[36]/BT_CFG[9] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL                                 12U   /*!< Signal channel */
+
+/* GPIO_EMC_13 (number 2), SEMC_BA0/U14[20] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL                                   BA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_14 (number 1), SEMC_BA1/U14[21] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL                                   BA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_EMC_10 (number 7), SEMC_CAS/U14[17] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL                             semc_cas   /*!< Signal name */
+
+/* GPIO_EMC_29 (number 127), SEMC_CKE/U14[37] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL                             semc_cke   /*!< Signal name */
+
+/* GPIO_EMC_30 (number 126), SEMC_CLK/U14[38] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL                             semc_clk   /*!< Signal name */
+
+/* GPIO_EMC_12 (number 3), SEMC_CS0/U14[19] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_SIGNAL                                   CS   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_09 (number 8), SEMC_WE/U14[16] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL                               semc_we   /*!< Signal name */
+
+/* GPIO_EMC_11 (number 4), SEMC_RAS/U14[18] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL                             semc_ras   /*!< Signal name */
+
+/* GPIO_EMC_28 (number 128), SEMC_DQS */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DQS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DQS_SIGNAL                             semc_dqs   /*!< Signal name */
+
+/* GPIO_EMC_31 (number 125), SEMC_DM1/U14[39] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL                                   DM   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_EMC_08 (number 9), SEMC_DM0/U14[15] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL                                   DM   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_39 (number 117), SEMC_D15/U14[53] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL                                 15U   /*!< Signal channel */
+
+/* GPIO_EMC_38 (number 118), SEMC_D14/U14[51] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL                                 14U   /*!< Signal channel */
+
+/* GPIO_EMC_37 (number 119), SEMC_D13/U14[50] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL                                 13U   /*!< Signal channel */
+
+/* GPIO_EMC_36 (number 120), SEMC_D12/U14[48] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL                                 12U   /*!< Signal channel */
+
+/* GPIO_EMC_34 (number 122), SEMC_D10/U14[45] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL                                 10U   /*!< Signal channel */
+
+/* GPIO_EMC_35 (number 121), SEMC_D11/U14[47] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL                                 11U   /*!< Signal channel */
+
+/* GPIO_EMC_33 (number 123), SEMC_D9/U14[44] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL                                   9U   /*!< Signal channel */
+
+/* GPIO_EMC_32 (number 124), SEMC_D8/U14[42] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL                                   8U   /*!< Signal channel */
+
+/* GPIO_EMC_07 (number 10), SEMC_D7/U14[13] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL                                   7U   /*!< Signal channel */
+
+/* GPIO_EMC_06 (number 12), SEMC_D6/U14[11] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL                                   6U   /*!< Signal channel */
+
+/* GPIO_EMC_05 (number 13), SEMC_D5/U14[10] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL                                   5U   /*!< Signal channel */
+
+/* GPIO_EMC_04 (number 14), SEMC_D4/U14[8] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL                                   4U   /*!< Signal channel */
+
+/* GPIO_EMC_03 (number 15), SEMC_D3/U14[7] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL                                   3U   /*!< Signal channel */
+
+/* GPIO_EMC_02 (number 16), SEMC_D2/U14[5] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL                                   2U   /*!< Signal channel */
+
+/* GPIO_EMC_01 (number 17), SEMC_D1/U14[4] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL                                   1U   /*!< Signal channel */
+
+/* GPIO_EMC_00 (number 18), SEMC_D0/U14[2] */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL                                   0U   /*!< Signal channel */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSDRAMPins(void);
+
+/* GPIO_SD_B1_01 (number 32), CAN1_RX/U9[4] */
+/* Routed pin properties */
+#define BOARD_INITCANPINS_CAN1_RX_PERIPHERAL                                CAN1   /*!< Peripheral name */
+#define BOARD_INITCANPINS_CAN1_RX_SIGNAL                                      RX   /*!< Signal name */
+
+/* GPIO_SD_B1_00 (number 33), CAN1_TX/U9[1] */
+/* Routed pin properties */
+#define BOARD_INITCANPINS_CAN1_TX_PERIPHERAL                                CAN1   /*!< Peripheral name */
+#define BOARD_INITCANPINS_CAN1_TX_SIGNAL                                      TX   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCANPins(void);
+
+/* GPIO_AD_B0_11 (number 97), ENET_CRS_DV/U11[18]/J19[3] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL                           ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL                         enet_rx_en   /*!< Signal name */
+
+/* GPIO_AD_B1_06 (number 84), ENET_INT/U11[21]/J17[8] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_INT_PERIPHERAL                             GPIO1   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_INT_SIGNAL                               gpio_io   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_INT_CHANNEL                                  22U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITENETPINS_ENET_INT_GPIO                                   GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITENETPINS_ENET_INT_GPIO_PIN                                 22U   /*!< GPIO pin number */
+#define BOARD_INITENETPINS_ENET_INT_GPIO_PIN_MASK                    (1U << 22U)   /*!< GPIO pin mask */
+#define BOARD_INITENETPINS_ENET_INT_PORT                                   GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITENETPINS_ENET_INT_PIN                                      22U   /*!< PORT pin number */
+#define BOARD_INITENETPINS_ENET_INT_PIN_MASK                         (1U << 22U)   /*!< PORT pin mask */
+
+/* GPIO_AD_B0_04 (number 107), JTAG_TDO/J16[13]/ENET_RST/U11[32] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RST_PERIPHERAL                             GPIO1   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RST_SIGNAL                               gpio_io   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_RST_CHANNEL                                   4U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITENETPINS_ENET_RST_GPIO                                   GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITENETPINS_ENET_RST_GPIO_PIN                                  4U   /*!< GPIO pin number */
+#define BOARD_INITENETPINS_ENET_RST_GPIO_PIN_MASK                     (1U << 4U)   /*!< GPIO pin mask */
+#define BOARD_INITENETPINS_ENET_RST_PORT                                   GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITENETPINS_ENET_RST_PIN                                       4U   /*!< PORT pin number */
+#define BOARD_INITENETPINS_ENET_RST_PIN_MASK                          (1U << 4U)   /*!< PORT pin mask */
+
+/* GPIO_AD_B0_08 (number 100), ENET_TX_CLK/U11[9] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL                           ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL                        enet_tx_clk   /*!< Signal name */
+
+/* GPIO_AD_B0_13 (number 95), ENET_TXEN/U11[23]/J19[5] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL                           enet_tx_en   /*!< Signal name */
+
+/* GPIO_AD_B0_15 (number 93), ENET_TXD1/U11[25]/J19[2] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL                         enet_tx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_AD_B0_14 (number 94), ENET_TXD0/U11[24]/J17[7] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL                         enet_tx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_AD_B0_12 (number 96), ENET_RXER/U11[20]/J19[4] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXER_SIGNAL                           enet_rx_er   /*!< Signal name */
+
+/* GPIO_AD_B0_09 (number 99), ENET_RXD1/U11[15]/J17[3] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL                         enet_rx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_AD_B0_10 (number 98), ENET_RXD0/U11[16]/J19[6] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL                         enet_rx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_40 (number 116), ENET_MDIO/U11[11] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL                            enet_mdio   /*!< Signal name */
+
+/* GPIO_EMC_41 (number 115), ENET_MDC/U11[12] */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL                              ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_MDC_SIGNAL                              enet_mdc   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitENETPins(void);
+
+/* GPIO_SD_B0_03 (number 45), SD1_CLK/J15[5] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL                             usdhc_clk   /*!< Signal name */
+
+/* GPIO_SD_B0_02 (number 46), SD1_CMD/J15[3] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL                             usdhc_cmd   /*!< Signal name */
+
+/* GPIO_SD_B0_04 (number 43), SD1_D0/J15[7] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL                                    0U   /*!< Signal channel */
+
+/* GPIO_SD_B0_05 (number 42), SD1_D1/J15[8] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL                                    1U   /*!< Signal channel */
+
+/* GPIO_SD_B0_00 (number 48), SD1_D2/J15[1] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_SD_B0_01 (number 47), SD1_D3/J15[2] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL                                    3U   /*!< Signal channel */
+
+/* GPIO_SD_B0_06 (number 41), SD_CD_SW/J15[9] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_PERIPHERAL                            GPIO3   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_SIGNAL                              gpio_io   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_CHANNEL                                 19U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_GPIO                                  GPIO3   /*!< GPIO peripheral base pointer */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_GPIO_PIN                                19U   /*!< GPIO pin number */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_GPIO_PIN_MASK                   (1U << 19U)   /*!< GPIO pin mask */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_PORT                                  GPIO3   /*!< PORT peripheral base pointer */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_PIN                                     19U   /*!< PORT pin number */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_PIN_MASK                        (1U << 19U)   /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSDHCPins(void);
+
+/* GPIO_SD_B1_07 (number 24), FlexSPI_CLK/U13[6] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL                     FLEXSPI_A_SCLK   /*!< Signal name */
+
+/* GPIO_SD_B1_08 (number 23), FlexSPI_D0_A/U13[5] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL                   FLEXSPI_A_DATA0   /*!< Signal name */
+
+/* GPIO_SD_B1_10 (number 21), FlexSPI_D1_A/U13[2] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL                   FLEXSPI_A_DATA1   /*!< Signal name */
+
+/* GPIO_SD_B1_09 (number 22), FlexSPI_D2_A/U13[3] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL                   FLEXSPI_A_DATA2   /*!< Signal name */
+
+/* GPIO_SD_B1_06 (number 25), FlexSPI_D3_A/U13[7] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL                   FLEXSPI_A_DATA3   /*!< Signal name */
+
+/* GPIO_SD_B1_11 (number 19), FlexSPI_SS0/U13[1] */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL                    FLEXSPI_A_SS0_B   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitQSPIPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
index f5e1aca5c..ad79d5002 100644
--- a/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex b/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex
new file mode 100644
index 000000000..4437a420e
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex
@@ -0,0 +1,628 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1020-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="a558cc6e-82c2-41f9-9f55-0348efc7896f" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1021xxxxx</processor>
+      <package>MIMXRT1021DAG5A</package>
+      <board>MIMXRT1020-EVK</board>
+      <board_revision>A3</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="52" pin_signal="WAKEUP" label="USER_BUTTON" identifier="USER_BUTTON"/>
+               <pin_label pin_num="106" pin_signal="GPIO_AD_B0_05" label="JTAG_nTRST/J16[3]/USER_LED/J17[5]" identifier="USER_LED"/>
+            </pin_labels>
+            <external_user_signals>
+               <properties/>
+            </external_user_signals>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO5" signal="gpio_io, 00" pin_num="52" pin_signal="WAKEUP">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 05" pin_num="106" pin_signal="GPIO_AD_B0_05">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="142" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="141" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="140" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="139" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="138" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="136" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="137" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="133" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="132" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="131" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="143" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="130" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="129" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="2" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="1" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="7" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="127" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="126" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="3" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="8" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="4" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="128" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="125" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="9" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="117" pin_signal="GPIO_EMC_39"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="118" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="119" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="120" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="122" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="121" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="123" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="124" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="10" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="12" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="13" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="14" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="15" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="16" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="17" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="18" pin_signal="GPIO_EMC_00"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN1" description="Peripheral CAN1 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN1" signal="RX" pin_num="32" pin_signal="GPIO_SD_B1_01"/>
+                  <pin peripheral="CAN1" signal="TX" pin_num="33" pin_signal="GPIO_SD_B1_00"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="97" pin_signal="GPIO_AD_B0_11"/>
+                  <pin peripheral="GPIO1" signal="gpio_io, 22" pin_num="84" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="107" pin_signal="GPIO_AD_B0_04"/>
+                  <pin peripheral="ENET" signal="enet_tx_clk" pin_num="100" pin_signal="GPIO_AD_B0_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="95" pin_signal="GPIO_AD_B0_13"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="93" pin_signal="GPIO_AD_B0_15"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="94" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="96" pin_signal="GPIO_AD_B0_12"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="99" pin_signal="GPIO_AD_B0_09"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="98" pin_signal="GPIO_AD_B0_10"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="116" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="115" pin_signal="GPIO_EMC_41"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="GPIO3" signal="gpio_io, 19" pin_num="41" pin_signal="GPIO_SD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="24" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="23" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="21" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="22" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="25" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="19" pin_signal="GPIO_SD_B1_11"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL2_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.USDHC1_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM.USDHC2_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_ENABLE_CFG" value="Disabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG" value="Disabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/dcd.c" update_enabled="true"/>
+            <file path="board/dcd.h" update_enabled="true"/>
+         </generated_project_files>
+         <dcdx_profile>
+            <processor_version>13.0.2</processor_version>
+            <output_format>c_array</output_format>
+         </dcdx_profile>
+         <dcdx_configurations>
+            <dcdx_configuration name="Device_configuration">
+               <description></description>
+               <options/>
+               <command_groups/>
+            </dcdx_configuration>
+         </dcdx_configurations>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="6d394465-bc9b-47f2-9a1f-3ca61f76d27b" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="d0b30ebd-b05e-42b2-8e94-40b1625c2dba" type="flexcan" type_id="flexcan_10d80efac19b25dcd240244aae88dca0" mode="interrupts" peripheral="CAN1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="wakeupSrc" value="kFLEXCAN_WakeupSrcUnfiltered"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableTimerSync" value="true"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="27a94726-61ef-42ac-b517-d1eda3853dfe" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="e2a4cccd-cb23-4714-8c90-022fcf6146e8" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="bd191d83-2cb2-40ed-a718-47b39d772006" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="d097438f-179b-43e0-b37c-aee31212cebd" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="d84400f7-fd84-4466-908a-04abca190ef6" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="4f0123a9-0338-4076-b275-b49951642704" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="18150193-6d2b-469f-88e5-4908669bf3e5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="602159e8-d65b-45d3-b63b-cd33be549134" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="eb963b89-5367-4d86-8885-82b4b8cff735" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+      <common name="common" version="1.0" enabled="true" update_project_code="true">
+         <core name="core0" role="primary" project_name="Project"/>
+      </common>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
new file mode 100644
index 000000000..45487d148
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MIMXRT1024)
+
+set(JLINK_DEVICE MIMXRT1024xxx5A)
+set(PYOCD_TARGET mimxrt1024)
+set(NXPLINK_DEVICE MIMXRT1024xxxxx:MIMXRT1024-EVK)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1024_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1024DAG5A
+    CFG_EXAMPLE_VIDEO_READONLY
+    #-Wno-error=array-bounds
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
new file mode 100644
index 000000000..39e63c472
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: i.MX RT1024 Evaluation Kit
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1024-evaluation-kit:MIMXRT1024-EVK
+*/
+
+#ifndef BOARD_MIMXRT1024_EVK_H_
+#define BOARD_MIMXRT1024_EVK_H_
+
+// required since iMXRT MCUX-SDK include this file for board size
+// RT1020-EVK #define BOARD_FLASH_SIZE (0x800000U)
+#define BOARD_FLASH_SIZE (0x400000U) // builtin flash of RT1024
+
+// LED: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24
+#define LED_PORT              BOARD_INITPINS_USER_LED_GPIO
+#define LED_PIN               BOARD_INITPINS_USER_LED_PIN
+#define LED_STATE_ON          1
+
+// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_GPIO
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_PIN
+#define BUTTON_STATE_ACTIVE   0
+
+// UART: IOMUXC_GPIO_AD_B0_07_LPUART1_RX, IOMUXC_GPIO_AD_B0_06_LPUART1_TX
+#define UART_PORT             LPUART1
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
+
+#endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
new file mode 100644
index 000000000..3c325cc93
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += -DCPU_MIMXRT1024DAG5A
+MCU_VARIANT = MIMXRT1024
+
+# warnings caused by mcu driver
+CFLAGS += -Wno-error=array-bounds
+
+# For flash-jlink target
+JLINK_DEVICE = MIMXRT1024xxx5A
+
+# For flash-pyocd target
+PYOCD_TARGET = mimxrt1024
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c
new file mode 100644
index 000000000..ba0cadafa
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c
@@ -0,0 +1,421 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1024xxxxx
+package_id: MIMXRT1024DAG5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1024-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
+- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput = false,                 /* Disable the PLL providing the ENET 125MHz reference clock */
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .enableClkOutput25M = false,              /* Disable the PLL providing the ENET 25MHz reference clock */
+        .loopDivider = 1,                         /* Set frequency of ethernet reference clock to 50 MHz */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
+#endif
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+    /* Backward compatibility for original bitfield name */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h
new file mode 100644
index 000000000..d678a4f66
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h
@@ -0,0 +1,108 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           0UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              62500000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            176000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            176000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/pin_mux.c
new file mode 100644
index 000000000..29a9d8d3d
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/pin_mux.c
@@ -0,0 +1,490 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1024xxxxx
+package_id: MIMXRT1024DAG5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1024-EVK
+pin_labels:
+- {pin_num: '52', pin_signal: WAKEUP, label: USER_BUTTON, identifier: USER_BUTTON}
+- {pin_num: '82', pin_signal: GPIO_AD_B1_08, label: 'UART_TX/USER_LED/J17[4]', identifier: USER_LED}
+power_domains: {NVCC_GPIO: '3.3'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
+
+/* GPIO_AD_B1_00~GPIO_AD_B1_05 can only be configured as flexspi function. Note that it can't be modified here */
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03,1U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK,1U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00,1U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02,1U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01,1U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B,1U);
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '52', peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
+  - {pin_num: '82', peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08, direction: OUTPUT}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+  CLOCK_EnableClock(kCLOCK_IomuxcSnvs);       /* iomuxc_snvs clock (iomuxc_snvs_clk_enable): 0x03U */
+
+  /* GPIO configuration of USER_LED on GPIO_AD_B1_08 (pin 82) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_B1_08 (pin 82) */
+  GPIO_PinInit(GPIO1, 24U, &USER_LED_config);
+
+  /* GPIO configuration of USER_BUTTON on WAKEUP (pin 52) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on WAKEUP (pin 52) */
+  GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B1_08_GPIO1_IO24,        /* GPIO_AD_B1_08 is configured as GPIO1_IO24 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_SNVS_WAKEUP_GPIO5_IO00,          /* WAKEUP is configured as GPIO5_IO00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07}
+  - {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_06_LPUART1_TX,        /* GPIO_AD_B0_06 is configured as LPUART1_TX */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_07_LPUART1_RX,        /* GPIO_AD_B0_07 is configured as LPUART1_RX */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSDRAMPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '142', peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_16}
+  - {pin_num: '141', peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_17}
+  - {pin_num: '140', peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_18}
+  - {pin_num: '139', peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_19}
+  - {pin_num: '138', peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_20}
+  - {pin_num: '136', peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_22}
+  - {pin_num: '137', peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_21}
+  - {pin_num: '133', peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_23}
+  - {pin_num: '132', peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_24}
+  - {pin_num: '131', peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_25}
+  - {pin_num: '143', peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_15}
+  - {pin_num: '130', peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_26}
+  - {pin_num: '129', peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_27}
+  - {pin_num: '2', peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_13}
+  - {pin_num: '1', peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_14}
+  - {pin_num: '7', peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_10}
+  - {pin_num: '127', peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_29}
+  - {pin_num: '126', peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_30}
+  - {pin_num: '3', peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_12}
+  - {pin_num: '8', peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_09}
+  - {pin_num: '4', peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_11}
+  - {pin_num: '128', peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_28}
+  - {pin_num: '125', peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_31}
+  - {pin_num: '9', peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
+  - {pin_num: '117', peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_39}
+  - {pin_num: '118', peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_38}
+  - {pin_num: '119', peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_37}
+  - {pin_num: '120', peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_36}
+  - {pin_num: '122', peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_34}
+  - {pin_num: '121', peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_35}
+  - {pin_num: '123', peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_33}
+  - {pin_num: '124', peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_32}
+  - {pin_num: '10', peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
+  - {pin_num: '12', peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
+  - {pin_num: '13', peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
+  - {pin_num: '14', peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
+  - {pin_num: '15', peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
+  - {pin_num: '16', peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
+  - {pin_num: '17', peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
+  - {pin_num: '18', peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSDRAMPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSDRAMPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_00_SEMC_DATA00,         /* GPIO_EMC_00 is configured as SEMC_DATA00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_01_SEMC_DATA01,         /* GPIO_EMC_01 is configured as SEMC_DATA01 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_02_SEMC_DATA02,         /* GPIO_EMC_02 is configured as SEMC_DATA02 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_03_SEMC_DATA03,         /* GPIO_EMC_03 is configured as SEMC_DATA03 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_04_SEMC_DATA04,         /* GPIO_EMC_04 is configured as SEMC_DATA04 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_05_SEMC_DATA05,         /* GPIO_EMC_05 is configured as SEMC_DATA05 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_06_SEMC_DATA06,         /* GPIO_EMC_06 is configured as SEMC_DATA06 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_07_SEMC_DATA07,         /* GPIO_EMC_07 is configured as SEMC_DATA07 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_08_SEMC_DM00,           /* GPIO_EMC_08 is configured as SEMC_DM00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_09_SEMC_WE,             /* GPIO_EMC_09 is configured as SEMC_WE */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_10_SEMC_CAS,            /* GPIO_EMC_10 is configured as SEMC_CAS */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_11_SEMC_RAS,            /* GPIO_EMC_11 is configured as SEMC_RAS */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_12_SEMC_CS0,            /* GPIO_EMC_12 is configured as SEMC_CS0 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_13_SEMC_BA0,            /* GPIO_EMC_13 is configured as SEMC_BA0 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_14_SEMC_BA1,            /* GPIO_EMC_14 is configured as SEMC_BA1 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_15_SEMC_ADDR10,         /* GPIO_EMC_15 is configured as SEMC_ADDR10 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_16_SEMC_ADDR00,         /* GPIO_EMC_16 is configured as SEMC_ADDR00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_17_SEMC_ADDR01,         /* GPIO_EMC_17 is configured as SEMC_ADDR01 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_18_SEMC_ADDR02,         /* GPIO_EMC_18 is configured as SEMC_ADDR02 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_19_SEMC_ADDR03,         /* GPIO_EMC_19 is configured as SEMC_ADDR03 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_20_SEMC_ADDR04,         /* GPIO_EMC_20 is configured as SEMC_ADDR04 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_21_SEMC_ADDR05,         /* GPIO_EMC_21 is configured as SEMC_ADDR05 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_22_SEMC_ADDR06,         /* GPIO_EMC_22 is configured as SEMC_ADDR06 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_23_SEMC_ADDR07,         /* GPIO_EMC_23 is configured as SEMC_ADDR07 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_24_SEMC_ADDR08,         /* GPIO_EMC_24 is configured as SEMC_ADDR08 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_25_SEMC_ADDR09,         /* GPIO_EMC_25 is configured as SEMC_ADDR09 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_26_SEMC_ADDR11,         /* GPIO_EMC_26 is configured as SEMC_ADDR11 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_27_SEMC_ADDR12,         /* GPIO_EMC_27 is configured as SEMC_ADDR12 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_28_SEMC_DQS,            /* GPIO_EMC_28 is configured as SEMC_DQS */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_29_SEMC_CKE,            /* GPIO_EMC_29 is configured as SEMC_CKE */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_30_SEMC_CLK,            /* GPIO_EMC_30 is configured as SEMC_CLK */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_31_SEMC_DM01,           /* GPIO_EMC_31 is configured as SEMC_DM01 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_32_SEMC_DATA08,         /* GPIO_EMC_32 is configured as SEMC_DATA08 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_33_SEMC_DATA09,         /* GPIO_EMC_33 is configured as SEMC_DATA09 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_34_SEMC_DATA10,         /* GPIO_EMC_34 is configured as SEMC_DATA10 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_35_SEMC_DATA11,         /* GPIO_EMC_35 is configured as SEMC_DATA11 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_36_SEMC_DATA12,         /* GPIO_EMC_36 is configured as SEMC_DATA12 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_37_SEMC_DATA13,         /* GPIO_EMC_37 is configured as SEMC_DATA13 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_38_SEMC_DATA14,         /* GPIO_EMC_38 is configured as SEMC_DATA14 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_39_SEMC_DATA15,         /* GPIO_EMC_39 is configured as SEMC_DATA15 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCANPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '32', peripheral: CAN1, signal: RX, pin_signal: GPIO_SD_B1_01}
+  - {pin_num: '33', peripheral: CAN1, signal: TX, pin_signal: GPIO_SD_B1_00}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCANPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCANPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX,       /* GPIO_SD_B1_00 is configured as FLEXCAN1_TX */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX,       /* GPIO_SD_B1_01 is configured as FLEXCAN1_RX */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitENETPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '97', peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_AD_B0_11}
+  - {pin_num: '84', peripheral: GPIO1, signal: 'gpio_io, 22', pin_signal: GPIO_AD_B1_06}
+  - {pin_num: '107', peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
+  - {pin_num: '100', peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_AD_B0_08}
+  - {pin_num: '95', peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_AD_B0_13}
+  - {pin_num: '93', peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_AD_B0_15}
+  - {pin_num: '94', peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_AD_B0_14}
+  - {pin_num: '96', peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_AD_B0_12}
+  - {pin_num: '99', peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_AD_B0_09}
+  - {pin_num: '98', peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_AD_B0_10}
+  - {pin_num: '116', peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_40}
+  - {pin_num: '115', peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_41}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitENETPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitENETPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_04_GPIO1_IO04,        /* GPIO_AD_B0_04 is configured as GPIO1_IO04 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK,       /* GPIO_AD_B0_08 is configured as ENET_TX_CLK */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_09_ENET_RDATA01,      /* GPIO_AD_B0_09 is configured as ENET_RDATA01 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_10_ENET_RDATA00,      /* GPIO_AD_B0_10 is configured as ENET_RDATA00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_11_ENET_RX_EN,        /* GPIO_AD_B0_11 is configured as ENET_RX_EN */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_12_ENET_RX_ER,        /* GPIO_AD_B0_12 is configured as ENET_RX_ER */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_13_ENET_TX_EN,        /* GPIO_AD_B0_13 is configured as ENET_TX_EN */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_14_ENET_TDATA00,      /* GPIO_AD_B0_14 is configured as ENET_TDATA00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_15_ENET_TDATA01,      /* GPIO_AD_B0_15 is configured as ENET_TDATA01 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B1_06_GPIO1_IO22,        /* GPIO_AD_B1_06 is configured as GPIO1_IO22 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_40_ENET_MDIO,           /* GPIO_EMC_40 is configured as ENET_MDIO */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_41_ENET_MDC,            /* GPIO_EMC_41 is configured as ENET_MDC */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSDHCPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '45', peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_03}
+  - {pin_num: '46', peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_02}
+  - {pin_num: '43', peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_04}
+  - {pin_num: '42', peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_05}
+  - {pin_num: '48', peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_00}
+  - {pin_num: '47', peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_01}
+  - {pin_num: '41', peripheral: GPIO3, signal: 'gpio_io, 19', pin_signal: GPIO_SD_B0_06}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSDHCPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUSDHCPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2,      /* GPIO_SD_B0_00 is configured as USDHC1_DATA2 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3,      /* GPIO_SD_B0_01 is configured as USDHC1_DATA3 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B0_02_USDHC1_CMD,        /* GPIO_SD_B0_02 is configured as USDHC1_CMD */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B0_03_USDHC1_CLK,        /* GPIO_SD_B0_03 is configured as USDHC1_CLK */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0,      /* GPIO_SD_B0_04 is configured as USDHC1_DATA0 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1,      /* GPIO_SD_B0_05 is configured as USDHC1_DATA1 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B0_06_GPIO3_IO19,        /* GPIO_SD_B0_06 is configured as GPIO3_IO19 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitQSPIPins:
+- options: {coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '24', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
+  - {pin_num: '23', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
+  - {pin_num: '21', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10}
+  - {pin_num: '22', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09}
+  - {pin_num: '25', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06}
+  - {pin_num: '19', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitQSPIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitQSPIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03,  /* GPIO_SD_B1_06 is configured as FLEXSPI_A_DATA03 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK,    /* GPIO_SD_B1_07 is configured as FLEXSPI_A_SCLK */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00,  /* GPIO_SD_B1_08 is configured as FLEXSPI_A_DATA00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02,  /* GPIO_SD_B1_09 is configured as FLEXSPI_A_DATA02 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01,  /* GPIO_SD_B1_10 is configured as FLEXSPI_A_DATA01 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B,   /* GPIO_SD_B1_11 is configured as FLEXSPI_A_SS0_B */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/pin_mux.h
new file mode 100644
index 000000000..73ca62533
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/pin_mux.h
@@ -0,0 +1,439 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/* Define the flexspi macro. Note that it can't be modified here */
+#define IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03 0x401F80FCU, 0x1U, 0x401F8374U, 0x1U, 0x401F8270U
+#define IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK 0x401F8100U, 0x1U, 0x401F8378U, 0x1U, 0x401F8274U
+#define IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00 0x401F8104U, 0x1U, 0x401F8368U, 0x1U, 0x401F8278U
+#define IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02 0x401F8108U, 0x1U, 0x401F8370U, 0x1U, 0x401F827CU
+#define IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01 0x401F810CU, 0x1U, 0x401F836CU, 0x1U, 0x401F8280U
+#define IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B 0x401F8110U, 0x1U, 0, 0, 0x401F8284U
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* WAKEUP (number 52), USER_BUTTON */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                    GPIO5   /*!< GPIO device name: GPIO5 */
+#define BOARD_INITPINS_USER_BUTTON_PORT                                    GPIO5   /*!< PORT device name: GPIO5 */
+#define BOARD_INITPINS_USER_BUTTON_PIN                                        0U   /*!< GPIO5 pin index: 0 */
+
+/* GPIO_AD_B1_08 (number 82), UART_TX/USER_LED/J17[4] */
+#define BOARD_INITPINS_USER_LED_GPIO                                       GPIO1   /*!< GPIO device name: GPIO1 */
+#define BOARD_INITPINS_USER_LED_PORT                                       GPIO1   /*!< PORT device name: GPIO1 */
+#define BOARD_INITPINS_USER_LED_PIN                                          24U   /*!< GPIO1 pin index: 24 */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+/* GPIO_AD_B0_07 (number 101), UART1_RXD/J17[8] */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL                    LPUART1   /*!< Device name: LPUART1 */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL                             RX   /*!< LPUART1 signal: RX */
+
+/* GPIO_AD_B0_06 (number 105), UART1_TXD/J17[12] */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL                    LPUART1   /*!< Device name: LPUART1 */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL                             TX   /*!< LPUART1 signal: TX */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void);
+
+/* GPIO_EMC_16 (number 142), SEMC_A0/U14[23]/BOOT_MODE[0] */
+#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL                                   0U   /*!< SEMC ADDR channel: 00 */
+
+/* GPIO_EMC_17 (number 141), SEMC_A1/U14[24]/BOOT_MODE[1] */
+#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL                                   1U   /*!< SEMC ADDR channel: 01 */
+
+/* GPIO_EMC_18 (number 140), SEMC_A2/U14[25]/BT_CFG[0] */
+#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL                                   2U   /*!< SEMC ADDR channel: 02 */
+
+/* GPIO_EMC_19 (number 139), SEMC_A3/U14[26]/BT_CFG[1] */
+#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL                                   3U   /*!< SEMC ADDR channel: 03 */
+
+/* GPIO_EMC_20 (number 138), SEMC_A4/U14[29]/BT_CFG[2] */
+#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL                                   4U   /*!< SEMC ADDR channel: 04 */
+
+/* GPIO_EMC_22 (number 136), SEMC_A6/U14[31]/BT_CFG[4] */
+#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL                                   6U   /*!< SEMC ADDR channel: 06 */
+
+/* GPIO_EMC_21 (number 137), SEMC_A5/U14[30]/BT_CFG[3] */
+#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL                                   5U   /*!< SEMC ADDR channel: 05 */
+
+/* GPIO_EMC_23 (number 133), SEMC_A7/U14[32]/BT_CFG[5] */
+#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL                                   7U   /*!< SEMC ADDR channel: 07 */
+
+/* GPIO_EMC_24 (number 132), SEMC_A8/U14[33]/BT_CFG[6] */
+#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL                                   8U   /*!< SEMC ADDR channel: 08 */
+
+/* GPIO_EMC_25 (number 131), SEMC_A9/U14[34]/BT_CFG[7] */
+#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL                                  ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL                                   9U   /*!< SEMC ADDR channel: 09 */
+
+/* GPIO_EMC_15 (number 143), SEMC_A10/U14[22] */
+#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL                                 ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL                                 10U   /*!< SEMC ADDR channel: 10 */
+
+/* GPIO_EMC_26 (number 130), SEMC_A11/U14[35]/BT_CFG[8] */
+#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL                                 ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL                                 11U   /*!< SEMC ADDR channel: 11 */
+
+/* GPIO_EMC_27 (number 129), SEMC_A12/U14[36]/BT_CFG[9] */
+#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL                                 ADDR   /*!< SEMC signal: ADDR */
+#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL                                 12U   /*!< SEMC ADDR channel: 12 */
+
+/* GPIO_EMC_13 (number 2), SEMC_BA0/U14[20] */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL                                   BA   /*!< SEMC signal: BA */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL                                  0U   /*!< SEMC BA channel: 0 */
+
+/* GPIO_EMC_14 (number 1), SEMC_BA1/U14[21] */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL                                   BA   /*!< SEMC signal: BA */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL                                  1U   /*!< SEMC BA channel: 1 */
+
+/* GPIO_EMC_10 (number 7), SEMC_CAS/U14[17] */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL                             semc_cas   /*!< SEMC signal: semc_cas */
+
+/* GPIO_EMC_29 (number 127), SEMC_CKE/U14[37] */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL                             semc_cke   /*!< SEMC signal: semc_cke */
+
+/* GPIO_EMC_30 (number 126), SEMC_CLK/U14[38] */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL                             semc_clk   /*!< SEMC signal: semc_clk */
+
+/* GPIO_EMC_12 (number 3), SEMC_CS0/U14[19] */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_SIGNAL                                   CS   /*!< SEMC signal: CS */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_CHANNEL                                  0U   /*!< SEMC CS channel: 0 */
+
+/* GPIO_EMC_09 (number 8), SEMC_WE/U14[16] */
+#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL                               semc_we   /*!< SEMC signal: semc_we */
+
+/* GPIO_EMC_11 (number 4), SEMC_RAS/U14[18] */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL                             semc_ras   /*!< SEMC signal: semc_ras */
+
+/* GPIO_EMC_28 (number 128), SAI3_MCLK */
+#define BOARD_INITSDRAMPINS_SEMC_DQS_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_DQS_SIGNAL                             semc_dqs   /*!< SEMC signal: semc_dqs */
+
+/* GPIO_EMC_31 (number 125), SEMC_DM1/U14[39] */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL                                   DM   /*!< SEMC signal: DM */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL                                  1U   /*!< SEMC DM channel: 1 */
+
+/* GPIO_EMC_08 (number 9), SEMC_DM0/U14[15] */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL                                   DM   /*!< SEMC signal: DM */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL                                  0U   /*!< SEMC DM channel: 0 */
+
+/* GPIO_EMC_39 (number 117), SEMC_D15/U14[53] */
+#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL                                 DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL                                 15U   /*!< SEMC DATA channel: 15 */
+
+/* GPIO_EMC_38 (number 118), SEMC_D14/U14[51] */
+#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL                                 DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL                                 14U   /*!< SEMC DATA channel: 14 */
+
+/* GPIO_EMC_37 (number 119), SEMC_D13/U14[50] */
+#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL                                 DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL                                 13U   /*!< SEMC DATA channel: 13 */
+
+/* GPIO_EMC_36 (number 120), SEMC_D12/U14[48] */
+#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL                                 DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL                                 12U   /*!< SEMC DATA channel: 12 */
+
+/* GPIO_EMC_34 (number 122), SEMC_D10/U14[45] */
+#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL                                 DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL                                 10U   /*!< SEMC DATA channel: 10 */
+
+/* GPIO_EMC_35 (number 121), SEMC_D11/U14[47] */
+#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL                             SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL                                 DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL                                 11U   /*!< SEMC DATA channel: 11 */
+
+/* GPIO_EMC_33 (number 123), SEMC_D9/U14[44] */
+#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL                                   9U   /*!< SEMC DATA channel: 09 */
+
+/* GPIO_EMC_32 (number 124), SEMC_D8/U14[42] */
+#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL                                   8U   /*!< SEMC DATA channel: 08 */
+
+/* GPIO_EMC_07 (number 10), SEMC_D7/U14[13] */
+#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL                                   7U   /*!< SEMC DATA channel: 07 */
+
+/* GPIO_EMC_06 (number 12), SEMC_D6/U14[11] */
+#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL                                   6U   /*!< SEMC DATA channel: 06 */
+
+/* GPIO_EMC_05 (number 13), SEMC_D5/U14[10] */
+#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL                                   5U   /*!< SEMC DATA channel: 05 */
+
+/* GPIO_EMC_04 (number 14), SEMC_D4/U14[8] */
+#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL                                   4U   /*!< SEMC DATA channel: 04 */
+
+/* GPIO_EMC_03 (number 15), SEMC_D3/U14[7] */
+#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL                                   3U   /*!< SEMC DATA channel: 03 */
+
+/* GPIO_EMC_02 (number 16), SEMC_D2/U14[5] */
+#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL                                   2U   /*!< SEMC DATA channel: 02 */
+
+/* GPIO_EMC_01 (number 17), SEMC_D1/U14[4] */
+#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL                                   1U   /*!< SEMC DATA channel: 01 */
+
+/* GPIO_EMC_00 (number 18), SEMC_D0/U14[2] */
+#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL                              SEMC   /*!< Device name: SEMC */
+#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL                                  DATA   /*!< SEMC signal: DATA */
+#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL                                   0U   /*!< SEMC DATA channel: 00 */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSDRAMPins(void);
+
+/* GPIO_SD_B1_01 (number 32), CAN1_RX/U9[4] */
+#define BOARD_INITCANPINS_CAN1_RX_PERIPHERAL                                CAN1   /*!< Device name: CAN1 */
+#define BOARD_INITCANPINS_CAN1_RX_SIGNAL                                      RX   /*!< CAN1 signal: RX */
+
+/* GPIO_SD_B1_00 (number 33), CAN1_TX/U9[1] */
+#define BOARD_INITCANPINS_CAN1_TX_PERIPHERAL                                CAN1   /*!< Device name: CAN1 */
+#define BOARD_INITCANPINS_CAN1_TX_SIGNAL                                      TX   /*!< CAN1 signal: TX */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCANPins(void);
+
+/* GPIO_AD_B0_11 (number 97), ENET_CRS_DV/U11[18]/J19[6] */
+#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL                           ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL                         enet_rx_en   /*!< ENET signal: enet_rx_en */
+
+/* GPIO_AD_B1_06 (number 84), ENET_INT/U11[21]/J17[16] */
+#define BOARD_INITENETPINS_ENET_INT_GPIO                                   GPIO1   /*!< GPIO device name: GPIO1 */
+#define BOARD_INITENETPINS_ENET_INT_PORT                                   GPIO1   /*!< PORT device name: GPIO1 */
+#define BOARD_INITENETPINS_ENET_INT_PIN                                      22U   /*!< GPIO1 pin index: 22 */
+
+/* GPIO_AD_B0_04 (number 107), JTAG_TDO/ENET_RST/U11[32] */
+#define BOARD_INITENETPINS_ENET_RST_GPIO                                   GPIO1   /*!< GPIO device name: GPIO1 */
+#define BOARD_INITENETPINS_ENET_RST_PORT                                   GPIO1   /*!< PORT device name: GPIO1 */
+#define BOARD_INITENETPINS_ENET_RST_PIN                                       4U   /*!< GPIO1 pin index: 4 */
+
+/* GPIO_AD_B0_08 (number 100), ENET_TX_REF_CLK/U11[9] */
+#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL                           ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL                        enet_tx_clk   /*!< ENET signal: enet_tx_clk */
+
+/* GPIO_AD_B0_13 (number 95), ENET_TXEN/U11[23]/J19[10] */
+#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL                             ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL                           enet_tx_en   /*!< ENET signal: enet_tx_en */
+
+/* GPIO_AD_B0_15 (number 93), ENET_TXD1/U11[25]/J19[4] */
+#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL                             ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL                         enet_tx_data   /*!< ENET signal: enet_tx_data */
+#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL                                  1U   /*!< ENET enet_tx_data channel: 1 */
+
+/* GPIO_AD_B0_14 (number 94), ENET_TXD0/U11[24]/J17[14] */
+#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL                             ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL                         enet_tx_data   /*!< ENET signal: enet_tx_data */
+#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL                                  0U   /*!< ENET enet_tx_data channel: 0 */
+
+/* GPIO_AD_B0_12 (number 96), ENET_RXER/U11[20]/J19[8] */
+#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL                             ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_RXER_SIGNAL                           enet_rx_er   /*!< ENET signal: enet_rx_er */
+
+/* GPIO_AD_B0_09 (number 99), ENET_RXD1/U11[15]/J17[6] */
+#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL                             ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL                         enet_rx_data   /*!< ENET signal: enet_rx_data */
+#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL                                  1U   /*!< ENET enet_rx_data channel: 1 */
+
+/* GPIO_AD_B0_10 (number 98), ENET_RXD0/U11[16]/J19[12] */
+#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL                             ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL                         enet_rx_data   /*!< ENET signal: enet_rx_data */
+#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL                                  0U   /*!< ENET enet_rx_data channel: 0 */
+
+/* GPIO_EMC_40 (number 116), ENET_MDIO/U11[11] */
+#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL                             ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL                            enet_mdio   /*!< ENET signal: enet_mdio */
+
+/* GPIO_EMC_41 (number 115), ENET_MDC/U11[12] */
+#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL                              ENET   /*!< Device name: ENET */
+#define BOARD_INITENETPINS_ENET_MDC_SIGNAL                              enet_mdc   /*!< ENET signal: enet_mdc */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitENETPins(void);
+
+/* GPIO_SD_B0_03 (number 45), SD1_CLK/J15[5] */
+#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL                            USDHC1   /*!< Device name: USDHC1 */
+#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL                             usdhc_clk   /*!< USDHC1 signal: usdhc_clk */
+
+/* GPIO_SD_B0_02 (number 46), SD1_CMD/J15[3] */
+#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL                            USDHC1   /*!< Device name: USDHC1 */
+#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL                             usdhc_cmd   /*!< USDHC1 signal: usdhc_cmd */
+
+/* GPIO_SD_B0_04 (number 43), SD1_D0/J15[7] */
+#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL                             USDHC1   /*!< Device name: USDHC1 */
+#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL                             usdhc_data   /*!< USDHC1 signal: usdhc_data */
+#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL                                    0U   /*!< USDHC1 usdhc_data channel: 0 */
+
+/* GPIO_SD_B0_05 (number 42), SD1_D1/J15[8] */
+#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL                             USDHC1   /*!< Device name: USDHC1 */
+#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL                             usdhc_data   /*!< USDHC1 signal: usdhc_data */
+#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL                                    1U   /*!< USDHC1 usdhc_data channel: 1 */
+
+/* GPIO_SD_B0_00 (number 48), SD1_D2/J15[1] */
+#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL                             USDHC1   /*!< Device name: USDHC1 */
+#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL                             usdhc_data   /*!< USDHC1 signal: usdhc_data */
+#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL                                    2U   /*!< USDHC1 usdhc_data channel: 2 */
+
+/* GPIO_SD_B0_01 (number 47), SD1_D3/J15[2] */
+#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL                             USDHC1   /*!< Device name: USDHC1 */
+#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL                             usdhc_data   /*!< USDHC1 signal: usdhc_data */
+#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL                                    3U   /*!< USDHC1 usdhc_data channel: 3 */
+
+/* GPIO_SD_B0_06 (number 41), SD_CD_SW/J15[9] */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_GPIO                                  GPIO3   /*!< GPIO device name: GPIO3 */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_PORT                                  GPIO3   /*!< PORT device name: GPIO3 */
+#define BOARD_INITUSDHCPINS_SD_CD_SW_PIN                                     19U   /*!< GPIO3 pin index: 19 */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSDHCPins(void);
+
+/* GPIO_SD_B1_07 (number 24), SAI3_TX_SYNC */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL                        FLEXSPI   /*!< Device name: FLEXSPI */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL                     FLEXSPI_A_SCLK   /*!< FLEXSPI signal: FLEXSPI_A_SCLK */
+
+/* GPIO_SD_B1_08 (number 23), SAI3_TXD */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL                       FLEXSPI   /*!< Device name: FLEXSPI */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL                   FLEXSPI_A_DATA0   /*!< FLEXSPI signal: FLEXSPI_A_DATA0 */
+
+/* GPIO_SD_B1_10 (number 21), SD_PWREN */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL                       FLEXSPI   /*!< Device name: FLEXSPI */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL                   FLEXSPI_A_DATA1   /*!< FLEXSPI signal: FLEXSPI_A_DATA1 */
+
+/* GPIO_SD_B1_09 (number 22), AUD_INT */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL                       FLEXSPI   /*!< Device name: FLEXSPI */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL                   FLEXSPI_A_DATA2   /*!< FLEXSPI signal: FLEXSPI_A_DATA2 */
+
+/* GPIO_SD_B1_06 (number 25), SAI3_TX_BCLK */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL                       FLEXSPI   /*!< Device name: FLEXSPI */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL                   FLEXSPI_A_DATA3   /*!< FLEXSPI signal: FLEXSPI_A_DATA3 */
+
+/* GPIO_SD_B1_11 (number 19), SAI3_RXD */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL                        FLEXSPI   /*!< Device name: FLEXSPI */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL                    FLEXSPI_A_SS0_B   /*!< FLEXSPI signal: FLEXSPI_A_SS0_B */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitQSPIPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c b/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c
new file mode 100644
index 000000000..43dc1e823
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkmimxrt1024_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig =
+        {
+            .tag              = FLEXSPI_CFG_BLK_TAG,
+            .version          = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
+            .csHoldTime       = 3u,
+            .csSetupTime      = 3u,
+            .sflashPadType    = kSerialFlash_4Pads,
+            .serialClkFreq    = kFlexSpiSerialClk_60MHz,
+            .sflashA1Size     = 4u * 1024u * 1024u,
+            .lookupTable =
+                {
+                    // Read LUTs
+                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+                },
+        },
+    .pageSize           = 256u,
+    .sectorSize         = 4u * 1024u,
+    .blockSize          = 64u * 1024u,
+    .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
new file mode 100644
index 000000000..5231dc034
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.1. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* FLEXSPI memory config block related definitions */
+#define FLEXSPI_CFG_BLK_TAG     (0x42464346UL) // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE    (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related definitions */
+#define CMD_INDEX_READ        0
+#define CMD_INDEX_READSTATUS  1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE       4
+
+#define CMD_LUT_SEQ_IDX_READ        0
+#define CMD_LUT_SEQ_IDX_READSTATUS  1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE       9
+
+#define CMD_SDR        0x01
+#define CMD_DDR        0x21
+#define RADDR_SDR      0x02
+#define RADDR_DDR      0x22
+#define CADDR_SDR      0x03
+#define CADDR_DDR      0x23
+#define MODE1_SDR      0x04
+#define MODE1_DDR      0x24
+#define MODE2_SDR      0x05
+#define MODE2_DDR      0x25
+#define MODE4_SDR      0x06
+#define MODE4_DDR      0x26
+#define MODE8_SDR      0x07
+#define MODE8_DDR      0x27
+#define WRITE_SDR      0x08
+#define WRITE_DDR      0x28
+#define READ_SDR       0x09
+#define READ_DDR       0x29
+#define LEARN_SDR      0x0A
+#define LEARN_DDR      0x2A
+#define DATSZ_SDR      0x0B
+#define DATSZ_DDR      0x2B
+#define DUMMY_SDR      0x0C
+#define DUMMY_DDR      0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS      0x1F
+#define STOP           0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_75MHz  = 4,
+    kFlexSpiSerialClk_80MHz  = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_133MHz = 7,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad  = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ        CMD_INDEX_READ        //!< 0
+#define NOR_CMD_INDEX_READSTATUS  CMD_INDEX_READSTATUS  //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE   5                     //!< 5
+#define NOR_CMD_INDEX_DUMMY       6                     //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK  7                     //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK  8 //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex
new file mode 100644
index 000000000..7c44950ec
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex
@@ -0,0 +1,527 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1024-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="a558cc6e-82c2-41f9-9f55-0348efc7896f" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1024xxxxx</processor>
+      <package>MIMXRT1024DAG5A</package>
+      <board>MIMXRT1024-EVK</board>
+      <board_revision>B1</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="52" pin_signal="WAKEUP" label="USER_BUTTON" identifier="USER_BUTTON"/>
+               <pin_label pin_num="82" pin_signal="GPIO_AD_B1_08" label="UART_TX/USER_LED/J17[4]" identifier="USER_LED"/>
+            </pin_labels>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO5" signal="gpio_io, 00" pin_num="52" pin_signal="WAKEUP">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 24" pin_num="82" pin_signal="GPIO_AD_B1_08">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="142" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="141" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="140" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="139" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="138" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="136" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="137" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="133" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="132" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="131" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="143" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="130" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="129" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="2" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="1" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="7" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="127" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="126" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="3" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="8" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="4" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="128" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="125" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="9" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="117" pin_signal="GPIO_EMC_39"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="118" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="119" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="120" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="122" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="121" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="123" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="124" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="10" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="12" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="13" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="14" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="15" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="16" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="17" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="18" pin_signal="GPIO_EMC_00"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN1" description="Peripheral CAN1 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN1" signal="RX" pin_num="32" pin_signal="GPIO_SD_B1_01"/>
+                  <pin peripheral="CAN1" signal="TX" pin_num="33" pin_signal="GPIO_SD_B1_00"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="97" pin_signal="GPIO_AD_B0_11"/>
+                  <pin peripheral="GPIO1" signal="gpio_io, 22" pin_num="84" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="107" pin_signal="GPIO_AD_B0_04"/>
+                  <pin peripheral="ENET" signal="enet_tx_clk" pin_num="100" pin_signal="GPIO_AD_B0_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="95" pin_signal="GPIO_AD_B0_13"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="93" pin_signal="GPIO_AD_B0_15"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="94" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="96" pin_signal="GPIO_AD_B0_12"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="99" pin_signal="GPIO_AD_B0_09"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="98" pin_signal="GPIO_AD_B0_10"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="116" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="115" pin_signal="GPIO_EMC_41"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="GPIO3" signal="gpio_io, 19" pin_num="41" pin_signal="GPIO_SD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="24" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="23" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="21" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="22" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="25" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="19" pin_signal="GPIO_SD_B1_11"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL2_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.USDHC1_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM.USDHC2_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_ENABLE_CFG" value="Disabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG" value="Disabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>13.0.2</processor_version>
+            <output_format>c_array</output_format>
+         </dcdx_profile>
+         <dcdx_configurations>
+            <dcdx_configuration name="Device_configuration">
+               <description></description>
+               <options/>
+               <command_groups/>
+            </dcdx_configuration>
+         </dcdx_configurations>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="6d394465-bc9b-47f2-9a1f-3ca61f76d27b" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="NVIC" uuid="096e7e36-6917-481a-a4c5-06822cfc2da4" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="5dc935cc-5865-4d50-bac9-89ad440a12ee" type_id="system_54b53072540eeeb8f8e9343e71f28176">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="c2fe99b8-bf9b-437f-9446-a35000b06679" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="generic_uart" uuid="eca93ea1-cadf-4247-bfdc-08769ef8ed12" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="fdf82c69-a73f-4f32-9699-457260453bc6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="af80d7a8-d163-4a6f-839d-0ce2b15abffd" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="dca6ee55-a78d-4884-99bd-4f821b552213" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="4c34638b-b184-4e9d-8a81-5f3a1287180a" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>N/A</processor_version>
+         </tee_profile>
+      </tee>
+      <common name="common" version="1.0" enabled="true" update_project_code="true">
+         <core name="core0" role="primary" project_name="Project"/>
+      </common>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake
new file mode 100644
index 000000000..1aee75b0d
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MIMXRT1052)
+
+set(JLINK_DEVICE MIMXRT1052xxxxB)
+set(PYOCD_TARGET mimxrt1050)
+set(NXPLINK_DEVICE MIMXRT1052xxxxB:EVK-MIMXRT1050)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbimxrt1050_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1052DVL6B
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
index 0472f608c..de7ab0535 100644
--- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -24,28 +24,29 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: i.MX RT1050 Evaluation Kit revB
+   url: https://www.nxp.com/part/IMXRT1050-EVKB
+*/
 
-#ifndef BOARD_H_
-#define BOARD_H_
+#ifndef BOARD_MIMXRT1050_EVKB_H_
+#define BOARD_MIMXRT1050_EVKB_H_
 
-// required since iMX RT10xx SDK include this file for board size
+// required since iMXRT MCUX-SDK include this file for board size
 #define BOARD_FLASH_SIZE (0x4000000U)
 
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIO1
-#define LED_PIN               9
+// LED: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
+#define LED_PORT              BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN               BOARD_INITPINS_USER_LED_CHANNEL
 #define LED_STATE_ON          0
 
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
-#define BUTTON_PORT           GPIO5
-#define BUTTON_PIN            0
+// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_PERIPHERAL
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_CHANNEL
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
+// UART: IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
 #define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
 
-#endif /* BOARD_H_ */
+#endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
index 9fd229105..60aa1e28f 100644
--- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
@@ -1,6 +1,8 @@
 CFLAGS += -DCPU_MIMXRT1052DVL6B
 MCU_VARIANT = MIMXRT1052
 
+JLINK_DEVICE = MIMXRT1052xxxxB
+
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1050
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c
new file mode 100644
index 000000000..9738c6350
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c
@@ -0,0 +1,495 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1052xxxxB
+package_id: MIMXRT1052DVL6B
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: IMXRT1050-EVKB
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '40'}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 40,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
+#endif
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(40);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+    /* Backward compatibility for original bitfield name */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h
new file mode 100644
index 000000000..6b4264bf2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h
@@ -0,0 +1,119 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           160000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/pin_mux.c
new file mode 100644
index 000000000..aebfa5f46
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/pin_mux.c
@@ -0,0 +1,618 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1052xxxxB
+package_id: MIMXRT1052DVL6B
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: IMXRT1050-EVKB
+pin_labels:
+- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED}
+- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper}
+  - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up_100K_Ohm}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+  CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+  /* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */
+  GPIO_PinInit(GPIO1, 9U, &USER_LED_config);
+
+  /* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on WAKEUP (pin L6) */
+  GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U);
+  IOMUXC_SetPinConfig(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0x01B0A0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0x10B0U);
+#else
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0x10B0U);
+#else
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
+#endif
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSDRAMPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
+  - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
+  - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
+  - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
+  - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
+  - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
+  - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
+  - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
+  - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
+  - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
+  - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
+  - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
+  - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
+  - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
+  - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
+  - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
+  - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
+  - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
+  - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
+  - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
+  - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
+  - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
+  - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
+  - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
+  - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
+  - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
+  - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
+  - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
+  - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
+  - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
+  - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
+  - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
+  - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
+  - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
+  - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
+  - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
+  - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
+  - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
+  - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSDRAMPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSDRAMPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DA00, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DA01, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DA02, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DA03, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DA04, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DA05, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DA06, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DA07, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
+#endif
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DA08, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DA09, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DA10, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DA11, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DA12, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DA13, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DA14, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DA15, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
+#endif
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX0, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U);
+#endif
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCSIPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
+  - {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
+  - {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
+  - {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
+  - {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
+  - {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
+  - {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
+  - {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
+  - {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04}
+  - {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
+  - {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
+  - {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
+  - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCSIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCSIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLCDPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLCDPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitLCDPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCANPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
+  - {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCANPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCANPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitENETPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40}
+  - {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41}
+  - {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10}
+  - {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
+  - {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
+  - {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
+  - {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
+  - {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
+  - {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
+  - {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitENETPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitENETPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSDHCPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
+  - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
+  - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
+  - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
+  - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
+  - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSDHCPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUSDHCPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitHyperFlashPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
+  - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
+  - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
+  - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
+  - {pin_num: L5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA3, pin_signal: GPIO_SD_B1_00}
+  - {pin_num: M5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA2, pin_signal: GPIO_SD_B1_01}
+  - {pin_num: M3, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA1, pin_signal: GPIO_SD_B1_02}
+  - {pin_num: M4, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA0, pin_signal: GPIO_SD_B1_03}
+  - {pin_num: P2, peripheral: FLEXSPI, signal: FLEXSPI_B_SCLK, pin_signal: GPIO_SD_B1_04}
+  - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
+  - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
+  - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitHyperFlashPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitHyperFlashPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3, 0U);
+#else
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
+#endif
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/pin_mux.h
new file mode 100644
index 000000000..3d3a7a93c
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/pin_mux.h
@@ -0,0 +1,761 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO1   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                   gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                       9U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_GPIO                                       GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN                                      9U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                         (1U << 9U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_LED_PORT                                       GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_PIN                                           9U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_LED_PIN_MASK                              (1U << 9U)   /*!< PORT pin mask */
+
+/* WAKEUP (coord L6), SD_PWREN */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO5   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    0U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                    GPIO5   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN                                   0U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK                      (1U << 0U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_BUTTON_PORT                                    GPIO5   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_PIN                                        0U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_BUTTON_PIN_MASK                           (1U << 0U)   /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL                             TX   /*!< Signal name */
+
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL                             RX   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void);
+
+/* GPIO_EMC_09 (coord C2), SEMC_A0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL                                   0U   /*!< Signal channel */
+
+/* GPIO_EMC_10 (coord G1), SEMC_A1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL                                   1U   /*!< Signal channel */
+
+/* GPIO_EMC_11 (coord G3), SEMC_A2 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL                                   2U   /*!< Signal channel */
+
+/* GPIO_EMC_12 (coord H1), SEMC_A3 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL                                   3U   /*!< Signal channel */
+
+/* GPIO_EMC_13 (coord A6), SEMC_A4 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL                                   4U   /*!< Signal channel */
+
+/* GPIO_EMC_14 (coord B6), SEMC_A5 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL                                   5U   /*!< Signal channel */
+
+/* GPIO_EMC_15 (coord B1), SEMC_A6 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL                                   6U   /*!< Signal channel */
+
+/* GPIO_EMC_16 (coord A5), SEMC_A7 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL                                   7U   /*!< Signal channel */
+
+/* GPIO_EMC_17 (coord A4), SEMC_A8 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL                                   8U   /*!< Signal channel */
+
+/* GPIO_EMC_18 (coord B2), SEMC_A9 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL                                   9U   /*!< Signal channel */
+
+/* GPIO_EMC_23 (coord G2), SEMC_A10 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL                                 10U   /*!< Signal channel */
+
+/* GPIO_EMC_19 (coord B4), SEMC_A11 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL                                 11U   /*!< Signal channel */
+
+/* GPIO_EMC_20 (coord A3), SEMC_A12 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL                                 12U   /*!< Signal channel */
+
+/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL                                   BA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL                                   BA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_EMC_24 (coord D3), SEMC_CAS */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL                             semc_cas   /*!< Signal name */
+
+/* GPIO_EMC_27 (coord A2), SEMC_CKE */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL                             semc_cke   /*!< Signal name */
+
+/* GPIO_EMC_26 (coord B3), SEMC_CLK */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL                             semc_clk   /*!< Signal name */
+
+/* GPIO_EMC_00 (coord E3), SEMC_D0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL                                   0U   /*!< Signal channel */
+
+/* GPIO_EMC_01 (coord F3), SEMC_D1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL                                   1U   /*!< Signal channel */
+
+/* GPIO_EMC_02 (coord F4), SEMC_D2 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL                                   2U   /*!< Signal channel */
+
+/* GPIO_EMC_03 (coord G4), SEMC_D3 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL                                   3U   /*!< Signal channel */
+
+/* GPIO_EMC_04 (coord F2), SEMC_D4 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL                                   4U   /*!< Signal channel */
+
+/* GPIO_EMC_05 (coord G5), SEMC_D5 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL                                   5U   /*!< Signal channel */
+
+/* GPIO_EMC_06 (coord H5), SEMC_D6 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL                                   6U   /*!< Signal channel */
+
+/* GPIO_EMC_07 (coord H4), SEMC_D7 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL                                   7U   /*!< Signal channel */
+
+/* GPIO_EMC_30 (coord C6), SEMC_D8 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL                                   8U   /*!< Signal channel */
+
+/* GPIO_EMC_31 (coord C5), SEMC_D9 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL                                   9U   /*!< Signal channel */
+
+/* GPIO_EMC_32 (coord D5), SEMC_D10 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL                                 10U   /*!< Signal channel */
+
+/* GPIO_EMC_33 (coord C4), SEMC_D11 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL                                 11U   /*!< Signal channel */
+
+/* GPIO_EMC_34 (coord D4), SEMC_D12 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL                                 12U   /*!< Signal channel */
+
+/* GPIO_EMC_35 (coord E5), SEMC_D13 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL                                 13U   /*!< Signal channel */
+
+/* GPIO_EMC_36 (coord C3), SEMC_D14 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL                                 14U   /*!< Signal channel */
+
+/* GPIO_EMC_37 (coord E4), SEMC_D15 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL                                 15U   /*!< Signal channel */
+
+/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL                                   DM   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL                                   DM   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_EMC_25 (coord D2), SEMC_RAS */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL                             semc_ras   /*!< Signal name */
+
+/* GPIO_EMC_28 (coord D1), SEMC_WE */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL                               semc_we   /*!< Signal name */
+
+/* GPIO_EMC_41 (coord C7), ENET_MDIO */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_ENET_MDIO_PERIPHERAL                            SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_ENET_MDIO_SIGNAL                                 CSX   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_ENET_MDIO_CHANNEL                                 0U   /*!< Signal channel */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSDRAMPins(void);
+
+/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D9_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D9_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D9_CHANNEL                                      9U   /*!< Signal channel */
+
+/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D8_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D8_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D8_CHANNEL                                      8U   /*!< Signal channel */
+
+/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D7_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D7_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D7_CHANNEL                                      7U   /*!< Signal channel */
+
+/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D6_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D6_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D6_CHANNEL                                      6U   /*!< Signal channel */
+
+/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D5_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D5_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D5_CHANNEL                                      5U   /*!< Signal channel */
+
+/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D4_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D4_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D4_CHANNEL                                      4U   /*!< Signal channel */
+
+/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D2_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D2_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D2_CHANNEL                                      2U   /*!< Signal channel */
+
+/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D3_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D3_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D3_CHANNEL                                      3U   /*!< Signal channel */
+
+/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_PIXCLK_PERIPHERAL                              CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_PIXCLK_SIGNAL                           csi_pixclk   /*!< Signal name */
+
+/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_MCLK_PERIPHERAL                                CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_MCLK_SIGNAL                               csi_mclk   /*!< Signal name */
+
+/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_VSYNC_PERIPHERAL                               CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_VSYNC_SIGNAL                             csi_vsync   /*!< Signal name */
+
+/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_HSYNC_PERIPHERAL                               CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_HSYNC_SIGNAL                             csi_hsync   /*!< Signal name */
+
+/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_I2C_SCL_PERIPHERAL                          LPI2C1   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_I2C_SCL_SIGNAL                                 SCL   /*!< Signal name */
+
+/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_I2C_SDA_PERIPHERAL                          LPI2C1   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_I2C_SDA_SIGNAL                                 SDA   /*!< Signal name */
+
+/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_PWDN_PERIPHERAL                              GPIO1   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_PWDN_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_PWDN_CHANNEL                                    4U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITCSIPINS_CSI_PWDN_GPIO                                    GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN                                   4U   /*!< GPIO pin number */
+#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN_MASK                      (1U << 4U)   /*!< GPIO pin mask */
+#define BOARD_INITCSIPINS_CSI_PWDN_PORT                                    GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_PWDN_PIN                                        4U   /*!< PORT pin number */
+#define BOARD_INITCSIPINS_CSI_PWDN_PIN_MASK                           (1U << 4U)   /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCSIPins(void);
+
+/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D0_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D0_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D0_CHANNEL                                    0U   /*!< Signal channel */
+
+/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D1_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D1_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D1_CHANNEL                                    1U   /*!< Signal channel */
+
+/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D2_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D2_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D2_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_B0_00 (coord D7), LCDIF_CLK */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_CLK_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_CLK_SIGNAL                             lcdif_clk   /*!< Signal name */
+
+/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D3_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D3_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D3_CHANNEL                                    3U   /*!< Signal channel */
+
+/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D4_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D4_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D4_CHANNEL                                    4U   /*!< Signal channel */
+
+/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D5_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D5_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D5_CHANNEL                                    5U   /*!< Signal channel */
+
+/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D6_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D6_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D6_CHANNEL                                    6U   /*!< Signal channel */
+
+/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D7_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D7_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D7_CHANNEL                                    7U   /*!< Signal channel */
+
+/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D8_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D8_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D8_CHANNEL                                    8U   /*!< Signal channel */
+
+/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D9_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D9_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D9_CHANNEL                                    9U   /*!< Signal channel */
+
+/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D10_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D10_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D10_CHANNEL                                  10U   /*!< Signal channel */
+
+/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D11_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D11_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D11_CHANNEL                                  11U   /*!< Signal channel */
+
+/* GPIO_B1_00 (coord A11), LCDIF_D12 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D12_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D12_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D12_CHANNEL                                  12U   /*!< Signal channel */
+
+/* GPIO_B1_01 (coord B11), LCDIF_D13 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D13_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D13_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D13_CHANNEL                                  13U   /*!< Signal channel */
+
+/* GPIO_B1_02 (coord C11), LCDIF_D14 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D14_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D14_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D14_CHANNEL                                  14U   /*!< Signal channel */
+
+/* GPIO_B1_03 (coord D11), LCDIF_D15 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D15_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D15_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D15_CHANNEL                                  15U   /*!< Signal channel */
+
+/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_ENABLE_PERIPHERAL                          LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_ENABLE_SIGNAL                       lcdif_enable   /*!< Signal name */
+
+/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_HSYNC_PERIPHERAL                           LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_HSYNC_SIGNAL                         lcdif_hsync   /*!< Signal name */
+
+/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_VSYNC_PERIPHERAL                           LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_VSYNC_SIGNAL                         lcdif_vsync   /*!< Signal name */
+
+/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PERIPHERAL                         GPIO2   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_SIGNAL                           gpio_io   /*!< Signal name */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_CHANNEL                              31U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO                               GPIO2   /*!< GPIO peripheral base pointer */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN                             31U   /*!< GPIO pin number */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN_MASK                (1U << 31U)   /*!< GPIO pin mask */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PORT                               GPIO2   /*!< PORT peripheral base pointer */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN                                  31U   /*!< PORT pin number */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN_MASK                     (1U << 31U)   /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLCDPins(void);
+
+/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */
+/* Routed pin properties */
+#define BOARD_INITCANPINS_CAN2_TX_PERIPHERAL                                CAN2   /*!< Peripheral name */
+#define BOARD_INITCANPINS_CAN2_TX_SIGNAL                                      TX   /*!< Signal name */
+
+/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */
+/* Routed pin properties */
+#define BOARD_INITCANPINS_CAN2_RX_PERIPHERAL                                CAN2   /*!< Peripheral name */
+#define BOARD_INITCANPINS_CAN2_RX_SIGNAL                                      RX   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCANPins(void);
+
+/* GPIO_EMC_40 (coord A7), ENET_MDC */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL                              ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_MDC_SIGNAL                              enet_mdc   /*!< Signal name */
+
+/* GPIO_EMC_41 (coord C7), ENET_MDIO */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL                            enet_mdio   /*!< Signal name */
+
+/* GPIO_B1_10 (coord B13), ENET_TX_CLK */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL                           ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL                       enet_ref_clk   /*!< Signal name */
+
+/* GPIO_B1_04 (coord E12), ENET_RXD0 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL                         enet_rx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_B1_05 (coord D12), ENET_RXD1 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL                         enet_rx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_B1_06 (coord C12), ENET_CRS_DV */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL                           ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL                         enet_rx_en   /*!< Signal name */
+
+/* GPIO_B1_11 (coord C13), ENET_RXER */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXER_SIGNAL                           enet_rx_er   /*!< Signal name */
+
+/* GPIO_B1_07 (coord B12), ENET_TXD0 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL                         enet_tx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_B1_08 (coord A12), ENET_TXD1 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL                         enet_tx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_B1_09 (coord A13), ENET_TXEN */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL                           enet_tx_en   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitENETPins(void);
+
+/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL                                    3U   /*!< Signal channel */
+
+/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL                                    1U   /*!< Signal channel */
+
+/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL                                    0U   /*!< Signal channel */
+
+/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL                             usdhc_cmd   /*!< Signal name */
+
+/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL                             usdhc_clk   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSDHCPins(void);
+
+/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_PERIPHERAL                  FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_SIGNAL               FLEXSPI_A_SCLK   /*!< Signal name */
+
+/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_A_PERIPHERAL                 FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_A_SIGNAL             FLEXSPI_A_DATA2   /*!< Signal name */
+
+/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_A_PERIPHERAL                 FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_A_SIGNAL             FLEXSPI_A_DATA0   /*!< Signal name */
+
+/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_A_PERIPHERAL                 FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_A_SIGNAL             FLEXSPI_A_DATA1   /*!< Signal name */
+
+/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_B_PERIPHERAL                 FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_B_SIGNAL             FLEXSPI_B_DATA3   /*!< Signal name */
+
+/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_B_PERIPHERAL                 FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_B_SIGNAL             FLEXSPI_B_DATA2   /*!< Signal name */
+
+/* GPIO_SD_B1_02 (coord M3), FlexSPI_D1_B */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_B_PERIPHERAL                 FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_B_SIGNAL             FLEXSPI_B_DATA1   /*!< Signal name */
+
+/* GPIO_SD_B1_03 (coord M4), FlexSPI_D0_B */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_B_PERIPHERAL                 FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_B_SIGNAL             FLEXSPI_B_DATA0   /*!< Signal name */
+
+/* GPIO_SD_B1_04 (coord P2), FlexSPI_CLK_B */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_B_PERIPHERAL                FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_B_SIGNAL             FLEXSPI_B_SCLK   /*!< Signal name */
+
+/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_SS0_PERIPHERAL                  FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_SS0_SIGNAL              FLEXSPI_A_SS0_B   /*!< Signal name */
+
+/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_A_PERIPHERAL                 FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_A_SIGNAL             FLEXSPI_A_DATA3   /*!< Signal name */
+
+/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */
+/* Routed pin properties */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_DQS_PERIPHERAL                  FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITHYPERFLASHPINS_FlexSPI_DQS_SIGNAL                FLEXSPI_A_DQS   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitHyperFlashPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h
index fe40e7ed7..7a14360e4 100644
--- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h
@@ -19,7 +19,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -27,7 +27,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -125,7 +125,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -186,7 +186,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -254,7 +254,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex
new file mode 100644
index 000000000..6bdfd46a1
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex
@@ -0,0 +1,1033 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="IMXRT1050-EVKB" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="789fd1d3-821c-40a6-b04d-44ccc5a5d158" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1052xxxxB</processor>
+      <package>MIMXRT1052DVL6B</package>
+      <board>IMXRT1050-EVKB</board>
+      <board_revision>A</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="F14" pin_signal="GPIO_AD_B0_09" label="JTAG_TDI/J21[5]/ENET_RST/J22[5]" identifier="USER_LED"/>
+               <pin_label pin_num="L6" pin_signal="WAKEUP" label="SD_PWREN" identifier="USER_BUTTON"/>
+            </pin_labels>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO1" signal="gpio_io, 09" pin_num="F14" pin_signal="GPIO_AD_B0_09">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO5" signal="gpio_io, 00" pin_num="L6" pin_signal="WAKEUP">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="CSX, 0" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCSIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/>
+                  <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/>
+                  <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/>
+                  <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/>
+                  <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/>
+                  <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/>
+                  <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/>
+                  <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/>
+                  <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/>
+                  <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/>
+                  <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SCL"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SDA"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLCDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+                  <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitHyperFlashPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitHyperFlashPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitHyperFlashPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitHyperFlashPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA3" pin_num="L5" pin_signal="GPIO_SD_B1_00"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA2" pin_num="M5" pin_signal="GPIO_SD_B1_01"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA1" pin_num="M3" pin_signal="GPIO_SD_B1_02"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA0" pin_num="M4" pin_signal="GPIO_SD_B1_03"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_SCLK" pin_num="P2" pin_signal="GPIO_SD_B1_04"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="160 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM.PLL3_SW_CLK_SEL" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="40" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="a7525270-2da6-4556-8d91-4ab9d0edc0e2" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="cb1fcaec-81fe-4d3e-a079-a7d2819d6075" type="flexcan" type_id="flexcan_10d80efac19b25dcd240244aae88dca0" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="wakeupSrc" value="kFLEXCAN_WakeupSrcUnfiltered"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableTimerSync" value="true"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI" uuid="da865a46-3511-4001-8bb0-5249c52b0e4d" type="csi" type_id="csi_b2cf1faba8074e676ac4be93ec552c5a" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi" quick_selection="QuickSelection1">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected/>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="47051ef3-2c25-4648-8f79-4ae87cd12674" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="64741c26-6183-46d0-8bfe-02a92aa90e05" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD" uuid="8bf370a5-e797-45e8-b8c4-629c84c62843" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="2"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="687e3f12-1330-4ff9-8138-6aaf372d3e22" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="17c5d0d5-726a-40f6-a434-b121e9798a55" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="4a40b9b1-b64b-41b7-8ba7-728cda5039cd" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="c8d21d99-3f5e-47f2-aba7-0588ad4c2132" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="dfa0bda9-5863-49b3-9482-3ee85a2b93f0" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="3358d4d0-14d8-4ca7-9c13-378a0dc7f9a2" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="65c68c04-c4f4-4fbc-8c15-452d53d79fe6" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="99f59d06-c3df-407a-856a-22072ef95a98" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+      <common name="common" version="1.0" enabled="true" update_project_code="true">
+         <core name="core0" role="primary" project_name="Project"/>
+      </common>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
new file mode 100644
index 000000000..f70a5f923
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
@@ -0,0 +1,17 @@
+set(MCU_VARIANT MIMXRT1062)
+
+set(JLINK_DEVICE MIMXRT1062xxx6A)
+#set(JLINK_OPTION "-USB 000726129165")
+set(PYOCD_TARGET mimxrt1060)
+set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1060_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1062DVL6A
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
index 7fa37e33f..5bbacadaf 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -24,28 +24,29 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: i.MX RT1060 Evaluation Kit revB
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1060-EVKB
+*/
 
-#ifndef BOARD_H_
-#define BOARD_H_
+#ifndef BOARD_MIMXRT1060_EVKB_H_
+#define BOARD_MIMXRT1060_EVKB_H_
 
-// required since iMX RT10xx SDK include this file for board size
+// required since iMXRT MCUX-SDK include this file for board size
 #define BOARD_FLASH_SIZE (0x800000U)
 
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIO1
-#define LED_PIN               9
+// LED: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
+#define LED_PORT              BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN               BOARD_INITPINS_USER_LED_CHANNEL
 #define LED_STATE_ON          0
 
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
-#define BUTTON_PORT           GPIO5
-#define BUTTON_PIN            0
+// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_PERIPHERAL
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_CHANNEL
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
+// UART: IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_GPIO_AD_B0_12_LPUART1_TX
 #define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_13_LPUART1_RX
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_12_LPUART1_TX
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
 
-#endif /* BOARD_H_ */
+#endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
index d21063c99..0317ee452 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
@@ -7,8 +7,8 @@ JLINK_DEVICE = MIMXRT1062xxx6A
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1060
 
-BOARD_TUD_RHPORT = 1
-BOARD_TUH_RHPORT = 0
+BOARD_TUD_RHPORT = 0
+BOARD_TUH_RHPORT = 1
 
 # flash using pyocd
 flash: flash-pyocd
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c
new file mode 100644
index 000000000..c55e0135a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c
@@ -0,0 +1,509 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 31,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+    /* Disable Flexspi2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi2);
+    /* Set FLEXSPI2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+    /* Set Flexspi2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can3);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    CLOCK_DisableClock(kCLOCK_Can3S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Set Enet2 output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+    /* Enable Enet2 output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set ENET2 Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/pin_mux.c
new file mode 100644
index 000000000..5d679709e
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/pin_mux.c
@@ -0,0 +1,497 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+pin_labels:
+- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED}
+- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper}
+  - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+  CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+  /* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */
+  GPIO_PinInit(GPIO1, 9U, &USER_LED_config);
+
+  /* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on WAKEUP (pin L6) */
+  GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSDRAMPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
+  - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
+  - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
+  - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
+  - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
+  - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
+  - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
+  - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
+  - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
+  - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
+  - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
+  - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
+  - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
+  - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
+  - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
+  - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
+  - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
+  - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
+  - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
+  - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
+  - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
+  - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
+  - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
+  - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
+  - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
+  - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
+  - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
+  - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
+  - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
+  - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
+  - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
+  - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
+  - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
+  - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
+  - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
+  - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
+  - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
+  - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
+  - {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
+  - {pin_num: B7, peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_39}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSDRAMPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSDRAMPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCSIPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
+  - {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
+  - {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
+  - {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
+  - {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
+  - {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
+  - {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
+  - {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
+  - {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04}
+  - {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
+  - {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
+  - {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
+  - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCSIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCSIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U);
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(BOARD_INITCSIPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLCDPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow}
+  - {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLCDPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitLCDPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U);
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
+    );
+  IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 &
+    (~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCANPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
+  - {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCANPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCANPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitENETPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40}
+  - {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41}
+  - {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10}
+  - {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
+  - {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
+  - {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
+  - {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
+  - {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
+  - {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
+  - {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitENETPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitENETPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSDHCPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
+  - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
+  - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
+  - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
+  - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
+  - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
+  - {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSDHCPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUSDHCPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitQSPIPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
+  - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
+  - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
+  - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
+  - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
+  - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
+  - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitQSPIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitQSPIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/pin_mux.h
new file mode 100644
index 000000000..bf494b6f6
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/pin_mux.h
@@ -0,0 +1,744 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x0200U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
+
+/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO1   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                   gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                       9U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_GPIO                                       GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN                                      9U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                         (1U << 9U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_LED_PORT                                       GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_PIN                                           9U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_LED_PIN_MASK                              (1U << 9U)   /*!< PORT pin mask */
+
+/* WAKEUP (coord L6), SD_PWREN */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO5   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    0U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                    GPIO5   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN                                   0U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK                      (1U << 0U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_BUTTON_PORT                                    GPIO5   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_PIN                                        0U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_BUTTON_PIN_MASK                           (1U << 0U)   /*!< PORT pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL                             TX   /*!< Signal name */
+
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL                             RX   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void);
+
+/* GPIO_EMC_09 (coord C2), SEMC_A0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL                                   0U   /*!< Signal channel */
+
+/* GPIO_EMC_10 (coord G1), SEMC_A1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL                                   1U   /*!< Signal channel */
+
+/* GPIO_EMC_11 (coord G3), SEMC_A2 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL                                   2U   /*!< Signal channel */
+
+/* GPIO_EMC_12 (coord H1), SEMC_A3 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL                                   3U   /*!< Signal channel */
+
+/* GPIO_EMC_13 (coord A6), SEMC_A4 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL                                   4U   /*!< Signal channel */
+
+/* GPIO_EMC_14 (coord B6), SEMC_A5 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL                                   5U   /*!< Signal channel */
+
+/* GPIO_EMC_15 (coord B1), SEMC_A6 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL                                   6U   /*!< Signal channel */
+
+/* GPIO_EMC_16 (coord A5), SEMC_A7 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL                                   7U   /*!< Signal channel */
+
+/* GPIO_EMC_17 (coord A4), SEMC_A8 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL                                   8U   /*!< Signal channel */
+
+/* GPIO_EMC_18 (coord B2), SEMC_A9 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL                                   9U   /*!< Signal channel */
+
+/* GPIO_EMC_23 (coord G2), SEMC_A10 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL                                 10U   /*!< Signal channel */
+
+/* GPIO_EMC_19 (coord B4), SEMC_A11 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL                                 11U   /*!< Signal channel */
+
+/* GPIO_EMC_20 (coord A3), SEMC_A12 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL                                 12U   /*!< Signal channel */
+
+/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL                                   BA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL                                   BA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_EMC_24 (coord D3), SEMC_CAS */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL                             semc_cas   /*!< Signal name */
+
+/* GPIO_EMC_27 (coord A2), SEMC_CKE */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL                             semc_cke   /*!< Signal name */
+
+/* GPIO_EMC_26 (coord B3), SEMC_CLK */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL                             semc_clk   /*!< Signal name */
+
+/* GPIO_EMC_00 (coord E3), SEMC_D0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL                                   0U   /*!< Signal channel */
+
+/* GPIO_EMC_01 (coord F3), SEMC_D1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL                                   1U   /*!< Signal channel */
+
+/* GPIO_EMC_02 (coord F4), SEMC_D2 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL                                   2U   /*!< Signal channel */
+
+/* GPIO_EMC_03 (coord G4), SEMC_D3 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL                                   3U   /*!< Signal channel */
+
+/* GPIO_EMC_04 (coord F2), SEMC_D4 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL                                   4U   /*!< Signal channel */
+
+/* GPIO_EMC_05 (coord G5), SEMC_D5 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL                                   5U   /*!< Signal channel */
+
+/* GPIO_EMC_06 (coord H5), SEMC_D6 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL                                   6U   /*!< Signal channel */
+
+/* GPIO_EMC_07 (coord H4), SEMC_D7 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL                                   7U   /*!< Signal channel */
+
+/* GPIO_EMC_30 (coord C6), SEMC_D8 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL                                   8U   /*!< Signal channel */
+
+/* GPIO_EMC_31 (coord C5), SEMC_D9 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL                                   9U   /*!< Signal channel */
+
+/* GPIO_EMC_32 (coord D5), SEMC_D10 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL                                 10U   /*!< Signal channel */
+
+/* GPIO_EMC_33 (coord C4), SEMC_D11 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL                                 11U   /*!< Signal channel */
+
+/* GPIO_EMC_34 (coord D4), SEMC_D12 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL                                 12U   /*!< Signal channel */
+
+/* GPIO_EMC_35 (coord E5), SEMC_D13 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL                                 13U   /*!< Signal channel */
+
+/* GPIO_EMC_36 (coord C3), SEMC_D14 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL                                 14U   /*!< Signal channel */
+
+/* GPIO_EMC_37 (coord E4), SEMC_D15 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL                                 15U   /*!< Signal channel */
+
+/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL                                   DM   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL                                   DM   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_EMC_25 (coord D2), SEMC_RAS */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL                             semc_ras   /*!< Signal name */
+
+/* GPIO_EMC_28 (coord D1), SEMC_WE */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL                               semc_we   /*!< Signal name */
+
+/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_SIGNAL                                   CS   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_39 (coord B7), SEMC_DQS */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DQS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DQS_SIGNAL                             semc_dqs   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSDRAMPins(void);
+
+#define BOARD_INITCSIPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x10U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
+
+/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D9_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D9_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D9_CHANNEL                                      9U   /*!< Signal channel */
+
+/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D8_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D8_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D8_CHANNEL                                      8U   /*!< Signal channel */
+
+/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D7_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D7_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D7_CHANNEL                                      7U   /*!< Signal channel */
+
+/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D6_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D6_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D6_CHANNEL                                      6U   /*!< Signal channel */
+
+/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D5_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D5_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D5_CHANNEL                                      5U   /*!< Signal channel */
+
+/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D4_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D4_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D4_CHANNEL                                      4U   /*!< Signal channel */
+
+/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D2_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D2_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D2_CHANNEL                                      2U   /*!< Signal channel */
+
+/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D3_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D3_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D3_CHANNEL                                      3U   /*!< Signal channel */
+
+/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_PIXCLK_PERIPHERAL                              CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_PIXCLK_SIGNAL                           csi_pixclk   /*!< Signal name */
+
+/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_MCLK_PERIPHERAL                                CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_MCLK_SIGNAL                               csi_mclk   /*!< Signal name */
+
+/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_VSYNC_PERIPHERAL                               CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_VSYNC_SIGNAL                             csi_vsync   /*!< Signal name */
+
+/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_HSYNC_PERIPHERAL                               CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_HSYNC_SIGNAL                             csi_hsync   /*!< Signal name */
+
+/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_I2C_SCL_PERIPHERAL                          LPI2C1   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_I2C_SCL_SIGNAL                                 SCL   /*!< Signal name */
+
+/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_I2C_SDA_PERIPHERAL                          LPI2C1   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_I2C_SDA_SIGNAL                                 SDA   /*!< Signal name */
+
+/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_PWDN_PERIPHERAL                              GPIO1   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_PWDN_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_PWDN_CHANNEL                                    4U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITCSIPINS_CSI_PWDN_GPIO                                    GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN                                   4U   /*!< GPIO pin number */
+#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN_MASK                      (1U << 4U)   /*!< GPIO pin mask */
+#define BOARD_INITCSIPINS_CSI_PWDN_PORT                                    GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_PWDN_PIN                                        4U   /*!< PORT pin number */
+#define BOARD_INITCSIPINS_CSI_PWDN_PIN_MASK                           (1U << 4U)   /*!< PORT pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCSIPins(void);
+
+#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x04U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
+#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x80000000U /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */
+
+/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D0_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D0_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D0_CHANNEL                                    0U   /*!< Signal channel */
+
+/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D1_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D1_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D1_CHANNEL                                    1U   /*!< Signal channel */
+
+/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D2_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D2_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D2_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_B0_00 (coord D7), LCDIF_CLK */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_CLK_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_CLK_SIGNAL                             lcdif_clk   /*!< Signal name */
+
+/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D3_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D3_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D3_CHANNEL                                    3U   /*!< Signal channel */
+
+/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D4_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D4_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D4_CHANNEL                                    4U   /*!< Signal channel */
+
+/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D5_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D5_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D5_CHANNEL                                    5U   /*!< Signal channel */
+
+/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D6_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D6_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D6_CHANNEL                                    6U   /*!< Signal channel */
+
+/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D7_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D7_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D7_CHANNEL                                    7U   /*!< Signal channel */
+
+/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D8_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D8_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D8_CHANNEL                                    8U   /*!< Signal channel */
+
+/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D9_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D9_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D9_CHANNEL                                    9U   /*!< Signal channel */
+
+/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D10_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D10_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D10_CHANNEL                                  10U   /*!< Signal channel */
+
+/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D11_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D11_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D11_CHANNEL                                  11U   /*!< Signal channel */
+
+/* GPIO_B1_00 (coord A11), LCDIF_D12 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D12_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D12_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D12_CHANNEL                                  12U   /*!< Signal channel */
+
+/* GPIO_B1_01 (coord B11), LCDIF_D13 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D13_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D13_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D13_CHANNEL                                  13U   /*!< Signal channel */
+
+/* GPIO_B1_02 (coord C11), LCDIF_D14 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D14_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D14_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D14_CHANNEL                                  14U   /*!< Signal channel */
+
+/* GPIO_B1_03 (coord D11), LCDIF_D15 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D15_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D15_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D15_CHANNEL                                  15U   /*!< Signal channel */
+
+/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_ENABLE_PERIPHERAL                          LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_ENABLE_SIGNAL                       lcdif_enable   /*!< Signal name */
+
+/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_HSYNC_PERIPHERAL                           LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_HSYNC_SIGNAL                         lcdif_hsync   /*!< Signal name */
+
+/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_VSYNC_PERIPHERAL                           LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_VSYNC_SIGNAL                         lcdif_vsync   /*!< Signal name */
+
+/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PERIPHERAL                         GPIO2   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_SIGNAL                           gpio_io   /*!< Signal name */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_CHANNEL                              31U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO                               GPIO2   /*!< GPIO peripheral base pointer */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN                             31U   /*!< GPIO pin number */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN_MASK                (1U << 31U)   /*!< GPIO pin mask */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PORT                               GPIO2   /*!< PORT peripheral base pointer */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN                                  31U   /*!< PORT pin number */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN_MASK                     (1U << 31U)   /*!< PORT pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLCDPins(void);
+
+/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */
+/* Routed pin properties */
+#define BOARD_INITCANPINS_CAN2_TX_PERIPHERAL                                CAN2   /*!< Peripheral name */
+#define BOARD_INITCANPINS_CAN2_TX_SIGNAL                                      TX   /*!< Signal name */
+
+/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */
+/* Routed pin properties */
+#define BOARD_INITCANPINS_CAN2_RX_PERIPHERAL                                CAN2   /*!< Peripheral name */
+#define BOARD_INITCANPINS_CAN2_RX_SIGNAL                                      RX   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCANPins(void);
+
+/* GPIO_EMC_40 (coord A7), ENET_MDC */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL                              ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_MDC_SIGNAL                              enet_mdc   /*!< Signal name */
+
+/* GPIO_EMC_41 (coord C7), ENET_MDIO */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL                            enet_mdio   /*!< Signal name */
+
+/* GPIO_B1_10 (coord B13), ENET_TX_CLK */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL                           ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL                       enet_ref_clk   /*!< Signal name */
+
+/* GPIO_B1_04 (coord E12), ENET_RXD0 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL                         enet_rx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_B1_05 (coord D12), ENET_RXD1 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL                         enet_rx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_B1_06 (coord C12), ENET_CRS_DV */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL                           ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL                         enet_rx_en   /*!< Signal name */
+
+/* GPIO_B1_11 (coord C13), ENET_RXER */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXER_SIGNAL                           enet_rx_er   /*!< Signal name */
+
+/* GPIO_B1_07 (coord B12), ENET_TXD0 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL                         enet_tx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_B1_08 (coord A12), ENET_TXD1 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL                         enet_tx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_B1_09 (coord A13), ENET_TXEN */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL                           enet_tx_en   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitENETPins(void);
+
+/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL                                    3U   /*!< Signal channel */
+
+/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL                                    1U   /*!< Signal channel */
+
+/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL                                    0U   /*!< Signal channel */
+
+/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL                             usdhc_cmd   /*!< Signal name */
+
+/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL                             usdhc_clk   /*!< Signal name */
+
+/* GPIO_B1_14 (coord C14), SD0_VSELECT */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD0_VSELECT_PERIPHERAL                        USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD0_VSELECT_SIGNAL                     usdhc_vselect   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSDHCPins(void);
+
+/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL                   FLEXSPI_A_DATA0   /*!< Signal name */
+
+/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL                   FLEXSPI_A_DATA1   /*!< Signal name */
+
+/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL                   FLEXSPI_A_DATA2   /*!< Signal name */
+
+/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL                   FLEXSPI_A_DATA3   /*!< Signal name */
+
+/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL                     FLEXSPI_A_SCLK   /*!< Signal name */
+
+/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL                    FLEXSPI_A_SS0_B   /*!< Signal name */
+
+/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL                      FLEXSPI_A_DQS   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitQSPIPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h
index 28d7db57d..b4ef4ad4f 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex b/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex
new file mode 100644
index 000000000..b9353ba44
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex
@@ -0,0 +1,1032 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1060-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="2174caba-38fe-48d5-8f89-42a23354d23b" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1062xxxxA</processor>
+      <package>MIMXRT1062DVL6A</package>
+      <board>MIMXRT1060-EVK</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="F14" pin_signal="GPIO_AD_B0_09" label="JTAG_TDI/J21[5]/ENET_RST/J22[5]" identifier="USER_LED"/>
+               <pin_label pin_num="L6" pin_signal="WAKEUP" label="SD_PWREN" identifier="USER_BUTTON"/>
+            </pin_labels>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO1" signal="gpio_io, 09" pin_num="F14" pin_signal="GPIO_AD_B0_09">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO5" signal="gpio_io, 00" pin_num="L6" pin_signal="WAKEUP">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCSIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/>
+                  <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/>
+                  <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/>
+                  <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/>
+                  <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/>
+                  <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/>
+                  <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/>
+                  <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/>
+                  <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/>
+                  <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/>
+                  <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SCL"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SDA"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLCDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+                  <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="96c1cec6-3bd3-47a2-8301-f38e4b0dd25f" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="eb0900eb-d552-4097-9dcf-a07e592a887f" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI" uuid="f67d9a64-c26d-4421-9805-a062b24146f2" type="csi" type_id="csi_3739ec1355c7b915be929f3b7e35095b" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi" quick_selection="QuickSelection1">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected/>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="f2c6cd0a-751c-4424-9248-a4d98da47de7" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="01f250e2-83d7-4b7b-a98d-772d1c3bdb42" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD" uuid="90a0c31d-6042-4687-af0f-0892536bc1ba" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="3"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="b31fa225-2a52-486b-9c5c-33a184a2c716" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="aa3cc953-557b-4557-b7fe-6fedc31acf98" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="8b3f852e-ee1e-45e9-abff-0ff722f1d65d" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="539d282e-5136-4289-9058-9a46b221ca45" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="6e4c02c4-0524-4905-91b5-01d2e2502186" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="c6d8fd36-2bbd-44c6-a160-54e7e12d0807" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="7d3626d3-4536-4838-a35d-3b8cf5a2bd71" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="738ea8df-6176-4e52-b4c7-b88aa9c17d13" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake
new file mode 100644
index 000000000..cd75c5227
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MIMXRT1064)
+
+set(JLINK_DEVICE MIMXRT1064xxx6A)
+set(PYOCD_TARGET mimxrt1064)
+set(NXPLINK_DEVICE MIMXRT1064xxxxA:EVK-MIMXRT1064)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1064_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1064DVL6A
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
index 5f51e91a2..6dc01e3e7 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -24,29 +24,29 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: i.MX RT1064 Evaluation Kit
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1064-EVK
+*/
 
-#ifndef BOARD_H_
-#define BOARD_H_
+#ifndef BOARD_MIMXRT1064_EVKB_H_
+#define BOARD_MIMXRT1064_EVKB_H_
 
-// required since iMX RT10xx SDK include this file for board size
+// required since iMXRT MCUX-SDK include this file for board size
 #define BOARD_FLASH_SIZE (0x400000U)
 
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIO1
-#define LED_PIN               9
+// LED: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
+#define LED_PORT              BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN               BOARD_INITPINS_USER_LED_CHANNEL
 #define LED_STATE_ON          0
 
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
-#define BUTTON_PORT           GPIO5
-#define BUTTON_PIN            0
+// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_PERIPHERAL
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_CHANNEL
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
+// UART: IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_GPIO_AD_B0_12_LPUART1_TX
 #define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_13_LPUART1_RX
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_12_LPUART1_TX
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
 
-
-#endif /* BOARD_H_ */
+#endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
index 00b574c52..ddde419ae 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
@@ -7,8 +7,8 @@ JLINK_DEVICE = MIMXRT1064xxx6A
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1064
 
-BOARD_TUD_RHPORT = 1
-BOARD_TUH_RHPORT = 0
+BOARD_TUD_RHPORT = 0
+BOARD_TUH_RHPORT = 1
 
 # flash using pyocd
 flash: flash-pyocd
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
new file mode 100644
index 000000000..778ab02f2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
@@ -0,0 +1,511 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1064xxxxA
+package_id: MIMXRT1064DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1064-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD1_DIV.scale, value: '16', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 31,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+    /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi2);
+    /* Set FLEXSPI2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+    /* Set Flexspi2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+#endif
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can3);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    CLOCK_DisableClock(kCLOCK_Can3S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Set Enet2 output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+    /* Enable Enet2 output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set ENET2 Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c
new file mode 100644
index 000000000..8e975dc72
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c
@@ -0,0 +1,497 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1064xxxxA
+package_id: MIMXRT1064DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1064-EVK
+pin_labels:
+- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED}
+- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper}
+  - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+  CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+  /* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */
+  GPIO_PinInit(GPIO1, 9U, &USER_LED_config);
+
+  /* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on WAKEUP (pin L6) */
+  GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSDRAMPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
+  - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
+  - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
+  - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
+  - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
+  - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
+  - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
+  - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
+  - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
+  - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
+  - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
+  - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
+  - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
+  - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
+  - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
+  - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
+  - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
+  - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
+  - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
+  - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
+  - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
+  - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
+  - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
+  - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
+  - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
+  - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
+  - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
+  - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
+  - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
+  - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
+  - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
+  - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
+  - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
+  - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
+  - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
+  - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
+  - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
+  - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
+  - {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
+  - {pin_num: B7, peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_39}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSDRAMPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSDRAMPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCSIPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
+  - {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
+  - {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
+  - {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
+  - {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
+  - {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
+  - {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
+  - {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
+  - {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04}
+  - {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
+  - {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
+  - {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
+  - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCSIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCSIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U);
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(BOARD_INITCSIPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLCDPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+  - {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow}
+  - {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLCDPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitLCDPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U);
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
+    );
+  IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 &
+    (~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCANPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
+  - {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCANPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCANPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitENETPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40}
+  - {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41}
+  - {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10}
+  - {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
+  - {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
+  - {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
+  - {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
+  - {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
+  - {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
+  - {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitENETPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitENETPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSDHCPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
+  - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
+  - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
+  - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
+  - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
+  - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
+  - {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSDHCPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUSDHCPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitQSPIPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
+  - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
+  - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
+  - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
+  - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
+  - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
+  - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitQSPIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitQSPIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h
new file mode 100644
index 000000000..bf494b6f6
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h
@@ -0,0 +1,744 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x0200U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
+
+/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO1   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                   gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                       9U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_GPIO                                       GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN                                      9U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                         (1U << 9U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_LED_PORT                                       GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_PIN                                           9U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_LED_PIN_MASK                              (1U << 9U)   /*!< PORT pin mask */
+
+/* WAKEUP (coord L6), SD_PWREN */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO5   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    0U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                    GPIO5   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN                                   0U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK                      (1U << 0U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_BUTTON_PORT                                    GPIO5   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_PIN                                        0U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_BUTTON_PIN_MASK                           (1U << 0U)   /*!< PORT pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL                             TX   /*!< Signal name */
+
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL                             RX   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void);
+
+/* GPIO_EMC_09 (coord C2), SEMC_A0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL                                   0U   /*!< Signal channel */
+
+/* GPIO_EMC_10 (coord G1), SEMC_A1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL                                   1U   /*!< Signal channel */
+
+/* GPIO_EMC_11 (coord G3), SEMC_A2 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL                                   2U   /*!< Signal channel */
+
+/* GPIO_EMC_12 (coord H1), SEMC_A3 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL                                   3U   /*!< Signal channel */
+
+/* GPIO_EMC_13 (coord A6), SEMC_A4 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL                                   4U   /*!< Signal channel */
+
+/* GPIO_EMC_14 (coord B6), SEMC_A5 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL                                   5U   /*!< Signal channel */
+
+/* GPIO_EMC_15 (coord B1), SEMC_A6 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL                                   6U   /*!< Signal channel */
+
+/* GPIO_EMC_16 (coord A5), SEMC_A7 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL                                   7U   /*!< Signal channel */
+
+/* GPIO_EMC_17 (coord A4), SEMC_A8 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL                                   8U   /*!< Signal channel */
+
+/* GPIO_EMC_18 (coord B2), SEMC_A9 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL                                  ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL                                   9U   /*!< Signal channel */
+
+/* GPIO_EMC_23 (coord G2), SEMC_A10 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL                                 10U   /*!< Signal channel */
+
+/* GPIO_EMC_19 (coord B4), SEMC_A11 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL                                 11U   /*!< Signal channel */
+
+/* GPIO_EMC_20 (coord A3), SEMC_A12 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL                                 ADDR   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL                                 12U   /*!< Signal channel */
+
+/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL                                   BA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL                                   BA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_EMC_24 (coord D3), SEMC_CAS */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL                             semc_cas   /*!< Signal name */
+
+/* GPIO_EMC_27 (coord A2), SEMC_CKE */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL                             semc_cke   /*!< Signal name */
+
+/* GPIO_EMC_26 (coord B3), SEMC_CLK */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL                             semc_clk   /*!< Signal name */
+
+/* GPIO_EMC_00 (coord E3), SEMC_D0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL                                   0U   /*!< Signal channel */
+
+/* GPIO_EMC_01 (coord F3), SEMC_D1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL                                   1U   /*!< Signal channel */
+
+/* GPIO_EMC_02 (coord F4), SEMC_D2 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL                                   2U   /*!< Signal channel */
+
+/* GPIO_EMC_03 (coord G4), SEMC_D3 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL                                   3U   /*!< Signal channel */
+
+/* GPIO_EMC_04 (coord F2), SEMC_D4 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL                                   4U   /*!< Signal channel */
+
+/* GPIO_EMC_05 (coord G5), SEMC_D5 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL                                   5U   /*!< Signal channel */
+
+/* GPIO_EMC_06 (coord H5), SEMC_D6 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL                                   6U   /*!< Signal channel */
+
+/* GPIO_EMC_07 (coord H4), SEMC_D7 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL                                   7U   /*!< Signal channel */
+
+/* GPIO_EMC_30 (coord C6), SEMC_D8 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL                                   8U   /*!< Signal channel */
+
+/* GPIO_EMC_31 (coord C5), SEMC_D9 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL                                  DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL                                   9U   /*!< Signal channel */
+
+/* GPIO_EMC_32 (coord D5), SEMC_D10 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL                                 10U   /*!< Signal channel */
+
+/* GPIO_EMC_33 (coord C4), SEMC_D11 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL                                 11U   /*!< Signal channel */
+
+/* GPIO_EMC_34 (coord D4), SEMC_D12 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL                                 12U   /*!< Signal channel */
+
+/* GPIO_EMC_35 (coord E5), SEMC_D13 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL                                 13U   /*!< Signal channel */
+
+/* GPIO_EMC_36 (coord C3), SEMC_D14 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL                                 14U   /*!< Signal channel */
+
+/* GPIO_EMC_37 (coord E4), SEMC_D15 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL                                 DATA   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL                                 15U   /*!< Signal channel */
+
+/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL                                   DM   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL                                   DM   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_EMC_25 (coord D2), SEMC_RAS */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL                             semc_ras   /*!< Signal name */
+
+/* GPIO_EMC_28 (coord D1), SEMC_WE */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL                              SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL                               semc_we   /*!< Signal name */
+
+/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_SIGNAL                                   CS   /*!< Signal name */
+#define BOARD_INITSDRAMPINS_SEMC_CS0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_EMC_39 (coord B7), SEMC_DQS */
+/* Routed pin properties */
+#define BOARD_INITSDRAMPINS_SEMC_DQS_PERIPHERAL                             SEMC   /*!< Peripheral name */
+#define BOARD_INITSDRAMPINS_SEMC_DQS_SIGNAL                             semc_dqs   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSDRAMPins(void);
+
+#define BOARD_INITCSIPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x10U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
+
+/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D9_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D9_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D9_CHANNEL                                      9U   /*!< Signal channel */
+
+/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D8_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D8_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D8_CHANNEL                                      8U   /*!< Signal channel */
+
+/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D7_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D7_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D7_CHANNEL                                      7U   /*!< Signal channel */
+
+/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D6_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D6_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D6_CHANNEL                                      6U   /*!< Signal channel */
+
+/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D5_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D5_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D5_CHANNEL                                      5U   /*!< Signal channel */
+
+/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D4_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D4_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D4_CHANNEL                                      4U   /*!< Signal channel */
+
+/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D2_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D2_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D2_CHANNEL                                      2U   /*!< Signal channel */
+
+/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_D3_PERIPHERAL                                  CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_D3_SIGNAL                                 csi_data   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_D3_CHANNEL                                      3U   /*!< Signal channel */
+
+/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_PIXCLK_PERIPHERAL                              CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_PIXCLK_SIGNAL                           csi_pixclk   /*!< Signal name */
+
+/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_MCLK_PERIPHERAL                                CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_MCLK_SIGNAL                               csi_mclk   /*!< Signal name */
+
+/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_VSYNC_PERIPHERAL                               CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_VSYNC_SIGNAL                             csi_vsync   /*!< Signal name */
+
+/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_HSYNC_PERIPHERAL                               CSI   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_HSYNC_SIGNAL                             csi_hsync   /*!< Signal name */
+
+/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_I2C_SCL_PERIPHERAL                          LPI2C1   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_I2C_SCL_SIGNAL                                 SCL   /*!< Signal name */
+
+/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_I2C_SDA_PERIPHERAL                          LPI2C1   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_I2C_SDA_SIGNAL                                 SDA   /*!< Signal name */
+
+/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_PWDN_PERIPHERAL                              GPIO1   /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_PWDN_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_PWDN_CHANNEL                                    4U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITCSIPINS_CSI_PWDN_GPIO                                    GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN                                   4U   /*!< GPIO pin number */
+#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN_MASK                      (1U << 4U)   /*!< GPIO pin mask */
+#define BOARD_INITCSIPINS_CSI_PWDN_PORT                                    GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_PWDN_PIN                                        4U   /*!< PORT pin number */
+#define BOARD_INITCSIPINS_CSI_PWDN_PIN_MASK                           (1U << 4U)   /*!< PORT pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCSIPins(void);
+
+#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x04U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
+#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x80000000U /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */
+
+/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D0_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D0_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D0_CHANNEL                                    0U   /*!< Signal channel */
+
+/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D1_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D1_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D1_CHANNEL                                    1U   /*!< Signal channel */
+
+/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D2_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D2_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D2_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_B0_00 (coord D7), LCDIF_CLK */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_CLK_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_CLK_SIGNAL                             lcdif_clk   /*!< Signal name */
+
+/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D3_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D3_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D3_CHANNEL                                    3U   /*!< Signal channel */
+
+/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D4_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D4_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D4_CHANNEL                                    4U   /*!< Signal channel */
+
+/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D5_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D5_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D5_CHANNEL                                    5U   /*!< Signal channel */
+
+/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D6_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D6_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D6_CHANNEL                                    6U   /*!< Signal channel */
+
+/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D7_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D7_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D7_CHANNEL                                    7U   /*!< Signal channel */
+
+/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D8_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D8_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D8_CHANNEL                                    8U   /*!< Signal channel */
+
+/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D9_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D9_SIGNAL                             lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D9_CHANNEL                                    9U   /*!< Signal channel */
+
+/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D10_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D10_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D10_CHANNEL                                  10U   /*!< Signal channel */
+
+/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D11_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D11_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D11_CHANNEL                                  11U   /*!< Signal channel */
+
+/* GPIO_B1_00 (coord A11), LCDIF_D12 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D12_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D12_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D12_CHANNEL                                  12U   /*!< Signal channel */
+
+/* GPIO_B1_01 (coord B11), LCDIF_D13 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D13_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D13_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D13_CHANNEL                                  13U   /*!< Signal channel */
+
+/* GPIO_B1_02 (coord C11), LCDIF_D14 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D14_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D14_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D14_CHANNEL                                  14U   /*!< Signal channel */
+
+/* GPIO_B1_03 (coord D11), LCDIF_D15 */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_D15_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_D15_SIGNAL                            lcdif_data   /*!< Signal name */
+#define BOARD_INITLCDPINS_LCDIF_D15_CHANNEL                                  15U   /*!< Signal channel */
+
+/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_ENABLE_PERIPHERAL                          LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_ENABLE_SIGNAL                       lcdif_enable   /*!< Signal name */
+
+/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_HSYNC_PERIPHERAL                           LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_HSYNC_SIGNAL                         lcdif_hsync   /*!< Signal name */
+
+/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCDIF_VSYNC_PERIPHERAL                           LCDIF   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCDIF_VSYNC_SIGNAL                         lcdif_vsync   /*!< Signal name */
+
+/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PERIPHERAL                         GPIO2   /*!< Peripheral name */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_SIGNAL                           gpio_io   /*!< Signal name */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_CHANNEL                              31U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO                               GPIO2   /*!< GPIO peripheral base pointer */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN                             31U   /*!< GPIO pin number */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN_MASK                (1U << 31U)   /*!< GPIO pin mask */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PORT                               GPIO2   /*!< PORT peripheral base pointer */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN                                  31U   /*!< PORT pin number */
+#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN_MASK                     (1U << 31U)   /*!< PORT pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLCDPins(void);
+
+/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */
+/* Routed pin properties */
+#define BOARD_INITCANPINS_CAN2_TX_PERIPHERAL                                CAN2   /*!< Peripheral name */
+#define BOARD_INITCANPINS_CAN2_TX_SIGNAL                                      TX   /*!< Signal name */
+
+/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */
+/* Routed pin properties */
+#define BOARD_INITCANPINS_CAN2_RX_PERIPHERAL                                CAN2   /*!< Peripheral name */
+#define BOARD_INITCANPINS_CAN2_RX_SIGNAL                                      RX   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCANPins(void);
+
+/* GPIO_EMC_40 (coord A7), ENET_MDC */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL                              ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_MDC_SIGNAL                              enet_mdc   /*!< Signal name */
+
+/* GPIO_EMC_41 (coord C7), ENET_MDIO */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL                            enet_mdio   /*!< Signal name */
+
+/* GPIO_B1_10 (coord B13), ENET_TX_CLK */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL                           ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL                       enet_ref_clk   /*!< Signal name */
+
+/* GPIO_B1_04 (coord E12), ENET_RXD0 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL                         enet_rx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_B1_05 (coord D12), ENET_RXD1 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL                         enet_rx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_B1_06 (coord C12), ENET_CRS_DV */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL                           ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL                         enet_rx_en   /*!< Signal name */
+
+/* GPIO_B1_11 (coord C13), ENET_RXER */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_RXER_SIGNAL                           enet_rx_er   /*!< Signal name */
+
+/* GPIO_B1_07 (coord B12), ENET_TXD0 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL                         enet_tx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL                                  0U   /*!< Signal channel */
+
+/* GPIO_B1_08 (coord A12), ENET_TXD1 */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL                         enet_tx_data   /*!< Signal name */
+#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL                                  1U   /*!< Signal channel */
+
+/* GPIO_B1_09 (coord A13), ENET_TXEN */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL                             ENET   /*!< Peripheral name */
+#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL                           enet_tx_en   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitENETPins(void);
+
+/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL                                    3U   /*!< Signal channel */
+
+/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL                                    1U   /*!< Signal channel */
+
+/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL                                    0U   /*!< Signal channel */
+
+/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL                             usdhc_cmd   /*!< Signal name */
+
+/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL                             usdhc_clk   /*!< Signal name */
+
+/* GPIO_B1_14 (coord C14), SD0_VSELECT */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD0_VSELECT_PERIPHERAL                        USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD0_VSELECT_SIGNAL                     usdhc_vselect   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSDHCPins(void);
+
+/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL                   FLEXSPI_A_DATA0   /*!< Signal name */
+
+/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL                   FLEXSPI_A_DATA1   /*!< Signal name */
+
+/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL                   FLEXSPI_A_DATA2   /*!< Signal name */
+
+/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL                   FLEXSPI_A_DATA3   /*!< Signal name */
+
+/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL                     FLEXSPI_A_SCLK   /*!< Signal name */
+
+/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL                    FLEXSPI_A_SS0_B   /*!< Signal name */
+
+/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL                      FLEXSPI_A_DQS   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitQSPIPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.c
index bfb1c2d59..9d30f26bd 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.c
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.c
@@ -17,7 +17,7 @@
  ******************************************************************************/
 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
 #if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
-__attribute__((section(".boot_hdr.conf")))
+__attribute__((section(".boot_hdr.conf"), used))
 #elif defined(__ICCARM__)
 #pragma location = ".boot_hdr.conf"
 #endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h
index efdfe583f..995e88cb9 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
new file mode 100644
index 000000000..3f0948101
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
@@ -0,0 +1,1037 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1064-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="d75e55f6-68ab-46ef-814b-b94593af7f06" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1064xxxxA</processor>
+      <package>MIMXRT1064DVL6A</package>
+      <board>MIMXRT1064-EVK</board>
+      <board_revision>1</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="F14" pin_signal="GPIO_AD_B0_09" label="JTAG_TDI/J21[5]/ENET_RST/J22[5]" identifier="USER_LED"/>
+               <pin_label pin_num="L6" pin_signal="WAKEUP" label="SD_PWREN" identifier="USER_BUTTON"/>
+            </pin_labels>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO1" signal="gpio_io, 09" pin_num="F14" pin_signal="GPIO_AD_B0_09">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO5" signal="gpio_io, 00" pin_num="L6" pin_signal="WAKEUP">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCSIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/>
+                  <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/>
+                  <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/>
+                  <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/>
+                  <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/>
+                  <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/>
+                  <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/>
+                  <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/>
+                  <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/>
+                  <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/>
+                  <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SCL"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SDA"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLCDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+                  <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_DIV.scale" value="16" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="1c6563a6-c68b-40e5-8828-2853c99f95fa" called_from_default_init="true" id_prefix="BOARD_" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="e311ffe2-a68e-4ccc-bab1-c97e2207c5f0" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="7b69310c-fa35-4379-ac89-358df9280646" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_RGB565" uuid="ae342c96-df71-41a3-8419-3cccf201c91e" type="csi" type_id="csi_20660d007fd9c28a0b6ec615663d2939" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="BOARD_BootClockRUN"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected>
+                                 <id>kCSI_HsyncActiveHigh</id>
+                                 <id>kCSI_VsyncActiveLow</id>
+                              </selected>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="81411659-def5-4dbf-839a-d5e5f32dec0b" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD_RGB565" uuid="8c491814-4517-44d9-95de-844144e0c6b5" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="2"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="352dfcca-72ab-4214-bb68-9c1a927c4922" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="fe5e46a0-17b8-41e8-9cbc-ffb6f1cf78c1" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="f79f6878-69b5-4063-9007-0b8e509f7274" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="7ce8b24b-29e6-4b69-86e5-bdfd641cef44" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="ef6a8ae2-3961-4a05-a37f-d42a6a4d8a56" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="00a2a52b-0c40-4dbf-a6d0-5257cfc384e0" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="f30f7e21-6805-4236-9ab3-ff06a6013fa1" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="ea574324-8cc3-4da3-bdfc-2bdba0dfc3df" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake
new file mode 100644
index 000000000..d5629f8ba
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake
@@ -0,0 +1,26 @@
+set(MCU_VARIANT MIMXRT1176)
+
+if (M4 STREQUAL "1")
+  set(MCU_CORE _cm4)
+  set(JLINK_CORE _M4)
+  set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld)
+  set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+else ()
+  set(MCU_CORE _cm7)
+  set(JLINK_CORE _M7)
+endif()
+
+set(JLINK_DEVICE MIMXRT1176xxxA${JLINK_CORE})
+set(PYOCD_TARGET mimxrt1170${MCU_CORE})
+set(NXPLINK_DEVICE MIMXRT1176xxxxx:MIMXRT1170-EVK)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbmimxrt1170_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1176DVMAA${MCU_CORE}
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h
new file mode 100644
index 000000000..c5d54b7a7
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: i.MX RT1070 Evaluation Kit
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVKB
+*/
+
+#ifndef BOARD_MIMXRT1170_EVKB_H_
+#define BOARD_MIMXRT1170_EVKB_H_
+
+// required since iMXRT MCUX-SDK include this file for board size
+#define BOARD_FLASH_SIZE (0x1000000U)
+
+// LED: IOMUXC_GPIO_AD_04_GPIO9_IO03
+#define LED_PORT              BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN               BOARD_INITPINS_USER_LED_CHANNEL
+#define LED_STATE_ON          0
+
+// SW8 button: IOMUXC_WAKEUP_DIG_GPIO13_IO00
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_PERIPHERAL
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_CHANNEL
+#define BUTTON_STATE_ACTIVE   0
+
+// UART: IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_GPIO_AD_B0_12_LPUART1_TX
+#define UART_PORT             LPUART1
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT
+
+#endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk
new file mode 100644
index 000000000..8270ae587
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk
@@ -0,0 +1,25 @@
+MCU_VARIANT = MIMXRT1176
+
+ifeq ($(M4), 1)
+  MCU_CORE = _cm4
+  JLINK_CORE = _M4
+  CPU_CORE = cortex-m4
+  LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx${MCU_CORE}_ram.ld
+else
+  MCU_CORE = _cm7
+  JLINK_CORE = _M7
+endif
+
+CFLAGS += -DCPU_MIMXRT1176DVMAA$(MCU_CORE)
+
+# For flash-jlink target
+JLINK_DEVICE = MIMXRT1176xxxA$(JLINK_CORE)
+
+# For flash-pyocd target
+PYOCD_TARGET = mimxrt1170$(MCU_CORE)
+
+BOARD_TUD_RHPORT = 0
+BOARD_TUH_RHPORT = 1
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c
new file mode 100644
index 000000000..66f1f983a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c
@@ -0,0 +1,885 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v14.0
+processor: MIMXRT1176xxxxx
+package_id: MIMXRT1176DVMAA
+mcu_data: ksdk2_0
+processor_version: 16.3.0
+board: MIMXRT1170-EVKB
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+#include "fsl_dcdc.h"
+#include "fsl_pmu.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+/* This function should not run from SDRAM since it will change SEMC configuration. */
+AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void));
+void UpdateSemcClock(void)
+{
+    /* Enable self-refresh mode and update semc clock root to 200MHz. */
+    SEMC->IPCMD = 0xA55A000D;
+    while ((SEMC->INTR & 0x3) == 0)
+        ;
+    SEMC->INTR                                = 0x3;
+    SEMC->DCCR                                = 0x0B;
+    /*
+    * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only
+    * need to change the SEMC clock root here. If customer is using their own DCD and
+    * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be
+    * adjusted here to fine tune the SDRAM performance
+    */
+    CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602;
+}
+#endif
+#endif
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ARM_PLL_CLK.outFreq, value: 996 MHz}
+- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: AXI_CLK_ROOT.outFreq, value: 996 MHz}
+- {id: BUS_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz}
+- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
+- {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
+- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz}
+- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: M7_CLK_ROOT.outFreq, value: 996 MHz}
+- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
+- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
+- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MQS_MCLK.outFreq, value: 24 MHz}
+- {id: OSC_24M.outFreq, value: 24 MHz}
+- {id: OSC_32K.outFreq, value: 32.768 kHz}
+- {id: OSC_RC_16M.outFreq, value: 16 MHz}
+- {id: OSC_RC_400M.outFreq, value: 400 MHz}
+- {id: OSC_RC_48M.outFreq, value: 48 MHz}
+- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
+- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 24 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 24 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 24 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 24 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 24 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 24 MHz}
+- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI4_MCLK1.outFreq, value: 24 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
+- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
+- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
+- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
+- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
+- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
+- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
+- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
+- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
+- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
+- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
+settings:
+- {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
+- {id: SOCDomainVoltage, value: OD}
+- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
+- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
+- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
+- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
+- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
+- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
+- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
+- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
+- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
+- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
+- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
+- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
+- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
+- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
+- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
+- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
+- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
+- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
+- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
+- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
+- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
+- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'}
+- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
+- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
+- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
+- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
+- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
+- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+
+#ifndef SKIP_POWER_ADJUSTMENT
+#if __CORTEX_M == 7
+#define BYPASS_LDO_LPSR 1
+#define SKIP_LDO_ADJUSTMENT 1
+#elif __CORTEX_M == 4
+#define SKIP_DCDC_ADJUSTMENT 1
+#define SKIP_FBB_ENABLE 1
+#endif
+#endif
+
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .postDivider = kCLOCK_PllPostDiv2,        /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
+        .loopDivider = 166,                       /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
+    };
+
+const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
+    {
+        .mfd = 268435455,                         /* Denominator of spread spectrum */
+        .ss = NULL,                               /* Spread spectrum parameter */
+        .ssEnable = false,                        /* Enable spread spectrum or not */
+    };
+
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 41,                        /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
+        .postDivider = 0,                         /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
+        .numerator = 1,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 960000,                    /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .ss = NULL,                               /* Spread spectrum parameter */
+        .ssEnable = false,                        /* Enable spread spectrum or not */
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    clock_root_config_t rootCfg = {0};
+
+#if !defined(SKIP_DCDC_CONFIGURATION) || (!SKIP_DCDC_CONFIGURATION)
+    /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
+    DCDC_BootIntoDCM(DCDC);
+
+#if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT)
+    if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU))
+    {
+        DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
+    }
+    else
+    {
+        /* Set 1.125V for production samples to align with data sheet requirement */
+        DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
+    }
+#endif /* SKIP_DCDC_ADJUSTMENT */
+#endif /* SKIP_DCDC_CONFIGURATION */
+
+#if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
+    /* Check if FBB need to be enabled in OverDrive(OD) mode */
+    if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1)
+    {
+        PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
+    }
+    else
+    {
+        PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
+    }
+#endif
+
+#if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
+    PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
+    PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
+#endif
+
+#if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT)
+    pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
+    pmu_static_lpsr_dig_config_t lpsrDigConfig;
+
+    if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL)
+    {
+        PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
+        PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
+    }
+
+    if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL)
+    {
+        PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
+        lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
+        PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
+    }
+#endif
+
+    /* Config CLK_1M */
+    CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
+
+    /* Init OSC RC 16M */
+    ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
+
+    /* Init OSC RC 400M */
+    CLOCK_OSC_EnableOscRc400M();
+
+    /* Init OSC RC 48M */
+    CLOCK_OSC_EnableOsc48M(true);
+    CLOCK_OSC_EnableOsc48MDiv2(true);
+
+    /* Config OSC 24M */
+    ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
+    /* Wait for 24M OSC to be stable. */
+    while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
+            (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
+    {
+    }
+
+    /* Switch core M7 clock root to OscRC48MDiv2 first */
+#if __CORTEX_M == 7
+    rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+    /* Switch core M7 systick clock root to OscRC48MDiv2 first */
+#if __CORTEX_M == 7
+    rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+    /* Switch core M4 clock root to OscRC48MDiv2 first */
+#if __CORTEX_M == 4
+    rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
+#endif
+
+    /* Switch the Bus_Lpsr clock root to OscRC48MDiv2 first */
+#if __CORTEX_M == 4
+    rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
+#endif
+
+    /*
+    * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
+    */
+    /* Init Arm Pll. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+
+    /* Bypass Sys Pll1. */
+    CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
+
+    /* DeInit Sys Pll1. */
+    CLOCK_DeinitSysPll1();
+
+    /* Init Sys Pll2. */
+    CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
+
+    /* Init System Pll2 pfd0. */
+    CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
+
+    /* Init System Pll2 pfd1. */
+    CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
+
+    /* Init System Pll2 pfd2. */
+    CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
+
+    /* Init System Pll2 pfd3. */
+    CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
+
+    /* Init Sys Pll3. */
+    CLOCK_InitSysPll3();
+
+    /* Init System Pll3 pfd0. */
+    CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
+
+    /* Init System Pll3 pfd1. */
+    CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
+
+    /* Init System Pll3 pfd2. */
+    CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
+
+    /* Init System Pll3 pfd3. */
+    CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
+
+    /* Bypass Audio Pll. */
+    CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
+
+    /* DeInit Audio Pll. */
+    CLOCK_DeinitAudioPll();
+
+    /* Init Video Pll. */
+    CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
+
+    /* Module clock root configurations. */
+    /* Configure M7 using ARM_PLL_CLK */
+#if __CORTEX_M == 7
+    rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+    /* Configure M4 using SYS_PLL3_PFD3_CLK */
+#if __CORTEX_M == 4
+    rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
+#endif
+
+    /* Configure BUS using SYS_PLL3_CLK */
+    rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
+    rootCfg.div = 2;
+    CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
+
+    /* Configure BUS_LPSR using SYS_PLL3_CLK */
+    rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
+    rootCfg.div = 3;
+    CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
+
+    /* Configure SEMC using SYS_PLL2_PFD1_CLK */
+#ifndef SKIP_SEMC_INIT
+    rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
+    rootCfg.div = 3;
+    CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    UpdateSemcClock();
+#endif
+#endif
+
+    /* Configure CSSYS using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
+
+    /* Configure CSTRACE using SYS_PLL2_CLK */
+    rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
+    rootCfg.div = 4;
+    CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
+
+    /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
+#if __CORTEX_M == 4
+    rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
+#endif
+
+    /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
+#if __CORTEX_M == 7
+    rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 240;
+    CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+    /* Configure ADC1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
+
+    /* Configure ADC2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
+
+    /* Configure ACMP using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
+
+    /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
+
+    /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
+
+    /* Configure GPT1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
+
+    /* Configure GPT2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
+
+    /* Configure GPT3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
+
+    /* Configure GPT4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
+
+    /* Configure GPT5 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
+
+    /* Configure GPT6 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
+
+    /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
+    rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
+#endif
+
+    /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
+
+    /* Configure CAN1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
+
+    /* Configure CAN2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
+
+    /* Configure CAN3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
+
+    /* Configure LPUART1 using SYS_PLL2_CLK */
+    rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
+    rootCfg.div = 22;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
+
+    /* Configure LPUART2 using SYS_PLL2_CLK */
+    rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
+    rootCfg.div = 22;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
+
+    /* Configure LPUART3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
+
+    /* Configure LPUART4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
+
+    /* Configure LPUART5 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
+
+    /* Configure LPUART6 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
+
+    /* Configure LPUART7 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
+
+    /* Configure LPUART8 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
+
+    /* Configure LPUART9 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
+
+    /* Configure LPUART10 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
+
+    /* Configure LPUART11 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
+
+    /* Configure LPUART12 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
+
+    /* Configure LPI2C1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
+
+    /* Configure LPI2C2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
+
+    /* Configure LPI2C3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
+
+    /* Configure LPI2C4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
+
+    /* Configure LPI2C5 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
+
+    /* Configure LPI2C6 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
+
+    /* Configure LPSPI1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
+
+    /* Configure LPSPI2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
+
+    /* Configure LPSPI3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
+
+    /* Configure LPSPI4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
+
+    /* Configure LPSPI5 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
+
+    /* Configure LPSPI6 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
+
+    /* Configure EMV1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
+
+    /* Configure EMV2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
+
+    /* Configure ENET1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
+
+    /* Configure ENET2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
+
+    /* Configure ENET_QOS using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
+
+    /* Configure ENET_25M using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
+
+    /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
+
+    /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
+
+    /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
+
+    /* Configure USDHC1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
+
+    /* Configure USDHC2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
+
+    /* Configure ASRC using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
+
+    /* Configure MQS using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
+
+    /* Configure MIC using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
+
+    /* Configure SPDIF using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
+
+    /* Configure SAI1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
+
+    /* Configure SAI2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
+
+    /* Configure SAI3 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
+
+    /* Configure SAI4 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
+
+    /* Configure GC355 using PLL_VIDEO_CLK */
+    rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
+    rootCfg.div = 2;
+    CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
+
+    /* Configure LCDIF using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
+
+    /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
+
+    /* Configure MIPI_REF using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
+
+    /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
+
+    /* Configure CSI2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
+
+    /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
+
+    /* Configure CSI2_UI using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
+
+    /* Configure CSI using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
+
+    /* Configure CKO1 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
+
+    /* Configure CKO2 using OSC_RC_48M_DIV2 */
+    rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
+    rootCfg.div = 1;
+    CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
+
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
+    /* Set ENET_1G Tx clock source. */
+    IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
+    /* Set ENET_1G Ref clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
+    /* Set ENET_QOS Tx clock source. */
+    IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK;
+    /* Set ENET_QOS Ref clock source. */
+    IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
+    /* Set GPT3 High frequency reference clock source. */
+    IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
+    /* Set GPT4 High frequency reference clock source. */
+    IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
+    /* Set GPT5 High frequency reference clock source. */
+    IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
+    /* Set GPT6 High frequency reference clock source. */
+    IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
+
+#if __CORTEX_M == 7
+    SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
+#else
+    SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
+#endif
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h
new file mode 100644
index 000000000..f68724314
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h
@@ -0,0 +1,202 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U  /*!< Board xtal32k frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if __CORTEX_M == 7
+    #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */
+#else
+    #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */
+#endif
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT              24000000UL     /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */
+#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT              24000000UL     /* Clock consumers of ADC1_CLK_ROOT output : LPADC1 */
+#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT              24000000UL     /* Clock consumers of ADC2_CLK_ROOT output : LPADC2 */
+#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK                996000000UL    /* Clock consumers of ARM_PLL_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT              24000000UL     /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
+#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT               996000000UL    /* Clock consumers of AXI_CLK_ROOT output : FLEXRAM */
+#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT               240000000UL    /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IEE__IEE_RT1170, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
+#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT          160000000UL    /* Clock consumers of BUS_LPSR_CLK_ROOT output : CAN3, GPIO10, GPIO11, GPIO12, GPIO7, GPIO8, GPIO9, IOMUXC_LPSR, LPI2C5, LPI2C6, LPSPI5, LPSPI6, LPUART11, LPUART12, MUA, MUB, PDM, PIT2, RDC, RTWDOG4, SAI4, SNVS, XRDC2_D0, XRDC2_D1 */
+#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT              24000000UL     /* Clock consumers of CAN1_CLK_ROOT output : CAN1 */
+#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT              24000000UL     /* Clock consumers of CAN2_CLK_ROOT output : CAN2 */
+#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT              24000000UL     /* Clock consumers of CAN3_CLK_ROOT output : CAN3 */
+#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT         24000000UL     /* Clock consumers of CCM_CLKO1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT         24000000UL     /* Clock consumers of CCM_CLKO2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL      /* Clock consumers of CLK_1M output : EWM, RTWDOG3, RTWDOG4 */
+#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT              24000000UL     /* Clock consumers of CSI2_CLK_ROOT output : MIPI_CSI2RX */
+#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT          24000000UL     /* Clock consumers of CSI2_ESC_CLK_ROOT output : MIPI_CSI2RX */
+#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT           24000000UL     /* Clock consumers of CSI2_UI_CLK_ROOT output : MIPI_CSI2RX */
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               24000000UL     /* Clock consumers of CSI_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT             24000000UL     /* Clock consumers of CSSYS_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT           132000000UL    /* Clock consumers of CSTRACE_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT            24000000UL     /* Clock consumers of ELCDIF_CLK_ROOT output : LCDIF */
+#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT              24000000UL     /* Clock consumers of EMV1_CLK_ROOT output : EMVSIM1 */
+#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT              24000000UL     /* Clock consumers of EMV2_CLK_ROOT output : EMVSIM2 */
+#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT             24000000UL     /* Clock consumers of ENET1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT             24000000UL     /* Clock consumers of ENET2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK            0UL            /* Clock consumers of ENET_1G_REF_CLK output : ENET_1G */
+#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK             24000000UL     /* Clock consumers of ENET_1G_TX_CLK output : ENET_1G */
+#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT          24000000UL     /* Clock consumers of ENET_25M_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT          24000000UL     /* Clock consumers of ENET_QOS_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK           0UL            /* Clock consumers of ENET_QOS_REF_CLK output : ENET_QOS */
+#define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK            0UL            /* Clock consumers of ENET_QOS_TX_CLK output : ENET_QOS */
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL            /* Clock consumers of ENET_REF_CLK output : ENET */
+#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT       24000000UL     /* Clock consumers of ENET_TIMER1_CLK_ROOT output : ENET */
+#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT       24000000UL     /* Clock consumers of ENET_TIMER2_CLK_ROOT output : ENET_1G */
+#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT       24000000UL     /* Clock consumers of ENET_TIMER3_CLK_ROOT output : ENET_QOS */
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL            /* Clock consumers of ENET_TX_CLK output : ENET */
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           24000000UL     /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           24000000UL     /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT          24000000UL     /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          24000000UL     /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
+#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT             492000012UL    /* Clock consumers of GC355_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT              24000000UL     /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT1_ipg_clk_highfreq output : N/A */
+#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT              24000000UL     /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT2_ipg_clk_highfreq output : N/A */
+#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT              24000000UL     /* Clock consumers of GPT3_CLK_ROOT output : GPT3 */
+#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT3_ipg_clk_highfreq output : N/A */
+#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT              24000000UL     /* Clock consumers of GPT4_CLK_ROOT output : GPT4 */
+#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT4_ipg_clk_highfreq output : N/A */
+#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT              24000000UL     /* Clock consumers of GPT5_CLK_ROOT output : GPT5 */
+#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT5_ipg_clk_highfreq output : N/A */
+#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT              24000000UL     /* Clock consumers of GPT6_CLK_ROOT output : GPT6 */
+#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT6_ipg_clk_highfreq output : N/A */
+#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT           24000000UL     /* Clock consumers of LCDIFV2_CLK_ROOT output : LCDIFV2 */
+#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C1_CLK_ROOT output : LPI2C1 */
+#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C2_CLK_ROOT output : LPI2C2 */
+#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C3_CLK_ROOT output : LPI2C3 */
+#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C4_CLK_ROOT output : LPI2C4 */
+#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C5_CLK_ROOT output : LPI2C5 */
+#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C6_CLK_ROOT output : LPI2C6 */
+#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI1_CLK_ROOT output : LPSPI1 */
+#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI2_CLK_ROOT output : LPSPI2 */
+#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI3_CLK_ROOT output : LPSPI3 */
+#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI4_CLK_ROOT output : LPSPI4 */
+#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI5_CLK_ROOT output : LPSPI5 */
+#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI6_CLK_ROOT output : LPSPI6 */
+#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT          24000000UL     /* Clock consumers of LPUART10_CLK_ROOT output : LPUART10 */
+#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT          24000000UL     /* Clock consumers of LPUART11_CLK_ROOT output : LPUART11 */
+#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT          24000000UL     /* Clock consumers of LPUART12_CLK_ROOT output : LPUART12 */
+#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT           24000000UL     /* Clock consumers of LPUART1_CLK_ROOT output : LPUART1 */
+#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT           24000000UL     /* Clock consumers of LPUART2_CLK_ROOT output : LPUART2 */
+#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT           24000000UL     /* Clock consumers of LPUART3_CLK_ROOT output : LPUART3 */
+#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT           24000000UL     /* Clock consumers of LPUART4_CLK_ROOT output : LPUART4 */
+#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT           24000000UL     /* Clock consumers of LPUART5_CLK_ROOT output : LPUART5 */
+#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT           24000000UL     /* Clock consumers of LPUART6_CLK_ROOT output : LPUART6 */
+#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT           24000000UL     /* Clock consumers of LPUART7_CLK_ROOT output : LPUART7 */
+#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT           24000000UL     /* Clock consumers of LPUART8_CLK_ROOT output : LPUART8 */
+#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT           24000000UL     /* Clock consumers of LPUART9_CLK_ROOT output : LPUART9 */
+#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT                392727272UL    /* Clock consumers of M4_CLK_ROOT output : ARM, DMA1, DMAMUX1, SSARC_HP, SSARC_LP, XRDC2_D0, XRDC2_D1 */
+#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT        24000000UL     /* Clock consumers of M4_SYSTICK_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT                996000000UL    /* Clock consumers of M7_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT        100000UL       /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT               24000000UL     /* Clock consumers of MIC_CLK_ROOT output : ASRC, PDM, SPDIF */
+#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT   24000000UL     /* Clock consumers of MIPI_DSI_TX_CLK_ESC_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT          24000000UL     /* Clock consumers of MIPI_ESC_CLK_ROOT output : DSI_HOST */
+#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT          24000000UL     /* Clock consumers of MIPI_REF_CLK_ROOT output : DSI_HOST */
+#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT               24000000UL     /* Clock consumers of MQS_CLK_ROOT output : ASRC */
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   24000000UL     /* Clock consumers of MQS_MCLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_OSC_24M                    24000000UL     /* Clock consumers of OSC_24M output : SPDIF, TMPSNS, USBPHY1, USBPHY2 */
+#define BOARD_BOOTCLOCKRUN_OSC_32K                    32768UL        /* Clock consumers of OSC_32K output : GPIO13, RTWDOG3, RTWDOG4 */
+#define BOARD_BOOTCLOCKRUN_OSC_RC_16M                 16000000UL     /* Clock consumers of OSC_RC_16M output : CCM, DCDC, EWM, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6, SSARC_LP */
+#define BOARD_BOOTCLOCKRUN_OSC_RC_400M                400000000UL    /* Clock consumers of OSC_RC_400M output : N/A */
+#define BOARD_BOOTCLOCKRUN_OSC_RC_48M                 48000000UL     /* Clock consumers of OSC_RC_48M output : N/A */
+#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2            24000000UL     /* Clock consumers of OSC_RC_48M_DIV2 output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK              0UL            /* Clock consumers of PLL_AUDIO_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION    0UL            /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE         0UL            /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK              984000025UL    /* Clock consumers of PLL_VIDEO_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION    0UL            /* Clock consumers of PLL_VIDEO_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE         0UL            /* Clock consumers of PLL_VIDEO_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              24000000UL     /* Clock consumers of SAI1_CLK_ROOT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 24000000UL     /* Clock consumers of SAI1_MCLK1 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 0UL            /* Clock consumers of SAI1_MCLK2 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 24000000UL     /* Clock consumers of SAI1_MCLK3 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              24000000UL     /* Clock consumers of SAI2_CLK_ROOT output : ASRC */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 24000000UL     /* Clock consumers of SAI2_MCLK1 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL            /* Clock consumers of SAI2_MCLK2 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 24000000UL     /* Clock consumers of SAI2_MCLK3 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              24000000UL     /* Clock consumers of SAI3_CLK_ROOT output : ASRC, SPDIF */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 24000000UL     /* Clock consumers of SAI3_MCLK1 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL            /* Clock consumers of SAI3_MCLK2 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 24000000UL     /* Clock consumers of SAI3_MCLK3 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT              24000000UL     /* Clock consumers of SAI4_CLK_ROOT output : ASRC, SPDIF */
+#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1                 24000000UL     /* Clock consumers of SAI4_MCLK1 output : SAI4 */
+#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2                 0UL            /* Clock consumers of SAI4_MCLK2 output : SAI4 */
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              198000000UL    /* Clock consumers of SEMC_CLK_ROOT output : SEMC, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
+#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT             24000000UL     /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT           0UL            /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK               0UL            /* Clock consumers of SYS_PLL1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK          0UL            /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK          0UL            /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION     0UL            /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE          0UL            /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK               528000000UL    /* Clock consumers of SYS_PLL2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK          352000000UL    /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK          594000000UL    /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK          396000000UL    /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK          297000000UL    /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION     0UL            /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE          0UL            /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK               480000000UL    /* Clock consumers of SYS_PLL3_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK          240000000UL    /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK          664615384UL    /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK          508235294UL    /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK          270000000UL    /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK          392727272UL    /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            24000000UL     /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            24000000UL     /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c
new file mode 100644
index 000000000..2c83fb55e
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c
@@ -0,0 +1,126 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v16.0
+processor: MIMXRT1176xxxxx
+package_id: MIMXRT1176DVMAA
+mcu_data: ksdk2_0
+processor_version: 16.3.0
+board: MIMXRT1170-EVKB
+external_user_signals: {}
+pin_labels:
+- {pin_num: M13, pin_signal: GPIO_AD_04, label: 'SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]', identifier: SIM1_PD;LED;USER_LED}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
+- pin_list:
+  - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
+    open_drain: Disable, drive_strength: High, slew_rate: Slow}
+  - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
+    open_drain: Disable, drive_strength: High, slew_rate: Slow}
+  - {pin_num: M13, peripheral: GPIO9, signal: 'gpio_io, 03', pin_signal: GPIO_AD_04, identifier: USER_LED, direction: OUTPUT, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper}
+  - {pin_num: T8, peripheral: GPIO13, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core.
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* LPCG on: LPCG is ON. */
+
+  /* GPIO configuration of USER_LED on GPIO_AD_04 (pin M13) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_04 (pin M13) */
+  GPIO_PinInit(GPIO9, 3U, &USER_LED_config);
+
+  /* GPIO configuration of USER_BUTTON on WAKEUP_DIG (pin T8) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on WAKEUP_DIG (pin T8) */
+  GPIO_PinInit(GPIO13, 0U, &USER_BUTTON_config);
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_04_GPIO9_IO03,           /* GPIO_AD_04 is configured as GPIO9_IO03 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_24_LPUART1_TXD,          /* GPIO_AD_24 is configured as LPUART1_TXD */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_25_LPUART1_RXD,          /* GPIO_AD_25 is configured as LPUART1_RXD */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_WAKEUP_DIG_GPIO13_IO00,          /* WAKEUP_DIG is configured as GPIO13_IO00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_AD_04_GPIO9_IO03,           /* GPIO_AD_04 PAD functional properties : */
+      0x02U);                                 /* Slew Rate Field: Slow Slew Rate
+                                                 Drive Strength Field: high drive strength
+                                                 Pull / Keep Select Field: Pull Disable
+                                                 Pull Up / Down Config. Field: Weak pull down
+                                                 Open Drain Field: Disabled
+                                                 Domain write protection: Both cores are allowed
+                                                 Domain write protection lock: Neither of DWP bits is locked */
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_AD_24_LPUART1_TXD,          /* GPIO_AD_24 PAD functional properties : */
+      0x02U);                                 /* Slew Rate Field: Slow Slew Rate
+                                                 Drive Strength Field: high drive strength
+                                                 Pull / Keep Select Field: Pull Disable
+                                                 Pull Up / Down Config. Field: Weak pull down
+                                                 Open Drain Field: Disabled
+                                                 Domain write protection: Both cores are allowed
+                                                 Domain write protection lock: Neither of DWP bits is locked */
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_AD_25_LPUART1_RXD,          /* GPIO_AD_25 PAD functional properties : */
+      0x02U);                                 /* Slew Rate Field: Slow Slew Rate
+                                                 Drive Strength Field: high drive strength
+                                                 Pull / Keep Select Field: Pull Disable
+                                                 Pull Up / Down Config. Field: Weak pull down
+                                                 Open Drain Field: Disabled
+                                                 Domain write protection: Both cores are allowed
+                                                 Domain write protection lock: Neither of DWP bits is locked */
+  IOMUXC_SetPinConfig(
+      IOMUXC_WAKEUP_DIG_GPIO13_IO00,          /* WAKEUP_DIG PAD functional properties : */
+      0x0EU);                                 /* Pull / Keep Select Field: Pull Enable
+                                                 Pull Up / Down Config. Field: Weak pull up
+                                                 Open Drain SNVS Field: Disabled
+                                                 Domain write protection: Both cores are allowed
+                                                 Domain write protection lock: Neither of DWP bits is locked */
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h
new file mode 100644
index 000000000..a5b621476
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h
@@ -0,0 +1,77 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* GPIO_AD_25 (coord M15), LPUART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_LPUART1_RXD_PERIPHERAL                            LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_LPUART1_RXD_SIGNAL                                    RXD   /*!< Signal name */
+
+/* GPIO_AD_24 (coord L13), LPUART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_LPUART1_TXD_PERIPHERAL                            LPUART1   /*!< Peripheral name */
+#define BOARD_INITPINS_LPUART1_TXD_SIGNAL                                    TXD   /*!< Signal name */
+
+/* GPIO_AD_04 (coord M13), SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO9   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                   gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                       3U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_GPIO                                       GPIO9   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN                                      3U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                         (1U << 3U)   /*!< GPIO pin mask */
+
+/* WAKEUP (coord T8), USER_BUTTON/SW7 */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                             GPIO13   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    0U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                   GPIO13   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN                                   0U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK                      (1U << 0U)   /*!< GPIO pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);                    /* Function assigned for the Cortex-M7F */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/evkbmimxrt1170_flexspi_nor_config.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/evkbmimxrt1170_flexspi_nor_config.c
new file mode 100644
index 000000000..0425cb2cb
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/evkbmimxrt1170_flexspi_nor_config.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2018-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkbmimxrt1170_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig =
+        {
+            .tag              = FLEXSPI_CFG_BLK_TAG,
+            .version          = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+            .csHoldTime       = 3u,
+            .csSetupTime      = 3u,
+            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
+            .controllerMiscOption = 0x10,
+            .deviceType           = kFlexSpiDeviceType_SerialNOR,
+            .sflashPadType        = kSerialFlash_4Pads,
+            .serialClkFreq        = kFlexSpiSerialClk_133MHz,
+            .sflashA1Size         = 64u * 1024u * 1024u,
+            .lookupTable =
+                {
+                    // Read LUTs
+                    [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20),
+                    [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+
+                    // Read Status LUTs
+                    [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
+
+                    // Write Enable LUTs
+                    [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
+
+                    // Erase Sector LUTs
+                    [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20),
+
+                    // Erase Block LUTs
+                    [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),
+
+                    // Pape Program LUTs
+                    [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x12, RADDR_SDR, FLEXSPI_1PAD, 0x20),
+                    [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
+
+                    // Erase Chip LUTs
+                    [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
+                },
+        },
+    .pageSize           = 256u,
+    .sectorSize         = 4u * 1024u,
+    .ipcmdSerialClkFreq = 0x1,
+    .blockSize          = 64u * 1024u,
+    .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/evkbmimxrt1170_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/evkbmimxrt1170_flexspi_nor_config.h
new file mode 100644
index 000000000..839bb78f5
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/evkbmimxrt1170_flexspi_nor_config.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright 2018-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.1. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* FLEXSPI memory config block related definitions */
+#define FLEXSPI_CFG_BLK_TAG     (0x42464346UL) // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE    (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related definitions */
+#define CMD_INDEX_READ        0
+#define CMD_INDEX_READSTATUS  1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE       4
+
+#define CMD_LUT_SEQ_IDX_READ        0
+#define CMD_LUT_SEQ_IDX_READSTATUS  1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE       9
+
+#define CMD_SDR        0x01
+#define CMD_DDR        0x21
+#define RADDR_SDR      0x02
+#define RADDR_DDR      0x22
+#define CADDR_SDR      0x03
+#define CADDR_DDR      0x23
+#define MODE1_SDR      0x04
+#define MODE1_DDR      0x24
+#define MODE2_SDR      0x05
+#define MODE2_DDR      0x25
+#define MODE4_SDR      0x06
+#define MODE4_DDR      0x26
+#define MODE8_SDR      0x07
+#define MODE8_DDR      0x27
+#define WRITE_SDR      0x08
+#define WRITE_DDR      0x28
+#define READ_SDR       0x09
+#define READ_DDR       0x29
+#define LEARN_SDR      0x0A
+#define LEARN_DDR      0x2A
+#define DATSZ_SDR      0x0B
+#define DATSZ_DDR      0x2B
+#define DUMMY_SDR      0x0C
+#define DUMMY_DDR      0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS      0x1F
+#define STOP           0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_80MHz  = 4,
+    kFlexSpiSerialClk_100MHz = 5,
+    kFlexSpiSerialClk_120MHz = 6,
+    kFlexSpiSerialClk_133MHz = 7,
+    kFlexSpiSerialClk_166MHz = 8,
+    kFlexSpiSerialClk_200MHz = 9,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad  = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ        CMD_INDEX_READ        //!< 0
+#define NOR_CMD_INDEX_READSTATUS  CMD_INDEX_READSTATUS  //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE   5                     //!< 5
+#define NOR_CMD_INDEX_DUMMY       6                     //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK  7                     //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK  8 //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t isDataOrderSwapped;     //!< The data order is swapped in OPI DDR mode
+    uint8_t reserved0;              //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t FlashStateCtx;         //!< Flash State Context after being configured
+    uint32_t reserve2[10];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex
new file mode 100644
index 000000000..a4c8917f7
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex
@@ -0,0 +1,661 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_16 http://mcuxpresso.nxp.com/XSD/mex_configuration_16.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="16" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_16" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1176xxxxx</processor>
+      <package>MIMXRT1176DVMAA</package>
+      <board>MIMXRT1170-EVKB</board>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="cm7">
+         <core name="Cortex-M4F" id="cm4" description=""/>
+         <core name="Cortex-M7F" id="cm7" description=""/>
+      </cores>
+      <description>Configuration imported from evkbmimxrt1170_dev_cdc_vcom_lite_bm_cm7</description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="16.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>16.3.0</processor_version>
+            <pin_labels>
+               <pin_label pin_num="M13" pin_signal="GPIO_AD_04" label="SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]" identifier="SIM1_PD;LED;USER_LED"/>
+            </pin_labels>
+            <external_user_signals>
+               <properties/>
+            </external_user_signals>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm7</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RXD" pin_num="M15" pin_signal="GPIO_AD_25">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="drive_strength" value="High"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="TXD" pin_num="L13" pin_signal="GPIO_AD_24">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="drive_strength" value="High"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO9" signal="gpio_io, 03" pin_num="M13" pin_signal="GPIO_AD_04">
+                     <pin_features>
+                        <pin_feature name="identifier" value="USER_LED"/>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO13" signal="gpio_io, 00" pin_num="T8" pin_signal="WAKEUP">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="14.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>16.3.0</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="&apos;XTALI&apos; (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="&apos;XTALI&apos; (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="&apos;XTALO&apos; (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="&apos;XTALO&apos; (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm4">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm4">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm4">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm4">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm4">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources/>
+               <clock_outputs>
+                  <clock_output id="ACMP_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ADC1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ADC2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ARM_PLL_CLK.outFreq" value="996 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ASRC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="AXI_CLK_ROOT.outFreq" value="996 MHz" locked="false" accuracy=""/>
+                  <clock_output id="BUS_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/>
+                  <clock_output id="BUS_LPSR_CLK_ROOT.outFreq" value="160 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CCM_CLKO1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CCM_CLKO2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI2_ESC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI2_UI_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSSYS_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSTRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ELCDIF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="EMV1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="EMV2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_1G_TX_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_QOS_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_TIMER1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_TIMER2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_TIMER3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GC355_CLK_ROOT.outFreq" value="492.0000125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT3_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT4_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT5_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT6_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIFV2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART10_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART11_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART12_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART7_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART8_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPUART9_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="M4_CLK_ROOT.outFreq" value="4320/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="M4_SYSTICK_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="M7_CLK_ROOT.outFreq" value="996 MHz" locked="false" accuracy=""/>
+                  <clock_output id="M7_SYSTICK_CLK_ROOT.outFreq" value="100 kHz" locked="false" accuracy=""/>
+                  <clock_output id="MIC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MIPI_DSI_TX_CLK_ESC_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MIPI_ESC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MIPI_REF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="OSC_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="OSC_32K.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="OSC_RC_16M.outFreq" value="16 MHz" locked="false" accuracy=""/>
+                  <clock_output id="OSC_RC_400M.outFreq" value="400 MHz" locked="false" accuracy=""/>
+                  <clock_output id="OSC_RC_48M.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="OSC_RC_48M_DIV2.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL_VIDEO_CLK.outFreq" value="984.000025 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI4_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL2_CLK.outFreq" value="528 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL2_PFD0_CLK.outFreq" value="352 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL2_PFD1_CLK.outFreq" value="594 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL2_PFD2_CLK.outFreq" value="396 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL2_PFD3_CLK.outFreq" value="297 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL3_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL3_DIV2_CLK.outFreq" value="240 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL3_PFD0_CLK.outFreq" value="8640/13 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL3_PFD1_CLK.outFreq" value="8640/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL3_PFD2_CLK.outFreq" value="270 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYS_PLL3_PFD3_CLK.outFreq" value="4320/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CoreBusClockRootsInitializationConfig" value="selectedCore" locked="false"/>
+                  <setting id="SOCDomainVoltage" value="OD" locked="false"/>
+                  <setting id="ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG" value="Low" locked="false"/>
+                  <setting id="ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG" value="Enabled" locked="false"/>
+                  <setting id="ANADIG_PLL.PLL_AUDIO_BYPASS.sel" value="ANADIG_OSC.OSC_24M" locked="false"/>
+                  <setting id="ANADIG_PLL.PLL_VIDEO.denom" value="960000" locked="false"/>
+                  <setting id="ANADIG_PLL.PLL_VIDEO.div" value="41" locked="false"/>
+                  <setting id="ANADIG_PLL.PLL_VIDEO.num" value="1" locked="false"/>
+                  <setting id="ANADIG_PLL.SYS_PLL1_BYPASS.sel" value="ANADIG_OSC.OSC_24M" locked="false"/>
+                  <setting id="ANADIG_PLL.SYS_PLL2.denom" value="268435455" locked="false"/>
+                  <setting id="ANADIG_PLL.SYS_PLL2.div" value="22" locked="false"/>
+                  <setting id="ANADIG_PLL.SYS_PLL2.num" value="0" locked="false"/>
+                  <setting id="ANADIG_PLL.SYS_PLL2_SS_DIV.scale" value="268435455" locked="false"/>
+                  <setting id="ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale" value="22" locked="true"/>
+                  <setting id="ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG" value="Enabled" locked="false"/>
+                  <setting id="ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG" value="Disabled" locked="false"/>
+                  <setting id="ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG" value="Enabled" locked="false"/>
+                  <setting id="ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG" value="Disabled" locked="false"/>
+                  <setting id="ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG" value="Disabled" locked="false"/>
+                  <setting id="ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG" value="Enabled" locked="false"/>
+                  <setting id="ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG" value="Enabled" locked="false"/>
+                  <setting id="ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT0.MUX.sel" value="ANADIG_PLL.ARM_PLL_CLK" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT1.MUX.sel" value="ANADIG_PLL.SYS_PLL3_PFD3_CLK" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT2.DIV.scale" value="2" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT2.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT25.DIV.scale" value="22" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT25.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT26.DIV.scale" value="22" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT26.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT3.DIV.scale" value="3" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT3.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT4.DIV.scale" value="3" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT4.MUX.sel" value="ANADIG_PLL.SYS_PLL2_PFD1_CLK" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT6.DIV.scale" value="4" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT6.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT68.DIV.scale" value="2" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT68.MUX.sel" value="ANADIG_PLL.PLL_VIDEO_CLK" locked="false"/>
+                  <setting id="CCM.CLOCK_ROOT8.DIV.scale" value="240" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>13.0.2</processor_version>
+            <output_format>c_array</output_format>
+         </dcdx_profile>
+         <dcdx_configurations>
+            <dcdx_configuration name="Device_configuration">
+               <description></description>
+               <options/>
+               <command_groups>
+                  <command_group name="Imported Commands" enabled="true">
+                     <commands>
+                        <command type="write_value" address="CCM_CLOCK_ROOT4_CONTROL" value="0x703" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39" value="0x10" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17" value="0x00" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16" value="0x08" value_width="4"/>
+                        <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17" value="0x08" value_width="4"/>
+                        <command type="write_value" address="SEMC_MCR" value="0x10000004" value_width="4"/>
+                        <command type="write_value" address="SEMC_BMCR0" value="0x81" value_width="4"/>
+                        <command type="write_value" address="SEMC_BMCR1" value="0x81" value_width="4"/>
+                        <command type="write_value" address="SEMC_BR0" value="0x8000001D" value_width="4"/>
+                        <command type="write_value" address="SEMC_SDRAMCR0" value="0xF32" value_width="4"/>
+                        <command type="write_value" address="SEMC_SDRAMCR1" value="0x772A22" value_width="4"/>
+                        <command type="write_value" address="SEMC_SDRAMCR2" value="0x10A0D" value_width="4"/>
+                        <command type="write_value" address="SEMC_SDRAMCR3" value="0x21210408" value_width="4"/>
+                        <command type="write_value" address="SEMC_IPCR0" value="0x80000000" value_width="4"/>
+                        <command type="write_value" address="SEMC_IPCR1" value="0x02" value_width="4"/>
+                        <command type="write_value" address="SEMC_IPCR2" value="0x00" value_width="4"/>
+                        <command type="write_value" address="SEMC_IPCMD" value="0xA55A000F" value_width="4"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/>
+                        <command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/>
+                        <command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/>
+                        <command type="write_value" address="SEMC_IPTXDAT" value="0x33" value_width="4"/>
+                        <command type="write_value" address="SEMC_IPCMD" value="0xA55A000A" value_width="4"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="nop"/>
+                        <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/>
+                        <command type="write_value" address="SEMC_SDRAMCR3" value="0x21210409" value_width="4"/>
+                     </commands>
+                  </command_group>
+               </command_groups>
+            </dcdx_configuration>
+         </dcdx_configurations>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <dependencies>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="LPUART Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="Unsupported version of the LPUART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.5.1</data>
+               </feature>
+            </dependency>
+         </dependencies>
+         <generated_project_files/>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="5580249f-8696-4d01-87fa-efd84baaea95" called_from_default_init="true" id_prefix="" core="cm7">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="ClockOutput" resourceId="LPUART1_CLK_ROOT" description="LPUART1 clock root is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_tx" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_rx" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <instances>
+                  <instance name="NVIC" uuid="27e59fb2-3864-4b83-bf0e-a683a8582c73" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+                  <instance name="LPUART1" uuid="78f9b1b2-5105-4480-a25a-29d8172b6270" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="cd2726b0-9595-440c-9375-bb6a010a1d55" type_id="system_54b53072540eeeb8f8e9343e71f28176">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="2491c39d-c21a-45f3-a984-57be0f6a77b5" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="fefc514e-ed7f-48ad-a874-de332dd5eb13" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="1dc54607-ada6-4731-ad75-479a19616c00" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="88660053-1bc1-49b8-884c-a12532e98a7a" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="9d37100d-c1fb-4f7e-b235-a952c5b03275" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="ad9ccf5d-6535-4f75-bb23-abb7e6fcc950" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>N/A</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/teensy_40/board.cmake b/hw/bsp/imxrt/boards/teensy_40/board.cmake
new file mode 100644
index 000000000..41fdc78f5
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MIMXRT1062)
+
+set(JLINK_DEVICE MIMXRT1062xxx6A)
+set(PYOCD_TARGET mimxrt1060)
+set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/teensy40_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1062DVL6A
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
+
+# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
+# Make sure it is in your PATH
+# flash: $(BUILD)/$(PROJECT).hex
+# teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_40/board.h b/hw/bsp/imxrt/boards/teensy_40/board.h
index b3cc0a8c5..ae749e894 100644
--- a/hw/bsp/imxrt/boards/teensy_40/board.h
+++ b/hw/bsp/imxrt/boards/teensy_40/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -24,29 +24,29 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Teensy 4.0
+   url: https://www.pjrc.com/store/teensy40.html
+*/
 
 #ifndef BOARD_H_
 #define BOARD_H_
 
-
-// required since iMX RT10xx SDK include this file for board size
+// required since iMXRT MCUX-SDK include this file for board size
 #define BOARD_FLASH_SIZE (2 * 1024 * 1024)
 
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_B0_03_GPIO2_IO03 // D13
-#define LED_PORT              GPIO2
-#define LED_PIN               3
+// LED D13: IOMUXC_GPIO_B0_03_GPIO2_IO03
+#define LED_PORT              BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN               BOARD_INITPINS_USER_LED_CHANNEL
 #define LED_STATE_ON          0
 
-// no button
-#define BUTTON_PINMUX         IOMUXC_GPIO_B0_01_GPIO2_IO01 // D12
-#define BUTTON_PORT           GPIO2
-#define BUTTON_PIN            1
+// no button D12: IOMUXC_GPIO_B0_01_GPIO2_IO01
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_PERIPHERAL
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_CHANNEL
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
+// UART D0, D1: IOMUXC_GPIO_AD_B0_03_LPUART6_RX, IOMUXC_GPIO_AD_B0_02_LPUART6_TX
 #define UART_PORT             LPUART6
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_03_LPUART6_RX  // D0
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_02_LPUART6_TX  // D1
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
 
 #endif /* BOARD_H_ */
diff --git a/hw/bsp/imxrt/boards/teensy_40/board.mk b/hw/bsp/imxrt/boards/teensy_40/board.mk
index 0ad5ea5c0..45ca0fb6e 100644
--- a/hw/bsp/imxrt/boards/teensy_40/board.mk
+++ b/hw/bsp/imxrt/boards/teensy_40/board.mk
@@ -5,6 +5,6 @@ MCU_VARIANT = MIMXRT1062
 JLINK_DEVICE = MIMXRT1062xxx6A
 
 # flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
-# Make sure it is in your PATH 
+# Make sure it is in your PATH
 flash: $(BUILD)/$(PROJECT).hex
 	teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c
new file mode 100644
index 000000000..c55e0135a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c
@@ -0,0 +1,509 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 31,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+    /* Disable Flexspi2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi2);
+    /* Set FLEXSPI2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+    /* Set Flexspi2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can3);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    CLOCK_DisableClock(kCLOCK_Can3S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Set Enet2 output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+    /* Enable Enet2 output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set ENET2 Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/teensy_40/board/pin_mux.c b/hw/bsp/imxrt/boards/teensy_40/board/pin_mux.c
new file mode 100644
index 000000000..4c16be993
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board/pin_mux.c
@@ -0,0 +1,181 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+pin_labels:
+- {pin_num: E7, pin_signal: GPIO_B0_01, label: LCDIF_ENABLE, identifier: USER_BUTTON}
+- {pin_num: D8, pin_signal: GPIO_B0_03, label: LCDIF_VSYNC, identifier: USER_LED}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: D8, peripheral: GPIO2, signal: 'gpio_io, 03', pin_signal: GPIO_B0_03, direction: OUTPUT}
+  - {pin_num: E7, peripheral: GPIO2, signal: 'gpio_io, 01', pin_signal: GPIO_B0_01, direction: INPUT, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  /* GPIO configuration of USER_BUTTON on GPIO_B0_01 (pin E7) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_B0_01 (pin E7) */
+  GPIO_PinInit(GPIO2, 1U, &USER_BUTTON_config);
+
+  /* GPIO configuration of USER_LED on GPIO_B0_03 (pin D8) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_B0_03 (pin D8) */
+  GPIO_PinInit(GPIO2, 3U, &USER_LED_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_GPIO2_IO01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_GPIO2_IO03, 0U);
+  IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 &
+    (~(BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_GPIO2_IO01, 0xB0B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSDHCPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
+  - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
+  - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
+  - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
+  - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
+  - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
+  - {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSDHCPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUSDHCPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitQSPIPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
+  - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
+  - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
+  - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
+  - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
+  - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
+  - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitQSPIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitQSPIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/teensy_40/board/pin_mux.h b/hw/bsp/imxrt/boards/teensy_40/board/pin_mux.h
new file mode 100644
index 000000000..f31f91598
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board/pin_mux.h
@@ -0,0 +1,189 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x0AU /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */
+
+/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO2   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                   gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                       3U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_GPIO                                       GPIO2   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN                                      3U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                         (1U << 3U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_LED_PORT                                       GPIO2   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_PIN                                           3U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_LED_PIN_MASK                              (1U << 3U)   /*!< PORT pin mask */
+
+/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO2   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    1U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                    GPIO2   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN                                   1U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK                      (1U << 1U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_BUTTON_PORT                                    GPIO2   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_PIN                                        1U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_BUTTON_PIN_MASK                           (1U << 1U)   /*!< PORT pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL                             TX   /*!< Signal name */
+
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL                             RX   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void);
+
+/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL                                    3U   /*!< Signal channel */
+
+/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL                                    1U   /*!< Signal channel */
+
+/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL                                    0U   /*!< Signal channel */
+
+/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL                             usdhc_cmd   /*!< Signal name */
+
+/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL                             usdhc_clk   /*!< Signal name */
+
+/* GPIO_B1_14 (coord C14), SD0_VSELECT */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD0_VSELECT_PERIPHERAL                        USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD0_VSELECT_SIGNAL                     usdhc_vselect   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSDHCPins(void);
+
+/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL                   FLEXSPI_A_DATA0   /*!< Signal name */
+
+/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL                   FLEXSPI_A_DATA1   /*!< Signal name */
+
+/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL                   FLEXSPI_A_DATA2   /*!< Signal name */
+
+/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL                   FLEXSPI_A_DATA3   /*!< Signal name */
+
+/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL                     FLEXSPI_A_SCLK   /*!< Signal name */
+
+/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL                    FLEXSPI_A_SS0_B   /*!< Signal name */
+
+/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL                      FLEXSPI_A_DQS   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitQSPIPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/teensy_40/teensy40.mex b/hw/bsp/imxrt/boards/teensy_40/teensy40.mex
new file mode 100644
index 000000000..1ade853ae
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/teensy40.mex
@@ -0,0 +1,651 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1060-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="2174caba-38fe-48d5-8f89-42a23354d23b" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1062xxxxA</processor>
+      <package>MIMXRT1062DVL6A</package>
+      <board>MIMXRT1060-EVK</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="E7" pin_signal="GPIO_B0_01" label="LCDIF_ENABLE" identifier="USER_BUTTON"/>
+               <pin_label pin_num="D8" pin_signal="GPIO_B0_03" label="LCDIF_VSYNC" identifier="USER_LED"/>
+            </pin_labels>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO2" signal="gpio_io, 03" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 01" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="96c1cec6-3bd3-47a2-8301-f38e4b0dd25f" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="eb0900eb-d552-4097-9dcf-a07e592a887f" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI" uuid="f67d9a64-c26d-4421-9805-a062b24146f2" type="csi" type_id="csi_3739ec1355c7b915be929f3b7e35095b" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi" quick_selection="QuickSelection1">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected/>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="f2c6cd0a-751c-4424-9248-a4d98da47de7" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="01f250e2-83d7-4b7b-a98d-772d1c3bdb42" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD" uuid="90a0c31d-6042-4687-af0f-0892536bc1ba" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="3"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="b31fa225-2a52-486b-9c5c-33a184a2c716" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="aa3cc953-557b-4557-b7fe-6fedc31acf98" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="8b3f852e-ee1e-45e9-abff-0ff722f1d65d" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="539d282e-5136-4289-9058-9a46b221ca45" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="6e4c02c4-0524-4905-91b5-01d2e2502186" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="c6d8fd36-2bbd-44c6-a160-54e7e12d0807" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="7d3626d3-4536-4838-a35d-3b8cf5a2bd71" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="738ea8df-6176-4e52-b4c7-b88aa9c17d13" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
index 7929906eb..dbedc90a0 100644
--- a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
+++ b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h>
+#include "teensy40_flexspi_nor_config.h"
 
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
diff --git a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h
index 56068ec6a..d24d4f10a 100644
--- a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.cmake b/hw/bsp/imxrt/boards/teensy_41/board.cmake
new file mode 100644
index 000000000..0fd8d528e
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MIMXRT1062)
+
+set(JLINK_DEVICE MIMXRT1062xxx6A)
+set(PYOCD_TARGET mimxrt1060)
+set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/teensy41_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1062DVL6A
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
+
+# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
+# Make sure it is in your PATH
+# flash: $(BUILD)/$(PROJECT).hex
+# teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.h b/hw/bsp/imxrt/boards/teensy_41/board.h
index b0b4931c7..1bc022c54 100644
--- a/hw/bsp/imxrt/boards/teensy_41/board.h
+++ b/hw/bsp/imxrt/boards/teensy_41/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -24,29 +24,29 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Teensy 4.1
+   url: https://www.pjrc.com/store/teensy41.html
+*/
 
 #ifndef BOARD_H_
 #define BOARD_H_
 
-
-// required since iMX RT10xx SDK include this file for board size
+// required since iMXRT MCUX-SDK include this file for board size
 #define BOARD_FLASH_SIZE (8 * 1024 * 1024)
 
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_B0_03_GPIO2_IO03 // D13
-#define LED_PORT              GPIO2
-#define LED_PIN               3
+// LED D13: IOMUXC_GPIO_B0_03_GPIO2_IO03
+#define LED_PORT              BOARD_INITPINS_USER_LED_PERIPHERAL
+#define LED_PIN               BOARD_INITPINS_USER_LED_CHANNEL
 #define LED_STATE_ON          0
 
-// no button
-#define BUTTON_PINMUX         IOMUXC_GPIO_B0_01_GPIO2_IO01 // D12
-#define BUTTON_PORT           GPIO2
-#define BUTTON_PIN            1
+// no button D12: IOMUXC_GPIO_B0_01_GPIO2_IO01
+#define BUTTON_PORT           BOARD_INITPINS_USER_BUTTON_PERIPHERAL
+#define BUTTON_PIN            BOARD_INITPINS_USER_BUTTON_CHANNEL
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
+// UART D0, D1: IOMUXC_GPIO_AD_B0_03_LPUART6_RX, IOMUXC_GPIO_AD_B0_02_LPUART6_TX
 #define UART_PORT             LPUART6
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_03_LPUART6_RX  // D0
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_02_LPUART6_TX  // D1
+#define UART_CLK_ROOT         BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
 
 #endif /* BOARD_H_ */
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.mk b/hw/bsp/imxrt/boards/teensy_41/board.mk
index 0ad5ea5c0..45ca0fb6e 100644
--- a/hw/bsp/imxrt/boards/teensy_41/board.mk
+++ b/hw/bsp/imxrt/boards/teensy_41/board.mk
@@ -5,6 +5,6 @@ MCU_VARIANT = MIMXRT1062
 JLINK_DEVICE = MIMXRT1062xxx6A
 
 # flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
-# Make sure it is in your PATH 
+# Make sure it is in your PATH
 flash: $(BUILD)/$(PROJECT).hex
 	teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c
new file mode 100644
index 000000000..c55e0135a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c
@@ -0,0 +1,509 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 31,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+    /* Disable Flexspi2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi2);
+    /* Set FLEXSPI2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+    /* Set Flexspi2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can3);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    CLOCK_DisableClock(kCLOCK_Can3S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Set Enet2 output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+    /* Enable Enet2 output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set ENET2 Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/teensy_41/board/pin_mux.c b/hw/bsp/imxrt/boards/teensy_41/board/pin_mux.c
new file mode 100644
index 000000000..4c16be993
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board/pin_mux.c
@@ -0,0 +1,181 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+pin_labels:
+- {pin_num: E7, pin_signal: GPIO_B0_01, label: LCDIF_ENABLE, identifier: USER_BUTTON}
+- {pin_num: D8, pin_signal: GPIO_B0_03, label: LCDIF_VSYNC, identifier: USER_LED}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: D8, peripheral: GPIO2, signal: 'gpio_io, 03', pin_signal: GPIO_B0_03, direction: OUTPUT}
+  - {pin_num: E7, peripheral: GPIO2, signal: 'gpio_io, 01', pin_signal: GPIO_B0_01, direction: INPUT, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  /* GPIO configuration of USER_BUTTON on GPIO_B0_01 (pin E7) */
+  gpio_pin_config_t USER_BUTTON_config = {
+      .direction = kGPIO_DigitalInput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_B0_01 (pin E7) */
+  GPIO_PinInit(GPIO2, 1U, &USER_BUTTON_config);
+
+  /* GPIO configuration of USER_LED on GPIO_B0_03 (pin D8) */
+  gpio_pin_config_t USER_LED_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 0U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_B0_03 (pin D8) */
+  GPIO_PinInit(GPIO2, 3U, &USER_LED_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_GPIO2_IO01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_GPIO2_IO03, 0U);
+  IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 &
+    (~(BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)))
+      | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U)
+    );
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_GPIO2_IO01, 0xB0B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
+    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSDHCPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
+  - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
+  - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
+  - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
+  - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
+  - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
+  - {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSDHCPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUSDHCPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitQSPIPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
+  - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
+  - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
+  - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
+  - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
+  - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
+  - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitQSPIPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitQSPIPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/teensy_41/board/pin_mux.h b/hw/bsp/imxrt/boards/teensy_41/board/pin_mux.h
new file mode 100644
index 000000000..f31f91598
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board/pin_mux.h
@@ -0,0 +1,189 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x0AU /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */
+
+/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO2   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_SIGNAL                                   gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CHANNEL                                       3U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_GPIO                                       GPIO2   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN                                      3U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                         (1U << 3U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_LED_PORT                                       GPIO2   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_PIN                                           3U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_LED_PIN_MASK                              (1U << 3U)   /*!< PORT pin mask */
+
+/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO2   /*!< Peripheral name */
+#define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
+#define BOARD_INITPINS_USER_BUTTON_CHANNEL                                    1U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_BUTTON_GPIO                                    GPIO2   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN                                   1U   /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK                      (1U << 1U)   /*!< GPIO pin mask */
+#define BOARD_INITPINS_USER_BUTTON_PORT                                    GPIO2   /*!< PORT peripheral base pointer */
+#define BOARD_INITPINS_USER_BUTTON_PIN                                        1U   /*!< PORT pin number */
+#define BOARD_INITPINS_USER_BUTTON_PIN_MASK                           (1U << 1U)   /*!< PORT pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL                             TX   /*!< Signal name */
+
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL                             RX   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void);
+
+/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL                                    3U   /*!< Signal channel */
+
+/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL                                    2U   /*!< Signal channel */
+
+/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL                                    1U   /*!< Signal channel */
+
+/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL                             USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL                             usdhc_data   /*!< Signal name */
+#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL                                    0U   /*!< Signal channel */
+
+/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL                             usdhc_cmd   /*!< Signal name */
+
+/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL                            USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL                             usdhc_clk   /*!< Signal name */
+
+/* GPIO_B1_14 (coord C14), SD0_VSELECT */
+/* Routed pin properties */
+#define BOARD_INITUSDHCPINS_SD0_VSELECT_PERIPHERAL                        USDHC1   /*!< Peripheral name */
+#define BOARD_INITUSDHCPINS_SD0_VSELECT_SIGNAL                     usdhc_vselect   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSDHCPins(void);
+
+/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL                   FLEXSPI_A_DATA0   /*!< Signal name */
+
+/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL                   FLEXSPI_A_DATA1   /*!< Signal name */
+
+/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL                   FLEXSPI_A_DATA2   /*!< Signal name */
+
+/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL                       FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL                   FLEXSPI_A_DATA3   /*!< Signal name */
+
+/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL                     FLEXSPI_A_SCLK   /*!< Signal name */
+
+/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL                    FLEXSPI_A_SS0_B   /*!< Signal name */
+
+/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */
+/* Routed pin properties */
+#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL                        FLEXSPI   /*!< Peripheral name */
+#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL                      FLEXSPI_A_DQS   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitQSPIPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41.mex b/hw/bsp/imxrt/boards/teensy_41/teensy41.mex
new file mode 100644
index 000000000..1ade853ae
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41.mex
@@ -0,0 +1,651 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1060-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="2174caba-38fe-48d5-8f89-42a23354d23b" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1062xxxxA</processor>
+      <package>MIMXRT1062DVL6A</package>
+      <board>MIMXRT1060-EVK</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <pin_labels>
+               <pin_label pin_num="E7" pin_signal="GPIO_B0_01" label="LCDIF_ENABLE" identifier="USER_BUTTON"/>
+               <pin_label pin_num="D8" pin_signal="GPIO_B0_03" label="LCDIF_VSYNC" identifier="USER_LED"/>
+            </pin_labels>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO2" signal="gpio_io, 03" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 01" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="96c1cec6-3bd3-47a2-8301-f38e4b0dd25f" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="eb0900eb-d552-4097-9dcf-a07e592a887f" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI" uuid="f67d9a64-c26d-4421-9805-a062b24146f2" type="csi" type_id="csi_3739ec1355c7b915be929f3b7e35095b" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi" quick_selection="QuickSelection1">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected/>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="f2c6cd0a-751c-4424-9248-a4d98da47de7" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="01f250e2-83d7-4b7b-a98d-772d1c3bdb42" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD" uuid="90a0c31d-6042-4687-af0f-0892536bc1ba" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="3"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="b31fa225-2a52-486b-9c5c-33a184a2c716" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="aa3cc953-557b-4557-b7fe-6fedc31acf98" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="8b3f852e-ee1e-45e9-abff-0ff722f1d65d" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="539d282e-5136-4289-9058-9a46b221ca45" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="6e4c02c4-0524-4905-91b5-01d2e2502186" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="c6d8fd36-2bbd-44c6-a160-54e7e12d0807" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="7d3626d3-4536-4838-a35d-3b8cf5a2bd71" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="738ea8df-6176-4e52-b4c7-b88aa9c17d13" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
index 2d2bf8f09..f40c72cf7 100644
--- a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h>
+#include "teensy41_flexspi_nor_config.h"
 
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h
index 56068ec6a..d24d4f10a 100644
--- a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/debug.jlinkscript b/hw/bsp/imxrt/debug.jlinkscript
new file mode 100644
index 000000000..fd8bcffef
--- /dev/null
+++ b/hw/bsp/imxrt/debug.jlinkscript
@@ -0,0 +1,5 @@
+int SetupTarget(void) {
+  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
+
+  return 0;
+}
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index fc6e9e266..ad529a227 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -24,112 +24,81 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+/* metadata:
+   manufacturer: NXP
+*/
+
+#include "bsp/board_api.h"
+#include "board/clock_config.h"
+#include "board/pin_mux.h"
 #include "board.h"
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include "fsl_clock.h"
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
 #include "fsl_iomuxc.h"
-#include "fsl_clock.h"
 #include "fsl_lpuart.h"
+#include "fsl_ocotp.h"
 
-#include "clock_config.h"
-
-#if defined(BOARD_TUD_RHPORT) && CFG_TUD_ENABLED
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
+#ifdef __GNUC__
+  #pragma GCC diagnostic pop
 #endif
 
-#if defined(BOARD_TUH_RHPORT) && CFG_TUH_ENABLED
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
-#endif
+/* --- Note about USB buffer RAM ---
+  For M7 core it's recommended to put USB buffer in DTCM for better performance (flexspi_nor linker default)
+  Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU():
+  - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
+  - (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N
+
+  For secondary M4 core, the USB controller doesn't support transfer from DTCM so OCRAM must be used:
+  - __NCACHE_REGION_SIZE is defined by the linker script by default
+  - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
+*/
+
+static void BOARD_ConfigMPU(void);
 
 // needed by fsl_flexspi_nor_boot
-const uint8_t dcd_data[] = { 0x00 };
+TU_ATTR_USED const uint8_t dcd_data[] = {0x00};
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
-void board_init(void)
-{
-  // Init clock
-  BOARD_BootClockRUN();
-  SystemCoreClockUpdate();
+// unify naming convention
+#if !defined(USBPHY1) && defined(USBPHY)
+  #define USBPHY1 USBPHY
+#endif
 
-  // Enable IOCON clock
-  CLOCK_EnableClock(kCLOCK_Iomuxc);
+static void init_usb_phy(uint8_t usb_id) {
+  USBPHY_Type *usb_phy;
 
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  if (usb_id == 0) {
+    usb_phy = USBPHY1;
+    CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
+    CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ);
+  }
 #ifdef USBPHY2
-  NVIC_SetPriority(USB_OTG2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-#endif
-
-  // LED
-  IOMUXC_SetPinMux( LED_PINMUX, 0U);
-  IOMUXC_SetPinConfig( LED_PINMUX, 0x10B0U);
-
-  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode };
-  GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
-  board_led_write(true);
-
-  // Button
-  IOMUXC_SetPinMux( BUTTON_PINMUX, 0U);
-  IOMUXC_SetPinConfig(BUTTON_PINMUX, 0x01B0A0U);
-  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0, kGPIO_IntRisingEdge, };
-  GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
-
-  // UART
-  IOMUXC_SetPinMux( UART_TX_PINMUX, 0U);
-  IOMUXC_SetPinMux( UART_RX_PINMUX, 0U);
-  IOMUXC_SetPinConfig( UART_TX_PINMUX, 0x10B0u);
-  IOMUXC_SetPinConfig( UART_RX_PINMUX, 0x10B0u);
-
-  lpuart_config_t uart_config;
-  LPUART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx = true;
-  uart_config.enableRx = true;
-
-  uint32_t freq;
-  if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
-  {
-    freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+  else if (usb_id == 1) {
+    usb_phy = USBPHY2;
+    CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
+    CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ);
   }
-  else
-  {
-    freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
-  }
-
-  LPUART_Init(UART_PORT, &uart_config, freq);
-
-  //------------- USB0 -------------//
-
-  // Clock
-  CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
-  CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
-
-  USBPHY_Type* usb_phy;
-
-  // RT105x RT106x have dual USB controller.
-#ifdef USBPHY1
-  usb_phy = USBPHY1;
-#else
-  usb_phy = USBPHY;
 #endif
+  else {
+    return;
+  }
 
   // Enable PHY support for Low speed device + LS via FS Hub
   usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
 
   // Enable all power for normal operation
+  // TODO may not be needed since it is called within CLOCK_EnableUsbhs0PhyPllClock()
   usb_phy->PWD = 0;
 
   // TX Timing
@@ -137,90 +106,533 @@ void board_init(void)
   phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
   phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
   usb_phy->TX = phytx;
+}
 
-  // RT105x RT106x have dual USB controller.
+void board_init(void) {
+  BOARD_ConfigMPU();
+  BOARD_InitPins();
+  BOARD_BootClockRUN();
+  SystemCoreClockUpdate();
+
+#ifdef TRACE_ETM
+  //CLOCK_EnableClock(kCLOCK_Trace);
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #ifdef USBPHY2
+  NVIC_SetPriority(USB_OTG2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
+#endif
+
+  board_led_write(true);
+
+  // UART
+  lpuart_config_t uart_config;
+  LPUART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
+
+  if (kStatus_Success != LPUART_Init(UART_PORT, &uart_config, UART_CLK_ROOT)) {
+    // failed to init uart, probably baudrate is not supported
+    // TU_BREAKPOINT();
+  }
+
+  //------------- USB -------------//
+  // Note: RT105x RT106x and later have dual USB controllers.
+  init_usb_phy(0);// USB0
 #ifdef USBPHY2
-  // USB1
-  CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
-  CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
-
-  usb_phy = USBPHY2;
-
-  // Enable PHY support for Low speed device + LS via FS Hub
-  usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
-  // Enable all power for normal operation
-  usb_phy->PWD = 0;
-
-  // TX Timing
-  phytx = usb_phy->TX;
-  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
-  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
-  usb_phy->TX = phytx;
+  init_usb_phy(1);// USB1
 #endif
 }
 
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
-void USB_OTG1_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(0)
-    tud_int_handler(0);
-  #endif
-
-  #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
-  #endif
+void USB_OTG1_IRQHandler(void) {
+  tusb_int_handler(0, true);
 }
 
-void USB_OTG2_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(1)
-    tud_int_handler(1);
-  #endif
-
-  #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
-  #endif
+void USB_OTG2_IRQHandler(void) {
+  tusb_int_handler(1, true);
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
-  // active low
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  LPUART_ReadBlocking(UART_PORT, buf, len);
-  return len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+
+#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL
+  OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk));
+#else
+  OCOTP_Init(OCOTP, 0u);
+#endif
+
+  // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info)
+  // into 8 bit wide destination, avoiding punning.
+  for (int i = 0; i < 4; ++i) {
+    uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1);
+    for (int j = 0; j < 4; j++) {
+      id[i * 4 + j] = wr & 0xff;
+      wr >>= 8;
+    }
+  }
+  OCOTP_Deinit(OCOTP);
+
+  return 16;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len);
+int board_uart_read(uint8_t *buf, int len) {
+  int count = 0;
+
+  while (count < len) {
+    uint8_t const rx_count = LPUART_GetRxFifoCount(UART_PORT);
+    if (!rx_count) {
+      // clear all error flag if any
+      uint32_t status_flags = LPUART_GetStatusFlags(UART_PORT);
+      status_flags &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag |
+                       kLPUART_NoiseErrorFlag);
+      LPUART_ClearStatusFlags(UART_PORT, status_flags);
+      break;
+    }
+
+    for (int i = 0; i < rx_count; i++) {
+      buf[count] = LPUART_ReadByte(UART_PORT);
+      count++;
+    }
+  }
+
+  return count;
+}
+
+int board_uart_write(void const *buf, int len) {
+  LPUART_WriteBlocking(UART_PORT, (uint8_t const *) buf, len);
   return len;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
+
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void _exit(int __status) {
+  while (1) {}
+}
+#endif
+#endif
+
+//--------------------------------------------------------------------
+// MPU configuration
+//--------------------------------------------------------------------
+#if __CORTEX_M == 7
+static void BOARD_ConfigMPU(void) {
+  #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+  extern uint32_t Image$$RW_m_ncache$$Base[];
+  /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
+  extern uint32_t Image$$RW_m_ncache_unused$$Base[];
+  extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
+  uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base;
+  uint32_t size = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
+  #elif defined(__MCUXPRESSO)
+    #if defined(__USE_SHMEM)
+  extern uint32_t __base_rpmsg_sh_mem;
+  extern uint32_t __top_rpmsg_sh_mem;
+  uint32_t nonCacheStart = (uint32_t) (&__base_rpmsg_sh_mem);
+  uint32_t size = (uint32_t) (&__top_rpmsg_sh_mem) - nonCacheStart;
+    #else
+  extern uint32_t __base_NCACHE_REGION;
+  extern uint32_t __top_NCACHE_REGION;
+  uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION);
+  uint32_t size = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart;
+    #endif
+  #elif defined(__ICCARM__) || defined(__GNUC__)
+  extern uint32_t __NCACHE_REGION_START[];
+  extern uint32_t __NCACHE_REGION_SIZE[];
+  uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START;
+  uint32_t size = (uint32_t) __NCACHE_REGION_SIZE;
+  #endif
+  volatile uint32_t i = 0;
+
+  #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
+  /* Disable I cache and D cache */
+  if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
+    SCB_DisableICache();
+  }
+  #endif
+  #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
+  if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
+    SCB_DisableDCache();
+  }
+  #endif
+
+  /* Disable MPU */
+  ARM_MPU_Disable();
+
+  /* MPU configure:
+     * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
+     * SubRegionDisable, Size)
+     * API in mpu_armv7.h.
+     * param DisableExec       Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
+     * disabled.
+     * param AccessPermission  Data access permissions, allows you to configure read/write access for User and
+     * Privileged mode.
+     *      Use MACROS defined in mpu_armv7.h:
+     * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
+     * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
+     *  TypeExtField  IsShareable  IsCacheable  IsBufferable   Memory Attribute    Shareability        Cache
+     *     0             x           0           0             Strongly Ordered    shareable
+     *     0             x           0           1              Device             shareable
+     *     0             0           1           0              Normal             not shareable   Outer and inner write
+     * through no write allocate
+     *     0             0           1           1              Normal             not shareable   Outer and inner write
+     * back no write allocate
+     *     0             1           1           0              Normal             shareable       Outer and inner write
+     * through no write allocate
+     *     0             1           1           1              Normal             shareable       Outer and inner write
+     * back no write allocate
+     *     1             0           0           0              Normal             not shareable   outer and inner
+     * noncache
+     *     1             1           0           0              Normal             shareable       outer and inner
+     * noncache
+     *     1             0           1           1              Normal             not shareable   outer and inner write
+     * back write/read acllocate
+     *     1             1           1           1              Normal             shareable       outer and inner write
+     * back write/read acllocate
+     *     2             x           0           0              Device              not shareable
+     *  Above are normal use settings, if your want to see more details or want to config different inner/outer cache
+     * policy.
+     *  please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
+     * param SubRegionDisable  Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
+     * param Size              Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
+     * mpu_armv7.h.
+     */
+
+  /*
+     * Add default region to deny access to whole address space to workaround speculative prefetch.
+     * Refer to Arm errata 1013783-B for more details.
+     *
+     */
+  /* Region 0 setting: Instruction access disabled, No data access permission. */
+  MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
+  MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
+
+  /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
+  MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+  /* Region 2 setting: Memory with Device type, not shareable,  non-cacheable. */
+  MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+  /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
+  MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+  /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
+  MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
+
+  /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
+  MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
+
+  #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
+  /* Region 6 setting: Memory with Normal type, not shareable, write through */
+  MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
+
+  /* Region 7 setting: Memory with Normal type, not shareable, write through */
+  MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
+  #else
+  /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
+  MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
+
+  /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
+  MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
+  #endif
+
+  #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
+  /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */
+  MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
+  #endif
+
+  #ifdef USE_SDRAM
+    #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
+  /* Region 9 setting: Memory with Normal type, not shareable, write through */
+  MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
+    #else
+  /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
+  MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
+    #endif
+  #endif
+
+  while ((size >> i) > 0x1U) {
+    i++;
+  }
+
+  if (i != 0) {
+    /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+    assert(!(nonCacheStart % size));
+    assert(size == (uint32_t) (1 << i));
+    assert(i >= 5);
+
+    /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
+    MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
+  }
+
+  /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
+  MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
+
+  /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
+  MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
+
+  /* Region 13 setting: Memory with Device type, not shareable, non-cacheable */
+  MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
+
+  /* Region 14 setting: Memory with Device type, not shareable, non-cacheable */
+  MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
+
+  /* Region 15 setting: Memory with Device type, not shareable, non-cacheable */
+  MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
+
+  /* Enable MPU */
+  ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
+
+  /* Enable I cache and D cache */
+  #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
+  SCB_EnableDCache();
+  #endif
+  #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
+  SCB_EnableICache();
+  #endif
+}
+
+#elif __CORTEX_M == 4
+
+void BOARD_ConfigMPU(void) {
+  #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+  extern uint32_t Image$$RW_m_ncache$$Base[];
+  /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
+  extern uint32_t Image$$RW_m_ncache_unused$$Base[];
+  extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
+  uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base;
+  uint32_t nonCacheSize = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
+  #elif defined(__MCUXPRESSO)
+  extern uint32_t __base_NCACHE_REGION;
+  extern uint32_t __top_NCACHE_REGION;
+  uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION);
+  uint32_t nonCacheSize = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart;
+  #elif defined(__ICCARM__) || defined(__GNUC__)
+  extern uint32_t __NCACHE_REGION_START[];
+  extern uint32_t __NCACHE_REGION_SIZE[];
+  uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START;
+  uint32_t nonCacheSize = (uint32_t) __NCACHE_REGION_SIZE;
+  #endif
+  #if defined(__USE_SHMEM)
+    #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+  extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
+  /* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
+  extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[];
+  extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[];
+  uint32_t rpmsgShmemStart = (uint32_t) Image$$RPMSG_SH_MEM$$Base;
+  uint32_t rpmsgShmemSize = (uint32_t) Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart;
+    #elif defined(__MCUXPRESSO)
+  extern uint32_t __base_rpmsg_sh_mem;
+  extern uint32_t __top_rpmsg_sh_mem;
+  uint32_t rpmsgShmemStart = (uint32_t) (&__base_rpmsg_sh_mem);
+  uint32_t rpmsgShmemSize = (uint32_t) (&__top_rpmsg_sh_mem) - rpmsgShmemStart;
+    #elif defined(__ICCARM__) || defined(__GNUC__)
+  extern uint32_t __RPMSG_SH_MEM_START[];
+  extern uint32_t __RPMSG_SH_MEM_SIZE[];
+  uint32_t rpmsgShmemStart = (uint32_t) __RPMSG_SH_MEM_START;
+  uint32_t rpmsgShmemSize = (uint32_t) __RPMSG_SH_MEM_SIZE;
+    #endif
+  #endif
+  uint32_t i = 0;
+
+  /* Only config non-cacheable region on system bus */
+  assert(nonCacheStart >= 0x20000000);
+
+  /* Disable code bus cache */
+  if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) {
+    /* Enable the processor code bus to push all modified lines. */
+    LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
+    /* Wait until the cache command completes. */
+    while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
+    }
+    /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+    LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
+    /* Now disable the cache. */
+    LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
+  }
+
+  /* Disable system bus cache */
+  if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) {
+    /* Enable the processor system bus to push all modified lines. */
+    LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
+    /* Wait until the cache command completes. */
+    while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
+    }
+    /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+    LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
+    /* Now disable the cache. */
+    LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
+  }
+
+  /* Disable MPU */
+  ARM_MPU_Disable();
+
+  #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
+  /* Region 0 setting: Memory with Normal type, not shareable, write through */
+  MPU->RBAR = ARM_MPU_RBAR(0, 0x20200000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
+
+  /* Region 1 setting: Memory with Normal type, not shareable, write through */
+  MPU->RBAR = ARM_MPU_RBAR(1, 0x20300000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
+
+  /* Region 2 setting: Memory with Normal type, not shareable, write through */
+  MPU->RBAR = ARM_MPU_RBAR(2, 0x80000000U);
+  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
+
+  while ((nonCacheSize >> i) > 0x1U) {
+    i++;
+  }
+
+  if (i != 0) {
+    /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+    assert(!(nonCacheStart % nonCacheSize));
+    assert(nonCacheSize == (uint32_t) (1 << i));
+    assert(i >= 5);
+
+    /* Region 3 setting: Memory with device type, not shareable, non-cacheable */
+    MPU->RBAR = ARM_MPU_RBAR(3, nonCacheStart);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
+  }
+
+    #if defined(__USE_SHMEM)
+  i = 0;
+
+  while ((rpmsgShmemSize >> i) > 0x1U) {
+    i++;
+  }
+
+  if (i != 0) {
+    /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+    assert(!(rpmsgShmemStart % rpmsgShmemSize));
+    assert(rpmsgShmemSize == (uint32_t) (1 << i));
+    assert(i >= 5);
+
+    /* Region 4 setting: Memory with device type, not shareable, non-cacheable */
+    MPU->RBAR = ARM_MPU_RBAR(4, rpmsgShmemStart);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
+  }
+    #endif
+  #else
+  while ((nonCacheSize >> i) > 0x1U) {
+    i++;
+  }
+
+  if (i != 0) {
+    /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+    assert(!(nonCacheStart % nonCacheSize));
+    assert(nonCacheSize == (uint32_t) (1 << i));
+    assert(i >= 5);
+
+    /* Region 0 setting: Memory with device type, not shareable, non-cacheable */
+    MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
+  }
+
+    #if defined(__USE_SHMEM)
+  i = 0;
+
+  while ((rpmsgShmemSize >> i) > 0x1U) {
+    i++;
+  }
+
+  if (i != 0) {
+    /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+    assert(!(rpmsgShmemStart % rpmsgShmemSize));
+    assert(rpmsgShmemSize == (uint32_t) (1 << i));
+    assert(i >= 5);
+
+    /* Region 1 setting: Memory with device type, not shareable, non-cacheable */
+    MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
+  }
+    #endif
+  #endif
+
+  /* Enable MPU */
+  ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
+
+  /* Enables the processor system bus to invalidate all lines in both ways.
+    and Initiate the processor system bus cache command. */
+  LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
+  /* Wait until the cache command completes */
+  while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
+  }
+  /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+  LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
+  /* Now enable the system bus cache. */
+  LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
+
+  /* Enables the processor code bus to invalidate all lines in both ways.
+    and Initiate the processor code bus code cache command. */
+  LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
+  /* Wait until the cache command completes. */
+  while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
+  }
+  /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+  LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
+  /* Now enable the code bus cache. */
+  LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
+}
+#endif
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
new file mode 100644
index 000000000..f08ccb3e5
--- /dev/null
+++ b/hw/bsp/imxrt/family.cmake
@@ -0,0 +1,156 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+set(MCU_VARIANT_WITH_CORE ${MCU_VARIANT}${MCU_CORE})
+
+# toolchain set up
+if (NOT DEFINED CMAKE_SYSTEM_CPU)
+  set(CMAKE_SYSTEM_CPU cortex-m7 CACHE INTERNAL "System Processor")
+endif ()
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.ld)
+    set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.icf)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S)
+    set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/startup_${MCU_VARIANT_WITH_CORE}.s)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/pin_mux.c
+    ${SDK_DIR}/drivers/common/fsl_common.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/igpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c
+    ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+    ${SDK_DIR}/drivers/ocotp/fsl_ocotp.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT_WITH_CORE}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    )
+
+  # Optional drivers: only available for some mcus: rt1160, rt1170
+  set(OPTIONAL_DRIVER fsl_dcdc.c fsl_pmu.c fsl_anatop_ai.c)
+  foreach(FILE IN LISTS OPTIONAL_DRIVER)
+    if(EXISTS ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/${FILE})
+      target_sources(${BOARD_TARGET} PRIVATE ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/${FILE})
+    endif()
+  endforeach()
+
+
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __STARTUP_CLEAR_BSS
+    CFG_TUSB_MEM_SECTION=__attribute__\(\(section\(\"NonCacheable\"\)\)\)
+    )
+
+  if (NOT M4 STREQUAL "1")
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      __ARMVFP__=0
+      __ARMFPV5__=0
+      XIP_EXTERNAL_FLASH=1
+      XIP_BOOT_HEADER_ENABLE=1
+      )
+  endif ()
+
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    #${SDK_DIR}/drivers/adc_12b1msps_sar
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/igpio
+    ${SDK_DIR}/drivers/lpspi
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/ocotp
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      # force linker to look for these symbols
+      -Wl,-uimage_vector_table
+      -Wl,-ug_boot_data
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -Wl,-uimage_vector_table
+      -Wl,-ug_boot_data
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX)
+  target_sources(${TARGET} PRIVATE
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 846ecd255..0cf84a4ae 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -1,23 +1,30 @@
 UF2_FAMILY_ID = 0x4fb2d5bd
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+CPU_CORE ?= cortex-m7
+MCU_VARIANT_WITH_CORE = ${MCU_VARIANT}${MCU_CORE}
+MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
+
 CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -D__ARMVFP__=0 -D__ARMFPV5__=0\
+  -D__STARTUP_CLEAR_BSS \
+  -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section("NonCacheable")))' \
+
+ifneq ($(M4), 1)
+CFLAGS += \
+  -D__ARMVFP__=0 \
+  -D__ARMFPV5__=0 \
   -DXIP_EXTERNAL_FLASH=1 \
-  -DXIP_BOOT_HEADER_ENABLE=1 \
-  -DCFG_TUSB_MCU=OPT_MCU_MIMXRT
+  -DXIP_BOOT_HEADER_ENABLE=1
+endif
 
 ifdef BOARD_TUD_RHPORT
 CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT)
 endif
+
 ifdef BOARD_TUH_RHPORT
 CFLAGS += -DBOARD_TUH_RHPORT=$(BOARD_TUH_RHPORT)
 endif
@@ -25,12 +32,14 @@ endif
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough -Wno-error=redundant-decls
 
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
+LDFLAGS_GCC += \
+  -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
 
 # All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx_flexspi_nor.ld
+LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx${MCU_CORE}_flexspi_nor.ld
 
-# TODO for net_lwip_webserver exmaple, but may not needed !! 
+# TODO for net_lwip_webserver example, but may not needed !!
 LDFLAGS += \
 	-Wl,--defsym,__stack_size__=0x800 \
 
@@ -38,26 +47,41 @@ SRC_C += \
 	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
 	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
 	src/portable/ehci/ehci.c \
-	$(MCU_DIR)/system_$(MCU_VARIANT).c \
+	${BOARD_PATH}/board/clock_config.c \
+	${BOARD_PATH}/board/pin_mux.c \
+	$(MCU_DIR)/system_$(MCU_VARIANT_WITH_CORE).c \
 	$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
-	$(MCU_DIR)/project_template/clock_config.c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(SDK_DIR)/drivers/common/fsl_common.c \
+	$(SDK_DIR)/drivers/common/fsl_common_arm.c \
 	$(SDK_DIR)/drivers/igpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
+	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c \
+	$(SDK_DIR)/drivers/ocotp/fsl_ocotp.c \
+
+# Optional drivers: only available for some mcus: rt1160, rt1170
+ifneq (,$(wildcard ${TOP}/${MCU_DIR}/drivers/fsl_dcdc.c))
+SRC_C += \
+  ${MCU_DIR}/drivers/fsl_dcdc.c \
+  ${MCU_DIR}/drivers/fsl_pmu.c \
+  ${MCU_DIR}/drivers/fsl_anatop_ai.c
+endif
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/project_template \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
 	$(TOP)/$(SDK_DIR)/drivers/igpio \
-	$(TOP)/$(SDK_DIR)/drivers/lpuart
+	$(TOP)/$(SDK_DIR)/drivers/lpuart \
+	$(TOP)/$(SDK_DIR)/drivers/ocotp \
 
-SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
+SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT_WITH_CORE).S
 
+# UF2 generation, iMXRT need to strip to text only before conversion
+APPLICATION_ADDR = 0x6000C000
+$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) -O binary -R .flash_config -R .ivt $^ $(BUILD)/$(PROJECT)-textonly.bin
+	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b $(APPLICATION_ADDR) -c -o $@ $(BUILD)/$(PROJECT)-textonly.bin
diff --git a/hw/bsp/kinetis_k/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_k/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..76004241a
--- /dev/null
+++ b/hw/bsp/kinetis_k/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,163 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/board.cmake b/hw/bsp/kinetis_k/boards/frdm_k64f/board.cmake
new file mode 100644
index 000000000..8ded9c1d5
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/frdm_k64f/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MK64F12)
+
+set(JLINK_DEVICE MK64FN1M0xxx12)
+set(PYOCD_TARGET k64f)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/MK64FN1M0xxx12_flash.ld)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/pin_mux.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/clock_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MK64FN1M0VMD12
+    )
+endfunction()
diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/board.h b/hw/bsp/kinetis_k/boards/frdm_k64f/board.h
new file mode 100644
index 000000000..75a10f961
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/frdm_k64f/board.h
@@ -0,0 +1,50 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* metadata:
+   name: Freedom K64F
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+#define LED_PORT              BOARD_LED_RED_GPIO
+#define LED_PIN               BOARD_LED_RED_GPIO_PIN
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           BOARD_SW2_GPIO
+#define BUTTON_PIN            BOARD_SW2_GPIO_PIN
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              UART0
+#define UART_CLOCK            CLOCK_GetFreq(UART0_CLK_SRC)
+
+#endif
diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/board.mk b/hw/bsp/kinetis_k/boards/frdm_k64f/board.mk
new file mode 100644
index 000000000..101fd49aa
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/frdm_k64f/board.mk
@@ -0,0 +1,19 @@
+MCU_VARIANT = MK64F12
+
+CFLAGS += \
+  -DCPU_MK64FN1M0VMD12 \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls
+
+SRC_C += \
+	$(BOARD_PATH)/board/clock_config.c \
+	$(BOARD_PATH)/board/pin_mux.c \
+
+LD_FILE = ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/MK64FN1M0xxx12_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = MK64FN1M0xxx12
+
+# For flash-pyocd target
+PYOCD_TARGET = k64f
diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/board/clock_config.c b/hw/bsp/kinetis_k/boards/frdm_k64f/board/clock_config.c
new file mode 100644
index 000000000..0933c6da9
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/frdm_k64f/board/clock_config.c
@@ -0,0 +1,324 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v12.0
+processor: MK64FN1M0xxx12
+package_id: MK64FN1M0VLL12
+mcu_data: ksdk2_0
+processor_version: 14.0.0
+board: FRDM-K64F
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_smc.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_IRCLK_DISABLE                                 0U  /*!< MCGIRCLK disabled */
+#define MCG_PLL_DISABLE                                   0U  /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_CLKOUT_SEL_FLEXBUS_CLK                        0U  /*!< CLKOUT pin clock select: FlexBus clock */
+#define SIM_ENET_1588T_CLK_SEL_OSCERCLK_CLK               2U  /*!< SDHC clock select: OSCERCLK clock */
+#define SIM_ENET_RMII_CLK_SEL_EXTAL_CLK                   0U  /*!< SDHC clock select: Core/system clock */
+#define SIM_OSC32KSEL_RTC32KCLK_CLK                       2U  /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+#define SIM_PLLFLLSEL_IRC48MCLK_CLK                       3U  /*!< PLLFLL select: IRC48MCLK clock */
+#define SIM_PLLFLLSEL_MCGPLLCLK_CLK                       1U  /*!< PLLFLL select: MCGPLLCLK clock */
+#define SIM_SDHC_CLK_SEL_OSCERCLK_CLK                     2U  /*!< SDHC clock select: OSCERCLK clock */
+#define SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK                 1U  /*!< Trace clock select: Core/system clock */
+#define SIM_USB_CLK_120000000HZ                   120000000U  /*!< Input SIM frequency for USB: 120000000Hz */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
+ * Description   : Configure FLL external reference divider (FRDIV).
+ * Param frdiv   : The value to set FRDIV.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
+{
+    MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
+}
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 60 MHz}
+- {id: CLKOUT.outFreq, value: 40 MHz}
+- {id: Core_clock.outFreq, value: 120 MHz, locked: true, accuracy: '0.001'}
+- {id: ENET1588TSCLK.outFreq, value: 50 MHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: FlexBus_clock.outFreq, value: 40 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFFCLK.outFreq, value: 1.5625 MHz}
+- {id: MCGIRCLK.outFreq, value: 2 MHz}
+- {id: OSCERCLK.outFreq, value: 50 MHz}
+- {id: PLLFLLCLK.outFreq, value: 120 MHz}
+- {id: RMIICLK.outFreq, value: 50 MHz}
+- {id: SDHCCLK.outFreq, value: 50 MHz}
+- {id: System_clock.outFreq, value: 120 MHz}
+- {id: TRACECLKIN.outFreq, value: 120 MHz}
+- {id: USB48MCLK.outFreq, value: 48 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: CLKOUTConfig, value: 'yes'}
+- {id: ENETTimeSrcConfig, value: 'yes'}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLL}
+- {id: MCG.PRDIV.scale, value: '15'}
+- {id: MCG.VDIV.scale, value: '36'}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: RMIISrcConfig, value: 'yes'}
+- {id: RTCCLKOUTConfig, value: 'yes'}
+- {id: RTC_CR_OSCE_CFG, value: Enabled}
+- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
+- {id: SDHCClkConfig, value: 'yes'}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV2.scale, value: '2'}
+- {id: SIM.OUTDIV3.scale, value: '3'}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
+- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.USBDIV.scale, value: '5'}
+- {id: SIM.USBFRAC.scale, value: '2'}
+- {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
+- {id: TraceClkConfig, value: 'yes'}
+- {id: USBClkConfig, value: 'yes'}
+sources:
+- {id: OSC.OSC.outFreq, value: 50 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+    {
+        .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
+        .fcrdiv = 0x1U,                           /* Fast IRC divider: divided by 2 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0xeU,                    /* PLL Reference divider: divided by 15 */
+                .vdiv = 0xcU,                     /* VCO divider: multiplied by 36 */
+            },
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+        .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+        .clkdiv1 = 0x1240000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 50000000U,                        /* Oscillator frequency: 50000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeExt,                 /* Use external clock */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
+                                  mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
+                        kMCG_PllClkSelPll0,
+                        &mcgConfig_BOARD_BootClockRUN.pll0Config);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+    /* Enable USB FS clock. */
+    CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, SIM_USB_CLK_120000000HZ);
+    /* Set enet timestamp clock source. */
+    CLOCK_SetEnetTime0Clock(SIM_ENET_1588T_CLK_SEL_OSCERCLK_CLK);
+    /* Set RMII clock source. */
+    CLOCK_SetRmii0Clock(SIM_ENET_RMII_CLK_SEL_EXTAL_CLK);
+    /* Set SDHC clock source. */
+    CLOCK_SetSdhc0Clock(SIM_SDHC_CLK_SEL_OSCERCLK_CLK);
+    /* Set CLKOUT source. */
+    CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK);
+    /* Set debug trace clock source. */
+    CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK);
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 4 MHz}
+- {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
+- {id: Flash_clock.outFreq, value: 800 kHz}
+- {id: FlexBus_clock.outFreq, value: 4 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: RTC_CR_OSCE_CFG, value: Enabled}
+- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV3.scale, value: '1'}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
+- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
+sources:
+- {id: OSC.OSC.outFreq, value: 50 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
+    {
+        .mcgMode = kMCG_ModeBLPI,                 /* BLPI - Bypassed Low Power Internal */
+        .irclkEnableMode = MCG_IRCLK_DISABLE,     /* MCGIRCLK disabled */
+        .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0x0U,                     /* VCO divider: multiplied by 24 */
+            },
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
+        .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+        .clkdiv1 = 0x40000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 0U,                               /* Oscillator frequency: 0Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeExt,                 /* Use external clock */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
+                         mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}
diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/board/clock_config.h b/hw/bsp/kinetis_k/boards/frdm_k64f/board/clock_config.h
new file mode 100644
index 000000000..88b141834
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/frdm_k64f/board/clock_config.h
@@ -0,0 +1,104 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         50000000U  /*!< Board xtal0 frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             120000000U  /*!< Core clock frequency: 120000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              4000000U  /*!< Core clock frequency: 4000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockVLPR configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
+/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
+/*! @brief OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/board/pin_mux.c b/hw/bsp/kinetis_k/boards/frdm_k64f/board/pin_mux.c
new file mode 100644
index 000000000..f4c245eef
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/frdm_k64f/board/pin_mux.c
@@ -0,0 +1,852 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v14.0
+processor: MK64FN1M0xxx12
+package_id: MK64FN1M0VLL12
+mcu_data: ksdk2_0
+processor_version: 14.0.0
+board: FRDM-K64F
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitButtons();
+    BOARD_InitLEDs();
+    BOARD_InitDEBUG_UART();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitButtons:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '78', peripheral: GPIOC, signal: 'GPIO, 6', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK, identifier: SW2,
+    direction: INPUT, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '38', peripheral: GPIOA, signal: 'GPIO, 4', pin_signal: PTA4/LLWU_P3/FTM0_CH1/NMI_b/EZP_CS_b, direction: INPUT, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitButtons
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitButtons(void)
+{
+    /* Port A Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortA);
+    /* Port C Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortC);
+
+    gpio_pin_config_t SW3_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTA4 (pin 38)  */
+    GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
+
+    gpio_pin_config_t SW2_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTC6 (pin 78)  */
+    GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
+
+    const port_pin_config_t SW3 = {/* Internal pull-up/down resistor is disabled */
+                                   kPORT_PullDisable,
+                                   /* Fast slew rate is configured */
+                                   kPORT_FastSlewRate,
+                                   /* Passive filter is disabled */
+                                   kPORT_PassiveFilterDisable,
+                                   /* Open drain is disabled */
+                                   kPORT_OpenDrainDisable,
+                                   /* Low drive strength is configured */
+                                   kPORT_LowDriveStrength,
+                                   /* Pin is configured as PTA4 */
+                                   kPORT_MuxAsGpio,
+                                   /* Pin Control Register fields [15:0] are not locked */
+                                   kPORT_UnlockRegister};
+    /* PORTA4 (pin 38) is configured as PTA4 */
+    PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
+
+    const port_pin_config_t SW2 = {/* Internal pull-up resistor is enabled */
+                                   kPORT_PullUp,
+                                   /* Fast slew rate is configured */
+                                   kPORT_FastSlewRate,
+                                   /* Passive filter is disabled */
+                                   kPORT_PassiveFilterDisable,
+                                   /* Open drain is disabled */
+                                   kPORT_OpenDrainDisable,
+                                   /* Low drive strength is configured */
+                                   kPORT_LowDriveStrength,
+                                   /* Pin is configured as PTC6 */
+                                   kPORT_MuxAsGpio,
+                                   /* Pin Control Register fields [15:0] are not locked */
+                                   kPORT_UnlockRegister};
+    /* PORTC6 (pin 78) is configured as PTC6 */
+    PORT_SetPinConfig(BOARD_SW2_PORT, BOARD_SW2_PIN, &SW2);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLEDs:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '67', peripheral: GPIOB, signal: 'GPIO, 21', pin_signal: PTB21/SPI2_SCK/FB_AD30/CMP1_OUT, direction: OUTPUT, gpio_init_state: 'true', slew_rate: slow,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '68', peripheral: GPIOB, signal: 'GPIO, 22', pin_signal: PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT, direction: OUTPUT, gpio_init_state: 'true', slew_rate: slow,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '33', peripheral: GPIOE, signal: 'GPIO, 26', pin_signal: PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB_CLKIN, direction: OUTPUT, gpio_init_state: 'true',
+    slew_rate: slow, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLEDs
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitLEDs(void)
+{
+    /* Port B Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortB);
+    /* Port E Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortE);
+
+    gpio_pin_config_t LED_BLUE_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PTB21 (pin 67)  */
+    GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
+
+    gpio_pin_config_t LED_RED_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PTB22 (pin 68)  */
+    GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
+
+    gpio_pin_config_t LED_GREEN_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PTE26 (pin 33)  */
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
+
+    const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
+                                        kPORT_PullDisable,
+                                        /* Slow slew rate is configured */
+                                        kPORT_SlowSlewRate,
+                                        /* Passive filter is disabled */
+                                        kPORT_PassiveFilterDisable,
+                                        /* Open drain is disabled */
+                                        kPORT_OpenDrainDisable,
+                                        /* Low drive strength is configured */
+                                        kPORT_LowDriveStrength,
+                                        /* Pin is configured as PTB21 */
+                                        kPORT_MuxAsGpio,
+                                        /* Pin Control Register fields [15:0] are not locked */
+                                        kPORT_UnlockRegister};
+    /* PORTB21 (pin 67) is configured as PTB21 */
+    PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
+
+    const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
+                                       kPORT_PullDisable,
+                                       /* Slow slew rate is configured */
+                                       kPORT_SlowSlewRate,
+                                       /* Passive filter is disabled */
+                                       kPORT_PassiveFilterDisable,
+                                       /* Open drain is disabled */
+                                       kPORT_OpenDrainDisable,
+                                       /* Low drive strength is configured */
+                                       kPORT_LowDriveStrength,
+                                       /* Pin is configured as PTB22 */
+                                       kPORT_MuxAsGpio,
+                                       /* Pin Control Register fields [15:0] are not locked */
+                                       kPORT_UnlockRegister};
+    /* PORTB22 (pin 68) is configured as PTB22 */
+    PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
+
+    const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
+                                         kPORT_PullDisable,
+                                         /* Slow slew rate is configured */
+                                         kPORT_SlowSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is disabled */
+                                         kPORT_OpenDrainDisable,
+                                         /* Low drive strength is configured */
+                                         kPORT_LowDriveStrength,
+                                         /* Pin is configured as PTE26 */
+                                         kPORT_MuxAsGpio,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTE26 (pin 33) is configured as PTE26 */
+    PORT_SetPinConfig(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, &LED_GREEN);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UART:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '63', peripheral: UART0, signal: TX, pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b, direction: OUTPUT, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '62', peripheral: UART0, signal: RX, pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN, slew_rate: fast, open_drain: disable, drive_strength: low,
+    pull_select: down, pull_enable: disable, passive_filter: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UART
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UART(void)
+{
+    /* Port B Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortB);
+
+    const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
+                                             kPORT_PullDisable,
+                                             /* Fast slew rate is configured */
+                                             kPORT_FastSlewRate,
+                                             /* Passive filter is disabled */
+                                             kPORT_PassiveFilterDisable,
+                                             /* Open drain is disabled */
+                                             kPORT_OpenDrainDisable,
+                                             /* Low drive strength is configured */
+                                             kPORT_LowDriveStrength,
+                                             /* Pin is configured as UART0_RX */
+                                             kPORT_MuxAlt3,
+                                             /* Pin Control Register fields [15:0] are not locked */
+                                             kPORT_UnlockRegister};
+    /* PORTB16 (pin 62) is configured as UART0_RX */
+    PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
+
+    const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
+                                             kPORT_PullDisable,
+                                             /* Fast slew rate is configured */
+                                             kPORT_FastSlewRate,
+                                             /* Passive filter is disabled */
+                                             kPORT_PassiveFilterDisable,
+                                             /* Open drain is disabled */
+                                             kPORT_OpenDrainDisable,
+                                             /* Low drive strength is configured */
+                                             kPORT_LowDriveStrength,
+                                             /* Pin is configured as UART0_TX */
+                                             kPORT_MuxAlt3,
+                                             /* Pin Control Register fields [15:0] are not locked */
+                                             kPORT_UnlockRegister};
+    /* PORTB17 (pin 63) is configured as UART0_TX */
+    PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
+
+    SIM->SOPT5 = ((SIM->SOPT5 &
+                   /* Mask bits to zero which are setting */
+                   (~(SIM_SOPT5_UART0TXSRC_MASK)))
+
+                  /* UART 0 transmit data source select: UART0_TX pin. */
+                  | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX));
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitOSC:
+- options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '50', peripheral: OSC, signal: EXTAL0, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0, identifier: EXTAL0, slew_rate: no_init, open_drain: no_init, drive_strength: no_init,
+    pull_select: no_init, pull_enable: no_init, passive_filter: no_init}
+  - {pin_num: '29', peripheral: RTC, signal: EXTAL32, pin_signal: EXTAL32}
+  - {pin_num: '28', peripheral: RTC, signal: XTAL32, pin_signal: XTAL32}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitOSC
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitOSC(void)
+{
+    /* Port A Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortA);
+
+    /* PORTA18 (pin 50) is configured as EXTAL0 */
+    PORT_SetPinMux(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, kPORT_PinDisabledOrAnalog);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitACCEL:
+- options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '32', peripheral: I2C0, signal: SDA, pin_signal: ADC0_SE18/PTE25/UART4_RX/I2C0_SDA/EWM_IN, slew_rate: fast, open_drain: enable, drive_strength: low,
+    pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '31', peripheral: I2C0, signal: SCL, pin_signal: ADC0_SE17/PTE24/UART4_TX/I2C0_SCL/EWM_OUT_b, slew_rate: fast, open_drain: enable, drive_strength: low,
+    pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '78', peripheral: GPIOC, signal: 'GPIO, 6', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK, identifier: ACCEL_INT1,
+    direction: INPUT, slew_rate: fast, open_drain: enable, drive_strength: low, pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '85', peripheral: GPIOC, signal: 'GPIO, 13', pin_signal: PTC13/UART4_CTS_b/FB_AD26, direction: INPUT, slew_rate: fast, open_drain: enable, drive_strength: low,
+    pull_select: up, pull_enable: enable, passive_filter: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitACCEL
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitACCEL(void)
+{
+    /* Port C Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortC);
+    /* Port E Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortE);
+
+    gpio_pin_config_t ACCEL_INT1_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTC6 (pin 78)  */
+    GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
+
+    gpio_pin_config_t ACCEL_INT2_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTC13 (pin 85)  */
+    GPIO_PinInit(BOARD_ACCEL_INT2_GPIO, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2_config);
+
+    const port_pin_config_t ACCEL_INT2 = {/* Internal pull-up resistor is enabled */
+                                          kPORT_PullUp,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is enabled */
+                                          kPORT_OpenDrainEnable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as PTC13 */
+                                          kPORT_MuxAsGpio,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTC13 (pin 85) is configured as PTC13 */
+    PORT_SetPinConfig(BOARD_ACCEL_INT2_PORT, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2);
+
+    const port_pin_config_t ACCEL_INT1 = {/* Internal pull-up resistor is enabled */
+                                          kPORT_PullUp,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is enabled */
+                                          kPORT_OpenDrainEnable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as PTC6 */
+                                          kPORT_MuxAsGpio,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTC6 (pin 78) is configured as PTC6 */
+    PORT_SetPinConfig(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1);
+
+    const port_pin_config_t ACCEL_SCL = {/* Internal pull-up resistor is enabled */
+                                         kPORT_PullUp,
+                                         /* Fast slew rate is configured */
+                                         kPORT_FastSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is enabled */
+                                         kPORT_OpenDrainEnable,
+                                         /* Low drive strength is configured */
+                                         kPORT_LowDriveStrength,
+                                         /* Pin is configured as I2C0_SCL */
+                                         kPORT_MuxAlt5,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTE24 (pin 31) is configured as I2C0_SCL */
+    PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
+
+    const port_pin_config_t ACCEL_SDA = {/* Internal pull-up resistor is enabled */
+                                         kPORT_PullUp,
+                                         /* Fast slew rate is configured */
+                                         kPORT_FastSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is enabled */
+                                         kPORT_OpenDrainEnable,
+                                         /* Low drive strength is configured */
+                                         kPORT_LowDriveStrength,
+                                         /* Pin is configured as I2C0_SDA */
+                                         kPORT_MuxAlt5,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTE25 (pin 32) is configured as I2C0_SDA */
+    PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitENET:
+- options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '54', peripheral: ENET, signal: RMII_MDC, pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/RMII0_MDC/MII0_MDC/FTM1_QD_PHB, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '53', peripheral: ENET, signal: RMII_MDIO, pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/RMII0_MDIO/MII0_MDIO/FTM1_QD_PHA, slew_rate: fast,
+    open_drain: enable, drive_strength: low, pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '43', peripheral: ENET, signal: RMII_RXD0, pin_signal: CMP2_IN1/PTA13/LLWU_P4/CAN0_RX/FTM1_CH1/RMII0_RXD0/MII0_RXD0/I2C2_SDA/I2S0_TX_FS/FTM1_QD_PHB,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '42', peripheral: ENET, signal: RMII_RXD1, pin_signal: CMP2_IN0/PTA12/CAN0_TX/FTM1_CH0/RMII0_RXD1/MII0_RXD1/I2C2_SCL/I2S0_TXD0/FTM1_QD_PHA, slew_rate: fast,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '39', peripheral: ENET, signal: RMII_RXER, pin_signal: PTA5/USB_CLKIN/FTM0_CH2/RMII0_RXER/MII0_RXER/CMP2_OUT/I2S0_TX_BCLK/JTAG_TRST_b, slew_rate: fast,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '46', peripheral: ENET, signal: RMII_TXD0, pin_signal: PTA16/SPI0_SOUT/UART0_CTS_b/UART0_COL_b/RMII0_TXD0/MII0_TXD0/I2S0_RX_FS/I2S0_RXD1, slew_rate: fast,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '47', peripheral: ENET, signal: RMII_TXD1, pin_signal: ADC1_SE17/PTA17/SPI0_SIN/UART0_RTS_b/RMII0_TXD1/MII0_TXD1/I2S0_MCLK, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '45', peripheral: ENET, signal: RMII_TXEN, pin_signal: PTA15/SPI0_SCK/UART0_RX/RMII0_TXEN/MII0_TXEN/I2S0_RXD0, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '44', peripheral: ENET, signal: RMII_CRS_DV, pin_signal: PTA14/SPI0_PCS0/UART0_TX/RMII0_CRS_DV/MII0_RXDV/I2C2_SCL/I2S0_RX_BCLK/I2S0_TXD1, slew_rate: fast,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+  - {pin_num: '50', peripheral: ENET, signal: RMII_CLKIN, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0, identifier: RMII_RXCLK, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitENET
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitENET(void)
+{
+    /* Port A Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortA);
+    /* Port B Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortB);
+
+    const port_pin_config_t RMII0_RXD1 = {/* Internal pull-up/down resistor is disabled */
+                                          kPORT_PullDisable,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is disabled */
+                                          kPORT_OpenDrainDisable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as RMII0_RXD1 */
+                                          kPORT_MuxAlt4,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTA12 (pin 42) is configured as RMII0_RXD1 */
+    PORT_SetPinConfig(BOARD_RMII0_RXD1_PORT, BOARD_RMII0_RXD1_PIN, &RMII0_RXD1);
+
+    const port_pin_config_t RMII0_RXD0 = {/* Internal pull-up/down resistor is disabled */
+                                          kPORT_PullDisable,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is disabled */
+                                          kPORT_OpenDrainDisable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as RMII0_RXD0 */
+                                          kPORT_MuxAlt4,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTA13 (pin 43) is configured as RMII0_RXD0 */
+    PORT_SetPinConfig(BOARD_RMII0_RXD0_PORT, BOARD_RMII0_RXD0_PIN, &RMII0_RXD0);
+
+    const port_pin_config_t RMII0_CRS_DV = {/* Internal pull-up/down resistor is disabled */
+                                            kPORT_PullDisable,
+                                            /* Fast slew rate is configured */
+                                            kPORT_FastSlewRate,
+                                            /* Passive filter is disabled */
+                                            kPORT_PassiveFilterDisable,
+                                            /* Open drain is disabled */
+                                            kPORT_OpenDrainDisable,
+                                            /* Low drive strength is configured */
+                                            kPORT_LowDriveStrength,
+                                            /* Pin is configured as RMII0_CRS_DV */
+                                            kPORT_MuxAlt4,
+                                            /* Pin Control Register fields [15:0] are not locked */
+                                            kPORT_UnlockRegister};
+    /* PORTA14 (pin 44) is configured as RMII0_CRS_DV */
+    PORT_SetPinConfig(BOARD_RMII0_CRS_DV_PORT, BOARD_RMII0_CRS_DV_PIN, &RMII0_CRS_DV);
+
+    const port_pin_config_t RMII0_TXEN = {/* Internal pull-up/down resistor is disabled */
+                                          kPORT_PullDisable,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is disabled */
+                                          kPORT_OpenDrainDisable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as RMII0_TXEN */
+                                          kPORT_MuxAlt4,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTA15 (pin 45) is configured as RMII0_TXEN */
+    PORT_SetPinConfig(BOARD_RMII0_TXEN_PORT, BOARD_RMII0_TXEN_PIN, &RMII0_TXEN);
+
+    const port_pin_config_t RMII0_TXD0 = {/* Internal pull-up/down resistor is disabled */
+                                          kPORT_PullDisable,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is disabled */
+                                          kPORT_OpenDrainDisable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as RMII0_TXD0 */
+                                          kPORT_MuxAlt4,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTA16 (pin 46) is configured as RMII0_TXD0 */
+    PORT_SetPinConfig(BOARD_RMII0_TXD0_PORT, BOARD_RMII0_TXD0_PIN, &RMII0_TXD0);
+
+    const port_pin_config_t RMII0_TXD1 = {/* Internal pull-up/down resistor is disabled */
+                                          kPORT_PullDisable,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is disabled */
+                                          kPORT_OpenDrainDisable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as RMII0_TXD1 */
+                                          kPORT_MuxAlt4,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTA17 (pin 47) is configured as RMII0_TXD1 */
+    PORT_SetPinConfig(BOARD_RMII0_TXD1_PORT, BOARD_RMII0_TXD1_PIN, &RMII0_TXD1);
+
+    const port_pin_config_t RMII_RXCLK = {/* Internal pull-up/down resistor is disabled */
+                                          kPORT_PullDisable,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is disabled */
+                                          kPORT_OpenDrainDisable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as EXTAL0 */
+                                          kPORT_PinDisabledOrAnalog,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTA18 (pin 50) is configured as EXTAL0 */
+    PORT_SetPinConfig(BOARD_RMII_RXCLK_PORT, BOARD_RMII_RXCLK_PIN, &RMII_RXCLK);
+
+    const port_pin_config_t RMII0_RXER = {/* Internal pull-up/down resistor is disabled */
+                                          kPORT_PullDisable,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is disabled */
+                                          kPORT_OpenDrainDisable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as RMII0_RXER */
+                                          kPORT_MuxAlt4,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTA5 (pin 39) is configured as RMII0_RXER */
+    PORT_SetPinConfig(BOARD_RMII0_RXER_PORT, BOARD_RMII0_RXER_PIN, &RMII0_RXER);
+
+    const port_pin_config_t RMII0_MDIO = {/* Internal pull-up resistor is enabled */
+                                          kPORT_PullUp,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is enabled */
+                                          kPORT_OpenDrainEnable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as RMII0_MDIO */
+                                          kPORT_MuxAlt4,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTB0 (pin 53) is configured as RMII0_MDIO */
+    PORT_SetPinConfig(BOARD_RMII0_MDIO_PORT, BOARD_RMII0_MDIO_PIN, &RMII0_MDIO);
+
+    const port_pin_config_t RMII0_MDC = {/* Internal pull-up/down resistor is disabled */
+                                         kPORT_PullDisable,
+                                         /* Fast slew rate is configured */
+                                         kPORT_FastSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is disabled */
+                                         kPORT_OpenDrainDisable,
+                                         /* Low drive strength is configured */
+                                         kPORT_LowDriveStrength,
+                                         /* Pin is configured as RMII0_MDC */
+                                         kPORT_MuxAlt4,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTB1 (pin 54) is configured as RMII0_MDC */
+    PORT_SetPinConfig(BOARD_RMII0_MDC_PORT, BOARD_RMII0_MDC_PIN, &RMII0_MDC);
+
+    SIM->SOPT2 = ((SIM->SOPT2 &
+                   /* Mask bits to zero which are setting */
+                   (~(SIM_SOPT2_RMIISRC_MASK)))
+
+                  /* RMII clock source select: EXTAL clock. */
+                  | SIM_SOPT2_RMIISRC(SOPT2_RMIISRC_EXTAL));
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSDHC:
+- options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '1', peripheral: SDHC, signal: 'DATA, 1', pin_signal: ADC1_SE4a/PTE0/SPI1_PCS1/UART1_TX/SDHC0_D1/TRACE_CLKOUT/I2C1_SDA/RTC_CLKOUT, slew_rate: fast,
+    open_drain: disable, drive_strength: high, pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '2', peripheral: SDHC, signal: 'DATA, 0', pin_signal: ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/SDHC0_D0/TRACE_D3/I2C1_SCL/SPI1_SIN, slew_rate: fast,
+    open_drain: disable, drive_strength: high, pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '3', peripheral: SDHC, signal: DCLK, pin_signal: ADC0_DP2/ADC1_SE6a/PTE2/LLWU_P1/SPI1_SCK/UART1_CTS_b/SDHC0_DCLK/TRACE_D2, slew_rate: fast, open_drain: disable,
+    drive_strength: high, pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '4', peripheral: SDHC, signal: CMD, pin_signal: ADC0_DM2/ADC1_SE7a/PTE3/SPI1_SIN/UART1_RTS_b/SDHC0_CMD/TRACE_D1/SPI1_SOUT, slew_rate: fast, open_drain: disable,
+    drive_strength: high, pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '5', peripheral: SDHC, signal: 'DATA, 3', pin_signal: PTE4/LLWU_P2/SPI1_PCS0/UART3_TX/SDHC0_D3/TRACE_D0, slew_rate: fast, open_drain: disable, drive_strength: high,
+    pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '6', peripheral: SDHC, signal: 'DATA, 2', pin_signal: PTE5/SPI1_PCS2/UART3_RX/SDHC0_D2/FTM3_CH0, slew_rate: fast, open_drain: disable, drive_strength: high,
+    pull_select: up, pull_enable: enable, passive_filter: disable}
+  - {pin_num: '7', peripheral: GPIOE, signal: 'GPIO, 6', pin_signal: PTE6/SPI1_PCS3/UART3_CTS_b/I2S0_MCLK/FTM3_CH1/USB_SOF_OUT, direction: INPUT, slew_rate: slow,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: enable, passive_filter: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSDHC
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSDHC(void)
+{
+    /* Port E Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortE);
+
+    gpio_pin_config_t SDHC_CD_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTE6 (pin 7)  */
+    GPIO_PinInit(BOARD_SDHC_CD_GPIO, BOARD_SDHC_CD_PIN, &SDHC_CD_config);
+
+    const port_pin_config_t SDHC0_D1 = {/* Internal pull-up resistor is enabled */
+                                        kPORT_PullUp,
+                                        /* Fast slew rate is configured */
+                                        kPORT_FastSlewRate,
+                                        /* Passive filter is disabled */
+                                        kPORT_PassiveFilterDisable,
+                                        /* Open drain is disabled */
+                                        kPORT_OpenDrainDisable,
+                                        /* High drive strength is configured */
+                                        kPORT_HighDriveStrength,
+                                        /* Pin is configured as SDHC0_D1 */
+                                        kPORT_MuxAlt4,
+                                        /* Pin Control Register fields [15:0] are not locked */
+                                        kPORT_UnlockRegister};
+    /* PORTE0 (pin 1) is configured as SDHC0_D1 */
+    PORT_SetPinConfig(BOARD_SDHC0_D1_PORT, BOARD_SDHC0_D1_PIN, &SDHC0_D1);
+
+    const port_pin_config_t SDHC0_D0 = {/* Internal pull-up resistor is enabled */
+                                        kPORT_PullUp,
+                                        /* Fast slew rate is configured */
+                                        kPORT_FastSlewRate,
+                                        /* Passive filter is disabled */
+                                        kPORT_PassiveFilterDisable,
+                                        /* Open drain is disabled */
+                                        kPORT_OpenDrainDisable,
+                                        /* High drive strength is configured */
+                                        kPORT_HighDriveStrength,
+                                        /* Pin is configured as SDHC0_D0 */
+                                        kPORT_MuxAlt4,
+                                        /* Pin Control Register fields [15:0] are not locked */
+                                        kPORT_UnlockRegister};
+    /* PORTE1 (pin 2) is configured as SDHC0_D0 */
+    PORT_SetPinConfig(BOARD_SDHC0_D0_PORT, BOARD_SDHC0_D0_PIN, &SDHC0_D0);
+
+    const port_pin_config_t SDHC0_DCLK = {/* Internal pull-up resistor is enabled */
+                                          kPORT_PullUp,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is disabled */
+                                          kPORT_OpenDrainDisable,
+                                          /* High drive strength is configured */
+                                          kPORT_HighDriveStrength,
+                                          /* Pin is configured as SDHC0_DCLK */
+                                          kPORT_MuxAlt4,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTE2 (pin 3) is configured as SDHC0_DCLK */
+    PORT_SetPinConfig(BOARD_SDHC0_DCLK_PORT, BOARD_SDHC0_DCLK_PIN, &SDHC0_DCLK);
+
+    const port_pin_config_t SDHC0_CMD = {/* Internal pull-up resistor is enabled */
+                                         kPORT_PullUp,
+                                         /* Fast slew rate is configured */
+                                         kPORT_FastSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is disabled */
+                                         kPORT_OpenDrainDisable,
+                                         /* High drive strength is configured */
+                                         kPORT_HighDriveStrength,
+                                         /* Pin is configured as SDHC0_CMD */
+                                         kPORT_MuxAlt4,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTE3 (pin 4) is configured as SDHC0_CMD */
+    PORT_SetPinConfig(BOARD_SDHC0_CMD_PORT, BOARD_SDHC0_CMD_PIN, &SDHC0_CMD);
+
+    const port_pin_config_t SDHC0_D3 = {/* Internal pull-up resistor is enabled */
+                                        kPORT_PullUp,
+                                        /* Fast slew rate is configured */
+                                        kPORT_FastSlewRate,
+                                        /* Passive filter is disabled */
+                                        kPORT_PassiveFilterDisable,
+                                        /* Open drain is disabled */
+                                        kPORT_OpenDrainDisable,
+                                        /* High drive strength is configured */
+                                        kPORT_HighDriveStrength,
+                                        /* Pin is configured as SDHC0_D3 */
+                                        kPORT_MuxAlt4,
+                                        /* Pin Control Register fields [15:0] are not locked */
+                                        kPORT_UnlockRegister};
+    /* PORTE4 (pin 5) is configured as SDHC0_D3 */
+    PORT_SetPinConfig(BOARD_SDHC0_D3_PORT, BOARD_SDHC0_D3_PIN, &SDHC0_D3);
+
+    const port_pin_config_t SDHC0_D2 = {/* Internal pull-up resistor is enabled */
+                                        kPORT_PullUp,
+                                        /* Fast slew rate is configured */
+                                        kPORT_FastSlewRate,
+                                        /* Passive filter is disabled */
+                                        kPORT_PassiveFilterDisable,
+                                        /* Open drain is disabled */
+                                        kPORT_OpenDrainDisable,
+                                        /* High drive strength is configured */
+                                        kPORT_HighDriveStrength,
+                                        /* Pin is configured as SDHC0_D2 */
+                                        kPORT_MuxAlt4,
+                                        /* Pin Control Register fields [15:0] are not locked */
+                                        kPORT_UnlockRegister};
+    /* PORTE5 (pin 6) is configured as SDHC0_D2 */
+    PORT_SetPinConfig(BOARD_SDHC0_D2_PORT, BOARD_SDHC0_D2_PIN, &SDHC0_D2);
+
+    const port_pin_config_t SDHC_CD = {/* Internal pull-down resistor is enabled */
+                                       kPORT_PullDown,
+                                       /* Slow slew rate is configured */
+                                       kPORT_SlowSlewRate,
+                                       /* Passive filter is disabled */
+                                       kPORT_PassiveFilterDisable,
+                                       /* Open drain is disabled */
+                                       kPORT_OpenDrainDisable,
+                                       /* Low drive strength is configured */
+                                       kPORT_LowDriveStrength,
+                                       /* Pin is configured as PTE6 */
+                                       kPORT_MuxAsGpio,
+                                       /* Pin Control Register fields [15:0] are not locked */
+                                       kPORT_UnlockRegister};
+    /* PORTE6 (pin 7) is configured as PTE6 */
+    PORT_SetPinConfig(BOARD_SDHC_CD_PORT, BOARD_SDHC_CD_PIN, &SDHC_CD);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSB:
+- options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '10', peripheral: USB0, signal: DP, pin_signal: USB0_DP}
+  - {pin_num: '11', peripheral: USB0, signal: DM, pin_signal: USB0_DM}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSB
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUSB(void)
+{
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/board/pin_mux.h b/hw/bsp/kinetis_k/boards/frdm_k64f/board/pin_mux.h
new file mode 100644
index 000000000..6d64832ba
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/frdm_k64f/board/pin_mux.h
@@ -0,0 +1,645 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+    kPIN_MUX_DirectionInput = 0U,        /* Input direction */
+    kPIN_MUX_DirectionOutput = 1U,       /* Output direction */
+    kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+/*! @name PORTC6 (number 78), U8[11]/SW2
+  @{ */
+/* Routed pin properties */
+#define BOARD_SW2_PERIPHERAL GPIOC                  /*!<@brief Peripheral name */
+#define BOARD_SW2_SIGNAL GPIO                       /*!<@brief Signal name */
+#define BOARD_SW2_CHANNEL 6                         /*!<@brief Signal channel */
+#define BOARD_SW2_PIN_NAME PTC6                     /*!<@brief Routed pin name */
+#define BOARD_SW2_LABEL "U8[11]/SW2"                /*!<@brief Label */
+#define BOARD_SW2_NAME "SW2"                        /*!<@brief Identifier */
+#define BOARD_SW2_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_SW2_GPIO GPIOC                        /*!<@brief GPIO peripheral base pointer */
+#define BOARD_SW2_GPIO_PIN 6U                       /*!<@brief GPIO pin number */
+#define BOARD_SW2_GPIO_PIN_MASK (1U << 6U)          /*!<@brief GPIO pin mask */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_SW2_PORT PORTC                        /*!<@brief PORT peripheral base pointer */
+#define BOARD_SW2_PIN 6U                            /*!<@brief PORT pin number */
+#define BOARD_SW2_PIN_MASK (1U << 6U)               /*!<@brief PORT pin mask */
+                                                    /* @} */
+
+/*! @name PORTA4 (number 38), SW3
+  @{ */
+/* Routed pin properties */
+#define BOARD_SW3_PERIPHERAL GPIOA                  /*!<@brief Peripheral name */
+#define BOARD_SW3_SIGNAL GPIO                       /*!<@brief Signal name */
+#define BOARD_SW3_CHANNEL 4                         /*!<@brief Signal channel */
+#define BOARD_SW3_PIN_NAME PTA4                     /*!<@brief Routed pin name */
+#define BOARD_SW3_LABEL "SW3"                       /*!<@brief Label */
+#define BOARD_SW3_NAME "SW3"                        /*!<@brief Identifier */
+#define BOARD_SW3_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_SW3_GPIO GPIOA                        /*!<@brief GPIO peripheral base pointer */
+#define BOARD_SW3_GPIO_PIN 4U                       /*!<@brief GPIO pin number */
+#define BOARD_SW3_GPIO_PIN_MASK (1U << 4U)          /*!<@brief GPIO pin mask */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_SW3_PORT PORTA                        /*!<@brief PORT peripheral base pointer */
+#define BOARD_SW3_PIN 4U                            /*!<@brief PORT pin number */
+#define BOARD_SW3_PIN_MASK (1U << 4U)               /*!<@brief PORT pin mask */
+                                                    /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitButtons(void);
+
+/*! @name PORTB21 (number 67), D12[3]/LEDRGB_BLUE
+  @{ */
+/* Routed pin properties */
+#define BOARD_LED_BLUE_PERIPHERAL GPIOB                   /*!<@brief Peripheral name */
+#define BOARD_LED_BLUE_SIGNAL GPIO                        /*!<@brief Signal name */
+#define BOARD_LED_BLUE_CHANNEL 21                         /*!<@brief Signal channel */
+#define BOARD_LED_BLUE_PIN_NAME PTB21                     /*!<@brief Routed pin name */
+#define BOARD_LED_BLUE_LABEL "D12[3]/LEDRGB_BLUE"         /*!<@brief Label */
+#define BOARD_LED_BLUE_NAME "LED_BLUE"                    /*!<@brief Identifier */
+#define BOARD_LED_BLUE_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_LED_BLUE_GPIO GPIOB                         /*!<@brief GPIO peripheral base pointer */
+#define BOARD_LED_BLUE_GPIO_PIN 21U                       /*!<@brief GPIO pin number */
+#define BOARD_LED_BLUE_GPIO_PIN_MASK (1U << 21U)          /*!<@brief GPIO pin mask */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_LED_BLUE_PORT PORTB                         /*!<@brief PORT peripheral base pointer */
+#define BOARD_LED_BLUE_PIN 21U                            /*!<@brief PORT pin number */
+#define BOARD_LED_BLUE_PIN_MASK (1U << 21U)               /*!<@brief PORT pin mask */
+                                                          /* @} */
+
+/*! @name PORTB22 (number 68), D12[1]/LEDRGB_RED
+  @{ */
+/* Routed pin properties */
+#define BOARD_LED_RED_PERIPHERAL GPIOB                   /*!<@brief Peripheral name */
+#define BOARD_LED_RED_SIGNAL GPIO                        /*!<@brief Signal name */
+#define BOARD_LED_RED_CHANNEL 22                         /*!<@brief Signal channel */
+#define BOARD_LED_RED_PIN_NAME PTB22                     /*!<@brief Routed pin name */
+#define BOARD_LED_RED_LABEL "D12[1]/LEDRGB_RED"          /*!<@brief Label */
+#define BOARD_LED_RED_NAME "LED_RED"                     /*!<@brief Identifier */
+#define BOARD_LED_RED_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_LED_RED_GPIO GPIOB                         /*!<@brief GPIO peripheral base pointer */
+#define BOARD_LED_RED_GPIO_PIN 22U                       /*!<@brief GPIO pin number */
+#define BOARD_LED_RED_GPIO_PIN_MASK (1U << 22U)          /*!<@brief GPIO pin mask */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_LED_RED_PORT PORTB                         /*!<@brief PORT peripheral base pointer */
+#define BOARD_LED_RED_PIN 22U                            /*!<@brief PORT pin number */
+#define BOARD_LED_RED_PIN_MASK (1U << 22U)               /*!<@brief PORT pin mask */
+                                                         /* @} */
+
+/*! @name PORTE26 (number 33), J2[1]/D12[4]/LEDRGB_GREEN
+  @{ */
+/* Routed pin properties */
+#define BOARD_LED_GREEN_PERIPHERAL GPIOE                   /*!<@brief Peripheral name */
+#define BOARD_LED_GREEN_SIGNAL GPIO                        /*!<@brief Signal name */
+#define BOARD_LED_GREEN_CHANNEL 26                         /*!<@brief Signal channel */
+#define BOARD_LED_GREEN_PIN_NAME PTE26                     /*!<@brief Routed pin name */
+#define BOARD_LED_GREEN_LABEL "J2[1]/D12[4]/LEDRGB_GREEN"  /*!<@brief Label */
+#define BOARD_LED_GREEN_NAME "LED_GREEN"                   /*!<@brief Identifier */
+#define BOARD_LED_GREEN_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_LED_GREEN_GPIO GPIOE                         /*!<@brief GPIO peripheral base pointer */
+#define BOARD_LED_GREEN_GPIO_PIN 26U                       /*!<@brief GPIO pin number */
+#define BOARD_LED_GREEN_GPIO_PIN_MASK (1U << 26U)          /*!<@brief GPIO pin mask */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_LED_GREEN_PORT PORTE                         /*!<@brief PORT peripheral base pointer */
+#define BOARD_LED_GREEN_PIN 26U                            /*!<@brief PORT pin number */
+#define BOARD_LED_GREEN_PIN_MASK (1U << 26U)               /*!<@brief PORT pin mask */
+                                                           /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLEDs(void);
+
+#define SOPT5_UART0TXSRC_UART_TX 0x00u /*!<@brief UART 0 transmit data source select: UART0_TX pin */
+
+/*! @name PORTB17 (number 63), U10[1]/UART0_TX
+  @{ */
+/* Routed pin properties */
+#define BOARD_DEBUG_UART_TX_PERIPHERAL UART0                   /*!<@brief Peripheral name */
+#define BOARD_DEBUG_UART_TX_SIGNAL TX                          /*!<@brief Signal name */
+#define BOARD_DEBUG_UART_TX_PIN_NAME UART0_TX                  /*!<@brief Routed pin name */
+#define BOARD_DEBUG_UART_TX_LABEL "U10[1]/UART0_TX"            /*!<@brief Label */
+#define BOARD_DEBUG_UART_TX_NAME "DEBUG_UART_TX"               /*!<@brief Identifier */
+#define BOARD_DEBUG_UART_TX_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_DEBUG_UART_TX_PORT PORTB                         /*!<@brief PORT peripheral base pointer */
+#define BOARD_DEBUG_UART_TX_PIN 17U                            /*!<@brief PORT pin number */
+#define BOARD_DEBUG_UART_TX_PIN_MASK (1U << 17U)               /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PORTB16 (number 62), U7[4]/UART0_RX
+  @{ */
+/* Routed pin properties */
+#define BOARD_DEBUG_UART_RX_PERIPHERAL UART0          /*!<@brief Peripheral name */
+#define BOARD_DEBUG_UART_RX_SIGNAL RX                 /*!<@brief Signal name */
+#define BOARD_DEBUG_UART_RX_PIN_NAME UART0_RX         /*!<@brief Routed pin name */
+#define BOARD_DEBUG_UART_RX_LABEL "U7[4]/UART0_RX"    /*!<@brief Label */
+#define BOARD_DEBUG_UART_RX_NAME "DEBUG_UART_RX"      /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_DEBUG_UART_RX_PORT PORTB                /*!<@brief PORT peripheral base pointer */
+#define BOARD_DEBUG_UART_RX_PIN 16U                   /*!<@brief PORT pin number */
+#define BOARD_DEBUG_UART_RX_PIN_MASK (1U << 16U)      /*!<@brief PORT pin mask */
+                                                      /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UART(void);
+
+/*! @name PORTA18 (number 50), U13[16]/RMII_RXCLK
+  @{ */
+/* Routed pin properties */
+#define BOARD_EXTAL0_PERIPHERAL OSC             /*!<@brief Peripheral name */
+#define BOARD_EXTAL0_SIGNAL EXTAL0              /*!<@brief Signal name */
+#define BOARD_EXTAL0_PIN_NAME EXTAL0            /*!<@brief Routed pin name */
+#define BOARD_EXTAL0_LABEL "U13[16]/RMII_RXCLK" /*!<@brief Label */
+#define BOARD_EXTAL0_NAME "EXTAL0"              /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_EXTAL0_PORT PORTA                 /*!<@brief PORT peripheral base pointer */
+#define BOARD_EXTAL0_PIN 18U                    /*!<@brief PORT pin number */
+#define BOARD_EXTAL0_PIN_MASK (1U << 18U)       /*!<@brief PORT pin mask */
+                                                /* @} */
+
+/*! @name EXTAL32 (number 29), Y3[2]/EXTAL32_RTC
+  @{ */
+/* Routed pin properties */
+#define BOARD_ETAL32K_PERIPHERAL RTC            /*!<@brief Peripheral name */
+#define BOARD_ETAL32K_SIGNAL EXTAL32            /*!<@brief Signal name */
+#define BOARD_ETAL32K_PIN_NAME EXTAL32          /*!<@brief Routed pin name */
+#define BOARD_ETAL32K_LABEL "Y3[2]/EXTAL32_RTC" /*!<@brief Label */
+#define BOARD_ETAL32K_NAME "ETAL32K"            /*!<@brief Identifier */
+                                                /* @} */
+
+/*! @name XTAL32 (number 28), Y3[1]/XTAL32_RTC
+  @{ */
+/* Routed pin properties */
+#define BOARD_XTAL32K_PERIPHERAL RTC           /*!<@brief Peripheral name */
+#define BOARD_XTAL32K_SIGNAL XTAL32            /*!<@brief Signal name */
+#define BOARD_XTAL32K_PIN_NAME XTAL32          /*!<@brief Routed pin name */
+#define BOARD_XTAL32K_LABEL "Y3[1]/XTAL32_RTC" /*!<@brief Label */
+#define BOARD_XTAL32K_NAME "XTAL32K"           /*!<@brief Identifier */
+                                               /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitOSC(void);
+
+/*! @name PORTE25 (number 32), J2[18]/U8[6]/I2C0_SDA
+  @{ */
+/* Routed pin properties */
+#define BOARD_ACCEL_SDA_PERIPHERAL I2C0               /*!<@brief Peripheral name */
+#define BOARD_ACCEL_SDA_SIGNAL SDA                    /*!<@brief Signal name */
+#define BOARD_ACCEL_SDA_PIN_NAME I2C0_SDA             /*!<@brief Routed pin name */
+#define BOARD_ACCEL_SDA_LABEL "J2[18]/U8[6]/I2C0_SDA" /*!<@brief Label */
+#define BOARD_ACCEL_SDA_NAME "ACCEL_SDA"              /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_ACCEL_SDA_PORT PORTE                    /*!<@brief PORT peripheral base pointer */
+#define BOARD_ACCEL_SDA_PIN 25U                       /*!<@brief PORT pin number */
+#define BOARD_ACCEL_SDA_PIN_MASK (1U << 25U)          /*!<@brief PORT pin mask */
+                                                      /* @} */
+
+/*! @name PORTE24 (number 31), J2[20]/U8[4]/I2C0_SCL
+  @{ */
+/* Routed pin properties */
+#define BOARD_ACCEL_SCL_PERIPHERAL I2C0               /*!<@brief Peripheral name */
+#define BOARD_ACCEL_SCL_SIGNAL SCL                    /*!<@brief Signal name */
+#define BOARD_ACCEL_SCL_PIN_NAME I2C0_SCL             /*!<@brief Routed pin name */
+#define BOARD_ACCEL_SCL_LABEL "J2[20]/U8[4]/I2C0_SCL" /*!<@brief Label */
+#define BOARD_ACCEL_SCL_NAME "ACCEL_SCL"              /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_ACCEL_SCL_PORT PORTE                    /*!<@brief PORT peripheral base pointer */
+#define BOARD_ACCEL_SCL_PIN 24U                       /*!<@brief PORT pin number */
+#define BOARD_ACCEL_SCL_PIN_MASK (1U << 24U)          /*!<@brief PORT pin mask */
+                                                      /* @} */
+
+/*! @name PORTC6 (number 78), U8[11]/SW2
+  @{ */
+/* Routed pin properties */
+#define BOARD_ACCEL_INT1_PERIPHERAL GPIOC                  /*!<@brief Peripheral name */
+#define BOARD_ACCEL_INT1_SIGNAL GPIO                       /*!<@brief Signal name */
+#define BOARD_ACCEL_INT1_CHANNEL 6                         /*!<@brief Signal channel */
+#define BOARD_ACCEL_INT1_PIN_NAME PTC6                     /*!<@brief Routed pin name */
+#define BOARD_ACCEL_INT1_LABEL "U8[11]/SW2"                /*!<@brief Label */
+#define BOARD_ACCEL_INT1_NAME "ACCEL_INT1"                 /*!<@brief Identifier */
+#define BOARD_ACCEL_INT1_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_ACCEL_INT1_GPIO GPIOC                        /*!<@brief GPIO peripheral base pointer */
+#define BOARD_ACCEL_INT1_GPIO_PIN 6U                       /*!<@brief GPIO pin number */
+#define BOARD_ACCEL_INT1_GPIO_PIN_MASK (1U << 6U)          /*!<@brief GPIO pin mask */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_ACCEL_INT1_PORT PORTC                        /*!<@brief PORT peripheral base pointer */
+#define BOARD_ACCEL_INT1_PIN 6U                            /*!<@brief PORT pin number */
+#define BOARD_ACCEL_INT1_PIN_MASK (1U << 6U)               /*!<@brief PORT pin mask */
+                                                           /* @} */
+
+/*! @name PORTC13 (number 85), U8[9]
+  @{ */
+/* Routed pin properties */
+#define BOARD_ACCEL_INT2_PERIPHERAL GPIOC                  /*!<@brief Peripheral name */
+#define BOARD_ACCEL_INT2_SIGNAL GPIO                       /*!<@brief Signal name */
+#define BOARD_ACCEL_INT2_CHANNEL 13                        /*!<@brief Signal channel */
+#define BOARD_ACCEL_INT2_PIN_NAME PTC13                    /*!<@brief Routed pin name */
+#define BOARD_ACCEL_INT2_LABEL "U8[9]"                     /*!<@brief Label */
+#define BOARD_ACCEL_INT2_NAME "ACCEL_INT2"                 /*!<@brief Identifier */
+#define BOARD_ACCEL_INT2_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_ACCEL_INT2_GPIO GPIOC                        /*!<@brief GPIO peripheral base pointer */
+#define BOARD_ACCEL_INT2_GPIO_PIN 13U                      /*!<@brief GPIO pin number */
+#define BOARD_ACCEL_INT2_GPIO_PIN_MASK (1U << 13U)         /*!<@brief GPIO pin mask */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_ACCEL_INT2_PORT PORTC                        /*!<@brief PORT peripheral base pointer */
+#define BOARD_ACCEL_INT2_PIN 13U                           /*!<@brief PORT pin number */
+#define BOARD_ACCEL_INT2_PIN_MASK (1U << 13U)              /*!<@brief PORT pin mask */
+                                                           /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitACCEL(void);
+
+#define SOPT2_RMIISRC_EXTAL 0x00u /*!<@brief RMII clock source select: EXTAL clock */
+
+/*! @name PORTB1 (number 54), U13[11]/RMII0_MDC
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII0_MDC_PERIPHERAL ENET           /*!<@brief Peripheral name */
+#define BOARD_RMII0_MDC_SIGNAL RMII_MDC           /*!<@brief Signal name */
+#define BOARD_RMII0_MDC_PIN_NAME RMII0_MDC        /*!<@brief Routed pin name */
+#define BOARD_RMII0_MDC_LABEL "U13[11]/RMII0_MDC" /*!<@brief Label */
+#define BOARD_RMII0_MDC_NAME "RMII0_MDC"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII0_MDC_PORT PORTB                /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII0_MDC_PIN 1U                    /*!<@brief PORT pin number */
+#define BOARD_RMII0_MDC_PIN_MASK (1U << 1U)       /*!<@brief PORT pin mask */
+                                                  /* @} */
+
+/*! @name PORTB0 (number 53), U13[10]/RMII0_MDIO
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII0_MDIO_PERIPHERAL ENET            /*!<@brief Peripheral name */
+#define BOARD_RMII0_MDIO_SIGNAL RMII_MDIO           /*!<@brief Signal name */
+#define BOARD_RMII0_MDIO_PIN_NAME RMII0_MDIO        /*!<@brief Routed pin name */
+#define BOARD_RMII0_MDIO_LABEL "U13[10]/RMII0_MDIO" /*!<@brief Label */
+#define BOARD_RMII0_MDIO_NAME "RMII0_MDIO"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII0_MDIO_PORT PORTB                 /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII0_MDIO_PIN 0U                     /*!<@brief PORT pin number */
+#define BOARD_RMII0_MDIO_PIN_MASK (1U << 0U)        /*!<@brief PORT pin mask */
+                                                    /* @} */
+
+/*! @name PORTA13 (number 43), U13[13]/RMII0_RXD_0
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII0_RXD0_PERIPHERAL ENET             /*!<@brief Peripheral name */
+#define BOARD_RMII0_RXD0_SIGNAL RMII_RXD0            /*!<@brief Signal name */
+#define BOARD_RMII0_RXD0_PIN_NAME RMII0_RXD0         /*!<@brief Routed pin name */
+#define BOARD_RMII0_RXD0_LABEL "U13[13]/RMII0_RXD_0" /*!<@brief Label */
+#define BOARD_RMII0_RXD0_NAME "RMII0_RXD0"           /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII0_RXD0_PORT PORTA                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII0_RXD0_PIN 13U                     /*!<@brief PORT pin number */
+#define BOARD_RMII0_RXD0_PIN_MASK (1U << 13U)        /*!<@brief PORT pin mask */
+                                                     /* @} */
+
+/*! @name PORTA12 (number 42), U13[12]/RMII0_RXD_1
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII0_RXD1_PERIPHERAL ENET             /*!<@brief Peripheral name */
+#define BOARD_RMII0_RXD1_SIGNAL RMII_RXD1            /*!<@brief Signal name */
+#define BOARD_RMII0_RXD1_PIN_NAME RMII0_RXD1         /*!<@brief Routed pin name */
+#define BOARD_RMII0_RXD1_LABEL "U13[12]/RMII0_RXD_1" /*!<@brief Label */
+#define BOARD_RMII0_RXD1_NAME "RMII0_RXD1"           /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII0_RXD1_PORT PORTA                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII0_RXD1_PIN 12U                     /*!<@brief PORT pin number */
+#define BOARD_RMII0_RXD1_PIN_MASK (1U << 12U)        /*!<@brief PORT pin mask */
+                                                     /* @} */
+
+/*! @name PORTA5 (number 39), U13[17]/RMII0_RXER
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII0_RXER_PERIPHERAL ENET            /*!<@brief Peripheral name */
+#define BOARD_RMII0_RXER_SIGNAL RMII_RXER           /*!<@brief Signal name */
+#define BOARD_RMII0_RXER_PIN_NAME RMII0_RXER        /*!<@brief Routed pin name */
+#define BOARD_RMII0_RXER_LABEL "U13[17]/RMII0_RXER" /*!<@brief Label */
+#define BOARD_RMII0_RXER_NAME "RMII0_RXER"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII0_RXER_PORT PORTA                 /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII0_RXER_PIN 5U                     /*!<@brief PORT pin number */
+#define BOARD_RMII0_RXER_PIN_MASK (1U << 5U)        /*!<@brief PORT pin mask */
+                                                    /* @} */
+
+/*! @name PORTA16 (number 46), U13[20]/RMII0_TXD0
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII0_TXD0_PERIPHERAL ENET            /*!<@brief Peripheral name */
+#define BOARD_RMII0_TXD0_SIGNAL RMII_TXD0           /*!<@brief Signal name */
+#define BOARD_RMII0_TXD0_PIN_NAME RMII0_TXD0        /*!<@brief Routed pin name */
+#define BOARD_RMII0_TXD0_LABEL "U13[20]/RMII0_TXD0" /*!<@brief Label */
+#define BOARD_RMII0_TXD0_NAME "RMII0_TXD0"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII0_TXD0_PORT PORTA                 /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII0_TXD0_PIN 16U                    /*!<@brief PORT pin number */
+#define BOARD_RMII0_TXD0_PIN_MASK (1U << 16U)       /*!<@brief PORT pin mask */
+                                                    /* @} */
+
+/*! @name PORTA17 (number 47), U13[21]/RMII0_TXD1
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII0_TXD1_PERIPHERAL ENET            /*!<@brief Peripheral name */
+#define BOARD_RMII0_TXD1_SIGNAL RMII_TXD1           /*!<@brief Signal name */
+#define BOARD_RMII0_TXD1_PIN_NAME RMII0_TXD1        /*!<@brief Routed pin name */
+#define BOARD_RMII0_TXD1_LABEL "U13[21]/RMII0_TXD1" /*!<@brief Label */
+#define BOARD_RMII0_TXD1_NAME "RMII0_TXD1"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII0_TXD1_PORT PORTA                 /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII0_TXD1_PIN 17U                    /*!<@brief PORT pin number */
+#define BOARD_RMII0_TXD1_PIN_MASK (1U << 17U)       /*!<@brief PORT pin mask */
+                                                    /* @} */
+
+/*! @name PORTA15 (number 45), U13[19]/RMII0_TXEN
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII0_TXEN_PERIPHERAL ENET            /*!<@brief Peripheral name */
+#define BOARD_RMII0_TXEN_SIGNAL RMII_TXEN           /*!<@brief Signal name */
+#define BOARD_RMII0_TXEN_PIN_NAME RMII0_TXEN        /*!<@brief Routed pin name */
+#define BOARD_RMII0_TXEN_LABEL "U13[19]/RMII0_TXEN" /*!<@brief Label */
+#define BOARD_RMII0_TXEN_NAME "RMII0_TXEN"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII0_TXEN_PORT PORTA                 /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII0_TXEN_PIN 15U                    /*!<@brief PORT pin number */
+#define BOARD_RMII0_TXEN_PIN_MASK (1U << 15U)       /*!<@brief PORT pin mask */
+                                                    /* @} */
+
+/*! @name PORTA14 (number 44), U13[15]/RMII0_CRS_DV
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII0_CRS_DV_PERIPHERAL ENET              /*!<@brief Peripheral name */
+#define BOARD_RMII0_CRS_DV_SIGNAL RMII_CRS_DV           /*!<@brief Signal name */
+#define BOARD_RMII0_CRS_DV_PIN_NAME RMII0_CRS_DV        /*!<@brief Routed pin name */
+#define BOARD_RMII0_CRS_DV_LABEL "U13[15]/RMII0_CRS_DV" /*!<@brief Label */
+#define BOARD_RMII0_CRS_DV_NAME "RMII0_CRS_DV"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII0_CRS_DV_PORT PORTA                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII0_CRS_DV_PIN 14U                      /*!<@brief PORT pin number */
+#define BOARD_RMII0_CRS_DV_PIN_MASK (1U << 14U)         /*!<@brief PORT pin mask */
+                                                        /* @} */
+
+/*! @name PORTA18 (number 50), U13[16]/RMII_RXCLK
+  @{ */
+/* Routed pin properties */
+#define BOARD_RMII_RXCLK_PERIPHERAL ENET            /*!<@brief Peripheral name */
+#define BOARD_RMII_RXCLK_SIGNAL RMII_CLKIN          /*!<@brief Signal name */
+#define BOARD_RMII_RXCLK_PIN_NAME EXTAL0            /*!<@brief Routed pin name */
+#define BOARD_RMII_RXCLK_LABEL "U13[16]/RMII_RXCLK" /*!<@brief Label */
+#define BOARD_RMII_RXCLK_NAME "RMII_RXCLK"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_RMII_RXCLK_PORT PORTA                 /*!<@brief PORT peripheral base pointer */
+#define BOARD_RMII_RXCLK_PIN 18U                    /*!<@brief PORT pin number */
+#define BOARD_RMII_RXCLK_PIN_MASK (1U << 18U)       /*!<@brief PORT pin mask */
+                                                    /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitENET(void);
+
+/*! @name PORTE0 (number 1), J15[P8]/SDHC0_D1
+  @{ */
+/* Routed pin properties */
+#define BOARD_SDHC0_D1_PERIPHERAL SDHC          /*!<@brief Peripheral name */
+#define BOARD_SDHC0_D1_SIGNAL DATA              /*!<@brief Signal name */
+#define BOARD_SDHC0_D1_CHANNEL 1                /*!<@brief Signal channel */
+#define BOARD_SDHC0_D1_PIN_NAME SDHC0_D1        /*!<@brief Routed pin name */
+#define BOARD_SDHC0_D1_LABEL "J15[P8]/SDHC0_D1" /*!<@brief Label */
+#define BOARD_SDHC0_D1_NAME "SDHC0_D1"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_SDHC0_D1_PORT PORTE               /*!<@brief PORT peripheral base pointer */
+#define BOARD_SDHC0_D1_PIN 0U                   /*!<@brief PORT pin number */
+#define BOARD_SDHC0_D1_PIN_MASK (1U << 0U)      /*!<@brief PORT pin mask */
+                                                /* @} */
+
+/*! @name PORTE1 (number 2), J15[P7]/SDHC0_D0
+  @{ */
+/* Routed pin properties */
+#define BOARD_SDHC0_D0_PERIPHERAL SDHC          /*!<@brief Peripheral name */
+#define BOARD_SDHC0_D0_SIGNAL DATA              /*!<@brief Signal name */
+#define BOARD_SDHC0_D0_CHANNEL 0                /*!<@brief Signal channel */
+#define BOARD_SDHC0_D0_PIN_NAME SDHC0_D0        /*!<@brief Routed pin name */
+#define BOARD_SDHC0_D0_LABEL "J15[P7]/SDHC0_D0" /*!<@brief Label */
+#define BOARD_SDHC0_D0_NAME "SDHC0_D0"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_SDHC0_D0_PORT PORTE               /*!<@brief PORT peripheral base pointer */
+#define BOARD_SDHC0_D0_PIN 1U                   /*!<@brief PORT pin number */
+#define BOARD_SDHC0_D0_PIN_MASK (1U << 1U)      /*!<@brief PORT pin mask */
+                                                /* @} */
+
+/*! @name PORTE2 (number 3), J15[P5]/SDHC0_DCLK
+  @{ */
+/* Routed pin properties */
+#define BOARD_SDHC0_DCLK_PERIPHERAL SDHC            /*!<@brief Peripheral name */
+#define BOARD_SDHC0_DCLK_SIGNAL DCLK                /*!<@brief Signal name */
+#define BOARD_SDHC0_DCLK_PIN_NAME SDHC0_DCLK        /*!<@brief Routed pin name */
+#define BOARD_SDHC0_DCLK_LABEL "J15[P5]/SDHC0_DCLK" /*!<@brief Label */
+#define BOARD_SDHC0_DCLK_NAME "SDHC0_DCLK"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_SDHC0_DCLK_PORT PORTE                 /*!<@brief PORT peripheral base pointer */
+#define BOARD_SDHC0_DCLK_PIN 2U                     /*!<@brief PORT pin number */
+#define BOARD_SDHC0_DCLK_PIN_MASK (1U << 2U)        /*!<@brief PORT pin mask */
+                                                    /* @} */
+
+/*! @name PORTE3 (number 4), J15[P3]/SDHC0_CMD
+  @{ */
+/* Routed pin properties */
+#define BOARD_SDHC0_CMD_PERIPHERAL SDHC           /*!<@brief Peripheral name */
+#define BOARD_SDHC0_CMD_SIGNAL CMD                /*!<@brief Signal name */
+#define BOARD_SDHC0_CMD_PIN_NAME SDHC0_CMD        /*!<@brief Routed pin name */
+#define BOARD_SDHC0_CMD_LABEL "J15[P3]/SDHC0_CMD" /*!<@brief Label */
+#define BOARD_SDHC0_CMD_NAME "SDHC0_CMD"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_SDHC0_CMD_PORT PORTE                /*!<@brief PORT peripheral base pointer */
+#define BOARD_SDHC0_CMD_PIN 3U                    /*!<@brief PORT pin number */
+#define BOARD_SDHC0_CMD_PIN_MASK (1U << 3U)       /*!<@brief PORT pin mask */
+                                                  /* @} */
+
+/*! @name PORTE4 (number 5), J15[P2]/SDHC0_D3
+  @{ */
+/* Routed pin properties */
+#define BOARD_SDHC0_D3_PERIPHERAL SDHC          /*!<@brief Peripheral name */
+#define BOARD_SDHC0_D3_SIGNAL DATA              /*!<@brief Signal name */
+#define BOARD_SDHC0_D3_CHANNEL 3                /*!<@brief Signal channel */
+#define BOARD_SDHC0_D3_PIN_NAME SDHC0_D3        /*!<@brief Routed pin name */
+#define BOARD_SDHC0_D3_LABEL "J15[P2]/SDHC0_D3" /*!<@brief Label */
+#define BOARD_SDHC0_D3_NAME "SDHC0_D3"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_SDHC0_D3_PORT PORTE               /*!<@brief PORT peripheral base pointer */
+#define BOARD_SDHC0_D3_PIN 4U                   /*!<@brief PORT pin number */
+#define BOARD_SDHC0_D3_PIN_MASK (1U << 4U)      /*!<@brief PORT pin mask */
+                                                /* @} */
+
+/*! @name PORTE5 (number 6), J15[P1]/SDHC0_D2
+  @{ */
+/* Routed pin properties */
+#define BOARD_SDHC0_D2_PERIPHERAL SDHC          /*!<@brief Peripheral name */
+#define BOARD_SDHC0_D2_SIGNAL DATA              /*!<@brief Signal name */
+#define BOARD_SDHC0_D2_CHANNEL 2                /*!<@brief Signal channel */
+#define BOARD_SDHC0_D2_PIN_NAME SDHC0_D2        /*!<@brief Routed pin name */
+#define BOARD_SDHC0_D2_LABEL "J15[P1]/SDHC0_D2" /*!<@brief Label */
+#define BOARD_SDHC0_D2_NAME "SDHC0_D2"          /*!<@brief Identifier */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_SDHC0_D2_PORT PORTE               /*!<@brief PORT peripheral base pointer */
+#define BOARD_SDHC0_D2_PIN 5U                   /*!<@brief PORT pin number */
+#define BOARD_SDHC0_D2_PIN_MASK (1U << 5U)      /*!<@brief PORT pin mask */
+                                                /* @} */
+
+/*! @name PORTE6 (number 7), J15[G1]/SD_CARD_DETECT
+  @{ */
+/* Routed pin properties */
+#define BOARD_SDHC_CD_PERIPHERAL GPIOE                  /*!<@brief Peripheral name */
+#define BOARD_SDHC_CD_SIGNAL GPIO                       /*!<@brief Signal name */
+#define BOARD_SDHC_CD_CHANNEL 6                         /*!<@brief Signal channel */
+#define BOARD_SDHC_CD_PIN_NAME PTE6                     /*!<@brief Routed pin name */
+#define BOARD_SDHC_CD_LABEL "J15[G1]/SD_CARD_DETECT"    /*!<@brief Label */
+#define BOARD_SDHC_CD_NAME "SDHC_CD"                    /*!<@brief Identifier */
+#define BOARD_SDHC_CD_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_SDHC_CD_GPIO GPIOE                        /*!<@brief GPIO peripheral base pointer */
+#define BOARD_SDHC_CD_GPIO_PIN 6U                       /*!<@brief GPIO pin number */
+#define BOARD_SDHC_CD_GPIO_PIN_MASK (1U << 6U)          /*!<@brief GPIO pin mask */
+
+/* Symbols to be used with PORT driver */
+#define BOARD_SDHC_CD_PORT PORTE                        /*!<@brief PORT peripheral base pointer */
+#define BOARD_SDHC_CD_PIN 6U                            /*!<@brief PORT pin number */
+#define BOARD_SDHC_CD_PIN_MASK (1U << 6U)               /*!<@brief PORT pin mask */
+                                                        /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSDHC(void);
+
+/*! @name USB0_DP (number 10), J22[3]/K64_MICRO_USB_DP
+  @{ */
+/* Routed pin properties */
+#define BOARD_USB_DP_PERIPHERAL USB0                 /*!<@brief Peripheral name */
+#define BOARD_USB_DP_SIGNAL DP                       /*!<@brief Signal name */
+#define BOARD_USB_DP_PIN_NAME USB0_DP                /*!<@brief Routed pin name */
+#define BOARD_USB_DP_LABEL "J22[3]/K64_MICRO_USB_DP" /*!<@brief Label */
+#define BOARD_USB_DP_NAME "USB_DP"                   /*!<@brief Identifier */
+                                                     /* @} */
+
+/*! @name USB0_DM (number 11), J22[2]/K64_MICRO_USB_DN
+  @{ */
+/* Routed pin properties */
+#define BOARD_USB_DM_PERIPHERAL USB0                 /*!<@brief Peripheral name */
+#define BOARD_USB_DM_SIGNAL DM                       /*!<@brief Signal name */
+#define BOARD_USB_DM_PIN_NAME USB0_DM                /*!<@brief Routed pin name */
+#define BOARD_USB_DM_LABEL "J22[2]/K64_MICRO_USB_DN" /*!<@brief Label */
+#define BOARD_USB_DM_NAME "USB_DM"                   /*!<@brief Identifier */
+                                                     /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSB(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex b/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex
new file mode 100644
index 000000000..4a8c77f95
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex
@@ -0,0 +1,950 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="FRDM-K64F" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_14 http://mcuxpresso.nxp.com/XSD/mex_configuration_14.xsd" uuid="c7cfbd44-6838-4477-a52a-4900c4871511" version="14" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_14" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MK64FN1M0xxx12</processor>
+      <package>MK64FN1M0VLL12</package>
+      <board>FRDM-K64F</board>
+      <board_revision>E1</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M4F" id="core0" description="M4 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>true</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="14.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>14.0.0</processor_version>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <prefix>BOARD_</prefix>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitButtons">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <prefix>BOARD_</prefix>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitButtons">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitButtons">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.gpio" description="Pins initialization requires the GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitButtons">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIOC" signal="GPIO, 6" pin_num="78" pin_signal="CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK">
+                     <pin_features>
+                        <pin_feature name="identifier" value="SW2"/>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIOA" signal="GPIO, 4" pin_num="38" pin_signal="PTA4/LLWU_P3/FTM0_CH1/NMI_b/EZP_CS_b">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitLEDs">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <prefix>BOARD_</prefix>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDs">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDs">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.gpio" description="Pins initialization requires the GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDs">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIOB" signal="GPIO, 21" pin_num="67" pin_signal="PTB21/SPI2_SCK/FB_AD30/CMP1_OUT">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="slew_rate" value="slow"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIOB" signal="GPIO, 22" pin_num="68" pin_signal="PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="slew_rate" value="slow"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIOE" signal="GPIO, 26" pin_num="33" pin_signal="PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB_CLKIN">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="slew_rate" value="slow"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UART">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <prefix>BOARD_</prefix>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="UART0" description="Peripheral UART0 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UART">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UART">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UART">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="UART0" signal="TX" pin_num="63" pin_signal="PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="UART0" signal="RX" pin_num="62" pin_signal="PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitOSC">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <prefix>BOARD_</prefix>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="OSC" description="Peripheral OSC is not initialized" problem_level="1" source="Pins:BOARD_InitOSC">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="RTC" description="Peripheral RTC is not initialized" problem_level="1" source="Pins:BOARD_InitOSC">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitOSC">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitOSC">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="OSC" signal="EXTAL0" pin_num="50" pin_signal="EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0">
+                     <pin_features>
+                        <pin_feature name="identifier" value="EXTAL0"/>
+                        <pin_feature name="slew_rate" value="no_init"/>
+                        <pin_feature name="open_drain" value="no_init"/>
+                        <pin_feature name="drive_strength" value="no_init"/>
+                        <pin_feature name="pull_select" value="no_init"/>
+                        <pin_feature name="pull_enable" value="no_init"/>
+                        <pin_feature name="passive_filter" value="no_init"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="RTC" signal="EXTAL32" pin_num="29" pin_signal="EXTAL32"/>
+                  <pin peripheral="RTC" signal="XTAL32" pin_num="28" pin_signal="XTAL32"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitACCEL">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <prefix>BOARD_</prefix>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="I2C0" description="Peripheral I2C0 is not initialized" problem_level="1" source="Pins:BOARD_InitACCEL">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCEL">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitACCEL">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.gpio" description="Pins initialization requires the GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCEL">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="I2C0" signal="SDA" pin_num="32" pin_signal="ADC0_SE18/PTE25/UART4_RX/I2C0_SDA/EWM_IN">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="enable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="I2C0" signal="SCL" pin_num="31" pin_signal="ADC0_SE17/PTE24/UART4_TX/I2C0_SCL/EWM_OUT_b">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="enable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIOC" signal="GPIO, 6" pin_num="78" pin_signal="CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK">
+                     <pin_features>
+                        <pin_feature name="identifier" value="ACCEL_INT1"/>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="enable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIOC" signal="GPIO, 13" pin_num="85" pin_signal="PTC13/UART4_CTS_b/FB_AD26">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="enable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitENET">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <prefix>BOARD_</prefix>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENET">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENET">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitENET">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="RMII_MDC" pin_num="54" pin_signal="ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/RMII0_MDC/MII0_MDC/FTM1_QD_PHB">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ENET" signal="RMII_MDIO" pin_num="53" pin_signal="ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/RMII0_MDIO/MII0_MDIO/FTM1_QD_PHA">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="enable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ENET" signal="RMII_RXD0" pin_num="43" pin_signal="CMP2_IN1/PTA13/LLWU_P4/CAN0_RX/FTM1_CH1/RMII0_RXD0/MII0_RXD0/I2C2_SDA/I2S0_TX_FS/FTM1_QD_PHB">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ENET" signal="RMII_RXD1" pin_num="42" pin_signal="CMP2_IN0/PTA12/CAN0_TX/FTM1_CH0/RMII0_RXD1/MII0_RXD1/I2C2_SCL/I2S0_TXD0/FTM1_QD_PHA">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ENET" signal="RMII_RXER" pin_num="39" pin_signal="PTA5/USB_CLKIN/FTM0_CH2/RMII0_RXER/MII0_RXER/CMP2_OUT/I2S0_TX_BCLK/JTAG_TRST_b">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ENET" signal="RMII_TXD0" pin_num="46" pin_signal="PTA16/SPI0_SOUT/UART0_CTS_b/UART0_COL_b/RMII0_TXD0/MII0_TXD0/I2S0_RX_FS/I2S0_RXD1">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ENET" signal="RMII_TXD1" pin_num="47" pin_signal="ADC1_SE17/PTA17/SPI0_SIN/UART0_RTS_b/RMII0_TXD1/MII0_TXD1/I2S0_MCLK">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ENET" signal="RMII_TXEN" pin_num="45" pin_signal="PTA15/SPI0_SCK/UART0_RX/RMII0_TXEN/MII0_TXEN/I2S0_RXD0">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ENET" signal="RMII_CRS_DV" pin_num="44" pin_signal="PTA14/SPI0_PCS0/UART0_TX/RMII0_CRS_DV/MII0_RXDV/I2C2_SCL/I2S0_RX_BCLK/I2S0_TXD1">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="ENET" signal="RMII_CLKIN" pin_num="50" pin_signal="EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0">
+                     <pin_features>
+                        <pin_feature name="identifier" value="RMII_RXCLK"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="disable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDHC">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <prefix>BOARD_</prefix>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SDHC" description="Peripheral SDHC is not initialized" problem_level="1" source="Pins:BOARD_InitSDHC">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDHC">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitSDHC">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.gpio" description="Pins initialization requires the GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitSDHC">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SDHC" signal="DATA, 1" pin_num="1" pin_signal="ADC1_SE4a/PTE0/SPI1_PCS1/UART1_TX/SDHC0_D1/TRACE_CLKOUT/I2C1_SDA/RTC_CLKOUT">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="high"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SDHC" signal="DATA, 0" pin_num="2" pin_signal="ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/SDHC0_D0/TRACE_D3/I2C1_SCL/SPI1_SIN">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="high"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SDHC" signal="DCLK" pin_num="3" pin_signal="ADC0_DP2/ADC1_SE6a/PTE2/LLWU_P1/SPI1_SCK/UART1_CTS_b/SDHC0_DCLK/TRACE_D2">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="high"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SDHC" signal="CMD" pin_num="4" pin_signal="ADC0_DM2/ADC1_SE7a/PTE3/SPI1_SIN/UART1_RTS_b/SDHC0_CMD/TRACE_D1/SPI1_SOUT">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="high"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SDHC" signal="DATA, 3" pin_num="5" pin_signal="PTE4/LLWU_P2/SPI1_PCS0/UART3_TX/SDHC0_D3/TRACE_D0">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="high"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SDHC" signal="DATA, 2" pin_num="6" pin_signal="PTE5/SPI1_PCS2/UART3_RX/SDHC0_D2/FTM3_CH0">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="high"/>
+                        <pin_feature name="pull_select" value="up"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIOE" signal="GPIO, 6" pin_num="7" pin_signal="PTE6/SPI1_PCS3/UART3_CTS_b/I2S0_MCLK/FTM3_CH1/USB_SOF_OUT">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="slew_rate" value="slow"/>
+                        <pin_feature name="open_drain" value="disable"/>
+                        <pin_feature name="drive_strength" value="low"/>
+                        <pin_feature name="pull_select" value="down"/>
+                        <pin_feature name="pull_enable" value="enable"/>
+                        <pin_feature name="passive_filter" value="disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSB">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <prefix>BOARD_</prefix>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USB0" description="Peripheral USB0 is not initialized" problem_level="1" source="Pins:BOARD_InitUSB">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSB">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USB0" signal="DP" pin_num="10" pin_signal="USB0_DP"/>
+                  <pin peripheral="USB0" signal="DM" pin_num="11" pin_signal="USB0_DM"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>14.0.0</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="OSC.EXTAL0" description="&apos;EXTAL0&apos; (Pins tool id: OSC.EXTAL0, Clocks tool id: OSC.EXTAL0) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="OSC.EXTAL0" description="&apos;EXTAL0&apos; (Pins tool id: OSC.EXTAL0, Clocks tool id: OSC.EXTAL0) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="OSC.OSC.outFreq" value="50 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="Bus_clock.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLKOUT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="Core_clock.outFreq" value="120 MHz" locked="true" accuracy="0.001"/>
+                  <clock_output id="ENET1588TSCLK.outFreq" value="50 MHz" locked="false" accuracy=""/>
+                  <clock_output id="Flash_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FlexBus_clock.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPO_clock.outFreq" value="1 kHz" locked="false" accuracy=""/>
+                  <clock_output id="MCGFFCLK.outFreq" value="1.5625 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MCGIRCLK.outFreq" value="2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="OSCERCLK.outFreq" value="50 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLLFLLCLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
+                  <clock_output id="RMIICLK.outFreq" value="50 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SDHCCLK.outFreq" value="50 MHz" locked="false" accuracy=""/>
+                  <clock_output id="System_clock.outFreq" value="120 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACECLKIN.outFreq" value="120 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB48MCLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="MCGMode" value="PEE" locked="false"/>
+                  <setting id="CLKOUTConfig" value="yes" locked="false"/>
+                  <setting id="ENETTimeSrcConfig" value="yes" locked="false"/>
+                  <setting id="MCG.FRDIV.scale" value="32" locked="false"/>
+                  <setting id="MCG.IRCS.sel" value="MCG.FCRDIV" locked="false"/>
+                  <setting id="MCG.IREFS.sel" value="MCG.FRDIV" locked="false"/>
+                  <setting id="MCG.PLLS.sel" value="MCG.PLL" locked="false"/>
+                  <setting id="MCG.PRDIV.scale" value="15" locked="false"/>
+                  <setting id="MCG.VDIV.scale" value="36" locked="false"/>
+                  <setting id="MCG_C1_IRCLKEN_CFG" value="Enabled" locked="false"/>
+                  <setting id="MCG_C2_RANGE0_CFG" value="Very_high" locked="false"/>
+                  <setting id="MCG_C2_RANGE0_FRDIV_CFG" value="Very_high" locked="false"/>
+                  <setting id="OSC_CR_ERCLKEN_CFG" value="Enabled" locked="false"/>
+                  <setting id="RMIISrcConfig" value="yes" locked="false"/>
+                  <setting id="RTCCLKOUTConfig" value="yes" locked="false"/>
+                  <setting id="RTC_CR_OSCE_CFG" value="Enabled" locked="false"/>
+                  <setting id="RTC_CR_OSC_CAP_LOAD_CFG" value="SC10PF" locked="false"/>
+                  <setting id="SDHCClkConfig" value="yes" locked="false"/>
+                  <setting id="SIM.OSC32KSEL.sel" value="RTC.RTC32KCLK" locked="false"/>
+                  <setting id="SIM.OUTDIV2.scale" value="2" locked="false"/>
+                  <setting id="SIM.OUTDIV3.scale" value="3" locked="false"/>
+                  <setting id="SIM.OUTDIV4.scale" value="5" locked="false"/>
+                  <setting id="SIM.PLLFLLSEL.sel" value="MCG.MCGPLLCLK" locked="false"/>
+                  <setting id="SIM.RTCCLKOUTSEL.sel" value="RTC.RTC32KCLK" locked="false"/>
+                  <setting id="SIM.SDHCSRCSEL.sel" value="OSC.OSCERCLK" locked="false"/>
+                  <setting id="SIM.TIMESRCSEL.sel" value="OSC.OSCERCLK" locked="false"/>
+                  <setting id="SIM.USBDIV.scale" value="5" locked="false"/>
+                  <setting id="SIM.USBFRAC.scale" value="2" locked="false"/>
+                  <setting id="SIM.USBSRCSEL.sel" value="SIM.USBDIV" locked="false"/>
+                  <setting id="TraceClkConfig" value="yes" locked="false"/>
+                  <setting id="USBClkConfig" value="yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockVLPR" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockVLPR">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.smc" description="Clocks initialization requires the SMC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockVLPR">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="OSC.OSC.outFreq" value="50 MHz" locked="false" enabled="false"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="Bus_clock.outFreq" value="4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="Core_clock.outFreq" value="4 MHz" locked="true" accuracy="0.001"/>
+                  <clock_output id="Flash_clock.outFreq" value="800 kHz" locked="false" accuracy=""/>
+                  <clock_output id="FlexBus_clock.outFreq" value="4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPO_clock.outFreq" value="1 kHz" locked="false" accuracy=""/>
+                  <clock_output id="System_clock.outFreq" value="4 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="MCGMode" value="BLPI" locked="false"/>
+                  <setting id="powerMode" value="VLPR" locked="false"/>
+                  <setting id="MCG.CLKS.sel" value="MCG.IRCS" locked="false"/>
+                  <setting id="MCG.FCRDIV.scale" value="1" locked="false"/>
+                  <setting id="MCG.FRDIV.scale" value="32" locked="false"/>
+                  <setting id="MCG.IRCS.sel" value="MCG.FCRDIV" locked="false"/>
+                  <setting id="MCG_C2_RANGE0_CFG" value="Very_high" locked="false"/>
+                  <setting id="MCG_C2_RANGE0_FRDIV_CFG" value="Very_high" locked="false"/>
+                  <setting id="RTC_CR_OSCE_CFG" value="Enabled" locked="false"/>
+                  <setting id="RTC_CR_OSC_CAP_LOAD_CFG" value="SC10PF" locked="false"/>
+                  <setting id="SIM.OSC32KSEL.sel" value="RTC.RTC32KCLK" locked="false"/>
+                  <setting id="SIM.OUTDIV3.scale" value="1" locked="false"/>
+                  <setting id="SIM.OUTDIV4.scale" value="5" locked="false"/>
+                  <setting id="SIM.PLLFLLSEL.sel" value="IRC48M.IRC48MCLK" locked="false"/>
+                  <setting id="SIM.RTCCLKOUTSEL.sel" value="RTC.RTC32KCLK" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="13.0" enabled="true" update_project_code="true">
+         <dependencies>
+            <dependency resourceType="SWComponent" resourceId="middleware.usb.common_header" description="USB Common Header is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="middleware.usb.common_header" description="An unsupported version of the USB Common Header in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="compatible">
+                  <data type="Version">2.8.0</data>
+               </feature>
+            </dependency>
+         </dependencies>
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+            <file path="source/generated/usb_device_composite.c" update_enabled="true"/>
+            <file path="source/generated/usb_device_composite.h" update_enabled="true"/>
+            <file path="source/generated/usb_device_config.h" update_enabled="true"/>
+            <file path="source/generated/usb_device_descriptor.c" update_enabled="true"/>
+            <file path="source/generated/usb_device_descriptor.h" update_enabled="true"/>
+            <file path="source/usb_device_interface_0_cic_vcom.c" update_enabled="true"/>
+            <file path="source/usb_device_interface_0_cic_vcom.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>14.0.0</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="a9140131-7ed9-4909-a4a4-202bd81c6834" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.sysmpu" description="The sysmpu driver is missing in the project  (required for the System MPU initialization)." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="enabled" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="middleware.usb.device_controller_khci" description="&quot;USB Device KHCI Controller Driver(FS)&quot; component is missing in the project." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="enabled" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="&quot;Common&quot; driver is missing in the project." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="enabled" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="ClockOutput" resourceId="USB48MCLK" description="USB Function Clock (USB48MCLK) is inactive and USB module will not work." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="middleware.usb.device.cdc.external" description="&quot;USB device CDC&quot; driver is missing in the project." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="enabled" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="middleware.usb.device.cdc.external" description="&quot;USB device CDC&quot; driver is missing in the project." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="enabled" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <instances>
+                  <instance name="NVIC" uuid="e1a88231-4d9e-46a3-b134-d2c743110640" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+                  <instance name="UART0" uuid="7ecfeff3-a6de-43d3-9c43-9dfdbc237b35" type="uart" type_id="uart_9b45c456566d03f79ecfe90751c10bb4" mode="polling" peripheral="UART0" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="uartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="uartConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="GetFreq"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kUART_EightDataBits"/>
+                           <setting name="stopBitCount" value="kUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="idleType" value="kUART_IdleTypeStartBit"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="SYSMPU" uuid="1d744f82-13f4-414f-bfaa-2f30bd3d54e1" type="mpu_utility" type_id="mpu_utility_bc3ea1f6add76edb6050f698d423d163" mode="SYSMPU" peripheral="SYSMPU" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="sysmpu_init">
+                        <setting name="mpuInit" value="disabled"/>
+                     </config_set>
+                  </instance>
+                  <instance name="USB0" uuid="cc0eb411-8fed-4548-b79c-9a8340cc02fd" type="usb" type_id="usb_cbf31fb9a3cef21890d93e737c3d2690" mode="device" peripheral="USB0" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="deviceSetting" quick_selection="QS_DEVICE_CDC_VCOM">
+                        <setting name="vendor_id" value="0x1FC9"/>
+                        <setting name="product_id" value="0x0094"/>
+                        <setting name="manufacturer_string" value="NXP"/>
+                        <setting name="product_string" value="VCOM"/>
+                        <setting name="self_powered" value="true"/>
+                        <setting name="suspend_resume" value="false"/>
+                        <setting name="max_power" value="100"/>
+                        <array name="interfaces">
+                           <struct name="0">
+                              <setting name="interface_class" value="kClassCic"/>
+                              <struct name="setting_cic" quick_selection="QS_INTERFACE_CIC_VCOM">
+                                 <setting name="interface_name" value="CIC VCOM"/>
+                                 <setting name="subclass" value="kSubclassAcm"/>
+                                 <setting name="protocol" value="kProtocolNone"/>
+                                 <setting name="implementation" value="kImplementationCicVcom"/>
+                                 <array name="endpoints_settings">
+                                    <struct name="0">
+                                       <setting name="setting_name" value="Default"/>
+                                       <array name="endpoints">
+                                          <struct name="0">
+                                             <setting name="direction" value="kIn"/>
+                                             <setting name="transfer_type" value="kInterrupt"/>
+                                             <setting name="synchronization" value="kNoSynchronization"/>
+                                             <setting name="usage" value="kData"/>
+                                             <setting name="max_packet_size_fs" value="k16"/>
+                                             <setting name="polling_interval_fs" value="8"/>
+                                             <setting name="bRefresh" value="0"/>
+                                             <setting name="bSynchAddress" value="NoSynchronization"/>
+                                          </struct>
+                                       </array>
+                                    </struct>
+                                 </array>
+                                 <setting name="data_interface_count" value="1"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="interface_class" value="kClassDic"/>
+                              <struct name="setting_dic" quick_selection="QS_INTERFACE_DIC_VCOM">
+                                 <setting name="interface_name" value="DIC VCOM"/>
+                                 <setting name="subclass" value="kSubclassNone"/>
+                                 <setting name="protocol" value="kProtocolNone"/>
+                                 <setting name="implementation" value="kImplementationDicVcom"/>
+                                 <array name="endpoints_settings">
+                                    <struct name="0">
+                                       <setting name="setting_name" value="Default"/>
+                                       <array name="endpoints">
+                                          <struct name="0">
+                                             <setting name="direction" value="kIn"/>
+                                             <setting name="transfer_type" value="kBulk"/>
+                                             <setting name="synchronization" value="kNoSynchronization"/>
+                                             <setting name="usage" value="kData"/>
+                                             <setting name="max_packet_size_fs" value="k64"/>
+                                             <setting name="polling_interval_fs" value="0"/>
+                                             <setting name="bRefresh" value="0"/>
+                                             <setting name="bSynchAddress" value="NoSynchronization"/>
+                                          </struct>
+                                          <struct name="1">
+                                             <setting name="direction" value="kOut"/>
+                                             <setting name="transfer_type" value="kBulk"/>
+                                             <setting name="synchronization" value="kNoSynchronization"/>
+                                             <setting name="usage" value="kData"/>
+                                             <setting name="max_packet_size_fs" value="k64"/>
+                                             <setting name="polling_interval_fs" value="0"/>
+                                             <setting name="bRefresh" value="0"/>
+                                             <setting name="bSynchAddress" value="NoSynchronization"/>
+                                          </struct>
+                                       </array>
+                                    </struct>
+                                 </array>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                     <config_set name="commonSettings">
+                        <struct name="mpu_init">
+                           <setting name="mpu_init_component" value="SYSMPU"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="f2b23d9d-334e-403a-a940-5a1f8e4a6e3f" type_id="system_54b53072540eeeb8f8e9343e71f28176">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="314839b2-20bd-4633-a78b-b9a907d37e75" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="91630462-4f6c-4ce1-bc31-8525c25dfb6a" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="3460120c-749d-46df-afa7-f8b75491d155" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="340e8605-0f8c-44e7-893f-099e6aba3723" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="dfb70626-d825-437a-bfe0-cd0bfc23485b" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="8c54bd92-b658-48de-8726-47edbf90bf20" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="5.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+      <common name="common" version="1.0" enabled="true" update_project_code="true">
+         <core name="core0" role="primary" project_name="Project"/>
+      </common>
+   </tools>
+</configuration>
diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board.cmake b/hw/bsp/kinetis_k/boards/teensy_35/board.cmake
new file mode 100644
index 000000000..ae4409e12
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/teensy_35/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MK64F12)
+
+set(JLINK_DEVICE MK64FX512xxx12)
+set(TEENSY_MCU TEENSY35)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/MK64FX512xxx12_flash.ld)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/pin_mux.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/clock_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MK64FX512VMD12
+    )
+endfunction()
diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board.h b/hw/bsp/kinetis_k/boards/teensy_35/board.h
new file mode 100644
index 000000000..4718a0241
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/teensy_35/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* metadata:
+   name: Teensy 3.5
+   url: https://www.pjrc.com/store/teensy35.html
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+#define LED_PORT              GPIOC
+#define LED_PIN               5
+#define LED_STATE_ON          1
+
+// Button
+
+// UART
+//#define UART_PORT             UART0
+//#define UART_PIN_CLOCK        kCLOCK_PortA
+//#define UART_PIN_PORT         PORTA
+//#define UART_PIN_RX           1u
+//#define UART_PIN_TX           2u
+//#define UART_PIN_FUNCTION     kPORT_MuxAlt2
+//#define SOPT5_UART0RXSRC_UART_RX      0x00u   /*!< UART0 receive data source select: UART0_RX pin */
+//#define SOPT5_UART0TXSRC_UART_TX      0x00u   /*!< UART0 transmit data source select: UART0_TX pin */
+
+#endif
diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board.mk b/hw/bsp/kinetis_k/boards/teensy_35/board.mk
new file mode 100644
index 000000000..2c4f87c25
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/teensy_35/board.mk
@@ -0,0 +1,23 @@
+MCU_VARIANT = MK64F12
+
+CFLAGS += \
+  -DCPU_MK64FX512VMD12 \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls
+
+SRC_C += \
+	$(BOARD_PATH)/board/clock_config.c \
+	$(BOARD_PATH)/board/pin_mux.c \
+
+LD_FILE = ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/MK64FX512xxx12_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = MK64FX512xxx12
+
+# For flash-pyocd target
+PYOCD_TARGET = k64f
+
+# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
+flash: $(BUILD)/$(PROJECT).hex
+	teensy_loader_cli --mcu=TEENSY35 -v -w $<
diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board/clock_config.c b/hw/bsp/kinetis_k/boards/teensy_35/board/clock_config.c
new file mode 100644
index 000000000..b69d10ccb
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/teensy_35/board/clock_config.c
@@ -0,0 +1,186 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MK64FX512xxx12
+package_id: MK64FX512VLQ12
+mcu_data: ksdk2_0
+processor_version: 13.0.1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_IRCLK_DISABLE                                 0U  /*!< MCGIRCLK disabled */
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_OSC32KCLK_CLK                       0U  /*!< OSC32KSEL select: OSC32KCLK clock */
+#define SIM_PLLFLLSEL_MCGPLLCLK_CLK                       1U  /*!< PLLFLL select: MCGPLLCLK clock */
+#define SIM_USB_CLK_120000000HZ                   120000000U  /*!< Input SIM frequency for USB: 120000000Hz */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
+ * Description   : Configure FLL external reference divider (FRDIV).
+ * Param frdiv   : The value to set FRDIV.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
+{
+    MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
+}
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 60 MHz}
+- {id: Core_clock.outFreq, value: 120 MHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: FlexBus_clock.outFreq, value: 40 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFFCLK.outFreq, value: 500 kHz}
+- {id: PLLFLLCLK.outFreq, value: 120 MHz}
+- {id: System_clock.outFreq, value: 120 MHz}
+- {id: USB48MCLK.outFreq, value: 48 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLL}
+- {id: MCG.PRDIV.scale, value: '4'}
+- {id: MCG.VDIV.scale, value: '30'}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: MCG_C5_PLLCLKEN0_CFG, value: Enabled}
+- {id: RTC_CR_CLKO_CFG, value: Disabled}
+- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
+- {id: SIM.OUTDIV2.scale, value: '2'}
+- {id: SIM.OUTDIV3.scale, value: '3'}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
+- {id: SIM.USBDIV.scale, value: '5'}
+- {id: SIM.USBFRAC.scale, value: '2'}
+- {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
+- {id: USBClkConfig, value: 'yes'}
+sources:
+- {id: OSC.OSC.outFreq, value: 16 MHz, enabled: true}
+- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+    {
+        .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
+        .irclkEnableMode = MCG_IRCLK_DISABLE,     /* MCGIRCLK disabled */
+        .ircs = kMCG_IrcSlow,                     /* Slow internal reference clock selected */
+        .fcrdiv = 0x1U,                           /* Fast IRC divider: divided by 2 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = kMCG_PllEnableIndependent,/* MCGPLLCLK enabled independent of MCG clock mode, MCGPLLCLK disabled in STOP mode */
+                .prdiv = 0x3U,                    /* PLL Reference divider: divided by 4 */
+                .vdiv = 0x6U,                     /* VCO divider: multiplied by 30 */
+            },
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
+        .clkdiv1 = 0x1240000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 16000000U,                        /* Oscillator frequency: 16000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeExt,                 /* Use external clock */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
+                        kMCG_PllClkSelPll0,
+                        &mcgConfig_BOARD_BootClockRUN.pll0Config);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+    /* Enable USB FS clock. */
+    CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, SIM_USB_CLK_120000000HZ);
+}
diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board/clock_config.h b/hw/bsp/kinetis_k/boards/teensy_35/board/clock_config.h
new file mode 100644
index 000000000..8601da9c2
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/teensy_35/board/clock_config.h
@@ -0,0 +1,69 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal0 frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             120000000U  /*!< Core clock frequency: 120000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board/pin_mux.c b/hw/bsp/kinetis_k/boards/teensy_35/board/pin_mux.c
new file mode 100644
index 000000000..d2c51e5c6
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/teensy_35/board/pin_mux.c
@@ -0,0 +1,61 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v13.1
+processor: MK64FX512xxx12
+package_id: MK64FX512VLQ12
+mcu_data: ksdk2_0
+processor_version: 13.0.1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '110', peripheral: GPIOC, signal: 'GPIO, 5', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FB_AD10/CMP0_OUT/FTM0_CH2}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+    /* Port C Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortC);
+
+    /* PORTC5 (pin 110) is configured as PTC5 */
+    PORT_SetPinMux(PORTC, 5U, kPORT_MuxAsGpio);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board/pin_mux.h b/hw/bsp/kinetis_k/boards/teensy_35/board/pin_mux.h
new file mode 100644
index 000000000..598ae8e9f
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/teensy_35/board/pin_mux.h
@@ -0,0 +1,45 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/kinetis_k/boards/teensy_35/teensy_35.mex b/hw/bsp/kinetis_k/boards/teensy_35/teensy_35.mex
new file mode 100644
index 000000000..52a087026
--- /dev/null
+++ b/hw/bsp/kinetis_k/boards/teensy_35/teensy_35.mex
@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MK64FX512xxx12" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="9011274c-fba8-40d5-b5c6-83fae0667023" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MK64FX512xxx12</processor>
+      <package>MK64FX512VLQ12</package>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M4F" id="core0" description="M4 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.1</processor_version>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIOC" signal="GPIO, 5" pin_num="110" pin_signal="PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FB_AD10/CMP0_OUT/FTM0_CH2"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.1</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="OSC.EXTAL0" description="&apos;EXTAL0&apos; (Pins tool id: OSC.EXTAL0, Clocks tool id: OSC.EXTAL0) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="OSC.EXTAL0" description="&apos;EXTAL0&apos; (Pins tool id: OSC.EXTAL0, Clocks tool id: OSC.EXTAL0) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="OSC.OSC.outFreq" value="16 MHz" locked="false" enabled="true"/>
+                  <clock_source id="RTC.RTC32kHz.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="Bus_clock.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="Core_clock.outFreq" value="120 MHz" locked="false" accuracy=""/>
+                  <clock_output id="Flash_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FlexBus_clock.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPO_clock.outFreq" value="1 kHz" locked="false" accuracy=""/>
+                  <clock_output id="MCGFFCLK.outFreq" value="500 kHz" locked="false" accuracy=""/>
+                  <clock_output id="PLLFLLCLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
+                  <clock_output id="System_clock.outFreq" value="120 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB48MCLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="MCGMode" value="PEE" locked="false"/>
+                  <setting id="MCG.FRDIV.scale" value="32" locked="false"/>
+                  <setting id="MCG.IREFS.sel" value="MCG.FRDIV" locked="false"/>
+                  <setting id="MCG.PLLS.sel" value="MCG.PLL" locked="false"/>
+                  <setting id="MCG.PRDIV.scale" value="4" locked="false"/>
+                  <setting id="MCG.VDIV.scale" value="30" locked="false"/>
+                  <setting id="MCG_C2_RANGE0_CFG" value="Very_high" locked="false"/>
+                  <setting id="MCG_C2_RANGE0_FRDIV_CFG" value="Very_high" locked="false"/>
+                  <setting id="MCG_C5_PLLCLKEN0_CFG" value="Enabled" locked="false"/>
+                  <setting id="RTC_CR_CLKO_CFG" value="Disabled" locked="false"/>
+                  <setting id="RTC_CR_OSC_CAP_LOAD_CFG" value="SC10PF" locked="false"/>
+                  <setting id="SIM.OUTDIV2.scale" value="2" locked="false"/>
+                  <setting id="SIM.OUTDIV3.scale" value="3" locked="false"/>
+                  <setting id="SIM.OUTDIV4.scale" value="5" locked="false"/>
+                  <setting id="SIM.PLLFLLSEL.sel" value="MCG.MCGPLLCLK" locked="false"/>
+                  <setting id="SIM.USBDIV.scale" value="5" locked="false"/>
+                  <setting id="SIM.USBFRAC.scale" value="2" locked="false"/>
+                  <setting id="SIM.USBSRCSEL.sel" value="SIM.USBDIV" locked="false"/>
+                  <setting id="USBClkConfig" value="yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>N/A</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <peripherals_profile>
+            <processor_version>13.0.1</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="7465f6d1-08aa-48d8-91d5-05023b3186dd" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="NVIC" uuid="84184268-649a-4026-9585-21289f314135" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="069bcce2-44e2-4d92-af51-398354938128" type_id="system_54b53072540eeeb8f8e9343e71f28176">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="53b11db5-341e-452e-9e8e-d62a780aca7b" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="038e164b-8b7a-4d53-8d64-b52445aa6477" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="e2176f5e-bfae-44bf-9ae7-5253becdddfa" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="a8335235-50ea-4aca-a006-aa73fcd95f74" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="dd55e60e-66c0-4980-808e-fe1c012d40fc" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="1a0aebd1-595c-442c-9741-c377be3f6029" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>N/A</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/kinetis_k/family.c b/hw/bsp/kinetis_k/family.c
new file mode 100644
index 000000000..59d80fa18
--- /dev/null
+++ b/hw/bsp/kinetis_k/family.c
@@ -0,0 +1,166 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ * Copyright (c) 2020, Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* metadata:
+   manufacturer: NXP
+*/
+
+#include "bsp/board_api.h"
+#include "board.h"
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_port.h"
+#include "fsl_clock.h"
+#include "fsl_uart.h"
+#include "fsl_sysmpu.h"
+
+#include "board/clock_config.h"
+#include "board/pin_mux.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void) {
+#if CFG_TUH_ENABLED
+  tuh_int_handler(0);
+#endif
+#if CFG_TUD_ENABLED
+  tud_int_handler(0);
+#endif
+}
+
+void board_init(void) {
+  BOARD_InitBootPins();
+  BOARD_BootClockRUN();
+  SystemCoreClockUpdate();
+  SYSMPU_Enable(SYSMPU, 0);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  // LED
+  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
+  GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
+  board_led_write(false);
+
+#if defined(BUTTON_PORT) && defined(BUTTON_PIN)
+  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
+  GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
+#endif
+
+#ifdef UART_DEV
+  const uart_config_t uart_config = {
+      .baudRate_Bps = 115200UL,
+      .parityMode = kUART_ParityDisabled,
+      .stopBitCount = kUART_OneStopBit,
+      .txFifoWatermark = 0U,
+      .rxFifoWatermark = 1U,
+      .idleType = kUART_IdleTypeStartBit,
+      .enableTx = true,
+      .enableRx = true
+  };
+  UART_Init(UART_DEV, &uart_config, UART_CLOCK);
+#endif
+
+  // USB
+  // USB clock is configured in BOARD_BootClockRUN()
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+#if defined(BUTTON_PORT) && defined(BUTTON_PIN)
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
+#else
+  return 0;
+#endif
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+#ifdef UART_DEV
+  // Read blocking will block until there is data
+//  UART_ReadBlocking(UART_DEV, buf, len);
+//  return len;
+  return 0;
+#else
+  return 0;
+#endif
+}
+
+int board_uart_write(void const *buf, int len) {
+  (void) buf;
+  (void) len;
+
+#ifdef UART_DEV
+  UART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
+  return len;
+#else
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void	_exit (int __status) {
+  while (1) {}
+}
+#endif
+
+#endif
diff --git a/hw/bsp/kinetis_k/family.cmake b/hw/bsp/kinetis_k/family.cmake
new file mode 100644
index 000000000..ce91777c9
--- /dev/null
+++ b/hw/bsp/kinetis_k/family.cmake
@@ -0,0 +1,116 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS KINETIS_K CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/uart/fsl_uart.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __STARTUP_CLEAR_BSS
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/gpio
+    ${SDK_DIR}/drivers/port
+    ${SDK_DIR}/drivers/smc
+    ${SDK_DIR}/drivers/sysmpu
+    ${SDK_DIR}/drivers/uart
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+    ${TOP}/src/portable/nxp/khci/hcd_khci.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+
+  if (DEFINED TEENSY_MCU)
+    family_flash_teensy(${TARGET})
+  endif ()
+endfunction()
diff --git a/hw/bsp/kinetis_k/family.mk b/hw/bsp/kinetis_k/family.mk
new file mode 100644
index 000000000..844ce332e
--- /dev/null
+++ b/hw/bsp/kinetis_k/family.mk
@@ -0,0 +1,38 @@
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
+
+MCU_DIR = $(SDK_DIR)/devices/${MCU_VARIANT}
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
+CFLAGS += \
+  -D__STARTUP_CLEAR_BSS \
+  -DCFG_TUSB_MCU=OPT_MCU_KINETIS_K \
+
+LDFLAGS += \
+  -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
+  -Wl,--defsym,__stack_size__=0x400 \
+  -Wl,--defsym,__heap_size__=0
+
+SRC_C += \
+	src/portable/nxp/khci/dcd_khci.c \
+	src/portable/nxp/khci/hcd_khci.c \
+	$(MCU_DIR)/system_${MCU_VARIANT}.c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/uart/fsl_uart.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/drivers \
+	$(TOP)/$(SDK_DIR)/drivers/common \
+	$(TOP)/$(SDK_DIR)/drivers/gpio \
+	$(TOP)/$(SDK_DIR)/drivers/port \
+	$(TOP)/$(SDK_DIR)/drivers/smc \
+	$(TOP)/$(SDK_DIR)/drivers/sysmpu \
+	$(TOP)/$(SDK_DIR)/drivers/uart \
+
+SRC_S += ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
diff --git a/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..0225abe8d
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,170 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.cmake b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.cmake
new file mode 100644
index 000000000..538aec2ca
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT K32L2A41A)
+
+set(JLINK_DEVICE K32L2A41xxxxA)
+set(PYOCD_TARGET K32L2A)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/K32L2A41xxxxA_flash.ld)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_K32L2A41VLH1A
+    )
+endfunction()
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h
new file mode 100644
index 000000000..9e2534307
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h
@@ -0,0 +1,96 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Freedom K32L2A4S
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-K32L2A4S
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "fsl_device_registers.h"
+
+#define USB_CLOCK_SOURCE kCLOCK_IpSrcFircAsync
+
+// LED
+// The Red   LED is on PTE29.
+// The Green LED is on PTC4.
+// The Blue  LED is on PTE31.
+#define LED_PIN_CLOCK         kCLOCK_PortC
+#define LED_GPIO              GPIOC
+#define LED_PORT              PORTC
+#define LED_PIN               4
+#define LED_STATE_ON          0
+
+// SW3 button1
+#define BUTTON_PIN_CLOCK      kCLOCK_PortE
+#define BUTTON_GPIO           GPIOE
+#define BUTTON_PORT           PORTE
+#define BUTTON_PIN            4
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_PORT             LPUART0
+#define UART_PIN_CLOCK        kCLOCK_PortB
+#define UART_PIN_GPIO         GPIOB
+#define UART_PIN_PORT         PORTB
+#define UART_PIN_RX           16u
+#define UART_PIN_TX           17u
+#define UART_CLOCK_SOURCE_HZ  CLOCK_GetFreq(kCLOCK_ScgFircClk)
+
+static inline void BOARD_InitBootPins(void) {
+  /*
+    Enable LPUART0 clock and configure port pins.
+    FIR clock is being used so the USB examples work.
+  */
+  PCC_LPUART0 = 0U;                          /* Clock must be off to set PCS */
+  PCC_LPUART0 = PCC_CLKCFG_PCS(
+      3U);        /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */
+  PCC_LPUART0 |= PCC_CLKCFG_CGC(1U);        /* Enable LPUART */
+
+  /* PORTB16 (pin 62) is configured as LPUART0_RX */
+  gpio_pin_config_t const lpuart_config_rx = {kGPIO_DigitalInput, 0};
+  GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx);
+  const port_pin_config_t UART_CFG = {
+      kPORT_PullUp,
+      kPORT_FastSlewRate,
+      kPORT_PassiveFilterDisable,
+      kPORT_OpenDrainDisable,
+      kPORT_LowDriveStrength,
+      kPORT_MuxAsGpio,
+      kPORT_UnlockRegister
+  };
+  PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG);
+  PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3);
+
+  /* PORTB17 (pin 63) is configured as LPUART0_TX */
+  gpio_pin_config_t const lpuart_config_tx = {kGPIO_DigitalOutput, 0};
+  GPIO_PinInit(UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx);
+  PORT_SetPinMux(UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3);
+}
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
new file mode 100644
index 000000000..c4dc65b63
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
@@ -0,0 +1,18 @@
+MCU = K32L2A41A
+
+CFLAGS += -DCPU_K32L2A41VLH1A
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual
+
+# All source paths should be relative to the top level.
+LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = K32L2A41xxxxA
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2A
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c
new file mode 100644
index 000000000..7947faefe
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c
@@ -0,0 +1,491 @@
+/*
+ * Copyright 2019 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
+ *    Note: The clock could not be set when it is being used as system clock.
+ *    In default out of reset, the CPU is clocked from FIRC(IRC48M),
+ *    so before setting FIRC, change to use another available clock source.
+ *
+ * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
+ *
+ * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
+ *    Wait until the system clock source is changed to target source.
+ *
+ * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
+ *    corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
+ *    Supported run mode and clock restrictions could be found in Reference Manual.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: K32L2A41xxxxA
+package_id: K32L2A41VLL1A
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_smc.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SCG_CLKOUTCNFG_SIRC                               2U  /*!< SCG CLKOUT clock select: Slow IRC */
+#define SCG_SOSC_DISABLE                                  0U  /*!< System OSC disabled */
+#define SCG_SPLL_DISABLE                                  0U  /*!< System PLL disabled */
+#define SCG_SYS_OSC_CAP_0P                                0U  /*!< Oscillator 0pF capacitor load */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+//extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_SetScgOutSel
+ * Description   : Set the SCG clock out select (CLKOUTSEL).
+ * Param setting : The selected clock source.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_SetScgOutSel(uint8_t setting)
+{
+     SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FircSafeConfig
+ * Description   : This function is used to safely configure FIRC clock.
+ *                 In default out of reset, the CPU is clocked from FIRC(IRC48M).
+ *                 Before setting FIRC, change to use SIRC as system clock,
+ *                 then configure FIRC. After FIRC is set, change back to use FIRC
+ *                 in case SIRC need to be configured.
+ * Param fircConfig  : FIRC configuration.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
+{
+    scg_sys_clk_config_t curConfig;
+    const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
+                                             .div1 = kSCG_AsyncClkDisable,
+                                             .div3 = kSCG_AsyncClkDivBy2,
+                                             .range = kSCG_SircRangeHigh};
+    scg_sys_clk_config_t sysClkSafeConfigSource = {
+         .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+         .reserved1 = 0,
+         .reserved2 = 0,
+         .reserved3 = 0,
+#endif
+         .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+         .reserved4 = 0,
+#endif
+         .src = kSCG_SysClkSrcSirc,    /* System clock source */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+         .reserved5 = 0,
+#endif
+    };
+    /* Init Sirc. */
+    CLOCK_InitSirc(&scgSircConfig);
+    /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
+    CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
+    /* Wait for clock source switch finished. */
+    do
+    {
+         CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != sysClkSafeConfigSource.src);
+
+    /* Init Firc. */
+    CLOCK_InitFirc(fircConfig);
+    /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
+    sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
+    CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
+    /* Wait for clock source switch finished. */
+    do
+    {
+         CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != sysClkSafeConfigSource.src);
+}
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Core_clock.outFreq, value: 48 MHz}
+- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
+- {id: SIRCDIV3_CLK.outFreq, value: 4 MHz}
+- {id: SIRC_CLK.outFreq, value: 8 MHz}
+- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
+- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
+- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
+- {id: Slow_clock.outFreq, value: 24 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
+- {id: SCG.SIRCDIV3.scale, value: '2', locked: true}
+- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
+- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
+- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
+sources:
+- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
+    {
+        .divSlow = kSCG_SysClkDivBy2,             /* Slow Clock Divider: divided by 2 */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+        .reserved1 = 0,
+        .reserved2 = 0,
+        .reserved3 = 0,
+#endif
+        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+        .reserved4 = 0,
+#endif
+        .src = kSCG_SysClkSrcFirc,                /* Fast IRC is selected as System Clock Source */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+        .reserved5 = 0,
+#endif
+    };
+const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 32768U,                           /* System Oscillator frequency: 32768Hz */
+        .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
+        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDivBy1,              /* System OSC Clock Divider 3: divided by 1 */
+        .capLoad = SCG_SYS_OSC_CAP_0P,            /* Oscillator capacity load: 0pF */
+        .workMode = kSCG_SysOscModeOscLowPower,   /* Oscillator low power */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDivBy2,              /* Slow IRC Clock Divider 3: divided by 2 */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,                       /* Fast IRC Trim disabled */
+    };
+const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = SCG_SPLL_DISABLE,           /* System PLL disabled */
+        .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 1: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 3: Clock output is disabled */
+        .src = kSCG_SysPllSrcSysOsc,              /* System PLL clock source is System OSC */
+        .prediv = 0,                              /* Divided by 1 */
+        .mult = 0,                                /* Multiply Factor is 16 */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    scg_sys_clk_config_t curConfig;
+
+    /* Init SOSC according to board configuration. */
+    CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
+    /* Set the XTAL0 frequency based on board settings. */
+    CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
+    /* Init FIRC. */
+    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
+    /* Init SIRC. */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
+    /* Set SCG to FIRC mode. */
+    CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
+    /* Wait for clock source switch finished. */
+    do
+    {
+         CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockHSRUN
+outputs:
+- {id: CLKOUT.outFreq, value: 8 MHz}
+- {id: Core_clock.outFreq, value: 96 MHz, locked: true, accuracy: '0.001'}
+- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
+- {id: PLLDIV1_CLK.outFreq, value: 96 MHz}
+- {id: PLLDIV3_CLK.outFreq, value: 96 MHz}
+- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
+- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
+- {id: SIRC_CLK.outFreq, value: 8 MHz}
+- {id: SOSCDIV1_CLK.outFreq, value: 32.768 kHz}
+- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
+- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
+- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
+- {id: Slow_clock.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SCGMode, value: SPLL}
+- {id: powerMode, value: HSRUN}
+- {id: CLKOUTConfig, value: 'yes'}
+- {id: SCG.DIVSLOW.scale, value: '4'}
+- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
+- {id: SCG.PREDIV.scale, value: '4'}
+- {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
+- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
+- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
+- {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
+- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
+- {id: SCG.SPLLDIV1.scale, value: '1', locked: true}
+- {id: SCG.SPLLDIV3.scale, value: '1', locked: true}
+- {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
+- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
+- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
+- {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
+sources:
+- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
+    {
+        .divSlow = kSCG_SysClkDivBy4,             /* Slow Clock Divider: divided by 4 */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+        .reserved1 = 0,
+        .reserved2 = 0,
+        .reserved3 = 0,
+#endif
+        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+        .reserved4 = 0,
+#endif
+        .src = kSCG_SysClkSrcSysPll,              /* System PLL is selected as System Clock Source */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+        .reserved5 = 0,
+#endif
+    };
+const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
+    {
+        .freq = 32768U,                           /* System Oscillator frequency: 32768Hz */
+        .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
+        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
+        .div1 = kSCG_AsyncClkDivBy1,              /* System OSC Clock Divider 1: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* System OSC Clock Divider 3: divided by 1 */
+        .capLoad = SCG_SYS_OSC_CAP_0P,            /* Oscillator capacity load: 0pF */
+        .workMode = kSCG_SysOscModeOscLowPower,   /* Oscillator low power */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 1: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
+    {
+        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,                       /* Fast IRC Trim disabled */
+    };
+const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN =
+    {
+        .enableMode = kSCG_SysPllEnable,          /* Enable SPLL clock */
+        .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
+        .div1 = kSCG_AsyncClkDivBy1,              /* System PLL Clock Divider 1: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* System PLL Clock Divider 3: divided by 1 */
+        .src = kSCG_SysPllSrcFirc,                /* System PLL clock source is Fast IRC */
+        .prediv = 3,                              /* Divided by 4 */
+        .mult = 0,                                /* Multiply Factor is 16 */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockHSRUN(void)
+{
+    scg_sys_clk_config_t curConfig;
+
+    /* Init SOSC according to board configuration. */
+    CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
+    /* Set the XTAL0 frequency based on board settings. */
+    CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
+    /* Init FIRC. */
+    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
+    /* Init SIRC. */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
+    /* Init SysPll. */
+    CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
+    /* Set HSRUN power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeHsrun(SMC);
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
+    {
+    }
+
+    /* Set SCG to SPLL mode. */
+    CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
+    /* Wait for clock source switch finished. */
+    do
+    {
+         CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
+    /* Set SCG CLKOUT selection. */
+    CLOCK_CONFIG_SetScgOutSel(SCG_CLKOUTCNFG_SIRC);
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Core_clock.outFreq, value: 8 MHz, locked: true, accuracy: '0.001'}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: SIRC_CLK.outFreq, value: 8 MHz}
+- {id: Slow_clock.outFreq, value: 1 MHz, locked: true, accuracy: '0.001'}
+- {id: System_clock.outFreq, value: 8 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: powerMode, value: VLPR}
+- {id: SCG.DIVSLOW.scale, value: '8'}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCLPEN_CFG, value: Enabled}
+sources:
+- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
+    {
+        .divSlow = kSCG_SysClkDivBy8,             /* Slow Clock Divider: divided by 8 */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+        .reserved1 = 0,
+        .reserved2 = 0,
+        .reserved3 = 0,
+#endif
+        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+        .reserved4 = 0,
+#endif
+        .src = kSCG_SysClkSrcSirc,                /* Slow IRC is selected as System Clock Source */
+#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
+        .reserved5 = 0,
+#endif
+    };
+const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 0U,                               /* System Oscillator frequency: 0Hz */
+        .enableMode = SCG_SOSC_DISABLE,           /* System OSC disabled */
+        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 3: Clock output is disabled */
+        .capLoad = SCG_SYS_OSC_CAP_0P,            /* Oscillator capacity load: 0pF */
+        .workMode = kSCG_SysOscModeExt,           /* Use external clock */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 3: Clock output is disabled */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
+    {
+        .enableMode = kSCG_FircEnable | kSCG_FircEnableInLowPower,/* Enable FIRC clock, Enable FIRC in low power mode */
+        .div1 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 1: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 3: Clock output is disabled */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,                       /* Fast IRC Trim disabled */
+    };
+const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR =
+    {
+        .enableMode = SCG_SPLL_DISABLE,           /* System PLL disabled */
+        .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 1: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 3: Clock output is disabled */
+        .src = kSCG_SysPllSrcSysOsc,              /* System PLL clock source is System OSC */
+        .prediv = 0,                              /* Divided by 1 */
+        .mult = 0,                                /* Multiply Factor is 16 */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Init FIRC. */
+    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockVLPR);
+    /* Init SIRC. */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
+    /* Allow SMC all power modes. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeVlpr(SMC);
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h
new file mode 100644
index 000000000..c01d5e03c
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2019 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                            32768U  /*!< Board xtal0 frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
+
+/*! @brief SCG set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
+/*! @brief System OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
+/*! @brief SIRC set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
+/*! @brief FIRC set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
+extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockRUN;
+/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
+ */
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK            96000000U  /*!< Core clock frequency: 96000000Hz */
+
+/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
+/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
+/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
+/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
+extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockHSRUN;
+/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
+ */
+
+/*******************************************************************************
+ * API for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockHSRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              8000000U  /*!< Core clock frequency: 8000000Hz */
+
+/*! @brief SCG set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
+/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
+/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
+/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
+extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockVLPR;
+/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
+ */
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.cmake b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.cmake
new file mode 100644
index 000000000..2ec2acace
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT K32L2B31A)
+
+set(JLINK_DEVICE K32L2B31xxxxA)
+set(PYOCD_TARGET K32L2B)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/K32L2B31xxxxA_flash.ld)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_K32L2B31VLH0A
+    )
+endfunction()
diff --git a/hw/bsp/frdm_k32l2b/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h
similarity index 65%
rename from hw/bsp/frdm_k32l2b/board.h
rename to hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h
index 825367915..854340d6d 100644
--- a/hw/bsp/frdm_k32l2b/board.h
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -24,12 +24,18 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Freedom K32L2B3
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3
+*/
 
 #ifndef BOARD_H_
 #define BOARD_H_
 
 #include "fsl_device_registers.h"
 
+#define USB_CLOCK_SOURCE kCLOCK_UsbSrcIrc48M
+
 // LED
 #define LED_PIN_CLOCK         kCLOCK_PortD
 #define LED_GPIO              GPIOD
@@ -52,5 +58,25 @@
 #define UART_PIN_TX           2u
 #define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */
 #define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */
+#define UART_CLOCK_SOURCE_HZ  CLOCK_GetFreq(kCLOCK_McgIrc48MClk)
+
+static inline void BOARD_InitBootPins(void) {
+  /* PORTA1 (pin 23) is configured as LPUART0_RX */
+  PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2);
+  /* PORTA2 (pin 24) is configured as LPUART0_TX */
+  PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2);
+
+  SIM->SOPT5 = ((SIM->SOPT5 &
+                 /* Mask bits to zero which are setting */
+                 (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
+                /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
+                | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
+                /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
+                | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
+
+  BOARD_BootClockRUN();
+  SystemCoreClockUpdate();
+  CLOCK_SetLpuart0Clock(1);
+}
 
 #endif /* BOARD_H_ */
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
new file mode 100644
index 000000000..9cf36c500
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
@@ -0,0 +1,18 @@
+MCU = K32L2B31A
+
+CFLAGS += -DCPU_K32L2B31VLH0A
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
+
+# All source paths should be relative to the top level.
+LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = K32L2B31xxxxA
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2B
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
new file mode 100644
index 000000000..86eb42ef8
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2019 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: K32L2B31xxxxA
+package_id: K32L2B31VLH0A
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+board: FRDM-K32L2B
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_smc.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_OSC32KCLK_CLK                       0U  /*!< OSC32KSEL select: OSC32KCLK clock */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+//extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 24 MHz}
+- {id: Core_clock.outFreq, value: 48 MHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 8 MHz}
+- {id: MCGPCLK.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: MCGMode, value: HIRC}
+- {id: MCG.CLKS.sel, value: MCG.HIRC}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
+- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
+- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
+sources:
+- {id: MCG.HIRC.outFreq, value: 48 MHz}
+- {id: OSC.OSC.outFreq, value: 32 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN =
+    {
+        .outSrc = kMCGLITE_ClkSrcHirc,            /* MCGOUTCLK source is HIRC */
+        .irclkEnableMode = kMCGLITE_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCGLITE_Lirc8M,                  /* Slow internal reference (LIRC) 8 MHz clock selected */
+        .fcrdiv = kMCGLITE_LircDivBy1,            /* Low-frequency Internal Reference Clock Divider: divided by 1 */
+        .lircDiv2 = kMCGLITE_LircDivBy1,          /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
+        .hircEnableInNotHircMode = true,          /* HIRC source is enabled */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
+        .clkdiv1 = 0x10000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 0U,                               /* Oscillator frequency: 0Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to HIRC mode. */
+    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 1 MHz}
+- {id: Core_clock.outFreq, value: 2 MHz}
+- {id: Flash_clock.outFreq, value: 1 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 2 MHz}
+- {id: System_clock.outFreq, value: 2 MHz}
+settings:
+- {id: MCGMode, value: LIRC2M}
+- {id: powerMode, value: VLPR}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: RTCCLKOUTConfig, value: 'yes'}
+- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
+- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
+sources:
+- {id: MCG.LIRC.outFreq, value: 2 MHz}
+- {id: OSC.OSC.outFreq, value: 32.768 kHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR =
+    {
+        .outSrc = kMCGLITE_ClkSrcLirc,            /* MCGOUTCLK source is LIRC */
+        .irclkEnableMode = kMCGLITE_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCGLITE_Lirc2M,                  /* Slow internal reference (LIRC) 2 MHz clock selected */
+        .fcrdiv = kMCGLITE_LircDivBy1,            /* Low-frequency Internal Reference Clock Divider: divided by 1 */
+        .lircDiv2 = kMCGLITE_LircDivBy1,          /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
+        .hircEnableInNotHircMode = false,         /* HIRC source is not enabled */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
+    {
+        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
+        .clkdiv1 = 0x10000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 0U,                               /* Oscillator frequency: 0Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to LIRC2M mode. */
+    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h
new file mode 100644
index 000000000..37328e7d8
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2019 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
+
+/*! @brief MCG lite set for BOARD_BootClockRUN configuration.
+ */
+extern const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              2000000U  /*!< Core clock frequency: 2000000Hz */
+
+/*! @brief MCG lite set for BOARD_BootClockVLPR configuration.
+ */
+extern const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR;
+/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
+/*! @brief OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.cmake b/hw/bsp/kinetis_k32l2/boards/kuiic/board.cmake
new file mode 100644
index 000000000..cf14000ac
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT K32L2B31A)
+
+set(JLINK_DEVICE K32L2B31xxxxA)
+set(PYOCD_TARGET K32L2B)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/kuiic.ld)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_K32L2B31VLH0A
+    )
+endfunction()
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.h b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h
new file mode 100644
index 000000000..f5895fc65
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h
@@ -0,0 +1,69 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Kuiic
+   url: https://github.com/nxf58843/kuiic
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "fsl_device_registers.h"
+
+#define USB_CLOCK_SOURCE kCLOCK_UsbSrcIrc48M
+
+// LED
+#define LED_PIN_CLOCK         kCLOCK_PortA
+#define LED_GPIO              GPIOA
+#define LED_PORT              PORTA
+#define LED_PIN               2
+#define LED_STATE_ON          1
+
+// UART
+#define UART_PORT             LPUART1
+#define UART_PIN_RX           3u
+#define UART_PIN_TX           0u
+
+#define UART_CLOCK_SOURCE_HZ  CLOCK_GetFreq(kCLOCK_McgIrc48MClk)
+
+static inline void BOARD_InitBootPins(void) {
+  /* PORTC3 is configured as LPUART0_RX */
+  PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3);
+  /* PORTA2 (pin 24) is configured as LPUART0_TX */
+  PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
+
+  SIM->SOPT5 = ((SIM->SOPT5 &
+                 /* Mask bits to zero which are setting */
+                 (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK)))
+                /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
+                | SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX)
+                /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
+                | SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX));
+  CLOCK_SetLpuart1Clock(1);
+}
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
new file mode 100644
index 000000000..2bc5b1e34
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
@@ -0,0 +1,18 @@
+MCU = K32L2B31A
+
+CFLAGS += -DCPU_K32L2B31VLH0A
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/kuiic.ld
+
+# For flash-jlink target
+JLINK_DEVICE = K32L2B31xxxxA
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2B
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.c b/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.c
new file mode 100644
index 000000000..c1a6d1a8d
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.c
@@ -0,0 +1,39 @@
+#include "clock_config.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+// extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
+    .outSrc          = kMCGLITE_ClkSrcHirc,  /* MCGOUTCLK source is HIRC */
+    .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCGLITE_Lirc8M,      /* Slow internal reference (LIRC) 8 MHz clock selected */
+    .fcrdiv          = kMCGLITE_LircDivBy1,  /* Low-frequency Internal Reference Clock Divider: divided by 1 */
+    .lircDiv2        = kMCGLITE_LircDivBy1,  /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
+    .hircEnableInNotHircMode = true,         /* HIRC source is enabled */
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+    .er32kSrc = SIM_OSC32KSEL_LPO_CLK,       /* OSC32KSEL select: LPO clock */
+    .clkdiv1  = 0x10000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
+};
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+  /* Set the system clock dividers in SIM to safe value. */
+  CLOCK_SetSimSafeDivs();
+  /* Set MCG to HIRC mode. */
+  CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
+  /* Set the clock configuration in SIM module. */
+  CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+  /* Set SystemCoreClock variable. */
+  SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.h b/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.h
new file mode 100644
index 000000000..920cad98f
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.h
@@ -0,0 +1,14 @@
+#ifndef CLOCK_CONFIG_H
+#define CLOCK_CONFIG_H
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SIM_OSC32KSEL_LPO_CLK         3U        /*!< OSC32KSEL select: LPO clock */
+#define SOPT5_LPUART1RXSRC_LPUART_RX  0x00u     /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */
+#define SOPT5_LPUART1TXSRC_LPUART_TX  0x00u     /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
+
+void BOARD_BootClockRUN(void);
+
+#endif
diff --git a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.ld
similarity index 99%
rename from hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
rename to hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.ld
index 5420ffc00..f478a99c7 100644
--- a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.ld
@@ -214,4 +214,3 @@ SECTIONS
 
   ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
 }
-
diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis_k32l2/family.c
similarity index 59%
rename from hw/bsp/frdm_k32l2b/frdm_k32l2b.c
rename to hw/bsp/kinetis_k32l2/family.c
index 924bb18e9..2fcc1b2af 100644
--- a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
+++ b/hw/bsp/kinetis_k32l2/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -25,61 +25,61 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
-#include "board.h"
+/* metadata:
+   manufacturer: NXP
+*/
+
 #include "fsl_gpio.h"
 #include "fsl_port.h"
 #include "fsl_clock.h"
 #include "fsl_lpuart.h"
 
 #include "clock_config.h"
+#include "bsp/board_api.h"
+#include "board.h"
+
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
+void USB0_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void board_init(void)
-{
-  /* Enable port clocks for UART/LED/Button pins */
-  CLOCK_EnableClock(UART_PIN_CLOCK);
-  CLOCK_EnableClock(LED_PIN_CLOCK);
-  CLOCK_EnableClock(BUTTON_PIN_CLOCK);
+void board_init(void) {
+  /* Enable port clocks for GPIO pins */
+  CLOCK_EnableClock(kCLOCK_PortA);
+  CLOCK_EnableClock(kCLOCK_PortB);
+  CLOCK_EnableClock(kCLOCK_PortC);
+  CLOCK_EnableClock(kCLOCK_PortD);
+  CLOCK_EnableClock(kCLOCK_PortE);
 
-  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
+  BOARD_InitBootPins();
+  BOARD_BootClockRUN();
+  SystemCoreClockUpdate();
+
+  gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0};
   GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
   PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio);
 
-  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
+#ifdef BUTTON_PIN
+  gpio_pin_config_t button_config = {kGPIO_DigitalInput, 0};
   GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
   const port_pin_config_t BUTTON_CFG = {
-    kPORT_PullUp, 
-    kPORT_FastSlewRate, 
-    kPORT_PassiveFilterDisable, 
-    kPORT_LowDriveStrength, 
-    kPORT_MuxAsGpio
+      kPORT_PullUp,
+      kPORT_FastSlewRate,
+      kPORT_PassiveFilterDisable,
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+      kPORT_OpenDrainDisable,
+#endif
+      kPORT_LowDriveStrength,
+      kPORT_MuxAsGpio,
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+      kPORT_UnlockRegister
+#endif
   };
   PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
-
-  /* PORTA1 (pin 23) is configured as LPUART0_RX */
-  PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2);
-  /* PORTA2 (pin 24) is configured as LPUART0_TX */
-  PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2);
-  
-  SIM->SOPT5 = ((SIM->SOPT5 &
-               /* Mask bits to zero which are setting */
-               (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
-               /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
-               | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
-               /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
-               | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
-
-  BOARD_BootClockRUN();
-  SystemCoreClockUpdate();
-  CLOCK_SetLpuart0Clock(1);
+#endif
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -94,47 +94,81 @@ void board_init(void)
   uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
   uart_config.enableTx = true;
   uart_config.enableRx = true;
-  LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk));
+  LPUART_Init(UART_PORT, &uart_config, UART_CLOCK_SOURCE_HZ);
 
   // USB
-  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
+  CLOCK_EnableUsbfs0Clock(USB_CLOCK_SOURCE, 48000000U);
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
+#ifdef BUTTON_PIN
   return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+#else
+  return 0;
+#endif
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
+#if 0 /*
+	Use this version if want the LED to blink during BOARD=board_test,
+	without having to hit a key.
+      */
+  if( 0U != (kLPUART_RxDataRegFullFlag & LPUART_GetStatusFlags( UART_PORT )) )
+    {
+      LPUART_ReadBlocking(UART_PORT, buf, len);
+      return len;
+    }
+
+  return( 0 );
+#else /* Wait for 'len' characters to come in */
+
   LPUART_ReadBlocking(UART_PORT, buf, len);
   return len;
+
+#endif
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
   LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
   return len;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
+#endif
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void	_exit (int __status) {
+  while (1) {}
+}
+#endif
+
 #endif
diff --git a/hw/bsp/kinetis_k32l2/family.cmake b/hw/bsp/kinetis_k32l2/family.cmake
new file mode 100644
index 000000000..946614a03
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/family.cmake
@@ -0,0 +1,111 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS KINETIS_K32L CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __STARTUP_CLEAR_BSS
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/gpio
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/port
+    ${SDK_DIR}/drivers/smc
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K32L)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/nxp/khci/dcd_khci.c
+    ${TOP}/src/portable/nxp/khci/hcd_khci.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  family_add_bin_hex(${TARGET})
+
+  if (DEFINED TEENSY_MCU)
+    family_flash_teensy(${TARGET})
+  endif ()
+endfunction()
diff --git a/hw/bsp/kinetis_k32l2/family.mk b/hw/bsp/kinetis_k32l2/family.mk
new file mode 100644
index 000000000..e18348d4d
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/family.mk
@@ -0,0 +1,35 @@
+UF2_FAMILY_ID = 0x7f83e793
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
+CFLAGS += \
+	-DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32L
+
+LDFLAGS_GCC += \
+  -nostartfiles \
+  -specs=nosys.specs -specs=nano.specs
+
+SRC_C += \
+	src/portable/nxp/khci/dcd_khci.c \
+	src/portable/nxp/khci/hcd_khci.c \
+	$(MCU_DIR)/system_$(MCU).c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/project_template \
+	$(TOP)/$(MCU_DIR)/drivers \
+	$(TOP)/$(SDK_DIR)/drivers/common \
+	$(TOP)/$(SDK_DIR)/drivers/gpio \
+	$(TOP)/$(SDK_DIR)/drivers/lpuart \
+	$(TOP)/$(SDK_DIR)/drivers/port \
+	$(TOP)/$(SDK_DIR)/drivers/smc \
+
+SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
diff --git a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..f2b3d649d
--- /dev/null
+++ b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.cmake b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.cmake
new file mode 100644
index 000000000..d34a56840
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT MKL25Z4)
+
+set(JLINK_DEVICE MKL25Z128xxx4)
+set(PYOCD_TARGET mkl25zl128)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../gcc/MKL25Z128xxx4_flash.ld)
+set(STARTUP_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../gcc/startup_MKL25Z4.S)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MKL25Z128VLK4
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h
new file mode 100644
index 000000000..b03fe91a8
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h
@@ -0,0 +1,63 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* metadata:
+   name: fomu
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
+#define LED_PORT              GPIOB
+#define LED_PIN_CLOCK         kCLOCK_PortB
+#define LED_PIN_PORT          PORTB
+#define LED_PIN               19U
+#define LED_PIN_FUNCTION      kPORT_MuxAsGpio
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN_CLOCK      kCLOCK_PortC
+#define BUTTON_PIN_PORT       PORTC
+#define BUTTON_PIN            9U
+#define BUTTON_PIN_FUNCTION   kPORT_MuxAsGpio
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_PORT             UART0
+#define UART_PIN_CLOCK        kCLOCK_PortA
+#define UART_PIN_PORT         PORTA
+#define UART_PIN_RX           1u
+#define UART_PIN_TX           2u
+#define UART_PIN_FUNCTION     kPORT_MuxAlt2
+#define SOPT5_UART0RXSRC_UART_RX      0x00u   /*!< UART0 receive data source select: UART0_RX pin */
+#define SOPT5_UART0TXSRC_UART_TX      0x00u   /*!< UART0 transmit data source select: UART0_TX pin */
+
+#endif
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
new file mode 100644
index 000000000..efd922c5e
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
@@ -0,0 +1,26 @@
+MCU = MKL25Z4
+
+CFLAGS += \
+  -DCPU_MKL25Z128VLK4 \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
+  -DCFG_EXAMPLE_MSC_READONLY
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls
+
+SRC_C += \
+	$(BOARD_PATH)/clock_config.c \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(FAMILY_PATH)/gcc/MKL25Z128xxx4_flash.ld
+
+SRC_S += $(FAMILY_PATH)/gcc/startup_$(MCU).S
+
+# For flash-jlink target
+JLINK_DEVICE = MKL25Z128xxx4
+
+# For flash-pyocd target
+PYOCD_TARGET = mkl25zl128
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c
new file mode 100644
index 000000000..deabe25aa
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!ClocksProfile
+product: Clocks v1.0
+processor: MKL25Z128xxx4
+package_id: MKL25Z128VLK4
+mcu_data: ksdk2_0
+processor_version: 1.1.0
+board: FRDM-KL25Z
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+#include "fsl_smc.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_PLL_DISABLE                                   0U  /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_LPO_CLK                             3U  /*!< OSC32KSEL select: LPO clock */
+#define SIM_PLLFLLSEL_MCGFLLCLK_CLK                       0U  /*!< PLLFLL select: MCGFLLCLK clock */
+#define SIM_PLLFLLSEL_MCGPLLCLK_CLK                       1U  /*!< PLLFLL select: MCGPLLCLK clock */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+//extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Code
+******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
+ * Description   : Configure FLL external reference divider (FRDIV).
+ * Param frdiv   : The value to set FRDIV.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
+{
+    MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 24 MHz}
+- {id: Core_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 8 MHz}
+- {id: PLLFLLCLK.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLL}
+- {id: MCG.PRDIV.scale, value: '2', locked: true}
+- {id: MCG.VDIV.scale, value: '24', locked: true}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: High}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
+- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: SIM.CLKOUTSEL.sel, value: SIM.OUTDIV4}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV1.scale, value: '2'}
+- {id: SIM.PLLFLLSEL.sel, value: SIM.MCGPLLCLK_DIV2}
+- {id: SIM.TPMSRCSEL.sel, value: SIM.PLLFLLSEL}
+- {id: SIM.UART0SRCSEL.sel, value: SIM.PLLFLLSEL}
+- {id: SIM.USBSRCSEL.sel, value: SIM.PLLFLLSEL}
+sources:
+- {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+    {
+        .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcSlow,                     /* Slow internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x1U,                    /* PLL Reference divider: divided by 2 */
+                .vdiv = 0x0U,                     /* VCO divider: multiplied by 24 */
+            },
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+        .er32kSrc = SIM_OSC32KSEL_LPO_CLK,        /* OSC32KSEL select: LPO clock */
+        .clkdiv1 = 0x10010000U,                   /* SIM_CLKDIV1 - OUTDIV1: /2, OUTDIV4: /2 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 8000000U,                         /* Oscillator frequency: 8000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(kMCG_OscselOsc,
+                        kMCG_PllClkSelPll0,
+                        &mcgConfig_BOARD_BootClockRUN.pll0Config);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
+                                  mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 800 kHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: Flash_clock.outFreq, value: 800 kHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: High}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+sources:
+- {id: OSC.OSC.outFreq, value: 8 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
+    {
+        .mcgMode = kMCG_ModeBLPI,                 /* BLPI - Bypassed Low Power Internal */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0x0U,                     /* VCO divider: multiplied by 24 */
+            },
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+        .er32kSrc = SIM_OSC32KSEL_LPO_CLK,        /* OSC32KSEL select: LPO clock */
+        .clkdiv1 = 0x40000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 0U,                               /* Oscillator frequency: 0Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
+                         mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h
new file mode 100644
index 000000000..1033d4e55
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#define BOARD_XTAL0_CLK_HZ                          8000000U  /*!< Board xtal0 frequency in Hz */
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              4000000U  /*!< Core clock frequency: 4000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockVLPR configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
+/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
+/*! @brief OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/kinetis_kl/family.c
similarity index 73%
rename from hw/bsp/frdm_kl25z/frdm_kl25z.c
rename to hw/bsp/kinetis_kl/family.c
index 8d93fdbaa..fe864f3a0 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/kinetis_kl/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -21,11 +21,14 @@
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+/* metadata:
+   manufacturer: NXP
+*/
+
+#include "bsp/board_api.h"
+#include "board.h"
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
 #include "fsl_port.h"
@@ -40,45 +43,13 @@
 void USB0_IRQHandler(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 #if CFG_TUD_ENABLED
   tud_int_handler(0);
 #endif
 }
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIOB
-#define LED_PIN_CLOCK         kCLOCK_PortB
-#define LED_PIN_PORT          PORTB
-#define LED_PIN               19U
-#define LED_PIN_FUNCTION      kPORT_MuxAsGpio
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN_CLOCK      kCLOCK_PortC
-#define BUTTON_PIN_PORT       PORTC
-#define BUTTON_PIN            9U
-#define BUTTON_PIN_FUNCTION   kPORT_MuxAsGpio
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             UART0
-#define UART_PIN_CLOCK        kCLOCK_PortA
-#define UART_PIN_PORT         PORTA
-#define UART_PIN_RX           1u
-#define UART_PIN_TX           2u
-#define UART_PIN_FUNCTION     kPORT_MuxAlt2
-#define SOPT5_UART0RXSRC_UART_RX      0x00u   /*!< UART0 receive data source select: UART0_RX pin */
-#define SOPT5_UART0TXSRC_UART_TX      0x00u   /*!< UART0 transmit data source select: UART0_TX pin */
-
-const uint8_t dcd_data[] = { 0x00 };
-
 void board_init(void)
 {
   BOARD_BootClockRUN();
@@ -103,7 +74,7 @@ void board_init(void)
   // Button
   CLOCK_EnableClock(BUTTON_PIN_CLOCK);
   port_pin_config_t button_port = {
-    .pullSelect = kPORT_PullUp, 
+    .pullSelect = kPORT_PullUp,
     .mux = BUTTON_PIN_FUNCTION,
   };
   PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port);
@@ -139,13 +110,13 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  GPIO_WritePinOutput(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
 }
 
 uint32_t board_button_read(void)
 {
 #if defined(BUTTON_PORT) && defined(BUTTON_PIN)
-  return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN);
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
 #endif
   return 0;
 }
@@ -174,3 +145,22 @@ uint32_t board_millis(void)
   return system_ticks;
 }
 #endif
+
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void	_exit (int __status) {
+  while (1) {}
+}
+#endif
+
+#endif
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
new file mode 100644
index 000000000..51a646258
--- /dev/null
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -0,0 +1,111 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/lpsci/fsl_lpsci.c
+    ${SDK_DIR}/drivers/uart/fsl_uart.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __STARTUP_CLEAR_BSS
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/gpio
+    ${SDK_DIR}/drivers/lpsci
+    ${SDK_DIR}/drivers/port
+    ${SDK_DIR}/drivers/smc
+    ${SDK_DIR}/drivers/uart
+    )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+    ${TOP}/src/portable/nxp/khci/hcd_khci.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/kinetis_kl/family.mk b/hw/bsp/kinetis_kl/family.mk
new file mode 100644
index 000000000..1fdce981a
--- /dev/null
+++ b/hw/bsp/kinetis_kl/family.mk
@@ -0,0 +1,37 @@
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
+
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
+CFLAGS += \
+  -D__STARTUP_CLEAR_BSS \
+  -DCFG_TUSB_MCU=OPT_MCU_KINETIS_KL \
+
+LDFLAGS += \
+  -nostartfiles \
+  -specs=nosys.specs -specs=nano.specs \
+  -Wl,--defsym,__stack_size__=0x400 \
+  -Wl,--defsym,__heap_size__=0
+
+SRC_C += \
+	src/portable/nxp/khci/dcd_khci.c \
+	src/portable/nxp/khci/hcd_khci.c \
+	$(MCU_DIR)/system_$(MCU).c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/lpsci/fsl_lpsci.c \
+	$(SDK_DIR)/drivers/uart/fsl_uart.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/drivers \
+	$(TOP)/$(SDK_DIR)/drivers/common \
+	$(TOP)/$(SDK_DIR)/drivers/gpio \
+	$(TOP)/$(SDK_DIR)/drivers/lpsci \
+	$(TOP)/$(SDK_DIR)/drivers/port \
+	$(TOP)/$(SDK_DIR)/drivers/smc \
+	$(TOP)/$(SDK_DIR)/drivers/uart \
diff --git a/hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld b/hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld
new file mode 100644
index 000000000..b38aa827c
--- /dev/null
+++ b/hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld
@@ -0,0 +1,253 @@
+/*
+** ###################################################################
+**     Processors:          MKL25Z128VFM4
+**                          MKL25Z128VFT4
+**                          MKL25Z128VLH4
+**                          MKL25Z128VLK4
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    KL25P80M48SF0RM, Rev.3, Sep 2012
+**     Version:             rev. 2.5, 2015-02-19
+**     Build:               b170214
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0200 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000200
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x0001FBF0
+  m_data                (RW)  : ORIGIN = 0x1FFFF000, LENGTH = 0x00004000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
diff --git a/hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S b/hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S
new file mode 100644
index 000000000..dc1438f3a
--- /dev/null
+++ b/hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S
@@ -0,0 +1,383 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL25Z4.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL25Z4                                                                     */
+/*  @version: 2.5                                                                         */
+/*  @date:    2015-2-19                                                                   */
+/*  @build:   b170112                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.                               */
+/* Copyright 2016 - 2017 NXP                                                              */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of the copyright holder nor the names of its                        */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA channel 0 transfer complete*/
+    .long   DMA1_IRQHandler                                 /* DMA channel 1 transfer complete*/
+    .long   DMA2_IRQHandler                                 /* DMA channel 2 transfer complete*/
+    .long   DMA3_IRQHandler                                 /* DMA channel 3 transfer complete*/
+    .long   Reserved20_IRQHandler                           /* Reserved interrupt*/
+    .long   FTFA_IRQHandler                                 /* Command complete and read collision*/
+    .long   LVD_LVW_IRQHandler                              /* Low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup Unit*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 single interrupt vector for all sources*/
+    .long   SPI1_IRQHandler                                 /* SPI1 single interrupt vector for all sources*/
+    .long   UART0_IRQHandler                                /* UART0 status and error*/
+    .long   UART1_IRQHandler                                /* UART1 status and error*/
+    .long   UART2_IRQHandler                                /* UART2 status and error*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   TPM0_IRQHandler                                 /* TPM0 single interrupt vector for all sources*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   RTC_IRQHandler                                  /* RTC alarm*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   PIT_IRQHandler                                  /* PIT interrupt*/
+    .long   Reserved39_IRQHandler                           /* Reserved interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   TSI0_IRQHandler                                 /* TSI0 interrupt*/
+    .long   MCG_IRQHandler                                  /* MCG interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTMR0 interrupt*/
+    .long   Reserved45_IRQHandler                           /* Reserved interrupt*/
+    .long   PORTA_IRQHandler                                /* PORTA Pin detect*/
+    .long   PORTD_IRQHandler                                /* PORTD Pin detect*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    .equ    VTOR, 0xE000ED08
+    ldr     r0, =VTOR
+    ldr     r1, =__isr_vector
+    str     r1, [r0]
+    ldr     r2, [r1]
+    msr     msp, r2
+#ifndef __NO_SYSTEM_INIT
+    ldr   r0,=SystemInit
+    blx   r0
+#endif
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble     .LC0
+
+.LC1:
+    subs    r3, 4
+    ldr    r0, [r1,r3]
+    str    r0, [r2,r3]
+    bgt    .LC1
+.LC0:
+
+#ifdef __STARTUP_CLEAR_BSS
+/*     This part of work usually is done in C library startup code. Otherwise,
+ *     define this macro to enable it in this startup.
+ *
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+
+    subs    r2, r1
+    ble .LC3
+
+    movs    r0, 0
+.LC2:
+    str r0, [r1, r2]
+    subs    r2, 4
+    bge .LC2
+.LC3:
+#endif
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr   r0,=__START
+    blx   r0
+#else
+    ldr   r0,=__libc_init_array
+    blx   r0
+    ldr   r0,=main
+    bx    r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA1_IRQHandler
+    .type DMA1_IRQHandler, %function
+DMA1_IRQHandler:
+    ldr   r0,=DMA1_DriverIRQHandler
+    bx    r0
+    .size DMA1_IRQHandler, . - DMA1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA2_IRQHandler
+    .type DMA2_IRQHandler, %function
+DMA2_IRQHandler:
+    ldr   r0,=DMA2_DriverIRQHandler
+    bx    r0
+    .size DMA2_IRQHandler, . - DMA2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA3_IRQHandler
+    .type DMA3_IRQHandler, %function
+DMA3_IRQHandler:
+    ldr   r0,=DMA3_DriverIRQHandler
+    bx    r0
+    .size DMA3_IRQHandler, . - DMA3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C0_IRQHandler
+    .type I2C0_IRQHandler, %function
+I2C0_IRQHandler:
+    ldr   r0,=I2C0_DriverIRQHandler
+    bx    r0
+    .size I2C0_IRQHandler, . - I2C0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C1_IRQHandler
+    .type I2C1_IRQHandler, %function
+I2C1_IRQHandler:
+    ldr   r0,=I2C1_DriverIRQHandler
+    bx    r0
+    .size I2C1_IRQHandler, . - I2C1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI0_IRQHandler
+    .type SPI0_IRQHandler, %function
+SPI0_IRQHandler:
+    ldr   r0,=SPI0_DriverIRQHandler
+    bx    r0
+    .size SPI0_IRQHandler, . - SPI0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI1_IRQHandler
+    .type SPI1_IRQHandler, %function
+SPI1_IRQHandler:
+    ldr   r0,=SPI1_DriverIRQHandler
+    bx    r0
+    .size SPI1_IRQHandler, . - SPI1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UART0_IRQHandler
+    .type UART0_IRQHandler, %function
+UART0_IRQHandler:
+    ldr   r0,=UART0_DriverIRQHandler
+    bx    r0
+    .size UART0_IRQHandler, . - UART0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UART1_IRQHandler
+    .type UART1_IRQHandler, %function
+UART1_IRQHandler:
+    ldr   r0,=UART1_DriverIRQHandler
+    bx    r0
+    .size UART1_IRQHandler, . - UART1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UART2_IRQHandler
+    .type UART2_IRQHandler, %function
+UART2_IRQHandler:
+    ldr   r0,=UART2_DriverIRQHandler
+    bx    r0
+    .size UART2_IRQHandler, . - UART2_IRQHandler
+
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    DMA0_DriverIRQHandler
+    def_irq_handler    DMA1_DriverIRQHandler
+    def_irq_handler    DMA2_DriverIRQHandler
+    def_irq_handler    DMA3_DriverIRQHandler
+    def_irq_handler    Reserved20_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    I2C0_DriverIRQHandler
+    def_irq_handler    I2C1_DriverIRQHandler
+    def_irq_handler    SPI0_DriverIRQHandler
+    def_irq_handler    SPI1_DriverIRQHandler
+    def_irq_handler    UART0_DriverIRQHandler
+    def_irq_handler    UART1_DriverIRQHandler
+    def_irq_handler    UART2_DriverIRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT_IRQHandler
+    def_irq_handler    Reserved39_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    Reserved45_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+
+    .end
diff --git a/hw/bsp/kuiic/board.mk b/hw/bsp/kuiic/board.mk
deleted file mode 100644
index 39e9d9deb..000000000
--- a/hw/bsp/kuiic/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR) tools/uf2
-
-# This board uses TinyUF2 for updates
-UF2_FAMILY_ID = 0x7f83e793
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_K32L2B31VLH0A \
-  -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
-
-# All source paths should be relative to the top level.
-LD_FILE = /hw/bsp/$(BOARD)/K32L2B31xxxxA_flash.ld
-
-SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	$(MCU_DIR)/system_K32L2B31A.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
-	$(TOP)/$(SDK_DIR)/drivers/smc \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/gpio \
-	$(TOP)/$(SDK_DIR)/drivers/port \
-	$(TOP)/$(SDK_DIR)/drivers/lpuart \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers 
-
-SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = K32L2B
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/hw/bsp/kuiic/kuiic.c b/hw/bsp/kuiic/kuiic.c
deleted file mode 100644
index 7aaa9e03c..000000000
--- a/hw/bsp/kuiic/kuiic.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- * Copyright (c) 2020, Koji Kitayama
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-#include "board.h"
-#include "fsl_smc.h"
-#include "fsl_gpio.h"
-#include "fsl_port.h"
-#include "fsl_clock.h"
-#include "fsl_lpuart.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define SIM_OSC32KSEL_LPO_CLK         3U        /*!< OSC32KSEL select: LPO clock */
-#define SOPT5_LPUART1RXSRC_LPUART_RX  0x00u     /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */
-#define SOPT5_LPUART1TXSRC_LPUART_TX  0x00u     /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-// extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- * Variables for BOARD_BootClockRUN configuration
- ******************************************************************************/
-const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
-    .outSrc          = kMCGLITE_ClkSrcHirc,  /* MCGOUTCLK source is HIRC */
-    .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
-    .ircs            = kMCGLITE_Lirc8M,      /* Slow internal reference (LIRC) 8 MHz clock selected */
-    .fcrdiv          = kMCGLITE_LircDivBy1,  /* Low-frequency Internal Reference Clock Divider: divided by 1 */
-    .lircDiv2        = kMCGLITE_LircDivBy1,  /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
-    .hircEnableInNotHircMode = true,         /* HIRC source is enabled */
-};
-const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
-    .er32kSrc = SIM_OSC32KSEL_LPO_CLK,       /* OSC32KSEL select: LPO clock */
-    .clkdiv1  = 0x10000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
-};
-
-/*******************************************************************************
- * Code for BOARD_BootClockRUN configuration
- ******************************************************************************/
-void BOARD_BootClockRUN(void)
-{
-    /* Set the system clock dividers in SIM to safe value. */
-    CLOCK_SetSimSafeDivs();
-    /* Set MCG to HIRC mode. */
-    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
-    /* Set the clock configuration in SIM module. */
-    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
-}
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void board_init(void)
-{
-  /* Enable port clocks for GPIO pins */
-  CLOCK_EnableClock(kCLOCK_PortA);
-  CLOCK_EnableClock(kCLOCK_PortB);
-  CLOCK_EnableClock(kCLOCK_PortC);
-  CLOCK_EnableClock(kCLOCK_PortD);
-  CLOCK_EnableClock(kCLOCK_PortE);
-
-  
-  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 };
-  GPIO_PinInit(GPIOA, 1U, &led_config);
-  PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio);  
-  led_config.outputLogic = 0;
-  GPIO_PinInit(GPIOA, 2U, &led_config);
-  PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio);
-
-#ifdef BUTTON_PIN
-  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
-  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
-  const port_pin_config_t BUTTON_CFG = {
-    kPORT_PullUp, 
-    kPORT_FastSlewRate, 
-    kPORT_PassiveFilterDisable, 
-    kPORT_LowDriveStrength, 
-    kPORT_MuxAsGpio
-  };
-  PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
-#endif
-
-  /* PORTC3 is configured as LPUART0_RX */
-  PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3);
-  /* PORTA2 (pin 24) is configured as LPUART0_TX */
-  PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
-  
-  SIM->SOPT5 = ((SIM->SOPT5 &
-               /* Mask bits to zero which are setting */
-               (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK)))
-               /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
-               | SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX)
-               /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
-               | SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX));
-
-  BOARD_BootClockRUN();
-  SystemCoreClockUpdate();
-  CLOCK_SetLpuart1Clock(1);
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  lpuart_config_t uart_config;
-  LPUART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx = true;
-  uart_config.enableRx = true;
-  LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk));
-
-  // USB
-  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  if (state) {
-    LED_GPIO->PDDR |= GPIO_FIT_REG((1UL << LED_PIN));
-  } else {
-    LED_GPIO->PDDR &= GPIO_FIT_REG(~(1UL << LED_PIN));
-  }
-//  GPIO_PinWrite(GPIOA, 1, state ? LED_STATE_ON : (1-LED_STATE_ON) );
-//  GPIO_PinWrite(GPIOA, 2, state ? (1-LED_STATE_ON) : LED_STATE_ON );
-}
-
-uint32_t board_button_read(void)
-{
-#ifdef BUTTON_PIN
-  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
-#else
-  return 0;
-#endif
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  LPUART_ReadBlocking(UART_PORT, buf, len);
-  return len;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h
similarity index 84%
rename from examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
rename to hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h
index bfdf1e926..0e0721674 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,25 +42,29 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// Include MCU header
-#include "bsp/board_mcu.h"
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #ifdef __GNUC__
+    #pragma GCC diagnostic push
+    #pragma GCC diagnostic ignored "-Wunused-parameter"
+  #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
-#error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
-#endif
+  #include "chip.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
-  // TODO fix/remove later  
-  extern u32 SystemCoreClock;
-#else
-  extern uint32_t SystemCoreClock;
+  #ifdef __GNUC__
+    #pragma GCC diagnostic pop
+  #endif
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU								        0
-#define configENABLE_FPU								        1
-#define configENABLE_TRUSTZONE					        0
-#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
@@ -68,7 +72,7 @@
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
 #define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( 0*1024 ) // dynamic is not used
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
 #define configIDLE_SHOULD_YIELD                 1
@@ -90,9 +94,11 @@
 #define configUSE_TICK_HOOK                    0
 #define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
 #define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
 
 /* Run time and task stats gathering related definitions. */
 #define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
 #define configUSE_TRACE_FACILITY               1 // legacy trace
 #define configUSE_STATS_FORMATTING_FUNCTIONS   0
 
@@ -115,7 +121,7 @@
 #define INCLUDE_vTaskDelayUntil                1
 #define INCLUDE_vTaskDelay                     1
 #define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
 #define INCLUDE_uxTaskGetStackHighWaterMark    0
 #define INCLUDE_xTaskGetIdleTaskHandle         0
 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
@@ -141,16 +147,6 @@
   #define configASSERT( x )
 #endif
 
-#ifdef __RX__
-/* Renesas RX series */
-#define vSoftwareInterruptISR					INT_Excep_ICU_SWINT
-#define vTickISR								INT_Excep_CMT0_CMI0
-#define configPERIPHERAL_CLOCK_HZ				(configCPU_CLOCK_HZ/2)
-#define configKERNEL_INTERRUPT_PRIORITY			1
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
-
-#else
-
 /* FreeRTOS hooks to NVIC vectors */
 #define xPortPendSVHandler    PendSV_Handler
 #define xPortSysTickHandler   SysTick_Handler
@@ -159,15 +155,9 @@
 //--------------------------------------------------------------------+
 // Interrupt nesting behavior configuration.
 //--------------------------------------------------------------------+
-#if defined(__NVIC_PRIO_BITS)
-  // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
-	#define configPRIO_BITS       __NVIC_PRIO_BITS
-#elif defined(__ECLIC_INTCTLBITS)
-  // RISC-V Bumblebee core from nuclei
-  #define configPRIO_BITS       __ECLIC_INTCTLBITS
-#else
-  #error "FreeRTOS configPRIO_BITS to be defined"
-#endif
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
 
 /* The lowest interrupt priority that can be used in a call to a "set priority" function. */
 #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
@@ -186,6 +176,4 @@ to all Cortex-M ports, and do not rely on any particular library functions. */
 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
 
-#endif
-
 #endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.cmake b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.cmake
new file mode 100644
index 000000000..12f75cd08
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.cmake
@@ -0,0 +1,19 @@
+set(LPC_FAMILY 11xx)
+set(JLINK_DEVICE LPC11U37/401)
+set(PYOCD_TARGET lpc11u37)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc11u37.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+  target_sources(${TARGET} PRIVATE
+    ${SDK_DIR}/src/gpio_${LPC_FAMILY}_1.c
+    ${SDK_DIR}/src/sysctl_${LPC_FAMILY}.c
+    )
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=unused-parameter
+    )
+endfunction()
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h
new file mode 100644
index 000000000..c8a48eecb
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h
@@ -0,0 +1,103 @@
+/* metadata:
+   name: LPCXpresso11U37
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13074
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PORT              1
+#define LED_PIN               24
+#define LED_STATE_ON          0
+
+// Wake up Switch
+#define BUTTON_PORT           0
+#define BUTTON_PIN            16
+#define BUTTON_STATE_ACTIVE   0
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t ExtRateIn = 0;
+
+/* Pin muxing table, only items that need changing from their default pin
+   state are in this table. Not every pin is mapped. */
+/* IOCON pin definitions for pin muxing */
+typedef struct {
+  uint32_t port : 8;			/* Pin port */
+  uint32_t pin : 8;			/* Pin number */
+  uint32_t modefunc : 16;		/* Function and mode */
+} PINMUX_GRP_T;
+
+static const PINMUX_GRP_T pinmuxing[] = {
+    {0,  3, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
+    {0,  6, (IOCON_FUNC1 | IOCON_MODE_INACT)},		/* PIO0_6 used for USB_CONNECT */
+
+    {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
+    {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
+};
+
+/* Setup system clocking */
+static inline void Chip_SetupXtalClocking(void) {
+  volatile int i;
+
+  /* Powerup main oscillator */
+  Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
+
+  /* Wait 200us for OSC to be stablized, no status
+     indication, dummy wait. */
+  for (i = 0; i < 0x100; i++) {}
+
+  /* Set system PLL input to main oscillator */
+  Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
+
+  /* Power down PLL to change the PLL divider ratio */
+  Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
+
+  /* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
+     MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
+     FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
+     FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
+  Chip_Clock_SetupSystemPLL(3, 1);
+
+  /* Powerup system PLL */
+  Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
+
+  /* Wait for PLL to lock */
+  while (!Chip_Clock_IsSystemPLLLocked()) {}
+
+  /* Set system clock divider to 1 */
+  Chip_Clock_SetSysClockDiv(1);
+
+  /* Setup FLASH access to 3 clocks */
+  Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
+
+  /* Set main clock source to the system PLL. This will drive 48MHz
+     for the main clock and 48MHz for the system clock */
+  Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
+
+  /* Set USB PLL input to main oscillator */
+  Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
+  /* Setup USB PLL  (FCLKIN = 12MHz) * 4 = 48MHz
+     MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
+     FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
+     FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
+  Chip_Clock_SetupUSBPLL(3, 1);
+
+  /* Powerup USB PLL */
+  Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
+
+  /* Wait for PLL to lock */
+  while (!Chip_Clock_IsUSBPLLLocked()) {}
+}
+
+static inline void Chip_USB_Init(void) {
+  /* enable USB main clock */
+  Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);
+  /* Enable AHB clock to the USB block and USB RAM. */
+  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
+  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USBRAM);
+  /* power UP USB Phy */
+  Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);
+}
+
+#endif
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
new file mode 100644
index 000000000..fdc17374b
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
@@ -0,0 +1,24 @@
+MCU = 11uxx
+MCU_DRV = 11xx
+
+CFLAGS += \
+  -DCORE_M0 \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'
+
+# mcu driver cause following warnings
+CFLAGS += \
+	-Wno-error=strict-prototypes \
+	-Wno-error=unused-parameter \
+	-Wno-error=redundant-decls
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc11u37.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC11U37/401
+PYOCD_TARGET = lpc11u37
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/lpcxpresso11u37/lpc11u37.ld b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
similarity index 82%
rename from hw/bsp/lpcxpresso11u37/lpc11u37.ld
rename to hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
index 6a2dfb7f5..8e0a4e4c6 100644
--- a/hw/bsp/lpcxpresso11u37/lpc11u37.ld
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
@@ -12,24 +12,24 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */  
-  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */  
-  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */  
+  MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */
+  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
+  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash128 = 0x0  ; /* MFlash128 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */  
-  __top_Flash = 0x0 + 0x20000 ; /* 128K bytes */  
-  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */  
-  __base_RAM2 = 0x20004000 ; /* RAM2 */  
-  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */  
+  __base_MFlash128 = 0x0  ; /* MFlash128 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */
+  __top_Flash = 0x0 + 0x20000 ; /* 128K bytes */
+  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
+  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
+  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */
+  __base_RAM2 = 0x20004000 ; /* RAM2 */
+  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
+  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
 
 
 ENTRY(ResetISR)
@@ -74,9 +74,9 @@ SECTIONS
     } > MFlash128
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash128
@@ -88,9 +88,9 @@ SECTIONS
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
     } > MFlash128
     __exidx_end = .;
- 
+
     _etext = .;
-        
+
     /* DATA section for RamUsb2 */
 
     .data_RAM2 : ALIGN(4)
@@ -176,11 +176,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) 
-                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
+                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
                                          )
            );
 
@@ -192,4 +192,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.cmake b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.cmake
new file mode 100644
index 000000000..b7393cb2f
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.cmake
@@ -0,0 +1,12 @@
+set(LPC_FAMILY 11u6x)
+set(JLINK_DEVICE LPC11U68)
+set(PYOCD_TARGET LPC11U68)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc11u68.ld)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${SDK_DIR}/src/gpio_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/syscon_${LPC_FAMILY}.c
+    )
+endfunction()
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h
new file mode 100644
index 000000000..50141e4a5
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h
@@ -0,0 +1,32 @@
+/* metadata:
+  name: LPCXpresso11U68
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13058
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PORT              2
+#define LED_PIN               17
+#define LED_STATE_ON          0
+
+// Wake up Switch
+#define BUTTON_PORT           0
+#define BUTTON_PIN            16
+#define BUTTON_STATE_ACTIVE   0
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t RTCOscRateIn = 32768;
+
+/* Pin muxing table, only items that need changing from their default pin
+   state are in this table. Not every pin is mapped. */
+static const PINMUX_GRP_T pinmuxing[] = {
+    {0, 3,  (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
+    {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
+    {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
+    {2, 0,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALIN
+    {2, 1,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALOUT
+};
+
+#endif
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
new file mode 100644
index 000000000..cf095c347
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
@@ -0,0 +1,17 @@
+MCU = 11u6x
+MCU_DRV = 11u6x
+
+CFLAGS += \
+  -DCORE_M0PLUS \
+  -D__VTOR_PRESENT=0 \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc11u68.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC11U68
+PYOCD_TARGET = lpc11u68
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/lpcxpresso11u68/lpc11u68.ld b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpc11u68.ld
similarity index 81%
rename from hw/bsp/lpcxpresso11u68/lpc11u68.ld
rename to hw/bsp/lpc11/boards/lpcxpresso11u68/lpc11u68.ld
index 56d9e4b89..4a35b192e 100644
--- a/hw/bsp/lpcxpresso11u68/lpc11u68.ld
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpc11u68.ld
@@ -11,29 +11,29 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */  
-  Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */  
-  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */  
+  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
+  Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
+  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash256 = 0x0  ; /* MFlash256 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */  
-  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */  
-  __base_Ram0_32 = 0x10000000  ; /* Ram0_32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_Ram0_32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_Ram1_2 = 0x20000000  ; /* Ram1_2 */  
-  __base_RAM2 = 0x20000000 ; /* RAM2 */  
-  __top_Ram1_2 = 0x20000000 + 0x800 ; /* 2K bytes */  
-  __top_RAM2 = 0x20000000 + 0x800 ; /* 2K bytes */  
-  __base_Ram2USB_2 = 0x20004000  ; /* Ram2USB_2 */  
-  __base_RAM3 = 0x20004000 ; /* RAM3 */  
-  __top_Ram2USB_2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __top_RAM3 = 0x20004000 + 0x800 ; /* 2K bytes */  
+  __base_MFlash256 = 0x0  ; /* MFlash256 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
+  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
+  __base_Ram0_32 = 0x10000000  ; /* Ram0_32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_Ram0_32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_Ram1_2 = 0x20000000  ; /* Ram1_2 */
+  __base_RAM2 = 0x20000000 ; /* RAM2 */
+  __top_Ram1_2 = 0x20000000 + 0x800 ; /* 2K bytes */
+  __top_RAM2 = 0x20000000 + 0x800 ; /* 2K bytes */
+  __base_Ram2USB_2 = 0x20004000  ; /* Ram2USB_2 */
+  __base_RAM3 = 0x20004000 ; /* RAM3 */
+  __top_Ram2USB_2 = 0x20004000 + 0x800 ; /* 2K bytes */
+  __top_RAM3 = 0x20004000 + 0x800 ; /* 2K bytes */
 
 ENTRY(ResetISR)
 
@@ -82,9 +82,9 @@ SECTIONS
     } > MFlash256
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash256
@@ -98,7 +98,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* possible MTB section for Ram1_2 */
     .mtb_buffer_RAM2 (NOLOAD) :
     {
@@ -172,7 +172,7 @@ SECTIONS
        *(.bss.$Ram1_2*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > Ram1_2 
+    } > Ram1_2
 
     /* BSS section for Ram2USB_2 */
     .bss_RAM3 : ALIGN(4)
@@ -182,7 +182,7 @@ SECTIONS
        *(.bss.$Ram2USB_2*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM3 = .) ;
-    } > Ram2USB_2 
+    } > Ram2USB_2
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -201,7 +201,7 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$Ram1_2*)
        . = ALIGN(4) ;
-    } > Ram1_2 
+    } > Ram1_2
 
     /* NOINIT section for Ram2USB_2 */
     .noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -209,13 +209,13 @@ SECTIONS
        *(.noinit.$RAM3*)
        *(.noinit.$Ram2USB_2*)
        . = ALIGN(4) ;
-    } > Ram2USB_2 
+    } > Ram2USB_2
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > Ram0_32
@@ -223,11 +223,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) 
-                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
+                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
                                          )
            );
 
@@ -239,4 +239,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c b/hw/bsp/lpc11/family.c
similarity index 67%
rename from hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
rename to hw/bsp/lpc11/family.c
index e33a5c6e5..b5371632c 100644
--- a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
+++ b/hw/bsp/lpc11/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,55 +24,50 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: NXP
+*/
+
+#ifdef __GNUC__
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 #include "chip.h"
-#include "../board.h"
+
+#ifdef __GNUC__
+  #pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+extern void USB_IRQHandler(void);
+extern void SysTick_Handler(void);
+void SystemInit(void);
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   tud_int_handler(0);
 }
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
-#define LED_PORT              2
-#define LED_PIN               17
-#define LED_STATE_ON          0
-
-// Wake up Switch
-#define BUTTON_PORT           0
-#define BUTTON_PIN            16
-#define BUTTON_STATE_ACTIVE   0
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing table, only items that need changing from their default pin
-   state are in this table. Not every pin is mapped. */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {0, 3,  (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
-  {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
-  {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
-  {2, 0,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALIN
-  {2, 1,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALOUT
-};
 
 // Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
   /* Enable IOCON clock */
   Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+  for (uint32_t i = 0; i < (sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); i++) {
+    Chip_IOCON_PinMuxSet(LPC_IOCON, pinmuxing[i].port, pinmuxing[i].pin, pinmuxing[i].modefunc);
+  }
   Chip_SetupXtalClocking();
 }
 
-void board_init(void)
-{
+void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -99,37 +94,42 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  if ( max_len < 16 ) return 0;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  id32[0] = Chip_IAP_ReadUID();
+  return 4;
+}
+
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
diff --git a/hw/bsp/lpc11/family.cmake b/hw/bsp/lpc11/family.cmake
new file mode 100644
index 000000000..6781b20c6
--- /dev/null
+++ b/hw/bsp/lpc11/family.cmake
@@ -0,0 +1,108 @@
+include_guard()
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+if (LPC_FAMILY STREQUAL 11xx)
+  set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc11uxx/lpc_chip_11uxx)
+else()
+  set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc${LPC_FAMILY}/lpc_chip_${LPC_FAMILY})
+endif()
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC11UXX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc${LPC_FAMILY}.c
+    ${SDK_DIR}/src/chip_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/clock_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/iap.c
+    ${SDK_DIR}/src/iocon_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/sysinit_${LPC_FAMILY}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    __VTOR_PRESENT=0
+    CORE_M0
+    CORE_M0PLUS
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -nostdlib
+      -Wno-error=incompatible-pointer-types
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC11UXX)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc11/family.mk b/hw/bsp/lpc11/family.mk
new file mode 100644
index 000000000..a3ec33768
--- /dev/null
+++ b/hw/bsp/lpc11/family.mk
@@ -0,0 +1,44 @@
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc$(MCU)/lpc_chip_$(MCU)
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
+CFLAGS += \
+  -flto \
+  -nostdlib \
+  -D__USE_LPCOPEN \
+  -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+# mcu driver cause following warnings
+CFLAGS += \
+  -Wno-error=incompatible-pointer-types \
+
+LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
+
+SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
+	$(MCU_DIR)/../gcc/cr_startup_lpc$(MCU_DRV).c \
+	$(MCU_DIR)/src/chip_$(MCU_DRV).c \
+	$(MCU_DIR)/src/clock_$(MCU_DRV).c \
+	$(MCU_DIR)/src/iap.c \
+	$(MCU_DIR)/src/iocon_$(MCU_DRV).c \
+	$(MCU_DIR)/src/sysinit_$(MCU_DRV).c
+
+ifeq ($(MCU),11u6x)
+SRC_C += \
+	$(MCU_DIR)/src/gpio_$(MCU_DRV).c \
+	$(MCU_DIR)/src/syscon_$(MCU_DRV).c \
+
+else
+
+SRC_C += \
+	$(MCU_DIR)/src/gpio_$(MCU_DRV)_1.c \
+	$(MCU_DIR)/src/sysctl_$(MCU_DRV).c
+endif
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR)/inc \
+
+# For flash-jlink target
+JLINK_DEVICE = LPC11U68
diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc13/FreeRTOSConfig/FreeRTOSConfig.h
similarity index 84%
rename from examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
rename to hw/bsp/lpc13/FreeRTOSConfig/FreeRTOSConfig.h
index 6a3630dbc..a56028d5d 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc13/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,26 +42,29 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// Include MCU header
-#include "bsp/board_mcu.h"
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #ifdef __GNUC__
+    #pragma GCC diagnostic push
+    #pragma GCC diagnostic ignored "-Wunused-parameter"
+  #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
-  #error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
-#endif
+  #include "chip.h"
 
-// TODO fix later
-#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
-  extern u32 SystemCoreClock;
-#else
-  // FIXME cause redundant-decls warnings
-  extern uint32_t SystemCoreClock;
+  #ifdef __GNUC__
+    #pragma GCC diagnostic pop
+  #endif
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU								        0
-#define configENABLE_FPU								        1
-#define configENABLE_TRUSTZONE					        0
-#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
@@ -69,7 +72,7 @@
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
 #define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( 0*1024 ) // dynamic is not used
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
 #define configIDLE_SHOULD_YIELD                 1
@@ -94,6 +97,7 @@
 
 /* Run time and task stats gathering related definitions. */
 #define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
 #define configUSE_TRACE_FACILITY               1 // legacy trace
 #define configUSE_STATS_FORMATTING_FUNCTIONS   0
 
@@ -116,7 +120,7 @@
 #define INCLUDE_vTaskDelayUntil                1
 #define INCLUDE_vTaskDelay                     1
 #define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
 #define INCLUDE_uxTaskGetStackHighWaterMark    0
 #define INCLUDE_xTaskGetIdleTaskHandle         0
 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
@@ -142,16 +146,6 @@
   #define configASSERT( x )
 #endif
 
-#ifdef __RX__
-/* Renesas RX series */
-#define vSoftwareInterruptISR					INT_Excep_ICU_SWINT
-#define vTickISR								INT_Excep_CMT0_CMI0
-#define configPERIPHERAL_CLOCK_HZ				(configCPU_CLOCK_HZ/2)
-#define configKERNEL_INTERRUPT_PRIORITY			1
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
-
-#else
-
 /* FreeRTOS hooks to NVIC vectors */
 #define xPortPendSVHandler    PendSV_Handler
 #define xPortSysTickHandler   SysTick_Handler
@@ -160,15 +154,9 @@
 //--------------------------------------------------------------------+
 // Interrupt nesting behavior configuration.
 //--------------------------------------------------------------------+
-#if defined(__NVIC_PRIO_BITS)
-  // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
-	#define configPRIO_BITS       __NVIC_PRIO_BITS
-#elif defined(__ECLIC_INTCTLBITS)
-  // RISC-V Bumblebee core from nuclei
-  #define configPRIO_BITS       __ECLIC_INTCTLBITS
-#else
-  #error "FreeRTOS configPRIO_BITS to be defined"
-#endif
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
 
 /* The lowest interrupt priority that can be used in a call to a "set priority" function. */
 #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
@@ -187,6 +175,4 @@ to all Cortex-M ports, and do not rely on any particular library functions. */
 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
 
-#endif
-
 #endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/board.cmake b/hw/bsp/lpc13/boards/lpcxpresso1347/board.cmake
new file mode 100644
index 000000000..afe2dc132
--- /dev/null
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/board.cmake
@@ -0,0 +1,11 @@
+set(JLINK_DEVICE LPC1347)
+set(PYOCD_TARGET LPC1347)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1347.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/board.h b/hw/bsp/lpc13/boards/lpcxpresso1347/board.h
new file mode 100644
index 000000000..acf29fdc6
--- /dev/null
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/board.h
@@ -0,0 +1,51 @@
+/* metadata:
+   name: LPCXpresso1347
+   url: https://www.nxp.com/products/no-longer-manufactured/lpcxpresso-board-for-lpc1347:OM13045
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+#define LED_PORT      0
+#define LED_PIN       7
+
+// Joytick Down if connected to LPCXpresso Base board
+#define BUTTON_PORT   1
+#define BUTTON_PIN    20
+
+//static const struct {
+//  uint8_t port;
+//  uint8_t pin;
+//} buttons[] =
+//{
+//    {1, 22 }, // Joystick up
+//    {1, 20 }, // Joystick down
+//    {1, 23 }, // Joystick left
+//    {1, 21 }, // Joystick right
+//    {1, 19 }, // Joystick press
+//    {0, 1  }, // SW3
+//};
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t ExtRateIn = 0;
+
+/* Pin muxing table, only items that need changing from their default pin
+   state are in this table. */
+static const PINMUX_GRP_T pinmuxing[] = {
+    {0, 1,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},  /* PIO0_1 used for CLKOUT */
+    {0, 2,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_PULLUP)},  /* PIO0_2 used for SSEL */
+    {0, 3,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},  /* PIO0_3 used for USB_VBUS */
+    {0, 6,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},  /* PIO0_6 used for USB_CONNECT */
+    {0, 8,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},  /* PIO0_8 used for MISO0 */
+    {0, 9,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},  /* PIO0_9 used for MOSI0 */
+    {0, 11, (IOCON_FUNC2 | IOCON_ADMODE_EN | IOCON_FILT_DIS)},  /* PIO0_11 used for AD0 */
+    {0, 18, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},  /* PIO0_18 used for RXD */
+    {0, 19, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},  /* PIO0_19 used for TXD */
+    {1, 29, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},  /* PIO1_29 used for SCK0 */
+};
+
+#endif
diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
new file mode 100644
index 000000000..31eb2f28f
--- /dev/null
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
@@ -0,0 +1,13 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+
+CFLAGS += \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc1347.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1347
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/lpcxpresso1347/lpc1347.ld b/hw/bsp/lpc13/boards/lpcxpresso1347/lpc1347.ld
similarity index 81%
rename from hw/bsp/lpcxpresso1347/lpc1347.ld
rename to hw/bsp/lpc13/boards/lpcxpresso1347/lpc1347.ld
index 42a4bb25c..a2111cd1c 100644
--- a/hw/bsp/lpcxpresso1347/lpc1347.ld
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/lpc1347.ld
@@ -11,29 +11,29 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */  
-  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */  
-  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */  
-  RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */  
+  MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */
+  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
+  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
+  RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash64 = 0x0  ; /* MFlash64 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */  
-  __top_Flash = 0x0 + 0x10000 ; /* 64K bytes */  
-  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */  
-  __base_RAM2 = 0x20004000 ; /* RAM2 */  
-  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __base_RamPeriph2 = 0x20000000  ; /* RamPeriph2 */  
-  __base_RAM3 = 0x20000000 ; /* RAM3 */  
-  __top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */  
-  __top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */  
+  __base_MFlash64 = 0x0  ; /* MFlash64 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */
+  __top_Flash = 0x0 + 0x10000 ; /* 64K bytes */
+  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
+  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
+  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */
+  __base_RAM2 = 0x20004000 ; /* RAM2 */
+  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
+  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
+  __base_RamPeriph2 = 0x20000000  ; /* RamPeriph2 */
+  __base_RAM3 = 0x20000000 ; /* RAM3 */
+  __top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */
+  __top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */
 
 ENTRY(ResetISR)
 
@@ -82,9 +82,9 @@ SECTIONS
     } > MFlash64
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash64
@@ -98,7 +98,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamUsb2 */
 
     .data_RAM2 : ALIGN(4)
@@ -153,7 +153,7 @@ SECTIONS
        *(.bss.$RamUsb2*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamUsb2 
+    } > RamUsb2
 
     /* BSS section for RamPeriph2 */
     .bss_RAM3 : ALIGN(4)
@@ -163,7 +163,7 @@ SECTIONS
        *(.bss.$RamPeriph2*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamPeriph2 
+    } > RamPeriph2
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -182,7 +182,7 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamUsb2*)
        . = ALIGN(4) ;
-    } > RamUsb2 
+    } > RamUsb2
 
     /* NOINIT section for RamPeriph2 */
     .noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -190,13 +190,13 @@ SECTIONS
        *(.noinit.$RAM3*)
        *(.noinit.$RamPeriph2*)
        . = ALIGN(4) ;
-    } > RamPeriph2 
+    } > RamPeriph2
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc8
@@ -204,11 +204,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -222,4 +222,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso1347/lpcxpresso1347.c b/hw/bsp/lpc13/family.c
similarity index 55%
rename from hw/bsp/lpcxpresso1347/lpcxpresso1347.c
rename to hw/bsp/lpc13/family.c
index a9a67ae3a..1faa54485 100644
--- a/hw/bsp/lpcxpresso1347/lpcxpresso1347.c
+++ b/hw/bsp/lpc13/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,71 +24,30 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: NXP
+*/
+
 #include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT      0
-#define LED_PIN       7
-
-// Joytick Down if connected to LPCXpresso Base board
-#define BUTTON_PORT   1
-#define BUTTON_PIN    20
-
-//static const struct {
-//  uint8_t port;
-//  uint8_t pin;
-//} buttons[] =
-//{
-//    {1, 22 }, // Joystick up
-//    {1, 20 }, // Joystick down
-//    {1, 23 }, // Joystick left
-//    {1, 21 }, // Joystick right
-//    {1, 19 }, // Joystick press
-//    {0, 1  }, // SW3
-//};
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-/* Pin muxing table, only items that need changing from their default pin
-   state are in this table. */
-static const PINMUX_GRP_T pinmuxing[] = 
-{
-  {0,  1,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_1 used for CLKOUT */
-  {0,  2,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_PULLUP)},	/* PIO0_2 used for SSEL */
-  {0,  3,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_3 used for USB_VBUS */
-  {0,  6,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_6 used for USB_CONNECT */
-  {0,  8,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_8 used for MISO0 */
-  {0,  9,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_9 used for MOSI0 */
-  {0,  11, (IOCON_FUNC2 | IOCON_ADMODE_EN      | IOCON_FILT_DIS)},	/* PIO0_11 used for AD0 */
-  {0,  18, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_18 used for RXD */
-  {0,  19, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_19 used for TXD */
-  {1,  29, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO1_29 used for SCK0 */
-};
-
 // Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
   /* Enable IOCON clock */
   Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
   Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
   Chip_SetupXtalClocking();
 }
 
-void board_init(void)
-{
+void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -117,36 +76,34 @@ void board_init(void)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   // active low
   return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
diff --git a/hw/bsp/lpc13/family.cmake b/hw/bsp/lpc13/family.cmake
new file mode 100644
index 000000000..e3c0b18c7
--- /dev/null
+++ b/hw/bsp/lpc13/family.cmake
@@ -0,0 +1,102 @@
+include_guard()
+
+set(LPC_FAMILY 13xx)
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc${LPC_FAMILY}/lpc_chip_${LPC_FAMILY})
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC13XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc${LPC_FAMILY}.c
+    ${SDK_DIR}/src/chip_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/clock_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/gpio_${LPC_FAMILY}_1.c
+    ${SDK_DIR}/src/iocon_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/sysctl_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/sysinit_${LPC_FAMILY}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    __VTOR_PRESENT=0
+    CORE_M3
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib)
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC13XX)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpc13/family.mk
similarity index 61%
rename from hw/bsp/lpcxpresso1347/board.mk
rename to hw/bsp/lpc13/family.mk
index bf9c97c82..4f8b48c4b 100644
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpc13/family.mk
@@ -1,26 +1,26 @@
 DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
+
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
   -nostdlib \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
 
 # startup.c and lpc_types.h cause following errors
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=redundant-decls
 
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1347.ld
+# caused by freeRTOS port !!
+CFLAGS += -Wno-error=maybe-uninitialized
 
 SRC_C += \
 	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
@@ -33,13 +33,5 @@ SRC_C += \
 	$(MCU_DIR)/src/sysinit_13xx.c
 
 INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1347
-
-# flash using jlink
-flash: flash-jlink
+  $(TOP)/$(BOARD_PATH) \
+  $(TOP)/$(MCU_DIR)/inc
diff --git a/hw/bsp/lpc15/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc15/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..33bc22b37
--- /dev/null
+++ b/hw/bsp/lpc15/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,179 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #ifdef __GNUC__
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+  #pragma GCC diagnostic ignored "-Wstrict-prototypes"
+  #endif
+
+  #include "chip.h"
+
+  #ifdef __GNUC__
+  #pragma GCC diagnostic pop
+  #endif
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.cmake b/hw/bsp/lpc15/boards/lpcxpresso1549/board.cmake
new file mode 100644
index 000000000..1e893b554
--- /dev/null
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.cmake
@@ -0,0 +1,11 @@
+set(JLINK_DEVICE lpc1549)
+set(PYOCD_TARGET lpc1549)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1549.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.h b/hw/bsp/lpc15/boards/lpcxpresso1549/board.h
index 5ed5b75b2..1be2045a9 100644
--- a/hw/bsp/lpc15/boards/lpcxpresso1549/board.h
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: LPCXpresso1549
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13056
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
index 6dd12ade1..d8079717e 100644
--- a/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
@@ -13,29 +13,29 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */  
-  Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */  
-  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */  
-  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */  
+  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
+  Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */
+  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */
+  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash256 = 0x0  ; /* MFlash256 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */  
-  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */  
-  __base_Ram0_16 = 0x2000000  ; /* Ram0_16 */  
-  __base_RAM = 0x2000000 ; /* RAM */  
-  __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */  
-  __base_Ram1_16 = 0x2004000  ; /* Ram1_16 */  
-  __base_RAM2 = 0x2004000 ; /* RAM2 */  
-  __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */  
-  __base_Ram2_4 = 0x2008000  ; /* Ram2_4 */  
-  __base_RAM3 = 0x2008000 ; /* RAM3 */  
-  __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */  
-  __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */  
+  __base_MFlash256 = 0x0  ; /* MFlash256 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
+  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
+  __base_Ram0_16 = 0x2000000  ; /* Ram0_16 */
+  __base_RAM = 0x2000000 ; /* RAM */
+  __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */
+  __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */
+  __base_Ram1_16 = 0x2004000  ; /* Ram1_16 */
+  __base_RAM2 = 0x2004000 ; /* RAM2 */
+  __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */
+  __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */
+  __base_Ram2_4 = 0x2008000  ; /* Ram2_4 */
+  __base_RAM3 = 0x2008000 ; /* RAM3 */
+  __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */
+  __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */
 
 ENTRY(ResetISR)
 
@@ -84,9 +84,9 @@ SECTIONS
     } > MFlash256
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash256
@@ -98,9 +98,9 @@ SECTIONS
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
     } > MFlash256
     __exidx_end = .;
- 
+
     _etext = .;
-        
+
     /* DATA section for Ram1_16 */
 
     .data_RAM2 : ALIGN(4)
@@ -225,11 +225,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_16 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -243,4 +243,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c
index 7f5984a3e..e23fdec43 100644
--- a/hw/bsp/lpc15/family.c
+++ b/hw/bsp/lpc15/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,8 +24,23 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: NXP
+*/
+
+#ifdef __GNUC__
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wstrict-prototypes"
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 #include "chip.h"
-#include "bsp/board.h"
+
+#ifdef __GNUC__
+  #pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/lpc15/family.cmake b/hw/bsp/lpc15/family.cmake
new file mode 100644
index 000000000..761c5a619
--- /dev/null
+++ b/hw/bsp/lpc15/family.cmake
@@ -0,0 +1,104 @@
+include_guard()
+
+set(LPC_FAMILY 15xx)
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc${LPC_FAMILY}/lpc_chip_${LPC_FAMILY})
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC15XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc${LPC_FAMILY}.c
+    ${SDK_DIR}/src/chip_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/clock_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/gpio_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/iocon_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/swm_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/sysctl_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/sysinit_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/uart_${LPC_FAMILY}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    #__VTOR_PRESENT=0
+    CORE_M3
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib)
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC15XX)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index c7dd3f8be..b83e008e8 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -1,18 +1,18 @@
 DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
   -nostdlib \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_LPC15XX \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual
@@ -28,12 +28,9 @@ SRC_C += \
 	$(MCU_DIR)/src/iocon_15xx.c \
 	$(MCU_DIR)/src/swm_15xx.c \
 	$(MCU_DIR)/src/sysctl_15xx.c \
+	$(MCU_DIR)/src/sysinit_15xx.c \
 	$(MCU_DIR)/src/uart_15xx.c \
-	$(MCU_DIR)/src/sysinit_15xx.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
diff --git a/hw/bsp/lpc17/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc17/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..9b66fb110
--- /dev/null
+++ b/hw/bsp/lpc17/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "chip.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        0
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/board.cmake b/hw/bsp/lpc17/boards/lpcxpresso1769/board.cmake
new file mode 100644
index 000000000..52575e0c1
--- /dev/null
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC1769)
+
+set(JLINK_DEVICE LPC1769)
+set(PYOCD_TARGET LPC1769)
+set(NXPLINK_DEVICE LPC1769:LPC1769)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1769.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/board.h b/hw/bsp/lpc17/boards/lpcxpresso1769/board.h
new file mode 100644
index 000000000..6f5c12854
--- /dev/null
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/board.h
@@ -0,0 +1,83 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: LPCXpresso1769
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13000
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              0
+#define LED_PIN               22
+#define LED_STATE_ON          1
+
+// JOYSTICK_DOWN if using LPCXpresso Base Board
+#define BUTTON_PORT           0
+#define BUTTON_PIN            15
+#define BUTTON_STATE_ACTIVE   0
+
+#define BOARD_UART_PORT   LPC_UART3
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t RTCOscRateIn = 32768;
+
+// Pin muxing configuration
+static const PINMUX_GRP_T pinmuxing[] = {
+    {0, 0,                    IOCON_MODE_INACT | IOCON_FUNC2},  /* TXD3 */
+    {0, 1,                    IOCON_MODE_INACT | IOCON_FUNC2},  /* RXD3 */
+    {LED_PORT,    LED_PIN,    IOCON_MODE_INACT | IOCON_FUNC0},  /* Led 0 */
+
+    /* Joystick buttons. */
+//  {2, 3,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_UP */
+    {BUTTON_PORT, BUTTON_PIN, IOCON_FUNC0 | IOCON_MODE_PULLUP},  /* JOYSTICK_DOWN */
+//  {2, 4,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_LEFT */
+//  {0, 16, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_RIGHT */
+//  {0, 17, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_PRESS */
+};
+
+static const PINMUX_GRP_T pin_usb_mux[] = {
+    {0, 29, IOCON_MODE_INACT | IOCON_FUNC1}, // D+
+    {0, 30, IOCON_MODE_INACT | IOCON_FUNC1}, // D-
+    {2, 9,  IOCON_MODE_INACT | IOCON_FUNC1}, // Soft Connect
+
+    {1, 19, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PPWR (Host mode)
+
+    // VBUS is not connected on this board, so leave the pin at default setting.
+    /// Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);  // USB VBUS
+};
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/board.mk b/hw/bsp/lpc17/boards/lpcxpresso1769/board.mk
new file mode 100644
index 000000000..e22c4f64b
--- /dev/null
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/board.mk
@@ -0,0 +1,8 @@
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc1769.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1769
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/lpcxpresso1769/lpc1769.ld b/hw/bsp/lpc17/boards/lpcxpresso1769/lpc1769.ld
similarity index 72%
rename from hw/bsp/lpcxpresso1769/lpc1769.ld
rename to hw/bsp/lpc17/boards/lpcxpresso1769/lpc1769.ld
index d1c83d8e2..a6c35c157 100644
--- a/hw/bsp/lpcxpresso1769/lpc1769.ld
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/lpc1769.ld
@@ -11,24 +11,24 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */  
+  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash512 = 0x0  ; /* MFlash512 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */  
-  __base_RAM2 = 0x2007c000 ; /* RAM2 */  
-  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
+  __base_MFlash512 = 0x0  ; /* MFlash512 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */
+  __base_RAM2 = 0x2007c000 ; /* RAM2 */
+  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
 
 ENTRY(ResetISR)
 
@@ -72,9 +72,9 @@ SECTIONS
     } > MFlash512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash512
@@ -88,7 +88,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamAHB32 */
 
     .data_RAM2 : ALIGN(4)
@@ -130,7 +130,7 @@ SECTIONS
        *(.bss.$RamAHB32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -140,7 +140,7 @@ SECTIONS
         *(COMMON)
         . = ALIGN(4) ;
         _ebss = .;
-        PROVIDE(end = .);
+/*        PROVIDE(end = .);*/
     } > RamLoc32
 
     /* NOINIT section for RamAHB32 */
@@ -149,28 +149,46 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamAHB32*)
        . = ALIGN(4) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+
+    /* hathach add heap section for clang */
+    .heap (NOLOAD): {
+        __heap_start = .;
+        __HeapBase = .;
+        __heap_base = .;
+        __end = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        PROVIDE(__end__ = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+        __heap_limit = .;
+        __heap_end = .;
+    } > RamLoc32
+
+/*    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);*/
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+    /* This cause issue with clang linker, so it is disabled */
+    /* MemManage_Handler, BusFault_Handler, UsageFault_Handler may not be defined */
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
+                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)
+                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)
+                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)
                                          ) );
 
     /* Provide basic symbols giving location and size of main text
@@ -181,4 +199,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc17/boards/mbed1768/board.cmake b/hw/bsp/lpc17/boards/mbed1768/board.cmake
new file mode 100644
index 000000000..688f34292
--- /dev/null
+++ b/hw/bsp/lpc17/boards/mbed1768/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC1768)
+
+set(JLINK_DEVICE LPC1768)
+set(PYOCD_TARGET LPC1768)
+set(NXPLINK_DEVICE LPC1768:LPC1768)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1768.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc17/boards/mbed1768/board.h b/hw/bsp/lpc17/boards/mbed1768/board.h
new file mode 100644
index 000000000..2c75cede4
--- /dev/null
+++ b/hw/bsp/lpc17/boards/mbed1768/board.h
@@ -0,0 +1,76 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: mbed 1768
+   url: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-arm-cortex-m3/arm-mbed-lpc1768-board:OM11043
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              1
+#define LED_PIN               18
+#define LED_STATE_ON          1
+
+// JOYSTICK_DOWN if using LPCXpresso Base Board
+#define BUTTON_PORT           0
+#define BUTTON_PIN            15
+#define BUTTON_STATE_ACTIVE   0
+
+#define BOARD_UART_PORT   LPC_UART3
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 10000000;
+const uint32_t RTCOscRateIn = 32768;
+
+// Pin muxing configuration
+static const PINMUX_GRP_T pinmuxing[] = {
+    {LED_PORT,  LED_PIN,  IOCON_MODE_INACT | IOCON_FUNC0},
+    {BUTTON_PORT, BUTTON_PIN, IOCON_FUNC0 | IOCON_MODE_PULLUP},
+};
+
+static const PINMUX_GRP_T pin_usb_mux[] = {
+    {0, 29, IOCON_MODE_INACT | IOCON_FUNC1}, // D+
+    {0, 30, IOCON_MODE_INACT | IOCON_FUNC1}, // D-
+    {2, 9,  IOCON_MODE_INACT | IOCON_FUNC1}, // Soft Connect
+
+    {1, 19, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PPWR (Host mode)
+    {1, 22, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PWRD
+
+    // VBUS is not connected on this board, so leave the pin at default setting.
+    // Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);  // USB VBUS
+};
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc17/boards/mbed1768/board.mk b/hw/bsp/lpc17/boards/mbed1768/board.mk
new file mode 100644
index 000000000..a982a970b
--- /dev/null
+++ b/hw/bsp/lpc17/boards/mbed1768/board.mk
@@ -0,0 +1,9 @@
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc1768.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1768
+PYOCD_TARGET = lpc1768
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/mbed1768/lpc1768.ld b/hw/bsp/lpc17/boards/mbed1768/lpc1768.ld
similarity index 72%
rename from hw/bsp/mbed1768/lpc1768.ld
rename to hw/bsp/lpc17/boards/mbed1768/lpc1768.ld
index d1c83d8e2..a6c35c157 100644
--- a/hw/bsp/mbed1768/lpc1768.ld
+++ b/hw/bsp/lpc17/boards/mbed1768/lpc1768.ld
@@ -11,24 +11,24 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */  
+  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash512 = 0x0  ; /* MFlash512 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */  
-  __base_RAM2 = 0x2007c000 ; /* RAM2 */  
-  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
+  __base_MFlash512 = 0x0  ; /* MFlash512 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */
+  __base_RAM2 = 0x2007c000 ; /* RAM2 */
+  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
 
 ENTRY(ResetISR)
 
@@ -72,9 +72,9 @@ SECTIONS
     } > MFlash512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash512
@@ -88,7 +88,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamAHB32 */
 
     .data_RAM2 : ALIGN(4)
@@ -130,7 +130,7 @@ SECTIONS
        *(.bss.$RamAHB32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -140,7 +140,7 @@ SECTIONS
         *(COMMON)
         . = ALIGN(4) ;
         _ebss = .;
-        PROVIDE(end = .);
+/*        PROVIDE(end = .);*/
     } > RamLoc32
 
     /* NOINIT section for RamAHB32 */
@@ -149,28 +149,46 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamAHB32*)
        . = ALIGN(4) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+
+    /* hathach add heap section for clang */
+    .heap (NOLOAD): {
+        __heap_start = .;
+        __HeapBase = .;
+        __heap_base = .;
+        __end = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        PROVIDE(__end__ = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+        __heap_limit = .;
+        __heap_end = .;
+    } > RamLoc32
+
+/*    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);*/
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+    /* This cause issue with clang linker, so it is disabled */
+    /* MemManage_Handler, BusFault_Handler, UsageFault_Handler may not be defined */
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
+                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)
+                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)
+                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)
                                          ) );
 
     /* Provide basic symbols giving location and size of main text
@@ -181,4 +199,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/mbed1768/mbed1768.c b/hw/bsp/lpc17/family.c
similarity index 60%
rename from hw/bsp/mbed1768/mbed1768.c
rename to hw/bsp/lpc17/family.c
index 08cf3adbd..7d3231f6a 100644
--- a/hw/bsp/mbed1768/mbed1768.c
+++ b/hw/bsp/lpc17/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,60 +24,30 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: NXP
+*/
+
 #include "chip.h"
-#include "../board.h"
-
-#define LED_PORT              1
-#define LED_PIN               18
-#define LED_STATE_ON          1
-
-// JOYSTICK_DOWN if using LPCXpresso Base Board
-#define BUTTON_PORT           0
-#define BUTTON_PIN            15
-#define BUTTON_STATE_ACTIVE   0
-
-#define BOARD_UART_PORT   LPC_UART3
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 10000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing configuration */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {LED_PORT,  LED_PIN,  IOCON_MODE_INACT | IOCON_FUNC0},
-  {BUTTON_PORT, BUTTON_PIN, IOCON_FUNC0 | IOCON_MODE_PULLUP},
-};
-
-static const PINMUX_GRP_T pin_usb_mux[] =
-{
-  {0, 29, IOCON_MODE_INACT | IOCON_FUNC1}, // D+
-  {0, 30, IOCON_MODE_INACT | IOCON_FUNC1}, // D-
-  {2,  9, IOCON_MODE_INACT | IOCON_FUNC1}, // Connect
-
-  {1, 19, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PPWR
-  {1, 22, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PWRD
-
-  /* VBUS is not connected on this board, so leave the pin at default setting. */
-  /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
-};
+#include "bsp/board_api.h"
+#include "board.h"
 
 // Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
 #ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
+  extern void (* const g_pfnVectors[])(void);
+  unsigned int* pSCB_VTOR = (unsigned int*) 0xE000ED08;
+  *pSCB_VTOR = (unsigned int) g_pfnVectors;
 #endif
 
   Chip_IOCON_Init(LPC_IOCON);
   Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
   Chip_SetupXtalClocking();
+
+  Chip_SYSCTL_SetFLASHAccess(FLASHTIM_100MHZ_CPU);
 }
 
-void board_init(void)
-{
+void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -89,11 +59,7 @@ void board_init(void)
 #endif
 
   Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
   Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
   Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
 
 #if 0
@@ -106,34 +72,34 @@ void board_init(void)
       .OpenDrain = 0,
       .Pinmode   = 0
   };
-	PINSEL_ConfigPin(&PinCfg);
+  PINSEL_ConfigPin(&PinCfg);
 
-	PinCfg.Portnum = 0;
-	PinCfg.Pinnum  = 1; // RXD is P0.1
-	PINSEL_ConfigPin(&PinCfg);
+  PinCfg.Portnum = 0;
+  PinCfg.Pinnum  = 1; // RXD is P0.1
+  PINSEL_ConfigPin(&PinCfg);
 
-	UART_CFG_Type UARTConfigStruct;
+  UART_CFG_Type UARTConfigStruct;
   UART_ConfigStructInit(&UARTConfigStruct);
-	UARTConfigStruct.Baud_rate = CFG_BOARD_UART_BAUDRATE;
+  UARTConfigStruct.Baud_rate = CFG_BOARD_UART_BAUDRATE;
 
-	UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
-	UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
+  UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
+  UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
 #endif
 
-	//------------- USB -------------//
+  //------------- USB -------------//
   Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
-	Chip_USB_Init();
+  Chip_USB_Init();
 
   enum {
     USBCLK_DEVCIE = 0x12,     // AHB + Device
-    USBCLK_HOST   = 0x19,     // AHB + Host + OTG
+    USBCLK_HOST = 0x19,     // AHB + Host + OTG
 //    0x1B // Host + Device + OTG + AHB
   };
 
   uint32_t const clk_en = CFG_TUD_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
 
   LPC_USB->OTGClkCtrl = clk_en;
-  while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
+  while ((LPC_USB->OTGClkSt & clk_en) != clk_en) {}
 
 #if CFG_TUH_ENABLED
   // set portfunc to host !!!
@@ -141,57 +107,53 @@ void board_init(void)
 #endif
 }
 
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  #if CFG_TUD_ENABLED
-    tud_int_handler(0);
-  #endif
-
-  #if CFG_TUH_ENABLED
-    tuh_int_handler(0);
-  #endif
-}
-
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
 //  return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
 //  UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
-  (void) buf; (void) len;
+  (void) buf;
+  (void) len;
   return 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+  #if CFG_TUD_ENABLED
+  tud_int_handler(0);
+  #endif
+
+  #if CFG_TUH_ENABLED
+  tuh_int_handler(0, true);
+  #endif
+}
+
 #endif
diff --git a/hw/bsp/lpc17/family.cmake b/hw/bsp/lpc17/family.cmake
new file mode 100644
index 000000000..771a0f405
--- /dev/null
+++ b/hw/bsp/lpc17/family.cmake
@@ -0,0 +1,103 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC175X_6X CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc175x_6x.c
+    ${SDK_DIR}/src/chip_17xx_40xx.c
+    ${SDK_DIR}/src/clock_17xx_40xx.c
+    ${SDK_DIR}/src/gpio_17xx_40xx.c
+    ${SDK_DIR}/src/iocon_17xx_40xx.c
+    ${SDK_DIR}/src/sysctl_17xx_40xx.c
+    ${SDK_DIR}/src/sysinit_17xx_40xx.c
+    ${SDK_DIR}/src/uart_17xx_40xx.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    CORE_M3
+    RTC_EV_SUPPORT=0
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib)
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC175X_6X)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+    ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+    ${TOP}/src/portable/ohci/ohci.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpc17/family.mk
similarity index 63%
rename from hw/bsp/lpcxpresso1769/board.mk
rename to hw/bsp/lpc17/family.mk
index 34b4d6dc0..d719a47b7 100644
--- a/hw/bsp/lpcxpresso1769/board.mk
+++ b/hw/bsp/lpc17/family.mk
@@ -1,10 +1,11 @@
 DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
+
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
   -nostdlib \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
@@ -14,13 +15,15 @@ CFLAGS += \
 # lpc_types.h cause following errors
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
 
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
+# caused by freeRTOS port !!
+CFLAGS += -Wno-error=maybe-uninitialized
 
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1769.ld
+LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 
 SRC_C += \
 	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
+	src/portable/ohci/ohci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
 	$(MCU_DIR)/src/clock_17xx_40xx.c \
@@ -28,16 +31,9 @@ SRC_C += \
 	$(MCU_DIR)/src/iocon_17xx_40xx.c \
 	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
 	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
-	$(MCU_DIR)/src/uart_17xx_40xx.c
+	$(MCU_DIR)/src/uart_17xx_40xx.c \
 
 INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1769
-
-# flash using jlink
-flash: flash-jlink
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR)/inc \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..17ddc1da4
--- /dev/null
+++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "chip.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
new file mode 100644
index 000000000..3abe6f3bb
--- /dev/null
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC18S37)
+
+set(JLINK_DEVICE LPC18S37)
+set(PYOCD_TARGET LPC18S37)
+set(NXPLINK_DEVICE LPC18S37:LPCXPRESSO18S37)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
index b3a7bc44f..2cf4dbdf8 100644
--- a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: LPCXpresso18s37
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso18s37-development-board:OM13076
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -62,6 +67,7 @@ static inline void board_lpc18_pinmux(void)
     // USB0
     //{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 },		                // P6_3 USB0_PWR_EN, USB0 VBus function
 
+    // USB1
     //{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
     //{ 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
     {0x2, 5, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4 },
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
index 51fd1539d..0dd971433 100644
--- a/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
@@ -12,43 +12,43 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
+  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
 }
 
 /* Define a symbol for the top of each memory region */
-__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */  
-__base_Flash = 0x1a000000 ; /* Flash */  
-__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */  
-__base_Flash2 = 0x1b000000 ; /* Flash2 */  
-__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-__base_RAM = 0x10000000 ; /* RAM */  
-__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */  
-__base_RAM2 = 0x10080000 ; /* RAM2 */  
-__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-__base_RAM3 = 0x20000000 ; /* RAM3 */  
-__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-__base_RAM4 = 0x20008000 ; /* RAM4 */  
-__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-__base_RAM5 = 0x2000c000 ; /* RAM5 */  
-__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
+__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
+__base_Flash = 0x1a000000 ; /* Flash */
+__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
+__base_Flash2 = 0x1b000000 ; /* Flash2 */
+__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+__base_RAM = 0x10000000 ; /* RAM */
+__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
+__base_RAM2 = 0x10080000 ; /* RAM2 */
+__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+__base_RAM3 = 0x20000000 ; /* RAM3 */
+__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+__base_RAM4 = 0x20008000 ; /* RAM4 */
+__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+__base_RAM5 = 0x2000c000 ; /* RAM5 */
+__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
 __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
 
 ENTRY(ResetISR)
@@ -137,9 +137,9 @@ SECTIONS
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
         __exidx_end = .;
     } > MFlashA512
- 
+
     _etext = .;
-        
+
     /* DATA section for RamLoc40 */
 
     .data_RAM2 : ALIGN(4)
@@ -296,7 +296,7 @@ SECTIONS
        PROVIDE(__end_bss_RamAHB_ETB16 = .) ;
     } > RamAHB_ETB16 AT> RamAHB_ETB16
 
-    /* MAIN BSS SECTION */
+    /* MAIN BSS SECTION: EDIT change to RamLoc40 */
     .bss : ALIGN(4)
     {
         _bss = .;
@@ -308,8 +308,23 @@ SECTIONS
         _ebss = .;
         PROVIDE(__end_bss_RAM = .) ;
         PROVIDE(__end_bss_RamLoc32 = .) ;
+/*        PROVIDE(end = .);*/
+    } > RamLoc40 AT> RamLoc40 /* > RamLoc32 AT> RamLoc32 */
+
+    /* hathach add heap section for clang */
+    .heap (NOLOAD): {
+        __heap_start = .;
+        __HeapBase = .;
+        __heap_base = .;
+        __end = .;
         PROVIDE(end = .);
-    } > RamLoc32 AT> RamLoc32
+        PROVIDE(_end = .);
+        PROVIDE(__end__ = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+        __heap_limit = .;
+        __heap_end = .;
+    } > RamLoc40
 
     /* NOINIT section for RamLoc40 */
     .noinit_RAM2 (NOLOAD) : ALIGN(4)
@@ -377,21 +392,23 @@ SECTIONS
          . = ALIGN(4) ;
         _end_noinit = .;
        PROVIDE(__end_noinit_RAM = .) ;
-       PROVIDE(__end_noinit_RamLoc32 = .) ;        
+       PROVIDE(__end_noinit_RamLoc32 = .) ;
     } > RamLoc32 AT> RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+/*    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);*/
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
+    /* This cause issue with clang linker, so it is disabled */
+    /* MemManage_Handler, BusFault_Handler, UsageFault_Handler may not be defined */
+/*    PROVIDE(__valid_user_code_checksum = 0 -*/
+/*                                         (_vStackTop*/
+/*                                         + (ResetISR + 1)*/
+/*                                         + (NMI_Handler + 1)*/
+/*                                         + (HardFault_Handler + 1)*/
+/*                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)*/
+/*                                         ) );*/
 
     /* Provide basic symbols giving location and size of main text
      * block, including initial values of RW data sections. Note that
@@ -401,4 +418,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.cmake b/hw/bsp/lpc18/boards/mcb1800/board.cmake
new file mode 100644
index 000000000..f6fae89d7
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC1857)
+
+set(JLINK_DEVICE LPC1857)
+set(PYOCD_TARGET LPC1857)
+set(NXPLINK_DEVICE LPC1857:MCB1857)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.h b/hw/bsp/lpc18/boards/mcb1800/board.h
index 6111da975..dba7a62a3 100644
--- a/hw/bsp/lpc18/boards/mcb1800/board.h
+++ b/hw/bsp/lpc18/boards/mcb1800/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Keil MCB1800
+   url: https://www.keil.com/arm/mcb1800/
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -41,10 +46,17 @@
 
 #define UART_DEV      LPC_USART3
 
-static inline void board_lpc18_pinmux(void)
-{
-  const PINMUX_GRP_T pinmuxing[] =
-  {
+static inline void board_lpc18_pinmux(void) {
+  const PINMUX_GRP_T pinmuxing[] = {
+    // ETM Trace
+    #ifdef TRACE_ETM
+    { 0xF, 4, SCU_MODE_FUNC2 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 5, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 6, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 7, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 8, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    #endif
+
     // LEDs
     { 0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4) },
     { 0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
@@ -64,7 +76,6 @@ static inline void board_lpc18_pinmux(void)
 
     // USB0
     { 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 },		                // P6_3 USB0_PWR_EN, USB0 VBus function
-
     { 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
     { 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
   };
@@ -72,8 +83,7 @@ static inline void board_lpc18_pinmux(void)
   Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
 
   /* Pin clock mux values, re-used structure, value in first index is meaningless */
-  const PINMUX_GRP_T pinclockmuxing[] =
-  {
+  const PINMUX_GRP_T pinclockmuxing[] = {
     { 0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
     { 0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
     { 0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
@@ -81,8 +91,7 @@ static inline void board_lpc18_pinmux(void)
   };
 
   /* Clock pins only, group field not used */
-  for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
-  {
+  for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) {
     Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
   }
 }
diff --git a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
index 9a308e342..143aa11ec 100644
--- a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
+++ b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
@@ -11,44 +11,44 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
+  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
 }
 
 /* Define a symbol for the top of each memory region */
-__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */  
-__base_Flash = 0x1a000000 ; /* Flash */  
-__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */  
-__base_Flash2 = 0x1b000000 ; /* Flash2 */  
-__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-__base_RAM = 0x10000000 ; /* RAM */  
-__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */  
-__base_RAM2 = 0x10080000 ; /* RAM2 */  
-__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-__base_RAM3 = 0x20000000 ; /* RAM3 */  
-__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-__base_RAM4 = 0x20008000 ; /* RAM4 */  
-__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-__base_RAM5 = 0x2000c000 ; /* RAM5 */  
-__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
+__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
+__base_Flash = 0x1a000000 ; /* Flash */
+__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
+__base_Flash2 = 0x1b000000 ; /* Flash2 */
+__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+__base_RAM = 0x10000000 ; /* RAM */
+__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
+__base_RAM2 = 0x10080000 ; /* RAM2 */
+__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+__base_RAM3 = 0x20000000 ; /* RAM3 */
+__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+__base_RAM4 = 0x20008000 ; /* RAM4 */
+__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+__base_RAM5 = 0x2000c000 ; /* RAM5 */
+__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
 
 ENTRY(ResetISR)
 
@@ -118,9 +118,9 @@ SECTIONS
     } > MFlashA512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlashA512
@@ -134,7 +134,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamLoc40 */
 
     .data_RAM2 : ALIGN(4)
@@ -215,7 +215,7 @@ SECTIONS
        *(.bss.$RamLoc40*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamLoc40 
+    } > RamLoc40
 
     /* BSS section for RamAHB32 */
     .bss_RAM3 : ALIGN(4)
@@ -225,7 +225,7 @@ SECTIONS
        *(.bss.$RamAHB32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* BSS section for RamAHB16 */
     .bss_RAM4 : ALIGN(4)
@@ -235,7 +235,7 @@ SECTIONS
        *(.bss.$RamAHB16*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM4 = .) ;
-    } > RamAHB16 
+    } > RamAHB16
 
     /* BSS section for RamAHB_ETB16 */
     .bss_RAM5 : ALIGN(4)
@@ -245,9 +245,9 @@ SECTIONS
        *(.bss.$RamAHB_ETB16*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM5 = .) ;
-    } > RamAHB_ETB16 
+    } > RamAHB_ETB16
 
-    /* MAIN BSS SECTION */
+    /* MAIN BSS SECTION: EDIT change to RamLoc40 */
     .bss : ALIGN(4)
     {
         _bss = .;
@@ -255,8 +255,8 @@ SECTIONS
         *(COMMON)
         . = ALIGN(4) ;
         _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc32
+        /* PROVIDE(end = .); */
+    } > RamLoc40 /* RamLoc32 */
 
     /* NOINIT section for RamLoc40 */
     .noinit_RAM2 (NOLOAD) : ALIGN(4)
@@ -264,7 +264,22 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamLoc40*)
        . = ALIGN(4) ;
-    } > RamLoc40 
+    } > RamLoc40
+
+    /* hathach add heap section for clang */
+    .heap (NOLOAD): {
+        __heap_start = .;
+        __HeapBase = .;
+        __heap_base = .;
+        __end = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        PROVIDE(__end__ = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+        __heap_limit = .;
+        __heap_end = .;
+    } > RamLoc40
 
     /* NOINIT section for RamAHB32 */
     .noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -272,7 +287,7 @@ SECTIONS
        *(.noinit.$RAM3*)
        *(.noinit.$RamAHB32*)
        . = ALIGN(4) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* NOINIT section for RamAHB16 */
     .noinit_RAM4 (NOLOAD) : ALIGN(4)
@@ -280,7 +295,7 @@ SECTIONS
        *(.noinit.$RAM4*)
        *(.noinit.$RamAHB16*)
        . = ALIGN(4) ;
-    } > RamAHB16 
+    } > RamAHB16
 
     /* NOINIT section for RamAHB_ETB16 */
     .noinit_RAM5 (NOLOAD) : ALIGN(4)
@@ -288,29 +303,31 @@ SECTIONS
        *(.noinit.$RAM5*)
        *(.noinit.$RamAHB_ETB16*)
        . = ALIGN(4) ;
-    } > RamAHB_ETB16 
+    } > RamAHB_ETB16
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+/*    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);*/
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
+    /* This cause issue with clang linker, so it is disabled */
+    /* MemManage_Handler, BusFault_Handler, UsageFault_Handler may not be defined */
+/*    PROVIDE(__valid_user_code_checksum = 0 -*/
+/*                                         (_vStackTop*/
+/*                                         + (ResetISR + 1)*/
+/*                                         + (NMI_Handler + 1)*/
+/*                                         + (HardFault_Handler + 1)*/
+/*                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)*/
+/*                                         ) );*/
 
     /* Provide basic symbols giving location and size of main text
      * block, including initial values of RW data sections. Note that
@@ -320,4 +337,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
new file mode 100644
index 000000000..f94960f09
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
@@ -0,0 +1,37 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Project.AddSvdFile ("Cortex-M3.svd");
+  Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC18xx.svd");
+
+  Project.SetDevice ("LPC1857");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  //File.Open ("../../../../../../examples/cmake-build-mcb1800/device/cdc_msc/cdc_msc.elf");
+  File.Open ("../../../../../../examples/cmake-build-mcb1800/host/cdc_msc_hid/cdc_msc_hid.elf");
+}
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+  //
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+  //
+  // Project.SetJLinkScript("./NXP_LPC1857JET256_TraceExample.pex");
+}
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index 72c20e034..0db5c83b6 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,71 +24,59 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: NXP
+*/
+
 #include "chip.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
-#ifdef BOARD_TUD_RHPORT
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
-#endif
+extern void USB0_IRQHandler(void);
+extern void USB1_IRQHandler(void);
+extern void SysTick_Handler(void);
+void SystemInit(void);
 
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(0)
-    tud_int_handler(0);
-  #endif
-
-  #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
-  #endif
+void USB0_IRQHandler(void) {
+  tusb_int_handler(0, true);
 }
 
-void USB1_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(1)
-    tud_int_handler(1);
-  #endif
-
-  #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
-  #endif
+void USB1_IRQHandler(void) {
+  tusb_int_handler(1, true);
 }
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
-
 /* System configuration variables used by chip driver */
 const uint32_t OscRateIn = 12000000;
 const uint32_t ExtRateIn = 0;
 
 // Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
 #ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
+  extern void (*const g_pfnVectors[])(void);
   unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
+  *pSCB_VTOR = (unsigned int) g_pfnVectors;
 #endif
 
   board_lpc18_pinmux();
-  Chip_SetupXtalClocking();
+
+#ifdef TRACE_ETM
+  // Trace clock is limited to 60MHz, limit CPU clock to 120MHz
+  Chip_SetupCoreClock(CLKIN_CRYSTAL, 120000000UL, true);
+#else
+  // CPU clock max to 180 Mhz
+  Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
+#endif
+
 }
 
-void board_init(void)
-{
+void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -115,40 +103,30 @@ void board_init(void)
   Chip_UART_TXEnable(UART_DEV);
 
   //------------- USB -------------//
-#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0)
   Chip_USB0_Init();
-#endif
-
-#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1)
   Chip_USB1_Init();
-#endif
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   // active low
   return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t *buf, int len) {
   return Chip_UART_Read(UART_DEV, buf, len);
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const* buf8 = (uint8_t const*) buf;
-  for(int i=0; i<len; i++)
-  {
+int board_uart_write(void const *buf, int len) {
+  uint8_t const *buf8 = (uint8_t const *) buf;
+  for (int i = 0; i < len; i++) {
     while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
     Chip_UART_SendByte(UART_DEV, buf8[i]);
   }
@@ -158,13 +136,13 @@ int board_uart_write(void const * buf, int len)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
new file mode 100644
index 000000000..6af1149bf
--- /dev/null
+++ b/hw/bsp/lpc18/family.cmake
@@ -0,0 +1,100 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc18xx.c
+    ${SDK_DIR}/src/chip_18xx_43xx.c
+    ${SDK_DIR}/src/clock_18xx_43xx.c
+    ${SDK_DIR}/src/gpio_18xx_43xx.c
+    ${SDK_DIR}/src/sysinit_18xx_43xx.c
+    ${SDK_DIR}/src/uart_18xx_43xx.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    CORE_M3
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${SDK_DIR}/inc/config_18xx
+    ${CMSIS_5}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib)
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index 7aa36abc4..f120f63b2 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -1,21 +1,20 @@
 DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
   -nostdlib \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
   -DCFG_TUSB_MCU=OPT_MCU_LPC18XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-qual
 
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
+LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 
 SRC_C += \
 	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
@@ -31,7 +30,5 @@ SRC_C += \
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(MCU_DIR)/inc \
-	$(TOP)/$(MCU_DIR)/inc/config_18xx
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+	$(TOP)/$(MCU_DIR)/inc/config_18xx \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
diff --git a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..8cd3ee3d8
--- /dev/null
+++ b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "chip.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       5
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake b/hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake
new file mode 100644
index 000000000..7f281d5f6
--- /dev/null
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE LPC4088)
+set(PYOCD_TARGET LPC4088)
+set(NXPLINK_DEVICE LPC4088:LPC4088)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4088.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.h b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h
new file mode 100644
index 000000000..ede0a306d
--- /dev/null
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h
@@ -0,0 +1,79 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Embedded Artists LPC4088 QuickStart Board
+   url: https://www.embeddedartists.com/products/lpc4088-quickstart-board/
+*/
+
+#ifndef EA4088QS__BOARD_H
+#define EA4088QS__BOARD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT      2
+#define LED_PIN       19
+
+#define BUTTON_PORT   2
+#define BUTTON_PIN    10
+#define BUTTON_ACTIV_STATE 0
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t RTCOscRateIn = 32768;
+
+/* Pin muxing configuration */
+static const PINMUX_GRP_T pinmuxing[] = {
+    // LED
+    { 2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT) },
+
+    // Button
+    { 2, 10, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_MODE_PULLUP) },
+
+    // USB1 as Host
+    { 0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // D+1
+    { 0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // D-1
+    { 1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // UP LED1
+    { 1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT) }, // PPWR1
+//  {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1
+//  {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1
+
+    // USB2 as Device
+    { 0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // D+2
+    { 0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // UP LED
+    { 0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT) }, // CONNECT2
+
+    /* VBUS is not connected on this board, so leave the pin at default setting. */
+    /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.mk b/hw/bsp/lpc40/boards/ea4088_quickstart/board.mk
new file mode 100644
index 000000000..d0bb4fe8c
--- /dev/null
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.mk
@@ -0,0 +1,8 @@
+
+LD_FILE = $(BOARD_PATH)/lpc4088.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC4088
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/ea4088qs/lpc4088.ld b/hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld
similarity index 75%
rename from hw/bsp/ea4088qs/lpc4088.ld
rename to hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld
index 4b1cddd6e..55b60e1e7 100644
--- a/hw/bsp/ea4088qs/lpc4088.ld
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld
@@ -11,24 +11,24 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  RamLoc64 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */  
-  RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */  
+  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  RamLoc64 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */
+  RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash512 = 0x0  ; /* MFlash512 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc64 = 0x10000000  ; /* RamLoc64 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc64 = 0x10000000 + 0x10000 ; /* 64K bytes */  
-  __top_RAM = 0x10000000 + 0x10000 ; /* 64K bytes */  
-  __base_RamPeriph32 = 0x20000000  ; /* RamPeriph32 */  
-  __base_RAM2 = 0x20000000 ; /* RAM2 */  
-  __top_RamPeriph32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM2 = 0x20000000 + 0x8000 ; /* 32K bytes */  
+  __base_MFlash512 = 0x0  ; /* MFlash512 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc64 = 0x10000000  ; /* RamLoc64 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc64 = 0x10000000 + 0x10000 ; /* 64K bytes */
+  __top_RAM = 0x10000000 + 0x10000 ; /* 64K bytes */
+  __base_RamPeriph32 = 0x20000000  ; /* RamPeriph32 */
+  __base_RAM2 = 0x20000000 ; /* RAM2 */
+  __top_RamPeriph32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM2 = 0x20000000 + 0x8000 ; /* 32K bytes */
 
 ENTRY(ResetISR)
 
@@ -72,9 +72,9 @@ SECTIONS
     } > MFlash512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash512
@@ -88,7 +88,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamPeriph32 */
 
     .data_RAM2 : ALIGN(4)
@@ -130,7 +130,7 @@ SECTIONS
        *(.bss.$RamPeriph32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamPeriph32 
+    } > RamPeriph32
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -140,7 +140,7 @@ SECTIONS
         *(COMMON)
         . = ALIGN(4) ;
         _ebss = .;
-        PROVIDE(end = .);
+/*        PROVIDE(end = .);*/
     } > RamLoc64
 
     /* NOINIT section for RamPeriph32 */
@@ -149,25 +149,41 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamPeriph32*)
        . = ALIGN(4) ;
-    } > RamPeriph32 
+    } > RamPeriph32
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc64
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+
+    /* hathach add heap section for clang */
+    .heap (NOLOAD): {
+        __heap_start = .;
+        __HeapBase = .;
+        __heap_base = .;
+        __end = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        PROVIDE(__end__ = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+        __heap_limit = .;
+        __heap_end = .;
+    } > RamLoc64
+
+/*    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);*/
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc64 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -181,4 +197,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug b/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug
new file mode 100644
index 000000000..6aaf1076d
--- /dev/null
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug
@@ -0,0 +1,238 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Edit.SysVar (VAR_POWER_SAMPLING_SPEED, FREQ_100_KHZ);
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M4F.svd");
+  Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC408x_7x_v0.7.svd");
+
+  Project.SetDevice ("LPC4088");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  // User settings
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ea4088-quickstart/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging a RAM program on a Cortex-M target device
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  Exec.Reset();
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//
+//    Util.Log("Resetting Program.");
+//
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
diff --git a/hw/bsp/ea4088qs/ea4088qs.c b/hw/bsp/lpc40/family.c
similarity index 60%
rename from hw/bsp/ea4088qs/ea4088qs.c
rename to hw/bsp/lpc40/family.c
index 7150ed393..b8bc99452 100644
--- a/hw/bsp/ea4088qs/ea4088qs.c
+++ b/hw/bsp/lpc40/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,90 +24,65 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: NXP
+*/
+
 #include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   #if CFG_TUD_ENABLED
-    tud_int_handler(0);
+  tud_int_handler(0);
   #endif
 
   #if CFG_TUH_ENABLED
-    tuh_int_handler(0);
+  tuh_int_handler(0, true);
   #endif
 }
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
-#define LED_PORT      2
-#define LED_PIN       19
-
-#define BUTTON_PORT   2
-#define BUTTON_PIN    10
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing configuration */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  // LED
-  {2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)},
-
-  // Button
-  {2, 10, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_MODE_PULLUP)},
-};
-
-static const PINMUX_GRP_T pin_usb_mux[] =
-{
-  // USB1 as Host
-  {0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+1
-  {0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D-1
-  {1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED1
-  {1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // PPWR1
-//  {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1
-//  {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1
-
-  // USB2 as Device
-  {0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+2
-  {0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED
-  {0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT)}, // CONNECT2
-
-  /* VBUS is not connected on this board, so leave the pin at default setting. */
-  /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
-};
 
 // Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
 #ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
+  extern void (*const g_pfnVectors[])(void);
   unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
+  *pSCB_VTOR = (unsigned int) g_pfnVectors;
 
-#if __FPU_USED == 1
-	fpuInit();
-#endif
+  #if __FPU_USED == 1
+  fpuInit();
+  #endif
 #endif // __USE_LPCOPEN
 
   Chip_IOCON_Init(LPC_IOCON);
   Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
 
-	/* CPU clock source starts with IRC */
-	/* Enable PBOOST for CPU clock over 100MHz */
-	Chip_SYSCTL_EnableBoost();
+#ifdef TRACE_ETM
+  const PINMUX_GRP_T trace_pinmux[] = {
+      {2, 2, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+      {2, 3, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+      {2, 4, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+      {2, 5, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+      {2, 6, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+  };
+  Chip_IOCON_SetPinMuxing(LPC_IOCON, trace_pinmux, sizeof(trace_pinmux) / sizeof(PINMUX_GRP_T));
+#endif
+
+  /* CPU clock source starts with IRC */
+  /* Enable PBOOST for CPU clock over 100MHz */
+  Chip_SYSCTL_EnableBoost();
 
   Chip_SetupXtalClocking();
 }
 
-void board_init(void)
-{
+void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -129,15 +104,14 @@ void board_init(void)
   // UART
 
   //------------- USB -------------//
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
 
   // Port1 as Host, Port2: Device
   Chip_USB_Init();
 
   enum {
     USBCLK_DEVCIE = 0x12, // AHB + Device
-    USBCLK_HOST = 0x19 ,  // AHB + OTG + Host
-    USBCLK_ALL  = 0x1B    // Host + Device + OTG + AHB
+    USBCLK_HOST = 0x19,  // AHB + OTG + Host
+    USBCLK_ALL = 0x1B    // Host + Device + OTG + AHB
   };
 
   LPC_USB->OTGClkCtrl = USBCLK_ALL;
@@ -151,40 +125,37 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
 }
 
-uint32_t board_button_read(void)
-{
-  // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
+uint32_t board_button_read(void) {
+  return BUTTON_ACTIV_STATE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t *buf, int len) {
   //return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
   //UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
-  (void) buf; (void) len;
+  (void) buf;
+  (void) len;
   return 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake
new file mode 100644
index 000000000..3a680eae6
--- /dev/null
+++ b/hw/bsp/lpc40/family.cmake
@@ -0,0 +1,104 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC40XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc40xx.c
+    ${SDK_DIR}/src/chip_17xx_40xx.c
+    ${SDK_DIR}/src/clock_17xx_40xx.c
+    ${SDK_DIR}/src/fpu_init.c
+    ${SDK_DIR}/src/gpio_17xx_40xx.c
+    ${SDK_DIR}/src/iocon_17xx_40xx.c
+    ${SDK_DIR}/src/sysctl_17xx_40xx.c
+    ${SDK_DIR}/src/sysinit_17xx_40xx.c
+    ${SDK_DIR}/src/uart_17xx_40xx.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    CORE_M4
+    CFG_TUSB_MEM_SECTION=__attribute__\(\(section\(\".data.$RAM2\"\)\)\)
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib)
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+    ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+    ${TOP}/src/portable/ohci/ohci.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/lpc40/family.mk
similarity index 71%
rename from hw/bsp/ea4088qs/board.mk
rename to hw/bsp/lpc40/family.mk
index b325dfeb4..ef9fe57b2 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/lpc40/family.mk
@@ -1,12 +1,11 @@
 DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib \
   -DCORE_M4 \
   -D__USE_LPCOPEN \
@@ -16,31 +15,24 @@ CFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
 
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
+LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 
 # All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc4088.ld
-
 SRC_C += \
 	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
+	src/portable/ohci/ohci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
 	$(MCU_DIR)/src/clock_17xx_40xx.c \
+	$(MCU_DIR)/src/fpu_init.c \
 	$(MCU_DIR)/src/gpio_17xx_40xx.c \
 	$(MCU_DIR)/src/iocon_17xx_40xx.c \
 	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
 	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
 	$(MCU_DIR)/src/uart_17xx_40xx.c \
-	$(MCU_DIR)/src/fpu_init.c
 
 INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4088
-
-# flash using jlink
-flash: flash-jlink
+	$(TOP)/$(MCU_DIR)/inc \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(BOARD_PATH)
diff --git a/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..17ddc1da4
--- /dev/null
+++ b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "chip.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc43/boards/ea4357/board.cmake b/hw/bsp/lpc43/boards/ea4357/board.cmake
new file mode 100644
index 000000000..8f4588463
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT LPC4357)
+
+set(JLINK_DEVICE LPC4357_M4)
+set(PYOCD_TARGET LPC4357)
+set(NXPLINK_DEVICE LPC4357:LPC4357)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4357.ld)
+
+function(update_board TARGET)
+  # EA4357 use I2C GPIO expander for LED
+  target_sources(${TARGET} PRIVATE
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pca9532.c
+    ${SDK_DIR}/src/i2c_18xx_43xx.c
+    ${SDK_DIR}/src/i2cm_18xx_43xx.c
+    )
+endfunction()
diff --git a/hw/bsp/lpc43/boards/ea4357/board.h b/hw/bsp/lpc43/boards/ea4357/board.h
new file mode 100644
index 000000000..fca617361
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/board.h
@@ -0,0 +1,90 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Embedded Artists LPC4357 Development Kit
+   url: https://www.embeddedartists.com/products/lpc4357-developers-kit/
+*/
+
+#ifndef _BOARD_EA4357_H
+#define _BOARD_EA4357_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "pca9532.h"
+
+// P9_1 joystick down
+#define BUTTON_PORT     4
+#define BUTTON_PIN      13
+#define BUTTON_STATE_ACTIVE   0
+
+#define UART_DEV        LPC_USART0
+#define UART_PORT       0x0f
+#define UART_PIN_TX     10
+#define UART_PIN_RX     11
+
+//static const struct {
+//  uint8_t mux_port;
+//  uint8_t mux_pin;
+//
+//  uint8_t gpio_port;
+//  uint8_t gpio_pin;
+//}buttons[] =
+//{
+//    {0x0a, 3, 4, 10 }, // Joystick up
+//    {0x09, 1, 4, 13 }, // Joystick down
+//    {0x0a, 2, 4, 9  }, // Joystick left
+//    {0x09, 0, 4, 12 }, // Joystick right
+//    {0x0a, 1, 4, 8  }, // Joystick press
+//    {0x02, 7, 0, 7  }, // SW6
+//};
+
+static const PINMUX_GRP_T pinmuxing[] = {
+    // Button ( Joystick down )
+    { 0x9, 1, SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP },
+
+    // UART
+    { UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1 },
+    { UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1 },
+
+    // USB
+};
+
+/* Pin clock mux values, re-used structure, value in first index is meaningless */
+//static const PINMUX_GRP_T pinclockmuxing[] = {
+//    { 0, 0, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0 },
+//    { 0, 1, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0 },
+//    { 0, 2, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0 },
+//    { 0, 3, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0 },
+//};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc43/boards/ea4357/board.mk b/hw/bsp/lpc43/boards/ea4357/board.mk
new file mode 100644
index 000000000..d0eb08d6d
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/board.mk
@@ -0,0 +1,11 @@
+# EA4357 use I2C GPIO expander for LED
+SRC_C += \
+  ${BOARD_PATH}/pca9532.c \
+	${SDK_DIR}/src/i2c_18xx_43xx.c \
+	${SDK_DIR}/src/i2cm_18xx_43xx.c \
+
+LD_FILE = ${BOARD_PATH}/lpc4357.ld
+
+JLINK_DEVICE = LPC4357_M4
+
+flash: flash-jlink
diff --git a/hw/bsp/ea4357/lpc4357.ld b/hw/bsp/lpc43/boards/ea4357/lpc4357.ld
similarity index 69%
rename from hw/bsp/ea4357/lpc4357.ld
rename to hw/bsp/lpc43/boards/ea4357/lpc4357.ld
index 14a0df328..002dcaaed 100644
--- a/hw/bsp/ea4357/lpc4357.ld
+++ b/hw/bsp/lpc43/boards/ea4357/lpc4357.ld
@@ -11,44 +11,44 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
+  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */  
-  __base_Flash = 0x1a000000 ; /* Flash */  
-  __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-  __base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */  
-  __base_Flash2 = 0x1b000000 ; /* Flash2 */  
-  __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-  __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamLoc40 = 0x10080000  ; /* RamLoc40 */  
-  __base_RAM2 = 0x10080000 ; /* RAM2 */  
-  __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-  __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-  __base_RAM3 = 0x20000000 ; /* RAM3 */  
-  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-  __base_RAM4 = 0x20008000 ; /* RAM4 */  
-  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-  __base_RAM5 = 0x2000c000 ; /* RAM5 */  
-  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
+  __base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
+  __base_Flash = 0x1a000000 ; /* Flash */
+  __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
+  __base_Flash2 = 0x1b000000 ; /* Flash2 */
+  __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
+  __base_RAM2 = 0x10080000 ; /* RAM2 */
+  __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+  __base_RAM3 = 0x20000000 ; /* RAM3 */
+  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+  __base_RAM4 = 0x20008000 ; /* RAM4 */
+  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+  __base_RAM5 = 0x2000c000 ; /* RAM5 */
+  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
 
 
 ENTRY(ResetISR)
@@ -119,9 +119,9 @@ SECTIONS
     } > MFlashA512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlashA512
@@ -135,7 +135,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamLoc40 */
 
     .data_RAM2 : ALIGN(4)
@@ -216,7 +216,7 @@ SECTIONS
        *(.bss.$RamLoc40*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamLoc40 
+    } > RamLoc40
 
     /* BSS section for RamAHB32 */
     .bss_RAM3 : ALIGN(4)
@@ -226,7 +226,7 @@ SECTIONS
        *(.bss.$RamAHB32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* BSS section for RamAHB16 */
     .bss_RAM4 : ALIGN(4)
@@ -236,7 +236,7 @@ SECTIONS
        *(.bss.$RamAHB16*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM4 = .) ;
-    } > RamAHB16 
+    } > RamAHB16
 
     /* BSS section for RamAHB_ETB16 */
     .bss_RAM5 : ALIGN(4)
@@ -246,9 +246,9 @@ SECTIONS
        *(.bss.$RamAHB_ETB16*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM5 = .) ;
-    } > RamAHB_ETB16 
+    } > RamAHB_ETB16
 
-    /* MAIN BSS SECTION */
+    /* MAIN BSS SECTION: EDIT change to RamLoc40 */
     .bss : ALIGN(4)
     {
         _bss = .;
@@ -256,8 +256,8 @@ SECTIONS
         *(COMMON)
         . = ALIGN(4) ;
         _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc32
+        /* PROVIDE(end = .); */
+    } > RamLoc40 /* RamLoc32 */
 
     /* NOINIT section for RamLoc40 */
     .noinit_RAM2 (NOLOAD) : ALIGN(4)
@@ -265,7 +265,22 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamLoc40*)
        . = ALIGN(4) ;
-    } > RamLoc40 
+    } > RamLoc40
+
+    /* hathach add heap section for clang */
+    .heap (NOLOAD): {
+        __heap_start = .;
+        __HeapBase = .;
+        __heap_base = .;
+        __end = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        PROVIDE(__end__ = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+        __heap_limit = .;
+        __heap_end = .;
+    } > RamLoc40
 
     /* NOINIT section for RamAHB32 */
     .noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -273,7 +288,7 @@ SECTIONS
        *(.noinit.$RAM3*)
        *(.noinit.$RamAHB32*)
        . = ALIGN(4) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* NOINIT section for RamAHB16 */
     .noinit_RAM4 (NOLOAD) : ALIGN(4)
@@ -281,7 +296,7 @@ SECTIONS
        *(.noinit.$RAM4*)
        *(.noinit.$RamAHB16*)
        . = ALIGN(4) ;
-    } > RamAHB16 
+    } > RamAHB16
 
     /* NOINIT section for RamAHB_ETB16 */
     .noinit_RAM5 (NOLOAD) : ALIGN(4)
@@ -289,29 +304,31 @@ SECTIONS
        *(.noinit.$RAM5*)
        *(.noinit.$RamAHB_ETB16*)
        . = ALIGN(4) ;
-    } > RamAHB_ETB16 
+    } > RamAHB_ETB16
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+/*    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);*/
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
+    /* This cause issue with clang linker, so it is disabled */
+    /* MemManage_Handler, BusFault_Handler, UsageFault_Hander may not be defined */
+/*    PROVIDE(__valid_user_code_checksum = 0 -*/
+/*                                         (_vStackTop*/
+/*                                         + (ResetISR + 1)*/
+/*                                         + (NMI_Handler + 1)*/
+/*                                         + (HardFault_Handler + 1)*/
+/*                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)*/
+/*                                         ) );*/
 
     /* Provide basic symbols giving location and size of main text
      * block, including initial values of RW data sections. Note that
@@ -321,4 +338,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/ea4357/pca9532.c b/hw/bsp/lpc43/boards/ea4357/pca9532.c
similarity index 99%
rename from hw/bsp/ea4357/pca9532.c
rename to hw/bsp/lpc43/boards/ea4357/pca9532.c
index eae3805c2..150167cde 100644
--- a/hw/bsp/ea4357/pca9532.c
+++ b/hw/bsp/lpc43/boards/ea4357/pca9532.c
@@ -57,7 +57,7 @@ static uint16_t ledStateShadow = 0;
  * Local Functions
  *****************************************************************************/
 
-static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len) 
+static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
 {
 	I2CM_XFER_T i2cData;
 
@@ -75,7 +75,7 @@ static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
 	return SUCCESS;
 }
 
-static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len) 
+static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
 {
 	I2CM_XFER_T i2cData;
 
@@ -181,7 +181,7 @@ uint16_t pca9532_getLedState (uint32_t shadow)
          * A blinking LED may be reported as on or off depending on
          * its state when reading the Input register.
          */
-        
+
         buf[0] = PCA9532_INPUT0;
         I2CWrite(PCA9532_I2C_ADDR, buf, 1);
 
diff --git a/hw/bsp/ea4357/pca9532.h b/hw/bsp/lpc43/boards/ea4357/pca9532.h
similarity index 97%
rename from hw/bsp/ea4357/pca9532.h
rename to hw/bsp/lpc43/boards/ea4357/pca9532.h
index 7a7c6e145..f21c1ff09 100644
--- a/hw/bsp/ea4357/pca9532.h
+++ b/hw/bsp/lpc43/boards/ea4357/pca9532.h
@@ -48,7 +48,7 @@
 #define KEY_MASK 0x000F
 
 /*
- * MMC Card Detect and MMC Write Protect are mapped to LED4 
+ * MMC Card Detect and MMC Write Protect are mapped to LED4
  * and LED5 on the PCA9532. Please note that WP is active low.
  */
 
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake
new file mode 100644
index 000000000..0858a97d5
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC43S67_M4)
+
+set(JLINK_DEVICE LPC43S67_M4)
+set(PYOCD_TARGET LPC43S67)
+set(NXPLINK_DEVICE LPC43S67:LPCXPRESSO43S67)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4367.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h
new file mode 100644
index 000000000..4427905e8
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h
@@ -0,0 +1,78 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: LPCXpresso43S67
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso43s67-development-board:OM13084
+*/
+
+#ifndef _BOARD_LPCXPRESSO43S67_H_
+#define _BOARD_LPCXPRESSO43S67_H_
+
+// Note: For USB Host demo, install JP4
+// WARNING: don't install JP4 when running as device
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED Red
+#define LED_PORT      3
+#define LED_PIN       7
+#define LED_STATE_ON  0
+
+// ISP Button (SW2)
+#define BUTTON_PORT   0
+#define BUTTON_PIN    7
+#define BUTTON_STATE_ACTIVE   0
+
+#define UART_DEV      LPC_USART0
+
+static const PINMUX_GRP_T pinmuxing[] = {
+    // LEDs P6_11 as GPIO3[7]
+    { 0x6, 11, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0 },
+
+    // Button P2_7 as GPIO0[7]
+    { 0x2, 7, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0 },
+
+    // UART
+    { 0x06, 4, SCU_MODE_PULLDOWN | SCU_MODE_FUNC2 },
+    { 0x02, 1, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1 },
+
+    // USB0
+    //{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 },		                // P6_3 USB0_PWR_EN, USB0 VBus function
+
+    // USB 1
+    //{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
+    //{ 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
+    {0x2, 5, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4 },
+};
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk
new file mode 100644
index 000000000..eeb02e311
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk
@@ -0,0 +1,6 @@
+LD_FILE = $(BOARD_PATH)/lpc4367.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC43S67_M4
+
+flash: flash-jlink
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld b/hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld
new file mode 100644
index 000000000..f19350e00
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld
@@ -0,0 +1,419 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2023
+ * Generated linker script file for LPC4337
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.7.1 [Build 9221] [2023-03-28] on Aug 14, 2023, 3:36:29 PM
+ */
+
+MEMORY
+{
+  /* Define each memory region */
+  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
+}
+
+  /* Define a symbol for the top of each memory region */
+  __base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
+  __base_Flash = 0x1a000000 ; /* Flash */
+  __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
+  __base_Flash2 = 0x1b000000 ; /* Flash2 */
+  __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
+  __base_RAM2 = 0x10080000 ; /* RAM2 */
+  __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+  __base_RAM3 = 0x20000000 ; /* RAM3 */
+  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+  __base_RAM4 = 0x20008000 ; /* RAM4 */
+  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+  __base_RAM5 = 0x2000c000 ; /* RAM5 */
+  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+     .text_Flash2 : ALIGN(4)
+    {
+       FILL(0xff)
+        *(.text_Flash2) /* for compatibility with previous releases */
+        *(.text_MFlashB512) /* for compatibility with previous releases */
+        *(.text.$Flash2)
+        *(.text.$MFlashB512)
+        *(.text_Flash2.*) /* for compatibility with previous releases */
+        *(.text_MFlashB512.*) /* for compatibility with previous releases */
+        *(.text.$Flash2.*)
+        *(.text.$MFlashB512.*)
+        *(.rodata.$Flash2)
+        *(.rodata.$MFlashB512)
+        *(.rodata.$Flash2.*)
+        *(.rodata.$MFlashB512.*)            } > MFlashB512
+
+    /* MAIN TEXT SECTION */
+    .text : ALIGN(4)
+    {
+        FILL(0xff)
+        __vectors_start__ = ABSOLUTE(.) ;
+        KEEP(*(.isr_vector))
+        /* Global Section Table */
+        . = ALIGN(4) ;
+        __section_table_start = .;
+        __data_section_table = .;
+        LONG(LOADADDR(.data));
+        LONG(    ADDR(.data));
+        LONG(  SIZEOF(.data));
+        LONG(LOADADDR(.data_RAM2));
+        LONG(    ADDR(.data_RAM2));
+        LONG(  SIZEOF(.data_RAM2));
+        LONG(LOADADDR(.data_RAM3));
+        LONG(    ADDR(.data_RAM3));
+        LONG(  SIZEOF(.data_RAM3));
+        LONG(LOADADDR(.data_RAM4));
+        LONG(    ADDR(.data_RAM4));
+        LONG(  SIZEOF(.data_RAM4));
+        LONG(LOADADDR(.data_RAM5));
+        LONG(    ADDR(.data_RAM5));
+        LONG(  SIZEOF(.data_RAM5));
+        __data_section_table_end = .;
+        __bss_section_table = .;
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+        LONG(    ADDR(.bss_RAM2));
+        LONG(  SIZEOF(.bss_RAM2));
+        LONG(    ADDR(.bss_RAM3));
+        LONG(  SIZEOF(.bss_RAM3));
+        LONG(    ADDR(.bss_RAM4));
+        LONG(  SIZEOF(.bss_RAM4));
+        LONG(    ADDR(.bss_RAM5));
+        LONG(  SIZEOF(.bss_RAM5));
+        __bss_section_table_end = .;
+        __section_table_end = . ;
+        /* End of Global Section Table */
+
+        *(.after_vectors*)
+
+       *(.text*)
+       *(.rodata .rodata.* .constdata .constdata.*)
+       . = ALIGN(4);
+    } > MFlashA512
+    /*
+     * for exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this.
+     */
+    .ARM.extab : ALIGN(4)
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > MFlashA512
+
+    .ARM.exidx : ALIGN(4)
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > MFlashA512
+
+    _etext = .;
+
+    /* DATA section for RamLoc40 */
+
+    .data_RAM2 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM2 = .) ;
+        PROVIDE(__start_data_RamLoc40 = .) ;
+        *(.ramfunc.$RAM2)
+        *(.ramfunc.$RamLoc40)
+        *(.data.$RAM2)
+        *(.data.$RamLoc40)
+        *(.data.$RAM2.*)
+        *(.data.$RamLoc40.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM2 = .) ;
+        PROVIDE(__end_data_RamLoc40 = .) ;
+     } > RamLoc40 AT>MFlashA512
+
+    /* DATA section for RamAHB32 */
+
+    .data_RAM3 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM3 = .) ;
+        PROVIDE(__start_data_RamAHB32 = .) ;
+        *(.ramfunc.$RAM3)
+        *(.ramfunc.$RamAHB32)
+        *(.data.$RAM3)
+        *(.data.$RamAHB32)
+        *(.data.$RAM3.*)
+        *(.data.$RamAHB32.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM3 = .) ;
+        PROVIDE(__end_data_RamAHB32 = .) ;
+     } > RamAHB32 AT>MFlashA512
+
+    /* DATA section for RamAHB16 */
+
+    .data_RAM4 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM4 = .) ;
+        PROVIDE(__start_data_RamAHB16 = .) ;
+        *(.ramfunc.$RAM4)
+        *(.ramfunc.$RamAHB16)
+        *(.data.$RAM4)
+        *(.data.$RamAHB16)
+        *(.data.$RAM4.*)
+        *(.data.$RamAHB16.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM4 = .) ;
+        PROVIDE(__end_data_RamAHB16 = .) ;
+     } > RamAHB16 AT>MFlashA512
+
+    /* DATA section for RamAHB_ETB16 */
+
+    .data_RAM5 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM5 = .) ;
+        PROVIDE(__start_data_RamAHB_ETB16 = .) ;
+        *(.ramfunc.$RAM5)
+        *(.ramfunc.$RamAHB_ETB16)
+        *(.data.$RAM5)
+        *(.data.$RamAHB_ETB16)
+        *(.data.$RAM5.*)
+        *(.data.$RamAHB_ETB16.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM5 = .) ;
+        PROVIDE(__end_data_RamAHB_ETB16 = .) ;
+     } > RamAHB_ETB16 AT>MFlashA512
+
+    /* MAIN DATA SECTION */
+    .uninit_RESERVED (NOLOAD) : ALIGN(4)
+    {
+        _start_uninit_RESERVED = .;
+        KEEP(*(.bss.$RESERVED*))
+       . = ALIGN(4) ;
+        _end_uninit_RESERVED = .;
+    } > RamLoc32 AT> RamLoc32
+
+    /* Main DATA section (RamLoc32) */
+    .data : ALIGN(4)
+    {
+       FILL(0xff)
+       _data = . ;
+       PROVIDE(__start_data_RAM = .) ;
+       PROVIDE(__start_data_RamLoc32 = .) ;
+       *(vtable)
+       *(.ramfunc*)
+       KEEP(*(CodeQuickAccess))
+       KEEP(*(DataQuickAccess))
+       *(RamFunction)
+       *(.data*)
+       . = ALIGN(4) ;
+       _edata = . ;
+       PROVIDE(__end_data_RAM = .) ;
+       PROVIDE(__end_data_RamLoc32 = .) ;
+    } > RamLoc32 AT>MFlashA512
+
+    /* BSS section for RamLoc40 */
+    .bss_RAM2 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM2 = .) ;
+       PROVIDE(__start_bss_RamLoc40 = .) ;
+       *(.bss.$RAM2)
+       *(.bss.$RamLoc40)
+       *(.bss.$RAM2.*)
+       *(.bss.$RamLoc40.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM2 = .) ;
+       PROVIDE(__end_bss_RamLoc40 = .) ;
+    } > RamLoc40 AT> RamLoc40
+
+    /* BSS section for RamAHB32 */
+    .bss_RAM3 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM3 = .) ;
+       PROVIDE(__start_bss_RamAHB32 = .) ;
+       *(.bss.$RAM3)
+       *(.bss.$RamAHB32)
+       *(.bss.$RAM3.*)
+       *(.bss.$RamAHB32.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM3 = .) ;
+       PROVIDE(__end_bss_RamAHB32 = .) ;
+    } > RamAHB32 AT> RamAHB32
+
+    /* BSS section for RamAHB16 */
+    .bss_RAM4 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM4 = .) ;
+       PROVIDE(__start_bss_RamAHB16 = .) ;
+       *(.bss.$RAM4)
+       *(.bss.$RamAHB16)
+       *(.bss.$RAM4.*)
+       *(.bss.$RamAHB16.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM4 = .) ;
+       PROVIDE(__end_bss_RamAHB16 = .) ;
+    } > RamAHB16 AT> RamAHB16
+
+    /* BSS section for RamAHB_ETB16 */
+    .bss_RAM5 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM5 = .) ;
+       PROVIDE(__start_bss_RamAHB_ETB16 = .) ;
+       *(.bss.$RAM5)
+       *(.bss.$RamAHB_ETB16)
+       *(.bss.$RAM5.*)
+       *(.bss.$RamAHB_ETB16.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM5 = .) ;
+       PROVIDE(__end_bss_RamAHB_ETB16 = .) ;
+    } > RamAHB_ETB16 AT> RamAHB_ETB16
+
+    /* MAIN BSS SECTION: EDIT change to RamLoc40 */
+    .bss : ALIGN(4)
+    {
+        _bss = .;
+        PROVIDE(__start_bss_RAM = .) ;
+        PROVIDE(__start_bss_RamLoc32 = .) ;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4) ;
+        _ebss = .;
+        PROVIDE(__end_bss_RAM = .) ;
+        PROVIDE(__end_bss_RamLoc32 = .) ;
+/*        PROVIDE(end = .);*/
+    } > RamLoc40 AT> RamLoc40 /* > RamLoc32 AT> RamLoc32 */
+
+    /* hathach add heap section for clang */
+    .heap (NOLOAD): {
+        __heap_start = .;
+        __HeapBase = .;
+        __heap_base = .;
+        __end = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        PROVIDE(__end__ = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+        __heap_limit = .;
+        __heap_end = .;
+    } > RamLoc40
+
+    /* NOINIT section for RamLoc40 */
+    .noinit_RAM2 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM2 = .) ;
+       PROVIDE(__start_noinit_RamLoc40 = .) ;
+       *(.noinit.$RAM2)
+       *(.noinit.$RamLoc40)
+       *(.noinit.$RAM2.*)
+       *(.noinit.$RamLoc40.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM2 = .) ;
+       PROVIDE(__end_noinit_RamLoc40 = .) ;
+    } > RamLoc40 AT> RamLoc40
+
+    /* NOINIT section for RamAHB32 */
+    .noinit_RAM3 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM3 = .) ;
+       PROVIDE(__start_noinit_RamAHB32 = .) ;
+       *(.noinit.$RAM3)
+       *(.noinit.$RamAHB32)
+       *(.noinit.$RAM3.*)
+       *(.noinit.$RamAHB32.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM3 = .) ;
+       PROVIDE(__end_noinit_RamAHB32 = .) ;
+    } > RamAHB32 AT> RamAHB32
+
+    /* NOINIT section for RamAHB16 */
+    .noinit_RAM4 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM4 = .) ;
+       PROVIDE(__start_noinit_RamAHB16 = .) ;
+       *(.noinit.$RAM4)
+       *(.noinit.$RamAHB16)
+       *(.noinit.$RAM4.*)
+       *(.noinit.$RamAHB16.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM4 = .) ;
+       PROVIDE(__end_noinit_RamAHB16 = .) ;
+    } > RamAHB16 AT> RamAHB16
+
+    /* NOINIT section for RamAHB_ETB16 */
+    .noinit_RAM5 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM5 = .) ;
+       PROVIDE(__start_noinit_RamAHB_ETB16 = .) ;
+       *(.noinit.$RAM5)
+       *(.noinit.$RamAHB_ETB16)
+       *(.noinit.$RAM5.*)
+       *(.noinit.$RamAHB_ETB16.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM5 = .) ;
+       PROVIDE(__end_noinit_RamAHB_ETB16 = .) ;
+    } > RamAHB_ETB16 AT> RamAHB_ETB16
+
+    /* DEFAULT NOINIT SECTION */
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        _noinit = .;
+        PROVIDE(__start_noinit_RAM = .) ;
+        PROVIDE(__start_noinit_RamLoc32 = .) ;
+        *(.noinit*)
+         . = ALIGN(4) ;
+        _end_noinit = .;
+       PROVIDE(__end_noinit_RAM = .) ;
+       PROVIDE(__end_noinit_RamLoc32 = .) ;
+    } > RamLoc32 AT> RamLoc32
+
+/*    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);*/
+
+    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+    /* ## Create checksum value (used in startup) ## */
+    /* This cause issue with clang linker, so it is disabled */
+    /* MemManage_Handler, BusFault_Handler, UsageFault_Hander may not be defined */
+/*    PROVIDE(__valid_user_code_checksum = 0 -*/
+/*                                         (_vStackTop*/
+/*                                         + (ResetISR + 1)*/
+/*                                         + (NMI_Handler + 1)*/
+/*                                         + (HardFault_Handler + 1)*/
+/*                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)*/
+/*                                         ) );*/
+
+    /* Provide basic symbols giving location and size of main text
+     * block, including initial values of RW data sections. Note that
+     * these will need extending to give a complete picture with
+     * complex images (e.g multiple Flash banks).
+     */
+    _image_start = LOADADDR(.text);
+    _image_end = LOADADDR(.data) + SIZEOF(.data);
+    _image_size = _image_end - _image_start;
+}
diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/lpc43/family.c
similarity index 64%
rename from hw/bsp/ea4357/ea4357.c
rename to hw/bsp/lpc43/family.c
index f88d3b89e..591090c36 100644
--- a/hw/bsp/ea4357/ea4357.c
+++ b/hw/bsp/lpc43/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,97 +24,70 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: NXP
+*/
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 #include "chip.h"
-#include "../board.h"
-#include "pca9532.h"
 
-#define UART_DEV        LPC_USART0
-#define UART_PORT       0x0f
-#define UART_PIN_TX     10
-#define UART_PIN_RX     11
-
-// P9_1 joystick down
-#define BUTTON_PORT     4
-#define BUTTON_PIN      13
-
-//static const struct {
-//  uint8_t mux_port;
-//  uint8_t mux_pin;
-//
-//  uint8_t gpio_port;
-//  uint8_t gpio_pin;
-//}buttons[] =
-//{
-//    {0x0a, 3, 4, 10 }, // Joystick up
-//    {0x09, 1, 4, 13 }, // Joystick down
-//    {0x0a, 2, 4, 9  }, // Joystick left
-//    {0x09, 0, 4, 12 }, // Joystick right
-//    {0x0a, 1, 4, 8  }, // Joystick press
-//    {0x02, 7, 0, 7  }, // SW6
-//};
-
-#ifdef BOARD_TUD_RHPORT
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
 #endif
 
-#ifdef BOARD_TUH_RHPORT
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
-#endif
-
-/*------------------------------------------------------------------*/
-/* BOARD API
- *------------------------------------------------------------------*/
+#include "bsp/board_api.h"
+#include "board.h"
 
 /* System configuration variables used by chip driver */
 const uint32_t OscRateIn = 12000000;
 const uint32_t ExtRateIn = 0;
 
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  // Button ( Joystick down )
-  {0x9, 1,  (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP)},
+extern void USB0_IRQHandler(void);
+extern void USB1_IRQHandler(void);
+extern void SysTick_Handler(void);
+void SystemInit(void);
 
-  // UART
-  {UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1},
-  {UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1},
-
-  // USB
-};
-
-/* Pin clock mux values, re-used structure, value in first index is meaningless */
-static const PINMUX_GRP_T pinclockmuxing[] =
-{
-  {0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 3,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-};
+/*------------------------------------------------------------------*/
+/* BOARD API
+ *------------------------------------------------------------------*/
 
 // Invoked by startup code
 void SystemInit(void)
 {
 #ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
   unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
+
+#ifdef __ICCARM__
+  extern void *__vector_table;
+  *pSCB_VTOR = (unsigned int) &__vector_table;
+
+#elif defined(__ARMCC_VERSION)
+  extern void *__Vectors;
+	*pSCB_VTOR = (unsigned int) &__Vectors;
+
+#else // other compoiler using cr_startup_lpc43xx.c
+	extern void (* const g_pfnVectors[])(void);
 	*pSCB_VTOR = (unsigned int) g_pfnVectors;
+#endif
 
 #if __FPU_USED == 1
 	fpuInit();
 #endif
-#endif // __USE_LPCOPEN
 
-	/* Setup system level pin muxing */
-	Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+#endif
 
-	/* Clock pins only, group field not used */
-	for (int i = 0; i <(int)  (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
-	{
-		Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
-	}
+  /* Setup system level pin muxing */
+  Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+
+//  /* Clock pins only, group field not used */
+//  for ( int i = 0; i < (int) (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++ ) {
+//    Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
+//  }
 
   Chip_SetupXtalClocking();
 }
@@ -133,13 +106,16 @@ void board_init(void)
 
   Chip_GPIO_Init(LPC_GPIO_PORT);
 
+#ifdef __PCA9532C_H
   // LED via pca9532 I2C
   Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
   Chip_I2C_Init(I2C0);
   Chip_I2C_SetClockRate(I2C0, 100000);
   Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling);
-
   pca9532_init();
+#else
+  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
+#endif
 
   // Button
   Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
@@ -182,9 +158,7 @@ void board_init(void)
    * - Insert jumpers in position 2-3 in JP17/JP18/JP19
    * - Insert jumpers in JP31 (OTG)
    */
-#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0)
   Chip_USB0_Init();
-#endif
 
   /* From EA4357 user manual
    *
@@ -207,17 +181,15 @@ void board_init(void)
    * - LED34 lights green when +5V is available on J20.
    * - JP15 shall not be inserted. JP16 has no effect
    */
-#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1)
   Chip_USB1_Init();
-#endif
 
   // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
   Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
 
-  #if PORT_SUPPORT_DEVICE(0)
-  // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
-  Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
+  #if defined(BOARD_TUD_RHPORT) &&  BOARD_TUD_RHPORT == 0
+    // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
+    Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
+    Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
   #endif
 
   // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
@@ -227,60 +199,49 @@ void board_init(void)
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(0)
-    tud_int_handler(0);
-  #endif
-
-  #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
-  #endif
+void USB0_IRQHandler(void) {
+  tusb_int_handler(0, true);
 }
 
-void USB1_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(1)
-    tud_int_handler(1);
-  #endif
-
-  #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
-  #endif
+void USB1_IRQHandler(void) {
+  tusb_int_handler(1, true);
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  if (state)
-  {
-    pca9532_setLeds( LED1, 0 );
-  }else
-  {
-    pca9532_setLeds( 0, LED1);
+void board_led_write(bool state) {
+  #ifdef __PCA9532C_H
+  if ( state ) {
+    pca9532_setLeds(LED1, 0);
+  } else {
+    pca9532_setLeds(0, LED1);
   }
+  #else
+  Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state ? LED_STATE_ON : !LED_STATE_ON);
+  #endif
 }
 
-uint32_t board_button_read(void)
-{
-  // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  if ( max_len < 16 ) return 0;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  Chip_IAP_ReadUID(id32);
+  return 16;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
   return Chip_UART_Read(UART_DEV, buf, len);
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const* buf8 = (uint8_t const*) buf;
-  for(int i=0; i<len; i++)
-  {
-    while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
+int board_uart_write(void const *buf, int len) {
+  uint8_t const *buf8 = (uint8_t const *) buf;
+  for ( int i = 0; i < len; i++ ) {
+    while ( (Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0 ) {}
     Chip_UART_SendByte(UART_DEV, buf8[i]);
   }
 
@@ -289,13 +250,13 @@ int board_uart_write(void const * buf, int len)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake
new file mode 100644
index 000000000..23c4aecea
--- /dev/null
+++ b/hw/bsp/lpc43/family.cmake
@@ -0,0 +1,111 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC43XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${SDK_DIR}/../gcc/cr_startup_lpc43xx.c)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${SDK_DIR}/../iar/iar_startup_lpc18xx43xx.s)
+  set(LD_FILE_IAR ${SDK_DIR}/../iar/linker/lpc18xx_43xx_ldscript_iflash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    ${SDK_DIR}/src/chip_18xx_43xx.c
+    ${SDK_DIR}/src/clock_18xx_43xx.c
+    ${SDK_DIR}/src/fpu_init.c
+    ${SDK_DIR}/src/gpio_18xx_43xx.c
+    ${SDK_DIR}/src/iap_18xx_43xx.c
+    ${SDK_DIR}/src/sysinit_18xx_43xx.c
+    ${SDK_DIR}/src/uart_18xx_43xx.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    CORE_M4
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${SDK_DIR}/inc/config_43xx
+    ${CMSIS_5}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -nostdlib
+      -Wno-error=incompatible-pointer-types
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC43XX)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc43/family.mk b/hw/bsp/lpc43/family.mk
new file mode 100644
index 000000000..e1406aae7
--- /dev/null
+++ b/hw/bsp/lpc43/family.mk
@@ -0,0 +1,39 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+SDK_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
+
+include ${TOP}/${BOARD_PATH}/board.mk
+CPU_CORE ?= cortex-m4
+
+CFLAGS += \
+  -flto \
+  -nostdlib \
+  -DCORE_M4 \
+  -D__USE_LPCOPEN \
+  -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
+
+# mcu driver cause following warnings
+CFLAGS += \
+  -Wno-error=unused-parameter \
+  -Wno-error=cast-qual \
+  -Wno-error=incompatible-pointer-types \
+
+LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
+
+SRC_C += \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
+	${SDK_DIR}/../gcc/cr_startup_lpc43xx.c \
+	${SDK_DIR}/src/chip_18xx_43xx.c \
+	${SDK_DIR}/src/clock_18xx_43xx.c \
+	${SDK_DIR}/src/fpu_init.c \
+	${SDK_DIR}/src/gpio_18xx_43xx.c \
+	${SDK_DIR}/src/iap_18xx_43xx.c \
+	${SDK_DIR}/src/sysinit_18xx_43xx.c \
+	${SDK_DIR}/src/uart_18xx_43xx.c \
+
+INC += \
+  $(TOP)/$(BOARD_PATH) \
+	${TOP}/${SDK_DIR}/inc \
+	${TOP}/${SDK_DIR}/inc/config_43xx \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
diff --git a/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..3bc226667
--- /dev/null
+++ b/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,169 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
+    defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake
new file mode 100644
index 000000000..1f549bf50
--- /dev/null
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT LPC51U68)
+
+set(JLINK_DEVICE LPC51U68)
+set(PYOCD_TARGET LPC51U68)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC51U68JBD64
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower.a
+    )
+endfunction()
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h
new file mode 100644
index 000000000..151fae24b
--- /dev/null
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h
@@ -0,0 +1,62 @@
+/* metadata:
+   name: LPCXpresso51u68
+   url: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+#define LED_PORT      0
+#define LED_PIN       29
+#define LED_STATE_ON  0
+
+// WAKE button
+#define BUTTON_PORT   0
+#define BUTTON_PIN    24
+
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN          0x80u   /*!< Enables digital function */
+#define IOCON_PIO_FUNC1               0x01u   /*!< Selects pin function 1 */
+#define IOCON_PIO_FUNC7               0x07u   /*!< Selects pin function 7 */
+#define IOCON_PIO_INPFILT_OFF       0x0100u   /*!< Input filter disabled */
+#define IOCON_PIO_INV_DI              0x00u   /*!< Input function is not inverted */
+#define IOCON_PIO_MODE_INACT          0x00u   /*!< No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI        0x00u   /*!< Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD       0x00u   /*!< Standard mode, output slew rate control is enabled */
+
+/****************************************************************
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: SYSTICK_clock.outFreq, value: 96 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+******************************************************************/
+static inline void BootClockFROHF96M(void) {
+  /*!< Set up the clock sources */
+  /*!< Set up FRO */
+  POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                             accidentally being below the voltage for current speed */
+  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
+
+  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+  /*!< Set up dividers */
+  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
+  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true);  /*!< Reset SYSTICKCLKDIV divider counter and halt it */
+  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */
+
+  /*!< Set up clock selectors - Attach clocks to the peripheries */
+  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+  /*!< Set SystemCoreClock variable. */
+  SystemCoreClock = 96000000U;
+}
+
+#endif
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
new file mode 100644
index 000000000..5627cb024
--- /dev/null
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
@@ -0,0 +1,11 @@
+MCU = LPC51U68
+
+CFLAGS += \
+  -DCPU_LPC51U68JBD64 \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))'
+
+JLINK_DEVICE = LPC51U68
+PYOCD_TARGET = LPC51U68
+
+# flash using pyocd (51u68 is not supported yet)
+flash: flash-pyocd
diff --git a/hw/bsp/lpc51/family.c b/hw/bsp/lpc51/family.c
new file mode 100644
index 000000000..0afe33d41
--- /dev/null
+++ b/hw/bsp/lpc51/family.c
@@ -0,0 +1,145 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: NXP
+*/
+
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_power.h"
+#include "fsl_iocon.h"
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+void board_init(void) {
+  // Enable IOCON clock
+  CLOCK_EnableClock(kCLOCK_Iocon);
+
+  // Enable GPIO0 clock
+  CLOCK_EnableClock(kCLOCK_Gpio0);
+
+  // Init 96 MHz clock
+  BootClockFROHF96M();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  GPIO_PortInit(GPIO, LED_PORT);
+  GPIO_PortInit(GPIO, BUTTON_PORT);
+
+  // LED
+  gpio_pin_config_t const led_config = {kGPIO_DigitalOutput, 0};
+  GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
+  board_led_write(true);
+
+  // Button
+  gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
+  GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
+
+  // USB
+  const uint32_t port1_pin6_config = (
+      IOCON_PIO_FUNC7       | /* Pin is configured as USB0_VBUS */
+      IOCON_PIO_MODE_INACT  | /* No addition pin function */
+      IOCON_PIO_INV_DI      | /* Input function is not inverted */
+      IOCON_PIO_DIGITAL_EN  | /* Enables digital function */
+      IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
+      IOCON_PIO_OPENDRAIN_DI  /* Open drain is disabled */
+  );
+  IOCON_PinMuxSet(IOCON, 1, 6, port1_pin6_config); /* PORT1 PIN6 (coords: 26) is configured as USB0_VBUS */
+
+  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*Turn on USB Phy */
+  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  // active low
+  return 1 - GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void	_exit (int __status) {
+  while (1) {}
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake
new file mode 100644
index 000000000..2146c29f7
--- /dev/null
+++ b/hw/bsp/lpc51/family.cmake
@@ -0,0 +1,122 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC51 CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}_flash.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    # driver
+    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    __STARTUP_CLEAR_BSS
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC51)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpcxpresso51u68/board.mk b/hw/bsp/lpc51/family.mk
similarity index 53%
rename from hw/bsp/lpcxpresso51u68/board.mk
rename to hw/bsp/lpc51/family.mk
index 98bef6758..b41b5438e 100644
--- a/hw/bsp/lpcxpresso51u68/board.mk
+++ b/hw/bsp/lpc51/family.mk
@@ -1,27 +1,28 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_LPC51U68JBD64 \
+  -D__STARTUP_CLEAR_BSS \
   -DCFG_TUSB_MCU=OPT_MCU_LPC51UXX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
 
-MCU_DIR = $(SDK_DIR)/devices/LPC51U68
+LDFLAGS_GCC += \
+  -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
 
 # All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/LPC51U68_flash.ld
+LD_FILE = $(MCU_DIR)/gcc/$(MCU)_flash.ld
 
 SRC_C += \
 	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/system_LPC51U68.c \
+	$(MCU_DIR)/system_$(MCU).c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(MCU_DIR)/drivers/fsl_power.c \
 	$(MCU_DIR)/drivers/fsl_reset.c \
@@ -30,23 +31,15 @@ SRC_C += \
 	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
 
 INC += \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+  $(TOP)/$(BOARD_PATH) \
+  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
 	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio	
+	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
 
-SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
+SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
 
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-JLINK_DEVICE = LPC51U68
-PYOCD_TARGET = LPC51U68
-
-# flash using pyocd (51u68 is not supported yet)
-flash: flash-pyocd
diff --git a/hw/bsp/lpc54/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc54/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6f10a7ab0
--- /dev/null
+++ b/hw/bsp/lpc54/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake
new file mode 100644
index 000000000..c0bbeecd5
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT LPC54114)
+set(MCU_CORE LPC54114_cm4)
+
+set(JLINK_DEVICE LPC54114J256_M4)
+set(PYOCD_TARGET LPC54114)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54114J256_cm4_flash.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54114J256BD64_cm4
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_cm4_hardabi.a
+    )
+endfunction()
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
index b1ad4258c..c43ca9d7d 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
+++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: LPCXpresso54114
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54114-board:OM13089
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake
new file mode 100644
index 000000000..f0715fa12
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake
@@ -0,0 +1,22 @@
+set(MCU_VARIANT LPC54608)
+set(MCU_CORE LPC54608)
+
+set(JLINK_DEVICE LPC54608J512)
+set(PYOCD_TARGET LPC54608)
+set(NXPLINK_DEVICE LPC54608:LPCXpresso54608)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54608J512_flash.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54608J512ET180
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_hardabi.a
+    )
+endfunction()
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
new file mode 100644
index 000000000..e985e97e0
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
@@ -0,0 +1,64 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: LPCXpresso54608
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-development-board-for-lpc5460x-mcus:OM13092
+*/
+
+#ifndef BOARD_LPCXPRESSO54608_H_
+#define BOARD_LPCXPRESSO54608_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              2
+#define LED_PIN               2
+#define LED_STATE_ON          0
+
+// WAKE button
+#define BUTTON_PORT           1
+#define BUTTON_PIN            1
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              USART0
+#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
+#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
+
+// USB0 VBUS
+#define USB0_VBUS_PINMUX      0, 22, IOCON_PIO_DIG_FUNC7_EN
+
+// XTAL
+//#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk b/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk
new file mode 100644
index 000000000..af2eaf507
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk
@@ -0,0 +1,18 @@
+MCU_VARIANT = LPC54608
+MCU_CORE = LPC54608
+
+PORT ?= 1
+
+CFLAGS += -DCPU_LPC54608J512ET180
+CFLAGS += -Wno-error=double-promotion
+
+LD_FILE = $(MCU_DIR)/gcc/LPC54608J512_flash.ld
+
+LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
+
+JLINK_DEVICE = LPC54608J512
+PYOCD_TARGET = LPC54608
+
+#flash: flash-pyocd
+
+flash: flash-jlink
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
new file mode 100644
index 000000000..1dea6f353
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
@@ -0,0 +1,22 @@
+set(MCU_VARIANT LPC54628)
+set(MCU_CORE LPC54628)
+
+set(JLINK_DEVICE LPC54628J512)
+set(PYOCD_TARGET LPC54628)
+set(NXPLINK_DEVICE LPC54628:LPCXpresso54628)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54628J512_flash.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54628J512ET180
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_hardabi.a
+    )
+endfunction()
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
index 670277512..837d26aef 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: LPCXpresso54628
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54628-development-board:OM13098
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk b/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
index 925374cc8..e0b382aeb 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
@@ -1,7 +1,7 @@
 MCU_VARIANT = LPC54628
 MCU_CORE = LPC54628
 
-PORT ?= 0
+PORT ?= 1
 
 CFLAGS += -DCPU_LPC54628J512ET180
 CFLAGS += -Wno-error=double-promotion
@@ -15,4 +15,4 @@ PYOCD_TARGET = LPC54628
 
 #flash: flash-pyocd
 
-flash: flash-jlink
\ No newline at end of file
+flash: flash-jlink
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 9bb341e73..9b9b5841b 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -24,27 +24,19 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: NXP
+*/
+
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
 #include "fsl_power.h"
 #include "fsl_iocon.h"
 #include "fsl_usart.h"
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
-#ifdef BOARD_TUD_RHPORT
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
-#endif
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -70,14 +62,12 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
+void USB0_IRQHandler(void) {
+  tusb_int_handler(0, true);
 }
 
-void USB1_IRQHandler(void)
-{
-  tud_int_handler(1);
+void USB1_IRQHandler(void) {
+  tusb_int_handler(1, true);
 }
 
 /****************************************************************
@@ -90,8 +80,7 @@ settings:
 sources:
 - {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
 ******************************************************************/
-void BootClockFROHF96M(void)
-{
+void BootClockFROHF96M(void) {
   /*!< Set up the clock sources */
   /*!< Set up FRO */
   POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
@@ -112,8 +101,7 @@ void BootClockFROHF96M(void)
   SystemCoreClock = 96000000U;
 }
 
-void board_init(void)
-{
+void board_init(void) {
   // Enable IOCON clock
   CLOCK_EnableClock(kCLOCK_Iocon);
 
@@ -164,13 +152,13 @@ void board_init(void)
 
 #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
   // LPC546xx and LPC540xx has OTG 1 FS + 1 HS rhports
-  #if PORT_SUPPORT_DEVICE(0)
+  #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
     // Port0 is Full Speed
     POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB Phy */
     CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
     CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
 
-    /*According to reference mannual, device mode setting has to be set by access usb host register */
+    /*According to reference manual, device mode setting has to be set by access usb host register */
     CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */
     USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
     CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */
@@ -178,11 +166,11 @@ void board_init(void)
     CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
   #endif
 
-  #if PORT_SUPPORT_DEVICE(1)
+  #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1
     // Port1 is High Speed
     POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
 
-    /*According to reference mannual, device mode setting has to be set by access usb host register */
+    /*According to reference manual, device mode setting has to be set by access usb host register */
     CLOCK_EnableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
     USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
     CLOCK_DisableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
@@ -200,38 +188,53 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   // active low
   return BUTTON_STATE_ACTIVE == GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  USART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+int board_uart_write(void const* buf, int len) {
+  USART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
   return 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
+
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void	_exit (int __status) {
+  while (1) {}
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
new file mode 100644
index 000000000..90497b9fb
--- /dev/null
+++ b/hw/bsp/lpc54/family.cmake
@@ -0,0 +1,155 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC54 CACHE INTERNAL "")
+
+if (NOT DEFINED PORT)
+  set(PORT 0)
+endif()
+
+# Host port will be the other port if available
+set(HOST_PORT $<NOT:${PORT}>)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    # driver
+    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/sctimer
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    BOARD_TUD_RHPORT=${PORT}
+    BOARD_TUH_RHPORT=${HOST_PORT}
+    __STARTUP_CLEAR_BSS
+    )
+
+  # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+  if (PORT EQUAL 1)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+      CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      )
+  else ()
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      )
+  endif ()
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+
+  # https://github.com/gsteiert/sct_neopixel/pull/1
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    set_source_files_properties(${TOP}/lib/sct_neopixel/sct_neopixel.c PROPERTIES
+      COMPILE_FLAGS "-Wno-unused-parameter")
+  endif ()
+
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC54)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index 39111d1ad..ea4c9c39c 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -1,22 +1,20 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
+  -D__STARTUP_CLEAR_BSS \
   -DCFG_TUSB_MCU=OPT_MCU_LPC54XXX \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
 
 ifeq ($(PORT), 1)
   $(info "PORT1 High Speed")
   CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
+  CFLAGS += -DBOARD_TUD_RHPORT=1
   # LPC55 Highspeed Port1 can only write to USB_SRAM region
   CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
 else
@@ -26,7 +24,9 @@ endif
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
 
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
+LDFLAGS_GCC += \
+  -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
 
 SRC_C += \
 	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
@@ -36,11 +36,12 @@ SRC_C += \
 	$(MCU_DIR)/drivers/fsl_reset.c \
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
+	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
+	$(SDK_DIR)/drivers/common/fsl_common_arm.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
@@ -49,6 +50,3 @@ INC += \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
 
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..d3f357576
--- /dev/null
+++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,150 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+#define configRUN_FREERTOS_SECURE_ONLY          1
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld b/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld
index 6b5d852aa..e2197b972 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld
+++ b/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld
@@ -231,4 +231,3 @@ SECTIONS
 
   ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
 }
-
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
new file mode 100644
index 000000000..3324ce888
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
@@ -0,0 +1,19 @@
+set(MCU_VARIANT LPC55S69)
+set(MCU_CORE LPC55S69_cm33_core0)
+
+set(JLINK_DEVICE LPC55S69)
+set(PYOCD_TARGET LPC55S69)
+set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC55S69JBD100_cm33_core0
+    )
+endfunction()
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.h b/hw/bsp/lpc55/boards/double_m33_express/board.h
index 975e74e92..dc11e47fc 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/board.h
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Double M33 Express
+   url: https://www.crowdsupply.com/steiert-solutions/double-m33-express
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
new file mode 100644
index 000000000..b3d0c3349
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
@@ -0,0 +1,17 @@
+set(MCU_VARIANT LPC55S28)
+set(MCU_CORE LPC55S28)
+
+set(JLINK_DEVICE LPC55S28)
+set(PYOCD_TARGET LPC55S28)
+set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC55S28JBD100
+    )
+endfunction()
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h
index f85701b08..907aee6a4 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: LPCXpresso55s28
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s28-development-board:LPC55S28-EVK
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
new file mode 100644
index 000000000..b52ec2f9d
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
@@ -0,0 +1,17 @@
+set(MCU_VARIANT LPC55S69)
+set(MCU_CORE LPC55S69_cm33_core0)
+
+set(JLINK_DEVICE LPC55S69_M33_0)
+set(PYOCD_TARGET LPC55S69)
+set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC55S69JBD100_cm33_core0
+    )
+endfunction()
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h
index f85701b08..e18d5bbad 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: LPCXpresso55s69
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/lpc55/boards/mcu_link/board.cmake b/hw/bsp/lpc55/boards/mcu_link/board.cmake
new file mode 100644
index 000000000..fd7cb6de6
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT LPC55S69)
+set(MCU_CORE LPC55S69_cm33_core0)
+
+set(JLINK_DEVICE LPC55S69)
+set(PYOCD_TARGET LPC55S69)
+set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC55S69JBD100_cm33_core0
+    # port 1 is highspeed
+    # BOARD_TUD_RHPORT=1
+    )
+endfunction()
diff --git a/hw/bsp/lpc55/boards/mcu_link/board.h b/hw/bsp/lpc55/boards/mcu_link/board.h
index 5e17cf9fd..1d71b3e79 100644
--- a/hw/bsp/lpc55/boards/mcu_link/board.h
+++ b/hw/bsp/lpc55/boards/mcu_link/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: MCU Link
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcu-link-debug-probe:MCU-LINK
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index e7aed5759..dbf8d71b7 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -24,26 +24,21 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+/* metadata:
+   manufacturer: NXP
+*/
+
+#include "bsp/board_api.h"
 #include "board.h"
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
 #include "fsl_power.h"
 #include "fsl_iocon.h"
 #include "fsl_usart.h"
+
+#ifdef NEOPIXEL_PIN
 #include "fsl_sctimer.h"
 #include "sct_neopixel.h"
-
-#ifdef BOARD_TUD_RHPORT
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
 #endif
 
 //--------------------------------------------------------------------+
@@ -69,64 +64,94 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
+void USB0_IRQHandler(void) {
+  tusb_int_handler(0, true);
 }
 
-void USB1_IRQHandler(void)
-{
-  tud_int_handler(1);
+void USB1_IRQHandler(void) {
+  tusb_int_handler(1, true);
 }
 
 /****************************************************************
-name: BOARD_BootClockFROHF96M
+name: BOARD_BootClockPLL100M
 outputs:
-- {id: SYSTICK_clock.outFreq, value: 96 MHz}
-- {id: System_clock.outFreq, value: 96 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
 settings:
-- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
 sources:
-- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
 ******************************************************************/
-void BootClockFROHF96M(void)
+void BOARD_BootClockPLL100M(void)
 {
-  /*!< Set up the clock sources */
-  /*!< Set up FRO */
-  POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on  */
-  CLOCK_SetupFROClocking(12000000U);     /*!< Set up FRO to the 12 MHz, just for sure */
-  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
-                                             accidentally being below the voltage for current speed */
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
 
-  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
 
-  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
 
-  /*!< Set up dividers */
-  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
 
-  /*!< Set up clock selectors - Attach clocks to the peripheries */
-  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
 
-  /*!< Set SystemCoreClock variable. */
-  SystemCoreClock = 96000000U;
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = 100000000U;
 }
 
-void board_init(void)
-{
+void board_init(void) {
   // Enable IOCON clock
   CLOCK_EnableClock(kCLOCK_Iocon);
 
-  // Init 96 MHz clock
-  BootClockFROHF96M();
+  // Init 100 MHz clock
+  BOARD_BootClockPLL100M();
 
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
   // Init all GPIO ports
@@ -135,7 +160,7 @@ void board_init(void)
 
   // LED
   IOCON_PinMuxSet(IOCON, LED_PORT, LED_PIN, IOCON_PIO_DIG_FUNC0_EN);
-  gpio_pin_config_t const led_config = { kGPIO_DigitalOutput, 1};
+  gpio_pin_config_t const led_config = {kGPIO_DigitalOutput, 1};
   GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
 
   board_led_write(0);
@@ -154,7 +179,7 @@ void board_init(void)
 
   // Button
   IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN);
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
+  gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
   GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
 
 #ifdef UART_DEV
@@ -167,8 +192,8 @@ void board_init(void)
   usart_config_t uart_config;
   USART_GetDefaultConfig(&uart_config);
   uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx     = true;
-  uart_config.enableRx     = true;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
   USART_Init(UART_DEV, &uart_config, 12000000);
 #endif
 
@@ -176,7 +201,7 @@ void board_init(void)
   /* PORT0 PIN22 configured as USB0_VBUS */
   IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
 
-#if PORT_SUPPORT_DEVICE(0)
+#if defined(BOARD_TUD_RHPORT)  && BOARD_TUD_RHPORT == 0
   // Port0 is Full Speed
 
   /* Turn on USB0 Phy */
@@ -192,7 +217,7 @@ void board_init(void)
   CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
   CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
 
-  /*According to reference mannual, device mode setting has to be set by access usb host register */
+  /*According to reference manual, device mode setting has to be set by access usb host register */
   CLOCK_EnableClock(kCLOCK_Usbhsl0);  // enable usb0 host clock
   USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
   CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
@@ -201,7 +226,7 @@ void board_init(void)
   CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
 #endif
 
-#if PORT_SUPPORT_DEVICE(1)
+#if defined(BOARD_TUD_RHPORT)  && BOARD_TUD_RHPORT == 1
   // Port1 is High Speed
 
   /* Turn on USB1 Phy */
@@ -213,7 +238,7 @@ void board_init(void)
   RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
   RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
 
-  /* According to reference mannual, device mode setting has to be set by access usb host register */
+  /* According to reference manual, device mode setting has to be set by access usb host register */
   CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
 
   USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
@@ -240,6 +265,10 @@ void board_init(void)
 //  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
 //  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
 //  USBPHY->TX = phytx;
+
+    ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
+    ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
+    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
 #endif
 }
 
@@ -247,9 +276,8 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 
 #ifdef NEOPIXEL_PIN
   if (state) {
@@ -263,33 +291,50 @@ void board_led_write(bool state)
 #endif
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   // active low
   return BUTTON_STATE_ACTIVE == GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  USART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+int board_uart_write(void const* buf, int len) {
+  USART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
   return len;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
+
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void	_exit (int __status) {
+  while (1) {}
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
new file mode 100644
index 000000000..cd1eb5f78
--- /dev/null
+++ b/hw/bsp/lpc55/family.cmake
@@ -0,0 +1,156 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC55 CACHE INTERNAL "")
+
+if (NOT DEFINED PORT)
+  set(PORT 0)
+endif()
+
+# Host port will be the other port if available
+set(HOST_PORT $<NOT:${PORT}>)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    # driver
+    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/sctimer
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    BOARD_TUD_RHPORT=${PORT}
+    BOARD_TUH_RHPORT=${HOST_PORT}
+    __STARTUP_CLEAR_BSS
+    )
+
+  # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+  if (PORT EQUAL 1)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+      CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      )
+  else ()
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      )
+  endif ()
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    # external driver
+    ${TOP}/lib/sct_neopixel/sct_neopixel.c
+    )
+
+  # https://github.com/gsteiert/sct_neopixel/pull/1
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    set_source_files_properties(${TOP}/lib/sct_neopixel/sct_neopixel.c PROPERTIES
+      COMPILE_FLAGS "-Wno-unused-parameter")
+  endif ()
+
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC55)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index 9d6702b94..d82e85904 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -1,22 +1,20 @@
 UF2_FAMILY_ID = 0x2abc77ec
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += lib/sct_neopixel $(SDK_DIR)
+DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
+MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
 
 # Default to Highspeed PORT1
 PORT ?= 1
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m33 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
+  -D__STARTUP_CLEAR_BSS \
   -DCFG_TUSB_MCU=OPT_MCU_LPC55XX \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
-  -DBOARD_TUD_RHPORT=$(PORT)
+  -DBOARD_TUD_RHPORT=$(PORT) \
 
 ifeq ($(PORT), 1)
   $(info "PORT1 High Speed")
@@ -31,7 +29,9 @@ endif
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal
 
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
+LDFLAGS_GCC += \
+  -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
 
 # All source paths should be relative to the top level.
 LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_CORE)_flash.ld
@@ -51,7 +51,7 @@ SRC_C += \
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/sct_neopixel \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
@@ -63,6 +63,3 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
 
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
deleted file mode 100644
index be6d2ed52..000000000
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0 \
-  -nostdlib \
-  -DCORE_M0 \
-  -D__USE_LPCOPEN \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_EXAMPLE_VIDEO_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=redundant-decls
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc11uxx/lpc_chip_11uxx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc11u37.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc11xx.c \
-	$(MCU_DIR)/src/chip_11xx.c \
-	$(MCU_DIR)/src/clock_11xx.c \
-	$(MCU_DIR)/src/gpio_11xx_1.c \
-	$(MCU_DIR)/src/iocon_11xx.c \
-	$(MCU_DIR)/src/sysctl_11xx.c \
-	$(MCU_DIR)/src/sysinit_11xx.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = LPC11U37/401
-
-# flash using pyocd 
-flash: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t lpc11u37 $<
diff --git a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c b/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
deleted file mode 100644
index 11f1797a2..000000000
--- a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//---------------------------------------------------------------- ----+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              1
-#define LED_PIN               24
-#define LED_STATE_ON          0
-
-// Wake up Switch
-#define BUTTON_PORT           0
-#define BUTTON_PIN            16
-#define BUTTON_STATE_ACTIVE   0
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-/* Pin muxing table, only items that need changing from their default pin
-   state are in this table. Not every pin is mapped. */
-/* IOCON pin definitions for pin muxing */
-typedef struct {
-	uint32_t port : 8;			/* Pin port */
-	uint32_t pin : 8;			/* Pin number */
-	uint32_t modefunc : 16;		/* Function and mode */
-} PINMUX_GRP_T;
-
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {0,  3, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
-  {0,  6, (IOCON_FUNC1 | IOCON_MODE_INACT)},		/* PIO0_6 used for USB_CONNECT */
-
-  {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
-  {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
-};
-
-/* Setup system clocking */
-static void SystemSetupClocking(void)
-{
-	volatile int i;
-
-	/* Powerup main oscillator */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
-
-	/* Wait 200us for OSC to be stablized, no status
-	   indication, dummy wait. */
-	for (i = 0; i < 0x100; i++) {}
-
-	/* Set system PLL input to main oscillator */
-	Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
-
-	/* Power down PLL to change the PLL divider ratio */
-	Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
-
-	/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
-	   MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
-	   FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
-	   FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
-	Chip_Clock_SetupSystemPLL(3, 1);
-
-	/* Powerup system PLL */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
-
-	/* Wait for PLL to lock */
-	while (!Chip_Clock_IsSystemPLLLocked()) {}
-
-	/* Set system clock divider to 1 */
-	Chip_Clock_SetSysClockDiv(1);
-
-	/* Setup FLASH access to 3 clocks */
-	Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
-
-	/* Set main clock source to the system PLL. This will drive 48MHz
-	   for the main clock and 48MHz for the system clock */
-	Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
-
-	/* Set USB PLL input to main oscillator */
-	Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
-	/* Setup USB PLL  (FCLKIN = 12MHz) * 4 = 48MHz
-	   MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
-	   FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
-	   FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
-	Chip_Clock_SetupUSBPLL(3, 1);
-
-	/* Powerup USB PLL */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
-
-	/* Wait for PLL to lock */
-	while (!Chip_Clock_IsUSBPLLLocked()) {}
-}
-
-// Invoked by startup code
-void SystemInit(void)
-{
-  SystemSetupClocking();
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RAM1);
-
-  /* Enable IOCON clock */
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
-  for (uint32_t i = 0; i < (sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); i++)
-  {
-		Chip_IOCON_PinMuxSet(LPC_IOCON, pinmuxing[i].port, pinmuxing[i].pin, pinmuxing[i].modefunc);
-	}
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-  // USB: Setup PLL clock, and power
-	/* enable USB main clock */
-	Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);
-	/* Enable AHB clock to the USB block and USB RAM. */
-	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
-	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USBRAM);
-	/* power UP USB Phy */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/lpcxpresso11u68/board.mk b/hw/bsp/lpcxpresso11u68/board.mk
deleted file mode 100644
index 922414f82..000000000
--- a/hw/bsp/lpcxpresso11u68/board.mk
+++ /dev/null
@@ -1,42 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -nostdlib \
-  -DCORE_M0PLUS \
-  -D__VTOR_PRESENT=0 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc11u6x/lpc_chip_11u6x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc11u68.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc11u6x.c \
-	$(MCU_DIR)/src/chip_11u6x.c \
-	$(MCU_DIR)/src/clock_11u6x.c \
-	$(MCU_DIR)/src/gpio_11u6x.c \
-	$(MCU_DIR)/src/iocon_11u6x.c \
-	$(MCU_DIR)/src/syscon_11u6x.c \
-	$(MCU_DIR)/src/sysinit_11u6x.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = LPC11U68
-
-# flash using pyocd 
-flash: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t lpc11u68 $<
diff --git a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
deleted file mode 100644
index b7bce93d2..000000000
--- a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  #if CFG_TUD_ENABLED
-    tud_int_handler(0);
-  #endif
-
-  #if CFG_TUH_ENABLED
-    tuh_int_handler(0);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              0
-#define LED_PIN               22
-#define LED_STATE_ON          1
-
-// JOYSTICK_DOWN if using LPCXpresso Base Board
-#define BUTTON_PORT           0
-#define BUTTON_PIN            15
-#define BUTTON_STATE_ACTIVE   0
-
-#define BOARD_UART_PORT   LPC_UART3
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing configuration */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {0,  0,   IOCON_MODE_INACT | IOCON_FUNC2},	/* TXD3 */
-  {0,  1,   IOCON_MODE_INACT | IOCON_FUNC2},	/* RXD3 */
-  {LED_PORT, LED_PIN,  IOCON_MODE_INACT | IOCON_FUNC0},	/* Led 0 */
-
-  /* Joystick buttons. */
-//  {2, 3,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_UP */
-  {BUTTON_PORT, BUTTON_PIN, IOCON_FUNC0 | IOCON_MODE_PULLUP},	/* JOYSTICK_DOWN */
-//  {2, 4,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_LEFT */
-//  {0, 16, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_RIGHT */
-//  {0, 17, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_PRESS */
-};
-
-static const PINMUX_GRP_T pin_usb_mux[] =
-{
-  {0, 29, IOCON_MODE_INACT | IOCON_FUNC1}, // D+
-  {0, 30, IOCON_MODE_INACT | IOCON_FUNC1}, // D-
-  {2,  9, IOCON_MODE_INACT | IOCON_FUNC1}, // Soft Connect
-
-  {1, 19, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PPWR (Host mode)
-
-  // VBUS is not connected on this board, so leave the pin at default setting.
-  /// Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);  // USB VBUS
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
-#endif
-
-  Chip_IOCON_Init(LPC_IOCON);
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-  Chip_SetupXtalClocking();
-
-  Chip_SYSCTL_SetFLASHAccess(FLASHTIM_100MHZ_CPU);
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-#if 0
-  //------------- UART -------------//
-  PINSEL_CFG_Type PinCfg =
-  {
-      .Portnum   = 0,
-      .Pinnum    = 0, // TXD is P0.0
-      .Funcnum   = 2,
-      .OpenDrain = 0,
-      .Pinmode   = 0
-  };
-	PINSEL_ConfigPin(&PinCfg);
-
-	PinCfg.Portnum = 0;
-	PinCfg.Pinnum  = 1; // RXD is P0.1
-	PINSEL_ConfigPin(&PinCfg);
-
-	UART_CFG_Type UARTConfigStruct;
-  UART_ConfigStructInit(&UARTConfigStruct);
-	UARTConfigStruct.Baud_rate = CFG_BOARD_UART_BAUDRATE;
-
-	UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
-	UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
-#endif
-
-	//------------- USB -------------//
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
-	Chip_USB_Init();
-
-  enum {
-    USBCLK_DEVCIE = 0x12,     // AHB + Device
-    USBCLK_HOST   = 0x19,     // AHB + Host + OTG
-//    0x1B // Host + Device + OTG + AHB
-  };
-
-  uint32_t const clk_en = CFG_TUD_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
-
-  LPC_USB->OTGClkCtrl = clk_en;
-  while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
-
-#if CFG_TUH_ENABLED
-  // set portfunc to host !!!
-  LPC_USB->StCtrl = 0x3; // should be 1
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-//  return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-//  UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c b/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c
deleted file mode 100644
index 6bade7743..000000000
--- a/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_power.h"
-#include "fsl_iocon.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT      0
-#define LED_PIN       29
-#define LED_STATE_ON  0
-
-// WAKE button
-#define BUTTON_PORT   0
-#define BUTTON_PIN    24
-
-// IOCON pin mux
-#define IOCON_PIO_DIGITAL_EN          0x80u   /*!< Enables digital function */
-#define IOCON_PIO_FUNC1               0x01u   /*!< Selects pin function 1 */
-#define IOCON_PIO_FUNC7               0x07u   /*!< Selects pin function 7 */
-#define IOCON_PIO_INPFILT_OFF       0x0100u   /*!< Input filter disabled */
-#define IOCON_PIO_INV_DI              0x00u   /*!< Input function is not inverted */
-#define IOCON_PIO_MODE_INACT          0x00u   /*!< No addition pin function */
-#define IOCON_PIO_OPENDRAIN_DI        0x00u   /*!< Open drain is disabled */
-#define IOCON_PIO_SLEW_STANDARD       0x00u   /*!< Standard mode, output slew rate control is enabled */
-
-/****************************************************************
-name: BOARD_BootClockFROHF96M
-outputs:
-- {id: SYSTICK_clock.outFreq, value: 96 MHz}
-- {id: System_clock.outFreq, value: 96 MHz}
-settings:
-- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
-sources:
-- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
-******************************************************************/
-void BootClockFROHF96M(void)
-{
-  /*!< Set up the clock sources */
-  /*!< Set up FRO */
-  POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
-  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
-                                             accidentally being below the voltage for current speed */
-  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
-
-  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
-
-  /*!< Set up dividers */
-  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
-  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true);  /*!< Reset SYSTICKCLKDIV divider counter and halt it */
-  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */
-
-  /*!< Set up clock selectors - Attach clocks to the peripheries */
-  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
-  /*!< Set SystemCoreClock variable. */
-  SystemCoreClock = 96000000U;
-}
-
-void board_init(void)
-{
-  // Enable IOCON clock
-  CLOCK_EnableClock(kCLOCK_Iocon);
-
-  // Enable GPIO0 clock
-  CLOCK_EnableClock(kCLOCK_Gpio0);
-
-  // Init 96 MHz clock
-  BootClockFROHF96M();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  GPIO_PortInit(GPIO, LED_PORT);
-  GPIO_PortInit(GPIO, BUTTON_PORT);
-
-  // LED
-  gpio_pin_config_t const led_config = { kGPIO_DigitalOutput, 0};
-  GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
-  board_led_write(true);
-
-  // Button
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
-  GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
-
-  // USB
-  const uint32_t port1_pin6_config = (
-    IOCON_PIO_FUNC7       | /* Pin is configured as USB0_VBUS */
-    IOCON_PIO_MODE_INACT  | /* No addition pin function */
-    IOCON_PIO_INV_DI      | /* Input function is not inverted */
-    IOCON_PIO_DIGITAL_EN  | /* Enables digital function */
-    IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
-    IOCON_PIO_OPENDRAIN_DI  /* Open drain is disabled */
-  );
-  IOCON_PinMuxSet(IOCON, 1, 6, port1_pin6_config); /* PORT1 PIN6 (coords: 26) is configured as USB0_VBUS */
-
-  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*Turn on USB Phy */
-  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return 1-GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..e5a76af85
--- /dev/null
+++ b/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "mxc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/max32650/README.md b/hw/bsp/max32650/README.md
new file mode 100644
index 000000000..ca66a1ac4
--- /dev/null
+++ b/hw/bsp/max32650/README.md
@@ -0,0 +1,46 @@
+# Analog Devices MAX32650/1/2
+
+This BSP is for working with the Analog Devices
+[MAX32650](https://www.analog.com/en/products/max32650.html),
+[MAX32651](https://www.analog.com/en/products/max32651.html) and
+[MAX32652](https://www.analog.com/en/products/max32652.html)
+microcontrollers.  The following boards are supported:
+ * [MAX32650EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html)
+ * [MAX32650FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html)
+ * [MAX32651EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html) (Secure Bootloader)
+
+This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
+interfaces and hardware abstraction layers. This source code package is fetched
+as part of the get-deps script.
+
+The microcontrollers utilize the standard GNU ARM toolchain.  If this toolchain
+is not already available on your build machine, it can be installed by using the
+bundled MSDK installation.  Details on downloading and installing can be found
+in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
+
+## Flashing
+
+### MAX32650 and MAX32652
+
+The default flashing behavior in this BSP for the MAX32650 and MAX32652 is to
+utilize JLink.  This can be done by running the `flash` or `flash-jlink` rule
+for Makefiles, or the `<target>-jlink` target for CMake.
+
+Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP
+compatible debug probe. However, at the time of writing, the necessary flashing
+algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
+branch.  To utilize the provided debug probes, please install the bundled MSDK
+package which includes the appropriate OpenOCD modifications.   To leverage this
+OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake
+target.
+
+### MAX32651
+
+The MAX32651 features an integrated secure bootloader which requires the
+application image be signed prior to flashing.  Both the Makefile and CMake
+scripts account for this signing automatically when building for the
+MAX32651EVKIT.
+
+To flash the signed image, the MSDK's OpenOCD variant must be used.  To flash
+the MAX32651EVKIT please install the bundled MSDK, and utilize the `flash-msdk`
+and `<target>-msdk` rule and target.
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.cmake b/hw/bsp/max32650/boards/max32650evkit/board.cmake
new file mode 100644
index 000000000..fffdcc9fb
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650evkit/board.cmake
@@ -0,0 +1,10 @@
+# Use the standard, non-secure linker file
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld)
+
+function(update_board_extras TARGET)
+  #No extra arguments
+endfunction()
+
+function(prepare_image TARGET_IN)
+  #No signing required
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.h b/hw/bsp/max32650/boards/max32650evkit/board.h
new file mode 100644
index 000000000..65ed2659e
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650evkit/board.h
@@ -0,0 +1,61 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: MAX32650 EVKIT
+   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html#eb-overview
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT        MXC_GPIO2
+#define LED_PIN         MXC_GPIO_PIN_25
+#define LED_VDDIO       MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON    0
+
+// Button
+#define BUTTON_PORT         MXC_GPIO2
+#define BUTTON_PIN          MXC_GPIO_PIN_28
+#define BUTTON_PULL         MXC_GPIO_PAD_WEAK_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM    0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.mk b/hw/bsp/max32650/boards/max32650evkit/board.mk
new file mode 100644
index 000000000..0bc210e11
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650evkit/board.mk
@@ -0,0 +1,2 @@
+# Use the standard, non-secure linker file
+LD_FILE = $(BOARD_PATH)/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32650evkit/max32650.ld b/hw/bsp/max32650/boards/max32650evkit/max32650.ld
new file mode 100644
index 000000000..0e56a91ec
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650evkit/max32650.ld
@@ -0,0 +1,119 @@
+MEMORY {
+    ROM (rx)   : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */
+    FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */
+}
+
+SECTIONS {
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)    /* program code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+         /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(vtable)
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
+        *(.flashprog*)      /* Flash program */
+
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialized global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        PROVIDE ( end = . );
+        PROVIDE ( _end = . );
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.cmake b/hw/bsp/max32650/boards/max32650fthr/board.cmake
new file mode 100644
index 000000000..fffdcc9fb
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650fthr/board.cmake
@@ -0,0 +1,10 @@
+# Use the standard, non-secure linker file
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld)
+
+function(update_board_extras TARGET)
+  #No extra arguments
+endfunction()
+
+function(prepare_image TARGET_IN)
+  #No signing required
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.h b/hw/bsp/max32650/boards/max32650fthr/board.h
new file mode 100644
index 000000000..755fa15b5
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650fthr/board.h
@@ -0,0 +1,62 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: MAX32650 Feather
+   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT        MXC_GPIO1
+#define LED_PIN         MXC_GPIO_PIN_14
+#define LED_VDDIO       MXC_GPIO_VSSEL_VDDIO
+#define LED_STATE_ON    0
+
+// Button
+#define BUTTON_PORT         MXC_GPIO1
+#define BUTTON_PIN          MXC_GPIO_PIN_19
+#define BUTTON_PULL         MXC_GPIO_PAD_WEAK_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for SWD UART Pins. Pin Mux handled by the HAL
+#define UART_NUM    0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.mk b/hw/bsp/max32650/boards/max32650fthr/board.mk
new file mode 100644
index 000000000..0bc210e11
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650fthr/board.mk
@@ -0,0 +1,2 @@
+# Use the standard, non-secure linker file
+LD_FILE = $(BOARD_PATH)/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32650fthr/max32650.ld b/hw/bsp/max32650/boards/max32650fthr/max32650.ld
new file mode 100644
index 000000000..0e56a91ec
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650fthr/max32650.ld
@@ -0,0 +1,119 @@
+MEMORY {
+    ROM (rx)   : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */
+    FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */
+}
+
+SECTIONS {
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)    /* program code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+         /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(vtable)
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
+        *(.flashprog*)      /* Flash program */
+
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialized global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        PROVIDE ( end = . );
+        PROVIDE ( _end = . );
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.cmake b/hw/bsp/max32650/boards/max32651evkit/board.cmake
new file mode 100644
index 000000000..bd8077a42
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32651evkit/board.cmake
@@ -0,0 +1,30 @@
+# Use the secure linker file
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32651.ld)
+
+function(update_board_extras TARGET)
+  # for the signed target, need to add the __SLA_FWK__ define
+  target_compile_definitions(${TARGET} PUBLIC
+    __SLA_FWK__
+    )
+endfunction()
+
+function(prepare_image TARGET_IN)
+  #For the signed target, set up a POST_BUILD command to sign the elf file once
+  #created
+  if((WIN32) OR (MINGW) OR (MSYS))
+    set(SIGN_EXE "sign_app.exe")
+  else()
+    set(SIGN_EXE "sign_app")
+  endif()
+  set(MCU_PATH "${TOP}/hw/mcu/analog/max32/")
+
+  # Custom POST_BUILD command
+  add_custom_command(
+    TARGET ${TARGET_IN} POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} $<TARGET_FILE:${TARGET_IN}>  -R .sig -O binary $<TARGET_FILE_DIR:${TARGET_IN}>/${TARGET_IN}.bin
+    COMMAND ${MCU_PATH}/Tools/SBT/bin/${SIGN_EXE} -c MAX32651 key_file=${MCU_PATH}/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key
+            ca=$<TARGET_FILE_DIR:${TARGET_IN}>/${TARGET_IN}.bin sca=$<TARGET_FILE_DIR:${TARGET_IN}>/${TARGET_IN}.sbin
+    COMMAND ${CMAKE_OBJCOPY} $<TARGET_FILE:${TARGET_IN}> --update-section .sig=$<TARGET_FILE_DIR:${TARGET_IN}>/${TARGET_IN}.sig
+    VERBATIM
+    )
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.h b/hw/bsp/max32650/boards/max32651evkit/board.h
new file mode 100644
index 000000000..0b49ff309
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32651evkit/board.h
@@ -0,0 +1,61 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: MAX32651 EVKIT
+   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT        MXC_GPIO2
+#define LED_PIN         MXC_GPIO_PIN_25
+#define LED_VDDIO       MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON    0
+
+// Button
+#define BUTTON_PORT         MXC_GPIO2
+#define BUTTON_PIN          MXC_GPIO_PIN_28
+#define BUTTON_PULL         MXC_GPIO_PAD_WEAK_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM    0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.mk b/hw/bsp/max32650/boards/max32651evkit/board.mk
new file mode 100644
index 000000000..b609598c1
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32651evkit/board.mk
@@ -0,0 +1,5 @@
+# Use the secure linker file
+LD_FILE = $(BOARD_PATH)/max32651.ld
+
+# Let the family script know the build needs to be signed
+SIGNED_BUILD := 1
diff --git a/hw/bsp/max32650/boards/max32651evkit/max32651.ld b/hw/bsp/max32650/boards/max32651evkit/max32651.ld
new file mode 100644
index 000000000..3921d10f2
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32651evkit/max32651.ld
@@ -0,0 +1,132 @@
+MEMORY {
+    HEADER (rx): ORIGIN = 0x10000000, LENGTH = 0x200
+    FLASH (rx) : ORIGIN = 0x10000200, LENGTH = 0x002FFE00 /* 3MB flash */
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */
+}
+
+/* Added Oct 9, 2018 to go to correct reset vector. */
+ENTRY(Reset_Handler)
+PROVIDE( _start_SWAP = (((Reset_Handler) >> 24) | (((Reset_Handler) & 0x00FF0000) >> 8) | (((Reset_Handler) & 0x0000FF00) << 8) | ((Reset_Handler) << 24)));
+PROVIDE_HIDDEN( _SLA_Size = _endimage - __end_header );
+PROVIDE( _SLA_Size_SWAP = (((_SLA_Size) >> 24) | (((_SLA_Size) & 0x00FF0000) >> 8) | (((_SLA_Size) & 0x0000FF00) << 8) | ((_SLA_Size) << 24)));
+
+/* Sections Definitions */
+SECTIONS {
+     .sb_sla_header : ALIGN(4)
+    {
+       FILL(0xFF)
+        KEEP(*(.sb_sla_header)) /* Header for ROM code */
+         __end_header = . ;
+        . = ALIGN(512);
+    } > HEADER
+
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)    /* program code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
+        *(.flashprog*)      /* Flash program */
+
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+    _enddata = LOADADDR(.data)+SIZEOF(.data);
+
+    .sb_sla_trailer : AT(_enddata)
+    {
+        KEEP(*(.sb_sla_trailer))
+        /* Align image with 16 byte boundary to conform to flash encryption block size. */
+        FILL(0xDEADC0DE);
+        /* NOTE: The FILL and ALIGN will not work unless something is written to the section.  So, we use LONG. */
+        LONG(0xDEADC0DE);
+        . = ALIGN(16);
+    }  > FLASH
+    _endimage = LOADADDR(.sb_sla_trailer)+SIZEOF(.sb_sla_trailer);
+    .sig :
+    {
+        KEEP(*(.sig))
+        LONG(0xDEADBEEF);
+
+    }  > FLASH
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialized global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        PROVIDE ( end = . );
+        PROVIDE ( _end = . );
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c
new file mode 100644
index 000000000..8f0e56734
--- /dev/null
+++ b/hw/bsp/max32650/family.c
@@ -0,0 +1,177 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: Analog Devices
+*/
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
+#endif
+
+#include "gpio.h"
+#include "mxc_sys.h"
+#include "mxc_device.h"
+#include "uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "board.h"
+#include "bsp/board_api.h"
+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
+
+void board_init(void) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+  mxc_gpio_cfg_t gpioConfig;
+
+  // LED
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_OUT;
+  gpioConfig.mask = LED_PIN;
+  gpioConfig.pad = MXC_GPIO_PAD_NONE;
+  gpioConfig.port = LED_PORT;
+  gpioConfig.vssel = LED_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+  board_led_write(false);
+
+  // Button
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_IN;
+  gpioConfig.mask = BUTTON_PIN;
+  gpioConfig.pad = BUTTON_PULL;
+  gpioConfig.port = BUTTON_PORT;
+  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+
+  // UART
+  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE);
+
+  //USB
+  // Startup the HIRC96M clock if it's not on already
+  if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) {
+      MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN;
+      MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY);
+  }
+
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+  MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#if LED_STATE_ON
+  state = !state;
+#endif
+  if (state) {
+    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
+  } else {
+    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
+  }
+}
+
+uint32_t board_button_read(void) {
+  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
+  return BUTTON_STATE_ACTIVE == state;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  uint8_t hw_id[13];//USN Buffer
+  MXC_SYS_GetUSN(hw_id, 13);
+
+  size_t act_len = TU_MIN(max_len, 13);
+  memcpy(id, hw_id, act_len);
+  return act_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  int uart_val;
+  int act_len = 0;
+
+  while (act_len < len) {
+    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
+      break;
+    } else {
+      *buf++ = (uint8_t) uart_val;
+      act_len++;
+    }
+  }
+  return act_len;
+}
+
+int board_uart_write(void const *buf, int len) {
+  int act_len = 0;
+  const uint8_t *ch_ptr = (const uint8_t *) buf;
+  while (act_len < len) {
+    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
+    act_len++;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake
new file mode 100644
index 000000000..b1d5dded7
--- /dev/null
+++ b/hw/bsp/max32650/family.cmake
@@ -0,0 +1,169 @@
+include_guard()
+
+set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
+set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific information and functions
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# Get the linker file
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(JLINK_DEVICE max32650)
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32650.cfg")
+
+set(FAMILY_MCUS MAX32650 CACHE INTERNAL "")
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    TARGET=MAX32650
+    TARGET_REV=0x4131
+    MXC_ASSERT_ENABLE
+    MAX32650
+    IAR_PRAGMAS=0
+    CFG_TUSB_MCU=OPT_MCU_MAX32650
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+
+    # Run any board specific updates
+    update_board_extras(${TARGET})
+endfunction()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
+  add_library(${BOARD_TARGET} STATIC
+    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/heap.c
+    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/header_MAX32650.c
+    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/system_max32650.c
+    ${PERIPH_SRC}/SYS/mxc_assert.c
+    ${PERIPH_SRC}/SYS/mxc_delay.c
+    ${PERIPH_SRC}/SYS/mxc_lock.c
+    ${PERIPH_SRC}/SYS/nvic_table.c
+    ${PERIPH_SRC}/SYS/pins_me10.c
+    ${PERIPH_SRC}/SYS/sys_me10.c
+    ${PERIPH_SRC}/TPU/tpu_me10.c
+    ${PERIPH_SRC}/TPU/tpu_reva.c
+    ${PERIPH_SRC}/FLC/flc_common.c
+    ${PERIPH_SRC}/FLC/flc_me10.c
+    ${PERIPH_SRC}/FLC/flc_reva.c
+    ${PERIPH_SRC}/GPIO/gpio_common.c
+    ${PERIPH_SRC}/GPIO/gpio_me10.c
+    ${PERIPH_SRC}/GPIO/gpio_reva.c
+    ${PERIPH_SRC}/ICC/icc_me10.c
+    ${PERIPH_SRC}/ICC/icc_reva.c
+    ${PERIPH_SRC}/ICC/icc_common.c
+    ${PERIPH_SRC}/UART/uart_common.c
+    ${PERIPH_SRC}/UART/uart_me10.c
+    ${PERIPH_SRC}/UART/uart_reva.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${MAX32_CMSIS}/Include
+    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Include
+    ${MAX32_PERIPH}/Include/MAX32650
+    ${PERIPH_SRC}/SYS
+    ${PERIPH_SRC}/GPIO
+    ${PERIPH_SRC}/TPU
+    ${PERIPH_SRC}/ICC
+    ${PERIPH_SRC}/FLC
+    ${PERIPH_SRC}/UART
+    )
+
+  target_compile_options(${BOARD_TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+  )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      -u sb_header #Needed when linking libraries to not lose the Signing header
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MAX32650)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/mentor/musb/dcd_musb.c
+    )
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    )
+
+    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    )
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  family_flash_openocd_adi(${TARGET})
+
+  # Add the optional MSDK OpenOCD flashing
+  family_flash_msdk(${TARGET})
+endfunction()
+
+function(family_flash_msdk TARGET)
+  # Prepare the image (signed) if the board requires it
+  prepare_image(${TARGET})
+
+  set(MAXIM_PATH "$ENV{MAXIM_PATH}")
+  add_custom_target(${TARGET}-msdk
+    DEPENDS ${TARGET}
+    COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts
+            -f interface/cmsis-dap.cfg -f target/max32650.cfg
+            -c "program $<TARGET_FILE:${TARGET}> verify; init; reset; exit"
+    VERBATIM
+  )
+endfunction()
diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk
new file mode 100644
index 000000000..d2fc293e4
--- /dev/null
+++ b/hw/bsp/max32650/family.mk
@@ -0,0 +1,140 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
+
+# Important locations in the hw support for MCU
+MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
+MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+
+# GCC
+SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S
+
+# --------------
+# Compiler Flags
+# --------------
+# Flags for the MAX32650/1/2 SDK
+CFLAGS +=   -DTARGET=MAX32650 \
+			-DTARGET_REV=0x4131 \
+			-DMXC_ASSERT_ENABLE \
+			-DMAX32650 \
+			-DIAR_PRAGMAS=0
+
+# Flags for TUSB features
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_MAX32650 \
+  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += 	-Wno-error=strict-prototypes \
+			-Wno-error=unused-parameter \
+			-Wno-error=cast-align \
+			-Wno-error=cast-qual \
+			-Wno-error=sign-compare
+
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+
+# Configure the flash rule. By default, use JLink.
+SIGNED_BUILD ?= 0
+DEFAULT_FLASH = flash-jlink
+
+# If the applications needs to be signed (for the MAX32651), sign it first and
+# then need to use MSDK's OpenOCD to flash it
+# Also need to include the __SLA_FWK__ define to enable the signed header into
+# memory
+ifeq ($(SIGNED_BUILD), 1)
+# Extra definitions to build for the secure part
+CFLAGS += -D__SLA_FWK__
+DEFAULT_FLASH := sign-build flash-msdk
+endif
+
+# For flash-jlink target
+JLINK_DEVICE = max32650
+
+# Configure the flash rule
+flash: $(DEFAULT_FLASH)
+
+# -----------------
+# Sources & Include
+# -----------------
+PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
+SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/heap.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/system_max32650.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/header_MAX32650.c \
+	$(PERIPH_SRC)/SYS/mxc_assert.c \
+	$(PERIPH_SRC)/SYS/mxc_delay.c \
+	$(PERIPH_SRC)/SYS/mxc_lock.c \
+	$(PERIPH_SRC)/SYS/nvic_table.c \
+	$(PERIPH_SRC)/SYS/pins_me10.c \
+	$(PERIPH_SRC)/SYS/sys_me10.c \
+	$(PERIPH_SRC)/FLC/flc_common.c \
+	$(PERIPH_SRC)/FLC/flc_me10.c \
+	$(PERIPH_SRC)/FLC/flc_reva.c \
+	$(PERIPH_SRC)/GPIO/gpio_common.c \
+	$(PERIPH_SRC)/GPIO/gpio_me10.c \
+	$(PERIPH_SRC)/GPIO/gpio_reva.c \
+	$(PERIPH_SRC)/ICC/icc_me10.c \
+	$(PERIPH_SRC)/ICC/icc_reva.c \
+	$(PERIPH_SRC)/ICC/icc_common.c \
+	$(PERIPH_SRC)/TPU/tpu_me10.c \
+	$(PERIPH_SRC)/TPU/tpu_reva.c \
+	$(PERIPH_SRC)/UART/uart_common.c \
+	$(PERIPH_SRC)/UART/uart_me10.c \
+	$(PERIPH_SRC)/UART/uart_reva.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MAX32_CMSIS)/Include \
+	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32650/Include \
+	$(TOP)/$(MAX32_PERIPH)/Include/MAX32650 \
+	$(PERIPH_SRC)/SYS \
+	$(PERIPH_SRC)/GPIO \
+	$(PERIPH_SRC)/ICC \
+	$(PERIPH_SRC)/FLC \
+	$(PERIPH_SRC)/TPU \
+	$(PERIPH_SRC)/UART
+
+
+# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the
+# MAX32651 has a secure bootloader which requires the image to be signed before
+# loading into flash. All MAX32651EVKIT's have the same key for evaluation
+# purposes, so create a special flash rule to sign the binary and flash using
+# the MSDK.
+MCU_PATH = $(TOP)/hw/mcu/analog/max32/
+# Assume no extension for sign utility
+SIGN_EXE = sign_app
+ifeq ($(OS), Windows_NT)
+# Must use .exe extension on Windows, since the binaries
+# for Linux may live in the same place.
+SIGN_EXE := sign_app.exe
+else
+UNAME = $(shell uname -s)
+ifneq ($(findstring MSYS_NT,$(UNAME)),)
+# Must also use .exe extension for MSYS2
+SIGN_EXE := sign_app.exe
+endif
+endif
+
+# Rule to sign the build.  This will in-place modify the existing .elf file
+# an populate the .sig section with the signature value
+sign-build: $(BUILD)/$(PROJECT).elf
+	$(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin
+	$(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \
+		key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \
+		ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin
+	$(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+		-f interface/cmsis-dap.cfg -f target/max32650.cfg \
+		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
diff --git a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..e5a76af85
--- /dev/null
+++ b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "mxc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/max32666/README.md b/hw/bsp/max32666/README.md
new file mode 100644
index 000000000..902d82e25
--- /dev/null
+++ b/hw/bsp/max32666/README.md
@@ -0,0 +1,32 @@
+# Analog Devices MAX32665/6
+
+This BSP is for working with the Analog Devices
+[MAX32665](https://www.analog.com/en/products/max32665.html) and
+[MAX32666](https://www.analog.com/en/products/max32666.html) microcontrollers.
+The following boards are supported:
+ * [MAX32666EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html)
+ * [MAX32666FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html)
+
+
+This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
+interfaces and hardware abstraction layers. This source code package is fetched
+as part of the get-deps script.
+
+The microcontrollers utilize the standard GNU ARM toolchain.  If this toolchain
+is not already available on your build machine, it can be installed by using the
+bundled MSDK installation.  Details on downloading and installing can be found
+in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
+
+## Flashing
+
+The default flashing behavior in this BSP is to utilize JLink.  This can be done
+by running the `flash` or `flash-jlink` rule for Makefiles, or the
+`<target>-jlink` target for CMake.
+
+Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP
+compatible debug probe. However, at the time of writing, the necessary flashing
+algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
+branch.  To utilize the provided debug probes, please install the bundled MSDK
+package which includes the appropriate OpenOCD modifications.   To leverage this
+OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake
+target.
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.cmake b/hw/bsp/max32666/boards/max32666evkit/board.cmake
new file mode 100644
index 000000000..9dc6962eb
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666evkit/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.h b/hw/bsp/max32666/boards/max32666evkit/board.h
new file mode 100644
index 000000000..54589444d
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666evkit/board.h
@@ -0,0 +1,62 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: MAX32666 EVKIT
+   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT        MXC_GPIO1
+#define LED_PIN         MXC_GPIO_PIN_14
+#define LED_VDDIO       MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON    0
+
+// Button
+#define BUTTON_PORT         MXC_GPIO1
+#define BUTTON_PIN          MXC_GPIO_PIN_6
+#define BUTTON_PULL         MXC_GPIO_PAD_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM    1
+#define UART_MAP    MAP_A
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.mk b/hw/bsp/max32666/boards/max32666evkit/board.mk
new file mode 100644
index 000000000..a813a5327
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666evkit/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.cmake b/hw/bsp/max32666/boards/max32666fthr/board.cmake
new file mode 100644
index 000000000..9dc6962eb
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666fthr/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.h b/hw/bsp/max32666/boards/max32666fthr/board.h
new file mode 100644
index 000000000..0caea5934
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666fthr/board.h
@@ -0,0 +1,62 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: MAX32666 Feather
+   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT        MXC_GPIO0
+#define LED_PIN         MXC_GPIO_PIN_29
+#define LED_VDDIO       MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON    0
+
+// Button
+#define BUTTON_PORT         MXC_GPIO1
+#define BUTTON_PIN          MXC_GPIO_PIN_10
+#define BUTTON_PULL         MXC_GPIO_PAD_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for UART on SWD. Pin Mux handled by the HAL
+#define UART_NUM    1
+#define UART_MAP    MAP_B
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.mk b/hw/bsp/max32666/boards/max32666fthr/board.mk
new file mode 100644
index 000000000..a813a5327
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666fthr/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max32666/family.c b/hw/bsp/max32666/family.c
new file mode 100644
index 000000000..05306c6c9
--- /dev/null
+++ b/hw/bsp/max32666/family.c
@@ -0,0 +1,177 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: Analog Devices
+*/
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
+#endif
+
+#include "gpio.h"
+#include "mxc_sys.h"
+#include "mcr_regs.h"
+#include "mxc_device.h"
+#include "uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "board.h"
+#include "bsp/board_api.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
+
+void board_init(void) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+  mxc_gpio_cfg_t gpioConfig;
+
+  // LED
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_OUT;
+  gpioConfig.mask = LED_PIN;
+  gpioConfig.pad = MXC_GPIO_PAD_NONE;
+  gpioConfig.port = LED_PORT;
+  gpioConfig.vssel = LED_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+  board_led_write(false);
+
+  // Button
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_IN;
+  gpioConfig.mask = BUTTON_PIN;
+  gpioConfig.pad = BUTTON_PULL;
+  gpioConfig.port = BUTTON_PORT;
+  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+
+  // UART
+  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, UART_MAP);
+
+  //USB
+  // Startup the HIRC96M clock if it's not on already
+  if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) {
+      MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN;
+  }
+
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+  MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#if LED_STATE_ON
+  state = !state;
+#endif
+  if (state) {
+    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
+  } else {
+    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
+  }
+}
+
+uint32_t board_button_read(void) {
+  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
+  return BUTTON_STATE_ACTIVE == state;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
+                                          /* All other 2nd parameter is optional checksum buffer */
+  MXC_SYS_GetUSN(hw_id, NULL);
+
+  size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
+  memcpy(id, hw_id, act_len);
+  return act_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  int uart_val;
+  int act_len = 0;
+
+  while (act_len < len) {
+    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
+      break;
+    } else {
+      *buf++ = (uint8_t) uart_val;
+      act_len++;
+    }
+  }
+  return act_len;
+}
+
+int board_uart_write(void const *buf, int len) {
+  int act_len = 0;
+  const uint8_t *ch_ptr = (const uint8_t *) buf;
+  while (act_len < len) {
+    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
+    act_len++;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake
new file mode 100644
index 000000000..49798729a
--- /dev/null
+++ b/hw/bsp/max32666/family.cmake
@@ -0,0 +1,147 @@
+include_guard()
+
+set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
+set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# Get the linker file from current location (family)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32666.ld)
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(JLINK_DEVICE max32666)
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32665.cfg")
+
+set(FAMILY_MCUS MAX32666 CACHE INTERNAL "")
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    TARGET=MAX32665
+    TARGET_REV=0x4131
+    MXC_ASSERT_ENABLE
+    MAX32665
+    IAR_PRAGMAS=0
+    CFG_TUSB_MCU=OPT_MCU_MAX32666
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+endfunction()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
+  add_library(${BOARD_TARGET} STATIC
+    ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/heap.c
+    ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/system_max32665.c
+    ${PERIPH_SRC}/SYS/mxc_assert.c
+    ${PERIPH_SRC}/SYS/mxc_delay.c
+    ${PERIPH_SRC}/SYS/mxc_lock.c
+    ${PERIPH_SRC}/SYS/nvic_table.c
+    ${PERIPH_SRC}/SYS/pins_me14.c
+    ${PERIPH_SRC}/SYS/sys_me14.c
+    ${PERIPH_SRC}/TPU/tpu_me14.c
+    ${PERIPH_SRC}/TPU/tpu_reva.c
+    ${PERIPH_SRC}/FLC/flc_common.c
+    ${PERIPH_SRC}/FLC/flc_me14.c
+    ${PERIPH_SRC}/FLC/flc_reva.c
+    ${PERIPH_SRC}/GPIO/gpio_common.c
+    ${PERIPH_SRC}/GPIO/gpio_me14.c
+    ${PERIPH_SRC}/GPIO/gpio_reva.c
+    ${PERIPH_SRC}/ICC/icc_me14.c
+    ${PERIPH_SRC}/ICC/icc_reva.c
+    ${PERIPH_SRC}/UART/uart_common.c
+    ${PERIPH_SRC}/UART/uart_me14.c
+    ${PERIPH_SRC}/UART/uart_reva.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${MAX32_CMSIS}/Include
+    ${MAX32_CMSIS}/Device/Maxim/MAX32665/Include
+    ${MAX32_PERIPH}/Include/MAX32665
+    ${PERIPH_SRC}/SYS
+    ${PERIPH_SRC}/GPIO
+    ${PERIPH_SRC}/TPU
+    ${PERIPH_SRC}/ICC
+    ${PERIPH_SRC}/FLC
+    ${PERIPH_SRC}/UART
+    )
+
+  target_compile_options(${BOARD_TARGET} PRIVATE
+  -Wno-error=strict-prototypes
+  )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MAX32666)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/mentor/musb/dcd_musb.c
+    )
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    )
+
+    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    )
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  family_flash_openocd_adi(${TARGET})
+endfunction()
diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk
new file mode 100644
index 000000000..b4f7d1e57
--- /dev/null
+++ b/hw/bsp/max32666/family.mk
@@ -0,0 +1,93 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
+
+# Important locations in the hw support for MCU
+MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
+MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+
+# GCC
+SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
+LD_FILE = $(FAMILY_PATH)/max32666.ld
+
+# --------------
+# Compiler Flags
+# --------------
+# Flags for the MAX32665/6 SDK
+CFLAGS +=   -DTARGET=MAX32665 \
+			-DTARGET_REV=0x4131 \
+			-DMXC_ASSERT_ENABLE \
+			-DMAX32665 \
+			-DIAR_PRAGMAS=0
+
+# Flags for TUSB features
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_MAX32666 \
+  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += 	-Wno-error=strict-prototypes \
+			-Wno-error=unused-parameter \
+			-Wno-error=cast-align \
+			-Wno-error=cast-qual
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+
+# For flash-jlink target
+JLINK_DEVICE = max32666
+
+# flash target using Jlink by default
+flash: flash-jlink
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+		-f interface/cmsis-dap.cfg -f target/max32665.cfg \
+		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
+
+# -----------------
+# Sources & Include
+# -----------------
+PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
+SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/heap.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/system_max32665.c \
+	$(PERIPH_SRC)/SYS/mxc_assert.c \
+	$(PERIPH_SRC)/SYS/mxc_delay.c \
+	$(PERIPH_SRC)/SYS/mxc_lock.c \
+	$(PERIPH_SRC)/SYS/nvic_table.c \
+	$(PERIPH_SRC)/SYS/pins_me14.c \
+	$(PERIPH_SRC)/SYS/sys_me14.c \
+	$(PERIPH_SRC)/FLC/flc_common.c \
+	$(PERIPH_SRC)/FLC/flc_me14.c \
+	$(PERIPH_SRC)/FLC/flc_reva.c \
+	$(PERIPH_SRC)/GPIO/gpio_common.c \
+	$(PERIPH_SRC)/GPIO/gpio_me14.c \
+	$(PERIPH_SRC)/GPIO/gpio_reva.c \
+	$(PERIPH_SRC)/ICC/icc_me14.c \
+	$(PERIPH_SRC)/ICC/icc_reva.c \
+	$(PERIPH_SRC)/TPU/tpu_me14.c \
+    $(PERIPH_SRC)/TPU/tpu_reva.c \
+	$(PERIPH_SRC)/UART/uart_common.c \
+	$(PERIPH_SRC)/UART/uart_me14.c \
+	$(PERIPH_SRC)/UART/uart_reva.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MAX32_CMSIS)/Include \
+	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32665/Include \
+	$(TOP)/$(MAX32_PERIPH)/Include/MAX32665 \
+	$(PERIPH_SRC)/SYS \
+	$(PERIPH_SRC)/GPIO \
+	$(PERIPH_SRC)/ICC \
+	$(PERIPH_SRC)/FLC \
+	$(PERIPH_SRC)/TPU \
+	$(PERIPH_SRC)/UART
diff --git a/hw/bsp/max32666/max32666.ld b/hw/bsp/max32666/max32666.ld
new file mode 100644
index 000000000..06c124247
--- /dev/null
+++ b/hw/bsp/max32666/max32666.ld
@@ -0,0 +1,135 @@
+/* SPID and SPIX Sections here are maximum possible sizes */
+/* If used, they should be adjusted for the external Flash/RAM size */
+MEMORY {
+
+    SPIX (rx)  : ORIGIN = 0x08000000,                           LENGTH = 0x08000000
+    FLASH (rx) : ORIGIN = 0x10000000,                           LENGTH = 0x00100000
+    SRAM (rwx)      : ORIGIN = 0x20000000,                      LENGTH = 0x0008C000
+    SPID (rw)       : ORIGIN = 0x80000000,                      LENGTH = 512M
+}
+
+/* Sections Definitions */
+SECTIONS {
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)    /* program code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    /* This section will keep the SPIX data until loaded into the external device */
+    /* Upon initialization of SPIX (user code needs to do this) */
+    .xip_section :
+    {
+        KEEP(*(.xip_section*))
+    } > SPIX AT>FLASH
+
+    __load_start_xip = LOADADDR(.xip_section);
+    __load_length_xip = SIZEOF(.xip_section);
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(vtable)
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
+        *(.flashprog*)      /* Flash program */
+
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialized global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Setup the stack for Core 1, it will only be used if the user code
+     * includes a definition of Stack_Size_Core1, which defines the space
+     * reserved above the main core's stack for core 1's stack */
+
+    __StackTop_Core1 = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit_Core1 = DEFINED(Stack_Size_Core1) ? __StackTop_Core1 - Stack_Size_Core1 : __StackTop_Core1;
+
+    /* Set stack top to end of RAM, and stack limit move down by Stack_Size.
+     * If core 1 is used, set the stack to the bottom of Core 1's stack region */
+
+    __StackTop = DEFINED(Stack_Size_Core1) ? __StackLimit_Core1 : ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - Stack_Size;
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        PROVIDE ( end = . );
+        PROVIDE ( _end = . );
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack(s) exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..e5a76af85
--- /dev/null
+++ b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "mxc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/max32690/README.md b/hw/bsp/max32690/README.md
new file mode 100644
index 000000000..081ae0ad4
--- /dev/null
+++ b/hw/bsp/max32690/README.md
@@ -0,0 +1,31 @@
+# Analog Devices MAX32690
+
+This BSP is for working with the Analog Devices
+[MAX32690](https://www.analog.com/en/products/max32690.html) microcontroller.
+The following boards are supported:
+ * [MAX32690EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html)
+ * [AD-APARD32690-SL](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html)
+
+
+This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
+interfaces and hardware abstraction layers. This source code package is fetched
+as part of the get-deps script.
+
+The microcontroller utilizes the standard GNU ARM toolchain.  If this toolchain
+is not already available on your build machine, it can be installed by using the
+bundled MSDK installation.  Details on downloading and installing can be found
+in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
+
+## Flashing
+
+The default flashing behavior in this BSP is to utilize JLink.  This can be done
+by running the `flash` or `flash-jlink` rule for Makefiles, or the
+`<target>-jlink` target for CMake.
+
+Both the Evaluation Kit and APARD boards are shipped with a CMSIS-DAP
+compatible debug probe. However, at the time of writing, the necessary flashing
+algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
+branch.  To utilize the provided debug probes, please install the bundled MSDK
+package which includes the appropriate OpenOCD modifications.   To leverage this
+OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake
+target.
diff --git a/hw/bsp/max32690/boards/apard32690/board.cmake b/hw/bsp/max32690/boards/apard32690/board.cmake
new file mode 100644
index 000000000..9dc6962eb
--- /dev/null
+++ b/hw/bsp/max32690/boards/apard32690/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/max32690/boards/apard32690/board.h
new file mode 100644
index 000000000..87b9c4e88
--- /dev/null
+++ b/hw/bsp/max32690/boards/apard32690/board.h
@@ -0,0 +1,61 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name:  APARD32690-SL
+   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT        MXC_GPIO2
+#define LED_PIN         MXC_GPIO_PIN_1
+#define LED_VDDIO       MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON    1
+
+// Button
+#define BUTTON_PORT         MXC_GPIO1
+#define BUTTON_PIN          MXC_GPIO_PIN_27
+#define BUTTON_PULL         MXC_GPIO_PAD_NONE
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for UART on ARM SWD Connector
+#define UART_NUM 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32690/boards/apard32690/board.mk b/hw/bsp/max32690/boards/apard32690/board.mk
new file mode 100644
index 000000000..a813a5327
--- /dev/null
+++ b/hw/bsp/max32690/boards/apard32690/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.cmake b/hw/bsp/max32690/boards/max32690evkit/board.cmake
new file mode 100644
index 000000000..9dc6962eb
--- /dev/null
+++ b/hw/bsp/max32690/boards/max32690evkit/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/max32690/boards/max32690evkit/board.h
new file mode 100644
index 000000000..aa8dbb1de
--- /dev/null
+++ b/hw/bsp/max32690/boards/max32690evkit/board.h
@@ -0,0 +1,61 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: MAX32690 EVKIT
+   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT        MXC_GPIO0
+#define LED_PIN         MXC_GPIO_PIN_14
+#define LED_VDDIO       MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON    0
+
+// Button
+#define BUTTON_PORT         MXC_GPIO4
+#define BUTTON_PIN          MXC_GPIO_PIN_0
+#define BUTTON_PULL         MXC_GPIO_PAD_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM 2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.mk b/hw/bsp/max32690/boards/max32690evkit/board.mk
new file mode 100644
index 000000000..a813a5327
--- /dev/null
+++ b/hw/bsp/max32690/boards/max32690evkit/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c
new file mode 100644
index 000000000..7ba5fbef3
--- /dev/null
+++ b/hw/bsp/max32690/family.c
@@ -0,0 +1,175 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: Analog Devices
+*/
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
+#endif
+
+#include "gpio.h"
+#include "mxc_sys.h"
+#include "mcr_regs.h"
+#include "mxc_device.h"
+#include "uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "board.h"
+#include "bsp/board_api.h"
+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
+
+void board_init(void) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+  mxc_gpio_cfg_t gpioConfig;
+
+  // LED
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_OUT;
+  gpioConfig.mask = LED_PIN;
+  gpioConfig.pad = MXC_GPIO_PAD_NONE;
+  gpioConfig.port = LED_PORT;
+  gpioConfig.vssel = LED_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+  board_led_write(false);
+
+  // Button
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_IN;
+  gpioConfig.mask = BUTTON_PIN;
+  gpioConfig.pad = BUTTON_PULL;
+  gpioConfig.port = BUTTON_PORT;
+  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+
+  // UART
+  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
+
+  //USB
+  MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO);
+  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+  MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#if LED_STATE_ON
+  state = !state;
+#endif
+  if (state) {
+    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
+  } else {
+    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
+  }
+}
+
+uint32_t board_button_read(void) {
+  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
+  return BUTTON_STATE_ACTIVE == state;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
+                                          /* All other 2nd parameter is optional checksum buffer */
+  MXC_SYS_GetUSN(hw_id, NULL);
+
+  size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
+  memcpy(id, hw_id, act_len);
+  return act_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  int uart_val;
+  int act_len = 0;
+
+  while (act_len < len) {
+    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
+      break;
+    } else {
+      *buf++ = (uint8_t) uart_val;
+      act_len++;
+    }
+  }
+  return act_len;
+}
+
+int board_uart_write(void const *buf, int len) {
+  int act_len = 0;
+  const uint8_t *ch_ptr = (const uint8_t *) buf;
+  while (act_len < len) {
+    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
+    act_len++;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake
new file mode 100644
index 000000000..0d544d9e6
--- /dev/null
+++ b/hw/bsp/max32690/family.cmake
@@ -0,0 +1,152 @@
+include_guard()
+
+set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
+set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# Get the linker file from current location (family)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld)
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(JLINK_DEVICE max32690)
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32690.cfg")
+
+set(FAMILY_MCUS MAX32690 CACHE INTERNAL "")
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    TARGET=MAX32690
+    TARGET_REV=0x4131
+    MXC_ASSERT_ENABLE
+    MAX32690
+    FLASH_ORIGIN=0x10000000
+    FLASH_SIZE=0x340000
+    SRAM_ORIGIN=0x20000000
+    SRAM_SIZE=0x100000
+    IAR_PRAGMAS=0
+    CFG_TUSB_MCU=OPT_MCU_MAX32690
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+endfunction()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
+  add_library(${BOARD_TARGET} STATIC
+    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/heap.c
+    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/system_max32690.c
+    ${PERIPH_SRC}/SYS/mxc_assert.c
+    ${PERIPH_SRC}/SYS/mxc_delay.c
+    ${PERIPH_SRC}/SYS/mxc_lock.c
+    ${PERIPH_SRC}/SYS/nvic_table.c
+    ${PERIPH_SRC}/SYS/pins_me18.c
+    ${PERIPH_SRC}/SYS/sys_me18.c
+    ${PERIPH_SRC}/CTB/ctb_me18.c
+    ${PERIPH_SRC}/CTB/ctb_reva.c
+    ${PERIPH_SRC}/CTB/ctb_common.c
+    ${PERIPH_SRC}/FLC/flc_common.c
+    ${PERIPH_SRC}/FLC/flc_me18.c
+    ${PERIPH_SRC}/FLC/flc_reva.c
+    ${PERIPH_SRC}/GPIO/gpio_common.c
+    ${PERIPH_SRC}/GPIO/gpio_me18.c
+    ${PERIPH_SRC}/GPIO/gpio_reva.c
+    ${PERIPH_SRC}/ICC/icc_me18.c
+    ${PERIPH_SRC}/ICC/icc_reva.c
+    ${PERIPH_SRC}/UART/uart_common.c
+    ${PERIPH_SRC}/UART/uart_me18.c
+    ${PERIPH_SRC}/UART/uart_revb.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${MAX32_CMSIS}/Include
+    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include
+    ${MAX32_PERIPH}/Include/MAX32690
+    ${PERIPH_SRC}/SYS
+    ${PERIPH_SRC}/GPIO
+    ${PERIPH_SRC}/CTB
+    ${PERIPH_SRC}/ICC
+    ${PERIPH_SRC}/FLC
+    ${PERIPH_SRC}/UART
+    )
+
+  target_compile_options(${BOARD_TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+  )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MAX32690)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/mentor/musb/dcd_musb.c
+    )
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    )
+
+    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    )
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  family_flash_openocd_adi(${TARGET})
+endfunction()
diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk
new file mode 100644
index 000000000..d4df8ef2f
--- /dev/null
+++ b/hw/bsp/max32690/family.mk
@@ -0,0 +1,101 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
+
+# Important locations in the hw support for MCU
+MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
+MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+
+# GCC
+SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S
+LD_FILE = $(FAMILY_PATH)/max32690.ld
+
+# --------------
+# Compiler Flags
+# --------------
+# Flags for the MAX32690 SDK
+CFLAGS +=   -DTARGET=MAX32690 \
+			-DTARGET_REV=0x4131 \
+			-DMXC_ASSERT_ENABLE \
+			-DMAX32690 \
+			-DFLASH_ORIGIN=0x10000000 \
+			-DFLASH_SIZE=0x340000 \
+			-DSRAM_ORIGIN=0x20000000 \
+			-DSRAM_SIZE=0x100000 \
+			-DIAR_PRAGMAS=0
+
+# Flags for TUSB features
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_MAX32690 \
+  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += 	-Wno-error=unused-parameter \
+			-Wno-error=strict-prototypes \
+			-Wno-error=old-style-declaration \
+			-Wno-error=sign-compare \
+			-Wno-error=cast-qual \
+			-Wno-lto-type-mismatch
+
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+
+# For flash-jlink target
+JLINK_DEVICE = max32690
+
+# flash target using Jlink by default
+flash: flash-jlink
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+		-f interface/cmsis-dap.cfg -f target/max32690.cfg \
+		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
+
+# -----------------
+# Sources & Include
+# -----------------
+PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
+SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \
+	$(PERIPH_SRC)/SYS/mxc_assert.c \
+	$(PERIPH_SRC)/SYS/mxc_delay.c \
+	$(PERIPH_SRC)/SYS/mxc_lock.c \
+	$(PERIPH_SRC)/SYS/nvic_table.c \
+	$(PERIPH_SRC)/SYS/pins_me18.c \
+	$(PERIPH_SRC)/SYS/sys_me18.c \
+	$(PERIPH_SRC)/CTB/ctb_me18.c \
+	$(PERIPH_SRC)/CTB/ctb_reva.c \
+	$(PERIPH_SRC)/CTB/ctb_common.c \
+	$(PERIPH_SRC)/FLC/flc_common.c \
+	$(PERIPH_SRC)/FLC/flc_me18.c \
+	$(PERIPH_SRC)/FLC/flc_reva.c \
+	$(PERIPH_SRC)/GPIO/gpio_common.c \
+	$(PERIPH_SRC)/GPIO/gpio_me18.c \
+	$(PERIPH_SRC)/GPIO/gpio_reva.c \
+	$(PERIPH_SRC)/ICC/icc_me18.c \
+	$(PERIPH_SRC)/ICC/icc_reva.c \
+	$(PERIPH_SRC)/UART/uart_common.c \
+	$(PERIPH_SRC)/UART/uart_me18.c \
+	$(PERIPH_SRC)/UART/uart_revb.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MAX32_CMSIS)/Include \
+	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \
+	$(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \
+	$(PERIPH_SRC)/SYS \
+	$(PERIPH_SRC)/GPIO \
+	$(PERIPH_SRC)/CTB \
+	$(PERIPH_SRC)/ICC \
+	$(PERIPH_SRC)/FLC \
+	$(PERIPH_SRC)/UART
diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/max32690/max32690.ld
new file mode 100644
index 000000000..64b906a54
--- /dev/null
+++ b/hw/bsp/max32690/max32690.ld
@@ -0,0 +1,164 @@
+MEMORY {
+    ROM        (rx) : ORIGIN = 0x00000000,    LENGTH = 0x00020000 /* 128kB ROM */
+    FLASH      (rx) : ORIGIN = 0x10000000,    LENGTH = 0x00340000
+    SRAM      (rwx) : ORIGIN = 0x20000000,    LENGTH = 0x00100000
+
+	/*
+     * Note that CS0/CS1 address mappings may be reversed using MXC_HPC->mbr0 and ->mbr1
+     * The following mappings are selected for simplicity
+     */
+    HPB_CS0 (rwx)  : ORIGIN = 0x60000000, LENGTH = 0x10000000  /* External Hyperbus/Xccelabus chip select 0 */
+    HPB_CS1 (rwx)  : ORIGIN = 0x70000000, LENGTH = 0x10000000  /* External Hyperbus/Xccelabus chip select 1 */
+}
+
+SECTIONS {
+    .rom :
+    {
+        KEEP(*(.rom_vector))
+        *(.rom_handlers*)
+    } > ROM
+
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        EXCLUDE_FILE (*riscv.o) *(.text*)    /* program code, exclude RISCV code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    /* These sections allow code to be compiled/linked for HPB addresses, but reside in
+     * flash until copied by code to the external HPB flash device
+     */
+    .hpb_cs0_section :
+    {
+	__hpb_cs0_start = ABSOLUTE(.);
+        KEEP(*(.hpb_cs0_section*))
+    } > HPB_CS0 AT>FLASH
+
+    __load_start_hpb_cs0 = LOADADDR(.hpb_cs0_section);
+    __load_length_hpb_cs0 = SIZEOF(.hpb_cs0_section);
+
+    .hpb_cs1_section :
+    {
+    	__hpb_cs1_start = ABSOLUTE(.);
+        KEEP(*(.hpb_cs1_section*))
+    } > HPB_CS1 AT>FLASH
+
+    __load_start_hpb_cs1 = LOADADDR(.hpb_cs1_section);
+    __load_length_hpb_cs1 = SIZEOF(.hpb_cs1_section);
+
+    /* Binary import */
+    .bin_storage :
+    {
+       FILL(0xFF)
+      _bin_start_ = .;
+      KEEP(*(.bin_storage_img))
+      _bin_end_ = .;
+      . = ALIGN(4);
+    } > FLASH
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(vtable)
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        /* Run the flash programming functions from SRAM */
+        *(.flashprog)
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialized global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        PROVIDE ( end = . );
+        PROVIDE ( _end = . );
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..e5a76af85
--- /dev/null
+++ b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "mxc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/max78002/README.md b/hw/bsp/max78002/README.md
new file mode 100644
index 000000000..4fb1bede4
--- /dev/null
+++ b/hw/bsp/max78002/README.md
@@ -0,0 +1,28 @@
+# Analog Devices MAX78002
+
+This BSP is for working with the Analog Devices
+[MAX78002](https://www.analog.com/en/products/max78002.html) AI microcontroller.
+The following boards are supported:
+ * [MAX78002EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html)
+
+This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
+interfaces and hardware abstraction layers. This source code package is fetched
+as part of the get-deps script.
+
+The microcontroller utilizes the standard GNU ARM toolchain.  If this toolchain
+is not already available on your build machine, it can be installed by using the
+bundled MSDK installation.  Details on downloading and installing can be found
+in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
+
+## Flashing
+
+The default flashing behavior in this BSP is to utilize JLink.  This can be done
+by running the `flash` or `flash-jlink` rule for Makefiles, or the
+`<target>-jlink` target for CMake.
+
+The Evaluation Kit is shipped with a CMSIS-DAP compatible debug probe. However,
+at the time of writing, the necessary flashing algorithms for OpenOCD have not
+yet been incorporated into the OpenOCD master branch.  To utilize the provided
+debug probes, please install the bundled MSDK package which includes the
+appropriate OpenOCD modifications.   To leverage this OpenOCD instance, run the
+`flash-msdk` Makefile rule, or `<target>-msdk` CMake target.
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.cmake b/hw/bsp/max78002/boards/max78002evkit/board.cmake
new file mode 100644
index 000000000..9dc6962eb
--- /dev/null
+++ b/hw/bsp/max78002/boards/max78002evkit/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.h b/hw/bsp/max78002/boards/max78002evkit/board.h
new file mode 100644
index 000000000..85d55d7de
--- /dev/null
+++ b/hw/bsp/max78002/boards/max78002evkit/board.h
@@ -0,0 +1,63 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: MAX78002 EVKIT
+   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT        MXC_GPIO2
+#define LED_PIN         MXC_GPIO_PIN_4
+#define LED_VDDIO       MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON    1
+
+// Button
+#define BUTTON_PORT         MXC_GPIO2
+#define BUTTON_PIN          MXC_GPIO_PIN_6
+#define BUTTON_PULL         MXC_GPIO_PAD_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM        0
+#define UART_PORT       MXC_GPIO0
+#define UART_VDDIO_BITS 0xF
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.mk b/hw/bsp/max78002/boards/max78002evkit/board.mk
new file mode 100644
index 000000000..a813a5327
--- /dev/null
+++ b/hw/bsp/max78002/boards/max78002evkit/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c
new file mode 100644
index 000000000..5c23f40f9
--- /dev/null
+++ b/hw/bsp/max78002/family.c
@@ -0,0 +1,173 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: Analog Devices
+*/
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
+#endif
+
+#include "gpio.h"
+#include "mxc_sys.h"
+#include "mcr_regs.h"
+#include "mxc_device.h"
+#include "uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "board.h"
+#include "bsp/board_api.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
+
+void board_init(void) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+  mxc_gpio_cfg_t gpioConfig;
+
+  // LED
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_OUT;
+  gpioConfig.mask = LED_PIN;
+  gpioConfig.pad = MXC_GPIO_PAD_NONE;
+  gpioConfig.port = LED_PORT;
+  gpioConfig.vssel = LED_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+  board_led_write(false);
+
+  // Button
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_IN;
+  gpioConfig.mask = BUTTON_PIN;
+  gpioConfig.pad = BUTTON_PULL;
+  gpioConfig.port = BUTTON_PORT;
+  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+
+  // UART
+  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
+  UART_PORT->vssel |= UART_VDDIO_BITS; //Set necessary bits to 3.3V
+
+  //USB
+  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#if LED_STATE_ON
+  state = !state;
+#endif
+  if (state) {
+    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
+  } else {
+    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
+  }
+}
+
+uint32_t board_button_read(void) {
+  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
+  return BUTTON_STATE_ACTIVE == state;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
+                                          /* All other 2nd parameter is optional checksum buffer */
+  MXC_SYS_GetUSN(hw_id, NULL);
+
+  size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
+  memcpy(id, hw_id, act_len);
+  return act_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  int uart_val;
+  int act_len = 0;
+
+  while (act_len < len) {
+    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
+      break;
+    } else {
+      *buf++ = (uint8_t) uart_val;
+      act_len++;
+    }
+  }
+  return act_len;
+}
+
+int board_uart_write(void const *buf, int len) {
+  int act_len = 0;
+  const uint8_t *ch_ptr = (const uint8_t *) buf;
+  while (act_len < len) {
+    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
+    act_len++;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake
new file mode 100644
index 000000000..ce0fcfa08
--- /dev/null
+++ b/hw/bsp/max78002/family.cmake
@@ -0,0 +1,166 @@
+include_guard()
+
+set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
+set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# Get the linker file from current location (family)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max78002.ld)
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(JLINK_DEVICE max78000)
+
+set(FAMILY_MCUS MAX78002 CACHE INTERNAL "")
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    TARGET=MAX78002
+    TARGET_REV=0x4131
+    MXC_ASSERT_ENABLE
+    MAX78002
+    IAR_PRAGMAS=0
+    CFG_TUSB_MCU=OPT_MCU_MAX78002
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+endfunction()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
+  add_library(${BOARD_TARGET} STATIC
+    ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/heap.c
+    ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/system_max78002.c
+    ${PERIPH_SRC}/SYS/mxc_assert.c
+    ${PERIPH_SRC}/SYS/mxc_delay.c
+    ${PERIPH_SRC}/SYS/mxc_lock.c
+    ${PERIPH_SRC}/SYS/nvic_table.c
+    ${PERIPH_SRC}/SYS/pins_ai87.c
+    ${PERIPH_SRC}/SYS/sys_ai87.c
+    ${PERIPH_SRC}/AES/aes_ai87.c
+    ${PERIPH_SRC}/AES/aes_revb.c
+    ${PERIPH_SRC}/FLC/flc_common.c
+    ${PERIPH_SRC}/FLC/flc_ai87.c
+    ${PERIPH_SRC}/FLC/flc_reva.c
+    ${PERIPH_SRC}/GPIO/gpio_common.c
+    ${PERIPH_SRC}/GPIO/gpio_ai87.c
+    ${PERIPH_SRC}/GPIO/gpio_reva.c
+    ${PERIPH_SRC}/ICC/icc_ai87.c
+    ${PERIPH_SRC}/ICC/icc_reva.c
+    ${PERIPH_SRC}/TRNG/trng_ai87.c
+    ${PERIPH_SRC}/TRNG/trng_revb.c
+    ${PERIPH_SRC}/UART/uart_common.c
+    ${PERIPH_SRC}/UART/uart_ai87.c
+    ${PERIPH_SRC}/UART/uart_revb.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${MAX32_CMSIS}/Include
+    ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include
+    ${MAX32_PERIPH}/Include/MAX78002
+    ${PERIPH_SRC}/SYS
+    ${PERIPH_SRC}/GPIO
+    ${PERIPH_SRC}/AES
+    ${PERIPH_SRC}/TRNG
+    ${PERIPH_SRC}/ICC
+    ${PERIPH_SRC}/FLC
+    ${PERIPH_SRC}/UART
+    )
+
+  target_compile_options(${BOARD_TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    -Wno-error=redundant-decls
+  )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    -Wno-error=redundant-decls
+    )
+
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MAX78002)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/mentor/musb/dcd_musb.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    -Wno-error=redundant-decls
+  )
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  family_flash_msdk(${TARGET})
+endfunction()
+
+# Add flash msdk target
+function(family_flash_msdk TARGET)
+  set(MAXIM_PATH "$ENV{MAXIM_PATH}")
+
+  add_custom_target(${TARGET}-msdk
+    DEPENDS ${TARGET}
+    COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts
+		        -f interface/cmsis-dap.cfg -f target/max78002.cfg
+		        -c "program $<TARGET_FILE:${TARGET}> verify; init; reset; exit"
+    VERBATIM
+    )
+endfunction()
diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk
new file mode 100644
index 000000000..997816261
--- /dev/null
+++ b/hw/bsp/max78002/family.mk
@@ -0,0 +1,99 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
+
+# Important locations in the hw support for MCU
+MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
+MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+
+# GCC
+SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S
+LD_FILE = $(FAMILY_PATH)/max78002.ld
+
+# --------------
+# Compiler Flags
+# --------------
+# Flags for the MAX78002 SDK
+CFLAGS +=   -DTARGET=MAX78002 \
+			-DTARGET_REV=0x4131 \
+			-DMXC_ASSERT_ENABLE \
+			-DMAX78002 \
+			-DIAR_PRAGMAS=0
+
+# Flags for TUSB features
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_MAX78002 \
+  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += 	-Wno-error=redundant-decls \
+			-Wno-error=strict-prototypes \
+			-Wno-error=unused-parameter \
+			-Wno-error=enum-conversion \
+			-Wno-error=sign-compare \
+			-Wno-error=cast-qual
+
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+
+# For flash-jlink target
+JLINK_DEVICE = max78000
+
+# flash target using Jlink by default
+flash: flash-jlink
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+		-f interface/cmsis-dap.cfg -f target/max78002.cfg \
+		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
+
+# -----------------
+# Sources & Include
+# -----------------
+PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
+SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \
+	$(PERIPH_SRC)/SYS/mxc_assert.c \
+	$(PERIPH_SRC)/SYS/mxc_delay.c \
+	$(PERIPH_SRC)/SYS/mxc_lock.c \
+	$(PERIPH_SRC)/SYS/nvic_table.c \
+	$(PERIPH_SRC)/SYS/pins_ai87.c \
+	$(PERIPH_SRC)/SYS/sys_ai87.c \
+	$(PERIPH_SRC)/AES/aes_ai87.c \
+	$(PERIPH_SRC)/AES/aes_revb.c \
+	$(PERIPH_SRC)/FLC/flc_common.c \
+	$(PERIPH_SRC)/FLC/flc_ai87.c \
+	$(PERIPH_SRC)/FLC/flc_reva.c \
+	$(PERIPH_SRC)/GPIO/gpio_common.c \
+	$(PERIPH_SRC)/GPIO/gpio_ai87.c \
+	$(PERIPH_SRC)/GPIO/gpio_reva.c \
+	$(PERIPH_SRC)/ICC/icc_ai87.c \
+	$(PERIPH_SRC)/ICC/icc_reva.c \
+	$(PERIPH_SRC)/TRNG/trng_ai87.c \
+	$(PERIPH_SRC)/TRNG/trng_revb.c \
+	$(PERIPH_SRC)/UART/uart_common.c \
+	$(PERIPH_SRC)/UART/uart_ai87.c \
+	$(PERIPH_SRC)/UART/uart_revb.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MAX32_CMSIS)/Include \
+	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \
+	$(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \
+	$(PERIPH_SRC)/SYS \
+	$(PERIPH_SRC)/GPIO \
+	$(PERIPH_SRC)/AES \
+	$(PERIPH_SRC)/ICC \
+	$(PERIPH_SRC)/FLC \
+	$(PERIPH_SRC)/TRNG \
+	$(PERIPH_SRC)/UART
diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/max78002/max78002.ld
new file mode 100644
index 000000000..e5c4866ee
--- /dev/null
+++ b/hw/bsp/max78002/max78002.ld
@@ -0,0 +1,182 @@
+MEMORY {
+    ROM (rx)   : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64 kB ROM */
+    FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00280000 /* 2.5 MB Flash */
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00060000 /* 384 kB SRAM */
+    /*CSI2 (rwx) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 4096 B CSI2 Buffer */
+}
+
+SECTIONS {
+    .rom :
+    {
+        KEEP(*(.rom_vector))
+        *(.rom_handlers*)
+    } > ROM
+
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        EXCLUDE_FILE (*riscv.o) *(.text*)    /* Program code (exclude RISCV code) */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+         /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    /* Binary import */
+    .bin_storage :
+    {
+       FILL(0xFF)
+      _bin_start_ = .;
+      KEEP(*(.bin_storage_img))
+      _bin_end_ = .;
+      . = ALIGN(4);
+    } > FLASH
+
+    .rom_code :
+    {
+        . = ALIGN(16);
+        _sran_code = .;
+        *(.rom_code_section)
+        _esran_code = .;
+    } > ROM
+
+    .flash_code :
+    {
+        . = ALIGN(16);
+        _sran_code = .;
+        *(.flash_code_section)
+        _esran_code = .;
+    } > FLASH
+
+    .sram_code :
+    {
+        . = ALIGN(16);
+        _sran_code = .;
+        *(.sram_code_section)
+        _esran_code = .;
+    } > SRAM
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        _csi = . + 0x20000;
+        *(vtable)
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialized global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    .shared :
+    {
+        . = ALIGN(4);
+        _shared = .;
+        *(.mailbox*)
+        . = ALIGN(4);
+        *(.shared*)     /*read-write zero initialized data: uninitialized global variable*/
+        _eshared = ALIGN(., 4);
+    } > SRAM
+    __shared_data = LOADADDR(.shared);
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        PROVIDE ( end = . );
+        PROVIDE ( _end = . );
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+
+    /* Section used by RISCV loader projects.  See RISCV_LOAD documentation in the build system. */
+    .riscv_flash :
+    {
+        /* Align address to mod 256 with a small offset. This is required to match the flash page size.*/
+        . = ALIGN(256); /* ALIGN operatator is used here.  Note that (. & 0x1FFFFF00) was used in the past, but a strange bug was seen on Windows where the & did not behave as expected.*/
+        . += 0x100;
+        _riscv_boot = .;
+        KEEP(*riscv.o (.text*))
+    } > FLASH
+}
diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk
deleted file mode 100644
index b0d885866..000000000
--- a/hw/bsp/mbed1768/board.mk
+++ /dev/null
@@ -1,45 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -nostdlib \
-  -DCORE_M3 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
-  -DRTC_EV_SUPPORT=0
-
-# startup.c and lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1768.ld
-
-SRC_C += \
-	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
-	$(MCU_DIR)/src/chip_17xx_40xx.c \
-	$(MCU_DIR)/src/clock_17xx_40xx.c \
-	$(MCU_DIR)/src/gpio_17xx_40xx.c \
-	$(MCU_DIR)/src/iocon_17xx_40xx.c \
-	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
-	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
-	$(MCU_DIR)/src/uart_17xx_40xx.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1768
-
-# flash using pyocd 
-flash: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t lpc1768 $<
-
diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..5bf990bab
--- /dev/null
+++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,153 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
new file mode 100644
index 000000000..7cd8991e6
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MCXA153)
+set(MCU_CORE MCXA153)
+
+set(JLINK_DEVICE MCXA153_M33)
+set(PYOCD_TARGET MCXA153)
+set(NXPLINK_DEVICE MCXA153:MCXA153)
+
+set(PORT 0)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXA153VLH
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.h b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
new file mode 100644
index 000000000..fb1290088
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
@@ -0,0 +1,69 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Freedom MCXA153
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA153
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO3
+#define LED_CLK               kCLOCK_GateGPIO3
+#define LED_PIN               12 // red
+#define LED_STATE_ON          0
+
+// ISP button (Dummy, use unused pin
+#define BUTTON_GPIO           GPIO3
+#define BUTTON_CLK            kCLOCK_GateGPIO3
+#define BUTTON_PIN            29 //sw2
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART0
+
+static inline void board_uart_init_clock(void) {
+  /* attach 12 MHz clock to LPUART0 (debug console) */
+  CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+  CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+  RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+}
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
new file mode 100644
index 000000000..af8416d8e
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
@@ -0,0 +1,14 @@
+MCU_VARIANT = MCXA153
+MCU_CORE = MCXA153
+PORT = 0
+
+CPU_CORE = cortex-m33-nodsp-nofp
+CFLAGS += \
+	-DCPU_MCXA153VLH \
+	-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
+
+JLINK_DEVICE = MCXA153
+PYOCD_TARGET = MCXA153
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
new file mode 100644
index 000000000..f16bc51f6
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v12.0
+processor: MCXA153
+package_id: MCXA153VLH
+mcu_data: ksdk2_0
+processor_version: 0.13.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_clock.h"
+#include "clock_config.h"
+#include "fsl_spc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+//uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockFRO96M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CPU_clock.outFreq, value: 12 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO12M */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO24M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 6 MHz}
+- {id: System_clock.outFreq, value: 24 MHz}
+settings:
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO24M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U);               /* !< Set AHBCLKDIV divider to value 2 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO48M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO48M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO64M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 64 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
+- {id: FRO_HF_clock.outFreq, value: 64 MHz}
+- {id: MAIN_clock.outFreq, value: 64 MHz}
+- {id: Slow_clock.outFreq, value: 16 MHz}
+- {id: System_clock.outFreq, value: 64 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 64 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO64M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(64000000U);               /*!< Enable FRO HF(64MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO96M
+called_from_default_init: true
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 96 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
+- {id: FRO_HF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 96 MHz}
+- {id: Slow_clock.outFreq, value: 24 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: CLKOUTDIV_HALT, value: Enable}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO96M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(96000000U);               /*!< Enable FRO HF(96MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h
new file mode 100644
index 000000000..aae811052
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK           24000000U  /*!< Core clock frequency: 24000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO24M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK           48000000U  /*!< Core clock frequency: 48000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK           64000000U  /*!< Core clock frequency: 64000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO64M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK           96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
new file mode 100644
index 000000000..cc8f56e63
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v14.0
+processor: MCXA153
+package_id: MCXA153VLH
+mcu_data: ksdk2_0
+processor_version: 0.14.3
+pin_labels:
+- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+    RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn);
+    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+    CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+    /* write to PORT0: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT0);
+
+    /* Write to GPIO3: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GateGPIO3);
+    /* Write to PORT3: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT3);
+    /* GPIO3 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+    /* PORT3 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+
+    const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */
+                                       kPORT_PullDisable,
+                                       /* Low internal pull resistor value is selected. */
+                                       kPORT_LowPullResistor,
+                                       /* Fast slew rate is configured */
+                                       kPORT_FastSlewRate,
+                                       /* Passive input filter is disabled */
+                                       kPORT_PassiveFilterDisable,
+                                       /* Open drain output is disabled */
+                                       kPORT_OpenDrainDisable,
+                                       /* Low drive strength is configured */
+                                       kPORT_LowDriveStrength,
+                                       /* Normal drive strength is configured */
+                                       kPORT_NormalDriveStrength,
+                                       /* Pin is configured as P3_12 */
+                                       kPORT_MuxAlt0,
+                                       /* Digital input enabled */
+                                       kPORT_InputBufferEnable,
+                                       /* Digital input is not inverted */
+                                       kPORT_InputNormal,
+                                       /* Pin Control Register fields [15:0] are not locked */
+                                       kPORT_UnlockRegister};
+    /* PORT3_12 (pin 38) is configured as P3_12 */
+      PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config);
+
+    const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_RXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_2 (pin 51) is configured as LPUART0_RXD */
+    PORT_SetPinConfig(PORT0, 2U, &port0_2_pin51_config);
+
+    const port_pin_config_t port0_3_pin52_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_TXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_3 (pin 52) is configured as LPUART0_TXD */
+    PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
+
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
new file mode 100644
index 000000000..06b6fdee9
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
new file mode 100644
index 000000000..8c3280743
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MCXN947)
+set(MCU_CORE MCXN947_cm33_core0)
+
+set(JLINK_DEVICE MCXN947_M33_0)
+set(PYOCD_TARGET MCXN947)
+set(NXPLINK_DEVICE MCXN947:MCXN947)
+
+set(PORT 1)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXN947VDF_cm33_core0
+    BOARD_TUD_RHPORT=${PORT}
+    # port 0 is fullspeed, port 1 is highspeed
+    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.h b/hw/bsp/mcx/boards/frdm_mcxn947/board.h
new file mode 100644
index 000000000..a35b6818a
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.h
@@ -0,0 +1,71 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Freedom MCXN947
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXN947
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO0
+#define LED_CLK               kCLOCK_Gpio0
+#define LED_PIN               10 // red
+#define LED_STATE_ON          0
+
+// WAKE button (Dummy, use unused pin
+#define BUTTON_GPIO           GPIO0
+#define BUTTON_CLK            kCLOCK_Gpio0
+#define BUTTON_PIN            23
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART4
+
+static inline void board_uart_init_clock(void) {
+  /* attach FRO 12M to FLEXCOMM4 */
+  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
+}
+
+//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
+//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
new file mode 100644
index 000000000..22fefd79b
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
@@ -0,0 +1,14 @@
+MCU_VARIANT = MCXN947
+MCU_CORE = MCXN947_cm33_core0
+PORT ?= 1
+
+CPU_CORE = cortex-m33
+CFLAGS += \
+	-DCPU_MCXN947VDF_cm33_core0 \
+	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
+
+JLINK_DEVICE = MCXN947_M33_0
+PYOCD_TARGET = MCXN947
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxn947/clock_config.c
new file mode 100644
index 000000000..37d2b4dfc
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/clock_config.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v10.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+board: MCX-N9XX-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "clock_config.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+// extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF144M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 144 MHz}
+- {id: MAIN_clock.outFreq, value: 144 MHz}
+- {id: Slow_clock.outFreq, value: 18 MHz}
+- {id: System_clock.outFreq, value: 72 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.FIRC.outFreq, value: 144 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF144M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 150 MHz}
+- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
+- {id: Slow_clock.outFreq, value: 37.5 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: RunPowerMode, value: OD}
+- {id: SCGMode, value: PLL0}
+- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
+- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
+- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up PLL0 */
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
+        .pllndiv = SCG_APLLNDIV_NDIV(8U),
+        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
+        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
+        .pllRate = 150000000U
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CLK_IN_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 100 MHz}
+- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
+- {id: Slow_clock.outFreq, value: 25 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: SCGMode, value: PLL1}
+- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
+- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
+- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupExtClocking(24000000U);
+    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
+
+    /*!< Set up PLL1 */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
+        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
+        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
+        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
+        .pllRate = 100000000U
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
+    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxn947/clock_config.h
new file mode 100644
index 000000000..c238a0423
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/clock_config.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
+#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
+#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF144M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.c
new file mode 100644
index 000000000..c33790ac5
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v12.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
+    invert_input: normal}
+  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
+ -  {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+  /* Enables the clock for PORT0: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port0);
+
+    /* Enables the clock for PORT1: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port1);
+
+
+    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P0 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_8 (pin A1) is configured as FC4_P0 */
+    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
+
+    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P1 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_9 (pin B1) is configured as FC4_P1 */
+    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
+
+    const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
+                                   kPORT_PullDisable,
+                                   /* Low internal pull resistor value is selected. */
+                                   kPORT_LowPullResistor,
+                                   /* Fast slew rate is configured */
+                                   kPORT_FastSlewRate,
+                                   /* Passive input filter is disabled */
+                                   kPORT_PassiveFilterDisable,
+                                   /* Open drain output is disabled */
+                                   kPORT_OpenDrainDisable,
+                                   /* Low drive strength is configured */
+                                   kPORT_LowDriveStrength,
+                                   /* Pin is configured as PIO0_23 */
+                                   kPORT_MuxAlt0,
+                                   /* Digital input enabled */
+                                   kPORT_InputBufferEnable,
+                                   /* Digital input is not inverted */
+                                   kPORT_InputNormal,
+                                   /* Pin Control Register fields [15:0] are not locked */
+                                   kPORT_UnlockRegister};
+    /* PORT0_23 (pin B7) is configured as PIO0_23 */
+    PORT_SetPinConfig(PORT0, 23U, &SW2);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.h
new file mode 100644
index 000000000..40968c275
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
new file mode 100644
index 000000000..8c3280743
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MCXN947)
+set(MCU_CORE MCXN947_cm33_core0)
+
+set(JLINK_DEVICE MCXN947_M33_0)
+set(PYOCD_TARGET MCXN947)
+set(NXPLINK_DEVICE MCXN947:MCXN947)
+
+set(PORT 1)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXN947VDF_cm33_core0
+    BOARD_TUD_RHPORT=${PORT}
+    # port 0 is fullspeed, port 1 is highspeed
+    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.h b/hw/bsp/mcx/boards/mcxn947brk/board.h
new file mode 100644
index 000000000..eef281787
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.h
@@ -0,0 +1,71 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: MCXN947 Breakout
+   url: n/a
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO3
+#define LED_CLK               kCLOCK_Gpio3
+#define LED_PIN               4 // red
+#define LED_STATE_ON          0
+
+// WAKE button (Dummy, use unused pin
+#define BUTTON_GPIO           GPIO0
+#define BUTTON_CLK            kCLOCK_Gpio0
+#define BUTTON_PIN            6
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART4
+
+static inline void board_uart_init_clock(void) {
+  /* attach FRO 12M to FLEXCOMM4 */
+  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
+}
+
+//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
+//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
new file mode 100644
index 000000000..22fefd79b
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk
@@ -0,0 +1,14 @@
+MCU_VARIANT = MCXN947
+MCU_CORE = MCXN947_cm33_core0
+PORT ?= 1
+
+CPU_CORE = cortex-m33
+CFLAGS += \
+	-DCPU_MCXN947VDF_cm33_core0 \
+	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
+
+JLINK_DEVICE = MCXN947_M33_0
+PYOCD_TARGET = MCXN947
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.c b/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
new file mode 100644
index 000000000..37d2b4dfc
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v10.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+board: MCX-N9XX-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "clock_config.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+// extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF144M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 144 MHz}
+- {id: MAIN_clock.outFreq, value: 144 MHz}
+- {id: Slow_clock.outFreq, value: 18 MHz}
+- {id: System_clock.outFreq, value: 72 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.FIRC.outFreq, value: 144 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF144M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 150 MHz}
+- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
+- {id: Slow_clock.outFreq, value: 37.5 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: RunPowerMode, value: OD}
+- {id: SCGMode, value: PLL0}
+- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
+- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
+- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up PLL0 */
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
+        .pllndiv = SCG_APLLNDIV_NDIV(8U),
+        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
+        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
+        .pllRate = 150000000U
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CLK_IN_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 100 MHz}
+- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
+- {id: Slow_clock.outFreq, value: 25 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: SCGMode, value: PLL1}
+- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
+- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
+- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupExtClocking(24000000U);
+    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
+
+    /*!< Set up PLL1 */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
+        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
+        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
+        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
+        .pllRate = 100000000U
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
+    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.h b/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
new file mode 100644
index 000000000..c238a0423
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
+#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
+#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF144M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
new file mode 100644
index 000000000..acc2f3e45
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v12.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
+    invert_input: normal}
+  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
+  - {pin_num: F14, peripheral: GPIO3, signal: 'GPIO, 4', pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, slew_rate: fast, open_drain: disable, drive_strength: low,
+    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for PORT1: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port1);
+    /* Enables the clock for PORT3: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port3);
+
+    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P0 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_8 (pin A1) is configured as FC4_P0 */
+    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
+
+    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P1 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_9 (pin B1) is configured as FC4_P1 */
+    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
+
+    const port_pin_config_t port3_4_pinF14_config = {/* Internal pull-up/down resistor is disabled */
+                                                     kPORT_PullDisable,
+                                                     /* Low internal pull resistor value is selected. */
+                                                     kPORT_LowPullResistor,
+                                                     /* Fast slew rate is configured */
+                                                     kPORT_FastSlewRate,
+                                                     /* Passive input filter is disabled */
+                                                     kPORT_PassiveFilterDisable,
+                                                     /* Open drain output is disabled */
+                                                     kPORT_OpenDrainDisable,
+                                                     /* Low drive strength is configured */
+                                                     kPORT_LowDriveStrength,
+                                                     /* Pin is configured as PIO3_4 */
+                                                     kPORT_MuxAlt0,
+                                                     /* Digital input enabled */
+                                                     kPORT_InputBufferEnable,
+                                                     /* Digital input is not inverted */
+                                                     kPORT_InputNormal,
+                                                     /* Pin Control Register fields [15:0] are not locked */
+                                                     kPORT_UnlockRegister};
+    /* PORT3_4 (pin F14) is configured as PIO3_4 */
+    PORT_SetPinConfig(PORT3, 4U, &port3_4_pinF14_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
new file mode 100644
index 000000000..40968c275
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/debug.jlinkscript b/hw/bsp/mcx/debug.jlinkscript
new file mode 100644
index 000000000..fd8bcffef
--- /dev/null
+++ b/hw/bsp/mcx/debug.jlinkscript
@@ -0,0 +1,5 @@
+int SetupTarget(void) {
+  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
+
+  return 0;
+}
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
new file mode 100644
index 000000000..2b9c60beb
--- /dev/null
+++ b/hw/bsp/mcx/family.c
@@ -0,0 +1,245 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: NXP
+*/
+
+#include "bsp/board_api.h"
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_lpuart.h"
+#include "board.h"
+
+#include "pin_mux.h"
+#include "clock_config.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_MCU == OPT_MCU_MCXN9
+void USB0_FS_IRQHandler(void) {
+  tusb_int_handler(0, true);
+}
+
+void USB1_HS_IRQHandler(void) {
+  tusb_int_handler(1, true);
+}
+
+#elif CFG_TUSB_MCU == OPT_MCU_MCXA15
+
+void USB0_IRQHandler(void) {
+  tusb_int_handler(0, true);
+}
+
+#endif
+
+
+void board_init(void) {
+  BOARD_InitPins();
+  BOARD_InitBootClocks();
+  CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  #if CFG_TUSB_MCU == OPT_MCU_MCXN9
+  NVIC_SetPriority(USB0_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #else
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
+#endif
+
+  // LED
+  CLOCK_EnableClock(LED_CLK);
+  gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0};
+  GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
+  board_led_write(0);
+
+#ifdef NEOPIXEL_PIN
+  // Neopixel
+  static uint32_t pixelData[NEOPIXEL_NUMBER];
+  IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
+
+  sctpix_init(NEOPIXEL_TYPE);
+  sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
+  sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
+  sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
+  sctpix_show();
+#endif
+
+  // Button
+#ifdef BUTTON_GPIO
+  CLOCK_EnableClock(BUTTON_CLK);
+  gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
+  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
+#endif
+
+#ifdef UART_DEV
+  // UART
+//  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
+//  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
+
+  // Enable UART when debug log is on
+  board_uart_init_clock();
+
+  lpuart_config_t uart_config;
+  LPUART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
+  LPUART_Init(UART_DEV, &uart_config, 12000000u);
+#endif
+
+  // USB VBUS
+  /* PORT0 PIN22 configured as USB0_VBUS */
+
+#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
+  // Port0 is Full Speed
+
+  #if CFG_TUSB_MCU == OPT_MCU_MCXA15
+  RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
+  #elif CFG_TUSB_MCU == OPT_MCU_MCXN9
+  CLOCK_AttachClk(kCLK_48M_to_USB0);
+  CLOCK_EnableClock(kCLOCK_Usb0Ram);
+  CLOCK_EnableClock(kCLOCK_Usb0Fs);
+  #endif
+
+  CLOCK_EnableUsbfsClock();
+#endif
+
+#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1 && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
+  // Port1 is High Speed
+
+  // Power
+  SPC0->ACTIVE_VDELAY = 0x0500;
+  /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, CORELDO is 1.0V) */
+  SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
+  SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
+                      SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
+  /* Wait until it is done */
+  while (SPC0->SC & SPC_SC_BUSY_MASK) {}
+  if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
+    SCG0->TRIM_LOCK = 0x5a5a0001U;
+    SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+    /* wait LDO ready */
+    while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK));
+  }
+  SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
+  SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
+  /* xtal = 20 ~ 30MHz */
+  SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
+  SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
+  while (1) {
+    if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
+      break;
+    }
+  }
+
+  // Clock
+  SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
+  CLOCK_EnableClock(kCLOCK_UsbHs);
+  CLOCK_EnableClock(kCLOCK_UsbHsPhy);
+  CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U);
+  CLOCK_EnableUsbhsClock();
+
+  // USB PHY
+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
+  USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
+#endif
+
+  // Enable PHY support for Low speed device + LS via FS Hub
+  USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+  // Enable all power for normal operation
+  USBPHY->PWD = 0;
+
+  // TX Timing
+  uint32_t phytx = USBPHY->TX;
+  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+  phytx |= USBPHY_TX_D_CAL(0x04) | USBPHY_TX_TXCAL45DP(0x07) | USBPHY_TX_TXCAL45DM(0x07);
+  //phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+  USBPHY->TX = phytx;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+
+#ifdef NEOPIXEL_PIN
+  if (state) {
+    sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
+    sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
+  } else {
+    sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
+    sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
+  }
+  sctpix_show();
+#endif
+}
+
+uint32_t board_button_read(void) {
+#ifdef BUTTON_GPIO
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+#endif
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+#ifdef UART_DEV
+  LPUART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
+  return len;
+#else
+  (void) buf; (void) len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+#endif
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
new file mode 100644
index 000000000..413c1b372
--- /dev/null
+++ b/hw/bsp/mcx/family.cmake
@@ -0,0 +1,131 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+if (MCU_VARIANT STREQUAL "MCXA153")
+  set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
+  set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
+elseif (MCU_VARIANT STREQUAL "MCXN947")
+  set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+  set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
+else()
+  message(FATAL_ERROR "MCU_VARIANT not supported")
+endif()
+
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  endif()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    # driver
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    )
+
+  if (${FAMILY_MCUS} STREQUAL "MCXN9")
+    target_sources(${BOARD_TARGET} PRIVATE
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
+    )
+  elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
+    target_sources(${BOARD_TARGET} PRIVATE
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_spc.c
+  )
+  endif()
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      #-nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  if (${FAMILY_MCUS} STREQUAL "MCXN9")
+    family_add_tinyusb(${TARGET} OPT_MCU_MCXN9)
+  elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
+    family_add_tinyusb(${TARGET} OPT_MCU_MCXA15)
+  endif()
+
+  target_sources(${TARGET} PUBLIC
+    # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+    ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
new file mode 100644
index 000000000..58149fb8d
--- /dev/null
+++ b/hw/bsp/mcx/family.mk
@@ -0,0 +1,58 @@
+UF2_FAMILY_ID = 0x2abc77ec
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+# Default to Highspeed PORT1
+PORT ?= 1
+
+CFLAGS += \
+  -flto \
+  -DBOARD_TUD_RHPORT=$(PORT) \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
+# All source paths should be relative to the top level.
+LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
+
+# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+ifeq ($(PORT), 1)
+  $(info "PORT1 High Speed")
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+	SRC_C += src/portable/chipidea/ci_hs/dcd_ci_hs.c
+else
+  $(info "PORT0 Full Speed")
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+  SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
+endif
+
+SRC_C += \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
+
+# fsl_lpflexcomm for MCXN9
+ifeq ($(MCU_VARIANT), MCXN947)
+	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c
+endif
+
+# fsl_spc for MCXNA15
+ifeq ($(MCU_VARIANT), MCXA153)
+	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c
+endif
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
+	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
+
+SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/hw/bsp/mm32/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mm32/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6622cf801
--- /dev/null
+++ b/hw/bsp/mm32/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,150 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "mm32_device.h"
+  extern u32 SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        0
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.cmake b/hw/bsp/mm32/boards/mm32f327x_mb39/board.cmake
new file mode 100644
index 000000000..4f3d145cf
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT mm32f327x)
+set(JLINK_DEVICE MM32F3273G9P)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    HSE_VALUE=8000000
+    )
+endfunction()
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.h b/hw/bsp/mm32/boards/mm32f327x_mb39/board.h
new file mode 100644
index 000000000..ee0800030
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.h
@@ -0,0 +1,24 @@
+/* metadata:
+   name: MM32F3273G9P MB-039
+   url: https://www.mindmotion.com.cn/support/development_tools/evaluation_boards/evboard/mm32f3273g9p/
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+// GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15); //Disable JTDI   AF to  AF15
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_Pin_15
+#define LED_STATE_ON          1
+
+//#define BUTTON_PORT           GPIOC
+//#define BUTTON_PIN            GPIO_PIN_13
+//#define BUTTON_STATE_ACTIVE   1
+
+#define UART_DEV              UART1
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF_7
+#define UART_TX_PIN           9
+#define UART_RX_PIN           10
+
+#endif
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
index b7663926f..f6d18315d 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
@@ -1,8 +1,9 @@
+MCU_VARIANT = mm32f327x
+CFLAGS += \
+	-DHSE_VALUE=8000000
+
+JLINK_DEVICE = MM32F3273G9P
+
 LD_FILE = $(BOARD_PATH)/flash.ld
-SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
 
-# For flash-jlink target
-#JLINK_DEVICE = stm32f411ve
-
-# flash target using on-board stlink
-#flash: flash-jlink
+flash: flash-jlink
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
index d96d6e43d..796ed04f6 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 MM32 SE TEAM
@@ -110,7 +110,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -121,12 +121,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -149,7 +149,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.cmake b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.cmake
new file mode 100644
index 000000000..4de25e2c4
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT mm32f327x)
+set(JLINK_DEVICE MM32F3273G8P)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    HSE_VALUE=12000000
+    )
+endfunction()
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h
new file mode 100644
index 000000000..522d494a8
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h
@@ -0,0 +1,19 @@
+/* metadata:
+   name: DshanMCU Pitaya Lite with MM32F3273G8P
+   url: https://gitee.com/weidongshan/DshanMCU-Pitaya-c
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+// GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15); //Disable JTDI   AF to  AF15
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_Pin_1
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_Pin_0
+#define BUTTON_STATE_ACTIVE   0
+
+
+#endif
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
new file mode 100644
index 000000000..dbcd314c8
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
@@ -0,0 +1,12 @@
+MCU_VARIANT = mm32f327x
+
+CFLAGS += \
+	-DHSE_VALUE=12000000
+
+LD_FILE = $(BOARD_PATH)/flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = MM32F3273G8P
+
+# flash target using on-board stlink
+#flash: flash-jlink
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
new file mode 100644
index 000000000..796ed04f6
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
@@ -0,0 +1,163 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2001FFFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/family.c
similarity index 59%
rename from hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
rename to hw/bsp/mm32/family.c
index 9793ba241..979efb6ca 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
+++ b/hw/bsp/mm32/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 MM32 SE TEAM
@@ -24,21 +24,39 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "mm32_device.h"
+/* metadata:
+   manufacturer: MindMotion
+*/
+
 #include "hal_conf.h"
-#include "tusb.h"
-#include "../board.h"
+#include "mm32_device.h"
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+#ifdef __GNUC__ // caused by extra declaration of SystemCoreClock in freeRTOSConfig.h
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
+extern u32 SystemCoreClock;
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler (void)
-{
+void OTG_FS_IRQHandler(void) {
   tud_int_handler(0);
-
 }
-void USB_DeviceClockInit (void)
-{
+
+void USB_DeviceClockInit(void) {
   /* Select USBCLK source */
   //  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
   RCC->CFGR &= ~(0x3 << 22);
@@ -47,125 +65,117 @@ void USB_DeviceClockInit (void)
   /* Enable USB clock */
   RCC->AHB2ENR |= 0x1 << 7;
 }
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
 
-extern u32 SystemCoreClock;
-const int baudrate = 115200;
-
-void board_init (void)
-{
-//   usb clock	
+void board_init(void) {
+//   usb clock
   USB_DeviceClockInit();
 
-  if ( SysTick_Config(SystemCoreClock / 1000) )
-  {
-    while ( 1 )
-      ;
-  }
+  SysTick_Config(SystemCoreClock / 1000);
   NVIC_SetPriority(SysTick_IRQn, 0x0);
 
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
+
   // LED
   GPIO_InitTypeDef GPIO_InitStruct;
-  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
   GPIO_StructInit(&GPIO_InitStruct);
-  GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15);                      //Disable JTDI   AF to  AF15
-
   GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15;
-  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
   GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
   GPIO_Init(GPIOA, &GPIO_InitStruct);
 
   board_led_write(true);
 
+  #ifdef BUTTON_PORT
+  GPIO_StructInit(&GPIO_InitStruct);
+  GPIO_InitStruct.GPIO_Pin = BUTTON_PIN;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
+  GPIO_InitStruct.GPIO_Mode = BUTTON_STATE_ACTIVE ? GPIO_Mode_IPD : GPIO_Mode_IPU;
+  GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+  #endif
+
+  #ifdef UART_DEV
   // UART
   UART_InitTypeDef UART_InitStruct;
 
-  RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE);    //enableUART1,GPIOAclock
-  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);    //
-  //UART initialset
-
-  GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
-  GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
+  RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE);  //enableUART1,GPIOAclock
+  GPIO_PinAFConfig(GPIOA, UART_TX_PIN, UART_GPIO_AF);
+  GPIO_PinAFConfig(GPIOA, UART_RX_PIN, UART_GPIO_AF);
 
   UART_StructInit(&UART_InitStruct);
-  UART_InitStruct.UART_BaudRate = baudrate;
+  UART_InitStruct.UART_BaudRate = CFG_BOARD_UART_BAUDRATE;
   UART_InitStruct.UART_WordLength = UART_WordLength_8b;
-  UART_InitStruct.UART_StopBits = UART_StopBits_1;    //one stopbit
-  UART_InitStruct.UART_Parity = UART_Parity_No;    //none odd-even  verify bit
-  UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;    //No hardware flow control
-  UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx;    // receive and sent  mode
+  UART_InitStruct.UART_StopBits = UART_StopBits_1;
+  UART_InitStruct.UART_Parity = UART_Parity_No;
+  UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
+  UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
 
-  UART_Init(UART1, &UART_InitStruct);    //initial uart 1
-  UART_Cmd(UART1, ENABLE);                    //enable uart 1
+  UART_Init(UART_DEV, &UART_InitStruct);
+  UART_Cmd(UART_DEV, ENABLE);
 
-  //UART1_TX   GPIOA.9
   GPIO_StructInit(&GPIO_InitStruct);
-  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStruct.GPIO_Pin = 1 << UART_TX_PIN;
   GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
   GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOA, &GPIO_InitStruct);
+  GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
-  //UART1_RX    GPIOA.10
-  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
+  GPIO_InitStruct.GPIO_Pin = 1 << UART_RX_PIN;
   GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(GPIOA, &GPIO_InitStruct);
-
+  GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+  #endif
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write (bool state)
-{
-  state ? (GPIO_ResetBits(GPIOA, GPIO_Pin_15)) : (GPIO_SetBits(GPIOA, GPIO_Pin_15));
+void board_led_write(bool state) {
+  GPIO_WriteBit(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read (void)
-{
+uint32_t board_button_read(void) {
+#ifdef BUTTON_PORT
+  return GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN) == BUTTON_STATE_ACTIVE;
+#else
   return 0;
+#endif
 }
 
-int board_uart_read (uint8_t *buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
 }
 
-int board_uart_write (void const *buf, int len)
-{
-  const char *buff = buf;
-  while ( len )
-  {
-    while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
-      ;    //The loop is sent until it is finished
+int board_uart_write(void const* buf, int len) {
+  #ifdef UART_DEV
+  const char* buff = buf;
+  while (len) {
+    while ((UART1->CSR & UART_IT_TXIEN) == 0);    //The loop is sent until it is finished
     UART1->TDR = (*buff & 0xFF);
     buff++;
     len--;
   }
   return len;
+  #else
+  (void) buf;
+  (void) len;
+  return 0;
+  #endif
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis (void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/mm32/family.cmake b/hw/bsp/mm32/family.cmake
new file mode 100644
index 000000000..0561a63a0
--- /dev/null
+++ b/hw/bsp/mm32/family.cmake
@@ -0,0 +1,101 @@
+include_guard()
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+string(REPLACE "mm32f" "MM32F" MCU_VARIANT_UPPER ${MCU_VARIANT})
+set(SDK_DIR ${TOP}/hw/mcu/mindmotion/mm32sdk/${MCU_VARIANT_UPPER})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS MM32F327X CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${SDK_DIR}/Source/GCC_StartAsm/startup_${MCU_VARIANT}_gcc.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${SDK_DIR}/Source/IAR_StartAsm/startup_${MCU_VARIANT}_iar.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  # set(LD_FILE_IAR )
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/Source/system_${MCU_VARIANT}.c
+    ${SDK_DIR}/HAL_Lib/Src/hal_gpio.c
+    ${SDK_DIR}/HAL_Lib/Src/hal_rcc.c
+    ${SDK_DIR}/HAL_Lib/Src/hal_uart.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${SDK_DIR}/Include
+    ${SDK_DIR}/HAL_Lib/Inc
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MM32F327X)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
index 1a9f51191..a790663ab 100644
--- a/hw/bsp/mm32/family.mk
+++ b/hw/bsp/mm32/family.mk
@@ -1,36 +1,33 @@
 UF2_FAMILY_ID = 0x0
-SDK_DIR = hw/mcu/mindmotion/mm32sdk
-DEPS_SUBMODULES += lib/CMSIS_5 $(SDK_DIR)
-
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+MCU_VARIANT_UPPER = $(subst mm32f,MM32F,${MCU_VARIANT})
+SDK_DIR = hw/mcu/mindmotion/mm32sdk/${MCU_VARIANT_UPPER}
+
+CPU_CORE ?= cortex-m3
+
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_MM32F327X 
+  -DCFG_TUSB_MCU=OPT_MCU_MM32F327X \
 
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=cast-qual
 
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  -specs=nosys.specs -specs=nano.specs \
+
 SRC_C += \
 	src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \
-	$(SDK_DIR)/mm32f327x/MM32F327x/Source/system_mm32f327x.c \
-	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c \
-	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c \
-	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c \
-	
+	$(SDK_DIR)/Source/system_${MCU_VARIANT}.c \
+	$(SDK_DIR)/HAL_Lib/Src/hal_gpio.c \
+	$(SDK_DIR)/HAL_Lib/Src/hal_rcc.c \
+	$(SDK_DIR)/HAL_Lib/Src/hal_uart.c \
+
+SRC_S += ${SDK_DIR}/Source/GCC_StartAsm/startup_${MCU_VARIANT}_gcc.s
+
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/Include \
-	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# flash target using on-board
-flash: flash-jlink
+	$(TOP)/$(SDK_DIR)/Include \
+	$(TOP)/$(SDK_DIR)/HAL_Lib/Inc
diff --git a/hw/bsp/msp430/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/msp430/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..4049fba65
--- /dev/null
+++ b/hw/bsp/msp430/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,80 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "msp430.h"
+#endif
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			1
+#define configUSE_TICK_HOOK			0
+#define configUSE_MALLOC_FAILED_HOOK           0
+#define configCPU_CLOCK_HZ			( ( unsigned long ) 7995392 ) /* Clock setup from main.c in the demo application. */
+#define configTICK_RATE_HZ			( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES		( 4 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned short ) 50 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 1700 ) )
+#define configMAX_TASK_NAME_LEN		( 8 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		1
+#define configIDLE_SHOULD_YIELD		1
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		0
+#define INCLUDE_uxTaskPriorityGet		0
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			0
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/hw/bsp/msp430/boards/msp_exp430f5529lp/board.cmake b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.cmake
new file mode 100644
index 000000000..59f591263
--- /dev/null
+++ b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.cmake
@@ -0,0 +1,9 @@
+set(MCU_VARIANT msp430f5529)
+set(LD_FILE_GNU ${SDK_DIR}/msp430f5529.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} INTERFACE
+    __MSP430F5529__
+    )
+
+endfunction()
diff --git a/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h
index ccfe321c2..8fbe5cc49 100644
--- a/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h
+++ b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: MSP430F5529 LaunchPad
+   url: https://www.ti.com/tool/MSP-EXP430F5529LP
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/msp430/boards/msp_exp430f5529lp/board.mk b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.mk
new file mode 100644
index 000000000..b45c62e83
--- /dev/null
+++ b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.mk
@@ -0,0 +1,4 @@
+CFLAGS += \
+  -D__MSP430F5529__ \
+
+LD_FILE = ${SDK_DIR}/msp430f5529.ld
diff --git a/hw/bsp/msp430/family.c b/hw/bsp/msp430/family.c
index 4b8ae393d..a45bd5f93 100644
--- a/hw/bsp/msp430/family.c
+++ b/hw/bsp/msp430/family.c
@@ -24,7 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+/* metadata:
+   manufacturer: Texas Instruments
+*/
+
+#include "bsp/board_api.h"
 #include "board.h"
 #include "msp430.h"
 
diff --git a/hw/bsp/msp430/family.cmake b/hw/bsp/msp430/family.cmake
new file mode 100644
index 000000000..ddd54b675
--- /dev/null
+++ b/hw/bsp/msp430/family.cmake
@@ -0,0 +1,82 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/ti/msp430/msp430-gcc-support-files/include)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU msp430 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/msp430_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS MSP430x5xx CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} INTERFACE)
+    target_compile_definitions(${BOARD_TARGET} INTERFACE
+      CFG_TUD_ENDPOINT0_SIZE=8
+      CFG_EXAMPLE_VIDEO_READONLY
+      CFG_EXAMPLE_MSC_READONLY
+      )
+    target_include_directories(${BOARD_TARGET} INTERFACE
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${SDK_DIR}
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} INTERFACE
+        "LINKER:--script=${LD_FILE_GNU}"
+        -L${SDK_DIR}
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} INTERFACE
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MSP430x5xx)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_msp430flasher(${TARGET})
+endfunction()
diff --git a/hw/bsp/msp430/family.mk b/hw/bsp/msp430/family.mk
index ceafa6ec1..06508ab2c 100644
--- a/hw/bsp/msp430/family.mk
+++ b/hw/bsp/msp430/family.mk
@@ -2,21 +2,21 @@ CROSS_COMPILE = msp430-elf-
 DEPS_SUBMODULES += hw/mcu/ti
 SKIP_NANOLIB = 1
 
+SDK_DIR = hw/mcu/ti/msp430/msp430-gcc-support-files/include
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 CFLAGS += \
-  -D__MSP430F5529__ \
   -DCFG_TUSB_MCU=OPT_MCU_MSP430x5xx \
 	-DCFG_EXAMPLE_MSC_READONLY \
 	-DCFG_TUD_ENDPOINT0_SIZE=8
 
-# All source paths should be relative to the top level.
-LD_FILE = hw/mcu/ti/msp430/msp430-gcc-support-files/include/msp430f5529.ld
-LDINC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include
-LDFLAGS += $(addprefix -L,$(LDINC))
+LDFLAGS += -L${TOP}/${SDK_DIR}
 
 SRC_C += src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
 
 INC += \
-	$(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include \
+	${TOP}/${SDK_DIR} \
 	$(TOP)/$(BOARD_PATH)
 
 # export for libmsp430.so to same installation
diff --git a/hw/bsp/msp432e4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/msp432e4/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..3dd5a1ee1
--- /dev/null
+++ b/hw/bsp/msp432e4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "msp.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.cmake b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.cmake
new file mode 100644
index 000000000..b2ef944a0
--- /dev/null
+++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT msp432e401y)
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __MSP432E401Y__
+    )
+endfunction()
diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
index 3130d663b..6206bb247 100644
--- a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
+++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: MSP432E401Y LaunchPad
+   url: https://www.ti.com/tool/MSP-EXP432E401Y
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.mk b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.mk
new file mode 100644
index 000000000..7354855cf
--- /dev/null
+++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.mk
@@ -0,0 +1,3 @@
+MCU_VARIANT = msp432e401y
+CFLAGS += \
+	-D__MSP432E401Y__ \
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 3d2d4085e..9a3b48b66 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -24,7 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+/* metadata:
+   manufacturer: Texas Instruments
+*/
+
+#include "bsp/board_api.h"
 #include "board.h"
 #include "msp.h"
 
@@ -34,7 +38,7 @@
 void USB0_IRQHandler(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 #if CFG_TUD_ENABLED
   tud_int_handler(0);
diff --git a/hw/bsp/msp432e4/family.cmake b/hw/bsp/msp432e4/family.cmake
new file mode 100644
index 000000000..f6939ecfe
--- /dev/null
+++ b/hw/bsp/msp432e4/family.cmake
@@ -0,0 +1,100 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/ti/msp432e4)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS MSP432E4 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/Source/${MCU_VARIANT}.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/Source/startup_${MCU_VARIANT}_gcc.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/Source/system_${MCU_VARIANT}.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/Include
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -mslow-flash-data
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MSP432E4)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/mentor/musb/dcd_musb.c
+    ${TOP}/src/portable/mentor/musb/hcd_musb.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_msp430flasher(${TARGET})
+endfunction()
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index e3cb90abc..d837f9351 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -1,41 +1,31 @@
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/ti
+SDK_SIR = hw/mcu/ti/msp432e4
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
 	-flto \
-	-mthumb \
 	-mslow-flash-data \
-	-mabi=aapcs \
-	-mcpu=cortex-m4 \
-	-mfloat-abi=hard \
-	-mfpu=fpv4-sp-d16 \
-	-D__MSP432E401Y__ \
 	-DCFG_TUSB_MCU=OPT_MCU_MSP432E4
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=cast-qual -Wno-error=format=
 
-# All source paths should be relative to the top level.
-LD_FILE = hw/mcu/ti/msp432e4/Source/msp432e401y.ld
-LDINC += $(TOP)/hw/mcu/ti/msp432e4/Include
-LDFLAGS += $(addprefix -L,$(LDINC))
+LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 
-MCU_DIR = hw/mcu/ti/msp432e4
+LD_FILE = hw/mcu/ti/msp432e4/Source/${MCU_VARIANT}.ld
 
 SRC_C += \
 	src/portable/mentor/musb/dcd_musb.c \
 	src/portable/mentor/musb/hcd_musb.c \
-	$(MCU_DIR)/Source/system_msp432e401y.c
+	$(SDK_SIR)/Source/system_${MCU_VARIANT}.c
 
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(MCU_DIR)/Include \
+	$(TOP)/$(SDK_SIR)/Include \
 	$(TOP)/$(BOARD_PATH)
 
-SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+SRC_S += $(SDK_SIR)/Source/startup_${MCU_VARIANT}_gcc.S
 
 # For flash-jlink target
-JLINK_DEVICE = MSP432E401Y
-JLINK_IF     = SWD
+JLINK_DEVICE = $(MCU_VARIANT)
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
deleted file mode 100644
index 3e901567c..000000000
--- a/hw/bsp/ngx4330/board.mk
+++ /dev/null
@@ -1,47 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib \
-  -DCORE_M4 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/ngx4330.ld
-
-SRC_C += \
-	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
-	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
-	src/portable/ehci/ehci.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
-	$(MCU_DIR)/src/chip_18xx_43xx.c \
-	$(MCU_DIR)/src/clock_18xx_43xx.c \
-	$(MCU_DIR)/src/gpio_18xx_43xx.c \
-	$(MCU_DIR)/src/sysinit_18xx_43xx.c \
-	$(MCU_DIR)/src/uart_18xx_43xx.c \
-	$(MCU_DIR)/src/fpu_init.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc \
-	$(TOP)/$(MCU_DIR)/inc/config_43xx
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4330
-JLINK_IF = swd 
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/ngx4330/ngx4330.c b/hw/bsp/ngx4330/ngx4330.c
deleted file mode 100644
index 4fc314165..000000000
--- a/hw/bsp/ngx4330/ngx4330.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-#define LED_PORT              1
-#define LED_PIN               12
-#define LED_STATE_ON          0
-
-#define BUTTON_PORT           0
-#define BUTTON_PIN            7
-#define BUTTON_STATE_ACTIVE   0
-
-#define BOARD_UART_PORT           LPC_USART0
-#define BOARD_UART_PIN_PORT       0x0f
-#define BOARD_UART_PIN_TX         10 // PF.10 : UART0_TXD
-#define BOARD_UART_PIN_RX         11 // PF.11 : UART0_RXD
-
-#ifdef BOARD_TUD_RHPORT
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
-#endif
-
-/*------------------------------------------------------------------*/
-/* BOARD API
- *------------------------------------------------------------------*/
-
-/* System configuration variables used by chip driver */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  // LED P2.12 as GPIO 1.12
-  {2, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
-
-  // Button P2.7 as GPIO 0.7
-  {2, 7,  (SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
-
-  // USB
-  {2, 6, (SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)}, // USB1_PWR_EN
-  {2, 5, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)}, // USB1_VBUS
-  {1, 7, (SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)}, // USB0_PWRN_EN
-
-  // SPIFI
-	{3, 3,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI CLK */
-	{3, 4,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI D3 */
-	{3, 5,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI D2 */
-	{3, 6,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI D1 */
-	{3, 7,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI D0 */
-	{3, 8,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}	/* SPIFI CS/SSEL */
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
-
-#if __FPU_USED == 1
-	fpuInit();
-#endif
-#endif // __USE_LPCOPEN
-
-	// Set up pinmux
-	Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-
-	//------------- Set up clock -------------//
-	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IRC, true, false);	// change SPIFI to IRC during clock programming
-	LPC_SPIFI->CTRL |= SPIFI_CTRL_FBCLK(1);								            // and set FBCLK in SPIFI controller
-
-	Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
-
-	/* Reset and enable 32Khz oscillator */
-	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
-	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
-	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
-	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
-	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-
-	/* Setup system base clocks and initial states. This won't enable and
-	   disable individual clocks, but sets up the base clock sources for
-	   each individual peripheral clock. */
-	Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO_PORT);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-
-#if 0
-  //------------- UART -------------//
-  scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_TX, MD_PDN, FUNC1);
-  scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_RX, MD_PLN | MD_EZI | MD_ZI, FUNC1);
-
-  UART_CFG_Type UARTConfigStruct;
-  UART_ConfigStructInit(&UARTConfigStruct);
-  UARTConfigStruct.Baud_rate   = CFG_BOARD_UART_BAUDRATE;
-  UARTConfigStruct.Clock_Speed = 0;
-
-  UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
-  UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
-#endif
-
-  //------------- USB -------------//
-  enum {
-    USBMODE_DEVICE = 2,
-    USBMODE_HOST   = 3
-  };
-
-  enum {
-    USBMODE_VBUS_LOW  = 0,
-    USBMODE_VBUS_HIGH = 1
-  };
-
-  /* USB0
-   * For USB Device operation; insert jumpers in position 1-2 in JP17/JP18/JP19. GPIO28 controls USB
-   * connect functionality and LED32 lights when the USB Device is connected. SJ4 has pads 1-2 shorted
-   * by default. LED33 is controlled by GPIO27 and signals USB-up state. GPIO54 is used for VBUS
-   * sensing.
-   * For USB Host operation; insert jumpers in position 2-3 in JP17/JP18/JP19. USB Host power is
-   * controlled via distribution switch U20 (found in schematic page 11). Signal GPIO26 is active low and
-   * enables +5V on VBUS2. LED35 light whenever +5V is present on VBUS2. GPIO55 is connected to
-   * status feedback from the distribution switch. GPIO54 is used for VBUS sensing. 15Kohm pull-down
-   * resistors are always active
-   */
-  Chip_USB0_Init();
-
-  /* USB1
-   * When USB channel #1 is used as USB Host, 15Kohm pull-down resistors are needed on the USB data
-   * signals. These are activated inside the USB OTG chip (U31), and this has to be done via the I2C
-   * interface of GPIO52/GPIO53.
-   * J20 is the connector to use when USB Host is used. In order to provide +5V to the external USB
-   * device connected to this connector (J20), channel A of U20 must be enabled. It is enabled by default
-   * since SJ5 is normally connected between pin 1-2. LED34 lights green when +5V is available on J20.
-   * JP15 shall not be inserted. JP16 has no effect
-   *
-   * When USB channel #1 is used as USB Device, a 1.5Kohm pull-up resistor is needed on the USB DP
-   * data signal. There are two methods to create this. JP15 is inserted and the pull-up resistor is always
-   * enabled. Alternatively, the pull-up resistor is activated inside the USB OTG chip (U31), and this has to
-   * be done via the I2C interface of GPIO52/GPIO53. In the latter case, JP15 shall not be inserted.
-   * J19 is the connector to use when USB Device is used. Normally it should be a USB-B connector for
-   * creating a USB Device interface, but the mini-AB connector can also be used in this case. The status
-   * of VBUS can be read via U31.
-   * JP16 shall not be inserted.
-   */
-  Chip_USB1_Init();
-//	Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 6);							/* GPIO5[6] = USB1_PWR_EN */
-//	Chip_GPIO_SetPinState(LPC_GPIO_PORT, 5, 6, true);							/* GPIO5[6] output high */
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(0)
-    tud_int_handler(0);
-  #endif
-
-  #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
-  #endif
-}
-
-void USB1_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(1)
-    tud_int_handler(1);
-  #endif
-
-  #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  //return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  //UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/ngx4330/ngx4330.ld b/hw/bsp/ngx4330/ngx4330.ld
deleted file mode 100644
index 7bd363f08..000000000
--- a/hw/bsp/ngx4330/ngx4330.ld
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * Copyright (c) 2008-2013 Code Red Technologies Ltd,
- * Copyright 2015, 2018-2019 NXP
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC4330
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Sep 9, 2019 12:09:49 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */  
-  RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
-  SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes (alias Flash) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_RamLoc128 = 0x10000000  ; /* RamLoc128 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc128 = 0x10000000 + 0x20000 ; /* 128K bytes */  
-  __top_RAM = 0x10000000 + 0x20000 ; /* 128K bytes */  
-  __base_RamLoc72 = 0x10080000  ; /* RamLoc72 */  
-  __base_RAM2 = 0x10080000 ; /* RAM2 */  
-  __top_RamLoc72 = 0x10080000 + 0x12000 ; /* 72K bytes */  
-  __top_RAM2 = 0x10080000 + 0x12000 ; /* 72K bytes */  
-  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-  __base_RAM3 = 0x20000000 ; /* RAM3 */  
-  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-  __base_RAM4 = 0x20008000 ; /* RAM4 */  
-  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-  __base_RAM5 = 0x2000c000 ; /* RAM5 */  
-  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-  __base_SPIFI = 0x14000000  ; /* SPIFI */  
-  __base_Flash = 0x14000000 ; /* Flash */  
-  __top_SPIFI = 0x14000000 + 0x400000 ; /* 4M bytes */  
-  __top_Flash = 0x14000000 + 0x400000 ; /* 4M bytes */  
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-     /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        LONG(LOADADDR(.data_RAM3));
-        LONG(    ADDR(.data_RAM3));
-        LONG(  SIZEOF(.data_RAM3));
-        LONG(LOADADDR(.data_RAM4));
-        LONG(    ADDR(.data_RAM4));
-        LONG(  SIZEOF(.data_RAM4));
-        LONG(LOADADDR(.data_RAM5));
-        LONG(    ADDR(.data_RAM5));
-        LONG(  SIZEOF(.data_RAM5));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        LONG(    ADDR(.bss_RAM3));
-        LONG(  SIZEOF(.bss_RAM3));
-        LONG(    ADDR(.bss_RAM4));
-        LONG(  SIZEOF(.bss_RAM4));
-        LONG(    ADDR(.bss_RAM5));
-        LONG(  SIZEOF(.bss_RAM5));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > SPIFI
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > SPIFI
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > SPIFI
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > SPIFI
-    __exidx_end = .;
- 
-    _etext = .;
-        
-    /* DATA section for RamLoc72 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamLoc72)
-        *(.data.$RAM2)
-        *(.data.$RamLoc72)
-        *(.data.$RAM2.*)
-        *(.data.$RamLoc72.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamLoc72 AT>SPIFI
-    /* DATA section for RamAHB32 */
-
-    .data_RAM3 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM3 = .) ;
-        *(.ramfunc.$RAM3)
-        *(.ramfunc.$RamAHB32)
-        *(.data.$RAM3)
-        *(.data.$RamAHB32)
-        *(.data.$RAM3.*)
-        *(.data.$RamAHB32.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM3 = .) ;
-     } > RamAHB32 AT>SPIFI
-    /* DATA section for RamAHB16 */
-
-    .data_RAM4 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM4 = .) ;
-        *(.ramfunc.$RAM4)
-        *(.ramfunc.$RamAHB16)
-        *(.data.$RAM4)
-        *(.data.$RamAHB16)
-        *(.data.$RAM4.*)
-        *(.data.$RamAHB16.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM4 = .) ;
-     } > RamAHB16 AT>SPIFI
-    /* DATA section for RamAHB_ETB16 */
-
-    .data_RAM5 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM5 = .) ;
-        *(.ramfunc.$RAM5)
-        *(.ramfunc.$RamAHB_ETB16)
-        *(.data.$RAM5)
-        *(.data.$RamAHB_ETB16)
-        *(.data.$RAM5.*)
-        *(.data.$RamAHB_ETB16.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM5 = .) ;
-     } > RamAHB_ETB16 AT>SPIFI
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED (NOLOAD) :
-    {
-        . = ALIGN(4) ;
-        KEEP(*(.bss.$RESERVED*))
-       . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc128
-
-    /* Main DATA section (RamLoc128) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc128 AT>SPIFI
-
-    /* BSS section for RamLoc72 */
-    .bss_RAM2 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2)
-       *(.bss.$RamLoc72)
-       *(.bss.$RAM2.*)
-       *(.bss.$RamLoc72.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamLoc72
-
-    /* BSS section for RamAHB32 */
-    .bss_RAM3 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM3 = .) ;
-       *(.bss.$RAM3)
-       *(.bss.$RamAHB32)
-       *(.bss.$RAM3.*)
-       *(.bss.$RamAHB32.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamAHB32
-
-    /* BSS section for RamAHB16 */
-    .bss_RAM4 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM4 = .) ;
-       *(.bss.$RAM4)
-       *(.bss.$RamAHB16)
-       *(.bss.$RAM4.*)
-       *(.bss.$RamAHB16.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM4 = .) ;
-    } > RamAHB16
-
-    /* BSS section for RamAHB_ETB16 */
-    .bss_RAM5 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM5 = .) ;
-       *(.bss.$RAM5)
-       *(.bss.$RamAHB_ETB16)
-       *(.bss.$RAM5.*)
-       *(.bss.$RamAHB_ETB16.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM5 = .) ;
-    } > RamAHB_ETB16
-
-    /* MAIN BSS SECTION */
-    .bss :
-    {
-        . = ALIGN(4) ;
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc128
-
-    /* NOINIT section for RamLoc72 */
-    .noinit_RAM2 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM2)
-       *(.noinit.$RamLoc72)
-       *(.noinit.$RAM2.*)
-       *(.noinit.$RamLoc72.*)
-       . = ALIGN(4) ;
-    } > RamLoc72
-
-    /* NOINIT section for RamAHB32 */
-    .noinit_RAM3 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM3)
-       *(.noinit.$RamAHB32)
-       *(.noinit.$RAM3.*)
-       *(.noinit.$RamAHB32.*)
-       . = ALIGN(4) ;
-    } > RamAHB32
-
-    /* NOINIT section for RamAHB16 */
-    .noinit_RAM4 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM4)
-       *(.noinit.$RamAHB16)
-       *(.noinit.$RAM4.*)
-       *(.noinit.$RamAHB16.*)
-       . = ALIGN(4) ;
-    } > RamAHB16
-
-    /* NOINIT section for RamAHB_ETB16 */
-    .noinit_RAM5 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM5)
-       *(.noinit.$RamAHB_ETB16)
-       *(.noinit.$RAM5.*)
-       *(.noinit.$RamAHB_ETB16.*)
-       . = ALIGN(4) ;
-    } > RamAHB_ETB16
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD):
-    {
-         . = ALIGN(4) ;
-        _noinit = .;
-        *(.noinit*)
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc128
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc128 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..0ddd536fb
--- /dev/null
+++ b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "nrf.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.cmake b/hw/bsp/nrf/boards/adafruit_clue/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/adafruit_clue/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.h b/hw/bsp/nrf/boards/adafruit_clue/board.h
index 2c58e8fe8..a5d90f608 100644
--- a/hw/bsp/nrf/boards/adafruit_clue/board.h
+++ b/hw/bsp/nrf/boards/adafruit_clue/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit CLUE
+   url: https://www.adafruit.com/product/4500
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.mk b/hw/bsp/nrf/boards/adafruit_clue/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/adafruit_clue/board.mk
+++ b/hw/bsp/nrf/boards/adafruit_clue/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld
deleted file mode 100755
index 5314a4e93..000000000
--- a/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
index f570740b6..9288a0c5e 100755
--- a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
@@ -1,7 +1,7 @@
 /* Linker script to configure memory regions. */
 
 SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
+/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/
 
 MEMORY
 {
@@ -20,7 +20,7 @@ SECTIONS
     KEEP(*(.svc_data))
     PROVIDE(__stop_svc_data = .);
   } > RAM
-  
+
   .fs_data :
   {
     PROVIDE(__start_fs_data = .);
@@ -29,4 +29,4 @@ SECTIONS
   } > RAM
 } INSERT AFTER .data;
 
-INCLUDE "nrf52_common.ld"
+INCLUDE "nrf_common.ld"
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
new file mode 100644
index 000000000..93647063a
--- /dev/null
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/arduino_nano33_ble.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
index d548e01c3..6e6a079ab 100644
--- a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Arduino Nano 33 BLE
+   url: https://store.arduino.cc/arduino-nano-33-ble
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
index a86c9dc7f..4cdac5f9f 100644
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit Circuit Playground Bluefruit
+   url: https://www.adafruit.com/product/4333
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
new file mode 100644
index 000000000..a0282aa23
--- /dev/null
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+# enable max3421 host driver for this board
+# set(MAX3421_HOST 1)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index 3208a948a..bfbb98677 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit Feather nRF52840 Express
+   url: https://www.adafruit.com/product/4062
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -45,6 +50,13 @@
 #define UART_RX_PIN     24
 #define UART_TX_PIN     25
 
+// SPI for USB host shield
+#define MAX3421_SCK_PIN  14
+#define MAX3421_MOSI_PIN 13
+#define MAX3421_MISO_PIN 15
+#define MAX3421_CS_PIN   27 // D10
+#define MAX3421_INTR_PIN 26 // D9
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
index f31899eb7..488f07b82 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
@@ -1,6 +1,12 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# enable max3421 host driver for this board
+MAX3421_HOST = 1
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
deleted file mode 100644
index 5314a4e93..000000000
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
index ece6e34cb..288a1b52e 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit Feather nRF52840 Sense
+   url: https://www.adafruit.com/product/4516
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
deleted file mode 100644
index 5314a4e93..000000000
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
index 132173a80..5f065eec0 100644
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit ItsyBitsy nRF52840 Express
+   url: https://www.adafruit.com/product/4481
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
deleted file mode 100644
index 5314a4e93..000000000
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
deleted file mode 100644
index 3afa234aa..000000000
--- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# flash using Nordic nrfutil (pip3 install nrfutil)
-# 	make BOARD=nrf52840_mdk_dongle SERIAL=/dev/ttyACM0 all flash
-NRFUTIL = nrfutil
-
-$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
-	$(NRFUTIL) pkg generate --hw-version 52 --sd-req 0x0000 --debug-mode --application $^ $@
-
-flash: $(BUILD)/$(PROJECT).zip
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200
\ No newline at end of file
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld
deleted file mode 100644
index 78eddc9c3..000000000
--- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x1000, LENGTH = 0xE0000-0x1000
-  RAM (rwx) :  ORIGIN = 0x20000008, LENGTH = 0x3fff8
-}
-
-
-INCLUDE "nrf_common.ld"
diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake
new file mode 100644
index 000000000..85314f3bc
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10056/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT nrf52840)
+
+function(update_board TARGET)
+endfunction()
+
+#board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
+#include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+#include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+#include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+#include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake)
diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h
index ab12d21aa..ec632e769 100644
--- a/hw/bsp/nrf/boards/pca10056/board.h
+++ b/hw/bsp/nrf/boards/pca10056/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Nordic nRF52840DK
+   url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,18 +36,28 @@
  extern "C" {
 #endif
 
+#define _PINNUM(port, pin)    ((port)*32 + (pin))
+
 // LED
 #define LED_PIN               13
 #define LED_STATE_ON          0
 
 // Button
-#define BUTTON_PIN            11
+#define BUTTON_PIN            25 // button 4
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
 #define UART_RX_PIN           8
 #define UART_TX_PIN           6
 
+// SPI for USB host shield
+// Pin is correct but not working probably due to signal incompatible (1.8V 3v3) with MAC3421E !?
+//#define MAX3421_SCK_PIN  _PINNUM(1, 15)
+//#define MAX3421_MOSI_PIN _PINNUM(1, 13)
+//#define MAX3421_MISO_PIN _PINNUM(1, 14)
+//#define MAX3421_CS_PIN   _PINNUM(1, 12)
+//#define MAX3421_INTR_PIN _PINNUM(1, 11)
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug
new file mode 100644
index 000000000..fa7ab9e23
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug
@@ -0,0 +1,238 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  // Dialog-generated settings
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M4F.svd");
+  Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd");
+
+  Project.SetDevice ("nRF52840_xxAA");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("8 MHz");
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  // User settings
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-pca10056/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging a RAM program on a Cortex-M target device
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  Exec.Reset();
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//
+//    Util.Log("Resetting Program.");
+//
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
diff --git a/hw/bsp/nrf/boards/pca10059/board.cmake b/hw/bsp/nrf/boards/pca10059/board.cmake
new file mode 100644
index 000000000..c79eb5964
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10059/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/pca10059.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10059/board.h b/hw/bsp/nrf/boards/pca10059/board.h
index 0810be648..3b95481ad 100644
--- a/hw/bsp/nrf/boards/pca10059/board.h
+++ b/hw/bsp/nrf/boards/pca10059/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Nordic nRF52840 Dongle
+   url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/nrf/boards/pca10059/pca10059.ld b/hw/bsp/nrf/boards/pca10059/pca10059.ld
index 510bfdd8c..adc80f3c4 100644
--- a/hw/bsp/nrf/boards/pca10059/pca10059.ld
+++ b/hw/bsp/nrf/boards/pca10059/pca10059.ld
@@ -1,7 +1,7 @@
 /* Linker script to configure memory regions. */
 
 SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
+/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/
 
 MEMORY
 {
@@ -11,3 +11,9 @@ MEMORY
 
 
 INCLUDE "nrf_common.ld"
+
+/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
+__tbss_start__ = __tbss_start;
+__tbss_end__ = __tbss_end;
+__sbss_start__ = __sbss_start;
+__sbss_end__ = __sbss_end;
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
new file mode 100644
index 000000000..6d183dde6
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -0,0 +1,7 @@
+set(MCU_VARIANT nrf5340_application)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PRIVATE
+    ${NRFX_PATH}/drivers/src/nrfx_usbreg.c
+    )
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
new file mode 100644
index 000000000..1c7981049
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -0,0 +1,65 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Nordic nRF5340 DK
+   url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF5340-DK
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define _PINNUM(port, pin)    ((port)*32 + (pin))
+
+// LED
+#define LED_PIN               28
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PIN            23
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_RX_PIN           22
+#define UART_TX_PIN           20
+
+// SPI for USB host shield
+// Pin is correct but not working probably due to signal incompatible (1.8V 3v3) with MAC3421E !?
+//#define MAX3421_SCK_PIN  _PINNUM(1, 15)
+//#define MAX3421_MOSI_PIN _PINNUM(1, 13)
+//#define MAX3421_MISO_PIN _PINNUM(1, 14)
+//#define MAX3421_CS_PIN   _PINNUM(1, 12)
+//#define MAX3421_INTR_PIN _PINNUM(1, 11)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/nrf/boards/pca10095/board.mk b/hw/bsp/nrf/boards/pca10095/board.mk
new file mode 100644
index 000000000..20580d619
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/board.mk
@@ -0,0 +1,17 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = nrf5340_application
+CFLAGS += -DNRF5340_XXAA -DNRF5340_XXAA_APPLICATION
+
+# enable max3421 host driver for this board
+MAX3421_HOST = 1
+
+LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf5340_xxaa_application.ld
+
+SRC_C += hw/mcu/nordic/nrfx/drivers/src/nrfx_usbreg.c
+
+# caused by void SystemStoreFICRNS() (without void) in system_nrf5340_application.c
+CFLAGS += -Wno-error=strict-prototypes
+
+# flash using jlink
+JLINK_DEVICE = nrf5340_xxaa_app
+flash: flash-jlink
diff --git a/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug b/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug
new file mode 100644
index 000000000..4ad0376a4
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug
@@ -0,0 +1,335 @@
+/*********************************************************************
+*                 (c) SEGGER Microcontroller GmbH                    *
+*                      The Embedded Experts                          *
+*                         www.segger.com                             *
+**********************************************************************
+
+File          :
+Created       : 30 Jun 2021 13:37
+Ozone Version : V3.24a
+*/
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  // Dialog-generated settings
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M33F.svd");
+  Project.AddSvdFile ("./nrf5340_application.svd");
+  Project.SetDevice ("nRF5340_xxAA_APP");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("16 MHz");
+
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  // User settings
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-pca10095/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*       OnStartupComplete
+*
+* Function description
+*   Called when program execution has reached/passed
+*   the startup completion point. Optional.
+*
+**********************************************************************
+*/
+//void OnStartupComplete (void) {
+//}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging an application in RAM on a Cortex-M target device.
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//  //
+//  // Set up initial stack pointer
+//  //
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//  }
+//  //
+//  // Set up entry point PC
+//  //
+//  PC = Elf.GetEntryPointPC();
+//
+//  if (PC != 0xFFFFFFFF) {
+//    Target.SetReg("PC", PC);
+//  } else if (VectorTableAddr != 0xFFFFFFFF) {
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  } else {
+//    Util.Error("Project file error: failed to set entry point PC", 1);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+**
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  _SetupTarget();
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  _SetupTarget();
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetResume
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetResume (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotLoad
+*
+* Function description
+*   Called upon loading a snapshot. Optional.
+*
+* Additional information
+*   This function is used to restore the target state in cases
+*   where values cannot simply be written to the target.
+*   Typical use: GPIO clock needs to be enabled, before
+*   GPIO is configured.
+*
+**********************************************************************
+*/
+//void OnSnapshotLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotSave
+*
+* Function description
+*   Called upon saving a snapshot. Optional.
+*
+* Additional information
+*   This function is usually used to save values of the target
+*   state which can either not be trivially read,
+*   or need to be restored in a specific way or order.
+*   Typically use: Memory Mapped Registers,
+*   such as PLL and GPIO configuration.
+*
+**********************************************************************
+*/
+//void OnSnapshotSave (void) {
+//}
+
+/*********************************************************************
+*
+*       OnError
+*
+* Function description
+*   Called when an error occurred. Optional.
+*
+**********************************************************************
+*/
+//void OnError (void) {
+//}
+
+/*********************************************************************
+*
+*       _SetupTarget
+*
+* Function description
+*   Setup the target.
+*   Called by AfterTargetReset() and AfterTargetDownload().
+*
+*   Auto-generated function. May be overridden by Ozone.
+*
+**********************************************************************
+*/
+void _SetupTarget(void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+  //
+  // Set up initial stack pointer
+  //
+  SP = Target.ReadU32(VectorTableAddr);
+  if (SP != 0xFFFFFFFF) {
+    Target.SetReg("SP", SP);
+  }
+  //
+  // Set up entry point PC
+  //
+  PC = Elf.GetEntryPointPC();
+  if (PC != 0xFFFFFFFF) {
+    Target.SetReg("PC", PC);
+  } else {
+    Util.Error("Project script error: failed to set up entry point PC", 1);
+  }
+}
diff --git a/hw/bsp/nrf/boards/pca10100/board.cmake b/hw/bsp/nrf/boards/pca10100/board.cmake
new file mode 100644
index 000000000..a925dae80
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10100/board.cmake
@@ -0,0 +1,4 @@
+set(MCU_VARIANT nrf52833)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10100/board.h b/hw/bsp/nrf/boards/pca10100/board.h
index 881133035..8aca6dce9 100644
--- a/hw/bsp/nrf/boards/pca10100/board.h
+++ b/hw/bsp/nrf/boards/pca10100/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Nordic nRF52833 DK
+   url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk
deleted file mode 100644
index be2ed3314..000000000
--- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf52840_xxaa.ld
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index a07332d4c..298ca2302 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,24 +24,53 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+/* metadata:
+   manufacturer: Nordic Semiconductor
+*/
+
+#include "bsp/board_api.h"
 #include "board.h"
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wcast-align"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#pragma GCC diagnostic ignored "-Wunused-variable"
+#pragma GCC diagnostic ignored "-Wundef"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
 #include "nrfx.h"
-#include "nrfx/hal/nrf_gpio.h"
-#include "nrfx/drivers/include/nrfx_power.h"
-#include "nrfx/drivers/include/nrfx_uarte.h"
+#include "hal/nrf_gpio.h"
+#include "nrfx_gpiote.h"
+#include "nrfx_power.h"
+#include "nrfx_uarte.h"
+#include "nrfx_spim.h"
 
 #ifdef SOFTDEVICE_PRESENT
 #include "nrf_sdm.h"
 #include "nrf_soc.h"
 #endif
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+
+// There is API changes between nrfx v2 and v3
+#if 85301 >= (10000*MDK_MAJOR_VERSION + 100*MDK_MINOR_VERSION + MDK_MICRO_VERSION)
+  // note MDK 8.53.1 is also used by nrfx v3.0.0, just skip this version and use later 3.x
+  #define NRFX_VER 2
+#else
+  #define NRFX_VER 3
+#endif
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
+void USBD_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -49,26 +78,56 @@ void USBD_IRQHandler(void)
 /* MACRO TYPEDEF CONSTANT ENUM
  *------------------------------------------------------------------*/
 
+// Value is chosen to be as same as NRFX_POWER_USB_EVT_* in nrfx_power.h
+enum {
+  USB_EVT_DETECTED = 0,
+  USB_EVT_REMOVED = 1,
+  USB_EVT_READY = 2
+};
+
+#ifdef NRF5340_XXAA
+  #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
+  #define VBUSDETECT_Msk USBREG_USBREGSTATUS_VBUSDETECT_Msk
+  #define OUTPUTRDY_Msk USBREG_USBREGSTATUS_OUTPUTRDY_Msk
+  #define GPIOTE_IRQn GPIOTE1_IRQn
+#else
+  #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_RC
+  #define VBUSDETECT_Msk POWER_USBREGSTATUS_VBUSDETECT_Msk
+  #define OUTPUTRDY_Msk POWER_USBREGSTATUS_OUTPUTRDY_Msk
+#endif
+
 static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
 
 // tinyusb function that handles power event (detected, ready, removed)
 // We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
 extern void tusb_hal_nrf_power_event(uint32_t event);
 
-
 // nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example)
-TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event)
-{
+TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
   tusb_hal_nrf_power_event((uint32_t) event);
 }
 
-void board_init(void)
-{
+//------------- Host using MAX2341E -------------//
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+static void max3421_init(void);
+static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
+
+#if NRFX_VER > 2
+static nrfx_gpiote_t _gpiote = NRFX_GPIOTE_INSTANCE(0);
+#endif
+
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+void board_init(void) {
   // stop LF clock just in case we jump from application without reset
   NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
 
   // Use Internal OSC to compatible with all boards
-  NRF_CLOCK->LFCLKSRC = CLOCK_LFCLKSRC_SRC_RC;
+  NRF_CLOCK->LFCLKSRC = LFCLK_SRC_RC;
   NRF_CLOCK->TASKS_LFCLKSTART = 1UL;
 
   // LED
@@ -78,26 +137,53 @@ void board_init(void)
   // Button
   nrf_gpio_cfg_input(BUTTON_PIN, NRF_GPIO_PIN_PULLUP);
 
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
-  SysTick_Config(SystemCoreClock/1000);
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_ZEPHYR
+  #ifdef CONFIG_HAS_HW_NRF_USBREG
+  // IRQ_CONNECT(USBREGULATOR_IRQn, DT_IRQ(DT_INST(0, nordic_nrf_clock), priority), nrfx_isr, nrfx_usbreg_irq_handler, 0);
+  // irq_enable(USBREGULATOR_IRQn);
+  #endif
+
+  /* USB device controller access from devicetree */
+  #define DT_DRV_COMPAT nordic_nrf_usbd
+  IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), nrfx_isr, USBD_IRQHandler, 0);
+  irq_enable(DT_INST_IRQN(0));
+#endif
 
   // UART
-  nrfx_uarte_config_t uart_cfg =
-  {
-    .pseltxd   = UART_TX_PIN,
-    .pselrxd   = UART_RX_PIN,
-    .pselcts   = NRF_UARTE_PSEL_DISCONNECTED,
-    .pselrts   = NRF_UARTE_PSEL_DISCONNECTED,
-    .p_context = NULL,
-    .baudrate  = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
-    .interrupt_priority = 7,
-    .hal_cfg = {
-      .hwfc      = NRF_UARTE_HWFC_DISABLED,
-      .parity    = NRF_UARTE_PARITY_EXCLUDED,
-    }
+  #if NRFX_VER <= 2
+  nrfx_uarte_config_t uart_cfg = {
+      .pseltxd   = UART_TX_PIN,
+      .pselrxd   = UART_RX_PIN,
+      .pselcts   = NRF_UARTE_PSEL_DISCONNECTED,
+      .pselrts   = NRF_UARTE_PSEL_DISCONNECTED,
+      .p_context = NULL,
+      .baudrate  = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
+      .interrupt_priority = 7,
+      .hal_cfg = {
+          .hwfc      = NRF_UARTE_HWFC_DISABLED,
+          .parity    = NRF_UARTE_PARITY_EXCLUDED,
+      }
   };
+  #else
+  nrfx_uarte_config_t uart_cfg = {
+      .txd_pin   = UART_TX_PIN,
+      .rxd_pin   = UART_RX_PIN,
+      .rts_pin   = NRF_UARTE_PSEL_DISCONNECTED,
+      .cts_pin   = NRF_UARTE_PSEL_DISCONNECTED,
+      .p_context = NULL,
+      .baudrate  = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
+      .interrupt_priority = 7,
+      .config = {
+          .hwfc      = NRF_UARTE_HWFC_DISABLED,
+          .parity    = NRF_UARTE_PARITY_EXCLUDED,
+      }
+  };
+  #endif
 
-  nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler);
+  nrfx_uarte_init(&_uart_id, &uart_cfg, NULL);
 
   //------------- USB -------------//
 #if CFG_TUD_ENABLED
@@ -123,67 +209,111 @@ void board_init(void)
 #endif
   {
     // Power module init
-    const nrfx_power_config_t pwr_cfg = { 0 };
+    const nrfx_power_config_t pwr_cfg = {0};
     nrfx_power_init(&pwr_cfg);
 
     // Register tusb function as USB power handler
     // cause cast-function-type warning
-    const nrfx_power_usbevt_config_t config = { .handler = power_event_handler };
+    const nrfx_power_usbevt_config_t config = {.handler = power_event_handler};
     nrfx_power_usbevt_init(&config);
-
     nrfx_power_usbevt_enable();
 
+    // USB power may already be ready at this time -> no event generated
+    // We need to invoke the handler based on the status initially
+#ifdef NRF5340_XXAA
+    usb_reg = NRF_USBREGULATOR->USBREGSTATUS;
+#else
     usb_reg = NRF_POWER->USBREGSTATUS;
+#endif
   }
 
-  if ( usb_reg & POWER_USBREGSTATUS_VBUSDETECT_Msk ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_DETECTED);
-  if ( usb_reg & POWER_USBREGSTATUS_OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_READY);
+  if ( usb_reg & VBUSDETECT_Msk ) {
+    tusb_hal_nrf_power_event(USB_EVT_DETECTED);
+  }
+  if ( usb_reg & OUTPUTRDY_Msk  ) {
+    tusb_hal_nrf_power_event(USB_EVT_READY);
+  }
 #endif
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+  max3421_init();
+#endif
+
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-//  return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+
+#ifdef NRF5340_XXAA
+  uintptr_t did_addr = (uintptr_t) NRF_FICR->INFO.DEVICEID;
+#else
+  uintptr_t did_addr = (uintptr_t) NRF_FICR->DEVICEID;
+#endif
+
+  const uint8_t* device_id = (const uint8_t*) did_addr;
+  for(uint8_t i=0; i<8; i++) {
+    id[i] = device_id[i];
+  }
+  return 8;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+//  nrfx_err_t err = nrfx_uarte_rx(&_uart_id, buf, (size_t) len);
+//  return NRFX_SUCCESS == err ? len : 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  nrfx_err_t err = nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len
+                                 #if NRFX_VER > 2
+                                 ,0
+                                 #endif
+                                );
+  return (NRFX_SUCCESS == err) ? len : 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
 
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+#endif
+
+//--------------------------------------------------------------------+
+// Softdevice running
+//--------------------------------------------------------------------+
 #ifdef SOFTDEVICE_PRESENT
 // process SOC event from SD
-uint32_t proc_soc(void)
-{
+uint32_t proc_soc(void) {
   uint32_t soc_evt;
   uint32_t err = sd_evt_get(&soc_evt);
 
@@ -200,25 +330,137 @@ uint32_t proc_soc(void)
   return err;
 }
 
-uint32_t proc_ble(void)
-{
+uint32_t proc_ble(void) {
   // do nothing with ble
   return NRF_ERROR_NOT_FOUND;
 }
 
-void SD_EVT_IRQHandler(void)
-{
+void SD_EVT_IRQHandler(void) {
   // process BLE and SOC until there is no more events
-  while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) )
-  {
-
+  while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) ) {
   }
 }
 
-void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info)
-{
+void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
   (void) id;
   (void) pc;
   (void) info;
 }
 #endif
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+#if NRFX_VER <= 2
+void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action ) {
+  if (action != NRF_GPIOTE_POLARITY_HITOLO) return;
+#else
+void max3421_int_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t action, void* p_context) {
+  (void) p_context;
+  if (action != NRFX_GPIOTE_TRIGGER_HITOLO) return;
+#endif
+
+  if (pin != MAX3421_INTR_PIN) return;
+  tuh_int_handler(1, true);
+}
+
+static void max3421_init(void) {
+  // Somehow pca10056/95 is not working probably due to signal incompatible (1.8V 3v3) with MAC3421E !?
+
+  // manually manage CS
+  nrf_gpio_cfg_output(MAX3421_CS_PIN);
+  nrf_gpio_pin_write(MAX3421_CS_PIN, 1);
+
+  // USB host using max3421e usb controller via SPI
+  nrfx_spim_config_t cfg = {
+      .sck_pin        = MAX3421_SCK_PIN,
+      .mosi_pin       = MAX3421_MOSI_PIN,
+      .miso_pin       = MAX3421_MISO_PIN,
+  #if NRFX_VER <= 2
+      .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
+      .frequency      = NRF_SPIM_FREQ_4M,
+  #else
+      .ss_pin         = NRF_SPIM_PIN_NOT_CONNECTED,
+      .frequency      = 4000000u,
+  #endif
+      .ss_active_high = false,
+      .irq_priority   = 3,
+      .orc            = 0xFF,
+      // default setting 4 Mhz, Mode 0, MSB first
+      .mode           = NRF_SPIM_MODE_0,
+      .bit_order      = NRF_SPIM_BIT_ORDER_MSB_FIRST,
+      .miso_pull      = NRF_GPIO_PIN_NOPULL,
+  };
+
+  // no handler --> blocking
+  TU_ASSERT(NRFX_SUCCESS == nrfx_spim_init(&_spi, &cfg, NULL, NULL), );
+
+  // max3421e interrupt pin
+  #if NRFX_VER <= 2
+  nrfx_gpiote_init(1);
+  nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
+  in_config.pull = NRF_GPIO_PIN_PULLUP;
+  NVIC_SetPriority(GPIOTE_IRQn, 2);
+  nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
+  nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
+  #else
+  nrf_gpio_pin_pull_t intr_pull = NRF_GPIO_PIN_PULLUP;
+  nrfx_gpiote_trigger_config_t intr_trigger = {
+      .trigger = NRFX_GPIOTE_TRIGGER_HITOLO,
+      .p_in_channel = NULL, // sensing mechanism
+  };
+  nrfx_gpiote_handler_config_t intr_handler = {
+      .handler = max3421_int_handler,
+      .p_context = NULL,
+  };
+  nrfx_gpiote_input_pin_config_t intr_config = {
+      .p_pull_config = &intr_pull,
+      .p_trigger_config = &intr_trigger,
+      .p_handler_config = &intr_handler,
+  };
+
+  nrfx_gpiote_init(&_gpiote, 1);
+  NVIC_SetPriority(GPIOTE_IRQn, 2);
+
+  nrfx_gpiote_input_configure(&_gpiote, MAX3421_INTR_PIN, &intr_config);
+  nrfx_gpiote_trigger_enable(&_gpiote, MAX3421_INTR_PIN, true);
+  #endif
+}
+
+// API to enable/disable MAX3421 INTR pin interrupt
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+
+  // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt
+  // when disabled and re-enabled.
+  if (enabled) {
+    NVIC_EnableIRQ(GPIOTE_IRQn);
+  } else {
+    NVIC_DisableIRQ(GPIOTE_IRQn);
+  }
+}
+
+// API to control MAX3421 SPI CS
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  nrf_gpio_pin_write(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+  (void) rhport;
+
+  nrfx_spim_xfer_desc_t xfer = {
+      .p_tx_buffer = tx_buf,
+      .tx_length   = tx_buf ? xfer_bytes : 0,
+      .p_rx_buffer = rx_buf,
+      .rx_length   = rx_buf ? xfer_bytes : 0,
+  };
+
+  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
+}
+
+#endif
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
new file mode 100644
index 000000000..7d0a9f6de
--- /dev/null
+++ b/hw/bsp/nrf/family.cmake
@@ -0,0 +1,149 @@
+include_guard()
+
+set(NRFX_PATH ${TOP}/hw/mcu/nordic/nrfx)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific, for zephyr BOARD_ALIAS may be used instead
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake OPTIONAL RESULT_VARIABLE board_cmake_included)
+if (NOT board_cmake_included)
+  include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD_ALIAS}/board.cmake)
+endif ()
+
+# toolchain set up
+if (MCU_VARIANT STREQUAL "nrf5340_application")
+  set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+  set(JLINK_DEVICE nrf5340_xxaa_app)
+else ()
+  set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+  set(JLINK_DEVICE ${MCU_VARIANT}_xxaa)
+endif ()
+
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  if (MCU_VARIANT STREQUAL "nrf5340_application")
+    set(MCU_VARIANT_XXAA "nrf5340_xxaa_application")
+  else ()
+    set(MCU_VARIANT_XXAA "${MCU_VARIANT}_xxaa")
+  endif ()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT_XXAA}.ld)
+  endif ()
+
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${NRFX_PATH}/mdk/gcc_startup_${MCU_VARIANT}.S)
+    set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${NRFX_PATH}/helpers/nrfx_flag32_allocator.c
+    ${NRFX_PATH}/drivers/src/nrfx_gpiote.c
+    ${NRFX_PATH}/drivers/src/nrfx_power.c
+    ${NRFX_PATH}/drivers/src/nrfx_spim.c
+    ${NRFX_PATH}/drivers/src/nrfx_uarte.c
+    ${NRFX_PATH}/mdk/system_${MCU_VARIANT}.c
+    ${NRFX_PATH}/soc/nrfx_atomic.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  string(TOUPPER "${MCU_VARIANT_XXAA}" MCU_VARIANT_XXAA_UPPER)
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __STARTUP_CLEAR_BSS
+    CONFIG_GPIO_AS_PINRESET
+    ${MCU_VARIANT_XXAA_UPPER}
+    )
+
+  if (TRACE_ETM STREQUAL "1")
+    # ENABLE_TRACE will cause system_nrf5x.c to set up ETM trace
+    target_compile_definitions(${BOARD_TARGET} PUBLIC ENABLE_TRACE)
+  endif ()
+
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/nrfx_config
+    ${NRFX_PATH}
+    ${NRFX_PATH}/mdk
+    ${NRFX_PATH}/drivers/include
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -L${NRFX_PATH}/mdk
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -L${NRFX_PATH}/mdk
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+
+#function(family_flash_adafruit_nrfutil TARGET)
+#  add_custom_target(${TARGET}-adafruit-nrfutil
+#    DEPENDS ${TARGET}
+#    COMMAND adafruit-nrfutil --verbose dfu serial --package $^ -p /dev/ttyACM0 -b 115200 --singlebank --touch 1200
+#    )
+#endfunction()
+
+
+function(family_configure_example TARGET RTOS)
+  # Board target
+  if (NOT RTOS STREQUAL zephyr)
+    add_board_target(board_${BOARD})
+    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+  endif ()
+
+  family_configure_common(${TARGET} ${RTOS})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PRIVATE
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+  if (RTOS STREQUAL zephyr AND DEFINED BOARD_ALIAS AND NOT BOARD STREQUAL BOARD_ALIAS)
+    target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD_ALIAS})
+  endif ()
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_NRF5X)
+  target_sources(${TARGET} PRIVATE
+    ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
+    )
+
+  # Flashing
+#  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+#  family_flash_adafruit_nrfutil(${TARGET})
+endfunction()
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index d8283a9e6..a8acb1624 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -1,48 +1,61 @@
 UF2_FAMILY_ID = 0xADA52840
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/nordic/nrfx
+
+NRFX_PATH = hw/mcu/nordic/nrfx
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# nRF52 is cortex-m4, nRF53 is cortex-m33
+CPU_CORE ?= cortex-m4
+
 CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -DCFG_TUSB_MCU=OPT_MCU_NRF5X \
-  -DCONFIG_GPIO_AS_PINRESET
+  -DCONFIG_GPIO_AS_PINRESET \
+  -D__STARTUP_CLEAR_BSS
+
+#CFLAGS += -nostdlib
+#CFLAGS += -D__START=main
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+CFLAGS_GCC += \
+  -flto \
+  -Wno-error=undef \
+  -Wno-error=unused-parameter \
+  -Wno-error=unused-variable \
+  -Wno-error=cast-align \
+  -Wno-error=cast-qual \
+  -Wno-error=redundant-decls \
 
-# All source paths should be relative to the top level.
-LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
+LDFLAGS_GCC += \
+  -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
+  -L$(TOP)/${NRFX_PATH}/mdk
 
-LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
+LDFLAGS_CLANG += \
+  -L$(TOP)/${NRFX_PATH}/mdk \
 
 SRC_C += \
   src/portable/nordic/nrf5x/dcd_nrf5x.c \
-  hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
-  hw/mcu/nordic/nrfx/drivers/src/nrfx_uarte.c \
-  hw/mcu/nordic/nrfx/mdk/system_$(MCU_VARIANT).c
+	${NRFX_PATH}/helpers/nrfx_flag32_allocator.c \
+	${NRFX_PATH}/drivers/src/nrfx_gpiote.c \
+  ${NRFX_PATH}/drivers/src/nrfx_power.c \
+  ${NRFX_PATH}/drivers/src/nrfx_spim.c \
+  ${NRFX_PATH}/drivers/src/nrfx_uarte.c \
+  ${NRFX_PATH}/mdk/system_$(MCU_VARIANT).c \
+  ${NRFX_PATH}/soc/nrfx_atomic.c
 
 INC += \
   $(TOP)/$(BOARD_PATH) \
+  $(TOP)/$(FAMILY_PATH)/nrfx_config \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/hw/mcu/nordic \
-  $(TOP)/hw/mcu/nordic/nrfx \
-  $(TOP)/hw/mcu/nordic/nrfx/mdk \
-  $(TOP)/hw/mcu/nordic/nrfx/hal \
-  $(TOP)/hw/mcu/nordic/nrfx/drivers/include \
-  $(TOP)/hw/mcu/nordic/nrfx/drivers/src \
+  $(TOP)/${NRFX_PATH} \
+  $(TOP)/${NRFX_PATH}/mdk \
+  $(TOP)/${NRFX_PATH}/hal \
+  $(TOP)/${NRFX_PATH}/drivers/include \
+  $(TOP)/${NRFX_PATH}/drivers/src \
 
-SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_$(MCU_VARIANT).S
+SRC_S += ${NRFX_PATH}/mdk/gcc_startup_$(MCU_VARIANT).S
 
 ASFLAGS += -D__HEAP_SIZE=0
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
 # For flash-jlink target
-JLINK_DEVICE = $(MCU_VARIANT)_xxaa
+JLINK_DEVICE ?= $(MCU_VARIANT)_xxaa
diff --git a/hw/bsp/nrf/linker/nrf52833_xxaa.ld b/hw/bsp/nrf/linker/nrf52833_xxaa.ld
new file mode 100644
index 000000000..ae4d0e5b3
--- /dev/null
+++ b/hw/bsp/nrf/linker/nrf52833_xxaa.ld
@@ -0,0 +1,20 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000
+  CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x20000
+}
+
+
+INCLUDE "nrf_common.ld"
+
+/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
+__tbss_start__ = __tbss_start;
+__tbss_end__ = __tbss_end;
+__sbss_start__ = __sbss_start;
+__sbss_end__ = __sbss_end;
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld b/hw/bsp/nrf/linker/nrf52840_s140_v6.ld
old mode 100755
new mode 100644
similarity index 59%
rename from hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
rename to hw/bsp/nrf/linker/nrf52840_s140_v6.ld
index 5314a4e93..037a14196
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
+++ b/hw/bsp/nrf/linker/nrf52840_s140_v6.ld
@@ -1,11 +1,11 @@
 /* Linker script to configure memory regions. */
 
 SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
+/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/
 
 MEMORY
 {
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
+  FLASH (rx) : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
 
   /* SRAM required by S132 depend on
    * - Attribute Table Size
@@ -13,8 +13,8 @@ MEMORY
    * - Max ATT MTU
    * - Concurrent connection peripheral + central + secure links
    * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
+   */
+  RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
 }
 
 SECTIONS
@@ -26,7 +26,7 @@ SECTIONS
     KEEP(*(.svc_data))
     PROVIDE(__stop_svc_data = .);
   } > RAM
-  
+
   .fs_data :
   {
     PROVIDE(__start_fs_data = .);
@@ -35,4 +35,10 @@ SECTIONS
   } > RAM
 } INSERT AFTER .data;
 
-INCLUDE "nrf52_common.ld"
+INCLUDE "nrf_common.ld"
+
+/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
+__tbss_start__ = __tbss_start;
+__tbss_end__ = __tbss_end;
+__sbss_start__ = __sbss_start;
+__sbss_end__ = __sbss_end;
diff --git a/hw/bsp/nrf/linker/nrf52840_xxaa.ld b/hw/bsp/nrf/linker/nrf52840_xxaa.ld
new file mode 100644
index 000000000..2d20ba7ac
--- /dev/null
+++ b/hw/bsp/nrf/linker/nrf52840_xxaa.ld
@@ -0,0 +1,20 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000
+  EXTFLASH (rx) : ORIGIN = 0x12000000, LENGTH = 0x8000000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
+  CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x40000
+}
+
+INCLUDE "nrf_common.ld"
+
+/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
+__tbss_start__ = __tbss_start;
+__tbss_end__ = __tbss_end;
+__sbss_start__ = __sbss_start;
+__sbss_end__ = __sbss_end;
diff --git a/hw/bsp/nrf/linker/nrf5340_xxaa_application.ld b/hw/bsp/nrf/linker/nrf5340_xxaa_application.ld
new file mode 100644
index 000000000..31762d0b2
--- /dev/null
+++ b/hw/bsp/nrf/linker/nrf5340_xxaa_application.ld
@@ -0,0 +1,21 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+/*GROUP(-lgcc -lc) not compatible with clang*/
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000
+  EXTFLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x8000000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
+  RAM1 (rwx) : ORIGIN = 0x20040000, LENGTH = 0x3F000
+}
+
+
+INCLUDE "nrf_common.ld"
+
+/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
+__tbss_start__ = __tbss_start;
+__tbss_end__ = __tbss_end;
+__sbss_start__ = __sbss_start;
+__sbss_end__ = __sbss_end;
diff --git a/hw/bsp/nrf/nrfx_config/nrfx_config.h b/hw/bsp/nrf/nrfx_config/nrfx_config.h
new file mode 100644
index 000000000..fbec4192b
--- /dev/null
+++ b/hw/bsp/nrf/nrfx_config/nrfx_config.h
@@ -0,0 +1,46 @@
+#ifndef NRFX_CONFIG_H__
+#define NRFX_CONFIG_H__
+
+#define NRFX_POWER_ENABLED   1
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  7
+
+#define NRFX_CLOCK_ENABLED   0
+#define NRFX_GPIOTE_ENABLED  1
+#define NRFX_GPIOTE0_ENABLED 1
+
+#define NRFX_UARTE_ENABLED   1
+#define NRFX_UARTE0_ENABLED  1
+
+#define NRFX_SPIM_ENABLED    1
+#define NRFX_SPIM1_ENABLED   1 // use SPI1 since nrf5340 share uart with spi
+
+#define NRFX_PRS_ENABLED     0
+#define NRFX_USBREG_ENABLED  1
+
+#if defined(NRF51)
+#include <templates/nrfx_config_nrf51.h>
+#elif defined(NRF52805_XXAA)
+#include <templates/nrfx_config_nrf52805.h>
+#elif defined(NRF52810_XXAA)
+#include <templates/nrfx_config_nrf52810.h>
+#elif defined(NRF52811_XXAA)
+#include <templates/nrfx_config_nrf52811.h>
+#elif defined(NRF52820_XXAA)
+#include <templates/nrfx_config_nrf52820.h>
+#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
+#include <templates/nrfx_config_nrf52832.h>
+#elif defined(NRF52833_XXAA)
+#include <templates/nrfx_config_nrf52833.h>
+#elif defined(NRF52840_XXAA)
+#include <templates/nrfx_config_nrf52840.h>
+#elif defined(NRF5340_XXAA_APPLICATION)
+#include <templates/nrfx_config_nrf5340_application.h>
+#elif defined(NRF5340_XXAA_NETWORK)
+    #include <templates/nrfx_config_nrf5340_network.h>
+#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA)
+    #include <templates/nrfx_config_nrf91.h>
+#else
+    #error "Unknown device."
+#endif
+
+#endif // NRFX_CONFIG_H__
diff --git a/hw/mcu/nordic/nrfx_glue.h b/hw/bsp/nrf/nrfx_config/nrfx_glue.h
similarity index 71%
rename from hw/mcu/nordic/nrfx_glue.h
rename to hw/bsp/nrf/nrfx_config/nrfx_glue.h
index cdf49b4ab..bc3b3689b 100644
--- a/hw/mcu/nordic/nrfx_glue.h
+++ b/hw/bsp/nrf/nrfx_config/nrfx_glue.h
@@ -1,7 +1,9 @@
 /*
- * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2024, Nordic Semiconductor ASA
  * All rights reserved.
  *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *
@@ -60,14 +62,14 @@ extern "C" {
 /**
  * @brief Macro for placing a runtime assertion.
  *
- * @param expression  Expression to evaluate.
+ * @param expression Expression to be evaluated.
  */
 #define NRFX_ASSERT(expression)
 
 /**
  * @brief Macro for placing a compile time assertion.
  *
- * @param expression  Expression to evaluate.
+ * @param expression Expression to be evaluated.
  */
 #define NRFX_STATIC_ASSERT(expression)
 
@@ -76,8 +78,8 @@ extern "C" {
 /**
  * @brief Macro for setting the priority of a specific IRQ.
  *
- * @param irq_number  IRQ number.
- * @param priority    Priority to set.
+ * @param irq_number IRQ number.
+ * @param priority   Priority to be set.
  */
 #define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority)
 static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number,
@@ -158,14 +160,10 @@ static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number)
     return (NVIC_GetPendingIRQ(irq_number) == 1);
 }
 
-/**
- * @brief Macro for entering into a critical section.
- */
+/** @brief Macro for entering into a critical section. */
 #define NRFX_CRITICAL_SECTION_ENTER()
 
-/**
- * @brief Macro for exiting from a critical section.
- */
+/** @brief Macro for exiting from a critical section. */
 #define NRFX_CRITICAL_SECTION_EXIT()
 
 //------------------------------------------------------------------------------
@@ -220,6 +218,75 @@ static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number)
 
 /** @} */
 
+//------------------------------------------------------------------------------
+
+#include <soc/nrfx_atomic.h>
+
+/**
+ * @brief Atomic 32 bit unsigned type.
+ */
+#define nrfx_atomic_t               nrfx_atomic_u32_t
+
+/**
+ * @brief Stores value to an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value to store.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value)
+
+/**
+ * @brief Performs logical OR operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of OR operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_OR(p_data, value)   nrfx_atomic_u32_fetch_or(p_data, value)
+
+/**
+ * @brief Performs logical AND operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of AND operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_AND(p_data, value)   nrfx_atomic_u32_fetch_and(p_data, value)
+
+/**
+ * @brief Performs logical XOR operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of XOR operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_XOR(p_data, value)   nrfx_atomic_u32_fetch_xor(p_data, value)
+
+/**
+ * @brief Performs logical ADD operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of ADD operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_ADD(p_data, value)   nrfx_atomic_u32_fetch_add(p_data, value)
+
+/**
+ * @brief Performs logical SUB operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of SUB operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_SUB(p_data, value)   nrfx_atomic_u32_fetch_sub(p_data, value)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/mcu/nordic/nrfx_log.h b/hw/bsp/nrf/nrfx_config/nrfx_log.h
similarity index 100%
rename from hw/mcu/nordic/nrfx_log.h
rename to hw/bsp/nrf/nrfx_config/nrfx_log.h
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index ad2ee1ea0..161ff9041 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -13,6 +13,8 @@ CFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=redundant-decls
 
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/nuc121_flash.ld
 
@@ -35,7 +37,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC121SC2AE
diff --git a/hw/bsp/nutiny_nuc121s/nuc121_flash.ld b/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
index 3966b276e..0c599a561 100644
--- a/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
+++ b/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
@@ -69,7 +69,7 @@ SECTIONS
  		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
  		*(SORT(.dtors.*))
  		*(.dtors)
-        
+
 		*(.rodata*)
 
 		KEEP(*(.eh_frame*))
diff --git a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
index 7117a3422..7cb9b2e69 100644
--- a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
+++ b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NuMicro.h"
 #include "clk.h"
 #include "sys.h"
diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk
index 000c8cd95..081764fd3 100644
--- a/hw/bsp/nutiny_nuc125s/board.mk
+++ b/hw/bsp/nutiny_nuc125s/board.mk
@@ -13,6 +13,8 @@ CFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=redundant-decls
 
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/nuc125_flash.ld
 
@@ -31,7 +33,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC125SC2AE
diff --git a/hw/bsp/nutiny_nuc125s/nuc125_flash.ld b/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
index 3966b276e..0c599a561 100644
--- a/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
+++ b/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
@@ -69,7 +69,7 @@ SECTIONS
  		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
  		*(SORT(.dtors.*))
  		*(.dtors)
-        
+
 		*(.rodata*)
 
 		KEEP(*(.eh_frame*))
diff --git a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
index 7117a3422..7cb9b2e69 100644
--- a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
+++ b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NuMicro.h"
 #include "clk.h"
 #include "sys.h"
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 0dcd897cb..2466b3a31 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -14,6 +14,8 @@ CFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=redundant-decls
 
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/nuc126_flash.ld
 
@@ -37,7 +39,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc126/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC126VG4AE
diff --git a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
index da62e7bd2..9974127a8 100644
--- a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
+++ b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NuMicro.h"
 #include "clk.h"
 #include "sys.h"
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index 4d7aac7f5..b54895b58 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -9,6 +9,8 @@ CFLAGS += \
   -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_NUC120
 
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld
 
@@ -30,7 +32,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc100_120/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC120LE3
diff --git a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
index 0d78116b8..18a189d8c 100644
--- a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
+++ b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NUC100Series.h"
 #include "clk.h"
 #include "sys.h"
diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk
index f27577e36..f3b389354 100644
--- a/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc505/board.mk
@@ -12,6 +12,8 @@ CFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=redundant-decls
 
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/nuc505_flashtoram.ld
 
@@ -42,14 +44,14 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc505/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = NUC505YO13Y
 
 # Note
-# To be able to program the SPI flash, it need to boot with ICP mode "1011". 
-# However, in ICP mode, opencod cannot establish connection to the mcu. 
+# To be able to program the SPI flash, it need to boot with ICP mode "1011".
+# However, in ICP mode, opencod cannot establish connection to the mcu.
 # Therefore, there is no easy command line flash for NUC505
 # It is probably better to just use Nuvoton NuMicro ICP programming on windows to program the board
 # - 1111 "SPI" (run from internal flash)
diff --git a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
index 49e66d2d0..3ec0066a3 100644
--- a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
+++ b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NUC505Series.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h b/hw/bsp/pic32mz/boards/olimex_emz64/board.h
similarity index 89%
rename from hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
rename to hw/bsp/pic32mz/boards/olimex_emz64/board.h
index 1d3565d5c..7f42e024f 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
+++ b/hw/bsp/pic32mz/boards/olimex_emz64/board.h
@@ -1,5 +1,5 @@
-/* 
- * The MIT License (MIT)
+/*
+* The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
  *
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Olimex PIC32-EMZ64
+   url: https://www.olimex.com/Products/PIC/Development/PIC32-EMZ64/open-source-hardware
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
index e47ec5f31..0bb6cb728 100644
--- a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
+++ b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2022 Jerzy Kasenberg
diff --git a/hw/bsp/pic32mz/boards/olimex_hmz144/board.h b/hw/bsp/pic32mz/boards/olimex_hmz144/board.h
new file mode 100644
index 000000000..c9c07bf77
--- /dev/null
+++ b/hw/bsp/pic32mz/boards/olimex_hmz144/board.h
@@ -0,0 +1,43 @@
+/*
+* The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Olimex PIC32-HMZ144
+   url: https://www.olimex.com/Products/PIC/Development/PIC32-HMZ144/open-source-hardware
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c
index 786f04978..da97f67a9 100644
--- a/hw/bsp/pic32mz/family.c
+++ b/hw/bsp/pic32mz/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2022 Jerzy Kasenberg
@@ -24,6 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Microchip
+*/
+
 #include <stdint.h>
 #include <stdbool.h>
 #include <xc.h>
diff --git a/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..b132e2559
--- /dev/null
+++ b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,168 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#pragma GCC diagnostic ignored "-Wundef"
+
+// extra push due to https://github.com/renesas/fsp/pull/278
+#pragma GCC diagnostic push
+#endif
+
+#include "bsp_api.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/ra/board_cfg.h b/hw/bsp/ra/board_cfg.h
new file mode 100644
index 000000000..825f8cd32
--- /dev/null
+++ b/hw/bsp/ra/board_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef BOARD_CFG_H_
+#define BOARD_CFG_H_
+#ifdef __cplusplus
+        extern "C" {
+        #endif
+
+        void bsp_init(void * p_args);
+
+        #ifdef __cplusplus
+        }
+        #endif
+#endif /* BOARD_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/board.cmake b/hw/bsp/ra/boards/portenta_c33/board.cmake
new file mode 100644
index 000000000..a1545f070
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/board.cmake
@@ -0,0 +1,16 @@
+set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra6m5)
+
+set(JLINK_DEVICE R7FA6M5BH)
+set(DFU_UTIL_VID_PID 2341:0368)
+
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h b/hw/bsp/ra/boards/portenta_c33/board.h
similarity index 83%
rename from hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
rename to hw/bsp/ra/boards/portenta_c33/board.h
index 6bb44f76d..7853c2dbd 100644
--- a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
+++ b/hw/bsp/ra/boards/portenta_c33/board.h
@@ -1,7 +1,7 @@
-/* 
+/*
  * The MIT License (MIT)
  *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,21 +24,23 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef BOARD_H_
-#define BOARD_H_
+/* metadata:
+   name: Arduino Portenta C33
+   url: https://www.arduino.cc/pro/hardware-product-portenta-c33/
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-// Note: need to insert jumper next to WS2812 pixel
-#define NEOPIXEL_PIN          45
-
-#define BUTTON_PIN            0
+#define LED_STATE_ON          1
 #define BUTTON_STATE_ACTIVE   0
 
 #ifdef __cplusplus
- }
+}
 #endif
 
-#endif /* BOARD_H_ */
+#endif
diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk
new file mode 100644
index 000000000..ab814cda6
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/board.mk
@@ -0,0 +1,11 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = ra6m5
+
+# Port 1 is highspeed
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
+
+JLINK_DEVICE = R7FA6M5BH
+DFU_UTIL_OPTION = -d 2341:0368 -a 0
+
+flash: flash-dfu-util
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..90afbdef3
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define RA_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #ifndef BSP_CFG_RTC_USED
+             #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+            #endif
+            #undef RA_NOT_DEFINED
+            #if defined(_RA_BOOT_IMAGE)
+             #define BSP_CFG_BOOT_IMAGE (1)
+            #endif
+            #define BSP_CFG_MCU_VCC_MV (3300)
+            #define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+            #define BSP_CFG_HEAP_BYTES (0x1000)
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PFS_PROTECT ((1))
+
+            #define BSP_CFG_C_RUNTIME_INIT ((1))
+            #define BSP_CFG_EARLY_INIT     ((0))
+
+            #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+            #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+            #endif
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+            #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+            #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+            #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+            #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..bd6a901c3
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..e532478f8
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M5BH3CFC
+      #define BSP_MCU_FEATURE_SET ('B')
+      #define BSP_ROM_SIZE_BYTES (2097152)
+      #define BSP_RAM_SIZE_BYTES (524288)
+      #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+      #define BSP_PACKAGE_LQFP
+      #define BSP_PACKAGE_PINS (176)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..c01219377
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,392 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+            #include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_MCU_GROUP_RA6M5 (1)
+            #define BSP_LOCO_HZ                 (32768)
+            #define BSP_MOCO_HZ                 (8000000)
+            #define BSP_SUB_CLOCK_HZ            (32768)
+            #if   BSP_CFG_HOCO_FREQUENCY == 0
+                #define BSP_HOCO_HZ                 (16000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 1
+                #define BSP_HOCO_HZ                 (18000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ                 (20000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+
+            #define BSP_CFG_FLL_ENABLE                 (0)
+
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
+            #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (1)
+
+            #if defined(_RA_TZ_SECURE)
+            #define BSP_TZ_SECURE_BUILD           (1)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #elif defined(_RA_TZ_NONSECURE)
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (1)
+            #else
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #endif
+
+            /* TrustZone Settings */
+            #define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+            #define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+            #define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
+
+            /* CMSIS TrustZone Settings */
+            #define SCB_CSR_AIRCR_INIT                (1)
+            #define SCB_AIRCR_BFHFNMINS_VAL           (0)
+            #define SCB_AIRCR_SYSRESETREQS_VAL        (1)
+            #define SCB_AIRCR_PRIS_VAL                (0)
+            #define TZ_FPU_NS_USAGE                   (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+            #define SCB_NSACR_CP10_11_VAL             (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+            #define FPU_FPCCR_TS_VAL                  (1U)
+#endif
+            #define FPU_FPCCR_CLRONRETS_VAL           (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+            #define FPU_FPCCR_CLRONRET_VAL            (1)
+#endif
+
+            /* The C-Cache line size that is configured during startup. */
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+            #define BSP_CFG_C_CACHE_LINE_SIZE   (1U)
+#endif
+
+            /* Type 1 Peripheral Security Attribution */
+
+            /* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+            0x33f4f9) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+            0x7fffcef4) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+            0xffae07f0) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+            0x3f3ff8) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+            0xfffffffc) /* Unused */
+#endif
+
+            /* Type 2 Peripheral Security Attribution */
+
+            /* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
+
+            /* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
+
+            /* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+            0xFFFFFFFCU)
+#endif
+
+            /* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
+            /* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
+
+            /* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+#endif
+
+            /* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
+
+            /* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+            0xFFFF0000U)
+#endif
+
+            /* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+            /* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+            0xFFFFFF00U)
+#endif
+
+            /* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
+#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
+
+            /* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
+
+            /* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
+
+            /* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+ #define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+            /* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+#endif
+
+            /* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+    #define BSP_TZ_CFG_SRAMSAR (\
+        1 | \
+        ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+        4 | \
+        0xFFFFFFF8U)
+#endif
+
+            /* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
+    #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
+
+            /* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+    /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+    #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
+
+            /* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+    #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
+            /* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+    #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
+
+            /* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+    #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+
+            #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+            #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+            #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+            #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+            #define OFS_SEQ5 (1 << 28) | (1 << 30)
+            #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+            /* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
+#else
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+#endif
+
+            #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (1 << 8))
+
+            /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+            #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+            /* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+            #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+#endif
+
+            /* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+            #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+            /* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+            #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+            /* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+            #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+#endif
+            /* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+            #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+            /* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+            #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+            #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+            #define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+            #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+            /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+            #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+            /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+            #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+            /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+            #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+            /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+            #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+            /* Security Attribution for Bank Select Register */
+#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
+            #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+            #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..c411386c1
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define LED1 (BSP_IO_PORT_01_PIN_07)
+#define SW1 (BSP_IO_PORT_04_PIN_08)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFC.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..d2688bf5b
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 000000000..91b9de11e
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
+#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */
+#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */
+#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
+#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
+#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c
new file mode 100644
index 000000000..50036c0ad
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h
new file mode 100644
index 000000000..6a08cbee0
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c
new file mode 100644
index 000000000..fad79741a
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c
@@ -0,0 +1,71 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_01_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_11_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+    }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/portenta_c33/script/fsp.ld b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld
new file mode 100644
index 000000000..605eef7d2
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+                  Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                          FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END    = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START    = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START   = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                            FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                            __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                           FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                           FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+                XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+                FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+                       DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+                       FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+                            OPTION_SETTING_LENGTH == 0 ? 0 :
+                            OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+  ITCM (rx)                       : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+  DTCM (rwx)                      : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+  FLASH (rx)                      : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+  RAM (rwx)                       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx)                 : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx)                 : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx)              : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx)              : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  OSPI_DEVICE_0_RAM (rwx)         : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1_RAM (rwx)         : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)                     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r)              : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_OFS (r)          : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+  OPTION_SETTING_SAS (r)          : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+  OPTION_SETTING_S (r)            : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+  ID_CODE (rx)                    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* Some devices have a gap of code flash between the vector table and ROM Registers.
+         * The flash gap section allows applications to place code and data in this section. */
+        *(.flash_gap*)
+
+        /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+        /* Allocate flash write-boundary-aligned
+         * space for sce9 wrapped public keys for mcuboot if the module is used.
+         */
+        KEEP(*(.mcuboot_sce9_key*))
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    . = .;
+    __itcm_data_pre_location = .;
+
+    /* Initialized ITCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .itcm_data : ALIGN(16)
+    {
+        /* Start of ITCM Secure Trustzone region. */
+        __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+        /* All ITCM data start */
+        __itcm_data_start = .;
+
+        KEEP(*(.itcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* All ITCM data end */
+        __itcm_data_end = .;
+
+        /*
+         * Start of the ITCM Non-Secure Trustzone region.
+         * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+    } > ITCM AT > FLASH = 0x00
+
+    /* Addresses exported for ITCM initialization. */
+    __itcm_data_init_start = LOADADDR(.itcm_data);
+    __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+    ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+    /* Restore location counter. */
+    /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+    . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+    __exidx_start = .;
+    /DISCARD/ :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    }
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    . = .;
+    __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+    /* Initialized DTCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .dtcm_data : ALIGN(16)
+    {
+        /* Start of DTCM Secure Trustzone region. */
+        __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+        /* Initialized DTCM data start */
+        __dtcm_data_start = .;
+
+        KEEP(*(.dtcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* Initialized DTCM data end */
+        __dtcm_data_end = .;
+    } > DTCM AT > FLASH = 0x00
+
+    . = __dtcm_data_end;
+    /* Uninitialized DTCM data. */
+    /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+    .dtcm_bss ALIGN(8) (NOLOAD) :
+    {
+        /* Uninitialized DTCM data start */
+        __dtcm_bss_start = .;
+
+        KEEP(*(.dtcm_bss*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+        . = ALIGN(8);
+
+        /* Uninitialized DTCM data end */
+        __dtcm_bss_end = .;
+
+        /*
+         * Start of the DTCM Non-Secure Trustzone region.
+         * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+         */
+        __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+    } > DTCM
+
+    /* Addresses exported for DTCM initialization. */
+    __dtcm_data_init_start = LOADADDR(.dtcm_data);
+    __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+    ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+    ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+    ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+    ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+    /* Restore location counter. */
+    /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+    . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+    /* TrustZone Secure Gateway Stubs Section */
+
+    /* Store location counter for SPI non-retentive sections. */
+    sgstubs_pre_location = .;
+
+    /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+    SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+    .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+    {
+        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+    FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = sgstubs_pre_location;
+    .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Support for OctaRAM */
+    .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_0_start__ = .;
+        *(.ospi_device_0_no_load*)
+        . = ALIGN(4);
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0_RAM
+
+    .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_1_start__ = .;
+        *(.ospi_device_1_no_load*)
+        . = ALIGN(4);
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1_RAM
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+     __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+    .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+    .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool.
+     *       Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+     *       memory region between TrustZone projects. */
+    __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+    .option_setting_ofs :
+    {
+        __OPTION_SETTING_OFS_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_ofs2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_dualsel))
+        __OPTION_SETTING_OFS_End = .;
+    } > OPTION_SETTING_OFS = 0xFF
+
+    .option_setting_sas :
+    {
+        __OPTION_SETTING_SAS_Start = .;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_SAS_End = .;
+    } > OPTION_SETTING_SAS = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_ofs3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps3))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel3))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld
new file mode 100644
index 000000000..74c648329
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld
@@ -0,0 +1,25 @@
+
+            /* generated memory regions file - do not edit */
+                            RAM_START  = 0x20000000;
+                RAM_LENGTH = 0x80000;
+                FLASH_START  = 0x00000000;
+                FLASH_LENGTH = 0x200000;
+                DATA_FLASH_START  = 0x08000000;
+                DATA_FLASH_LENGTH = 0x2000;
+                OPTION_SETTING_START  = 0x0100A100;
+                OPTION_SETTING_LENGTH = 0x100;
+                OPTION_SETTING_S_START  = 0x0100A200;
+                OPTION_SETTING_S_LENGTH = 0x100;
+                ID_CODE_START  = 0x00000000;
+                ID_CODE_LENGTH = 0x0;
+                SDRAM_START  = 0x80010000;
+                SDRAM_LENGTH = 0x0;
+                QSPI_FLASH_START  = 0x60000000;
+                QSPI_FLASH_LENGTH = 0x4000000;
+                OSPI_DEVICE_0_START  = 0x68000000;
+                OSPI_DEVICE_0_LENGTH = 0x8000000;
+                OSPI_DEVICE_1_START  = 0x70000000;
+                OSPI_DEVICE_1_LENGTH = 0x10000000;
+
+/* Board has bootloader */
+FLASH_IMAGE_START = 0x10000;
diff --git a/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml
new file mode 100644
index 000000000..fcc9d711d
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml
@@ -0,0 +1,240 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.custom"/>
+    <option key="CPU" value="RA6M5"/>
+    <option key="Core" value="CM33"/>
+    <option key="#TargetName#" value="R7FA6M5BH3CFC"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m33"/>
+    <option key="#DeviceCommand#" value="R7FA6M5BH"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA6M5BH3CFC.pincfg"/>
+    <option key="#FSPVersion#" value="5.6.0"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra6m5.R7FA6M5BH3CFC">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="2097152"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.irq_count_hidden" value="96"/>
+    </config>
+    <config id="config.bsp.ra6m5">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra6m5.fsp">
+      <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
+      <property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
+      <property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
+      <property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
+      <property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
+      <property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/>
+      <property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
+      <property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/>
+      <property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/>
+      <property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/>
+      <property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/>
+      <property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
+      <property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
+      <property id="config.bsp.fsp.tz.banksel_sel" value="config.bsp.fsp.tz.banksel_sel.both"/>
+      <property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/>
+      <property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
+      <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
+      <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/>
+      <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
+      <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
+      <property id="config.bsp.fsp.BPS.BPS0" value=""/>
+      <property id="config.bsp.fsp.BPS.BPS1" value=""/>
+      <property id="config.bsp.fsp.BPS.BPS2" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS2" value=""/>
+      <property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/>
+      <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="16666666"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
+      <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/>
+      <property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/>
+      <property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="8"/>
+      <property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="4864"/>
+      <property id="config.bsp.fsp.mcu.canfd.afl_rules" value="128"/>
+      <property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="64"/>
+      <property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="5"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x03F9"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
+      <property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="65535"/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x1000"/>
+      <property id="config.bsp.common.heap" value="0x1000"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
+    <node id="board.clock.pll.div" option="board.clock.pll.div.3"/>
+    <node id="board.clock.pll.mul" option="board.clock.pll.mul.250"/>
+    <node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
+    <node id="board.clock.pll2.source" option="board.clock.pll2.source.xtal"/>
+    <node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
+    <node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/>
+    <node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.uclk.source" option="board.clock.uclk.source.pll2"/>
+    <node id="board.clock.u60ck.source" option="board.clock.u60ck.source.pll2"/>
+    <node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
+    <node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
+    <node id="board.clock.cecclk.source" option="board.clock.cecclk.source.disabled"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
+    <node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
+    <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
+    <node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/>
+    <node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
+    <node id="board.clock.u60ck.div" option="board.clock.u60ck.div.4"/>
+    <node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.1"/>
+    <node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.1"/>
+    <node id="board.clock.cecclk.div" option="board.clock.cecclk.div.1"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
+    <node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+    <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
+    <node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
+    <node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
+    <node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
+    <node id="board.clock.cecclk.display" option="board.clock.cecclk.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
+      <description>Arm CMSIS Version 6 - Core (M)</description>
+      <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="5.6.0">
+      <description>Custom Board Support Files</description>
+      <originalPack>Renesas.RA_board_custom.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="R7FA6M5BH3CFC" vendor="Renesas" version="5.6.0">
+      <description>Board support package for R7FA6M5BH3CFC</description>
+      <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA6M5</description>
+      <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA6M5 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA6M5 - Events</description>
+      <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+    </context>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p107.symbolic_name" value="LED1"/>
+    <symbolicName propertyId="p408.symbolic_name" value="SW1"/>
+    <pincfg active="true" name="R7FA6M5BH3CFC.pincfg" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p107.output.low" configurationId="p107"/>
+      <configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+      <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p408.input" configurationId="p408"/>
+      <configSetting altId="p408.gpio_mode.gpio_mode_in" configurationId="p408.gpio_mode"/>
+      <configSetting altId="p408.gpio_pupd.gpio_pupd_ip_up" configurationId="p408.gpio_pupd"/>
+      <configSetting altId="pb01.usbhs0.vbus" configurationId="pb01"/>
+      <configSetting altId="pb01.gpio_mode.gpio_mode_peripheral" configurationId="pb01.gpio_mode"/>
+      <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
+      <configSetting altId="usbhs0.mode.device" configurationId="usbhs0.mode"/>
+      <configSetting altId="usbhs0.vbus.pb01" configurationId="usbhs0.vbus"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.cmake b/hw/bsp/ra/boards/ra2a1_ek/board.cmake
new file mode 100644
index 000000000..9c679c4b5
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/board.cmake
@@ -0,0 +1,10 @@
+set(CMAKE_SYSTEM_CPU cortex-m23 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra2a1)
+
+set(JLINK_DEVICE R7FA2A1AB)
+
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC)
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.h b/hw/bsp/ra/boards/ra2a1_ek/board.h
new file mode 100644
index 000000000..d925fc551
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/board.h
@@ -0,0 +1,46 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: RA2A1 EK
+   url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2a1-evaluation-kit-ra2a1-mcu-group
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_STATE_ON          1
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.mk b/hw/bsp/ra/boards/ra2a1_ek/board.mk
new file mode 100644
index 000000000..7a176418e
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m23
+MCU_VARIANT = ra2a1
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA2A1AB
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..bf1fe0cc6
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define RA_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #ifndef BSP_CFG_RTC_USED
+             #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+            #endif
+            #undef RA_NOT_DEFINED
+            #if defined(_RA_BOOT_IMAGE)
+             #define BSP_CFG_BOOT_IMAGE (1)
+            #endif
+            #define BSP_CFG_MCU_VCC_MV (3300)
+            #define BSP_CFG_STACK_MAIN_BYTES (0x400)
+            #define BSP_CFG_HEAP_BYTES (0x400)
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PFS_PROTECT ((1))
+
+            #define BSP_CFG_C_RUNTIME_INIT ((1))
+            #define BSP_CFG_EARLY_INIT     ((0))
+
+            #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+            #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+            #endif
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+            #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+            #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+            #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+            #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..eb82f4697
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (2)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..6970e4c33
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA2A1AB3CFM
+      #define BSP_MCU_FEATURE_SET ('A')
+      #define BSP_ROM_SIZE_BYTES (262144)
+      #define BSP_RAM_SIZE_BYTES (32768)
+      #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+      #define BSP_PACKAGE_LQFP
+      #define BSP_PACKAGE_PINS (64)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..24e3efaa2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,89 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_MCU_GROUP_RA2A1 (1)
+            #define BSP_LOCO_HZ                 (32768)
+            #define BSP_MOCO_HZ                 (8000000)
+            #define BSP_SUB_CLOCK_HZ            (32768)
+            #if   BSP_CFG_HOCO_FREQUENCY == 0
+                #define BSP_HOCO_HZ             (24000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ             (32000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 4
+                #define BSP_HOCO_HZ             (48000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 5
+                #define BSP_HOCO_HZ             (64000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
+            #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (0)
+
+            #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+            #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+            #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+            #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+            #define OFS_SEQ5 (1 << 28) | (1 << 30)
+            #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+            #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+            #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+            #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+            #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+            #endif
+            /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+            #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+            /*
+            ID Code
+            Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
+            WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
+            */
+            #if defined(BSP_ID_CODE_LOCKED)
+            #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+            #else
+            /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+            #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+            #endif
+
+            #if (0)
+            #define BSP_SECTION_FLASH_GAP BSP_PLACE_IN_SECTION(".flash_gap")
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..fc48a5809
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define LED1 (BSP_IO_PORT_02_PIN_05)
+#define SW1 (BSP_IO_PORT_02_PIN_06)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA2A1-EK.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..d2688bf5b
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 000000000..6b41669d3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
+#define BSP_CFG_SDADC_CLOCK_SOURCE (0) /* SDADCCLK Src: HOCO */
+#define BSP_CFG_SDADCCLK_DIV (7) /* SDADCCLK Div /12 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c
new file mode 100644
index 000000000..50036c0ad
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h
new file mode 100644
index 000000000..6a08cbee0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c
new file mode 100644
index 000000000..7fed32687
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c
@@ -0,0 +1,115 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_00_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+    }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld
new file mode 100644
index 000000000..605eef7d2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+                  Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                          FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END    = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START    = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START   = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                            FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                            __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                           FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                           FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+                XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+                FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+                       DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+                       FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+                            OPTION_SETTING_LENGTH == 0 ? 0 :
+                            OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+  ITCM (rx)                       : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+  DTCM (rwx)                      : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+  FLASH (rx)                      : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+  RAM (rwx)                       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx)                 : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx)                 : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx)              : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx)              : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  OSPI_DEVICE_0_RAM (rwx)         : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1_RAM (rwx)         : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)                     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r)              : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_OFS (r)          : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+  OPTION_SETTING_SAS (r)          : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+  OPTION_SETTING_S (r)            : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+  ID_CODE (rx)                    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* Some devices have a gap of code flash between the vector table and ROM Registers.
+         * The flash gap section allows applications to place code and data in this section. */
+        *(.flash_gap*)
+
+        /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+        /* Allocate flash write-boundary-aligned
+         * space for sce9 wrapped public keys for mcuboot if the module is used.
+         */
+        KEEP(*(.mcuboot_sce9_key*))
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    . = .;
+    __itcm_data_pre_location = .;
+
+    /* Initialized ITCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .itcm_data : ALIGN(16)
+    {
+        /* Start of ITCM Secure Trustzone region. */
+        __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+        /* All ITCM data start */
+        __itcm_data_start = .;
+
+        KEEP(*(.itcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* All ITCM data end */
+        __itcm_data_end = .;
+
+        /*
+         * Start of the ITCM Non-Secure Trustzone region.
+         * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+    } > ITCM AT > FLASH = 0x00
+
+    /* Addresses exported for ITCM initialization. */
+    __itcm_data_init_start = LOADADDR(.itcm_data);
+    __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+    ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+    /* Restore location counter. */
+    /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+    . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+    __exidx_start = .;
+    /DISCARD/ :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    }
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    . = .;
+    __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+    /* Initialized DTCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .dtcm_data : ALIGN(16)
+    {
+        /* Start of DTCM Secure Trustzone region. */
+        __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+        /* Initialized DTCM data start */
+        __dtcm_data_start = .;
+
+        KEEP(*(.dtcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* Initialized DTCM data end */
+        __dtcm_data_end = .;
+    } > DTCM AT > FLASH = 0x00
+
+    . = __dtcm_data_end;
+    /* Uninitialized DTCM data. */
+    /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+    .dtcm_bss ALIGN(8) (NOLOAD) :
+    {
+        /* Uninitialized DTCM data start */
+        __dtcm_bss_start = .;
+
+        KEEP(*(.dtcm_bss*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+        . = ALIGN(8);
+
+        /* Uninitialized DTCM data end */
+        __dtcm_bss_end = .;
+
+        /*
+         * Start of the DTCM Non-Secure Trustzone region.
+         * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+         */
+        __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+    } > DTCM
+
+    /* Addresses exported for DTCM initialization. */
+    __dtcm_data_init_start = LOADADDR(.dtcm_data);
+    __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+    ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+    ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+    ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+    ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+    /* Restore location counter. */
+    /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+    . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+    /* TrustZone Secure Gateway Stubs Section */
+
+    /* Store location counter for SPI non-retentive sections. */
+    sgstubs_pre_location = .;
+
+    /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+    SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+    .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+    {
+        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+    FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = sgstubs_pre_location;
+    .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Support for OctaRAM */
+    .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_0_start__ = .;
+        *(.ospi_device_0_no_load*)
+        . = ALIGN(4);
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0_RAM
+
+    .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_1_start__ = .;
+        *(.ospi_device_1_no_load*)
+        . = ALIGN(4);
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1_RAM
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+     __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+    .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+    .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool.
+     *       Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+     *       memory region between TrustZone projects. */
+    __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+    .option_setting_ofs :
+    {
+        __OPTION_SETTING_OFS_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_ofs2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_dualsel))
+        __OPTION_SETTING_OFS_End = .;
+    } > OPTION_SETTING_OFS = 0xFF
+
+    .option_setting_sas :
+    {
+        __OPTION_SETTING_SAS_Start = .;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_SAS_End = .;
+    } > OPTION_SETTING_SAS = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_ofs3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps3))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel3))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld
new file mode 100644
index 000000000..2d6992fed
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+            /* generated memory regions file - do not edit */
+                            RAM_START  = 0x20000000;
+                RAM_LENGTH = 0x8000;
+                FLASH_START  = 0x00000000;
+                FLASH_LENGTH = 0x40000;
+                DATA_FLASH_START  = 0x40100000;
+                DATA_FLASH_LENGTH = 0x2000;
+                OPTION_SETTING_START  = 0x00000000;
+                OPTION_SETTING_LENGTH = 0x0;
+                OPTION_SETTING_S_START  = 0x80000000;
+                OPTION_SETTING_S_LENGTH = 0x0;
+                ID_CODE_START  = 0x01010018;
+                ID_CODE_LENGTH = 0x20;
+                SDRAM_START  = 0x80010000;
+                SDRAM_LENGTH = 0x0;
+                QSPI_FLASH_START  = 0x60000000;
+                QSPI_FLASH_LENGTH = 0x0;
+                OSPI_DEVICE_0_START  = 0x80020000;
+                OSPI_DEVICE_0_LENGTH = 0x0;
+                OSPI_DEVICE_1_START  = 0x80030000;
+                OSPI_DEVICE_1_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml
new file mode 100644
index 000000000..beeeb67f2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml
@@ -0,0 +1,258 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.ra2a1_ek"/>
+    <option key="CPU" value="RA2A1"/>
+    <option key="Core" value="CM23"/>
+    <option key="#TargetName#" value="R7FA2A1AB3CFM"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m23"/>
+    <option key="#DeviceCommand#" value="R7FA2A1AB"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA2A1AB3CFM.pincfg"/>
+    <option key="#FSPVersion#" value="5.6.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra2a1_ek##"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra2a1.R7FA2A1AB3CFM">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="262144"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.irq_count_hidden" value="32"/>
+    </config>
+    <config id="config.bsp.ra2a1">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra2a1.fsp">
+      <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
+      <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
+      <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/>
+      <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/>
+      <property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_start" value="0x000FFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc0_end" value="0x000FFFFF"/>
+      <property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc1_start" value="0x000FFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc1_end" value="0x000FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg0_start" value="0x000FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg0_end" value="0x000FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="32000000"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="3333333"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
+      <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="1"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="8000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="16000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
+      <property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
+      <property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
+      <property id="config.bsp.common.id1" value=""/>
+      <property id="config.bsp.common.id2" value=""/>
+      <property id="config.bsp.common.id3" value=""/>
+      <property id="config.bsp.common.id4" value=""/>
+      <property id="config.bsp.common.id_fixed" value=""/>
+      <property id="config.bsp.common.fill_flash_gap" value="config.bsp.common.fill_flash_gap.disabled"/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x400"/>
+      <property id="config.bsp.common.heap" value="0x400"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="12000000" option="_edit"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.hoco"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
+    <node id="board.clock.sdadcclk.source" option="board.clock.sdadcclk.source.hoco"/>
+    <node id="board.clock.sdadcclk.div" option="board.clock.sdadcclk.div.12"/>
+    <node id="board.clock.sdadcclk.display" option="board.clock.sdadcclk.display.value"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0">
+      <description>Simple application that blinks an LED. No RTOS included.</description>
+      <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
+      <description>Arm CMSIS Version 6 - Core (M)</description>
+      <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra2a1_ek" variant="" vendor="Renesas" version="5.6.0">
+      <description>RA2A1-EK Board Support Files</description>
+      <originalPack>Renesas.RA_board_ra2a1_ek.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="device" variant="R7FA2A1AB3CFM" vendor="Renesas" version="5.6.0">
+      <description>Board support package for R7FA2A1AB3CFM</description>
+      <originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA2A1</description>
+      <originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA2A1 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA2A1 - Events</description>
+      <originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+    </context>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p205.symbolic_name" value="LED1"/>
+    <symbolicName propertyId="p206.symbolic_name" value="SW1"/>
+    <pincfg active="true" name="RA2A1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="adc0.an06.p003" configurationId="adc0.an06"/>
+      <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
+      <configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
+      <configSetting altId="ctsu0.ts15.p001" configurationId="ctsu0.ts15"/>
+      <configSetting altId="ctsu0.tscap.p409" configurationId="ctsu0.tscap"/>
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p001.ctsu0.ts15" configurationId="p001"/>
+      <configSetting altId="p001.gpio_mode.gpio_mode_peripheral" configurationId="p001.gpio_mode"/>
+      <configSetting altId="p003.adc0.an06" configurationId="p003"/>
+      <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p111.spi0.rspck" configurationId="p111"/>
+      <configSetting altId="p111.gpio_mode.gpio_mode_peripheral" configurationId="p111.gpio_mode"/>
+      <configSetting altId="p112.spi0.ssl0" configurationId="p112"/>
+      <configSetting altId="p112.gpio_mode.gpio_mode_peripheral" configurationId="p112.gpio_mode"/>
+      <configSetting altId="p201.input" configurationId="p201"/>
+      <configSetting altId="p201.gpio_mode.gpio_mode_in" configurationId="p201.gpio_mode"/>
+      <configSetting altId="p204.sci0.rxd" configurationId="p204"/>
+      <configSetting altId="p204.gpio_mode.gpio_mode_peripheral" configurationId="p204.gpio_mode"/>
+      <configSetting altId="p205.output.low" configurationId="p205"/>
+      <configSetting altId="p205.gpio_mode.gpio_mode_out.low" configurationId="p205.gpio_mode"/>
+      <configSetting altId="p206.input" configurationId="p206"/>
+      <configSetting altId="p206.gpio_mode.gpio_mode_in" configurationId="p206.gpio_mode"/>
+      <configSetting altId="p206.gpio_pupd.gpio_pupd_ip_up" configurationId="p206.gpio_pupd"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+      <configSetting altId="p303.spi0.mosi" configurationId="p303"/>
+      <configSetting altId="p303.gpio_mode.gpio_mode_peripheral" configurationId="p303.gpio_mode"/>
+      <configSetting altId="p304.spi0.miso" configurationId="p304"/>
+      <configSetting altId="p304.gpio_mode.gpio_mode_peripheral" configurationId="p304.gpio_mode"/>
+      <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p409.ctsu0.tscap" configurationId="p409"/>
+      <configSetting altId="p409.gpio_mode.gpio_mode_peripheral" configurationId="p409.gpio_mode"/>
+      <configSetting altId="p411.sci0.txd" configurationId="p411"/>
+      <configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
+      <configSetting altId="p914.usbfs0.dp" configurationId="p914"/>
+      <configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/>
+      <configSetting altId="p915.usbfs0.dm" configurationId="p915"/>
+      <configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/>
+      <configSetting altId="sci0.mode.asynchronous.free" configurationId="sci0.mode"/>
+      <configSetting altId="sci0.rxd.p204" configurationId="sci0.rxd"/>
+      <configSetting altId="sci0.txd.p411" configurationId="sci0.txd"/>
+      <configSetting altId="spi0.miso.p304" configurationId="spi0.miso"/>
+      <configSetting altId="spi0.mode.enabled.b" configurationId="spi0.mode"/>
+      <configSetting altId="spi0.mosi.p303" configurationId="spi0.mosi"/>
+      <configSetting altId="spi0.pairing.b" configurationId="spi0.pairing"/>
+      <configSetting altId="spi0.rspck.p111" configurationId="spi0.rspck"/>
+      <configSetting altId="spi0.ssl0.p112" configurationId="spi0.ssl0"/>
+      <configSetting altId="usbfs0.dm.p915" configurationId="usbfs0.dm"/>
+      <configSetting altId="usbfs0.dp.p914" configurationId="usbfs0.dp"/>
+      <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
+    </pincfg>
+    <pincfg active="false" name="R7FA2A1AB3CFM.pincfg" selected="false" symbol="">
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.cmake b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
new file mode 100644
index 000000000..247dea619
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
@@ -0,0 +1,12 @@
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m1)
+
+set(JLINK_DEVICE R7FA4M1AB)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h
new file mode 100644
index 000000000..e146261be
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.h
@@ -0,0 +1,46 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: RA4M1 EK
+   url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_STATE_ON          1
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.mk b/hw/bsp/ra/boards/ra4m1_ek/board.mk
new file mode 100644
index 000000000..f257c0000
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m4
+MCU_VARIANT = ra4m1
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M1AB
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..43b0f5b65
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define RA_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #ifndef BSP_CFG_RTC_USED
+             #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+            #endif
+            #undef RA_NOT_DEFINED
+            #if defined(_RA_BOOT_IMAGE)
+             #define BSP_CFG_BOOT_IMAGE (1)
+            #endif
+            #define BSP_CFG_MCU_VCC_MV (3300)
+            #define BSP_CFG_STACK_MAIN_BYTES (0x800)
+            #define BSP_CFG_HEAP_BYTES (0x1000)
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PFS_PROTECT ((1))
+
+            #define BSP_CFG_C_RUNTIME_INIT ((1))
+            #define BSP_CFG_EARLY_INIT     ((0))
+
+            #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+            #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+            #endif
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+            #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+            #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+            #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+            #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..243fad9b6
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M1AB3CFP
+      #define BSP_MCU_FEATURE_SET ('A')
+      #define BSP_ROM_SIZE_BYTES (262144)
+      #define BSP_RAM_SIZE_BYTES (32768)
+      #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+      #define BSP_PACKAGE_LQFP
+      #define BSP_PACKAGE_PINS (100)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..3d482b2b6
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,84 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_MCU_GROUP_RA4M1 (1)
+            #define BSP_LOCO_HZ                 (32768)
+            #define BSP_MOCO_HZ                 (8000000)
+            #define BSP_SUB_CLOCK_HZ            (32768)
+            #if   BSP_CFG_HOCO_FREQUENCY == 0
+                #define BSP_HOCO_HZ             (24000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ             (32000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 4
+                #define BSP_HOCO_HZ             (48000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 5
+                #define BSP_HOCO_HZ             (64000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
+            #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (1)
+
+            #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+            #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+            #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+            #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+            #define OFS_SEQ5 (1 << 28) | (1 << 30)
+            #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+            #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+            #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+            #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+            #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+            #endif
+            /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+            #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+            /*
+            ID Code
+            Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+            WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+            */
+            #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+            #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+            #else
+            /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+            #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..f77a5bcec
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define SW1 (BSP_IO_PORT_01_PIN_05)
+#define LED1 (BSP_IO_PORT_01_PIN_06)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M1-EK.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..d2688bf5b
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 000000000..81ac5dc11
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,21 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(8U,0U) /* PLL Mul x8 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c
new file mode 100644
index 000000000..50036c0ad
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h
new file mode 100644
index 000000000..6a08cbee0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c
new file mode 100644
index 000000000..baa713443
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c
@@ -0,0 +1,119 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_00_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+    }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld
new file mode 100644
index 000000000..605eef7d2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+                  Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                          FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END    = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START    = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START   = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                            FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                            __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                           FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                           FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+                XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+                FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+                       DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+                       FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+                            OPTION_SETTING_LENGTH == 0 ? 0 :
+                            OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+  ITCM (rx)                       : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+  DTCM (rwx)                      : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+  FLASH (rx)                      : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+  RAM (rwx)                       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx)                 : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx)                 : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx)              : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx)              : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  OSPI_DEVICE_0_RAM (rwx)         : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1_RAM (rwx)         : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)                     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r)              : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_OFS (r)          : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+  OPTION_SETTING_SAS (r)          : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+  OPTION_SETTING_S (r)            : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+  ID_CODE (rx)                    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* Some devices have a gap of code flash between the vector table and ROM Registers.
+         * The flash gap section allows applications to place code and data in this section. */
+        *(.flash_gap*)
+
+        /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+        /* Allocate flash write-boundary-aligned
+         * space for sce9 wrapped public keys for mcuboot if the module is used.
+         */
+        KEEP(*(.mcuboot_sce9_key*))
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    . = .;
+    __itcm_data_pre_location = .;
+
+    /* Initialized ITCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .itcm_data : ALIGN(16)
+    {
+        /* Start of ITCM Secure Trustzone region. */
+        __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+        /* All ITCM data start */
+        __itcm_data_start = .;
+
+        KEEP(*(.itcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* All ITCM data end */
+        __itcm_data_end = .;
+
+        /*
+         * Start of the ITCM Non-Secure Trustzone region.
+         * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+    } > ITCM AT > FLASH = 0x00
+
+    /* Addresses exported for ITCM initialization. */
+    __itcm_data_init_start = LOADADDR(.itcm_data);
+    __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+    ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+    /* Restore location counter. */
+    /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+    . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+    __exidx_start = .;
+    /DISCARD/ :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    }
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    . = .;
+    __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+    /* Initialized DTCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .dtcm_data : ALIGN(16)
+    {
+        /* Start of DTCM Secure Trustzone region. */
+        __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+        /* Initialized DTCM data start */
+        __dtcm_data_start = .;
+
+        KEEP(*(.dtcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* Initialized DTCM data end */
+        __dtcm_data_end = .;
+    } > DTCM AT > FLASH = 0x00
+
+    . = __dtcm_data_end;
+    /* Uninitialized DTCM data. */
+    /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+    .dtcm_bss ALIGN(8) (NOLOAD) :
+    {
+        /* Uninitialized DTCM data start */
+        __dtcm_bss_start = .;
+
+        KEEP(*(.dtcm_bss*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+        . = ALIGN(8);
+
+        /* Uninitialized DTCM data end */
+        __dtcm_bss_end = .;
+
+        /*
+         * Start of the DTCM Non-Secure Trustzone region.
+         * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+         */
+        __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+    } > DTCM
+
+    /* Addresses exported for DTCM initialization. */
+    __dtcm_data_init_start = LOADADDR(.dtcm_data);
+    __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+    ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+    ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+    ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+    ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+    /* Restore location counter. */
+    /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+    . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+    /* TrustZone Secure Gateway Stubs Section */
+
+    /* Store location counter for SPI non-retentive sections. */
+    sgstubs_pre_location = .;
+
+    /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+    SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+    .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+    {
+        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+    FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = sgstubs_pre_location;
+    .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Support for OctaRAM */
+    .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_0_start__ = .;
+        *(.ospi_device_0_no_load*)
+        . = ALIGN(4);
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0_RAM
+
+    .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_1_start__ = .;
+        *(.ospi_device_1_no_load*)
+        . = ALIGN(4);
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1_RAM
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+     __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+    .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+    .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool.
+     *       Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+     *       memory region between TrustZone projects. */
+    __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+    .option_setting_ofs :
+    {
+        __OPTION_SETTING_OFS_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_ofs2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_dualsel))
+        __OPTION_SETTING_OFS_End = .;
+    } > OPTION_SETTING_OFS = 0xFF
+
+    .option_setting_sas :
+    {
+        __OPTION_SETTING_SAS_Start = .;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_SAS_End = .;
+    } > OPTION_SETTING_SAS = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_ofs3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps3))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel3))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld
new file mode 100644
index 000000000..2d6992fed
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+            /* generated memory regions file - do not edit */
+                            RAM_START  = 0x20000000;
+                RAM_LENGTH = 0x8000;
+                FLASH_START  = 0x00000000;
+                FLASH_LENGTH = 0x40000;
+                DATA_FLASH_START  = 0x40100000;
+                DATA_FLASH_LENGTH = 0x2000;
+                OPTION_SETTING_START  = 0x00000000;
+                OPTION_SETTING_LENGTH = 0x0;
+                OPTION_SETTING_S_START  = 0x80000000;
+                OPTION_SETTING_S_LENGTH = 0x0;
+                ID_CODE_START  = 0x01010018;
+                ID_CODE_LENGTH = 0x20;
+                SDRAM_START  = 0x80010000;
+                SDRAM_LENGTH = 0x0;
+                QSPI_FLASH_START  = 0x60000000;
+                QSPI_FLASH_LENGTH = 0x0;
+                OSPI_DEVICE_0_START  = 0x80020000;
+                OSPI_DEVICE_0_LENGTH = 0x0;
+                OSPI_DEVICE_1_START  = 0x80030000;
+                OSPI_DEVICE_1_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml
new file mode 100644
index 000000000..2ca7fe595
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml
@@ -0,0 +1,271 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.ra4m1ek"/>
+    <option key="CPU" value="RA4M1"/>
+    <option key="Core" value="CM4"/>
+    <option key="#TargetName#" value="R7FA4M1AB3CFP"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m4"/>
+    <option key="#DeviceCommand#" value="R7FA4M1AB"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA4M1AB3CFP.pincfg"/>
+    <option key="#FSPVersion#" value="5.6.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra4m1_ek##"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra4m1.R7FA4M1AB3CFP">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="262144"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.irq_count_hidden" value="32"/>
+    </config>
+    <config id="config.bsp.ra4m1">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra4m1.fsp">
+      <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
+      <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
+      <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/>
+      <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/>
+      <property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_start" value="0x00FFFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc0_end" value="0x00FFFFFF"/>
+      <property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc1_start" value="0x00FFFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc1_end" value="0x00FFFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg0_start" value="0x00FFFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg0_end" value="0x00FFFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="64000000"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="6666666"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
+      <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="1"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="12000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="24000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
+      <property id="config.bsp.fsp.mcu.slcdc.1_4_bias_method" value="1"/>
+      <property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
+      <property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
+      <property id="config.bsp.common.id1" value=""/>
+      <property id="config.bsp.common.id2" value=""/>
+      <property id="config.bsp.common.id3" value=""/>
+      <property id="config.bsp.common.id4" value=""/>
+      <property id="config.bsp.common.id_fixed" value=""/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x800"/>
+      <property id="config.bsp.common.heap" value="0x1000"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="12000000" option="_edit"/>
+    <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.24m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.pll.div" option="board.clock.pll.div.2"/>
+    <node id="board.clock.pll.mul" option="board.clock.pll.mul.8"/>
+    <node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclka.div" option="board.clock.pclka.div.1"/>
+    <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.1"/>
+    <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+    <node id="board.clock.uclk.source" option="board.clock.uclk.source.pll"/>
+    <node id="board.clock.uclk.display" option="board.clock.clkout.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0">
+      <description>Simple application that blinks an LED. No RTOS included.</description>
+      <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
+      <description>Arm CMSIS Version 6 - Core (M)</description>
+      <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra4m1_ek" variant="" vendor="Renesas" version="5.6.0">
+      <description>RA4M1-EK Board Support Files</description>
+      <originalPack>Renesas.RA_board_ra4m1_ek.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="R7FA4M1AB3CFP" vendor="Renesas" version="5.6.0">
+      <description>Board support package for R7FA4M1AB3CFP</description>
+      <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA4M1</description>
+      <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA4M1 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA4M1 - Events</description>
+      <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+    </context>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p105.symbolic_name" value="SW1"/>
+    <symbolicName propertyId="p106.symbolic_name" value="LED1"/>
+    <pincfg active="true" name="RA4M1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="adc0.an04.p004" configurationId="adc0.an04"/>
+      <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
+      <configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
+      <configSetting altId="ctsu0.ts35.p115" configurationId="ctsu0.ts35"/>
+      <configSetting altId="ctsu0.tscap.p205" configurationId="ctsu0.tscap"/>
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p004.adc0.an04" configurationId="p004"/>
+      <configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
+      <configSetting altId="p100.spi0.miso" configurationId="p100"/>
+      <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
+      <configSetting altId="p101.spi0.mosi" configurationId="p101"/>
+      <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
+      <configSetting altId="p102.spi0.rspck" configurationId="p102"/>
+      <configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
+      <configSetting altId="p103.spi0.ssl0" configurationId="p103"/>
+      <configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
+      <configSetting altId="p105.input" configurationId="p105"/>
+      <configSetting altId="p105.gpio_mode.gpio_mode_in" configurationId="p105.gpio_mode"/>
+      <configSetting altId="p105.gpio_pupd.gpio_pupd_ip_up" configurationId="p105.gpio_pupd"/>
+      <configSetting altId="p106.output.low" configurationId="p106"/>
+      <configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p115.ctsu0.ts35" configurationId="p115"/>
+      <configSetting altId="p115.gpio_mode.gpio_mode_peripheral" configurationId="p115.gpio_mode"/>
+      <configSetting altId="p205.ctsu0.tscap" configurationId="p205"/>
+      <configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+      <configSetting altId="p400.output.low" configurationId="p400"/>
+      <configSetting altId="p400.gpio_mode.gpio_mode_out.low" configurationId="p400.gpio_mode"/>
+      <configSetting altId="p401.sci1.txd" configurationId="p401"/>
+      <configSetting altId="p401.gpio_mode.gpio_mode_peripheral" configurationId="p401.gpio_mode"/>
+      <configSetting altId="p402.sci1.rxd" configurationId="p402"/>
+      <configSetting altId="p402.gpio_mode.gpio_mode_peripheral" configurationId="p402.gpio_mode"/>
+      <configSetting altId="p403.output.low" configurationId="p403"/>
+      <configSetting altId="p403.gpio_mode.gpio_mode_out.low" configurationId="p403.gpio_mode"/>
+      <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p914.usbfs0.usbdp" configurationId="p914"/>
+      <configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/>
+      <configSetting altId="p915.usbfs0.usbdm" configurationId="p915"/>
+      <configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/>
+      <configSetting altId="sci1.mode.asynchronous.free" configurationId="sci1.mode"/>
+      <configSetting altId="sci1.rxd.p402" configurationId="sci1.rxd"/>
+      <configSetting altId="sci1.txd.p401" configurationId="sci1.txd"/>
+      <configSetting altId="spi0.miso.p100" configurationId="spi0.miso"/>
+      <configSetting altId="spi0.mode.enabled.a" configurationId="spi0.mode"/>
+      <configSetting altId="spi0.mosi.p101" configurationId="spi0.mosi"/>
+      <configSetting altId="spi0.rspck.p102" configurationId="spi0.rspck"/>
+      <configSetting altId="spi0.ssl0.p103" configurationId="spi0.ssl0"/>
+      <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
+      <configSetting altId="usbfs0.usbdm.p915" configurationId="usbfs0.usbdm"/>
+      <configSetting altId="usbfs0.usbdp.p914" configurationId="usbfs0.usbdp"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
+    </pincfg>
+    <pincfg active="false" name="R7FA4M1AB3CFP.pincfg" selected="false" symbol="">
+      <configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
+      <configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
+      <configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
+      <configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
+      <configSetting altId="p108.debug0.tms" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p109.debug0.tdo" configurationId="p109"/>
+      <configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
+      <configSetting altId="p110.debug0.tdi" configurationId="p110"/>
+      <configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
+      <configSetting altId="p300.debug0.tck" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.cmake b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
new file mode 100644
index 000000000..b413abc36
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
@@ -0,0 +1,10 @@
+set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m3)
+
+set(JLINK_DEVICE R7FA4M3AF)
+
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC)
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h
new file mode 100644
index 000000000..8b277f6f0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.h
@@ -0,0 +1,58 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: RA4M3 EK
+   url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m3-evaluation-kit-ra4m3-mcu-group
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1 (BSP_IO_PORT_04_PIN_15)
+#define LED_STATE_ON          1
+
+#define SW1  (BSP_IO_PORT_00_PIN_05)
+#define BUTTON_STATE_ACTIVE   0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+  {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
+  {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
+    // USB FS
+  {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+  {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+  {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk
new file mode 100644
index 000000000..5987269b5
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = ra4m3
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M3AF
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..96087fa0d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define RA_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #ifndef BSP_CFG_RTC_USED
+             #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+            #endif
+            #undef RA_NOT_DEFINED
+            #if defined(_RA_BOOT_IMAGE)
+             #define BSP_CFG_BOOT_IMAGE (1)
+            #endif
+            #define BSP_CFG_MCU_VCC_MV (3300)
+            #define BSP_CFG_STACK_MAIN_BYTES (0x800)
+            #define BSP_CFG_HEAP_BYTES (0x800)
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PFS_PROTECT ((1))
+
+            #define BSP_CFG_C_RUNTIME_INIT ((1))
+            #define BSP_CFG_EARLY_INIT     ((0))
+
+            #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+            #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+            #endif
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+            #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+            #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+            #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+            #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..1aaa4be0a
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M3AF3CFB
+      #define BSP_MCU_FEATURE_SET ('A')
+      #define BSP_ROM_SIZE_BYTES (1048576)
+      #define BSP_RAM_SIZE_BYTES (131072)
+      #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+      #define BSP_PACKAGE_LQFP
+      #define BSP_PACKAGE_PINS (144)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..cb9429057
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,388 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+            #include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_MCU_GROUP_RA4M3 (1)
+            #define BSP_LOCO_HZ                 (32768)
+            #define BSP_MOCO_HZ                 (8000000)
+            #define BSP_SUB_CLOCK_HZ            (32768)
+            #if   BSP_CFG_HOCO_FREQUENCY == 0
+                #define BSP_HOCO_HZ                 (16000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 1
+                #define BSP_HOCO_HZ                 (18000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ                 (20000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+
+            #define BSP_CFG_FLL_ENABLE                 (0)
+
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
+            #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (1)
+
+            #if defined(_RA_TZ_SECURE)
+            #define BSP_TZ_SECURE_BUILD           (1)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #elif defined(_RA_TZ_NONSECURE)
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (1)
+            #else
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #endif
+
+            /* TrustZone Settings */
+            #define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+            #define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+            #define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
+
+            /* CMSIS TrustZone Settings */
+            #define SCB_CSR_AIRCR_INIT                (1)
+            #define SCB_AIRCR_BFHFNMINS_VAL           (0)
+            #define SCB_AIRCR_SYSRESETREQS_VAL        (1)
+            #define SCB_AIRCR_PRIS_VAL                (0)
+            #define TZ_FPU_NS_USAGE                   (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+            #define SCB_NSACR_CP10_11_VAL             (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+            #define FPU_FPCCR_TS_VAL                  (1U)
+#endif
+            #define FPU_FPCCR_CLRONRETS_VAL           (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+            #define FPU_FPCCR_CLRONRET_VAL            (1)
+#endif
+
+            /* The C-Cache line size that is configured during startup. */
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+            #define BSP_CFG_C_CACHE_LINE_SIZE   (1U)
+#endif
+
+            /* Type 1 Peripheral Security Attribution */
+
+            /* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+            0x33f4f9) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+            0x7fffcef4) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+            0xffae07f0) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+            0x3f3ff8) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+            0xfffffffc) /* Unused */
+#endif
+
+            /* Type 2 Peripheral Security Attribution */
+
+            /* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
+
+            /* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
+
+            /* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+            0xFFFFFFFCU)
+#endif
+
+            /* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
+            /* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
+
+            /* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+#endif
+
+            /* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
+
+            /* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+            0xFFFF0000U)
+#endif
+
+            /* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+            /* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+            0xFFFFFF00U)
+#endif
+
+            /* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
+#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
+
+            /* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
+
+            /* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
+
+            /* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+ #define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+            /* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+#endif
+
+            /* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+    #define BSP_TZ_CFG_SRAMSAR (\
+        1 | \
+        ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+        4 | \
+        0xFFFFFFF8U)
+#endif
+
+            /* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
+    #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
+
+            /* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+    /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+    #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
+
+            /* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+    #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
+            /* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+    #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
+
+            /* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+    #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+
+            #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+            #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+            #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+            #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+            #define OFS_SEQ5 (1 << 28) | (1 << 30)
+            #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+            /* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
+#else
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+#endif
+
+            #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (1 << 8))
+
+            /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+            #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+            /* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+            #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU)
+#endif
+
+            /* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+            #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+            /* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+            #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+            /* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+            #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
+#endif
+            /* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+            #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+            /* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+            #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+            #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+            #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
+#endif
+            /* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+            #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+            /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+            #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+            /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+            #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+            /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+            #define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU)
+#endif
+            /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+            #define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+            #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..8ed58a11b
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,67 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define ARDUINO_A0_MIKROBUS_AN (BSP_IO_PORT_00_PIN_00)
+#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01)
+#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_03)
+#define SW1 (BSP_IO_PORT_00_PIN_05)
+#define SW2 (BSP_IO_PORT_00_PIN_06)
+#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_07)
+#define PMOD1_INT (BSP_IO_PORT_00_PIN_08)
+#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14)
+#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15)
+#define ARDUINO_RX_MIKROBUS_RX (BSP_IO_PORT_01_PIN_00)
+#define ARDUINO_TX_MIKROBUS_TX (BSP_IO_PORT_01_PIN_01)
+#define ARDUINO_D2 (BSP_IO_PORT_01_PIN_05)
+#define ARDUINO_D3 (BSP_IO_PORT_01_PIN_11)
+#define MIKROBUS_RST (BSP_IO_PORT_01_PIN_15)
+#define ARDUINO_MISO_MIKROBUS_MISO_PMOD1_MISO (BSP_IO_PORT_02_PIN_02)
+#define ARDUINO_MOSI_MIKROBUS_MOSI_PMOD1_MOSI (BSP_IO_PORT_02_PIN_03)
+#define ARDUINO_CLK_MIKROBUS_CLK_PMOD1_CLK (BSP_IO_PORT_02_PIN_04)
+#define ARDUINO_SS_MIKCRBUS_SS (BSP_IO_PORT_02_PIN_05)
+#define PMOD1_SS1 (BSP_IO_PORT_02_PIN_06)
+#define PMOD1_SS2 (BSP_IO_PORT_02_PIN_07)
+#define PMOD1_SS3 (BSP_IO_PORT_03_PIN_02)
+#define ARDUINO_D9 (BSP_IO_PORT_03_PIN_03)
+#define ARDUINO_D7 (BSP_IO_PORT_03_PIN_04)
+#define QSPI_CLK (BSP_IO_PORT_03_PIN_05)
+#define QSPI_SSL (BSP_IO_PORT_03_PIN_06)
+#define QSPI_IO0 (BSP_IO_PORT_03_PIN_07)
+#define QSPI_IO1 (BSP_IO_PORT_03_PIN_08)
+#define QSPI_IO2 (BSP_IO_PORT_03_PIN_09)
+#define QSPI_IO3 (BSP_IO_PORT_03_PIN_10)
+#define PMOD1_RST (BSP_IO_PORT_03_PIN_11)
+#define LED3 (BSP_IO_PORT_04_PIN_00)
+#define LED2 (BSP_IO_PORT_04_PIN_04)
+#define USB_VBUS (BSP_IO_PORT_04_PIN_07)
+#define ARDUINO_D6_MIKROBUS_PWM (BSP_IO_PORT_04_PIN_08)
+#define MIKROBUS_INT (BSP_IO_PORT_04_PIN_09)
+#define PMOD2_INT (BSP_IO_PORT_04_PIN_14)
+#define LED1 (BSP_IO_PORT_04_PIN_15)
+#define USB_VBUS_EN (BSP_IO_PORT_05_PIN_00)
+#define USB_VBUS_OC (BSP_IO_PORT_05_PIN_01)
+#define GROVE2_AN1 (BSP_IO_PORT_05_PIN_05)
+#define GROVE2_AN2 (BSP_IO_PORT_05_PIN_06)
+#define GROVE1_SDA_QWIIC_SDA (BSP_IO_PORT_05_PIN_11)
+#define GROVE1_SCL_QWIIC_SCL (BSP_IO_PORT_05_PIN_12)
+#define ARDUINO_SCL_MIKROBUS_SCL (BSP_IO_PORT_06_PIN_01)
+#define ARDUINO_SDA_MIKROBUS_SDA (BSP_IO_PORT_06_PIN_02)
+#define ARDUINO_D8 (BSP_IO_PORT_06_PIN_11)
+#define ARDUINO_RST (BSP_IO_PORT_06_PIN_12)
+#define PMOD2_RST (BSP_IO_PORT_07_PIN_08)
+#define PMOD2_SS2 (BSP_IO_PORT_07_PIN_09)
+#define PMOD2_SS3 (BSP_IO_PORT_07_PIN_10)
+#define ARDUINO_D5 (BSP_IO_PORT_07_PIN_12)
+#define ARDUINO_D4 (BSP_IO_PORT_07_PIN_13)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M3 EK */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..d2688bf5b
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 000000000..3eac2985e
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,25 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c
new file mode 100644
index 000000000..50036c0ad
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h
new file mode 100644
index 000000000..6a08cbee0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c
new file mode 100644
index 000000000..bf30782cf
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c
@@ -0,0 +1,263 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_00_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_10,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_10,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_13,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+    }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld
new file mode 100644
index 000000000..605eef7d2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+                  Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                          FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END    = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START    = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START   = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                            FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                            __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                           FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                           FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+                XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+                FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+                       DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+                       FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+                            OPTION_SETTING_LENGTH == 0 ? 0 :
+                            OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+  ITCM (rx)                       : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+  DTCM (rwx)                      : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+  FLASH (rx)                      : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+  RAM (rwx)                       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx)                 : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx)                 : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx)              : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx)              : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  OSPI_DEVICE_0_RAM (rwx)         : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1_RAM (rwx)         : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)                     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r)              : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_OFS (r)          : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+  OPTION_SETTING_SAS (r)          : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+  OPTION_SETTING_S (r)            : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+  ID_CODE (rx)                    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* Some devices have a gap of code flash between the vector table and ROM Registers.
+         * The flash gap section allows applications to place code and data in this section. */
+        *(.flash_gap*)
+
+        /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+        /* Allocate flash write-boundary-aligned
+         * space for sce9 wrapped public keys for mcuboot if the module is used.
+         */
+        KEEP(*(.mcuboot_sce9_key*))
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    . = .;
+    __itcm_data_pre_location = .;
+
+    /* Initialized ITCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .itcm_data : ALIGN(16)
+    {
+        /* Start of ITCM Secure Trustzone region. */
+        __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+        /* All ITCM data start */
+        __itcm_data_start = .;
+
+        KEEP(*(.itcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* All ITCM data end */
+        __itcm_data_end = .;
+
+        /*
+         * Start of the ITCM Non-Secure Trustzone region.
+         * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+    } > ITCM AT > FLASH = 0x00
+
+    /* Addresses exported for ITCM initialization. */
+    __itcm_data_init_start = LOADADDR(.itcm_data);
+    __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+    ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+    /* Restore location counter. */
+    /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+    . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+    __exidx_start = .;
+    /DISCARD/ :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    }
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    . = .;
+    __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+    /* Initialized DTCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .dtcm_data : ALIGN(16)
+    {
+        /* Start of DTCM Secure Trustzone region. */
+        __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+        /* Initialized DTCM data start */
+        __dtcm_data_start = .;
+
+        KEEP(*(.dtcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* Initialized DTCM data end */
+        __dtcm_data_end = .;
+    } > DTCM AT > FLASH = 0x00
+
+    . = __dtcm_data_end;
+    /* Uninitialized DTCM data. */
+    /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+    .dtcm_bss ALIGN(8) (NOLOAD) :
+    {
+        /* Uninitialized DTCM data start */
+        __dtcm_bss_start = .;
+
+        KEEP(*(.dtcm_bss*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+        . = ALIGN(8);
+
+        /* Uninitialized DTCM data end */
+        __dtcm_bss_end = .;
+
+        /*
+         * Start of the DTCM Non-Secure Trustzone region.
+         * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+         */
+        __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+    } > DTCM
+
+    /* Addresses exported for DTCM initialization. */
+    __dtcm_data_init_start = LOADADDR(.dtcm_data);
+    __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+    ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+    ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+    ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+    ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+    /* Restore location counter. */
+    /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+    . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+    /* TrustZone Secure Gateway Stubs Section */
+
+    /* Store location counter for SPI non-retentive sections. */
+    sgstubs_pre_location = .;
+
+    /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+    SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+    .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+    {
+        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+    FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = sgstubs_pre_location;
+    .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Support for OctaRAM */
+    .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_0_start__ = .;
+        *(.ospi_device_0_no_load*)
+        . = ALIGN(4);
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0_RAM
+
+    .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_1_start__ = .;
+        *(.ospi_device_1_no_load*)
+        . = ALIGN(4);
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1_RAM
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+     __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+    .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+    .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool.
+     *       Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+     *       memory region between TrustZone projects. */
+    __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+    .option_setting_ofs :
+    {
+        __OPTION_SETTING_OFS_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_ofs2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_dualsel))
+        __OPTION_SETTING_OFS_End = .;
+    } > OPTION_SETTING_OFS = 0xFF
+
+    .option_setting_sas :
+    {
+        __OPTION_SETTING_SAS_Start = .;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_SAS_End = .;
+    } > OPTION_SETTING_SAS = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_ofs3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps3))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel3))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld
new file mode 100644
index 000000000..04d7de497
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+            /* generated memory regions file - do not edit */
+                            RAM_START  = 0x20000000;
+                RAM_LENGTH = 0x20000;
+                FLASH_START  = 0x00000000;
+                FLASH_LENGTH = 0x100000;
+                DATA_FLASH_START  = 0x08000000;
+                DATA_FLASH_LENGTH = 0x2000;
+                OPTION_SETTING_START  = 0x0100A100;
+                OPTION_SETTING_LENGTH = 0x100;
+                OPTION_SETTING_S_START  = 0x0100A200;
+                OPTION_SETTING_S_LENGTH = 0x100;
+                ID_CODE_START  = 0x00000000;
+                ID_CODE_LENGTH = 0x0;
+                SDRAM_START  = 0x80010000;
+                SDRAM_LENGTH = 0x0;
+                QSPI_FLASH_START  = 0x60000000;
+                QSPI_FLASH_LENGTH = 0x4000000;
+                OSPI_DEVICE_0_START  = 0x80020000;
+                OSPI_DEVICE_0_LENGTH = 0x0;
+                OSPI_DEVICE_1_START  = 0x80030000;
+                OSPI_DEVICE_1_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml
new file mode 100644
index 000000000..1d75f1b72
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml
@@ -0,0 +1,432 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.ra4m3ek"/>
+    <option key="CPU" value="RA4M3"/>
+    <option key="Core" value="CM33"/>
+    <option key="#TargetName#" value="R7FA4M3AF3CFB"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m33"/>
+    <option key="#DeviceCommand#" value="R7FA4M3AF"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA4M3AF3CFB.pincfg"/>
+    <option key="#FSPVersion#" value="5.6.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra4m3_ek##"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra4m3.R7FA4M3AF3CFB">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="1048576"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.irq_count_hidden" value="96"/>
+    </config>
+    <config id="config.bsp.ra4m3">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra4m3.fsp">
+      <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
+      <property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
+      <property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
+      <property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
+      <property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
+      <property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/>
+      <property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
+      <property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/>
+      <property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/>
+      <property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/>
+      <property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/>
+      <property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
+      <property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
+      <property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/>
+      <property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
+      <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
+      <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/>
+      <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
+      <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
+      <property id="config.bsp.fsp.BPS.BPS0" value=""/>
+      <property id="config.bsp.fsp.BPS.BPS1" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
+      <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="16666666"/>
+      <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x1"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x1"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0219"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
+      <property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="32767"/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x800"/>
+      <property id="config.bsp.common.heap" value="0x800"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
+    <node id="board.clock.pll.div" option="board.clock.pll.div.3"/>
+    <node id="board.clock.pll.mul" option="board.clock.pll.mul.250"/>
+    <node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
+    <node id="board.clock.pll2.source" option="board.clock.pll2.source.xtal"/>
+    <node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
+    <node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/>
+    <node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.uclk.source" option="board.clock.uclk.source.pll2"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
+    <node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
+    <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+    <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0">
+      <description>Simple application that blinks an LED. No RTOS included.</description>
+      <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
+      <description>Arm CMSIS Version 6 - Core (M)</description>
+      <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m3" subgroup="device" variant="R7FA4M3AF3CFB" vendor="Renesas" version="5.6.0">
+      <description>Board support package for R7FA4M3AF3CFB</description>
+      <originalPack>Renesas.RA_mcu_ra4m3.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m3" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA4M3</description>
+      <originalPack>Renesas.RA_mcu_ra4m3.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m3" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA4M3 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra4m3.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m3" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA4M3 - Events</description>
+      <originalPack>Renesas.RA_mcu_ra4m3.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra4m3_ek" variant="" vendor="Renesas" version="5.6.0">
+      <description>RA4M3-EK Board Support Files</description>
+      <originalPack>Renesas.RA_board_ra4m3_ek.5.6.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+    </context>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p000.symbolic_name" value="ARDUINO_A0_MIKROBUS_AN"/>
+    <symbolicName propertyId="p001.symbolic_name" value="ARDUINO_A1"/>
+    <symbolicName propertyId="p003.symbolic_name" value="ARDUINO_A2"/>
+    <symbolicName propertyId="p005.symbolic_name" value="SW1"/>
+    <symbolicName propertyId="p006.symbolic_name" value="SW2"/>
+    <symbolicName propertyId="p007.symbolic_name" value="ARDUINO_A3"/>
+    <symbolicName propertyId="p008.symbolic_name" value="PMOD1_INT"/>
+    <symbolicName propertyId="p014.symbolic_name" value="ARDUINO_A4"/>
+    <symbolicName propertyId="p015.symbolic_name" value="ARDUINO_A5"/>
+    <symbolicName propertyId="p100.symbolic_name" value="ARDUINO_RX_MIKROBUS_RX"/>
+    <symbolicName propertyId="p101.symbolic_name" value="ARDUINO_TX_MIKROBUS_TX"/>
+    <symbolicName propertyId="p105.symbolic_name" value="ARDUINO_D2"/>
+    <symbolicName propertyId="p111.symbolic_name" value="ARDUINO_D3"/>
+    <symbolicName propertyId="p115.symbolic_name" value="MIKROBUS_RST"/>
+    <symbolicName propertyId="p202.symbolic_name" value="ARDUINO_MISO_MIKROBUS_MISO_PMOD1_MISO"/>
+    <symbolicName propertyId="p203.symbolic_name" value="ARDUINO_MOSI_MIKROBUS_MOSI_PMOD1_MOSI"/>
+    <symbolicName propertyId="p204.symbolic_name" value="ARDUINO_CLK_MIKROBUS_CLK_PMOD1_CLK"/>
+    <symbolicName propertyId="p205.symbolic_name" value="ARDUINO_SS_MIKCRBUS_SS"/>
+    <symbolicName propertyId="p206.symbolic_name" value="PMOD1_SS1"/>
+    <symbolicName propertyId="p207.symbolic_name" value="PMOD1_SS2"/>
+    <symbolicName propertyId="p302.symbolic_name" value="PMOD1_SS3"/>
+    <symbolicName propertyId="p303.symbolic_name" value="ARDUINO_D9"/>
+    <symbolicName propertyId="p304.symbolic_name" value="ARDUINO_D7"/>
+    <symbolicName propertyId="p305.symbolic_name" value="QSPI_CLK"/>
+    <symbolicName propertyId="p306.symbolic_name" value="QSPI_SSL"/>
+    <symbolicName propertyId="p307.symbolic_name" value="QSPI_IO0"/>
+    <symbolicName propertyId="p308.symbolic_name" value="QSPI_IO1"/>
+    <symbolicName propertyId="p309.symbolic_name" value="QSPI_IO2"/>
+    <symbolicName propertyId="p310.symbolic_name" value="QSPI_IO3"/>
+    <symbolicName propertyId="p311.symbolic_name" value="PMOD1_RST"/>
+    <symbolicName propertyId="p400.symbolic_name" value="LED3"/>
+    <symbolicName propertyId="p404.symbolic_name" value="LED2"/>
+    <symbolicName propertyId="p407.symbolic_name" value="USB_VBUS"/>
+    <symbolicName propertyId="p408.symbolic_name" value="ARDUINO_D6_MIKROBUS_PWM"/>
+    <symbolicName propertyId="p409.symbolic_name" value="MIKROBUS_INT"/>
+    <symbolicName propertyId="p414.symbolic_name" value="PMOD2_INT"/>
+    <symbolicName propertyId="p415.symbolic_name" value="LED1"/>
+    <symbolicName propertyId="p500.symbolic_name" value="USB_VBUS_EN"/>
+    <symbolicName propertyId="p501.symbolic_name" value="USB_VBUS_OC"/>
+    <symbolicName propertyId="p505.symbolic_name" value="GROVE2_AN1"/>
+    <symbolicName propertyId="p506.symbolic_name" value="GROVE2_AN2"/>
+    <symbolicName propertyId="p511.symbolic_name" value="GROVE1_SDA_QWIIC_SDA"/>
+    <symbolicName propertyId="p512.symbolic_name" value="GROVE1_SCL_QWIIC_SCL"/>
+    <symbolicName propertyId="p601.symbolic_name" value="ARDUINO_SCL_MIKROBUS_SCL"/>
+    <symbolicName propertyId="p602.symbolic_name" value="ARDUINO_SDA_MIKROBUS_SDA"/>
+    <symbolicName propertyId="p611.symbolic_name" value="ARDUINO_D8"/>
+    <symbolicName propertyId="p612.symbolic_name" value="ARDUINO_RST"/>
+    <symbolicName propertyId="p708.symbolic_name" value="PMOD2_RST"/>
+    <symbolicName propertyId="p709.symbolic_name" value="PMOD2_SS2"/>
+    <symbolicName propertyId="p710.symbolic_name" value="PMOD2_SS3"/>
+    <symbolicName propertyId="p712.symbolic_name" value="ARDUINO_D5"/>
+    <symbolicName propertyId="p713.symbolic_name" value="ARDUINO_D4"/>
+    <pincfg active="true" name="RA4M3 EK" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="adc0.an00.p000" configurationId="adc0.an00"/>
+      <configSetting altId="adc0.an01.p001" configurationId="adc0.an01"/>
+      <configSetting altId="adc0.an03.p003" configurationId="adc0.an03"/>
+      <configSetting altId="adc0.an07.p007" configurationId="adc0.an07"/>
+      <configSetting altId="adc0.an12.p014" configurationId="adc0.an12"/>
+      <configSetting altId="adc0.an13.p015" configurationId="adc0.an13"/>
+      <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
+      <configSetting altId="adc1.an21.p505" configurationId="adc1.an21"/>
+      <configSetting altId="adc1.an22.p506" configurationId="adc1.an22"/>
+      <configSetting altId="adc1.mode.custom" configurationId="adc1.mode"/>
+      <configSetting altId="cgc0.extal.p212" configurationId="cgc0.extal"/>
+      <configSetting altId="cgc0.mode.mainsub" configurationId="cgc0.mode"/>
+      <configSetting altId="cgc0.xtal.p213" configurationId="cgc0.xtal"/>
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="gpt6.gtiocb.p408" configurationId="gpt6.gtiocb"/>
+      <configSetting altId="gpt6.mode.gtiocaorgtiocb.free" configurationId="gpt6.mode"/>
+      <configSetting altId="iic1.mode.enabled.a" configurationId="iic1.mode"/>
+      <configSetting altId="iic1.scl.p512" configurationId="iic1.scl"/>
+      <configSetting altId="iic1.sda.p511" configurationId="iic1.sda"/>
+      <configSetting altId="p000.asel" configurationId="p000"/>
+      <configSetting altId="p000.gpio_mode.gpio_mode_an" configurationId="p000.gpio_mode"/>
+      <configSetting altId="p001.asel" configurationId="p001"/>
+      <configSetting altId="p001.gpio_mode.gpio_mode_an" configurationId="p001.gpio_mode"/>
+      <configSetting altId="p003.asel" configurationId="p003"/>
+      <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
+      <configSetting altId="p005.input" configurationId="p005"/>
+      <configSetting altId="p005.gpio_mode.gpio_mode_in" configurationId="p005.gpio_mode"/>
+      <configSetting altId="p006.input" configurationId="p006"/>
+      <configSetting altId="p006.gpio_irq.gpio_irq_enabled" configurationId="p006.gpio_irq"/>
+      <configSetting altId="p006.gpio_mode.gpio_mode_in" configurationId="p006.gpio_mode"/>
+      <configSetting altId="p007.asel" configurationId="p007"/>
+      <configSetting altId="p007.gpio_mode.gpio_mode_an" configurationId="p007.gpio_mode"/>
+      <configSetting altId="p008.input" configurationId="p008"/>
+      <configSetting altId="p008.gpio_irq.gpio_irq_enabled" configurationId="p008.gpio_irq"/>
+      <configSetting altId="p008.gpio_mode.gpio_mode_in" configurationId="p008.gpio_mode"/>
+      <configSetting altId="p008.gpio_pupd.gpio_pupd_ip_up" configurationId="p008.gpio_pupd"/>
+      <configSetting altId="p014.asel" configurationId="p014"/>
+      <configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/>
+      <configSetting altId="p015.asel" configurationId="p015"/>
+      <configSetting altId="p015.gpio_mode.gpio_mode_an" configurationId="p015.gpio_mode"/>
+      <configSetting altId="p100.sci0.rxd" configurationId="p100"/>
+      <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
+      <configSetting altId="p101.sci0.txd" configurationId="p101"/>
+      <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
+      <configSetting altId="p105.output.low" configurationId="p105"/>
+      <configSetting altId="p105.gpio_mode.gpio_mode_out.low" configurationId="p105.gpio_mode"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p111.output.low" configurationId="p111"/>
+      <configSetting altId="p111.gpio_mode.gpio_mode_out.low" configurationId="p111.gpio_mode"/>
+      <configSetting altId="p115.output.low" configurationId="p115"/>
+      <configSetting altId="p115.gpio_mode.gpio_mode_out.low" configurationId="p115.gpio_mode"/>
+      <configSetting altId="p202.spi0.miso" configurationId="p202"/>
+      <configSetting altId="p202.gpio_mode.gpio_mode_peripheral" configurationId="p202.gpio_mode"/>
+      <configSetting altId="p203.spi0.mosi" configurationId="p203"/>
+      <configSetting altId="p203.gpio_mode.gpio_mode_peripheral" configurationId="p203.gpio_mode"/>
+      <configSetting altId="p204.spi0.rspck" configurationId="p204"/>
+      <configSetting altId="p204.gpio_mode.gpio_mode_peripheral" configurationId="p204.gpio_mode"/>
+      <configSetting altId="p205.spi0.ssl0" configurationId="p205"/>
+      <configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/>
+      <configSetting altId="p206.spi0.ssl1" configurationId="p206"/>
+      <configSetting altId="p206.gpio_mode.gpio_mode_peripheral" configurationId="p206.gpio_mode"/>
+      <configSetting altId="p207.spi0.ssl2" configurationId="p207"/>
+      <configSetting altId="p207.gpio_mode.gpio_mode_peripheral" configurationId="p207.gpio_mode"/>
+      <configSetting altId="p212.cgc0.extal" configurationId="p212"/>
+      <configSetting altId="p212.gpio_mode.gpio_mode_peripheral" configurationId="p212.gpio_mode"/>
+      <configSetting altId="p213.cgc0.xtal" configurationId="p213"/>
+      <configSetting altId="p213.gpio_mode.gpio_mode_peripheral" configurationId="p213.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+      <configSetting altId="p302.spi0.ssl3" configurationId="p302"/>
+      <configSetting altId="p302.gpio_mode.gpio_mode_peripheral" configurationId="p302.gpio_mode"/>
+      <configSetting altId="p303.output.low" configurationId="p303"/>
+      <configSetting altId="p303.gpio_mode.gpio_mode_out.low" configurationId="p303.gpio_mode"/>
+      <configSetting altId="p304.output.low" configurationId="p304"/>
+      <configSetting altId="p304.gpio_mode.gpio_mode_out.low" configurationId="p304.gpio_mode"/>
+      <configSetting altId="p305.qspi0.qspclk" configurationId="p305"/>
+      <configSetting altId="p305.gpio_mode.gpio_mode_peripheral" configurationId="p305.gpio_mode"/>
+      <configSetting altId="p306.qspi0.qssl" configurationId="p306"/>
+      <configSetting altId="p306.gpio_mode.gpio_mode_peripheral" configurationId="p306.gpio_mode"/>
+      <configSetting altId="p307.qspi0.qio0" configurationId="p307"/>
+      <configSetting altId="p307.gpio_mode.gpio_mode_peripheral" configurationId="p307.gpio_mode"/>
+      <configSetting altId="p308.qspi0.qio1" configurationId="p308"/>
+      <configSetting altId="p308.gpio_mode.gpio_mode_peripheral" configurationId="p308.gpio_mode"/>
+      <configSetting altId="p309.qspi0.qio2" configurationId="p309"/>
+      <configSetting altId="p309.gpio_mode.gpio_mode_peripheral" configurationId="p309.gpio_mode"/>
+      <configSetting altId="p310.qspi0.qio3" configurationId="p310"/>
+      <configSetting altId="p310.gpio_mode.gpio_mode_peripheral" configurationId="p310.gpio_mode"/>
+      <configSetting altId="p311.output.low" configurationId="p311"/>
+      <configSetting altId="p311.gpio_mode.gpio_mode_out.low" configurationId="p311.gpio_mode"/>
+      <configSetting altId="p400.output.low" configurationId="p400"/>
+      <configSetting altId="p400.gpio_mode.gpio_mode_out.low" configurationId="p400.gpio_mode"/>
+      <configSetting altId="p404.output.low" configurationId="p404"/>
+      <configSetting altId="p404.gpio_mode.gpio_mode_out.low" configurationId="p404.gpio_mode"/>
+      <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p408.gpt6.gtiocb" configurationId="p408"/>
+      <configSetting altId="p408.gpio_mode.gpio_mode_peripheral" configurationId="p408.gpio_mode"/>
+      <configSetting altId="p409.input" configurationId="p409"/>
+      <configSetting altId="p409.gpio_irq.gpio_irq_enabled" configurationId="p409.gpio_irq"/>
+      <configSetting altId="p409.gpio_mode.gpio_mode_in" configurationId="p409.gpio_mode"/>
+      <configSetting altId="p409.gpio_pupd.gpio_pupd_ip_up" configurationId="p409.gpio_pupd"/>
+      <configSetting altId="p414.input" configurationId="p414"/>
+      <configSetting altId="p414.gpio_irq.gpio_irq_enabled" configurationId="p414.gpio_irq"/>
+      <configSetting altId="p414.gpio_mode.gpio_mode_in" configurationId="p414.gpio_mode"/>
+      <configSetting altId="p414.gpio_pupd.gpio_pupd_ip_up" configurationId="p414.gpio_pupd"/>
+      <configSetting altId="p415.output.low" configurationId="p415"/>
+      <configSetting altId="p415.gpio_mode.gpio_mode_out.low" configurationId="p415.gpio_mode"/>
+      <configSetting altId="p500.usbfs0.vbusen" configurationId="p500"/>
+      <configSetting altId="p500.gpio_mode.gpio_mode_peripheral" configurationId="p500.gpio_mode"/>
+      <configSetting altId="p501.usbfs0.ovrcura" configurationId="p501"/>
+      <configSetting altId="p501.gpio_mode.gpio_mode_peripheral" configurationId="p501.gpio_mode"/>
+      <configSetting altId="p505.asel" configurationId="p505"/>
+      <configSetting altId="p505.gpio_mode.gpio_mode_an" configurationId="p505.gpio_mode"/>
+      <configSetting altId="p506.asel" configurationId="p506"/>
+      <configSetting altId="p506.gpio_mode.gpio_mode_an" configurationId="p506.gpio_mode"/>
+      <configSetting altId="p511.iic1.sda" configurationId="p511"/>
+      <configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/>
+      <configSetting altId="p512.iic1.scl" configurationId="p512"/>
+      <configSetting altId="p512.gpio_mode.gpio_mode_peripheral" configurationId="p512.gpio_mode"/>
+      <configSetting altId="p601.sci9.scl" configurationId="p601"/>
+      <configSetting altId="p601.gpio_mode.gpio_mode_peripheral" configurationId="p601.gpio_mode"/>
+      <configSetting altId="p601.gpio_otype.gpio_otype_n_ch_od" configurationId="p601.gpio_otype"/>
+      <configSetting altId="p602.sci9.sda" configurationId="p602"/>
+      <configSetting altId="p602.gpio_mode.gpio_mode_peripheral" configurationId="p602.gpio_mode"/>
+      <configSetting altId="p602.gpio_otype.gpio_otype_n_ch_od" configurationId="p602.gpio_otype"/>
+      <configSetting altId="p611.output.low" configurationId="p611"/>
+      <configSetting altId="p611.gpio_mode.gpio_mode_out.low" configurationId="p611.gpio_mode"/>
+      <configSetting altId="p612.output.low" configurationId="p612"/>
+      <configSetting altId="p612.gpio_mode.gpio_mode_out.low" configurationId="p612.gpio_mode"/>
+      <configSetting altId="p708.output.low" configurationId="p708"/>
+      <configSetting altId="p708.gpio_mode.gpio_mode_out.low" configurationId="p708.gpio_mode"/>
+      <configSetting altId="p709.output.low" configurationId="p709"/>
+      <configSetting altId="p709.gpio_mode.gpio_mode_out.low" configurationId="p709.gpio_mode"/>
+      <configSetting altId="p710.output.low" configurationId="p710"/>
+      <configSetting altId="p710.gpio_mode.gpio_mode_out.low" configurationId="p710.gpio_mode"/>
+      <configSetting altId="p712.output.low" configurationId="p712"/>
+      <configSetting altId="p712.gpio_mode.gpio_mode_out.low" configurationId="p712.gpio_mode"/>
+      <configSetting altId="p713.output.low" configurationId="p713"/>
+      <configSetting altId="p713.gpio_mode.gpio_mode_out.low" configurationId="p713.gpio_mode"/>
+      <configSetting altId="qspi0.mode.quad.b" configurationId="qspi0.mode"/>
+      <configSetting altId="qspi0.pairing.b" configurationId="qspi0.pairing"/>
+      <configSetting altId="qspi0.qio0.p307" configurationId="qspi0.qio0"/>
+      <configSetting altId="qspi0.qio1.p308" configurationId="qspi0.qio1"/>
+      <configSetting altId="qspi0.qio2.p309" configurationId="qspi0.qio2"/>
+      <configSetting altId="qspi0.qio3.p310" configurationId="qspi0.qio3"/>
+      <configSetting altId="qspi0.qspclk.p305" configurationId="qspi0.qspclk"/>
+      <configSetting altId="qspi0.qssl.p306" configurationId="qspi0.qssl"/>
+      <configSetting altId="sci0.mode.asynchronous.free" configurationId="sci0.mode"/>
+      <configSetting altId="sci0.rxd.p100" configurationId="sci0.rxd"/>
+      <configSetting altId="sci0.txd.p101" configurationId="sci0.txd"/>
+      <configSetting altId="sci9.mode.iic.free" configurationId="sci9.mode"/>
+      <configSetting altId="sci9.scl.p601" configurationId="sci9.scl"/>
+      <configSetting altId="sci9.sda.p602" configurationId="sci9.sda"/>
+      <configSetting altId="spi0.miso.p202" configurationId="spi0.miso"/>
+      <configSetting altId="spi0.mode.enabled.free" configurationId="spi0.mode"/>
+      <configSetting altId="spi0.mosi.p203" configurationId="spi0.mosi"/>
+      <configSetting altId="spi0.pairing.free" configurationId="spi0.pairing"/>
+      <configSetting altId="spi0.rspck.p204" configurationId="spi0.rspck"/>
+      <configSetting altId="spi0.ssl0.p205" configurationId="spi0.ssl0"/>
+      <configSetting altId="spi0.ssl1.p206" configurationId="spi0.ssl1"/>
+      <configSetting altId="spi0.ssl2.p207" configurationId="spi0.ssl2"/>
+      <configSetting altId="spi0.ssl3.p302" configurationId="spi0.ssl3"/>
+      <configSetting altId="usbfs0.mode.custom" configurationId="usbfs0.mode"/>
+      <configSetting altId="usbfs0.ovrcura.p501" configurationId="usbfs0.ovrcura"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
+      <configSetting altId="usbfs0.vbusen.p500" configurationId="usbfs0.vbusen"/>
+    </pincfg>
+    <pincfg active="false" name="R7FA4M3AF3CFB.pincfg" selected="false" symbol="">
+      <configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
+      <configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
+      <configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
+      <configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
+      <configSetting altId="p108.debug0.tms" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p109.debug0.tdo" configurationId="p109"/>
+      <configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
+      <configSetting altId="p110.debug0.tdi" configurationId="p110"/>
+      <configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
+      <configSetting altId="p300.debug0.tck" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.cmake b/hw/bsp/ra/boards/ra6m1_ek/board.cmake
new file mode 100644
index 000000000..957e8394d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.cmake
@@ -0,0 +1,10 @@
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra6m1)
+
+set(JLINK_DEVICE R7FA6M1AD)
+
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC)
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h
new file mode 100644
index 000000000..2024a0335
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.h
@@ -0,0 +1,46 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: RA6M1 EK
+   url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_STATE_ON          1
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.mk b/hw/bsp/ra/boards/ra6m1_ek/board.mk
new file mode 100644
index 000000000..f06b693d8
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m4
+MCU_VARIANT = ra6m1
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA6M1AD
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..90afbdef3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define RA_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #ifndef BSP_CFG_RTC_USED
+             #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+            #endif
+            #undef RA_NOT_DEFINED
+            #if defined(_RA_BOOT_IMAGE)
+             #define BSP_CFG_BOOT_IMAGE (1)
+            #endif
+            #define BSP_CFG_MCU_VCC_MV (3300)
+            #define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+            #define BSP_CFG_HEAP_BYTES (0x1000)
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PFS_PROTECT ((1))
+
+            #define BSP_CFG_C_RUNTIME_INIT ((1))
+            #define BSP_CFG_EARLY_INIT     ((0))
+
+            #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+            #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+            #endif
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+            #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+            #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+            #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+            #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..bd6a901c3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..5e7841442
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M1AD3CFP
+      #define BSP_MCU_FEATURE_SET ('A')
+      #define BSP_ROM_SIZE_BYTES (524288)
+      #define BSP_RAM_SIZE_BYTES (262144)
+      #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+      #define BSP_PACKAGE_LQFP
+      #define BSP_PACKAGE_PINS (100)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..16349b5ff
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,84 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_MCU_GROUP_RA6M1 (1)
+            #define BSP_LOCO_HZ                 (32768)
+            #define BSP_MOCO_HZ                 (8000000)
+            #define BSP_SUB_CLOCK_HZ            (32768)
+            #if   BSP_CFG_HOCO_FREQUENCY == 0
+                #define BSP_HOCO_HZ                 (16000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 1
+                #define BSP_HOCO_HZ                 (18000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ                 (20000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+
+            #define BSP_CFG_FLL_ENABLE                 (0)
+
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
+            #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (1)
+
+            #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+            #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+            #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+            #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+            #define OFS_SEQ5 (1 << 28) | (1 << 30)
+            #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+            #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (1 << 8))
+            #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+            #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+            #endif
+            /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+            #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+            /*
+            ID Code
+            Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
+            WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
+            */
+            #if defined(BSP_ID_CODE_LOCKED)
+            #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+            #else
+            /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+            #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..8ba9aafba
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define LED1 (BSP_IO_PORT_01_PIN_12)
+#define SW1 (BSP_IO_PORT_04_PIN_15)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..d2688bf5b
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 000000000..945a6010b
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,23 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c
new file mode 100644
index 000000000..50036c0ad
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h
new file mode 100644
index 000000000..6a08cbee0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c
new file mode 100644
index 000000000..80774b0a5
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c
@@ -0,0 +1,115 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_00_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+    }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld
new file mode 100644
index 000000000..605eef7d2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+                  Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                          FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END    = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START    = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START   = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                            FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                            __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                           FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                           FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+                XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+                FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+                       DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+                       FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+                            OPTION_SETTING_LENGTH == 0 ? 0 :
+                            OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+  ITCM (rx)                       : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+  DTCM (rwx)                      : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+  FLASH (rx)                      : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+  RAM (rwx)                       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx)                 : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx)                 : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx)              : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx)              : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  OSPI_DEVICE_0_RAM (rwx)         : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1_RAM (rwx)         : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)                     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r)              : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_OFS (r)          : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+  OPTION_SETTING_SAS (r)          : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+  OPTION_SETTING_S (r)            : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+  ID_CODE (rx)                    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* Some devices have a gap of code flash between the vector table and ROM Registers.
+         * The flash gap section allows applications to place code and data in this section. */
+        *(.flash_gap*)
+
+        /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+        /* Allocate flash write-boundary-aligned
+         * space for sce9 wrapped public keys for mcuboot if the module is used.
+         */
+        KEEP(*(.mcuboot_sce9_key*))
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    . = .;
+    __itcm_data_pre_location = .;
+
+    /* Initialized ITCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .itcm_data : ALIGN(16)
+    {
+        /* Start of ITCM Secure Trustzone region. */
+        __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+        /* All ITCM data start */
+        __itcm_data_start = .;
+
+        KEEP(*(.itcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* All ITCM data end */
+        __itcm_data_end = .;
+
+        /*
+         * Start of the ITCM Non-Secure Trustzone region.
+         * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+    } > ITCM AT > FLASH = 0x00
+
+    /* Addresses exported for ITCM initialization. */
+    __itcm_data_init_start = LOADADDR(.itcm_data);
+    __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+    ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+    /* Restore location counter. */
+    /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+    . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+    __exidx_start = .;
+    /DISCARD/ :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    }
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    . = .;
+    __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+    /* Initialized DTCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .dtcm_data : ALIGN(16)
+    {
+        /* Start of DTCM Secure Trustzone region. */
+        __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+        /* Initialized DTCM data start */
+        __dtcm_data_start = .;
+
+        KEEP(*(.dtcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* Initialized DTCM data end */
+        __dtcm_data_end = .;
+    } > DTCM AT > FLASH = 0x00
+
+    . = __dtcm_data_end;
+    /* Uninitialized DTCM data. */
+    /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+    .dtcm_bss ALIGN(8) (NOLOAD) :
+    {
+        /* Uninitialized DTCM data start */
+        __dtcm_bss_start = .;
+
+        KEEP(*(.dtcm_bss*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+        . = ALIGN(8);
+
+        /* Uninitialized DTCM data end */
+        __dtcm_bss_end = .;
+
+        /*
+         * Start of the DTCM Non-Secure Trustzone region.
+         * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+         */
+        __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+    } > DTCM
+
+    /* Addresses exported for DTCM initialization. */
+    __dtcm_data_init_start = LOADADDR(.dtcm_data);
+    __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+    ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+    ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+    ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+    ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+    /* Restore location counter. */
+    /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+    . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+    /* TrustZone Secure Gateway Stubs Section */
+
+    /* Store location counter for SPI non-retentive sections. */
+    sgstubs_pre_location = .;
+
+    /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+    SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+    .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+    {
+        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+    FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = sgstubs_pre_location;
+    .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Support for OctaRAM */
+    .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_0_start__ = .;
+        *(.ospi_device_0_no_load*)
+        . = ALIGN(4);
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0_RAM
+
+    .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_1_start__ = .;
+        *(.ospi_device_1_no_load*)
+        . = ALIGN(4);
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1_RAM
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+     __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+    .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+    .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool.
+     *       Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+     *       memory region between TrustZone projects. */
+    __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+    .option_setting_ofs :
+    {
+        __OPTION_SETTING_OFS_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_ofs2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_dualsel))
+        __OPTION_SETTING_OFS_End = .;
+    } > OPTION_SETTING_OFS = 0xFF
+
+    .option_setting_sas :
+    {
+        __OPTION_SETTING_SAS_Start = .;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_SAS_End = .;
+    } > OPTION_SETTING_SAS = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_ofs3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps3))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel3))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld
new file mode 100644
index 000000000..9d973c737
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+            /* generated memory regions file - do not edit */
+                            RAM_START  = 0x1FFE0000;
+                RAM_LENGTH = 0x40000;
+                FLASH_START  = 0x00000000;
+                FLASH_LENGTH = 0x80000;
+                DATA_FLASH_START  = 0x40100000;
+                DATA_FLASH_LENGTH = 0x2000;
+                OPTION_SETTING_START  = 0x00000000;
+                OPTION_SETTING_LENGTH = 0x0;
+                OPTION_SETTING_S_START  = 0x80000000;
+                OPTION_SETTING_S_LENGTH = 0x0;
+                ID_CODE_START  = 0x0100A150;
+                ID_CODE_LENGTH = 0x10;
+                SDRAM_START  = 0x80010000;
+                SDRAM_LENGTH = 0x0;
+                QSPI_FLASH_START  = 0x60000000;
+                QSPI_FLASH_LENGTH = 0x4000000;
+                OSPI_DEVICE_0_START  = 0x80020000;
+                OSPI_DEVICE_0_LENGTH = 0x0;
+                OSPI_DEVICE_1_START  = 0x80030000;
+                OSPI_DEVICE_1_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml
new file mode 100644
index 000000000..4c5d77ed0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml
@@ -0,0 +1,270 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.ra6m1ek"/>
+    <option key="CPU" value="RA6M1"/>
+    <option key="Core" value="CM4"/>
+    <option key="#TargetName#" value="R7FA6M1AD3CFP"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m4"/>
+    <option key="#DeviceCommand#" value="R7FA6M1AD"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA6M1AD3CFP.pincfg"/>
+    <option key="#FSPVersion#" value="5.6.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra6m1_ek##"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra6m1.R7FA6M1AD3CFP">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="524288"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.irq_count_hidden" value="96"/>
+    </config>
+    <config id="config.bsp.ra6m1">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra6m1.fsp">
+      <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
+      <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
+      <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
+      <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_start" value="0xFFFFFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc0_end" value="0xFFFFFFFF"/>
+      <property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc1_start" value="0xFFFFFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc1_end" value="0xFFFFFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg0_start" value="0x00FFFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg0_end" value="0x00FFFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
+      <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="60000000"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="20000000"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="1"/>
+      <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="30000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="30000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x1"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x1"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
+      <property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
+      <property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
+      <property id="config.bsp.common.id1" value=""/>
+      <property id="config.bsp.common.id2" value=""/>
+      <property id="config.bsp.common.id3" value=""/>
+      <property id="config.bsp.common.id4" value=""/>
+      <property id="config.bsp.common.id_fixed" value=""/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x1000"/>
+      <property id="config.bsp.common.heap" value="0x1000"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="12000000" option="_edit"/>
+    <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.pll.div" option="board.clock.pll.div.1"/>
+    <node id="board.clock.pll.mul" option="board.clock.pll.mul.200"/>
+    <node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
+    <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
+    <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/>
+    <node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
+    <node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
+    <node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
+    <node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
+    <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0">
+      <description>Simple application that blinks an LED. No RTOS included.</description>
+      <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
+      <description>Arm CMSIS Version 6 - Core (M)</description>
+      <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra6m1_ek" variant="" vendor="Renesas" version="5.6.0">
+      <description>RA6M1-EK Board Support Files</description>
+      <originalPack>Renesas.RA_board_ra6m1_ek.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m1" subgroup="device" variant="R7FA6M1AD3CFP" vendor="Renesas" version="5.6.0">
+      <description>Board support package for R7FA6M1AD3CFP</description>
+      <originalPack>Renesas.RA_mcu_ra6m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA6M1</description>
+      <originalPack>Renesas.RA_mcu_ra6m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA6M1 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra6m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA6M1 - Events</description>
+      <originalPack>Renesas.RA_mcu_ra6m1.5.6.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+    </context>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p112.symbolic_name" value="LED1"/>
+    <symbolicName propertyId="p415.symbolic_name" value="SW1"/>
+    <pincfg active="true" name="RA6M1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="adc1.an00.p004" configurationId="adc1.an00"/>
+      <configSetting altId="adc1.mode.custom" configurationId="adc1.mode"/>
+      <configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
+      <configSetting altId="ctsu0.ts02.p207" configurationId="ctsu0.ts02"/>
+      <configSetting altId="ctsu0.tscap.p205" configurationId="ctsu0.tscap"/>
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p004.asel" configurationId="p004"/>
+      <configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
+      <configSetting altId="p100.spi0.miso" configurationId="p100"/>
+      <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
+      <configSetting altId="p101.spi0.mosi" configurationId="p101"/>
+      <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
+      <configSetting altId="p102.spi0.rspck" configurationId="p102"/>
+      <configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
+      <configSetting altId="p103.spi0.ssl0" configurationId="p103"/>
+      <configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
+      <configSetting altId="p104.sci8.rxd" configurationId="p104"/>
+      <configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/>
+      <configSetting altId="p105.sci8.txd" configurationId="p105"/>
+      <configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/>
+      <configSetting altId="p106.output.low" configurationId="p106"/>
+      <configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/>
+      <configSetting altId="p107.output.low" configurationId="p107"/>
+      <configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p112.output.low" configurationId="p112"/>
+      <configSetting altId="p112.gpio_mode.gpio_mode_out.low" configurationId="p112.gpio_mode"/>
+      <configSetting altId="p201.input" configurationId="p201"/>
+      <configSetting altId="p201.gpio_mode.gpio_mode_in" configurationId="p201.gpio_mode"/>
+      <configSetting altId="p205.ctsu0.tscap" configurationId="p205"/>
+      <configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/>
+      <configSetting altId="p207.ctsu0.ts02" configurationId="p207"/>
+      <configSetting altId="p207.gpio_mode.gpio_mode_peripheral" configurationId="p207.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+      <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p415.input" configurationId="p415"/>
+      <configSetting altId="p415.gpio_mode.gpio_mode_in" configurationId="p415.gpio_mode"/>
+      <configSetting altId="p415.gpio_pupd.gpio_pupd_ip_up" configurationId="p415.gpio_pupd"/>
+      <configSetting altId="sci8.mode.asynchronous.free" configurationId="sci8.mode"/>
+      <configSetting altId="sci8.rxd.p104" configurationId="sci8.rxd"/>
+      <configSetting altId="sci8.txd.p105" configurationId="sci8.txd"/>
+      <configSetting altId="spi0.miso.p100" configurationId="spi0.miso"/>
+      <configSetting altId="spi0.mode.enabled.a" configurationId="spi0.mode"/>
+      <configSetting altId="spi0.mosi.p101" configurationId="spi0.mosi"/>
+      <configSetting altId="spi0.rspck.p102" configurationId="spi0.rspck"/>
+      <configSetting altId="spi0.ssl0.p103" configurationId="spi0.ssl0"/>
+      <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
+    </pincfg>
+    <pincfg active="false" name="R7FA6M1AD3CFP.pincfg" selected="false" symbol="">
+      <configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
+      <configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
+      <configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
+      <configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
+      <configSetting altId="p108.debug0.tms" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p109.debug0.tdo" configurationId="p109"/>
+      <configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
+      <configSetting altId="p110.debug0.tdi" configurationId="p110"/>
+      <configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
+      <configSetting altId="p300.debug0.tck" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
new file mode 100644
index 000000000..bc99845a1
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -0,0 +1,16 @@
+set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra6m5)
+
+set(JLINK_DEVICE R7FA6M5BH)
+set(JLINK_OPTION "-USB 000831915224")
+
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h
new file mode 100644
index 000000000..32ede3a97
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.h
@@ -0,0 +1,47 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: RA6M5 EK
+   url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m5-evaluation-kit-ra6m5-mcu-group
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_STATE_ON          1
+#define BUTTON_STATE_ACTIVE   0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk
new file mode 100644
index 000000000..5fcc1d0f1
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk
@@ -0,0 +1,11 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = ra6m5
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA6M5BH
+
+# Port 1 is highspeed
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
new file mode 100644
index 000000000..ca18fed7c
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
@@ -0,0 +1,104 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Project.AddSvdFile ("Cortex-M33.svd");
+  Project.AddSvdFile ("./R7FA6M5BH.svd");
+
+  Project.SetDevice ("R7FA6M5BH");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  File.Open ("../../../../../../examples/cmake-build-ra6m5_ek/device/cdc_msc/cdc_msc.elf");
+}
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+	Project.SetJLinkScript("../../../debug.jlinkscript");
+}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr != 0xFFFFFFFF) {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+  } else {
+    Util.Log("Project file error: failed to get program base");
+  }
+
+  PC = Elf.GetEntryPointPC();
+
+  if (PC != 0xFFFFFFFF) {
+    Target.SetReg("PC", PC);
+  } else if (VectorTableAddr != 0xFFFFFFFF) {
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr != 0xFFFFFFFF) {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+  } else {
+    Util.Log("Project file error: failed to get program base");
+  }
+
+  PC = Elf.GetEntryPointPC();
+
+  if (PC != 0xFFFFFFFF) {
+    Target.SetReg("PC", PC);
+  } else if (VectorTableAddr != 0xFFFFFFFF) {
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..90afbdef3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define RA_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #ifndef BSP_CFG_RTC_USED
+             #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+            #endif
+            #undef RA_NOT_DEFINED
+            #if defined(_RA_BOOT_IMAGE)
+             #define BSP_CFG_BOOT_IMAGE (1)
+            #endif
+            #define BSP_CFG_MCU_VCC_MV (3300)
+            #define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+            #define BSP_CFG_HEAP_BYTES (0x1000)
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PFS_PROTECT ((1))
+
+            #define BSP_CFG_C_RUNTIME_INIT ((1))
+            #define BSP_CFG_EARLY_INIT     ((0))
+
+            #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+            #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+            #endif
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+            #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+            #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+            #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+            #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..bd6a901c3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..e532478f8
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M5BH3CFC
+      #define BSP_MCU_FEATURE_SET ('B')
+      #define BSP_ROM_SIZE_BYTES (2097152)
+      #define BSP_RAM_SIZE_BYTES (524288)
+      #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+      #define BSP_PACKAGE_LQFP
+      #define BSP_PACKAGE_PINS (176)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..c01219377
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,392 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+            #include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_MCU_GROUP_RA6M5 (1)
+            #define BSP_LOCO_HZ                 (32768)
+            #define BSP_MOCO_HZ                 (8000000)
+            #define BSP_SUB_CLOCK_HZ            (32768)
+            #if   BSP_CFG_HOCO_FREQUENCY == 0
+                #define BSP_HOCO_HZ                 (16000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 1
+                #define BSP_HOCO_HZ                 (18000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ                 (20000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+
+            #define BSP_CFG_FLL_ENABLE                 (0)
+
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
+            #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (1)
+
+            #if defined(_RA_TZ_SECURE)
+            #define BSP_TZ_SECURE_BUILD           (1)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #elif defined(_RA_TZ_NONSECURE)
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (1)
+            #else
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #endif
+
+            /* TrustZone Settings */
+            #define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+            #define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+            #define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
+
+            /* CMSIS TrustZone Settings */
+            #define SCB_CSR_AIRCR_INIT                (1)
+            #define SCB_AIRCR_BFHFNMINS_VAL           (0)
+            #define SCB_AIRCR_SYSRESETREQS_VAL        (1)
+            #define SCB_AIRCR_PRIS_VAL                (0)
+            #define TZ_FPU_NS_USAGE                   (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+            #define SCB_NSACR_CP10_11_VAL             (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+            #define FPU_FPCCR_TS_VAL                  (1U)
+#endif
+            #define FPU_FPCCR_CLRONRETS_VAL           (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+            #define FPU_FPCCR_CLRONRET_VAL            (1)
+#endif
+
+            /* The C-Cache line size that is configured during startup. */
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+            #define BSP_CFG_C_CACHE_LINE_SIZE   (1U)
+#endif
+
+            /* Type 1 Peripheral Security Attribution */
+
+            /* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+            0x33f4f9) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+            0x7fffcef4) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+            0xffae07f0) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+            0x3f3ff8) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+            0xfffffffc) /* Unused */
+#endif
+
+            /* Type 2 Peripheral Security Attribution */
+
+            /* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
+
+            /* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
+
+            /* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+            0xFFFFFFFCU)
+#endif
+
+            /* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
+            /* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
+
+            /* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+#endif
+
+            /* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
+
+            /* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+            0xFFFF0000U)
+#endif
+
+            /* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+            /* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+            0xFFFFFF00U)
+#endif
+
+            /* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
+#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
+
+            /* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
+
+            /* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
+
+            /* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+ #define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+            /* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+#endif
+
+            /* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+    #define BSP_TZ_CFG_SRAMSAR (\
+        1 | \
+        ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+        4 | \
+        0xFFFFFFF8U)
+#endif
+
+            /* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
+    #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
+
+            /* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+    /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+    #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
+
+            /* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+    #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
+            /* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+    #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
+
+            /* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+    #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+
+            #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+            #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+            #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+            #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+            #define OFS_SEQ5 (1 << 28) | (1 << 30)
+            #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+            /* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
+#else
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+#endif
+
+            #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (1 << 8))
+
+            /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+            #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+            /* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+            #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+#endif
+
+            /* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+            #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+            /* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+            #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+            /* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+            #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+#endif
+            /* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+            #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+            /* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+            #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+            #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+            #define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+            #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+            /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+            #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+            /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+            #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+            /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+            #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+            /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+            #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+            /* Security Attribution for Bank Select Register */
+#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
+            #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+            #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..d2eec08ae
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,99 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define MIKROBUS_AN_ARDUINO_A0 (BSP_IO_PORT_00_PIN_00)
+#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01)
+#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_02)
+#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_03)
+#define SW2 (BSP_IO_PORT_00_PIN_04)
+#define SW1 (BSP_IO_PORT_00_PIN_05)
+#define LED1 (BSP_IO_PORT_00_PIN_06)
+#define LED2 (BSP_IO_PORT_00_PIN_07)
+#define LED3 (BSP_IO_PORT_00_PIN_08)
+#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14)
+#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15)
+#define OSPI_CLK (BSP_IO_PORT_01_PIN_00)
+#define OSPI_SIO7 (BSP_IO_PORT_01_PIN_01)
+#define OSPI_SIO1 (BSP_IO_PORT_01_PIN_02)
+#define OSPI_SIO6 (BSP_IO_PORT_01_PIN_03)
+#define OSPI_DQS (BSP_IO_PORT_01_PIN_04)
+#define OSPI_SIO5 (BSP_IO_PORT_01_PIN_05)
+#define OSPI_SIO0 (BSP_IO_PORT_01_PIN_06)
+#define OSPI_SIO3 (BSP_IO_PORT_01_PIN_07)
+#define MIKROBUS_PWM_ARDUINO_D3_PWM (BSP_IO_PORT_01_PIN_11)
+#define ARDUINO_D4 (BSP_IO_PORT_01_PIN_12)
+#define ARDUINO_D5 (BSP_IO_PORT_01_PIN_13)
+#define ARDUINO_D6 (BSP_IO_PORT_01_PIN_14)
+#define ARDUINO_D9 (BSP_IO_PORT_01_PIN_15)
+#define MIKROBUS_MISO_ARDUINO_MISO_PMOD1_MISO (BSP_IO_PORT_02_PIN_02)
+#define MIKROBUS_MOSI_ARDUINO_MOSI_PMOD1_MOSI (BSP_IO_PORT_02_PIN_03)
+#define MIKROBUS_SCK_ARDUINO_SCK_PMOD1_SCK (BSP_IO_PORT_02_PIN_04)
+#define MIKROBUS_SS_ARDUINO_SS (BSP_IO_PORT_02_PIN_05)
+#define PMOD1_SS (BSP_IO_PORT_02_PIN_06)
+#define ARDUINO_D8 (BSP_IO_PORT_02_PIN_07)
+#define PMOD1_SS2 (BSP_IO_PORT_03_PIN_01)
+#define PMOD1_SS3 (BSP_IO_PORT_03_PIN_02)
+#define MIKROBUS_RESET_ARDUINO_RESET (BSP_IO_PORT_03_PIN_03)
+#define QSPI_CLK (BSP_IO_PORT_03_PIN_05)
+#define QSPI_CS (BSP_IO_PORT_03_PIN_06)
+#define QSPI_IO0 (BSP_IO_PORT_03_PIN_07)
+#define QSPI_IO1 (BSP_IO_PORT_03_PIN_08)
+#define QSPI_IO2 (BSP_IO_PORT_03_PIN_09)
+#define QSPI_IO3 (BSP_IO_PORT_03_PIN_10)
+#define PMOD1_RST (BSP_IO_PORT_03_PIN_11)
+#define PMOD2_INT (BSP_IO_PORT_04_PIN_00)
+#define ETH_MDC (BSP_IO_PORT_04_PIN_01)
+#define ETH_MDIO (BSP_IO_PORT_04_PIN_02)
+#define ETH_RST (BSP_IO_PORT_04_PIN_03)
+#define PMOD2_RST (BSP_IO_PORT_04_PIN_04)
+#define ETH_TXEN (BSP_IO_PORT_04_PIN_05)
+#define ETH_TXD1 (BSP_IO_PORT_04_PIN_06)
+#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07)
+#define PMOD2_SS2 (BSP_IO_PORT_04_PIN_08)
+#define MIKROBUS_INT_ARDUINO_INT0 (BSP_IO_PORT_04_PIN_09)
+#define PMOD2_MISO (BSP_IO_PORT_04_PIN_10)
+#define PMOD2_MOSI (BSP_IO_PORT_04_PIN_11)
+#define PMOD2_SCK (BSP_IO_PORT_04_PIN_12)
+#define PMOS2_SS (BSP_IO_PORT_04_PIN_13)
+#define GROVE1_SDA_QWIIC_SDA (BSP_IO_PORT_04_PIN_14)
+#define GROVE1_SCL_QWIIC_SCL (BSP_IO_PORT_04_PIN_15)
+#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00)
+#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01)
+#define GROVE2_SCL (BSP_IO_PORT_05_PIN_05)
+#define GROVE2_SDA (BSP_IO_PORT_05_PIN_06)
+#define MIKROBUS_SDA_ARDUINO_SDA (BSP_IO_PORT_05_PIN_11)
+#define MIKROBUS_SCL_ARDUINO_SCL (BSP_IO_PORT_05_PIN_12)
+#define OSPI_SIO4 (BSP_IO_PORT_06_PIN_00)
+#define OSPI_SIO2 (BSP_IO_PORT_06_PIN_01)
+#define OSPI_CS1 (BSP_IO_PORT_06_PIN_02)
+#define ARDUINO_D7 (BSP_IO_PORT_06_PIN_08)
+#define CAN_TXD (BSP_IO_PORT_06_PIN_09)
+#define CAN_RDX (BSP_IO_PORT_06_PIN_10)
+#define CAN_STBY (BSP_IO_PORT_06_PIN_11)
+#define MIKROBUS_TX_ARDUINO_TX (BSP_IO_PORT_06_PIN_13)
+#define MIKROBUS_RX_ARDUINO_RX (BSP_IO_PORT_06_PIN_14)
+#define OSPI_RST (BSP_IO_PORT_06_PIN_15)
+#define ETH_TXD0 (BSP_IO_PORT_07_PIN_00)
+#define ETH_50REF (BSP_IO_PORT_07_PIN_01)
+#define ETH_RXD0 (BSP_IO_PORT_07_PIN_02)
+#define ETH_RXD1 (BSP_IO_PORT_07_PIN_03)
+#define ETH_RXERR (BSP_IO_PORT_07_PIN_04)
+#define ETH_CRSDV (BSP_IO_PORT_07_PIN_05)
+#define ETH_INT (BSP_IO_PORT_07_PIN_06)
+#define USBHS_OVERCURA (BSP_IO_PORT_07_PIN_07)
+#define PMOD2_SS3 (BSP_IO_PORT_07_PIN_08)
+#define PMOD1_INT (BSP_IO_PORT_09_PIN_05)
+#define USBHS_VBUS_EN (BSP_IO_PORT_11_PIN_00)
+#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M5 EK */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..d2688bf5b
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 000000000..0eb5e0516
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,37 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+
+#define BSP_CFG_CLOCKS_SECURE   (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ         (24000000)                         /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY  (2)                                /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE      (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV         (BSP_CLOCKS_PLL_DIV_3)             /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL         (BSP_CLOCKS_PLL_MUL(25U,0U))       /* PLL Mul x25.0 */
+#define BSP_CFG_PLL2_SOURCE     (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV        (BSP_CLOCKS_PLL_DIV_2)             /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL        (BSP_CLOCKS_PLL_MUL(20U,0U))       /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE    (BSP_CLOCKS_SOURCE_CLOCK_PLL)      /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE   (BSP_CLOCKS_CLOCK_DISABLED)        /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE      (BSP_CLOCKS_SOURCE_CLOCK_PLL2)     /* UCLK Src: PLL2 */
+#define BSP_CFG_U60CK_SOURCE    (BSP_CLOCKS_SOURCE_CLOCK_PLL2)     /* U60CK Src: PLL2 */
+#define BSP_CFG_OCTA_SOURCE     (BSP_CLOCKS_CLOCK_DISABLED)        /* OCTASPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED)        /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE   (BSP_CLOCKS_CLOCK_DISABLED)        /* CECCLK Disabled */
+#define BSP_CFG_ICLK_DIV        (BSP_CLOCKS_SYS_CLOCK_DIV_1)       /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_2)       /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_4)       /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_4)       /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_2)       /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV        (BSP_CLOCKS_SYS_CLOCK_DIV_2)       /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT     (2)                                /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV        (BSP_CLOCKS_SYS_CLOCK_DIV_4)       /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV      (BSP_CLOCKS_SYS_CLOCK_DIV_1)       /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV         (BSP_CLOCKS_USB_CLOCK_DIV_5)       /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV       (BSP_CLOCKS_USB60_CLOCK_DIV_4)     /* U60CK Div /4 */
+#define BSP_CFG_OCTA_DIV        (BSP_CLOCKS_OCTA_CLOCK_DIV_1)      /* OCTASPICLK Div /1 */
+#define BSP_CFG_CANFDCLK_DIV    (BSP_CLOCKS_CANFD_CLOCK_DIV_1)     /* CANFDCLK Div /1 */
+#define BSP_CFG_CECCLK_DIV      (BSP_CLOCKS_CEC_CLOCK_DIV_1)       /* CECCLK Div /1 */
+
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c
new file mode 100644
index 000000000..50036c0ad
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h
new file mode 100644
index 000000000..6a08cbee0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c
new file mode 100644
index 000000000..6b814d74a
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c
@@ -0,0 +1,411 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_00_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_13,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_10,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_10,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_10,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_13,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_10,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_13,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_11_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+    },
+    {
+        .pin = BSP_IO_PORT_11_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+    }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld
new file mode 100644
index 000000000..605eef7d2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+                  Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                          FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END    = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START    = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START   = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                            FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                            __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                           FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                           FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+                XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+                FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+                       DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+                       FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+                            OPTION_SETTING_LENGTH == 0 ? 0 :
+                            OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+  ITCM (rx)                       : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+  DTCM (rwx)                      : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+  FLASH (rx)                      : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+  RAM (rwx)                       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx)                 : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx)                 : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx)              : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx)              : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  OSPI_DEVICE_0_RAM (rwx)         : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1_RAM (rwx)         : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)                     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r)              : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_OFS (r)          : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+  OPTION_SETTING_SAS (r)          : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+  OPTION_SETTING_S (r)            : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+  ID_CODE (rx)                    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* Some devices have a gap of code flash between the vector table and ROM Registers.
+         * The flash gap section allows applications to place code and data in this section. */
+        *(.flash_gap*)
+
+        /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+        /* Allocate flash write-boundary-aligned
+         * space for sce9 wrapped public keys for mcuboot if the module is used.
+         */
+        KEEP(*(.mcuboot_sce9_key*))
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    . = .;
+    __itcm_data_pre_location = .;
+
+    /* Initialized ITCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .itcm_data : ALIGN(16)
+    {
+        /* Start of ITCM Secure Trustzone region. */
+        __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+        /* All ITCM data start */
+        __itcm_data_start = .;
+
+        KEEP(*(.itcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* All ITCM data end */
+        __itcm_data_end = .;
+
+        /*
+         * Start of the ITCM Non-Secure Trustzone region.
+         * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+    } > ITCM AT > FLASH = 0x00
+
+    /* Addresses exported for ITCM initialization. */
+    __itcm_data_init_start = LOADADDR(.itcm_data);
+    __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+    ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+    /* Restore location counter. */
+    /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+    . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+    __exidx_start = .;
+    /DISCARD/ :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    }
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    . = .;
+    __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+    /* Initialized DTCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .dtcm_data : ALIGN(16)
+    {
+        /* Start of DTCM Secure Trustzone region. */
+        __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+        /* Initialized DTCM data start */
+        __dtcm_data_start = .;
+
+        KEEP(*(.dtcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* Initialized DTCM data end */
+        __dtcm_data_end = .;
+    } > DTCM AT > FLASH = 0x00
+
+    . = __dtcm_data_end;
+    /* Uninitialized DTCM data. */
+    /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+    .dtcm_bss ALIGN(8) (NOLOAD) :
+    {
+        /* Uninitialized DTCM data start */
+        __dtcm_bss_start = .;
+
+        KEEP(*(.dtcm_bss*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+        . = ALIGN(8);
+
+        /* Uninitialized DTCM data end */
+        __dtcm_bss_end = .;
+
+        /*
+         * Start of the DTCM Non-Secure Trustzone region.
+         * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+         */
+        __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+    } > DTCM
+
+    /* Addresses exported for DTCM initialization. */
+    __dtcm_data_init_start = LOADADDR(.dtcm_data);
+    __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+    ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+    ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+    ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+    ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+    /* Restore location counter. */
+    /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+    . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+    /* TrustZone Secure Gateway Stubs Section */
+
+    /* Store location counter for SPI non-retentive sections. */
+    sgstubs_pre_location = .;
+
+    /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+    SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+    .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+    {
+        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+    FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = sgstubs_pre_location;
+    .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Support for OctaRAM */
+    .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_0_start__ = .;
+        *(.ospi_device_0_no_load*)
+        . = ALIGN(4);
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0_RAM
+
+    .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_1_start__ = .;
+        *(.ospi_device_1_no_load*)
+        . = ALIGN(4);
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1_RAM
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+     __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+    .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+    .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool.
+     *       Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+     *       memory region between TrustZone projects. */
+    __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+    .option_setting_ofs :
+    {
+        __OPTION_SETTING_OFS_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_ofs2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_dualsel))
+        __OPTION_SETTING_OFS_End = .;
+    } > OPTION_SETTING_OFS = 0xFF
+
+    .option_setting_sas :
+    {
+        __OPTION_SETTING_SAS_Start = .;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_SAS_End = .;
+    } > OPTION_SETTING_SAS = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_ofs3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps3))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel3))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld
new file mode 100644
index 000000000..19864683f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+            /* generated memory regions file - do not edit */
+                            RAM_START  = 0x20000000;
+                RAM_LENGTH = 0x80000;
+                FLASH_START  = 0x00000000;
+                FLASH_LENGTH = 0x200000;
+                DATA_FLASH_START  = 0x08000000;
+                DATA_FLASH_LENGTH = 0x2000;
+                OPTION_SETTING_START  = 0x0100A100;
+                OPTION_SETTING_LENGTH = 0x100;
+                OPTION_SETTING_S_START  = 0x0100A200;
+                OPTION_SETTING_S_LENGTH = 0x100;
+                ID_CODE_START  = 0x00000000;
+                ID_CODE_LENGTH = 0x0;
+                SDRAM_START  = 0x80010000;
+                SDRAM_LENGTH = 0x0;
+                QSPI_FLASH_START  = 0x60000000;
+                QSPI_FLASH_LENGTH = 0x4000000;
+                OSPI_DEVICE_0_START  = 0x68000000;
+                OSPI_DEVICE_0_LENGTH = 0x8000000;
+                OSPI_DEVICE_1_START  = 0x70000000;
+                OSPI_DEVICE_1_LENGTH = 0x10000000;
diff --git a/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml
new file mode 100644
index 000000000..4544d0f2a
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml
@@ -0,0 +1,670 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.ra6m5ek"/>
+    <option key="CPU" value="RA6M5"/>
+    <option key="Core" value="CM33"/>
+    <option key="#TargetName#" value="R7FA6M5BH3CFC"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m33"/>
+    <option key="#DeviceCommand#" value="R7FA6M5BH"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA6M5BH3CFC.pincfg"/>
+    <option key="#FSPVersion#" value="5.6.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra6m5_ek##"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra6m5.R7FA6M5BH3CFC">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="2097152"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.irq_count_hidden" value="96"/>
+    </config>
+    <config id="config.bsp.ra6m5">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra6m5.fsp">
+      <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
+      <property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
+      <property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
+      <property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
+      <property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
+      <property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/>
+      <property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
+      <property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/>
+      <property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/>
+      <property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/>
+      <property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/>
+      <property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
+      <property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
+      <property id="config.bsp.fsp.tz.banksel_sel" value="config.bsp.fsp.tz.banksel_sel.both"/>
+      <property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/>
+      <property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
+      <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
+      <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/>
+      <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
+      <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
+      <property id="config.bsp.fsp.BPS.BPS0" value=""/>
+      <property id="config.bsp.fsp.BPS.BPS1" value=""/>
+      <property id="config.bsp.fsp.BPS.BPS2" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS2" value=""/>
+      <property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/>
+      <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="16666666"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
+      <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/>
+      <property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/>
+      <property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="8"/>
+      <property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="4864"/>
+      <property id="config.bsp.fsp.mcu.canfd.afl_rules" value="128"/>
+      <property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="64"/>
+      <property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="5"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x03F9"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
+      <property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="65535"/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x1000"/>
+      <property id="config.bsp.common.heap" value="0x1000"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
+    <node id="board.clock.pll.div" option="board.clock.pll.div.3"/>
+    <node id="board.clock.pll.mul" option="board.clock.pll.mul.250"/>
+    <node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
+    <node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
+    <node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
+    <node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/>
+    <node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.uclk.source" option="board.clock.uclk.source.disabled"/>
+    <node id="board.clock.u60ck.source" option="board.clock.u60ck.source.disabled"/>
+    <node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
+    <node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
+    <node id="board.clock.cecclk.source" option="board.clock.cecclk.source.disabled"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
+    <node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
+    <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
+    <node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/>
+    <node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
+    <node id="board.clock.u60ck.div" option="board.clock.u60ck.div.1"/>
+    <node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.1"/>
+    <node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.6"/>
+    <node id="board.clock.cecclk.div" option="board.clock.cecclk.div.1"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
+    <node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+    <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
+    <node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
+    <node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
+    <node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
+    <node id="board.clock.cecclk.display" option="board.clock.cecclk.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0">
+      <description>Simple application that blinks an LED. No RTOS included.</description>
+      <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
+      <description>Arm CMSIS Version 6 - Core (M)</description>
+      <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra6m5_ek" variant="" vendor="Renesas" version="5.6.0">
+      <description>RA6M5-EK Board Support Files</description>
+      <originalPack>Renesas.RA_board_ra6m5_ek.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="R7FA6M5BH3CFC" vendor="Renesas" version="5.6.0">
+      <description>Board support package for R7FA6M5BH3CFC</description>
+      <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA6M5</description>
+      <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA6M5 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA6M5 - Events</description>
+      <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+    </context>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p000.symbolic_name" value="MIKROBUS_AN_ARDUINO_A0"/>
+    <symbolicName propertyId="p001.symbolic_name" value="ARDUINO_A1"/>
+    <symbolicName propertyId="p002.symbolic_name" value="ARDUINO_A2"/>
+    <symbolicName propertyId="p003.symbolic_name" value="ARDUINO_A3"/>
+    <symbolicName propertyId="p004.symbolic_name" value="SW2"/>
+    <symbolicName propertyId="p005.symbolic_name" value="SW1"/>
+    <symbolicName propertyId="p006.symbolic_name" value="LED1"/>
+    <symbolicName propertyId="p007.symbolic_name" value="LED2"/>
+    <symbolicName propertyId="p008.symbolic_name" value="LED3"/>
+    <symbolicName propertyId="p014.symbolic_name" value="ARDUINO_A4"/>
+    <symbolicName propertyId="p015.symbolic_name" value="ARDUINO_A5"/>
+    <symbolicName propertyId="p100.symbolic_name" value="OSPI_CLK"/>
+    <symbolicName propertyId="p101.symbolic_name" value="OSPI_SIO7"/>
+    <symbolicName propertyId="p102.symbolic_name" value="OSPI_SIO1"/>
+    <symbolicName propertyId="p103.symbolic_name" value="OSPI_SIO6"/>
+    <symbolicName propertyId="p104.symbolic_name" value="OSPI_DQS"/>
+    <symbolicName propertyId="p105.symbolic_name" value="OSPI_SIO5"/>
+    <symbolicName propertyId="p106.symbolic_name" value="OSPI_SIO0"/>
+    <symbolicName propertyId="p107.symbolic_name" value="OSPI_SIO3"/>
+    <symbolicName propertyId="p111.symbolic_name" value="MIKROBUS_PWM_ARDUINO_D3_PWM"/>
+    <symbolicName propertyId="p112.symbolic_name" value="ARDUINO_D4"/>
+    <symbolicName propertyId="p113.symbolic_name" value="ARDUINO_D5"/>
+    <symbolicName propertyId="p114.symbolic_name" value="ARDUINO_D6"/>
+    <symbolicName propertyId="p115.symbolic_name" value="ARDUINO_D9"/>
+    <symbolicName propertyId="p202.symbolic_name" value="MIKROBUS_MISO_ARDUINO_MISO_PMOD1_MISO"/>
+    <symbolicName propertyId="p203.symbolic_name" value="MIKROBUS_MOSI_ARDUINO_MOSI_PMOD1_MOSI"/>
+    <symbolicName propertyId="p204.symbolic_name" value="MIKROBUS_SCK_ARDUINO_SCK_PMOD1_SCK"/>
+    <symbolicName propertyId="p205.symbolic_name" value="MIKROBUS_SS_ARDUINO_SS"/>
+    <symbolicName propertyId="p206.symbolic_name" value="PMOD1_SS"/>
+    <symbolicName propertyId="p207.symbolic_name" value="ARDUINO_D8"/>
+    <symbolicName propertyId="p301.symbolic_name" value="PMOD1_SS2"/>
+    <symbolicName propertyId="p302.symbolic_name" value="PMOD1_SS3"/>
+    <symbolicName propertyId="p303.symbolic_name" value="MIKROBUS_RESET_ARDUINO_RESET"/>
+    <symbolicName propertyId="p305.symbolic_name" value="QSPI_CLK"/>
+    <symbolicName propertyId="p306.symbolic_name" value="QSPI_CS"/>
+    <symbolicName propertyId="p307.symbolic_name" value="QSPI_IO0"/>
+    <symbolicName propertyId="p308.symbolic_name" value="QSPI_IO1"/>
+    <symbolicName propertyId="p309.symbolic_name" value="QSPI_IO2"/>
+    <symbolicName propertyId="p310.symbolic_name" value="QSPI_IO3"/>
+    <symbolicName propertyId="p311.symbolic_name" value="PMOD1_RST"/>
+    <symbolicName propertyId="p400.symbolic_name" value="PMOD2_INT"/>
+    <symbolicName propertyId="p401.symbolic_name" value="ETH_MDC"/>
+    <symbolicName propertyId="p402.symbolic_name" value="ETH_MDIO"/>
+    <symbolicName propertyId="p403.symbolic_name" value="ETH_RST"/>
+    <symbolicName propertyId="p404.symbolic_name" value="PMOD2_RST"/>
+    <symbolicName propertyId="p405.symbolic_name" value="ETH_TXEN"/>
+    <symbolicName propertyId="p406.symbolic_name" value="ETH_TXD1"/>
+    <symbolicName propertyId="p407.symbolic_name" value="USBFS_VBUS"/>
+    <symbolicName propertyId="p408.symbolic_name" value="PMOD2_SS2"/>
+    <symbolicName propertyId="p409.symbolic_name" value="MIKROBUS_INT_ARDUINO_INT0"/>
+    <symbolicName propertyId="p410.symbolic_name" value="PMOD2_MISO"/>
+    <symbolicName propertyId="p411.symbolic_name" value="PMOD2_MOSI"/>
+    <symbolicName propertyId="p412.symbolic_name" value="PMOD2_SCK"/>
+    <symbolicName propertyId="p413.symbolic_name" value="PMOS2_SS"/>
+    <symbolicName propertyId="p414.symbolic_name" value="GROVE1_SDA_QWIIC_SDA"/>
+    <symbolicName propertyId="p415.symbolic_name" value="GROVE1_SCL_QWIIC_SCL"/>
+    <symbolicName propertyId="p500.symbolic_name" value="USBFS_VBUS_EN"/>
+    <symbolicName propertyId="p501.symbolic_name" value="USBFS_OVERCURA"/>
+    <symbolicName propertyId="p505.symbolic_name" value="GROVE2_SCL"/>
+    <symbolicName propertyId="p506.symbolic_name" value="GROVE2_SDA"/>
+    <symbolicName propertyId="p511.symbolic_name" value="MIKROBUS_SDA_ARDUINO_SDA"/>
+    <symbolicName propertyId="p512.symbolic_name" value="MIKROBUS_SCL_ARDUINO_SCL"/>
+    <symbolicName propertyId="p600.symbolic_name" value="OSPI_SIO4"/>
+    <symbolicName propertyId="p601.symbolic_name" value="OSPI_SIO2"/>
+    <symbolicName propertyId="p602.symbolic_name" value="OSPI_CS1"/>
+    <symbolicName propertyId="p608.symbolic_name" value="ARDUINO_D7"/>
+    <symbolicName propertyId="p609.symbolic_name" value="CAN_TXD"/>
+    <symbolicName propertyId="p610.symbolic_name" value="CAN_RDX"/>
+    <symbolicName propertyId="p611.symbolic_name" value="CAN_STBY"/>
+    <symbolicName propertyId="p613.symbolic_name" value="MIKROBUS_TX_ARDUINO_TX"/>
+    <symbolicName propertyId="p614.symbolic_name" value="MIKROBUS_RX_ARDUINO_RX"/>
+    <symbolicName propertyId="p615.symbolic_name" value="OSPI_RST"/>
+    <symbolicName propertyId="p700.symbolic_name" value="ETH_TXD0"/>
+    <symbolicName propertyId="p701.symbolic_name" value="ETH_50REF"/>
+    <symbolicName propertyId="p702.symbolic_name" value="ETH_RXD0"/>
+    <symbolicName propertyId="p703.symbolic_name" value="ETH_RXD1"/>
+    <symbolicName propertyId="p704.symbolic_name" value="ETH_RXERR"/>
+    <symbolicName propertyId="p705.symbolic_name" value="ETH_CRSDV"/>
+    <symbolicName propertyId="p706.symbolic_name" value="ETH_INT"/>
+    <symbolicName propertyId="p707.symbolic_name" value="USBHS_OVERCURA"/>
+    <symbolicName propertyId="p708.symbolic_name" value="PMOD2_SS3"/>
+    <symbolicName propertyId="p905.symbolic_name" value="PMOD1_INT"/>
+    <symbolicName propertyId="pb00.symbolic_name" value="USBHS_VBUS_EN"/>
+    <symbolicName propertyId="pb01.symbolic_name" value="USBHS_VBUS"/>
+    <pincfg active="true" name="RA6M5 EK" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="adc0.an00.p000" configurationId="adc0.an00"/>
+      <configSetting altId="adc0.an01.p001" configurationId="adc0.an01"/>
+      <configSetting altId="adc0.an02.p002" configurationId="adc0.an02"/>
+      <configSetting altId="adc0.an03.p003" configurationId="adc0.an03"/>
+      <configSetting altId="adc0.an12.p014" configurationId="adc0.an12"/>
+      <configSetting altId="adc0.an13.p015" configurationId="adc0.an13"/>
+      <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
+      <configSetting altId="can1.crx.p610" configurationId="can1.crx"/>
+      <configSetting altId="can1.ctx.p609" configurationId="can1.ctx"/>
+      <configSetting altId="can1.mode.enabled.free" configurationId="can1.mode"/>
+      <configSetting altId="cgc0.extal.p212" configurationId="cgc0.extal"/>
+      <configSetting altId="cgc0.mode.mainsub" configurationId="cgc0.mode"/>
+      <configSetting altId="cgc0.xtal.p213" configurationId="cgc0.xtal"/>
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="etherc0.rmii.crs_dv.p705" configurationId="etherc0.rmii.crs_dv"/>
+      <configSetting altId="etherc0.rmii.mdc.p401" configurationId="etherc0.rmii.mdc"/>
+      <configSetting altId="etherc0.rmii.mdio.p402" configurationId="etherc0.rmii.mdio"/>
+      <configSetting altId="etherc0.rmii.mode.rmii.free" configurationId="etherc0.rmii.mode"/>
+      <configSetting altId="etherc0.rmii.pairing.free" configurationId="etherc0.rmii.pairing"/>
+      <configSetting altId="etherc0.rmii.ref50ck.p701" configurationId="etherc0.rmii.ref50ck"/>
+      <configSetting altId="etherc0.rmii.rx_er.p704" configurationId="etherc0.rmii.rx_er"/>
+      <configSetting altId="etherc0.rmii.rxd0.p702" configurationId="etherc0.rmii.rxd0"/>
+      <configSetting altId="etherc0.rmii.rxd1.p703" configurationId="etherc0.rmii.rxd1"/>
+      <configSetting altId="etherc0.rmii.txd0.p700" configurationId="etherc0.rmii.txd0"/>
+      <configSetting altId="etherc0.rmii.txd1.p406" configurationId="etherc0.rmii.txd1"/>
+      <configSetting altId="etherc0.rmii.txd_en.p405" configurationId="etherc0.rmii.txd_en"/>
+      <configSetting altId="gpt3.gtioca.p111" configurationId="gpt3.gtioca"/>
+      <configSetting altId="gpt3.mode.gtiocaorgtiocb.free" configurationId="gpt3.mode"/>
+      <configSetting altId="iic1.mode.enabled.a" configurationId="iic1.mode"/>
+      <configSetting altId="iic1.scl.p512" configurationId="iic1.scl"/>
+      <configSetting altId="iic1.sda.p511" configurationId="iic1.sda"/>
+      <configSetting altId="iic2.mode.enabled.free" configurationId="iic2.mode"/>
+      <configSetting altId="iic2.pairing.free" configurationId="iic2.pairing"/>
+      <configSetting altId="iic2.scl.p415" configurationId="iic2.scl"/>
+      <configSetting altId="iic2.sda.p414" configurationId="iic2.sda"/>
+      <configSetting altId="ospi0.mode.custom.free" configurationId="ospi0.mode"/>
+      <configSetting altId="ospi0.omcs1.p602" configurationId="ospi0.omcs1"/>
+      <configSetting altId="ospi0.omdqs.p104" configurationId="ospi0.omdqs"/>
+      <configSetting altId="ospi0.omsclk.p100" configurationId="ospi0.omsclk"/>
+      <configSetting altId="ospi0.omsio0.p106" configurationId="ospi0.omsio0"/>
+      <configSetting altId="ospi0.omsio1.p102" configurationId="ospi0.omsio1"/>
+      <configSetting altId="ospi0.omsio2.p601" configurationId="ospi0.omsio2"/>
+      <configSetting altId="ospi0.omsio3.p107" configurationId="ospi0.omsio3"/>
+      <configSetting altId="ospi0.omsio4.p600" configurationId="ospi0.omsio4"/>
+      <configSetting altId="ospi0.omsio5.p105" configurationId="ospi0.omsio5"/>
+      <configSetting altId="ospi0.omsio6.p103" configurationId="ospi0.omsio6"/>
+      <configSetting altId="ospi0.omsio7.p101" configurationId="ospi0.omsio7"/>
+      <configSetting altId="ospi0.pairing.free" configurationId="ospi0.pairing"/>
+      <configSetting altId="p000.asel" configurationId="p000"/>
+      <configSetting altId="p000.gpio_mode.gpio_mode_an" configurationId="p000.gpio_mode"/>
+      <configSetting altId="p001.asel" configurationId="p001"/>
+      <configSetting altId="p001.gpio_mode.gpio_mode_an" configurationId="p001.gpio_mode"/>
+      <configSetting altId="p002.asel" configurationId="p002"/>
+      <configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/>
+      <configSetting altId="p003.asel" configurationId="p003"/>
+      <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
+      <configSetting altId="p004.input" configurationId="p004"/>
+      <configSetting altId="p004.gpio_irq.gpio_irq_enabled" configurationId="p004.gpio_irq"/>
+      <configSetting altId="p004.gpio_mode.gpio_mode_in" configurationId="p004.gpio_mode"/>
+      <configSetting altId="p005.input" configurationId="p005"/>
+      <configSetting altId="p005.gpio_irq.gpio_irq_enabled" configurationId="p005.gpio_irq"/>
+      <configSetting altId="p005.gpio_mode.gpio_mode_in" configurationId="p005.gpio_mode"/>
+      <configSetting altId="p006.output.low" configurationId="p006"/>
+      <configSetting altId="p006.gpio_mode.gpio_mode_out.low" configurationId="p006.gpio_mode"/>
+      <configSetting altId="p007.output.low" configurationId="p007"/>
+      <configSetting altId="p007.gpio_mode.gpio_mode_out.low" configurationId="p007.gpio_mode"/>
+      <configSetting altId="p008.output.low" configurationId="p008"/>
+      <configSetting altId="p008.gpio_mode.gpio_mode_out.low" configurationId="p008.gpio_mode"/>
+      <configSetting altId="p014.asel" configurationId="p014"/>
+      <configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/>
+      <configSetting altId="p015.asel" configurationId="p015"/>
+      <configSetting altId="p015.gpio_mode.gpio_mode_an" configurationId="p015.gpio_mode"/>
+      <configSetting altId="p100.ospi0.omsclk" configurationId="p100"/>
+      <configSetting altId="p100.gpio_speed.gpio_speed_highspeedhigh" configurationId="p100.gpio_drivecapacity"/>
+      <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
+      <configSetting altId="p101.ospi0.omsio7" configurationId="p101"/>
+      <configSetting altId="p101.gpio_speed.gpio_speed_highspeedhigh" configurationId="p101.gpio_drivecapacity"/>
+      <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
+      <configSetting altId="p102.ospi0.omsio1" configurationId="p102"/>
+      <configSetting altId="p102.gpio_speed.gpio_speed_highspeedhigh" configurationId="p102.gpio_drivecapacity"/>
+      <configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
+      <configSetting altId="p103.ospi0.omsio6" configurationId="p103"/>
+      <configSetting altId="p103.gpio_speed.gpio_speed_highspeedhigh" configurationId="p103.gpio_drivecapacity"/>
+      <configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
+      <configSetting altId="p104.ospi0.omdqs" configurationId="p104"/>
+      <configSetting altId="p104.gpio_speed.gpio_speed_highspeedhigh" configurationId="p104.gpio_drivecapacity"/>
+      <configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/>
+      <configSetting altId="p105.ospi0.omsio5" configurationId="p105"/>
+      <configSetting altId="p105.gpio_speed.gpio_speed_highspeedhigh" configurationId="p105.gpio_drivecapacity"/>
+      <configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/>
+      <configSetting altId="p106.ospi0.omsio0" configurationId="p106"/>
+      <configSetting altId="p106.gpio_speed.gpio_speed_highspeedhigh" configurationId="p106.gpio_drivecapacity"/>
+      <configSetting altId="p106.gpio_mode.gpio_mode_peripheral" configurationId="p106.gpio_mode"/>
+      <configSetting altId="p107.ospi0.omsio3" configurationId="p107"/>
+      <configSetting altId="p107.gpio_speed.gpio_speed_highspeedhigh" configurationId="p107.gpio_drivecapacity"/>
+      <configSetting altId="p107.gpio_mode.gpio_mode_peripheral" configurationId="p107.gpio_mode"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p111.gpt3.gtioca" configurationId="p111"/>
+      <configSetting altId="p111.gpio_speed.gpio_speed_high" configurationId="p111.gpio_drivecapacity"/>
+      <configSetting altId="p111.gpio_mode.gpio_mode_peripheral" configurationId="p111.gpio_mode"/>
+      <configSetting altId="p112.output.low" configurationId="p112"/>
+      <configSetting altId="p112.gpio_speed.gpio_speed_high" configurationId="p112.gpio_drivecapacity"/>
+      <configSetting altId="p112.gpio_mode.gpio_mode_out.low" configurationId="p112.gpio_mode"/>
+      <configSetting altId="p113.output.low" configurationId="p113"/>
+      <configSetting altId="p113.gpio_speed.gpio_speed_high" configurationId="p113.gpio_drivecapacity"/>
+      <configSetting altId="p113.gpio_mode.gpio_mode_out.low" configurationId="p113.gpio_mode"/>
+      <configSetting altId="p114.output.low" configurationId="p114"/>
+      <configSetting altId="p114.gpio_speed.gpio_speed_high" configurationId="p114.gpio_drivecapacity"/>
+      <configSetting altId="p114.gpio_mode.gpio_mode_out.low" configurationId="p114.gpio_mode"/>
+      <configSetting altId="p115.output.low" configurationId="p115"/>
+      <configSetting altId="p115.gpio_speed.gpio_speed_high" configurationId="p115.gpio_drivecapacity"/>
+      <configSetting altId="p115.gpio_mode.gpio_mode_out.low" configurationId="p115.gpio_mode"/>
+      <configSetting altId="p202.spi0.miso" configurationId="p202"/>
+      <configSetting altId="p202.gpio_speed.gpio_speed_high" configurationId="p202.gpio_drivecapacity"/>
+      <configSetting altId="p202.gpio_mode.gpio_mode_peripheral" configurationId="p202.gpio_mode"/>
+      <configSetting altId="p203.spi0.mosi" configurationId="p203"/>
+      <configSetting altId="p203.gpio_speed.gpio_speed_high" configurationId="p203.gpio_drivecapacity"/>
+      <configSetting altId="p203.gpio_mode.gpio_mode_peripheral" configurationId="p203.gpio_mode"/>
+      <configSetting altId="p204.spi0.rspck" configurationId="p204"/>
+      <configSetting altId="p204.gpio_speed.gpio_speed_high" configurationId="p204.gpio_drivecapacity"/>
+      <configSetting altId="p204.gpio_mode.gpio_mode_peripheral" configurationId="p204.gpio_mode"/>
+      <configSetting altId="p205.spi0.ssl0" configurationId="p205"/>
+      <configSetting altId="p205.gpio_speed.gpio_speed_high" configurationId="p205.gpio_drivecapacity"/>
+      <configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/>
+      <configSetting altId="p206.spi0.ssl1" configurationId="p206"/>
+      <configSetting altId="p206.gpio_speed.gpio_speed_high" configurationId="p206.gpio_drivecapacity"/>
+      <configSetting altId="p206.gpio_mode.gpio_mode_peripheral" configurationId="p206.gpio_mode"/>
+      <configSetting altId="p207.output.low" configurationId="p207"/>
+      <configSetting altId="p207.gpio_speed.gpio_speed_high" configurationId="p207.gpio_drivecapacity"/>
+      <configSetting altId="p207.gpio_mode.gpio_mode_out.low" configurationId="p207.gpio_mode"/>
+      <configSetting altId="p208.trace0.tdata3" configurationId="p208"/>
+      <configSetting altId="p208.gpio_mode.gpio_mode_peripheral" configurationId="p208.gpio_mode"/>
+      <configSetting altId="p209.trace0.tdata2" configurationId="p209"/>
+      <configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/>
+      <configSetting altId="p210.trace0.tdata1" configurationId="p210"/>
+      <configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/>
+      <configSetting altId="p211.trace0.tdata0" configurationId="p211"/>
+      <configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/>
+      <configSetting altId="p212.cgc0.extal" configurationId="p212"/>
+      <configSetting altId="p212.gpio_mode.gpio_mode_peripheral" configurationId="p212.gpio_mode"/>
+      <configSetting altId="p213.cgc0.xtal" configurationId="p213"/>
+      <configSetting altId="p213.gpio_mode.gpio_mode_peripheral" configurationId="p213.gpio_mode"/>
+      <configSetting altId="p214.trace0.tclk" configurationId="p214"/>
+      <configSetting altId="p214.gpio_mode.gpio_mode_peripheral" configurationId="p214.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+      <configSetting altId="p301.spi0.ssl2" configurationId="p301"/>
+      <configSetting altId="p301.gpio_speed.gpio_speed_high" configurationId="p301.gpio_drivecapacity"/>
+      <configSetting altId="p301.gpio_mode.gpio_mode_peripheral" configurationId="p301.gpio_mode"/>
+      <configSetting altId="p302.spi0.ssl3" configurationId="p302"/>
+      <configSetting altId="p302.gpio_speed.gpio_speed_high" configurationId="p302.gpio_drivecapacity"/>
+      <configSetting altId="p302.gpio_mode.gpio_mode_peripheral" configurationId="p302.gpio_mode"/>
+      <configSetting altId="p303.output.low" configurationId="p303"/>
+      <configSetting altId="p303.gpio_speed.gpio_speed_high" configurationId="p303.gpio_drivecapacity"/>
+      <configSetting altId="p303.gpio_mode.gpio_mode_out.low" configurationId="p303.gpio_mode"/>
+      <configSetting altId="p305.qspi0.qspclk" configurationId="p305"/>
+      <configSetting altId="p305.gpio_speed.gpio_speed_high" configurationId="p305.gpio_drivecapacity"/>
+      <configSetting altId="p305.gpio_mode.gpio_mode_peripheral" configurationId="p305.gpio_mode"/>
+      <configSetting altId="p306.qspi0.qssl" configurationId="p306"/>
+      <configSetting altId="p306.gpio_speed.gpio_speed_high" configurationId="p306.gpio_drivecapacity"/>
+      <configSetting altId="p306.gpio_mode.gpio_mode_peripheral" configurationId="p306.gpio_mode"/>
+      <configSetting altId="p307.qspi0.qio0" configurationId="p307"/>
+      <configSetting altId="p307.gpio_speed.gpio_speed_high" configurationId="p307.gpio_drivecapacity"/>
+      <configSetting altId="p307.gpio_mode.gpio_mode_peripheral" configurationId="p307.gpio_mode"/>
+      <configSetting altId="p308.qspi0.qio1" configurationId="p308"/>
+      <configSetting altId="p308.gpio_speed.gpio_speed_high" configurationId="p308.gpio_drivecapacity"/>
+      <configSetting altId="p308.gpio_mode.gpio_mode_peripheral" configurationId="p308.gpio_mode"/>
+      <configSetting altId="p309.qspi0.qio2" configurationId="p309"/>
+      <configSetting altId="p309.gpio_speed.gpio_speed_high" configurationId="p309.gpio_drivecapacity"/>
+      <configSetting altId="p309.gpio_mode.gpio_mode_peripheral" configurationId="p309.gpio_mode"/>
+      <configSetting altId="p310.qspi0.qio3" configurationId="p310"/>
+      <configSetting altId="p310.gpio_speed.gpio_speed_high" configurationId="p310.gpio_drivecapacity"/>
+      <configSetting altId="p310.gpio_mode.gpio_mode_peripheral" configurationId="p310.gpio_mode"/>
+      <configSetting altId="p311.output.low" configurationId="p311"/>
+      <configSetting altId="p311.gpio_speed.gpio_speed_high" configurationId="p311.gpio_drivecapacity"/>
+      <configSetting altId="p311.gpio_mode.gpio_mode_out.low" configurationId="p311.gpio_mode"/>
+      <configSetting altId="p400.input" configurationId="p400"/>
+      <configSetting altId="p400.gpio_irq.gpio_irq_enabled" configurationId="p400.gpio_irq"/>
+      <configSetting altId="p400.gpio_mode.gpio_mode_in" configurationId="p400.gpio_mode"/>
+      <configSetting altId="p400.gpio_pupd.gpio_pupd_ip_up" configurationId="p400.gpio_pupd"/>
+      <configSetting altId="p401.etherc0.rmii.mdc" configurationId="p401"/>
+      <configSetting altId="p401.gpio_speed.gpio_speed_high" configurationId="p401.gpio_drivecapacity"/>
+      <configSetting altId="p401.gpio_mode.gpio_mode_peripheral" configurationId="p401.gpio_mode"/>
+      <configSetting altId="p402.etherc0.rmii.mdio" configurationId="p402"/>
+      <configSetting altId="p402.gpio_speed.gpio_speed_high" configurationId="p402.gpio_drivecapacity"/>
+      <configSetting altId="p402.gpio_mode.gpio_mode_peripheral" configurationId="p402.gpio_mode"/>
+      <configSetting altId="p403.output.high" configurationId="p403"/>
+      <configSetting altId="p403.gpio_speed.gpio_speed_high" configurationId="p403.gpio_drivecapacity"/>
+      <configSetting altId="p403.gpio_mode.gpio_mode_out.high" configurationId="p403.gpio_mode"/>
+      <configSetting altId="p404.output.low" configurationId="p404"/>
+      <configSetting altId="p404.gpio_speed.gpio_speed_high" configurationId="p404.gpio_drivecapacity"/>
+      <configSetting altId="p404.gpio_mode.gpio_mode_out.low" configurationId="p404.gpio_mode"/>
+      <configSetting altId="p405.etherc0.rmii.txd_en" configurationId="p405"/>
+      <configSetting altId="p405.gpio_speed.gpio_speed_high" configurationId="p405.gpio_drivecapacity"/>
+      <configSetting altId="p405.gpio_mode.gpio_mode_peripheral" configurationId="p405.gpio_mode"/>
+      <configSetting altId="p406.etherc0.rmii.txd1" configurationId="p406"/>
+      <configSetting altId="p406.gpio_speed.gpio_speed_high" configurationId="p406.gpio_drivecapacity"/>
+      <configSetting altId="p406.gpio_mode.gpio_mode_peripheral" configurationId="p406.gpio_mode"/>
+      <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
+      <configSetting altId="p407.gpio_speed.gpio_speed_high" configurationId="p407.gpio_drivecapacity"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p408.output.low" configurationId="p408"/>
+      <configSetting altId="p408.gpio_speed.gpio_speed_high" configurationId="p408.gpio_drivecapacity"/>
+      <configSetting altId="p408.gpio_mode.gpio_mode_out.low" configurationId="p408.gpio_mode"/>
+      <configSetting altId="p409.input" configurationId="p409"/>
+      <configSetting altId="p409.gpio_irq.gpio_irq_enabled" configurationId="p409.gpio_irq"/>
+      <configSetting altId="p409.gpio_mode.gpio_mode_in" configurationId="p409.gpio_mode"/>
+      <configSetting altId="p409.gpio_pupd.gpio_pupd_ip_up" configurationId="p409.gpio_pupd"/>
+      <configSetting altId="p410.spi1.miso" configurationId="p410"/>
+      <configSetting altId="p410.gpio_speed.gpio_speed_high" configurationId="p410.gpio_drivecapacity"/>
+      <configSetting altId="p410.gpio_mode.gpio_mode_peripheral" configurationId="p410.gpio_mode"/>
+      <configSetting altId="p411.spi1.mosi" configurationId="p411"/>
+      <configSetting altId="p411.gpio_speed.gpio_speed_high" configurationId="p411.gpio_drivecapacity"/>
+      <configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
+      <configSetting altId="p412.spi1.rspck" configurationId="p412"/>
+      <configSetting altId="p412.gpio_speed.gpio_speed_high" configurationId="p412.gpio_drivecapacity"/>
+      <configSetting altId="p412.gpio_mode.gpio_mode_peripheral" configurationId="p412.gpio_mode"/>
+      <configSetting altId="p413.spi1.ssl0" configurationId="p413"/>
+      <configSetting altId="p413.gpio_speed.gpio_speed_high" configurationId="p413.gpio_drivecapacity"/>
+      <configSetting altId="p413.gpio_mode.gpio_mode_peripheral" configurationId="p413.gpio_mode"/>
+      <configSetting altId="p414.iic2.sda" configurationId="p414"/>
+      <configSetting altId="p414.gpio_speed.gpio_speed_high" configurationId="p414.gpio_drivecapacity"/>
+      <configSetting altId="p414.gpio_mode.gpio_mode_peripheral" configurationId="p414.gpio_mode"/>
+      <configSetting altId="p415.iic2.scl" configurationId="p415"/>
+      <configSetting altId="p415.gpio_speed.gpio_speed_high" configurationId="p415.gpio_drivecapacity"/>
+      <configSetting altId="p415.gpio_mode.gpio_mode_peripheral" configurationId="p415.gpio_mode"/>
+      <configSetting altId="p500.usbfs0.vbusen" configurationId="p500"/>
+      <configSetting altId="p500.gpio_speed.gpio_speed_high" configurationId="p500.gpio_drivecapacity"/>
+      <configSetting altId="p500.gpio_mode.gpio_mode_peripheral" configurationId="p500.gpio_mode"/>
+      <configSetting altId="p501.usbfs0.ovrcura" configurationId="p501"/>
+      <configSetting altId="p501.gpio_speed.gpio_speed_high" configurationId="p501.gpio_drivecapacity"/>
+      <configSetting altId="p501.gpio_mode.gpio_mode_peripheral" configurationId="p501.gpio_mode"/>
+      <configSetting altId="p505.sci6.scl" configurationId="p505"/>
+      <configSetting altId="p505.gpio_speed.gpio_speed_high" configurationId="p505.gpio_drivecapacity"/>
+      <configSetting altId="p505.gpio_mode.gpio_mode_peripheral" configurationId="p505.gpio_mode"/>
+      <configSetting altId="p505.gpio_otype.gpio_otype_n_ch_od" configurationId="p505.gpio_otype"/>
+      <configSetting altId="p506.sci6.sda" configurationId="p506"/>
+      <configSetting altId="p506.gpio_speed.gpio_speed_high" configurationId="p506.gpio_drivecapacity"/>
+      <configSetting altId="p506.gpio_mode.gpio_mode_peripheral" configurationId="p506.gpio_mode"/>
+      <configSetting altId="p506.gpio_otype.gpio_otype_n_ch_od" configurationId="p506.gpio_otype"/>
+      <configSetting altId="p511.iic1.sda" configurationId="p511"/>
+      <configSetting altId="p511.gpio_speed.gpio_speed_high" configurationId="p511.gpio_drivecapacity"/>
+      <configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/>
+      <configSetting altId="p512.iic1.scl" configurationId="p512"/>
+      <configSetting altId="p512.gpio_speed.gpio_speed_high" configurationId="p512.gpio_drivecapacity"/>
+      <configSetting altId="p512.gpio_mode.gpio_mode_peripheral" configurationId="p512.gpio_mode"/>
+      <configSetting altId="p600.ospi0.omsio4" configurationId="p600"/>
+      <configSetting altId="p600.gpio_speed.gpio_speed_highspeedhigh" configurationId="p600.gpio_drivecapacity"/>
+      <configSetting altId="p600.gpio_mode.gpio_mode_peripheral" configurationId="p600.gpio_mode"/>
+      <configSetting altId="p601.ospi0.omsio2" configurationId="p601"/>
+      <configSetting altId="p601.gpio_speed.gpio_speed_highspeedhigh" configurationId="p601.gpio_drivecapacity"/>
+      <configSetting altId="p601.gpio_mode.gpio_mode_peripheral" configurationId="p601.gpio_mode"/>
+      <configSetting altId="p602.ospi0.omcs1" configurationId="p602"/>
+      <configSetting altId="p602.gpio_mode.gpio_mode_peripheral" configurationId="p602.gpio_mode"/>
+      <configSetting altId="p608.output.low" configurationId="p608"/>
+      <configSetting altId="p608.gpio_speed.gpio_speed_high" configurationId="p608.gpio_drivecapacity"/>
+      <configSetting altId="p608.gpio_mode.gpio_mode_out.low" configurationId="p608.gpio_mode"/>
+      <configSetting altId="p609.can1.ctx" configurationId="p609"/>
+      <configSetting altId="p609.gpio_mode.gpio_mode_peripheral" configurationId="p609.gpio_mode"/>
+      <configSetting altId="p610.can1.crx" configurationId="p610"/>
+      <configSetting altId="p610.gpio_mode.gpio_mode_peripheral" configurationId="p610.gpio_mode"/>
+      <configSetting altId="p611.output.low" configurationId="p611"/>
+      <configSetting altId="p611.gpio_speed.gpio_speed_high" configurationId="p611.gpio_drivecapacity"/>
+      <configSetting altId="p611.gpio_mode.gpio_mode_out.low" configurationId="p611.gpio_mode"/>
+      <configSetting altId="p613.sci7.txd" configurationId="p613"/>
+      <configSetting altId="p613.gpio_mode.gpio_mode_peripheral" configurationId="p613.gpio_mode"/>
+      <configSetting altId="p614.sci7.rxd" configurationId="p614"/>
+      <configSetting altId="p614.gpio_mode.gpio_mode_peripheral" configurationId="p614.gpio_mode"/>
+      <configSetting altId="p615.output.high" configurationId="p615"/>
+      <configSetting altId="p615.gpio_speed.gpio_speed_medium" configurationId="p615.gpio_drivecapacity"/>
+      <configSetting altId="p615.gpio_mode.gpio_mode_out.high" configurationId="p615.gpio_mode"/>
+      <configSetting altId="p700.etherc0.rmii.txd0" configurationId="p700"/>
+      <configSetting altId="p700.gpio_speed.gpio_speed_high" configurationId="p700.gpio_drivecapacity"/>
+      <configSetting altId="p700.gpio_mode.gpio_mode_peripheral" configurationId="p700.gpio_mode"/>
+      <configSetting altId="p701.etherc0.rmii.ref50ck" configurationId="p701"/>
+      <configSetting altId="p701.gpio_speed.gpio_speed_high" configurationId="p701.gpio_drivecapacity"/>
+      <configSetting altId="p701.gpio_mode.gpio_mode_peripheral" configurationId="p701.gpio_mode"/>
+      <configSetting altId="p702.etherc0.rmii.rxd0" configurationId="p702"/>
+      <configSetting altId="p702.gpio_speed.gpio_speed_high" configurationId="p702.gpio_drivecapacity"/>
+      <configSetting altId="p702.gpio_mode.gpio_mode_peripheral" configurationId="p702.gpio_mode"/>
+      <configSetting altId="p703.etherc0.rmii.rxd1" configurationId="p703"/>
+      <configSetting altId="p703.gpio_speed.gpio_speed_high" configurationId="p703.gpio_drivecapacity"/>
+      <configSetting altId="p703.gpio_mode.gpio_mode_peripheral" configurationId="p703.gpio_mode"/>
+      <configSetting altId="p704.etherc0.rmii.rx_er" configurationId="p704"/>
+      <configSetting altId="p704.gpio_speed.gpio_speed_high" configurationId="p704.gpio_drivecapacity"/>
+      <configSetting altId="p704.gpio_mode.gpio_mode_peripheral" configurationId="p704.gpio_mode"/>
+      <configSetting altId="p705.etherc0.rmii.crs_dv" configurationId="p705"/>
+      <configSetting altId="p705.gpio_speed.gpio_speed_high" configurationId="p705.gpio_drivecapacity"/>
+      <configSetting altId="p705.gpio_mode.gpio_mode_peripheral" configurationId="p705.gpio_mode"/>
+      <configSetting altId="p706.input" configurationId="p706"/>
+      <configSetting altId="p706.gpio_irq.gpio_irq_enabled" configurationId="p706.gpio_irq"/>
+      <configSetting altId="p706.gpio_mode.gpio_mode_in" configurationId="p706.gpio_mode"/>
+      <configSetting altId="p707.usbhs0.ovrcura" configurationId="p707"/>
+      <configSetting altId="p707.gpio_mode.gpio_mode_peripheral" configurationId="p707.gpio_mode"/>
+      <configSetting altId="p708.spi1.ssl3" configurationId="p708"/>
+      <configSetting altId="p708.gpio_speed.gpio_speed_high" configurationId="p708.gpio_drivecapacity"/>
+      <configSetting altId="p708.gpio_mode.gpio_mode_peripheral" configurationId="p708.gpio_mode"/>
+      <configSetting altId="p905.input" configurationId="p905"/>
+      <configSetting altId="p905.gpio_irq.gpio_irq_enabled" configurationId="p905.gpio_irq"/>
+      <configSetting altId="p905.gpio_mode.gpio_mode_in" configurationId="p905.gpio_mode"/>
+      <configSetting altId="p905.gpio_pupd.gpio_pupd_ip_up" configurationId="p905.gpio_pupd"/>
+      <configSetting altId="pb00.usbhs0.vbusen" configurationId="pb00"/>
+      <configSetting altId="pb00.gpio_speed.gpio_speed_high" configurationId="pb00.gpio_drivecapacity"/>
+      <configSetting altId="pb00.gpio_mode.gpio_mode_peripheral" configurationId="pb00.gpio_mode"/>
+      <configSetting altId="pb01.usbhs0.vbus" configurationId="pb01"/>
+      <configSetting altId="pb01.gpio_speed.gpio_speed_high" configurationId="pb01.gpio_drivecapacity"/>
+      <configSetting altId="pb01.gpio_mode.gpio_mode_peripheral" configurationId="pb01.gpio_mode"/>
+      <configSetting altId="qspi0.mode.quad.free" configurationId="qspi0.mode"/>
+      <configSetting altId="qspi0.pairing.free" configurationId="qspi0.pairing"/>
+      <configSetting altId="qspi0.qio0.p307" configurationId="qspi0.qio0"/>
+      <configSetting altId="qspi0.qio1.p308" configurationId="qspi0.qio1"/>
+      <configSetting altId="qspi0.qio2.p309" configurationId="qspi0.qio2"/>
+      <configSetting altId="qspi0.qio3.p310" configurationId="qspi0.qio3"/>
+      <configSetting altId="qspi0.qspclk.p305" configurationId="qspi0.qspclk"/>
+      <configSetting altId="qspi0.qssl.p306" configurationId="qspi0.qssl"/>
+      <configSetting altId="sci6.mode.iic.free" configurationId="sci6.mode"/>
+      <configSetting altId="sci6.scl.p505" configurationId="sci6.scl"/>
+      <configSetting altId="sci6.sda.p506" configurationId="sci6.sda"/>
+      <configSetting altId="sci7.mode.asynchronous.free" configurationId="sci7.mode"/>
+      <configSetting altId="sci7.rxd.p614" configurationId="sci7.rxd"/>
+      <configSetting altId="sci7.txd.p613" configurationId="sci7.txd"/>
+      <configSetting altId="spi0.miso.p202" configurationId="spi0.miso"/>
+      <configSetting altId="spi0.mode.custom.free" configurationId="spi0.mode"/>
+      <configSetting altId="spi0.mosi.p203" configurationId="spi0.mosi"/>
+      <configSetting altId="spi0.pairing.free" configurationId="spi0.pairing"/>
+      <configSetting altId="spi0.rspck.p204" configurationId="spi0.rspck"/>
+      <configSetting altId="spi0.ssl0.p205" configurationId="spi0.ssl0"/>
+      <configSetting altId="spi0.ssl1.p206" configurationId="spi0.ssl1"/>
+      <configSetting altId="spi0.ssl2.p301" configurationId="spi0.ssl2"/>
+      <configSetting altId="spi0.ssl3.p302" configurationId="spi0.ssl3"/>
+      <configSetting altId="spi1.miso.p410" configurationId="spi1.miso"/>
+      <configSetting altId="spi1.mode.enabled.free" configurationId="spi1.mode"/>
+      <configSetting altId="spi1.mosi.p411" configurationId="spi1.mosi"/>
+      <configSetting altId="spi1.pairing.free" configurationId="spi1.pairing"/>
+      <configSetting altId="spi1.rspck.p412" configurationId="spi1.rspck"/>
+      <configSetting altId="spi1.ssl0.p413" configurationId="spi1.ssl0"/>
+      <configSetting altId="spi1.ssl3.p708" configurationId="spi1.ssl3"/>
+      <configSetting altId="trace0.mode.trace4bit" configurationId="trace0.mode"/>
+      <configSetting altId="trace0.tclk.p214" configurationId="trace0.tclk"/>
+      <configSetting altId="trace0.tdata0.p211" configurationId="trace0.tdata0"/>
+      <configSetting altId="trace0.tdata1.p210" configurationId="trace0.tdata1"/>
+      <configSetting altId="trace0.tdata2.p209" configurationId="trace0.tdata2"/>
+      <configSetting altId="trace0.tdata3.p208" configurationId="trace0.tdata3"/>
+      <configSetting altId="usbfs0.mode.custom" configurationId="usbfs0.mode"/>
+      <configSetting altId="usbfs0.ovrcura.p501" configurationId="usbfs0.ovrcura"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
+      <configSetting altId="usbfs0.vbusen.p500" configurationId="usbfs0.vbusen"/>
+      <configSetting altId="usbhs0.mode.custom" configurationId="usbhs0.mode"/>
+      <configSetting altId="usbhs0.ovrcura.p707" configurationId="usbhs0.ovrcura"/>
+      <configSetting altId="usbhs0.vbus.pb01" configurationId="usbhs0.vbus"/>
+      <configSetting altId="usbhs0.vbusen.pb00" configurationId="usbhs0.vbusen"/>
+    </pincfg>
+    <pincfg active="false" name="R7FA6M5BH3CFC.pincfg" selected="false" symbol="">
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.cmake b/hw/bsp/ra/boards/ra8m1_ek/board.cmake
new file mode 100644
index 000000000..c61166f38
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/board.cmake
@@ -0,0 +1,16 @@
+set(CMAKE_SYSTEM_CPU cortex-m85 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra8m1)
+
+set(JLINK_DEVICE R7FA8M1AH)
+#set(JLINK_OPTION "-USB 001083115236")
+
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.h b/hw/bsp/ra/boards/ra8m1_ek/board.h
new file mode 100644
index 000000000..54672452f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/board.h
@@ -0,0 +1,47 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: RA8M1 EK
+   url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8m1-evaluation-kit-ra8m1-mcu-group
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_STATE_ON          1
+#define BUTTON_STATE_ACTIVE   0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.mk b/hw/bsp/ra/boards/ra8m1_ek/board.mk
new file mode 100644
index 000000000..2e56b3781
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/board.mk
@@ -0,0 +1,11 @@
+CPU_CORE = cortex-m85
+MCU_VARIANT = ra8m1
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA8M1AH
+
+# Port 1 is highspeed
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex b/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex
new file mode 100644
index 000000000..70dd323ec
Binary files /dev/null and b/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex differ
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug b/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug
new file mode 100644
index 000000000..242a15db9
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug
@@ -0,0 +1,231 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetDevice ("R7FA8M1AH");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M85F.svd");
+  Project.AddSvdFile ("../../../../../../../cmsis-svd-data/data/Renesas/R7FA6M5BH.svd");
+
+  File.Open ("../../../../../../examples/cmake-build-ra8m1_ek/device/cdc_msc/cdc_msc.elf");
+}
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+	//Project.SetJLinkScript("../../../debug.jlinkscript");
+  Project.SetJLinkScript ("$(ProjectDir)/Renesas_RA8_TracePins.pex");
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  _SetupTarget();
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetResume
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetResume (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotLoad
+*
+* Function description
+*   Called upon loading a snapshot. Optional.
+*
+* Additional information
+*   This function is used to restore the target state in cases
+*   where values cannot simply be written to the target.
+*   Typical use: GPIO clock needs to be enabled, before
+*   GPIO is configured.
+*
+**********************************************************************
+*/
+//void OnSnapshotLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotSave
+*
+* Function description
+*   Called upon saving a snapshot. Optional.
+*
+* Additional information
+*   This function is usually used to save values of the target
+*   state which can either not be trivially read,
+*   or need to be restored in a specific way or order.
+*   Typically use: Memory Mapped Registers,
+*   such as PLL and GPIO configuration.
+*
+**********************************************************************
+*/
+//void OnSnapshotSave (void) {
+//}
+
+/*********************************************************************
+*
+*       OnError
+*
+* Function description
+*   Called when an error occurred. Optional.
+*
+**********************************************************************
+*/
+//void OnError (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterProjectLoad
+*
+* Function description
+*   After Project load routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterProjectLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       _SetupTarget
+*
+* Function description
+*   Setup the target.
+*   Called by AfterTargetReset() and AfterTargetDownload().
+*
+*   Auto-generated function. May be overridden by Ozone.
+*
+**********************************************************************
+*/
+void _SetupTarget(void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+  //
+  // Set up initial stack pointer
+  //
+  SP = Target.ReadU32(VectorTableAddr);
+  if (SP != 0xFFFFFFFF) {
+    Target.SetReg("SP", SP);
+  }
+  //
+  // Set up entry point PC
+  //
+  PC = Elf.GetEntryPointPC();
+  if (PC != 0xFFFFFFFF) {
+    Target.SetReg("PC", PC);
+  } else {
+    Util.Error("Project script error: failed to set up entry point PC", 1);
+  }
+}
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..90afbdef3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define RA_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #ifndef BSP_CFG_RTC_USED
+             #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+            #endif
+            #undef RA_NOT_DEFINED
+            #if defined(_RA_BOOT_IMAGE)
+             #define BSP_CFG_BOOT_IMAGE (1)
+            #endif
+            #define BSP_CFG_MCU_VCC_MV (3300)
+            #define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+            #define BSP_CFG_HEAP_BYTES (0x1000)
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PFS_PROTECT ((1))
+
+            #define BSP_CFG_C_RUNTIME_INIT ((1))
+            #define BSP_CFG_EARLY_INIT     ((0))
+
+            #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+            #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+            #endif
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+            #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+            #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+            #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+            #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..92e7ddcdb
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (8)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..a22da075d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA8M1AHECBD
+      #define BSP_MCU_FEATURE_SET ('A')
+      #define BSP_ROM_SIZE_BYTES (2064384)
+      #define BSP_RAM_SIZE_BYTES (917504)
+      #define BSP_DATA_FLASH_SIZE_BYTES (12288)
+      #define BSP_PACKAGE_BGA
+      #define BSP_PACKAGE_PINS (224)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..94f09c61f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,526 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_MCU_GROUP_RA8M1 (1)
+            #define BSP_LOCO_HZ                 (32768)
+            #define BSP_MOCO_HZ                 (8000000)
+            #define BSP_SUB_CLOCK_HZ            (0)
+            #if   BSP_CFG_HOCO_FREQUENCY == 0
+                #define BSP_HOCO_HZ                 (16000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 1
+                #define BSP_HOCO_HZ                 (18000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ                 (20000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 4
+                #define BSP_HOCO_HZ                 (32000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 7
+                #define BSP_HOCO_HZ                 (48000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+
+            #define BSP_CFG_FLL_ENABLE                   (0)
+
+            #define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE  (1)
+            #define BSP_CFG_SLEEP_MODE_DELAY_ENABLE      (1)
+            #define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE     (1)
+            #define BSP_CFG_RTOS_IDLE_SLEEP           (0)
+            #define BSP_CFG_CLOCK_SETTLING_DELAY_US      (150)
+
+            #if defined(BSP_PACKAGE_LQFP) && (BSP_PACKAGE_PINS == 100)
+                #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (180000000U)
+            #elif defined(BSP_PACKAGE_LQFP)
+                #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (200000000U)
+            #else
+                #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (240000000U)
+            #endif
+
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
+            #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (1)
+
+            #if defined(_RA_TZ_SECURE)
+            #define BSP_TZ_SECURE_BUILD           (1)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #elif defined(_RA_TZ_NONSECURE)
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (1)
+            #else
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #endif
+
+            /* TrustZone Settings */
+            #define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+            #define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+            #define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
+
+            /* CMSIS TrustZone Settings */
+            #define SCB_CSR_AIRCR_INIT                (1)
+            #define SCB_AIRCR_BFHFNMINS_VAL           (0)
+            #define SCB_AIRCR_SYSRESETREQS_VAL        (1)
+            #define SCB_AIRCR_PRIS_VAL                (0)
+            #define TZ_FPU_NS_USAGE                   (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+            #define SCB_NSACR_CP10_11_VAL             (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+            #define FPU_FPCCR_TS_VAL                  (1U)
+#endif
+            #define FPU_FPCCR_CLRONRETS_VAL           (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+            #define FPU_FPCCR_CLRONRET_VAL            (1)
+#endif
+
+            /* Type 1 Peripheral Security Attribution */
+
+            /* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* USBHS */ | \
+            (1 << 15) /* ETHERC/EDMAC */ | \
+            (1 << 16) /* OSPI */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */)
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* SDHI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP-E51A */)
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* AGT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* AGT0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC121 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC120 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */)
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* RTC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* GPT13 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* GPT12 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* GPT11 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* GPT10 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */)
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* DTC_DMAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */)
+#endif
+
+            /* Type 2 Peripheral Security Attribution */
+
+            /* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0x00000007U)
+#endif
+
+            /* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+            /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */
+#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0)
+#define BSP_TZ_CFG_LVDSAR (0U)
+#else
+#define BSP_TZ_CFG_LVDSAR (3U)
+#endif
+#endif
+
+            /* Security attribution for LPM registers.
+             * - OPCCR based on clock security.
+             * - Set remaining registers based on LPM security.
+             */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\
+                                                  0x002E0106U | \
+                                                  (BSP_CFG_CLOCKS_SECURE == 0)))
+#endif
+            /* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0U : 0xAF1FFFFFU)
+#endif
+            /* RAM Standby Control Security Attribution Register. */
+#ifndef BSP_TZ_CFG_RSCSAR
+#define BSP_TZ_CFG_RSCSAR ((RA_NOT_DEFINED > 0) ? 0U : 0x00037FFFU)
+#endif
+
+            /* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0x047F3BFDU)
+#endif
+#endif
+
+            /* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#if 0
+#define BSP_TZ_CFG_BBFSAR   (0U)
+#else
+#define BSP_TZ_CFG_BBFSAR   (0x1FU)
+#endif
+#endif
+
+            /* Security attribution for Battery Backup registers (VBTBKRn). */
+#ifndef BSP_TZ_CFG_VBRSABAR
+#if 0
+#define BSP_TZ_CFG_VBRSABAR (0xFFE0)
+#else
+#define BSP_TZ_CFG_VBRSABAR (0xED00)
+#endif
+#endif
+
+            /* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */)
+#endif
+
+            /* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0U) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+            /* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_DMACCHSAR
+#define BSP_TZ_CFG_DMACCHSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */)
+#endif
+
+            /* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0U : 0xFF1D0000U)
+#endif
+
+            /* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0U : 0x00007F08U)
+#endif
+
+            /* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently Trusted Event Route Control is not supported. */
+#ifndef BSP_TZ_CFG_TEVTRCR
+#define BSP_TZ_CFG_TEVTRCR (0)
+#endif
+
+            /* Security attribution register for ELCR, ELSEGR0, ELSEGR1 Security Attribution. */
+#ifndef BSP_TZ_CFG_ELCSARA
+ #define BSP_TZ_CFG_ELCSARA (0x00000007U)
+#endif
+
+            /* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+ #define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+            /* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#define BSP_TZ_CFG_FSAR (\
+        ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */\
+        ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 1)) | /* FCACHESA */\
+        ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \
+        ((RA_NOT_DEFINED) > 0 ? 0U : (1U << 9U)) | /* FACICMISA */\
+        ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 10U)) /* FACICMRSA */)
+#endif
+
+            /* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+    #define BSP_TZ_CFG_SRAMSAR (\
+        ((1U) << 0U) | /* SRAMSA0 */\
+        ((1U) << 1U) | /* SRAMSA1 */\
+        ((1U) << 7U) | /* STBRAMSA */\
+        ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */)
+#endif
+
+            /* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+    /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+    #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR)
+#endif
+
+            /* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+    #define BSP_TZ_CFG_BUSSARA (1U)
+#endif
+            /* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+    #define BSP_TZ_CFG_BUSSARB (1U)
+#endif
+            /* Security Attribution Register C for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARC
+    #define BSP_TZ_CFG_BUSSARC (1U)
+#endif
+
+            /* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+    #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+
+            #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+            #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+            #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+            #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+            #define OFS_SEQ5 (1 << 28) | (1 << 30)
+            #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+            #define BSP_CFG_ROM_REG_OFS2 ((1 << 0) | 0xFFFFFFFEU)
+
+            /* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U)))
+#else
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U)
+#endif
+#endif
+            #define BSP_CFG_ROM_REG_OFS1_INITECCEN (0 << 25)
+            #define BSP_CFG_ROM_REG_OFS1 (0xFCFFFED0 | (1 << 3) | (7) | (1 << 5) |  (1 << 8) | (1 << 24) | (BSP_CFG_ROM_REG_OFS1_INITECCEN))
+
+            /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+            #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+            /* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+            #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+#endif
+
+            /* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+            #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+            /* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+            #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+            /* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+            #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+#endif
+            /* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+            #define BSP_CFG_ROM_REG_BPS3 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+            #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+            #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+            #define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+#endif
+            /* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+            #define BSP_CFG_ROM_REG_PBPS3 (~( 0U))
+#endif
+            /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+            #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+            /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+            #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+            /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+            #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+            /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+            #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+            /* Security Attribution for Bank Select Register */
+#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
+            #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+            #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+            /* FSBL Control Register 0 */
+#ifndef BSP_CFG_ROM_REG_FSBLCTRL0
+#define BSP_CFG_ROM_REG_FSBLCTRL0 ( \
+                (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos) | \
+                (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos) | \
+                (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos) | \
+                (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos) | \
+                0xFFFFF000)
+#endif
+
+            /* FSBL Control Register 1 */
+#ifndef BSP_CFG_ROM_REG_FSBLCTRL1
+#define BSP_CFG_ROM_REG_FSBLCTRL1 ( \
+                (3 << R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos) | \
+                0xFFFFFFFC)
+#endif
+
+            /* FSBL Control Register 2 */
+#ifndef BSP_CFG_ROM_REG_FSBLCTRL2
+#define BSP_CFG_ROM_REG_FSBLCTRL2 ( \
+                (15 << R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos) | \
+                (0x1F << R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos) | \
+                0xFFFFFE00)
+#endif
+
+            /* Start Address of Code Certificate Register 0 */
+#ifndef BSP_CFG_ROM_REG_SACC0
+#define BSP_CFG_ROM_REG_SACC0 (0xFFFFFFFF)
+#endif
+
+            /* Start Address of Code Certificate Register 1 */
+#ifndef BSP_CFG_ROM_REG_SACC1
+#define BSP_CFG_ROM_REG_SACC1 (0xFFFFFFFF)
+#endif
+
+            /* Start Address of Measurement Report Register */
+#ifndef BSP_CFG_ROM_REG_SAMR
+#define BSP_CFG_ROM_REG_SAMR (0xFFFFFFFF)
+#endif
+
+#ifndef BSP_CFG_DCACHE_ENABLED
+#define BSP_CFG_DCACHE_ENABLED (0)
+#endif
+
+
+#ifndef BSP_CFG_SDRAM_ENABLED
+ #define BSP_CFG_SDRAM_ENABLED  (0)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TRAS
+ #define BSP_CFG_SDRAM_TRAS  (6)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TRCD
+ #define BSP_CFG_SDRAM_TRCD  (3)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TRP
+ #define BSP_CFG_SDRAM_TRP  (3)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TWR
+ #define BSP_CFG_SDRAM_TWR  (2)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TCL
+ #define BSP_CFG_SDRAM_TCL  (3)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TRFC
+ #define BSP_CFG_SDRAM_TRFC  (937)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TREFW
+ #define BSP_CFG_SDRAM_TREFW  (8)
+#endif
+
+#ifndef BSP_CFG_SDRAM_INIT_ARFI
+ #define BSP_CFG_SDRAM_INIT_ARFI  (10)
+#endif
+
+#ifndef BSP_CFG_SDRAM_INIT_ARFC
+ #define BSP_CFG_SDRAM_INIT_ARFC  (8)
+#endif
+
+#ifndef BSP_CFG_SDRAM_INIT_PRC
+ #define BSP_CFG_SDRAM_INIT_PRC  (3)
+#endif
+
+#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
+ #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT  (1)
+#endif
+
+#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
+ #define BSP_CFG_SDRAM_ENDIAN_MODE  (0)
+#endif
+
+#ifndef BSP_CFG_SDRAM_ACCESS_MODE
+ #define BSP_CFG_SDRAM_ACCESS_MODE  (1)
+#endif
+
+#ifndef BSP_CFG_SDRAM_BUS_WIDTH
+ #define BSP_CFG_SDRAM_BUS_WIDTH  (0)
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..883363437
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,127 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define ENET_RMII_INT (BSP_IO_PORT_00_PIN_00)
+#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_01)
+#define GROVE2_AN102 (BSP_IO_PORT_00_PIN_02)
+#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_03)
+#define ARDUINO_A0_MIKROBUS_AN000 (BSP_IO_PORT_00_PIN_04)
+#define GROVE2_AN001 (BSP_IO_PORT_00_PIN_05)
+#define PMOD1_IRQ11 (BSP_IO_PORT_00_PIN_06)
+#define ARDUINO_A004 (BSP_IO_PORT_00_PIN_07)
+#define USER_S2 (BSP_IO_PORT_00_PIN_08)
+#define SW1 (BSP_IO_PORT_00_PIN_09)
+#define MIKROBUS_IRQ14 (BSP_IO_PORT_00_PIN_10)
+#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14)
+#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15)
+#define OSPI_DQ0 (BSP_IO_PORT_01_PIN_00)
+#define OSPI_DQ3 (BSP_IO_PORT_01_PIN_01)
+#define OSPI_DQ4 (BSP_IO_PORT_01_PIN_02)
+#define OSPI_DQ2 (BSP_IO_PORT_01_PIN_03)
+#define OSPI_CS (BSP_IO_PORT_01_PIN_04)
+#define OSPI_INT (BSP_IO_PORT_01_PIN_05)
+#define OSPI_RESET (BSP_IO_PORT_01_PIN_06)
+#define LED3 (BSP_IO_PORT_01_PIN_07)
+#define ETH_A_RMII_RMII_RXDV (BSP_IO_PORT_01_PIN_12)
+#define ETH_A_LINKSTA (BSP_IO_PORT_01_PIN_14)
+#define MPLX_CTRL (BSP_IO_PORT_01_PIN_15)
+#define NMI (BSP_IO_PORT_02_PIN_00)
+#define MD (BSP_IO_PORT_02_PIN_01)
+#define CAN_STB (BSP_IO_PORT_02_PIN_07)
+#define TDI (BSP_IO_PORT_02_PIN_08)
+#define TDO (BSP_IO_PORT_02_PIN_09)
+#define SWDIO (BSP_IO_PORT_02_PIN_10)
+#define SWCLK (BSP_IO_PORT_02_PIN_11)
+#define EXTAL (BSP_IO_PORT_02_PIN_12)
+#define XTAL (BSP_IO_PORT_02_PIN_13)
+#define ETH_A_RXER (BSP_IO_PORT_03_PIN_00)
+#define ETH_A_RXD1 (BSP_IO_PORT_03_PIN_01)
+#define ETH_A_RXD0 (BSP_IO_PORT_03_PIN_02)
+#define ETH_A_REFCLK (BSP_IO_PORT_03_PIN_03)
+#define ETH_A_TXD0 (BSP_IO_PORT_03_PIN_04)
+#define ETH_A_TXD1 (BSP_IO_PORT_03_PIN_05)
+#define ETH_A_TXEN (BSP_IO_PORT_03_PIN_06)
+#define ETH_A_MDIO (BSP_IO_PORT_03_PIN_07)
+#define ETH_A_MDC (BSP_IO_PORT_03_PIN_08)
+#define ARDUINO_D0_MIKROBUS_RXD3 (BSP_IO_PORT_03_PIN_09)
+#define ARDUINO_D1_MIKROBUS_TXD3 (BSP_IO_PORT_03_PIN_10)
+#define CAN_RXD (BSP_IO_PORT_03_PIN_11)
+#define CAN_TXD (BSP_IO_PORT_03_PIN_12)
+#define I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic (BSP_IO_PORT_04_PIN_00)
+#define I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic (BSP_IO_PORT_04_PIN_01)
+#define ETH_B_MDIO (BSP_IO_PORT_04_PIN_02)
+#define ETH_B_LINKSTA (BSP_IO_PORT_04_PIN_03)
+#define ETH_B_RST_N (BSP_IO_PORT_04_PIN_04)
+#define ETH_B_TXEN (BSP_IO_PORT_04_PIN_05)
+#define ETH_B_TXD1 (BSP_IO_PORT_04_PIN_06)
+#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07)
+#define USBHS_VBUSEN (BSP_IO_PORT_04_PIN_08)
+#define USBHS_OVRCURA (BSP_IO_PORT_04_PIN_09)
+#define MISOB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_10)
+#define MOSIB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_11)
+#define RSPCKB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_12)
+#define SSLB0_B_ARDUINO_D10_MIKROBUS (BSP_IO_PORT_04_PIN_13)
+#define LED2 (BSP_IO_PORT_04_PIN_14)
+#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00)
+#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01)
+#define MIKROBUS_RESET (BSP_IO_PORT_05_PIN_02)
+#define PMOD2_7_IRQ1 (BSP_IO_PORT_05_PIN_08)
+#define GROVE2_IIC_SDA1 (BSP_IO_PORT_05_PIN_11)
+#define GROVE2_IIC_SCL1 (BSP_IO_PORT_05_PIN_12)
+#define LED1 (BSP_IO_PORT_06_PIN_00)
+#define ARDUINO_D5 (BSP_IO_PORT_06_PIN_01)
+#define ARDUINO_D6 (BSP_IO_PORT_06_PIN_02)
+#define ARDUINO_D9 (BSP_IO_PORT_06_PIN_03)
+#define PMOD1_3_MISO0_RXD0_SCL0 (BSP_IO_PORT_06_PIN_09)
+#define PMOD1_2_MOSI0_TXD0 (BSP_IO_PORT_06_PIN_10)
+#define PMOD1_4_SCK0 (BSP_IO_PORT_06_PIN_11)
+#define PMOD1_1_SSL0_CTS_RTS (BSP_IO_PORT_06_PIN_12)
+#define PMOD1_1_CTS0 (BSP_IO_PORT_06_PIN_13)
+#define PMOD1_9_GPIO (BSP_IO_PORT_06_PIN_14)
+#define PMOD1_10_GPIO (BSP_IO_PORT_06_PIN_15)
+#define ETH_B_TXD0 (BSP_IO_PORT_07_PIN_00)
+#define ETH_B_REFCLK (BSP_IO_PORT_07_PIN_01)
+#define ETH_B_RXD0 (BSP_IO_PORT_07_PIN_02)
+#define ETH_B_RXD1 (BSP_IO_PORT_07_PIN_03)
+#define ETH_B_RXER (BSP_IO_PORT_07_PIN_04)
+#define ETH_B_RMII_RXDV (BSP_IO_PORT_07_PIN_05)
+#define I3C_SDA0_PULLUP (BSP_IO_PORT_07_PIN_11)
+#define OSPI_DQ5 (BSP_IO_PORT_08_PIN_00)
+#define OSPI_DS (BSP_IO_PORT_08_PIN_01)
+#define OSPI_DQ6 (BSP_IO_PORT_08_PIN_02)
+#define OSPI_DQ1 (BSP_IO_PORT_08_PIN_03)
+#define OSPI_DQ7 (BSP_IO_PORT_08_PIN_04)
+#define OSPI_CK (BSP_IO_PORT_08_PIN_08)
+#define PMOD2_8_RESET (BSP_IO_PORT_08_PIN_09)
+#define PMOD2_9_GPIO (BSP_IO_PORT_08_PIN_10)
+#define PMOD2_10_GPIO (BSP_IO_PORT_08_PIN_11)
+#define ARDUINO_RESET (BSP_IO_PORT_08_PIN_12)
+#define USBFS_P (BSP_IO_PORT_08_PIN_14)
+#define USBFS_N (BSP_IO_PORT_08_PIN_15)
+#define ARDUINO_D4 (BSP_IO_PORT_09_PIN_05)
+#define ARDUINO_D2 (BSP_IO_PORT_09_PIN_06)
+#define ARDUINO_D3_MIKROBUS_GTIOC13A (BSP_IO_PORT_09_PIN_07)
+#define ARDUINO_D7 (BSP_IO_PORT_09_PIN_08)
+#define ARDUINO_D8 (BSP_IO_PORT_09_PIN_09)
+#define PMOD2_3_MISO2_RXD2 (BSP_IO_PORT_10_PIN_02)
+#define PMOD2_2_MOSI2_TXD2 (BSP_IO_PORT_10_PIN_03)
+#define PMOD2_4_SCK2 (BSP_IO_PORT_10_PIN_04)
+#define PMOD2_1_CTS_RTS_SSL2 (BSP_IO_PORT_10_PIN_05)
+#define PMOD2_1_CTS2 (BSP_IO_PORT_10_PIN_06)
+#define PMOD1_8_RESET (BSP_IO_PORT_10_PIN_08)
+#define JLOB_COMS_TX (BSP_IO_PORT_10_PIN_14)
+#define JLOB_COMS_RX (BSP_IO_PORT_10_PIN_15)
+#define I3C_SCL0_PULLUP (BSP_IO_PORT_11_PIN_00)
+#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA8M1 EK */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..d2688bf5b
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 000000000..f2f1ae0c9
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,56 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (7) /* HOCO 48MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL Mul x80-99|Mul x96|PLL Mul x96.00 */
+#define BSP_CFG_PLL_FREQUENCY_HZ (960000000) /* PLL 960000000Hz */
+#define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */
+#define BSP_CFG_PLL1P_FREQUENCY_HZ (480000000) /* PLL1P 480000000Hz */
+#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_4) /* PLL1Q Div /4 */
+#define BSP_CFG_PLL1Q_FREQUENCY_HZ (240000000) /* PLL1Q 240000000Hz */
+#define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL1R Div /2 */
+#define BSP_CFG_PLL1R_FREQUENCY_HZ (480000000) /* PLL1R 480000000Hz */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL2 Mul x80-99|Mul x96|PLL2 Mul x96.00 */
+#define BSP_CFG_PLL2_FREQUENCY_HZ (0) /* PLL2 0Hz */
+#define BSP_CFG_PL2ODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL2P Div /2 */
+#define BSP_CFG_PLL2P_FREQUENCY_HZ (0) /* PLL2P 0Hz */
+#define BSP_CFG_PL2ODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL2Q Div /2 */
+#define BSP_CFG_PLL2Q_FREQUENCY_HZ (0) /* PLL2Q 0Hz */
+#define BSP_CFG_PL2ODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL2R Div /2 */
+#define BSP_CFG_PLL2R_FREQUENCY_HZ (0) /* PLL2R 0Hz */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* Clock Src: PLL1P */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_SCICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SCICLK Disabled */
+#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
+#define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* I3CCLK Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* UCK Src: PLL1Q */
+#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* U60CK Src: PLL1P */
+#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
+#define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKA Div /4 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKB Div /8 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKC Div /8 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */
+#define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKE Div /2 */
+#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* BCLK Div /4 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* FCLK Div /8 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_SCICLK_DIV (BSP_CLOCKS_SCI_CLOCK_DIV_4) /* SCICLK Div /4 */
+#define BSP_CFG_SPICLK_DIV (BSP_CLOCKS_SPI_CLOCK_DIV_4) /* SPICLK Div /4 */
+#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_8) /* CANFDCLK Div /8 */
+#define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_3) /* I3CCLK Div /3 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCK Div /5 */
+#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_8) /* U60CK Div /8 */
+#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_4) /* OCTASPICLK Div /4 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c
new file mode 100644
index 000000000..50036c0ad
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h
new file mode 100644
index 000000000..6a08cbee0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c
new file mode 100644
index 000000000..b92421739
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c
@@ -0,0 +1,275 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_00_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_10,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_10,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_13,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_12,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_09,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_02,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_03,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_04,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_05,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_06,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+    },
+    {
+        .pin = BSP_IO_PORT_11_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+    }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld
new file mode 100644
index 000000000..d7f78a915
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld
@@ -0,0 +1,823 @@
+/*
+                  Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+OPTION_SETTING_DATA_FLASH_S_START = DEFINED(OPTION_SETTING_DATA_FLASH_S_START) ? OPTION_SETTING_DATA_FLASH_S_START : 0;
+OPTION_SETTING_DATA_FLASH_S_LENGTH = DEFINED(OPTION_SETTING_DATA_FLASH_S_LENGTH) ? OPTION_SETTING_DATA_FLASH_S_LENGTH : 0;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_DATA_FLASH = PROJECT_SECURE_OR_FLAT && (OPTION_SETTING_DATA_FLASH_S_LENGTH != 0);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                          FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END    = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START    = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START   = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                            FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                            __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                           FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                           FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+                XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+                FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+                       DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+                       FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+                            OPTION_SETTING_LENGTH == 0 ? 0 :
+                            OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+  ITCM (rx)                       : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+  DTCM (rwx)                      : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+  FLASH (rx)                      : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+  RAM (rwx)                       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx)                 : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx)                 : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx)              : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx)              : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  OSPI_DEVICE_0_RAM (rwx)         : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1_RAM (rwx)         : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)                     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r)              : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_OFS (r)          : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+  OPTION_SETTING_SAS (r)          : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+  OPTION_SETTING_S (r)            : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+  OPTION_SETTING_DATA_FLASH_S (r) : ORIGIN = OPTION_SETTING_DATA_FLASH_S_START, LENGTH = OPTION_SETTING_DATA_FLASH_S_LENGTH
+  ID_CODE (rx)                    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* Some devices have a gap of code flash between the vector table and ROM Registers.
+         * The flash gap section allows applications to place code and data in this section. */
+        *(.flash_gap*)
+
+        /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+        /* Allocate flash write-boundary-aligned
+         * space for sce9 wrapped public keys for mcuboot if the module is used.
+         */
+        KEEP(*(.mcuboot_sce9_key*))
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    . = .;
+    __itcm_data_pre_location = .;
+
+    /* Initialized ITCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .itcm_data : ALIGN(16)
+    {
+        /* Start of ITCM Secure Trustzone region. */
+        __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+        /* All ITCM data start */
+        __itcm_data_start = .;
+
+        KEEP(*(.itcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* All ITCM data end */
+        __itcm_data_end = .;
+
+        /*
+         * Start of the ITCM Non-Secure Trustzone region.
+         * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+    } > ITCM AT > FLASH = 0x00
+
+    /* Addresses exported for ITCM initialization. */
+    __itcm_data_init_start = LOADADDR(.itcm_data);
+    __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+    ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+    /* Restore location counter. */
+    /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+    . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+    __exidx_start = .;
+    /DISCARD/ :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    }
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    . = .;
+    __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+    /* Initialized DTCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .dtcm_data : ALIGN(16)
+    {
+        /* Start of DTCM Secure Trustzone region. */
+        __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+        /* Initialized DTCM data start */
+        __dtcm_data_start = .;
+
+        KEEP(*(.dtcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* Initialized DTCM data end */
+        __dtcm_data_end = .;
+    } > DTCM AT > FLASH = 0x00
+
+    . = __dtcm_data_end;
+    /* Uninitialized DTCM data. */
+    /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+    .dtcm_bss ALIGN(8) (NOLOAD) :
+    {
+        /* Uninitialized DTCM data start */
+        __dtcm_bss_start = .;
+
+        KEEP(*(.dtcm_bss*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+        . = ALIGN(8);
+
+        /* Uninitialized DTCM data end */
+        __dtcm_bss_end = .;
+
+        /*
+         * Start of the DTCM Non-Secure Trustzone region.
+         * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+         */
+        __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+    } > DTCM
+
+    /* Addresses exported for DTCM initialization. */
+    __dtcm_data_init_start = LOADADDR(.dtcm_data);
+    __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+    ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+    ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+    ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+    ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+    /* Restore location counter. */
+    /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+    . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+    /* TrustZone Secure Gateway Stubs Section */
+
+    /* Store location counter for SPI non-retentive sections. */
+    sgstubs_pre_location = .;
+
+    /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+    SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+    .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+    {
+        __FLASH_NSC_START = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+    FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = sgstubs_pre_location;
+    .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Support for OctaRAM */
+    .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_0_start__ = .;
+        *(.ospi_device_0_no_load*)
+        . = ALIGN(4);
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0_RAM
+
+    .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_1_start__ = .;
+        *(.ospi_device_1_no_load*)
+        . = ALIGN(4);
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1_RAM
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+     __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+    .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+    .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    . = .;
+    __nocache_pre_location = .;
+    .nocache ALIGN(32) (NOLOAD):
+    {
+        __nocache_start = .;
+
+        KEEP(*(.nocache))
+
+        . = ALIGN(32);
+        __nocache_end = .;
+    } > RAM
+    . = (SIZEOF(.nocache) > 0) ? __nocache_end : __nocache_pre_location;
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __RAM_NSC_START = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(FLASH_BOOTLOADER_LENGTH) ? (RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH) : DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_NSC_START, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    . = .;
+    __nocache_sdram_pre_location = .;
+    .nocache_sdram ALIGN(32) (NOLOAD):
+    {
+        __nocache_sdram_start = .;
+
+        KEEP(*(.nocache_sdram))
+
+        . = ALIGN(32);
+        __nocache_sdram_end = .;
+    } > SDRAM
+    . = (SIZEOF(.nocache_sdram) > 0) ? __nocache_sdram_end : __nocache_sdram_pre_location;
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool.
+     *       Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+     *       memory region between TrustZone projects. */
+    __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+    .option_setting_ofs :
+    {
+        __OPTION_SETTING_OFS_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_ofs2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_dualsel))
+        __OPTION_SETTING_OFS_End = .;
+    } > OPTION_SETTING_OFS = 0xFF
+
+    .option_setting_sas :
+    {
+        __OPTION_SETTING_SAS_Start = .;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_SAS_End = .;
+    } > OPTION_SETTING_SAS = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_ofs3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps3))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel3))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_DATA_FLASH_S_S = ORIGIN(OPTION_SETTING_DATA_FLASH_S);
+
+    .option_setting_data_flash_s :
+    {
+        __OPTION_SETTING_DATA_FLASH_S_Start = .;
+        KEEP(*(.option_setting_data_flash_fsblctrl0))
+        . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x04 : __OPTION_SETTING_DATA_FLASH_S_Start;
+        KEEP(*(.option_setting_data_flash_fsblctrl1))
+        . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x08 : __OPTION_SETTING_DATA_FLASH_S_Start;
+        KEEP(*(.option_setting_data_flash_fsblctrl2))
+        . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x0C : __OPTION_SETTING_DATA_FLASH_S_Start;
+        KEEP(*(.option_setting_data_flash_sacc0))
+        . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x10 : __OPTION_SETTING_DATA_FLASH_S_Start;
+        KEEP(*(.option_setting_data_flash_sacc1))
+        . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x14 : __OPTION_SETTING_DATA_FLASH_S_Start;
+        KEEP(*(.option_setting_data_flash_samr))
+        . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x2E0 : __OPTION_SETTING_DATA_FLASH_S_Start;
+        KEEP(*(.option_setting_data_flash_hoemrtpk))
+        __OPTION_SETTING_DATA_FLASH_S_End = .;
+    } > OPTION_SETTING_DATA_FLASH_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_DATA_FLASH_S_N = __OPTION_SETTING_DATA_FLASH_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld
new file mode 100644
index 000000000..2bc162511
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld
@@ -0,0 +1,30 @@
+
+            /* generated memory regions file - do not edit */
+                            RAM_START  = 0x22000000;
+                RAM_LENGTH = 0xE0000;
+                FLASH_START  = 0x02000000;
+                FLASH_LENGTH = 0x1F8000;
+                DATA_FLASH_START  = 0x27000000;
+                DATA_FLASH_LENGTH = 0x3000;
+                OPTION_SETTING_START  = 0x0300A100;
+                OPTION_SETTING_LENGTH = 0x100;
+                OPTION_SETTING_S_START  = 0x0300A200;
+                OPTION_SETTING_S_LENGTH = 0x100;
+                OPTION_SETTING_DATA_FLASH_S_START  = 0x27030080;
+                OPTION_SETTING_DATA_FLASH_S_LENGTH = 0x800;
+                ID_CODE_START  = 0x00000000;
+                ID_CODE_LENGTH = 0x0;
+                SDRAM_START  = 0x68000000;
+                SDRAM_LENGTH = 0x8000000;
+                QSPI_FLASH_START  = 0x60000000;
+                QSPI_FLASH_LENGTH = 0x0;
+                OSPI_DEVICE_0_START  = 0x80000000;
+                OSPI_DEVICE_0_LENGTH = 0x10000000;
+                OSPI_DEVICE_1_START  = 0x90000000;
+                OSPI_DEVICE_1_LENGTH = 0x10000000;
+                ITCM_START  = 0x00000000;
+                ITCM_LENGTH = 0x10000;
+                DTCM_START  = 0x20000000;
+                DTCM_LENGTH = 0x10000;
+                NS_OFFSET_START  = 0x10000000;
+                NS_OFFSET_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml
new file mode 100644
index 000000000..0f83b4a11
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml
@@ -0,0 +1,680 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.ra8m1ek"/>
+    <option key="CPU" value="RA8M1"/>
+    <option key="Core" value="CM85"/>
+    <option key="#TargetName#" value="R7FA8M1AHECBD"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m85"/>
+    <option key="#DeviceCommand#" value="R7FA8M1AH"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA8M1AHECBD.pincfg"/>
+    <option key="#FSPVersion#" value="5.6.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra8m1_ek##"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra8m1.R7FA8M1AHECBD">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="2064384"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.irq_count_hidden" value="96"/>
+    </config>
+    <config id="config.bsp.ra8m1">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra8m1.fsp">
+      <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
+      <property id="config.bsp.fsp.sdram.enabled" value="config.bsp.fsp.sdram.enabled.disabled"/>
+      <property id="config.bsp.fsp.sdram.tras" value="config.bsp.fsp.sdram.tras.6"/>
+      <property id="config.bsp.fsp.sdram.trcd" value="config.bsp.fsp.sdram.trcd.3"/>
+      <property id="config.bsp.fsp.sdram.trp" value="config.bsp.fsp.sdram.trp.3"/>
+      <property id="config.bsp.fsp.sdram.twr" value="config.bsp.fsp.sdram.twr.2"/>
+      <property id="config.bsp.fsp.sdram.tcl" value="config.bsp.fsp.sdram.tcl.3"/>
+      <property id="config.bsp.fsp.sdram.trfc" value="937"/>
+      <property id="config.bsp.fsp.sdram.trefw" value="config.bsp.fsp.sdram.trefw.8"/>
+      <property id="config.bsp.fsp.sdram.arfi" value="config.bsp.fsp.sdram.arfi.10"/>
+      <property id="config.bsp.fsp.sdram.arfc" value="config.bsp.fsp.sdram.arfc.8"/>
+      <property id="config.bsp.fsp.sdram.prc" value="config.bsp.fsp.sdram.prc.3"/>
+      <property id="config.bsp.fsp.sdram.addr_shift" value="config.bsp.fsp.sdram.addr_shift.9"/>
+      <property id="config.bsp.fsp.sdram.endian_mode" value="config.bsp.fsp.sdram.endian_mode.little"/>
+      <property id="config.bsp.fsp.sdram.continuous_access_mode" value="config.bsp.fsp.sdram.continuous_access_mode.enabled"/>
+      <property id="config.bsp.fsp.sdram.bus_width" value="config.bsp.fsp.sdram.bus_width.16"/>
+      <property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
+      <property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
+      <property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
+      <property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
+      <property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
+      <property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/>
+      <property id="config.bsp.fsp.tz.sramsar.sramsa0" value="config.bsp.fsp.tz.sramsar.sramsa0.both"/>
+      <property id="config.bsp.fsp.tz.sramsar.sramsa1" value="config.bsp.fsp.tz.sramsar.sramsa1.both"/>
+      <property id="config.bsp.fsp.tz.sramsar.stbramsa" value="config.bsp.fsp.tz.sramsar.stbramsa.both"/>
+      <property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
+      <property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
+      <property id="config.bsp.fsp.tz.bussarc" value="config.bsp.fsp.tz.bussarc.both"/>
+      <property id="config.bsp.fsp.tz.banksel_sel" value="config.bsp.fsp.tz.banksel_sel.both"/>
+      <property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
+      <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
+      <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/>
+      <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/>
+      <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.low_power_consumption" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.low_power_consumption.secure"/>
+      <property id="config.bsp.fsp.OFS1_SEL.swdbg" value="config.bsp.fsp.OFS1_SEL.swdbg.secure"/>
+      <property id="config.bsp.fsp.OFS1_SEL.initeccen" value="config.bsp.fsp.OFS1_SEL.initeccen.secure"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.160"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.low_power_consumption" value="config.bsp.fsp.OFS1.voltage_detection0.low_power_consumption.disabled"/>
+      <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
+      <property id="config.bsp.fsp.OFS1.swdbg" value="config.bsp.fsp.OFS1.swdbg.disabled"/>
+      <property id="config.bsp.fsp.OFS1.initeccen" value="config.bsp.fsp.OFS1.initeccen.disabled"/>
+      <property id="config.bsp.fsp.OFS2.dcdc" value="config.bsp.fsp.OFS2.dcdc.enabled"/>
+      <property id="config.bsp.fsp.BPS.BPS0" value=""/>
+      <property id="config.bsp.fsp.BPS.BPS1" value=""/>
+      <property id="config.bsp.fsp.BPS.BPS2" value=""/>
+      <property id="config.bsp.fsp.BPS.BPS3" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS2" value=""/>
+      <property id="config.bsp.fsp.PBPS.PBPS3" value=""/>
+      <property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/>
+      <property id="config.bsp.fsp.FSBLCTRL0.FSBLEN" value="config.bsp.fsp.FSBLCTRL0.FSBLEN.disabled"/>
+      <property id="config.bsp.fsp.FSBLCTRL0.FSBLSKIPSW" value="config.bsp.fsp.FSBLCTRL0.FSBLSKIPSW.disabled"/>
+      <property id="config.bsp.fsp.FSBLCTRL0.FSBLSKIPDS" value="config.bsp.fsp.FSBLCTRL0.FSBLSKIPDS.disabled"/>
+      <property id="config.bsp.fsp.FSBLCTRL0.FSBLCLK" value="config.bsp.fsp.FSBLCTRL0.FSBLCLK.240"/>
+      <property id="config.bsp.fsp.FSBLCTRL1.FSBLEXMD" value="config.bsp.fsp.FSBLCTRL1.FSBLEXMD.secure_report"/>
+      <property id="config.bsp.fsp.FSBLCTRL2.PORTPN" value="config.bsp.fsp.FSBLCTRL2.PORTPN.15"/>
+      <property id="config.bsp.fsp.FSBLCTRL2.PORTGN" value="config.bsp.fsp.FSBLCTRL2.PORTGN.reserved"/>
+      <property id="config.bsp.fsp.SACC0" value="0xFFFFFFFF"/>
+      <property id="config.bsp.fsp.SACC1" value="0xFFFFFFFF"/>
+      <property id="config.bsp.fsp.SAMR" value="0xFFFFFFFF"/>
+      <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
+      <property id="config.bsp.fsp.clock_settling_delay" value="config.bsp.fsp.clock_settling_delay.enabled"/>
+      <property id="config.bsp.fsp.sleep_mode_delays" value="config.bsp.fsp.sleep_mode_delays.enabled"/>
+      <property id="config.bsp.fsp.rtos_idle_sleep" value="config.bsp.fsp.rtos_idle_sleep.disabled"/>
+      <property id="config.bsp.fsp.mstp_change_delays" value="config.bsp.fsp.mstp_change_delays.enabled"/>
+      <property id="config.bsp.fsp.settling_delay_us" value="150"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="60000000"/>
+      <property id="config.bsp.fsp.mcu.sci_b_uart.max_baud" value="30000000"/>
+      <property id="config.bsp.fsp.mcu.sci_b_uart.ctspen_channels" value="0x021F"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="1"/>
+      <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="30000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="60000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0x3FFF"/>
+      <property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/>
+      <property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="2"/>
+      <property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="1216"/>
+      <property id="config.bsp.fsp.mcu.canfd.afl_rules" value="32"/>
+      <property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="16"/>
+      <property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="8"/>
+      <property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="32767"/>
+      <property id="config.bsp.fsp.mcu.sci_b_lin.max_baud" value="7500000"/>
+      <property id="config.bsp.fsp.dcache" value="config.bsp.fsp.dcache.disabled"/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x1000"/>
+      <property id="config.bsp.common.heap" value="0x1000"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="20000000" option="_edit"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
+    <node id="board.clock.pll.div" option="board.clock.pll.div.2"/>
+    <node id="board.clock.pll.mul" option="board.clock.pll.mul.96_00"/>
+    <node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
+    <node id="board.clock.pll1p.div" option="board.clock.pll1p.div.2"/>
+    <node id="board.clock.pll1p.display" option="board.clock.pll1p.display.value"/>
+    <node id="board.clock.pll1q.div" option="board.clock.pll1q.div.4"/>
+    <node id="board.clock.pll1q.display" option="board.clock.pll1q.display.value"/>
+    <node id="board.clock.pll1r.div" option="board.clock.pll1r.div.2"/>
+    <node id="board.clock.pll1r.display" option="board.clock.pll1r.display.value"/>
+    <node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
+    <node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
+    <node id="board.clock.pll2.mul" option="board.clock.pll2.mul.96_00"/>
+    <node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
+    <node id="board.clock.pll2p.div" option="board.clock.pll2p.div.2"/>
+    <node id="board.clock.pll2p.display" option="board.clock.pll2p.display.value"/>
+    <node id="board.clock.pll2q.div" option="board.clock.pll2q.div.2"/>
+    <node id="board.clock.pll2q.display" option="board.clock.pll2q.display.value"/>
+    <node id="board.clock.pll2r.div" option="board.clock.pll2r.div.2"/>
+    <node id="board.clock.pll2r.display" option="board.clock.pll2r.display.value"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.pll1p"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.sciclk.source" option="board.clock.sciclk.source.disabled"/>
+    <node id="board.clock.spiclk.source" option="board.clock.spiclk.source.disabled"/>
+    <node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
+    <node id="board.clock.i3cclk.source" option="board.clock.i3cclk.source.disabled"/>
+    <node id="board.clock.uck.source" option="board.clock.uck.source.pll1q"/>
+    <node id="board.clock.u60ck.source" option="board.clock.u60ck.source.pll1p"/>
+    <node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
+    <node id="board.clock.cpuclk.div" option="board.clock.cpuclk.div.1"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
+    <node id="board.clock.pclka.div" option="board.clock.pclka.div.4"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.8"/>
+    <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.8"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.4"/>
+    <node id="board.clock.pclke.div" option="board.clock.pclke.div.2"/>
+    <node id="board.clock.sdclkout.enable" option="board.clock.sdclkout.enable.enabled"/>
+    <node id="board.clock.bclk.div" option="board.clock.bclk.div.4"/>
+    <node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.8"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.sciclk.div" option="board.clock.sciclk.div.4"/>
+    <node id="board.clock.spiclk.div" option="board.clock.spiclk.div.4"/>
+    <node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.8"/>
+    <node id="board.clock.i3cclk.div" option="board.clock.i3cclk.div.3"/>
+    <node id="board.clock.uck.div" option="board.clock.uck.div.5"/>
+    <node id="board.clock.u60ck.div" option="board.clock.u60ck.div.8"/>
+    <node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.4"/>
+    <node id="board.clock.cpuclk.display" option="board.clock.cpuclk.display.value"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.pclke.display" option="board.clock.pclke.display.value"/>
+    <node id="board.clock.sdclkout.display" option="board.clock.sdclkout.display.value"/>
+    <node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
+    <node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+    <node id="board.clock.sciclk.display" option="board.clock.sciclk.display.value"/>
+    <node id="board.clock.spiclk.display" option="board.clock.spiclk.display.value"/>
+    <node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
+    <node id="board.clock.i3cclk.display" option="board.clock.i3cclk.display.value"/>
+    <node id="board.clock.uck.display" option="board.clock.uck.display.value"/>
+    <node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
+    <node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0">
+      <description>Simple application that blinks an LED. No RTOS included.</description>
+      <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
+      <description>Arm CMSIS Version 6 - Core (M)</description>
+      <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra8m1_ek" variant="" vendor="Renesas" version="5.6.0">
+      <description>RA8M1-EK Board Support Files</description>
+      <originalPack>Renesas.RA_board_ra8m1_ek.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="device" variant="R7FA8M1AHECBD" vendor="Renesas" version="5.6.0">
+      <description>Board support package for R7FA8M1AHECBD</description>
+      <originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA8M1</description>
+      <originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA8M1 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA8M1 - Events</description>
+      <originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_usb_basic" variant="" vendor="Renesas" version="5.6.0">
+      <description>USB Basic</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_usb_pcdc" variant="" vendor="Renesas" version="5.6.0">
+      <description>USB Peripheral Communications Device Class</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <module id="module.driver.pcdc_on_usb.216998869">
+      <property id="module.driver.pcdc.name" value="g_pcdc0"/>
+    </module>
+    <module id="module.driver.basic_on_usb.877233012">
+      <property id="module.driver.basic.name" value="g_basic1"/>
+      <property id="module.driver.usb_basic.usb_mode" value="module.driver.usb_basic.usb_mode.host"/>
+      <property id="module.driver.usb_basic.usb_speed" value="module.driver.usb_basic.usb_speed.hs"/>
+      <property id="module.driver.usb_basic.usb_modulenumber" value="module.driver.usb_basic.usb_modulenumber.1"/>
+      <property id="module.driver.usb_basic.usb_classtype" value="module.driver.usb_basic.usb_classtype.pcdc"/>
+      <property id="module.driver.usb_basic.p_usb_reg" value="g_usb_descriptor"/>
+      <property id="module.driver.usb_basic.complience_cb" value="NULL"/>
+      <property id="module.driver.usb_basic.ipl" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.usb_basic.ipl_r" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.usb_basic.ipl_d0" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.usb_basic.ipl_d1" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.usb_basic.hsipl" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.usb_basic.hsipl_d0" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.usb_basic.hsipl_d1" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.usb_basic.rtos_callback" value="NULL"/>
+      <property id="module.driver.usb_basic.other_context" value="NULL"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+      <stack module="module.driver.pcdc_on_usb.216998869">
+        <stack module="module.driver.basic_on_usb.877233012" requires="module.driver.basic_on_usb.requires.basic"/>
+      </stack>
+    </context>
+    <config id="config.driver.usb_basic">
+      <property id="config.driver.usb_basic.param_checking_enable" value="config.driver.usb_basic.param_checking_enable.bsp"/>
+      <property id="config.driver.usb_basic.pll_clock_frequency" value="config.driver.usb_basic.pll_clock_frequency.20mhz"/>
+      <property id="config.driver.usb_basic.buswait" value="config.driver.usb_basic.buswait.7"/>
+      <property id="config.driver.usb_basic.bc_function" value="config.driver.usb_basic.bc_function.enable"/>
+      <property id="config.driver.usb_basic.power_source" value="config.driver.usb_basic.power_source.high"/>
+      <property id="config.driver.usb_basic.dcp_function" value="config.driver.usb_basic.dcp_function.disable"/>
+      <property id="config.driver.usb_basic.request" value="config.driver.usb_basic.request.enable"/>
+      <property id="config.driver.usb_basic.dblb" value="config.driver.usb_basic.dblb.enable"/>
+      <property id="config.driver.usb_basic.cntmd" value="config.driver.usb_basic.cntmd.disable"/>
+      <property id="config.driver.usb_basic.ldo_regulator" value="config.driver.usb_basic.ldo_regulator.disable"/>
+      <property id="config.driver.usb_basic.type_c" value="config.driver.usb_basic.type_c.disable"/>
+      <property id="config.driver.usb_basic.dma" value="config.driver.usb_basic.dma.disable"/>
+      <property id="config.driver.usb_basic.source_address" value="config.driver.usb_basic.source_address.none"/>
+      <property id="config.driver.usb_basic.dest_address" value="config.driver.usb_basic.dest_address.none"/>
+      <property id="config.driver.usb_basic.compliance_mode" value="config.driver.usb_basic.compliance_mode.disable"/>
+      <property id="config.driver.usb_basic.tpl_table" value="NULL"/>
+    </config>
+    <config id="config.driver.usb_pcdc">
+      <property id="config.driver.usb_pcdc.bulk_in" value="config.driver.usb_pcdc.bulk_in.pipe4"/>
+      <property id="config.driver.usb_pcdc.bulk_out" value="config.driver.usb_pcdc.bulk_out.pipe5"/>
+      <property id="config.driver.usb_pcdc.int_in" value="config.driver.usb_pcdc.int_in.pipe6"/>
+    </config>
+    <config id="config.driver.usb_pcdc_class"/>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p000.symbolic_name" value="ENET_RMII_INT"/>
+    <symbolicName propertyId="p001.symbolic_name" value="ARDUINO_A3"/>
+    <symbolicName propertyId="p002.symbolic_name" value="GROVE2_AN102"/>
+    <symbolicName propertyId="p003.symbolic_name" value="ARDUINO_A1"/>
+    <symbolicName propertyId="p004.symbolic_name" value="ARDUINO_A0_MIKROBUS_AN000"/>
+    <symbolicName propertyId="p005.symbolic_name" value="GROVE2_AN001"/>
+    <symbolicName propertyId="p006.symbolic_name" value="PMOD1_IRQ11"/>
+    <symbolicName propertyId="p007.symbolic_name" value="ARDUINO_A004"/>
+    <symbolicName propertyId="p008.symbolic_name" value="USER_S2"/>
+    <symbolicName propertyId="p009.symbolic_name" value="SW1"/>
+    <symbolicName propertyId="p010.symbolic_name" value="MIKROBUS_IRQ14"/>
+    <symbolicName propertyId="p014.symbolic_name" value="ARDUINO_A4"/>
+    <symbolicName propertyId="p015.symbolic_name" value="ARDUINO_A5"/>
+    <symbolicName propertyId="p100.symbolic_name" value="OSPI_DQ0"/>
+    <symbolicName propertyId="p101.symbolic_name" value="OSPI_DQ3"/>
+    <symbolicName propertyId="p102.symbolic_name" value="OSPI_DQ4"/>
+    <symbolicName propertyId="p103.symbolic_name" value="OSPI_DQ2"/>
+    <symbolicName propertyId="p104.symbolic_name" value="OSPI_CS"/>
+    <symbolicName propertyId="p105.symbolic_name" value="OSPI_INT"/>
+    <symbolicName propertyId="p106.symbolic_name" value="OSPI_RESET"/>
+    <symbolicName propertyId="p107.symbolic_name" value="LED3"/>
+    <symbolicName propertyId="p112.symbolic_name" value="ETH_A_RMII_RMII_RXDV"/>
+    <symbolicName propertyId="p114.symbolic_name" value="ETH_A_LINKSTA"/>
+    <symbolicName propertyId="p115.symbolic_name" value="MPLX_CTRL"/>
+    <symbolicName propertyId="p200.symbolic_name" value="NMI"/>
+    <symbolicName propertyId="p201.symbolic_name" value="MD"/>
+    <symbolicName propertyId="p207.symbolic_name" value="CAN_STB"/>
+    <symbolicName propertyId="p208.symbolic_name" value="TDI"/>
+    <symbolicName propertyId="p209.symbolic_name" value="TDO"/>
+    <symbolicName propertyId="p210.symbolic_name" value="SWDIO"/>
+    <symbolicName propertyId="p211.symbolic_name" value="SWCLK"/>
+    <symbolicName propertyId="p212.symbolic_name" value="EXTAL"/>
+    <symbolicName propertyId="p213.symbolic_name" value="XTAL"/>
+    <symbolicName propertyId="p300.symbolic_name" value="ETH_A_RXER"/>
+    <symbolicName propertyId="p301.symbolic_name" value="ETH_A_RXD1"/>
+    <symbolicName propertyId="p302.symbolic_name" value="ETH_A_RXD0"/>
+    <symbolicName propertyId="p303.symbolic_name" value="ETH_A_REFCLK"/>
+    <symbolicName propertyId="p304.symbolic_name" value="ETH_A_TXD0"/>
+    <symbolicName propertyId="p305.symbolic_name" value="ETH_A_TXD1"/>
+    <symbolicName propertyId="p306.symbolic_name" value="ETH_A_TXEN"/>
+    <symbolicName propertyId="p307.symbolic_name" value="ETH_A_MDIO"/>
+    <symbolicName propertyId="p308.symbolic_name" value="ETH_A_MDC"/>
+    <symbolicName propertyId="p309.symbolic_name" value="ARDUINO_D0_MIKROBUS_RXD3"/>
+    <symbolicName propertyId="p310.symbolic_name" value="ARDUINO_D1_MIKROBUS_TXD3"/>
+    <symbolicName propertyId="p311.symbolic_name" value="CAN_RXD"/>
+    <symbolicName propertyId="p312.symbolic_name" value="CAN_TXD"/>
+    <symbolicName propertyId="p400.symbolic_name" value="I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic"/>
+    <symbolicName propertyId="p401.symbolic_name" value="I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic"/>
+    <symbolicName propertyId="p402.symbolic_name" value="ETH_B_MDIO"/>
+    <symbolicName propertyId="p403.symbolic_name" value="ETH_B_LINKSTA"/>
+    <symbolicName propertyId="p404.symbolic_name" value="ETH_B_RST_N"/>
+    <symbolicName propertyId="p405.symbolic_name" value="ETH_B_TXEN"/>
+    <symbolicName propertyId="p406.symbolic_name" value="ETH_B_TXD1"/>
+    <symbolicName propertyId="p407.symbolic_name" value="USBFS_VBUS"/>
+    <symbolicName propertyId="p408.symbolic_name" value="USBHS_VBUSEN"/>
+    <symbolicName propertyId="p409.symbolic_name" value="USBHS_OVRCURA"/>
+    <symbolicName propertyId="p410.symbolic_name" value="MISOB_B_ARDUINO_MIKROBUS"/>
+    <symbolicName propertyId="p411.symbolic_name" value="MOSIB_B_ARDUINO_MIKROBUS"/>
+    <symbolicName propertyId="p412.symbolic_name" value="RSPCKB_B_ARDUINO_MIKROBUS"/>
+    <symbolicName propertyId="p413.symbolic_name" value="SSLB0_B_ARDUINO_D10_MIKROBUS"/>
+    <symbolicName propertyId="p414.symbolic_name" value="LED2"/>
+    <symbolicName propertyId="p500.symbolic_name" value="USBFS_VBUS_EN"/>
+    <symbolicName propertyId="p501.symbolic_name" value="USBFS_OVERCURA"/>
+    <symbolicName propertyId="p502.symbolic_name" value="MIKROBUS_RESET"/>
+    <symbolicName propertyId="p508.symbolic_name" value="PMOD2_7_IRQ1"/>
+    <symbolicName propertyId="p511.symbolic_name" value="GROVE2_IIC_SDA1"/>
+    <symbolicName propertyId="p512.symbolic_name" value="GROVE2_IIC_SCL1"/>
+    <symbolicName propertyId="p600.symbolic_name" value="LED1"/>
+    <symbolicName propertyId="p601.symbolic_name" value="ARDUINO_D5"/>
+    <symbolicName propertyId="p602.symbolic_name" value="ARDUINO_D6"/>
+    <symbolicName propertyId="p603.symbolic_name" value="ARDUINO_D9"/>
+    <symbolicName propertyId="p609.symbolic_name" value="PMOD1_3_MISO0_RXD0_SCL0"/>
+    <symbolicName propertyId="p610.symbolic_name" value="PMOD1_2_MOSI0_TXD0"/>
+    <symbolicName propertyId="p611.symbolic_name" value="PMOD1_4_SCK0"/>
+    <symbolicName propertyId="p612.symbolic_name" value="PMOD1_1_SSL0_CTS_RTS"/>
+    <symbolicName propertyId="p613.symbolic_name" value="PMOD1_1_CTS0"/>
+    <symbolicName propertyId="p614.symbolic_name" value="PMOD1_9_GPIO"/>
+    <symbolicName propertyId="p615.symbolic_name" value="PMOD1_10_GPIO"/>
+    <symbolicName propertyId="p700.symbolic_name" value="ETH_B_TXD0"/>
+    <symbolicName propertyId="p701.symbolic_name" value="ETH_B_REFCLK"/>
+    <symbolicName propertyId="p702.symbolic_name" value="ETH_B_RXD0"/>
+    <symbolicName propertyId="p703.symbolic_name" value="ETH_B_RXD1"/>
+    <symbolicName propertyId="p704.symbolic_name" value="ETH_B_RXER"/>
+    <symbolicName propertyId="p705.symbolic_name" value="ETH_B_RMII_RXDV"/>
+    <symbolicName propertyId="p711.symbolic_name" value="I3C_SDA0_PULLUP"/>
+    <symbolicName propertyId="p800.symbolic_name" value="OSPI_DQ5"/>
+    <symbolicName propertyId="p801.symbolic_name" value="OSPI_DS"/>
+    <symbolicName propertyId="p802.symbolic_name" value="OSPI_DQ6"/>
+    <symbolicName propertyId="p803.symbolic_name" value="OSPI_DQ1"/>
+    <symbolicName propertyId="p804.symbolic_name" value="OSPI_DQ7"/>
+    <symbolicName propertyId="p808.symbolic_name" value="OSPI_CK"/>
+    <symbolicName propertyId="p809.symbolic_name" value="PMOD2_8_RESET"/>
+    <symbolicName propertyId="p810.symbolic_name" value="PMOD2_9_GPIO"/>
+    <symbolicName propertyId="p811.symbolic_name" value="PMOD2_10_GPIO"/>
+    <symbolicName propertyId="p812.symbolic_name" value="ARDUINO_RESET"/>
+    <symbolicName propertyId="p814.symbolic_name" value="USBFS_P"/>
+    <symbolicName propertyId="p815.symbolic_name" value="USBFS_N"/>
+    <symbolicName propertyId="p905.symbolic_name" value="ARDUINO_D4"/>
+    <symbolicName propertyId="p906.symbolic_name" value="ARDUINO_D2"/>
+    <symbolicName propertyId="p907.symbolic_name" value="ARDUINO_D3_MIKROBUS_GTIOC13A"/>
+    <symbolicName propertyId="p908.symbolic_name" value="ARDUINO_D7"/>
+    <symbolicName propertyId="p909.symbolic_name" value="ARDUINO_D8"/>
+    <symbolicName propertyId="pa02.symbolic_name" value="PMOD2_3_MISO2_RXD2"/>
+    <symbolicName propertyId="pa03.symbolic_name" value="PMOD2_2_MOSI2_TXD2"/>
+    <symbolicName propertyId="pa04.symbolic_name" value="PMOD2_4_SCK2"/>
+    <symbolicName propertyId="pa05.symbolic_name" value="PMOD2_1_CTS_RTS_SSL2"/>
+    <symbolicName propertyId="pa06.symbolic_name" value="PMOD2_1_CTS2"/>
+    <symbolicName propertyId="pa08.symbolic_name" value="PMOD1_8_RESET"/>
+    <symbolicName propertyId="pa14.symbolic_name" value="JLOB_COMS_TX"/>
+    <symbolicName propertyId="pa15.symbolic_name" value="JLOB_COMS_RX"/>
+    <symbolicName propertyId="pb00.symbolic_name" value="I3C_SCL0_PULLUP"/>
+    <symbolicName propertyId="pb01.symbolic_name" value="USBHS_VBUS"/>
+    <pincfg active="true" name="RA8M1 EK" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="adc0.an000.p004" configurationId="adc0.an000"/>
+      <configSetting altId="adc0.an001.p005" configurationId="adc0.an001"/>
+      <configSetting altId="adc0.an004.p007" configurationId="adc0.an004"/>
+      <configSetting altId="adc0.an007.p014" configurationId="adc0.an007"/>
+      <configSetting altId="adc0.mode.custom.free" configurationId="adc0.mode"/>
+      <configSetting altId="adc1.an102.p002" configurationId="adc1.an102"/>
+      <configSetting altId="adc1.an104.p003" configurationId="adc1.an104"/>
+      <configSetting altId="adc1.an105.p015" configurationId="adc1.an105"/>
+      <configSetting altId="adc1.an106.p011" configurationId="adc1.an106"/>
+      <configSetting altId="adc1.mode.custom.free" configurationId="adc1.mode"/>
+      <configSetting altId="ether_rmii.pairing.a" configurationId="ether_rmii.pairing"/>
+      <configSetting altId="iic1.mode.enabled.a" configurationId="iic1.mode"/>
+      <configSetting altId="iic1.scl1.p512" configurationId="iic1.scl1"/>
+      <configSetting altId="iic1.sda1.p511" configurationId="iic1.sda1"/>
+      <configSetting altId="irq12.irq12_dash_ds.p008" configurationId="irq12.irq12_dash_ds"/>
+      <configSetting altId="irq12.mode.custom.free" configurationId="irq12.mode"/>
+      <configSetting altId="irq13.irq13_dash_ds.p009" configurationId="irq13.irq13_dash_ds"/>
+      <configSetting altId="irq13.mode.custom.free" configurationId="irq13.mode"/>
+      <configSetting altId="irq9.mode.custom.free" configurationId="irq9.mode"/>
+      <configSetting altId="jtag_fslash_swd.mode.swd.free" configurationId="jtag_fslash_swd.mode"/>
+      <configSetting altId="jtag_fslash_swd.swclk.p211" configurationId="jtag_fslash_swd.swclk"/>
+      <configSetting altId="jtag_fslash_swd.swdio.p210" configurationId="jtag_fslash_swd.swdio"/>
+      <configSetting altId="ospi.mode.custom.free" configurationId="ospi.mode"/>
+      <configSetting altId="ospi.om_cs1.p104" configurationId="ospi.om_cs1"/>
+      <configSetting altId="ospi.om_dqs.p801" configurationId="ospi.om_dqs"/>
+      <configSetting altId="ospi.om_ecsint1.p105" configurationId="ospi.om_ecsint1"/>
+      <configSetting altId="ospi.om_reset.p106" configurationId="ospi.om_reset"/>
+      <configSetting altId="ospi.om_sclk.p808" configurationId="ospi.om_sclk"/>
+      <configSetting altId="ospi.om_sio0.p100" configurationId="ospi.om_sio0"/>
+      <configSetting altId="ospi.om_sio1.p803" configurationId="ospi.om_sio1"/>
+      <configSetting altId="ospi.om_sio2.p103" configurationId="ospi.om_sio2"/>
+      <configSetting altId="ospi.om_sio3.p101" configurationId="ospi.om_sio3"/>
+      <configSetting altId="ospi.om_sio4.p102" configurationId="ospi.om_sio4"/>
+      <configSetting altId="ospi.om_sio5.p800" configurationId="ospi.om_sio5"/>
+      <configSetting altId="ospi.om_sio6.p802" configurationId="ospi.om_sio6"/>
+      <configSetting altId="ospi.om_sio7.p804" configurationId="ospi.om_sio7"/>
+      <configSetting altId="p000.input" configurationId="p000"/>
+      <configSetting altId="p000.gpio_mode.gpio_mode_in" configurationId="p000.gpio_mode"/>
+      <configSetting altId="p002.adc1.an102" configurationId="p002"/>
+      <configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/>
+      <configSetting altId="p003.adc1.an104" configurationId="p003"/>
+      <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
+      <configSetting altId="p004.adc0.an000" configurationId="p004"/>
+      <configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
+      <configSetting altId="p005.adc0.an001" configurationId="p005"/>
+      <configSetting altId="p005.gpio_mode.gpio_mode_an" configurationId="p005.gpio_mode"/>
+      <configSetting altId="p007.adc0.an004" configurationId="p007"/>
+      <configSetting altId="p007.gpio_mode.gpio_mode_an" configurationId="p007.gpio_mode"/>
+      <configSetting altId="p008.irq12.irq12_dash_ds" configurationId="p008"/>
+      <configSetting altId="p008.gpio_irq.gpio_irq_enabled" configurationId="p008.gpio_irq"/>
+      <configSetting altId="p008.gpio_mode.gpio_mode_irq" configurationId="p008.gpio_mode"/>
+      <configSetting altId="p009.irq13.irq13_dash_ds" configurationId="p009"/>
+      <configSetting altId="p009.gpio_irq.gpio_irq_enabled" configurationId="p009.gpio_irq"/>
+      <configSetting altId="p009.gpio_mode.gpio_mode_irq" configurationId="p009.gpio_mode"/>
+      <configSetting altId="p011.adc1.an106" configurationId="p011"/>
+      <configSetting altId="p011.gpio_mode.gpio_mode_an" configurationId="p011.gpio_mode"/>
+      <configSetting altId="p014.adc0.an007" configurationId="p014"/>
+      <configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/>
+      <configSetting altId="p015.adc1.an105" configurationId="p015"/>
+      <configSetting altId="p015.gpio_mode.gpio_mode_an" configurationId="p015.gpio_mode"/>
+      <configSetting altId="p100.ospi.om_sio0" configurationId="p100"/>
+      <configSetting altId="p100.gpio_speed.gpio_speed_hh" configurationId="p100.gpio_drivecapacity"/>
+      <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
+      <configSetting altId="p101.ospi.om_sio3" configurationId="p101"/>
+      <configSetting altId="p101.gpio_speed.gpio_speed_hh" configurationId="p101.gpio_drivecapacity"/>
+      <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
+      <configSetting altId="p102.ospi.om_sio4" configurationId="p102"/>
+      <configSetting altId="p102.gpio_speed.gpio_speed_hh" configurationId="p102.gpio_drivecapacity"/>
+      <configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
+      <configSetting altId="p103.ospi.om_sio2" configurationId="p103"/>
+      <configSetting altId="p103.gpio_speed.gpio_speed_hh" configurationId="p103.gpio_drivecapacity"/>
+      <configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
+      <configSetting altId="p104.ospi.om_cs1" configurationId="p104"/>
+      <configSetting altId="p104.gpio_speed.gpio_speed_h" configurationId="p104.gpio_drivecapacity"/>
+      <configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/>
+      <configSetting altId="p105.ospi.om_ecsint1" configurationId="p105"/>
+      <configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/>
+      <configSetting altId="p106.ospi.om_reset" configurationId="p106"/>
+      <configSetting altId="p106.gpio_mode.gpio_mode_peripheral" configurationId="p106.gpio_mode"/>
+      <configSetting altId="p107.output.low" configurationId="p107"/>
+      <configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/>
+      <configSetting altId="p209.trace.traceswo" configurationId="p209"/>
+      <configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/>
+      <configSetting altId="p210.jtag_fslash_swd.swdio" configurationId="p210"/>
+      <configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/>
+      <configSetting altId="p211.jtag_fslash_swd.swclk" configurationId="p211"/>
+      <configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/>
+      <configSetting altId="p304.trace.tdata3" configurationId="p304"/>
+      <configSetting altId="p304.gpio_mode.gpio_mode_peripheral" configurationId="p304.gpio_mode"/>
+      <configSetting altId="p305.trace.tdata2" configurationId="p305"/>
+      <configSetting altId="p305.gpio_mode.gpio_mode_peripheral" configurationId="p305.gpio_mode"/>
+      <configSetting altId="p306.trace.tdata1" configurationId="p306"/>
+      <configSetting altId="p306.gpio_mode.gpio_mode_peripheral" configurationId="p306.gpio_mode"/>
+      <configSetting altId="p307.trace.tdata0" configurationId="p307"/>
+      <configSetting altId="p307.gpio_mode.gpio_mode_peripheral" configurationId="p307.gpio_mode"/>
+      <configSetting altId="p308.trace.tclk" configurationId="p308"/>
+      <configSetting altId="p308.gpio_mode.gpio_mode_peripheral" configurationId="p308.gpio_mode"/>
+      <configSetting altId="p407.usbfs.usb_vbus" configurationId="p407"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p408.usbhs.usbhs_vbusen" configurationId="p408"/>
+      <configSetting altId="p408.gpio_mode.gpio_mode_peripheral" configurationId="p408.gpio_mode"/>
+      <configSetting altId="p409.usbhs.usbhs_ovrcura" configurationId="p409"/>
+      <configSetting altId="p409.gpio_mode.gpio_mode_peripheral" configurationId="p409.gpio_mode"/>
+      <configSetting altId="p410.spi1.miso1" configurationId="p410"/>
+      <configSetting altId="p410.gpio_speed.gpio_speed_h" configurationId="p410.gpio_drivecapacity"/>
+      <configSetting altId="p410.gpio_mode.gpio_mode_peripheral" configurationId="p410.gpio_mode"/>
+      <configSetting altId="p411.spi1.mosi1" configurationId="p411"/>
+      <configSetting altId="p411.gpio_speed.gpio_speed_h" configurationId="p411.gpio_drivecapacity"/>
+      <configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
+      <configSetting altId="p412.spi1.rspck1" configurationId="p412"/>
+      <configSetting altId="p412.gpio_speed.gpio_speed_h" configurationId="p412.gpio_drivecapacity"/>
+      <configSetting altId="p412.gpio_mode.gpio_mode_peripheral" configurationId="p412.gpio_mode"/>
+      <configSetting altId="p413.spi1.sslb0" configurationId="p413"/>
+      <configSetting altId="p413.gpio_speed.gpio_speed_h" configurationId="p413.gpio_drivecapacity"/>
+      <configSetting altId="p413.gpio_mode.gpio_mode_peripheral" configurationId="p413.gpio_mode"/>
+      <configSetting altId="p414.output.low" configurationId="p414"/>
+      <configSetting altId="p414.gpio_mode.gpio_mode_out.low" configurationId="p414.gpio_mode"/>
+      <configSetting altId="p500.usbfs.usb_vbusen" configurationId="p500"/>
+      <configSetting altId="p500.gpio_mode.gpio_mode_peripheral" configurationId="p500.gpio_mode"/>
+      <configSetting altId="p501.usbfs.usb_ovrcura" configurationId="p501"/>
+      <configSetting altId="p501.gpio_mode.gpio_mode_peripheral" configurationId="p501.gpio_mode"/>
+      <configSetting altId="p511.iic1.sda1" configurationId="p511"/>
+      <configSetting altId="p511.gpio_speed.gpio_speed_m" configurationId="p511.gpio_drivecapacity"/>
+      <configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/>
+      <configSetting altId="p512.iic1.scl1" configurationId="p512"/>
+      <configSetting altId="p512.gpio_speed.gpio_speed_m" configurationId="p512.gpio_drivecapacity"/>
+      <configSetting altId="p512.gpio_mode.gpio_mode_peripheral" configurationId="p512.gpio_mode"/>
+      <configSetting altId="p600.output.low" configurationId="p600"/>
+      <configSetting altId="p600.gpio_mode.gpio_mode_out.low" configurationId="p600.gpio_mode"/>
+      <configSetting altId="p800.ospi.om_sio5" configurationId="p800"/>
+      <configSetting altId="p800.gpio_speed.gpio_speed_hh" configurationId="p800.gpio_drivecapacity"/>
+      <configSetting altId="p800.gpio_mode.gpio_mode_peripheral" configurationId="p800.gpio_mode"/>
+      <configSetting altId="p801.ospi.om_dqs" configurationId="p801"/>
+      <configSetting altId="p801.gpio_speed.gpio_speed_hh" configurationId="p801.gpio_drivecapacity"/>
+      <configSetting altId="p801.gpio_mode.gpio_mode_peripheral" configurationId="p801.gpio_mode"/>
+      <configSetting altId="p802.ospi.om_sio6" configurationId="p802"/>
+      <configSetting altId="p802.gpio_speed.gpio_speed_hh" configurationId="p802.gpio_drivecapacity"/>
+      <configSetting altId="p802.gpio_mode.gpio_mode_peripheral" configurationId="p802.gpio_mode"/>
+      <configSetting altId="p803.ospi.om_sio1" configurationId="p803"/>
+      <configSetting altId="p803.gpio_speed.gpio_speed_hh" configurationId="p803.gpio_drivecapacity"/>
+      <configSetting altId="p803.gpio_mode.gpio_mode_peripheral" configurationId="p803.gpio_mode"/>
+      <configSetting altId="p804.ospi.om_sio7" configurationId="p804"/>
+      <configSetting altId="p804.gpio_speed.gpio_speed_hh" configurationId="p804.gpio_drivecapacity"/>
+      <configSetting altId="p804.gpio_mode.gpio_mode_peripheral" configurationId="p804.gpio_mode"/>
+      <configSetting altId="p808.ospi.om_sclk" configurationId="p808"/>
+      <configSetting altId="p808.gpio_speed.gpio_speed_hh" configurationId="p808.gpio_drivecapacity"/>
+      <configSetting altId="p808.gpio_mode.gpio_mode_peripheral" configurationId="p808.gpio_mode"/>
+      <configSetting altId="p809.output.low" configurationId="p809"/>
+      <configSetting altId="p809.gpio_mode.gpio_mode_out.low" configurationId="p809.gpio_mode"/>
+      <configSetting altId="p814.usbfs.usb_dp" configurationId="p814"/>
+      <configSetting altId="p814.gpio_mode.gpio_mode_peripheral" configurationId="p814.gpio_mode"/>
+      <configSetting altId="p815.usbfs.usb_dm" configurationId="p815"/>
+      <configSetting altId="p815.gpio_mode.gpio_mode_peripheral" configurationId="p815.gpio_mode"/>
+      <configSetting altId="pa02.sci2.rxd2" configurationId="pa02"/>
+      <configSetting altId="pa02.gpio_speed.gpio_speed_h" configurationId="pa02.gpio_drivecapacity"/>
+      <configSetting altId="pa02.gpio_mode.gpio_mode_peripheral" configurationId="pa02.gpio_mode"/>
+      <configSetting altId="pa03.sci2.txd2" configurationId="pa03"/>
+      <configSetting altId="pa03.gpio_speed.gpio_speed_h" configurationId="pa03.gpio_drivecapacity"/>
+      <configSetting altId="pa03.gpio_mode.gpio_mode_peripheral" configurationId="pa03.gpio_mode"/>
+      <configSetting altId="pa04.sci2.sck2" configurationId="pa04"/>
+      <configSetting altId="pa04.gpio_speed.gpio_speed_h" configurationId="pa04.gpio_drivecapacity"/>
+      <configSetting altId="pa04.gpio_mode.gpio_mode_peripheral" configurationId="pa04.gpio_mode"/>
+      <configSetting altId="pa05.sci2.cts_rts2" configurationId="pa05"/>
+      <configSetting altId="pa05.gpio_speed.gpio_speed_h" configurationId="pa05.gpio_drivecapacity"/>
+      <configSetting altId="pa05.gpio_mode.gpio_mode_peripheral" configurationId="pa05.gpio_mode"/>
+      <configSetting altId="pa06.input" configurationId="pa06"/>
+      <configSetting altId="pa06.gpio_mode.gpio_mode_in" configurationId="pa06.gpio_mode"/>
+      <configSetting altId="pa14.sci9.txd9" configurationId="pa14"/>
+      <configSetting altId="pa14.gpio_speed.gpio_speed_h" configurationId="pa14.gpio_drivecapacity"/>
+      <configSetting altId="pa14.gpio_mode.gpio_mode_peripheral" configurationId="pa14.gpio_mode"/>
+      <configSetting altId="pa15.sci9.rxd9" configurationId="pa15"/>
+      <configSetting altId="pa15.gpio_speed.gpio_speed_h" configurationId="pa15.gpio_drivecapacity"/>
+      <configSetting altId="pa15.gpio_mode.gpio_mode_peripheral" configurationId="pa15.gpio_mode"/>
+      <configSetting altId="pb01.usbhs.usbhs_vbus" configurationId="pb01"/>
+      <configSetting altId="pb01.gpio_speed.gpio_speed_h" configurationId="pb01.gpio_drivecapacity"/>
+      <configSetting altId="pb01.gpio_mode.gpio_mode_peripheral" configurationId="pb01.gpio_mode"/>
+      <configSetting altId="sci0.mode.custom.free" configurationId="sci0.mode"/>
+      <configSetting altId="sci1.mode.custom.free" configurationId="sci1.mode"/>
+      <configSetting altId="sci2.cts_rts2.pa05" configurationId="sci2.cts_rts2"/>
+      <configSetting altId="sci2.mode.custom.free" configurationId="sci2.mode"/>
+      <configSetting altId="sci2.rxd2.pa02" configurationId="sci2.rxd2"/>
+      <configSetting altId="sci2.sck2.pa04" configurationId="sci2.sck2"/>
+      <configSetting altId="sci2.txd2.pa03" configurationId="sci2.txd2"/>
+      <configSetting altId="sci4.mode.custom.free" configurationId="sci4.mode"/>
+      <configSetting altId="sci9.mode.custom.free" configurationId="sci9.mode"/>
+      <configSetting altId="sci9.rxd9.pa15" configurationId="sci9.rxd9"/>
+      <configSetting altId="sci9.txd9.pa14" configurationId="sci9.txd9"/>
+      <configSetting altId="spi1.miso1.p410" configurationId="spi1.miso1"/>
+      <configSetting altId="spi1.mode.custom.free" configurationId="spi1.mode"/>
+      <configSetting altId="spi1.mosi1.p411" configurationId="spi1.mosi1"/>
+      <configSetting altId="spi1.rspck1.p412" configurationId="spi1.rspck1"/>
+      <configSetting altId="spi1.sslb0.p413" configurationId="spi1.sslb0"/>
+      <configSetting altId="system.mode.custom.free" configurationId="system.mode"/>
+      <configSetting altId="trace.mode.custom.free" configurationId="trace.mode"/>
+      <configSetting altId="trace.tclk.p308" configurationId="trace.tclk"/>
+      <configSetting altId="trace.tdata0.p307" configurationId="trace.tdata0"/>
+      <configSetting altId="trace.tdata1.p306" configurationId="trace.tdata1"/>
+      <configSetting altId="trace.tdata2.p305" configurationId="trace.tdata2"/>
+      <configSetting altId="trace.tdata3.p304" configurationId="trace.tdata3"/>
+      <configSetting altId="trace.traceswo.p209" configurationId="trace.traceswo"/>
+      <configSetting altId="usbfs.mode.custom.free" configurationId="usbfs.mode"/>
+      <configSetting altId="usbfs.usb_dm.p815" configurationId="usbfs.usb_dm"/>
+      <configSetting altId="usbfs.usb_dp.p814" configurationId="usbfs.usb_dp"/>
+      <configSetting altId="usbfs.usb_ovrcura.p501" configurationId="usbfs.usb_ovrcura"/>
+      <configSetting altId="usbfs.usb_vbus.p407" configurationId="usbfs.usb_vbus"/>
+      <configSetting altId="usbfs.usb_vbusen.p500" configurationId="usbfs.usb_vbusen"/>
+      <configSetting altId="usbhs.mode.custom.free" configurationId="usbhs.mode"/>
+      <configSetting altId="usbhs.usbhs_ovrcura.p409" configurationId="usbhs.usbhs_ovrcura"/>
+      <configSetting altId="usbhs.usbhs_vbus.pb01" configurationId="usbhs.usbhs_vbus"/>
+      <configSetting altId="usbhs.usbhs_vbusen.p408" configurationId="usbhs.usbhs_vbusen"/>
+    </pincfg>
+    <pincfg active="false" name="R7FA8M1AHECBD.pincfg" selected="false" symbol="">
+      <configSetting altId="jtag_fslash_swd.mode.jtag.free" configurationId="jtag_fslash_swd.mode"/>
+      <configSetting altId="jtag_fslash_swd.tck.p211" configurationId="jtag_fslash_swd.tck"/>
+      <configSetting altId="jtag_fslash_swd.tdi.p208" configurationId="jtag_fslash_swd.tdi"/>
+      <configSetting altId="jtag_fslash_swd.tdo.p209" configurationId="jtag_fslash_swd.tdo"/>
+      <configSetting altId="jtag_fslash_swd.tms.p210" configurationId="jtag_fslash_swd.tms"/>
+      <configSetting altId="p208.jtag_fslash_swd.tdi" configurationId="p208"/>
+      <configSetting altId="p208.gpio_mode.gpio_mode_peripheral" configurationId="p208.gpio_mode"/>
+      <configSetting altId="p209.jtag_fslash_swd.tdo" configurationId="p209"/>
+      <configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/>
+      <configSetting altId="p210.jtag_fslash_swd.tms" configurationId="p210"/>
+      <configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/>
+      <configSetting altId="p211.jtag_fslash_swd.tck" configurationId="p211"/>
+      <configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake
new file mode 100644
index 000000000..735a93035
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.cmake
@@ -0,0 +1,9 @@
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m1)
+set(JLINK_DEVICE R7FA4M1AB)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/src/portable/mentor/musb/musb_tm4c.h b/hw/bsp/ra/boards/uno_r4/board.h
similarity index 82%
rename from src/portable/mentor/musb/musb_tm4c.h
rename to hw/bsp/ra/boards/uno_r4/board.h
index 65a1751b0..4e7ebb5ce 100644
--- a/src/portable/mentor/musb/musb_tm4c.h
+++ b/hw/bsp/ra/boards/uno_r4/board.h
@@ -1,7 +1,7 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,22 +24,23 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_MUSB_TM4C_H_
-#define _TUSB_MUSB_TM4C_H_
+/* metadata:
+   name: Arduino UNO R4
+   url: https://store-usa.arduino.cc/pages/uno-r4
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_TM4C123
-  #include "TM4C123.h"
-//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129
-#else
-  #error "Unsupported MCUs"
-#endif
+#define LED_STATE_ON         1
+#define BUTTON_STATE_ACTIVE  0
 
 #ifdef __cplusplus
- }
+}
 #endif
 
 #endif
diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk
new file mode 100644
index 000000000..f257c0000
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m4
+MCU_VARIANT = ra4m1
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M1AB
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..4eef62a0e
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define RA_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #ifndef BSP_CFG_RTC_USED
+             #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+            #endif
+            #undef RA_NOT_DEFINED
+            #if defined(_RA_BOOT_IMAGE)
+             #define BSP_CFG_BOOT_IMAGE (1)
+            #endif
+            #define BSP_CFG_MCU_VCC_MV (3300)
+            #define BSP_CFG_STACK_MAIN_BYTES (0x800)
+            #define BSP_CFG_HEAP_BYTES (0x1000)
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PFS_PROTECT ((1))
+
+            #define BSP_CFG_C_RUNTIME_INIT ((1))
+            #define BSP_CFG_EARLY_INIT     ((0))
+
+            #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+            #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0)
+            #endif
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+            #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+            #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+            #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+            #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..3f1d02b0d
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M1AB3CNE
+      #define BSP_MCU_FEATURE_SET ('A')
+      #define BSP_ROM_SIZE_BYTES (262144)
+      #define BSP_RAM_SIZE_BYTES (32768)
+      #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+      #define BSP_PACKAGE_QFN
+      #define BSP_PACKAGE_PINS (48)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..3d482b2b6
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,84 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_MCU_GROUP_RA4M1 (1)
+            #define BSP_LOCO_HZ                 (32768)
+            #define BSP_MOCO_HZ                 (8000000)
+            #define BSP_SUB_CLOCK_HZ            (32768)
+            #if   BSP_CFG_HOCO_FREQUENCY == 0
+                #define BSP_HOCO_HZ             (24000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ             (32000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 4
+                #define BSP_HOCO_HZ             (48000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 5
+                #define BSP_HOCO_HZ             (64000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
+            #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (1)
+
+            #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+            #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+            #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+            #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+            #define OFS_SEQ5 (1 << 28) | (1 << 30)
+            #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+            #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+            #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+            #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+            #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+            #endif
+            /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+            #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+            /*
+            ID Code
+            Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+            WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+            */
+            #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+            #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+            #else
+            /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+            #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..5440b293b
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define SW1 (BSP_IO_PORT_01_PIN_10) /* active low */
+#define LED1 (BSP_IO_PORT_01_PIN_11) /* active high */
+extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA4M1AB3CNE.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..d2688bf5b
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 000000000..559000a7a
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,21 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: Disabled */
+#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12U,0U) /* PLL Mul x12 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c
new file mode 100644
index 000000000..50036c0ad
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h
new file mode 100644
index 000000000..6a08cbee0
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c b/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c
new file mode 100644
index 000000000..58262de8b
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c
@@ -0,0 +1,75 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_01_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_10,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_11,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_14,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_15,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+    }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/uno_r4/script/fsp.ld b/hw/bsp/ra/boards/uno_r4/script/fsp.ld
new file mode 100644
index 000000000..605eef7d2
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+                  Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                          FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END    = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START    = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START   = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                            FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                            __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                           FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                           FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+                XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+                FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+                       DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+                       FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+                            OPTION_SETTING_LENGTH == 0 ? 0 :
+                            OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+  ITCM (rx)                       : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+  DTCM (rwx)                      : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+  FLASH (rx)                      : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+  RAM (rwx)                       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx)                 : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx)                 : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx)              : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx)              : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  OSPI_DEVICE_0_RAM (rwx)         : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1_RAM (rwx)         : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)                     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r)              : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_OFS (r)          : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+  OPTION_SETTING_SAS (r)          : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+  OPTION_SETTING_S (r)            : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+  ID_CODE (rx)                    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* Some devices have a gap of code flash between the vector table and ROM Registers.
+         * The flash gap section allows applications to place code and data in this section. */
+        *(.flash_gap*)
+
+        /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+        /* Allocate flash write-boundary-aligned
+         * space for sce9 wrapped public keys for mcuboot if the module is used.
+         */
+        KEEP(*(.mcuboot_sce9_key*))
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    . = .;
+    __itcm_data_pre_location = .;
+
+    /* Initialized ITCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .itcm_data : ALIGN(16)
+    {
+        /* Start of ITCM Secure Trustzone region. */
+        __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+        /* All ITCM data start */
+        __itcm_data_start = .;
+
+        KEEP(*(.itcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* All ITCM data end */
+        __itcm_data_end = .;
+
+        /*
+         * Start of the ITCM Non-Secure Trustzone region.
+         * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+    } > ITCM AT > FLASH = 0x00
+
+    /* Addresses exported for ITCM initialization. */
+    __itcm_data_init_start = LOADADDR(.itcm_data);
+    __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+    ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+    /* Restore location counter. */
+    /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+    . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+    __exidx_start = .;
+    /DISCARD/ :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    }
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    . = .;
+    __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+    /* Initialized DTCM data. */
+    /* Aligned to FCACHE2 for RA8. */
+    .dtcm_data : ALIGN(16)
+    {
+        /* Start of DTCM Secure Trustzone region. */
+        __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+        /* Initialized DTCM data start */
+        __dtcm_data_start = .;
+
+        KEEP(*(.dtcm_data*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+        . = ALIGN(8);
+
+        /* Initialized DTCM data end */
+        __dtcm_data_end = .;
+    } > DTCM AT > FLASH = 0x00
+
+    . = __dtcm_data_end;
+    /* Uninitialized DTCM data. */
+    /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+    .dtcm_bss ALIGN(8) (NOLOAD) :
+    {
+        /* Uninitialized DTCM data start */
+        __dtcm_bss_start = .;
+
+        KEEP(*(.dtcm_bss*))
+
+        /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+        . = ALIGN(8);
+
+        /* Uninitialized DTCM data end */
+        __dtcm_bss_end = .;
+
+        /*
+         * Start of the DTCM Non-Secure Trustzone region.
+         * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+         */
+        __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+    } > DTCM
+
+    /* Addresses exported for DTCM initialization. */
+    __dtcm_data_init_start = LOADADDR(.dtcm_data);
+    __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+    ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+    ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+    ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+    ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+    ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+    ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+    ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+    /* Restore location counter. */
+    /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+    /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+    . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+    /* TrustZone Secure Gateway Stubs Section */
+
+    /* Store location counter for SPI non-retentive sections. */
+    sgstubs_pre_location = .;
+
+    /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+    SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+    .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+    {
+        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+    FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = sgstubs_pre_location;
+    .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Support for OctaRAM */
+    .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_0_start__ = .;
+        *(.ospi_device_0_no_load*)
+        . = ALIGN(4);
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0_RAM
+
+    .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_1_start__ = .;
+        *(.ospi_device_1_no_load*)
+        . = ALIGN(4);
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1_RAM
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+     __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+    .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+    .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool.
+     *       Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+     *       memory region between TrustZone projects. */
+    __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+    .option_setting_ofs :
+    {
+        __OPTION_SETTING_OFS_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_ofs2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_dualsel))
+        __OPTION_SETTING_OFS_End = .;
+    } > OPTION_SETTING_OFS = 0xFF
+
+    .option_setting_sas :
+    {
+        __OPTION_SETTING_SAS_Start = .;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_SAS_End = .;
+    } > OPTION_SETTING_SAS = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_ofs3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps3))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel3))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld b/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld
new file mode 100644
index 000000000..22775395c
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld
@@ -0,0 +1,25 @@
+
+            /* generated memory regions file - do not edit */
+                            RAM_START  = 0x20000000;
+                RAM_LENGTH = 0x8000;
+                FLASH_START  = 0x00000000;
+                FLASH_LENGTH = 0x40000;
+                DATA_FLASH_START  = 0x40100000;
+                DATA_FLASH_LENGTH = 0x2000;
+                OPTION_SETTING_START  = 0x00000000;
+                OPTION_SETTING_LENGTH = 0x0;
+                OPTION_SETTING_S_START  = 0x80000000;
+                OPTION_SETTING_S_LENGTH = 0x0;
+                ID_CODE_START  = 0x01010018;
+                ID_CODE_LENGTH = 0x20;
+                SDRAM_START  = 0x80010000;
+                SDRAM_LENGTH = 0x0;
+                QSPI_FLASH_START  = 0x60000000;
+                QSPI_FLASH_LENGTH = 0x0;
+                OSPI_DEVICE_0_START  = 0x80020000;
+                OSPI_DEVICE_0_LENGTH = 0x0;
+                OSPI_DEVICE_1_START  = 0x80030000;
+                OSPI_DEVICE_1_LENGTH = 0x0;
+
+/* Uno R4 has bootloader */
+FLASH_IMAGE_START = 0x4000;
diff --git a/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml
new file mode 100644
index 000000000..b716c8ec9
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml
@@ -0,0 +1,218 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.custom"/>
+    <option key="CPU" value="RA4M1"/>
+    <option key="Core" value="CM4"/>
+    <option key="#TargetName#" value="R7FA4M1AB3CNE"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m4"/>
+    <option key="#DeviceCommand#" value="R7FA4M1AB"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA4M1AB3CNE.pincfg"/>
+    <option key="#FSPVersion#" value="5.6.0"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra4m1.R7FA4M1AB3CNE">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="262144"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.irq_count_hidden" value="32"/>
+    </config>
+    <config id="config.bsp.ra4m1">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra4m1.fsp">
+      <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
+      <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
+      <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/>
+      <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/>
+      <property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_start" value="0x00FFFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc0_end" value="0x00FFFFFF"/>
+      <property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc1_start" value="0x00FFFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc1_end" value="0x00FFFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg0_start" value="0x00FFFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg0_end" value="0x00FFFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="64000000"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="6666666"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
+      <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="1"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="12000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="24000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
+      <property id="config.bsp.fsp.mcu.slcdc.1_4_bias_method" value="1"/>
+      <property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
+      <property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
+      <property id="config.bsp.common.id1" value=""/>
+      <property id="config.bsp.common.id2" value=""/>
+      <property id="config.bsp.common.id3" value=""/>
+      <property id="config.bsp.common.id4" value=""/>
+      <property id="config.bsp.common.id_fixed" value=""/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x800"/>
+      <property id="config.bsp.common.heap" value="0x1000"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.disabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.disabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="0" option="_edit"/>
+    <node id="board.clock.pll.source" option="board.clock.pll.source.disabled"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.pll.div" option="board.clock.pll.div.4"/>
+    <node id="board.clock.pll.mul" option="board.clock.pll.mul.12"/>
+    <node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.hoco"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclka.div" option="board.clock.pclka.div.1"/>
+    <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.1"/>
+    <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+    <node id="board.clock.uclk.source" option="board.clock.uclk.source.hoco"/>
+    <node id="board.clock.uclk.display" option="board.clock.clkout.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
+      <description>Arm CMSIS Version 6 - Core (M)</description>
+      <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="5.6.0">
+      <description>Custom Board Support Files</description>
+      <originalPack>Renesas.RA_board_custom.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="R7FA4M1AB3CNE" vendor="Renesas" version="5.6.0">
+      <description>Board support package for R7FA4M1AB3CNE</description>
+      <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA4M1</description>
+      <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA4M1 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
+      <description>Board support package for RA4M1 - Events</description>
+      <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+    </context>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p110.symbolic_name" value="SW1"/>
+    <symbolicName propertyId="p111.symbolic_name" value="LED1"/>
+    <comment propertyId="p110.comment" value="active low"/>
+    <comment propertyId="p111.comment" value="active high"/>
+    <pincfg active="true" name="R7FA4M1AB3CNE.pincfg" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p110.input" configurationId="p110"/>
+      <configSetting altId="p110.gpio_mode.gpio_mode_in" configurationId="p110.gpio_mode"/>
+      <configSetting altId="p110.gpio_pupd.gpio_pupd_ip_up" configurationId="p110.gpio_pupd"/>
+      <configSetting altId="p111.output.low" configurationId="p111"/>
+      <configSetting altId="p111.gpio_mode.gpio_mode_out.low" configurationId="p111.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+      <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p914.usbfs0.usbdp" configurationId="p914"/>
+      <configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/>
+      <configSetting altId="p915.usbfs0.usbdm" configurationId="p915"/>
+      <configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/>
+      <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
+      <configSetting altId="usbfs0.usbdm.p915" configurationId="usbfs0.usbdm"/>
+      <configSetting altId="usbfs0.usbdp.p914" configurationId="usbfs0.usbdp"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/hw/bsp/ra/debug.jlinkscript b/hw/bsp/ra/debug.jlinkscript
new file mode 100644
index 000000000..b34cfaa7f
--- /dev/null
+++ b/hw/bsp/ra/debug.jlinkscript
@@ -0,0 +1,4 @@
+int SetupTarget(void) {
+  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x80000");
+  return 0;
+}
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
new file mode 100644
index 000000000..0fd24e493
--- /dev/null
+++ b/hw/bsp/ra/family.c
@@ -0,0 +1,252 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Rafael Silva
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: Renesas
+*/
+
+#include <stdio.h>
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#pragma GCC diagnostic ignored "-Wundef"
+#endif
+
+#include "common_data.h"
+#include "renesas.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY         (0xA500U)
+
+//--------------------------------------------------------------------+
+// Vector Data
+//--------------------------------------------------------------------+
+
+BSP_DONT_REMOVE BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS)
+const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] = {
+    [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
+    [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
+
+#ifndef BSP_MCU_GROUP_RA2A1
+    [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
+    [3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
+#endif
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+    [4] = usbhs_interrupt_handler, /* USBHS INT (USBHS interrupt) */
+    [5] = usbhs_d0fifo_handler,    /* USBHS FIFO 0 (DMA transfer request 0) */
+    [6] = usbhs_d1fifo_handler,    /* USBHS FIFO 1 (DMA transfer request 1) */
+#endif
+};
+
+const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
+    [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),            /* USBFS INT (USBFS interrupt) */
+    [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME),         /* USBFS RESUME (USBFS resume interrupt) */
+
+#ifndef BSP_MCU_GROUP_RA2A1
+    [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0),         /* USBFS FIFO 0 (DMA transfer request 0) */
+    [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1),         /* USBFS FIFO 1 (DMA transfer request 1) */
+#endif
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+    [4] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME), /* USBHS USB INT RESUME (USBHS interrupt) */
+    [5] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_0),         /* USBHS FIFO 0 (DMA transfer request 0) */
+    [6] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_1),         /* USBHS FIFO 1 (DMA transfer request 1) */
+#endif
+};
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_init(void) {
+  // Enable global interrupts in CPSR register since board with bootloader such as Arduino Uno R4
+  // can transfer CPU control with CPSR.I bit set to 0 (disable IRQ)
+  __enable_irq();
+
+  /* Configure pins. */
+  R_IOPORT_Open(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME);
+
+#ifdef TRACE_ETM
+  // TRCKCR is protected by PRCR bit0 register
+  R_SYSTEM->PRCR = (uint16_t) (BSP_PRV_PRCR_KEY | 0x01);
+
+  // Enable trace clock (max 100Mhz). Since PLL/CPU is 200Mhz, clock div = 2
+  R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01;
+
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_KEY;
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+  board_led_write(false);
+}
+
+void board_init_after_tusb(void) {
+  // For board that use USB LDO regulator
+#if defined(BOARD_UNO_R4)
+  R_USB_FS0->USBMC |= R_USB_FS0_USBMC_VDCEN_Msk;
+#endif
+}
+
+void board_led_write(bool state) {
+  R_IOPORT_PinWrite(&IOPORT_CFG_CTRL, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
+}
+
+uint32_t board_button_read(void) {
+  bsp_io_level_t lvl = !BUTTON_STATE_ACTIVE;
+  R_IOPORT_PinRead(&IOPORT_CFG_CTRL, SW1, &lvl);
+  return lvl == BUTTON_STATE_ACTIVE;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  max_len = tu_min32(max_len, sizeof(bsp_unique_id_t));
+  bsp_unique_id_t const *uid = R_BSP_UniqueIdGet();
+  memcpy(id, uid->unique_id_bytes, max_len);
+  return max_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+//------------- USB0 FullSpeed -------------//
+void usbfs_interrupt_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+
+  tusb_int_handler(0, true);
+}
+
+void usbfs_resume_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+
+  tusb_int_handler(0, true);
+}
+
+void usbfs_d0fifo_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
+
+void usbfs_d1fifo_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
+
+//------------- USB1 HighSpeed -------------//
+#ifdef BOARD_HAS_USB_HIGHSPEED
+void usbhs_interrupt_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+
+  tusb_int_handler(1, true);
+}
+
+void usbhs_d0fifo_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
+
+void usbhs_d1fifo_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
+#endif
+
+//--------------------------------------------------------------------+
+// stdlib
+//--------------------------------------------------------------------+
+
+int close(int fd) {
+  (void) fd;
+  return -1;
+}
+
+int fstat(int fd, void *pstat) {
+  (void) fd;
+  (void) pstat;
+  return 0;
+}
+
+off_t lseek(int fd, off_t pos, int whence) {
+  (void) fd;
+  (void) pos;
+  (void) whence;
+  return 0;
+}
+
+int isatty(int fd) {
+  (void) fd;
+  return 1;
+}
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
new file mode 100644
index 000000000..42a32631c
--- /dev/null
+++ b/hw/bsp/ra/family.cmake
@@ -0,0 +1,167 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(CMSIS_DIR ${TOP}/lib/CMSIS_6)
+set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+#set(FREERTOS_PORT A_CUSTOM_PORT CACHE INTERNAL "")
+
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "")
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif ()
+
+if (NOT DEFINED RHPORT_SPEED)
+  set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/startup.c
+      ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/system.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_clocks.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_common.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_delay.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_group_irq.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_guard.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_io.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_irq.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_register_protection.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_security.c
+      ${FSP_RA}/src/r_ioport/r_ioport.c
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/common_data.c
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/pin_data.c
+      )
+
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -ffreestanding
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg/bsp
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${FSP_RA}/inc
+      ${FSP_RA}/inc/api
+      ${FSP_RA}/inc/instances
+      ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Include
+      ${FSP_RA}/src/bsp/mcu/all
+      ${FSP_RA}/src/bsp/mcu/${MCU_VARIANT}
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+      BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+      BOARD_TUH_RHPORT=${RHPORT_HOST}
+      BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+      set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script/fsp.ld)
+    endif ()
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        # linker file
+        "LINKER:--script=${LD_FILE_GNU}"
+        -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script
+        -Wl,--defsym=end=__bss_end__
+        -nostartfiles
+        --specs=nano.specs --specs=nosys.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    # Explicitly added bsp_rom_registers here, otherwise MCU can be bricked if g_bsp_rom_registers is dropped by linker
+    ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    )
+  target_compile_options(${TARGET} PUBLIC
+    -Wno-error=undef
+    -Wno-error=strict-prototypes
+    )
+
+#  # RA has custom freertos port
+#  if (NOT TARGET freertos_kernel_port)
+#    add_library(freertos_kernel_port STATIC)
+#    target_sources(freertos_kernel_port PUBLIC ${FSP_RA}/src/rm_freertos_port/port.c)
+#    target_include_directories(freertos_kernel_port PUBLIC ${FSP_RA}/src/rm_freertos_port)
+#
+#    target_link_libraries(freertos_kernel_port PUBLIC freertos_kernel)
+#  endif ()
+
+    # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_RAXXX)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
+    ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
+    ${TOP}/src/portable/renesas/rusb2/rusb2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  family_add_bin_hex(${TARGET})
+
+  if (DEFINED DFU_UTIL_VID_PID)
+    family_flash_dfu_util(${TARGET} ${DFU_UTIL_VID_PID})
+  endif ()
+endfunction()
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
new file mode 100644
index 000000000..6ac7c262f
--- /dev/null
+++ b/hw/bsp/ra/family.mk
@@ -0,0 +1,102 @@
+FSP_RA = hw/mcu/renesas/fsp/ra/fsp
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+# Don't include options setting in .bin file since it create unnecessary large file due to padding
+OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
+
+# Determine RHPORT_DEVICE_SPEED if not defined
+ifndef RHPORT_DEVICE_SPEED
+ifeq ($(RHPORT_DEVICE), 0)
+  RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
+# Determine RHPORT_HOST_SPEED if not defined
+ifndef RHPORT_HOST_SPEED
+ifeq ($(RHPORT_HOST), 0)
+  RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_RAXXX \
+	-DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
+	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
+	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
+	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+
+CFLAGS_GCC += \
+  -flto \
+	-Wno-error=undef \
+	-Wno-error=strict-prototypes \
+	-Wno-error=cast-align \
+	-Wno-error=cast-qual \
+	-Wno-error=unused-but-set-variable \
+	-Wno-error=unused-variable \
+	-ffreestanding
+
+LDFLAGS_GCC += \
+	-nostartfiles -nostdlib \
+  -specs=nosys.specs -specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
+SRC_C += \
+	src/portable/renesas/rusb2/dcd_rusb2.c \
+	src/portable/renesas/rusb2/hcd_rusb2.c \
+	src/portable/renesas/rusb2/rusb2_common.c \
+	${BOARD_PATH}/ra_gen/common_data.c \
+	${BOARD_PATH}/ra_gen/pin_data.c \
+	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
+	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_common.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_delay.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_group_irq.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_guard.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_io.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_irq.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_register_protection.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_rom_registers.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_sbrk.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_security.c \
+	$(FSP_RA)/src/r_ioport/r_ioport.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(BOARD_PATH)/ra_cfg/fsp_cfg \
+	$(TOP)/$(BOARD_PATH)/ra_cfg/fsp_cfg/bsp \
+	$(TOP)/$(BOARD_PATH)/ra_gen \
+	$(TOP)/lib/CMSIS_6/CMSIS/Core/Include \
+	$(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \
+	$(TOP)/$(FSP_RA)/inc \
+	$(TOP)/$(FSP_RA)/inc/api \
+	$(TOP)/$(FSP_RA)/inc/instances \
+  $(TOP)/$(FSP_RA)/src/bsp/mcu/all \
+	$(TOP)/$(FSP_RA)/src/bsp/mcu/$(MCU_VARIANT) \
+
+ifndef LD_FILE
+LD_FILE = $(BOARD_PATH)/script/fsp.ld
+endif
+
+LDFLAGS += -L$(TOP)/$(BOARD_PATH)/script
+LDFLAGS += -Wl,--defsym=end=__bss_end__
+
+# For freeRTOS port source
+# hack to use the port provided by renesas
+FREERTOS_PORTABLE_SRC = $(FSP_RA)/src/rm_freertos_port
diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h
new file mode 100644
index 000000000..a85d064bd
--- /dev/null
+++ b/hw/bsp/ra/vector_data.h
@@ -0,0 +1,43 @@
+/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
+#ifndef VECTOR_DATA_H
+#define VECTOR_DATA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
+#define BOARD_HAS_USB_HIGHSPEED
+#endif
+
+/* ISR prototypes */
+void usbfs_interrupt_handler(void);
+void usbfs_resume_handler(void);
+
+#ifndef BSP_MCU_GROUP_RA2A1
+void usbfs_d0fifo_handler(void);
+void usbfs_d1fifo_handler(void);
+#endif
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+void usbhs_interrupt_handler(void);
+void usbhs_d0fifo_handler(void);
+void usbhs_d1fifo_handler(void);
+#endif
+
+/* Vector table allocations */
+#define USBFS_INT_IRQn    0
+#define USBFS_RESUME_IRQn 1
+#define USBFS_FIFO_0_IRQn 2
+#define USBFS_FIFO_1_IRQn 3
+
+#define USBHS_USB_INT_RESUME_IRQn  4 /* USBHS USB INT RESUME (USBHS interrupt) */
+#define USBHS_FIFO_0_IRQn          5 /* USBHS FIFO 0 (DMA transfer request 0) */
+#define USBHS_FIFO_1_IRQn          6 /* USBHS FIFO 1 (DMA transfer request 1) */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index f25f80e09..5dbb1dd37 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Pico
+   url: https://www.raspberrypi.org/products/raspberry-pi-pico/
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,6 +36,7 @@
  extern "C" {
 #endif
 
+// LED
 #ifdef PICO_DEFAULT_LED_PIN
 #define LED_PIN               PICO_DEFAULT_LED_PIN
 #define LED_STATE_ON          (!(PICO_DEFAULT_LED_PIN_INVERTED))
@@ -40,24 +46,55 @@
 #define BUTTON_BOOTSEL
 #define BUTTON_STATE_ACTIVE   0
 
-#if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && defined(PICO_DEFAULT_UART)
+// UART
+#if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && \
+    defined(PICO_DEFAULT_UART) && defined(LIB_PICO_STDIO_UART)
 #define UART_DEV              PICO_DEFAULT_UART
 #define UART_TX_PIN           PICO_DEFAULT_UART_TX_PIN
 #define UART_RX_PIN           PICO_DEFAULT_UART_RX_PIN
 #endif
 
-// PIO_USB_DP_PIN_DEFAULT is 0, which conflict with UART, change to other pin
-#ifndef PIO_USB_DP_PIN
-#define PIO_USB_DP_PIN        20
+//--------------------------------------------------------------------+
+// PIO_USB
+// default to pin on Adafruit Feather rp2040 USB Host or Tester if defined
+//--------------------------------------------------------------------+
+
+// #define USE_ADAFRUIT_FEATHER_RP2040_USBHOST
+#ifdef USE_ADAFRUIT_FEATHER_RP2040_USBHOST
+#define PICO_DEFAULT_PIO_USB_DP_PIN       16
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   18
+#endif
+
+#ifndef PICO_DEFAULT_PIO_USB_DP_PIN
+#define PICO_DEFAULT_PIO_USB_DP_PIN       20
 #endif
 
 // VBUS enable pin and its active state
-#define PIO_USB_VBUSEN_PIN    22
-
-#ifndef PIO_USB_VBUSEN_STATE
-#define PIO_USB_VBUSEN_STATE  1
+#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_PIN
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   22
 #endif
 
+// VBUS enable state
+#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_STATE
+#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1
+#endif
+
+//--------------------------------------------------------------------
+// USB Host MAX3421E
+//--------------------------------------------------------------------
+
+#ifdef PICO_DEFAULT_SPI
+#define MAX3421_SPI      PICO_DEFAULT_SPI // sdk v2
+#else
+#define MAX3421_SPI      PICO_DEFAULT_SPI_INSTANCE // sdk v1
+#endif
+
+#define MAX3421_SCK_PIN  PICO_DEFAULT_SPI_SCK_PIN
+#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN
+#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN
+#define MAX3421_CS_PIN   10
+#define MAX3421_INTR_PIN 9
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake
new file mode 100644
index 000000000..2afe0f264
--- /dev/null
+++ b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake
@@ -0,0 +1,5 @@
+set(PICO_PLATFORM rp2040)
+set(PICO_BOARD adafruit_feather_rp2040)
+
+# Enable MAX3421E USB Host
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
index 8280c835d..804cdb50a 100644
--- a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
@@ -1 +1,2 @@
-set(PICO_BOARD pico)
\ No newline at end of file
+set(PICO_PLATFORM rp2040)
+set(PICO_BOARD pico)
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake
new file mode 100644
index 000000000..3482e2674
--- /dev/null
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake
@@ -0,0 +1,2 @@
+set(PICO_PLATFORM rp2350-arm-s)
+set(PICO_BOARD pico2)
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 26008168d..24aa0b616 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -25,20 +25,36 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Raspberry Pi
+*/
+
 #include "pico/stdlib.h"
 #include "pico/binary_info.h"
+#include "pico/unique_id.h"
 #include "hardware/gpio.h"
 #include "hardware/sync.h"
+#include "hardware/resets.h"
+#include "hardware/clocks.h"
 #include "hardware/structs/ioqspi.h"
 #include "hardware/structs/sio.h"
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
-#if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
+#ifdef UART_DEV
+static uart_inst_t *uart_inst;
+#endif
+
+#if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB)
 #include "pio_usb.h"
 #endif
 
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+#include "hardware/spi.h"
+static void max3421_init(void);
+#endif
+
 #ifdef BUTTON_BOOTSEL
 // This example blinks the Picoboard LED when the BOOTSEL button is pressed.
 //
@@ -51,90 +67,89 @@
 // This doesn't work if others are trying to access flash at the same time,
 // e.g. XIP streamer, or the other core.
 bool __no_inline_not_in_flash_func(get_bootsel_button)(void) {
-    const uint CS_PIN_INDEX = 1;
+  const uint CS_PIN_INDEX = 1;
 
-    // Must disable interrupts, as interrupt handlers may be in flash, and we
-    // are about to temporarily disable flash access!
-    uint32_t flags = save_and_disable_interrupts();
+  // Must disable interrupts, as interrupt handlers may be in flash, and we
+  // are about to temporarily disable flash access!
+  uint32_t flags = save_and_disable_interrupts();
 
-    // Set chip select to Hi-Z
-    hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
-                    GPIO_OVERRIDE_LOW << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
-                    IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
+  // Set chip select to Hi-Z
+  hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
+                  GPIO_OVERRIDE_LOW << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
+                  IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
 
-    // Note we can't call into any sleep functions in flash right now
-    for (volatile int i = 0; i < 1000; ++i);
+  // Note we can't call into any sleep functions in flash right now
+  for (volatile int i = 0; i < 1000; ++i);
 
-    // The HI GPIO registers in SIO can observe and control the 6 QSPI pins.
-    // Note the button pulls the pin *low* when pressed.
-    bool button_state = (sio_hw->gpio_hi_in & (1u << CS_PIN_INDEX));
+  // The HI GPIO registers in SIO can observe and control the 6 QSPI pins.
+  // Note the button pulls the pin *low* when pressed.
 
-    // Need to restore the state of chip select, else we are going to have a
-    // bad time when we return to code in flash!
-    hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
-                    GPIO_OVERRIDE_NORMAL << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
-                    IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
+  #ifdef __ARM_ARCH_6M__ // CM0 for rp2040
+    #define CS_BIT (1u << 1)
+  #else // rp2350 (cm33/risv)
+    #define CS_BIT SIO_GPIO_HI_IN_QSPI_CSN_BITS
+  #endif
+  bool button_state = (sio_hw->gpio_hi_in & CS_BIT);
 
-    restore_interrupts(flags);
+  // Need to restore the state of chip select, else we are going to have a
+  // bad time when we return to code in flash!
+  hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
+                  GPIO_OVERRIDE_NORMAL << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
+                  IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
 
-    return button_state;
+  restore_interrupts(flags);
+
+  return button_state;
 }
 #endif
 
 //------------- Segger RTT retarget -------------//
 #if defined(LOGGER_RTT)
-
 // Logging with RTT
 // - If RTT Control Block is not found by 'Auto Detection` try to use 'Search Range` with '0x20000000 0x10000'
 // - SWD speed is rather slow around 1000Khz
-
 #include "pico/stdio/driver.h"
 #include "SEGGER_RTT.h"
 
-static void stdio_rtt_write (const char *buf, int length)
-{
-  SEGGER_RTT_Write(0, buf, length);
+static void stdio_rtt_write (const char *buf, int length) {
+  SEGGER_RTT_Write(0, buf, (unsigned) length);
 }
 
-static int stdio_rtt_read (char *buf, int len)
-{
-  return SEGGER_RTT_Read(0, buf, len);
+static int stdio_rtt_read (char *buf, int len) {
+  return (int) SEGGER_RTT_Read(0, buf, (unsigned) len);
 }
 
-static stdio_driver_t stdio_rtt =
-{
+static stdio_driver_t stdio_rtt = {
   .out_chars = stdio_rtt_write,
   .out_flush = NULL,
   .in_chars = stdio_rtt_read
 };
 
-void stdio_rtt_init(void)
-{
+void stdio_rtt_init(void) {
   stdio_set_driver_enabled(&stdio_rtt, true);
 }
-
 #endif
 
-#ifdef UART_DEV
-static uart_inst_t *uart_inst;
-#endif
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 
 void board_init(void)
 {
-#if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
+#if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB)
   // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb
   set_sys_clock_khz(120000, true);
 
-#ifdef PIO_USB_VBUSEN_PIN
-  gpio_init(PIO_USB_VBUSEN_PIN);
-  gpio_set_dir(PIO_USB_VBUSEN_PIN, GPIO_OUT);
-  gpio_put(PIO_USB_VBUSEN_PIN, PIO_USB_VBUSEN_STATE);
+#ifdef PICO_DEFAULT_PIO_USB_VBUSEN_PIN
+  gpio_init(PICO_DEFAULT_PIO_USB_VBUSEN_PIN);
+  gpio_set_dir(PICO_DEFAULT_PIO_USB_VBUSEN_PIN, GPIO_OUT);
+  gpio_put(PICO_DEFAULT_PIO_USB_VBUSEN_PIN, PICO_DEFAULT_PIO_USB_VBUSEN_STATE);
 #endif
 
   // rp2040 use pico-pio-usb for host tuh_configure() can be used to passed pio configuration to the host stack
   // Note: tuh_configure() must be called before tuh_init()
   pio_usb_configuration_t pio_cfg = PIO_USB_DEFAULT_CONFIG;
-  pio_cfg.pin_dp = PIO_USB_DP_PIN;
+  pio_cfg.pin_dp = PICO_DEFAULT_PIO_USB_DP_PIN;
   tuh_configure(BOARD_TUH_RHPORT, TUH_CFGID_RPI_PIO_USB_CONFIGURATION, &pio_cfg);
 #endif
 
@@ -148,8 +163,8 @@ void board_init(void)
 #ifndef BUTTON_BOOTSEL
 #endif
 
-#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
-  bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART));
+#ifdef UART_DEV
+  bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_RX_PIN, GPIO_FUNC_UART));
   uart_inst = uart_get_instance(UART_DEV);
   stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, UART_RX_PIN);
 #endif
@@ -163,7 +178,15 @@ void board_init(void)
 #endif
 
 #if CFG_TUH_ENABLED
-  // set portfunc to host !!!
+  #if CFG_TUH_MAX3421
+  max3421_init();
+  #endif
+#endif
+
+#if !CFG_TUD_ENABLED && !CFG_TUH_ENABLED
+  // board test exxample, reset usb controller
+  reset_block(RESETS_RESET_USBCTRL_BITS);
+  unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
 #endif
 }
 
@@ -171,17 +194,15 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   (void) state;
 
 #ifdef LED_PIN
-  gpio_put(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  gpio_put(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 #endif
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
 #ifdef BUTTON_BOOTSEL
   return BUTTON_STATE_ACTIVE == get_bootsel_button();
 #else
@@ -189,12 +210,23 @@ uint32_t board_button_read(void)
 #endif
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  pico_unique_board_id_t pico_id;
+  pico_get_unique_board_id(&pico_id);
+
+  size_t len = PICO_UNIQUE_BOARD_ID_SIZE_BYTES;
+  if (len > max_len) {
+    len = max_len;
+  }
+
+  memcpy(id, pico_id.id, len);
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
 #ifdef UART_DEV
   int count = 0;
-  while ( (count < len) && uart_is_readable(uart_inst) )
-  {
+  while ( (count < len) && uart_is_readable(uart_inst) ) {
     buf[count] = uart_getc(uart_inst);
     count++;
   }
@@ -205,11 +237,10 @@ int board_uart_read(uint8_t* buf, int len)
 #endif
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
 #ifdef UART_DEV
-  char const* bufch = (char const*) buf;
-  for(int i=0;i<len;i++) {
+  char const *bufch = (char const *) buf;
+  for ( int i = 0; i < len; i++ ) {
     uart_putc(uart_inst, bufch[i]);
   }
   return len;
@@ -219,13 +250,86 @@ int board_uart_write(void const * buf, int len)
 #endif
 }
 
-int board_getchar(void)
-{
+int board_getchar(void) {
   return getchar_timeout_us(0);
 }
 
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
-// rp2040 implementation will install approriate handler when initializing
+// rp2040 implementation will install appropriate handler when initializing
 // tinyusb. There is no need to forward IRQ from application
 //--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+void max3421_int_handler(uint gpio, uint32_t event_mask) {
+  if (!(gpio == MAX3421_INTR_PIN && event_mask & GPIO_IRQ_EDGE_FALL)) return;
+  tuh_int_handler(BOARD_TUH_RHPORT, true);
+}
+
+static void max3421_init(void) {
+  // CS pin
+  gpio_init(MAX3421_CS_PIN);
+  gpio_set_dir(MAX3421_CS_PIN, GPIO_OUT);
+  gpio_put(MAX3421_CS_PIN, true);
+
+  // Interrupt pin
+  gpio_init(MAX3421_INTR_PIN);
+  gpio_set_dir(MAX3421_INTR_PIN, GPIO_IN);
+  gpio_pull_up(MAX3421_INTR_PIN);
+  gpio_set_irq_enabled_with_callback(MAX3421_INTR_PIN, GPIO_IRQ_EDGE_FALL, true, max3421_int_handler);
+
+  // SPI init
+  spi_init(MAX3421_SPI, 4*1000000ul);
+  gpio_set_function(MAX3421_SCK_PIN, GPIO_FUNC_SPI);
+  gpio_set_function(MAX3421_MOSI_PIN, GPIO_FUNC_SPI);
+  gpio_set_function(MAX3421_MISO_PIN, GPIO_FUNC_SPI);
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wnull-dereference"
+#endif
+  spi_set_format(MAX3421_SPI, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+}
+
+//// API to enable/disable MAX3421 INTR pin interrupt
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+  irq_set_enabled(IO_IRQ_BANK0, enabled);
+}
+
+// API to control MAX3421 SPI CS
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  gpio_put(MAX3421_CS_PIN, !active);
+}
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+  (void) rhport;
+
+  if (tx_buf == NULL && rx_buf == NULL) {
+    return false;
+  }
+
+  int ret;
+
+  if (tx_buf == NULL) {
+    ret = spi_read_blocking(MAX3421_SPI, 0, rx_buf, xfer_bytes);
+  }else if (rx_buf == NULL) {
+    ret = spi_write_blocking(MAX3421_SPI, tx_buf, xfer_bytes);
+  }else {
+    ret = spi_write_read_blocking(spi0, tx_buf, rx_buf, xfer_bytes);
+  }
+
+  return ret == (int) xfer_bytes;
+}
+
+#endif
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 964855c05..cf5295f22 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -1,85 +1,104 @@
 cmake_minimum_required(VERSION 3.13)
-if (NOT TARGET _rp2040_family_inclusion_marker)
-	add_library(_rp2040_family_inclusion_marker INTERFACE)
+include_guard(GLOBAL)
 
-	if (NOT BOARD)
-		message("BOARD not specified, defaulting to pico_sdk")
-		set(BOARD pico_sdk)
-	endif()
+if (NOT BOARD)
+	message("BOARD not specified, defaulting to pico_sdk")
+	set(BOARD pico_sdk)
+endif()
 
-	# add the SDK in case we are standalone tinyusb example (noop if already present)
-	include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake)
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
-	# include basic family CMake functionality
-	set(FAMILY_MCUS RP2040)
+#if (TOOLCHAIN STREQUAL "clang")
+#	set(PICO_COMPILER "pico_arm_clang")
+#else()
+#	set(PICO_COMPILER "pico_arm_gcc")
+#endif()
 
-	include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+# add the SDK in case we are standalone tinyusb example (noop if already present)
+include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake)
 
-	# TOP is absolute path to root directory of TinyUSB git repo
-	set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-	get_filename_component(TOP "${TOP}" REALPATH)
+# include basic family CMake functionality
+set(FAMILY_MCUS RP2040)
 
-	if (NOT PICO_TINYUSB_PATH)
-		set(PICO_TINYUSB_PATH ${TOP})
-	endif()
+if (PICO_PLATFORM STREQUAL "rp2040")
+	set(JLINK_DEVICE rp2040_m0_0)
+	set(OPENOCD_TARGET rp2040)
+elseif (PICO_PLATFORM STREQUAL "rp2350-arm-s" OR PICO_PLATFORM STREQUAL "rp2350")
+	set(JLINK_DEVICE rp2350_m33_0)
+	set(OPENOCD_TARGET rp2350)
+elseif (PICO_PLATFORM STREQUAL "rp2350-riscv")
+	set(JLINK_DEVICE rp2350_riscv_0)
+	set(OPENOCD_TARGET rp2350-riscv)
+endif()
 
-	#------------------------------------
-	# Base config for both device and host; wrapped by SDK's tinyusb_common
-	#------------------------------------
-	add_library(tinyusb_common_base INTERFACE)
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${OPENOCD_TARGET}.cfg -c \"adapter speed 5000\"")
 
-	target_sources(tinyusb_common_base INTERFACE
-			${TOP}/src/tusb.c
-			${TOP}/src/common/tusb_fifo.c
-			)
+if (NOT PICO_TINYUSB_PATH)
+	set(PICO_TINYUSB_PATH ${TOP})
+endif()
 
-	target_include_directories(tinyusb_common_base INTERFACE
-			${TOP}/src
-			${TOP}/src/common
-			${TOP}/hw
-			)
+if (NOT TINYUSB_OPT_OS)
+	set(TINYUSB_OPT_OS OPT_OS_PICO)
+endif()
 
-	target_link_libraries(tinyusb_common_base INTERFACE
-			hardware_structs
-			hardware_irq
-			hardware_resets
-			pico_sync
-			)
+#------------------------------------
+# Base config for both device and host; wrapped by SDK's tinyusb_common
+#------------------------------------
+add_library(tinyusb_common_base INTERFACE)
 
-	set(TINYUSB_DEBUG_LEVEL 0)
-	if (CMAKE_BUILD_TYPE STREQUAL "Debug")
-		message("Compiling TinyUSB with CFG_TUSB_DEBUG=1")
-		set(TINYUSB_DEBUG_LEVEL 1)
-	endif()
-	
-	target_compile_definitions(tinyusb_common_base INTERFACE
-			CFG_TUSB_MCU=OPT_MCU_RP2040
-			CFG_TUSB_OS=OPT_OS_PICO
-			#CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
+target_sources(tinyusb_common_base INTERFACE
+	${TOP}/src/tusb.c
+	${TOP}/src/common/tusb_fifo.c
 	)
 
-	#------------------------------------
-	# Base config for device mode; wrapped by SDK's tinyusb_device
-	#------------------------------------
-	add_library(tinyusb_device_base INTERFACE)
-	target_sources(tinyusb_device_base INTERFACE
-			${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
-			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-			${TOP}/src/device/usbd.c
-			${TOP}/src/device/usbd_control.c
-			${TOP}/src/class/audio/audio_device.c
-			${TOP}/src/class/cdc/cdc_device.c
-			${TOP}/src/class/dfu/dfu_device.c
-			${TOP}/src/class/dfu/dfu_rt_device.c
-			${TOP}/src/class/hid/hid_device.c
-			${TOP}/src/class/midi/midi_device.c
-			${TOP}/src/class/msc/msc_device.c
-			${TOP}/src/class/net/ecm_rndis_device.c
-			${TOP}/src/class/net/ncm_device.c
-			${TOP}/src/class/usbtmc/usbtmc_device.c
-			${TOP}/src/class/vendor/vendor_device.c
-			${TOP}/src/class/video/video_device.c
-			)
+target_include_directories(tinyusb_common_base INTERFACE
+	${TOP}/src
+	)
+
+if(DEFINED LOG)
+	set(TINYUSB_DEBUG_LEVEL ${LOG})
+elseif (CMAKE_BUILD_TYPE STREQUAL "Debug")
+	message("Compiling TinyUSB with CFG_TUSB_DEBUG=1")
+	set(TINYUSB_DEBUG_LEVEL 1)
+else ()
+	set(TINYUSB_DEBUG_LEVEL 0)
+endif()
+
+target_compile_definitions(tinyusb_common_base INTERFACE
+	CFG_TUSB_MCU=OPT_MCU_RP2040
+	CFG_TUSB_OS=${TINYUSB_OPT_OS}
+	CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
+)
+
+target_link_libraries(tinyusb_common_base INTERFACE
+	hardware_structs
+	hardware_irq
+	hardware_resets
+	pico_sync
+	)
+
+#------------------------------------
+# Base config for device mode; wrapped by SDK's tinyusb_device
+#------------------------------------
+add_library(tinyusb_device_base INTERFACE)
+target_sources(tinyusb_device_base INTERFACE
+		${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+		${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
+		${TOP}/src/device/usbd.c
+		${TOP}/src/device/usbd_control.c
+		${TOP}/src/class/audio/audio_device.c
+		${TOP}/src/class/cdc/cdc_device.c
+		${TOP}/src/class/dfu/dfu_device.c
+		${TOP}/src/class/dfu/dfu_rt_device.c
+		${TOP}/src/class/hid/hid_device.c
+		${TOP}/src/class/midi/midi_device.c
+		${TOP}/src/class/msc/msc_device.c
+		${TOP}/src/class/net/ecm_rndis_device.c
+		${TOP}/src/class/net/ncm_device.c
+		${TOP}/src/class/usbtmc/usbtmc_device.c
+		${TOP}/src/class/vendor/vendor_device.c
+		${TOP}/src/class/video/video_device.c
+		)
 
 	#------------------------------------
 	# Base config for host mode; wrapped by SDK's tinyusb_host
@@ -92,190 +111,298 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/host/hub.c
 			${TOP}/src/class/cdc/cdc_host.c
 			${TOP}/src/class/hid/hid_host.c
+      ${TOP}/src/class/midi/midi_host.c
 			${TOP}/src/class/msc/msc_host.c
-            ${TOP}/src/class/midi/midi_host.c
 			${TOP}/src/class/vendor/vendor_host.c
 			)
 
-	# Sometimes have to do host specific actions in mostly common functions
-	target_compile_definitions(tinyusb_host_base INTERFACE
-			RP2040_USB_HOST_MODE=1
+# Sometimes have to do host specific actions in mostly common functions
+target_compile_definitions(tinyusb_host_base INTERFACE
+		RP2040_USB_HOST_MODE=1
+)
+
+#------------------------------------
+# Host MAX3421
+#------------------------------------
+add_library(tinyusb_host_max3421 INTERFACE)
+target_sources(tinyusb_host_max3421 INTERFACE
+	${TOP}/src/portable/analog/max3421/hcd_max3421.c
+	)
+target_compile_definitions(tinyusb_host_max3421 INTERFACE
+	CFG_TUH_MAX3421=1
+	)
+target_link_libraries(tinyusb_host_max3421 INTERFACE
+	hardware_spi
 	)
 
-	#------------------------------------
-	# BSP & Additions
-	#------------------------------------
-	add_library(tinyusb_bsp INTERFACE)
-	target_sources(tinyusb_bsp INTERFACE
-			${TOP}/hw/bsp/rp2040/family.c
-			)
-	#	target_include_directories(tinyusb_bsp INTERFACE
-	#			${TOP}/hw/bsp/rp2040)
+#------------------------------------
+# BSP & Additions
+#------------------------------------
+add_library(tinyusb_bsp INTERFACE)
+target_sources(tinyusb_bsp INTERFACE
+	${TOP}/hw/bsp/rp2040/family.c
+	)
+target_include_directories(tinyusb_bsp INTERFACE
+	${TOP}/hw
+	)
+target_link_libraries(tinyusb_bsp INTERFACE
+	pico_unique_id
+	hardware_clocks
+	)
 
-	# tinyusb_additions will hold our extra settings for examples
-	add_library(tinyusb_additions INTERFACE)
+# tinyusb_additions will hold our extra settings for examples
+add_library(tinyusb_additions INTERFACE)
 
+target_compile_definitions(tinyusb_additions INTERFACE
+	PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1
+	PICO_RP2040_USB_DEVICE_UFRAME_FIX=1
+)
+
+if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
 	target_compile_definitions(tinyusb_additions INTERFACE
-		PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1
+			LOGGER_RTT
+			#SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
 	)
 
-	if(DEFINED LOG)
-		target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG})
-	endif()
+	target_sources(tinyusb_additions INTERFACE
+			${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+	)
 
-	if(LOGGER STREQUAL "rtt")
-		target_compile_definitions(tinyusb_additions INTERFACE
-				LOGGER_RTT
-				SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
-		)
+	set_source_files_properties(${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+		PROPERTIES
+		COMPILE_FLAGS "-Wno-cast-qual -Wno-cast-align -Wno-sign-conversion")
 
-		target_sources(tinyusb_additions INTERFACE
-				${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
-		)
-
-		target_include_directories(tinyusb_additions INTERFACE
-				${TOP}/lib/SEGGER_RTT/RTT
-		)
-	endif()
-
-	#------------------------------------
-	# Functions
-	#------------------------------------
-
-	function(family_configure_target TARGET)
-		pico_add_extra_outputs(${TARGET})
-		pico_enable_stdio_uart(${TARGET} 1)
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board tinyusb_additions)
-	endfunction()
-
-	function(rp2040_family_configure_example_warnings TARGET)
-		if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS)
-			family_add_default_example_warnings(${TARGET})
-		endif()
-		suppress_tinyusb_warnings()
-	endfunction()
-
-	function(family_configure_device_example TARGET)
-		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device)
-		rp2040_family_configure_example_warnings(${TARGET})
-	endfunction()
-
-	function(family_configure_host_example TARGET)
-		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
-		rp2040_family_configure_example_warnings(${TARGET})
-	endfunction()
-
-	function(family_add_pico_pio_usb TARGET)
-		target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
-	endfunction()
-
-	function(family_configure_dual_usb_example TARGET)
-		family_configure_target(${TARGET})
-		# require tinyusb_pico_pio_usb
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb )
-		rp2040_family_configure_example_warnings(${TARGET})
-	endfunction()
-
-	function(check_and_add_pico_pio_usb_support)
-		# check for pico_generate_pio_header (as depending on environment we may be called before SDK is
-		# initialized in which case it isn't available yet), and only do the initialization once
-		if (COMMAND pico_generate_pio_header AND NOT TARGET tinyusb_pico_pio_usb)
-			#------------------------------------
-			# PIO USB for both host and device
-			#------------------------------------
-
-			if (NOT DEFINED PICO_PIO_USB_PATH)
-				set(PICO_PIO_USB_PATH "${TOP}/hw/mcu/raspberry_pi/Pico-PIO-USB")
-			endif()
-
-			if (EXISTS ${PICO_PIO_USB_PATH}/src/pio_usb.c)
-				add_library(tinyusb_pico_pio_usb INTERFACE)
-				target_sources(tinyusb_device_base INTERFACE
-						${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
-						)
-				target_sources(tinyusb_host_base INTERFACE
-						${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
-						)
-
-				target_sources(tinyusb_pico_pio_usb INTERFACE
-						${PICO_PIO_USB_PATH}/src/pio_usb.c
-						${PICO_PIO_USB_PATH}/src/pio_usb_host.c
-						${PICO_PIO_USB_PATH}/src/pio_usb_device.c
-						${PICO_PIO_USB_PATH}/src/usb_crc.c
-						)
-
-				target_include_directories(tinyusb_pico_pio_usb INTERFACE
-						${PICO_PIO_USB_PATH}/src
-						)
-
-				target_link_libraries(tinyusb_pico_pio_usb INTERFACE
-						hardware_dma
-						hardware_pio
-						pico_multicore
-						)
-
-				target_compile_definitions(tinyusb_pico_pio_usb INTERFACE
-						PIO_USB_USE_TINYUSB
-						)
-
-				pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_tx.pio)
-				pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_rx.pio)
-			endif()
-		endif()
-	endfunction()
-
-	# Try to add Pico-PIO_USB support now for the case where this file is included directly
-	# after Pico SDK initialization, but without using the family_ functions (as is the case
-	# when included by the SDK itself)
-	check_and_add_pico_pio_usb_support()
-
-	function(family_initialize_project PROJECT DIR)
-		# call the original version of this function from family_common.cmake
-		_family_initialize_project(${PROJECT} ${DIR})
-		enable_language(C CXX ASM)
-		pico_sdk_init()
-
-		# now re-check for adding Pico-PIO_USB support now SDK is definitely available
-		check_and_add_pico_pio_usb_support()
-	endfunction()
-
-	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
-	function(suppress_tinyusb_warnings)
-		# some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior
-		if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-			if (CMAKE_C_COMPILER_VERSION VERSION_LESS 10.0)
-				set(CONVERSION_WARNING_FILES
-					${PICO_TINYUSB_PATH}/src/tusb.c
-					${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
-					${PICO_TINYUSB_PATH}/src/device/usbd.c
-					${PICO_TINYUSB_PATH}/src/device/usbd_control.c
-					${PICO_TINYUSB_PATH}/src/host/usbh.c
-					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
-					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
-					${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
-					${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
-					${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
-					${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c
-					${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
-					${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
-					${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
-					${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
-					)
-				foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES)
-					set_source_files_properties(
-							${SOURCE_FILE}
-							PROPERTIES
-							COMPILE_FLAGS "-Wno-conversion")
-				endforeach()
-			endif()
-			if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0)
-				set_source_files_properties(
-						${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-						PROPERTIES
-						COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds")
-			endif()
-		endif()
-	endfunction()
+	target_include_directories(tinyusb_additions INTERFACE
+			${TOP}/lib/SEGGER_RTT/RTT
+	)
 endif()
+
+#------------------------------------
+# Functions
+#------------------------------------
+
+function(family_configure_target TARGET RTOS)
+	if (RTOS STREQUAL noos OR RTOS STREQUAL "")
+		set(RTOS_SUFFIX "")
+	else()
+		set(RTOS_SUFFIX _${RTOS})
+	endif()
+	# export RTOS_SUFFIX to parent scope
+	set(RTOS_SUFFIX ${RTOS_SUFFIX} PARENT_SCOPE)
+
+	# compile define from command line
+	if(DEFINED CFLAGS_CLI)
+		separate_arguments(CFLAGS_CLI)
+		target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI})
+	endif()
+
+	pico_add_extra_outputs(${TARGET})
+	pico_enable_stdio_uart(${TARGET} 1)
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_board${RTOS_SUFFIX} tinyusb_additions)
+
+	family_flash_openocd(${TARGET})
+	family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(rp2040_family_configure_example_warnings TARGET)
+	if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS)
+		family_add_default_example_warnings(${TARGET})
+	endif()
+	if(CMAKE_C_COMPILER_ID STREQUAL "Clang")
+		target_compile_options(${TARGET} PRIVATE -Wno-unreachable-code)
+	endif()
+	suppress_tinyusb_warnings()
+endfunction()
+
+
+function(family_configure_device_example TARGET RTOS)
+	family_configure_target(${TARGET} ${RTOS})
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device${RTOS_SUFFIX})
+	rp2040_family_configure_example_warnings(${TARGET})
+endfunction()
+
+
+function(family_add_pico_pio_usb TARGET)
+	target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
+endfunction()
+
+
+# since Pico-PIO_USB compiler support may lag, and change from version to version, add a function that pico-sdk/pico-examples
+# can check (if present) in case the user has updated their TinyUSB
+function(is_compiler_supported_by_pico_pio_usb OUTVAR)
+	if ((NOT CMAKE_C_COMPILER_ID STREQUAL "GNU"))
+		SET(${OUTVAR} 0 PARENT_SCOPE)
+	else()
+		set(${OUTVAR} 1 PARENT_SCOPE)
+	endif()
+endfunction()
+
+function(family_configure_host_example TARGET RTOS)
+	family_configure_target(${TARGET} ${RTOS})
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host${RTOS_SUFFIX})
+	rp2040_family_configure_example_warnings(${TARGET})
+
+	# For rp2040 enable pico-pio-usb
+	if (TARGET tinyusb_pico_pio_usb)
+		# Pico-PIO-USB does not compile with all pico-sdk supported compilers, so check before enabling it
+		is_compiler_supported_by_pico_pio_usb(PICO_PIO_USB_COMPILER_SUPPORTED)
+		if (PICO_PIO_USB_COMPILER_SUPPORTED)
+			family_add_pico_pio_usb(${PROJECT})
+		endif()
+	endif()
+
+	# for max3421 host
+	if (MAX3421_HOST STREQUAL "1")
+		target_link_libraries(${TARGET} PUBLIC tinyusb_host_max3421)
+	endif()
+endfunction()
+
+
+function(family_configure_dual_usb_example TARGET RTOS)
+	family_configure_target(${TARGET} ${RTOS})
+	# require tinyusb_pico_pio_usb
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb )
+	rp2040_family_configure_example_warnings(${TARGET})
+endfunction()
+
+
+function(check_and_add_pico_pio_usb_support)
+	# check for pico_generate_pio_header (as depending on environment we may be called before SDK is
+	# initialized in which case it isn't available yet), and only do the initialization once
+	if (COMMAND pico_generate_pio_header AND NOT TARGET tinyusb_pico_pio_usb)
+		#------------------------------------
+		# PIO USB for both host and device
+		#------------------------------------
+
+		if (NOT DEFINED PICO_PIO_USB_PATH)
+			set(PICO_PIO_USB_PATH "${TOP}/hw/mcu/raspberry_pi/Pico-PIO-USB")
+		endif()
+
+		if (EXISTS ${PICO_PIO_USB_PATH}/src/pio_usb.c)
+			add_library(tinyusb_pico_pio_usb INTERFACE)
+			target_sources(tinyusb_device_base INTERFACE
+					${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+					)
+			target_sources(tinyusb_host_base INTERFACE
+					${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+					)
+
+			target_sources(tinyusb_pico_pio_usb INTERFACE
+					${PICO_PIO_USB_PATH}/src/pio_usb.c
+					${PICO_PIO_USB_PATH}/src/pio_usb_host.c
+					${PICO_PIO_USB_PATH}/src/pio_usb_device.c
+					${PICO_PIO_USB_PATH}/src/usb_crc.c
+					)
+
+			target_include_directories(tinyusb_pico_pio_usb INTERFACE
+					${PICO_PIO_USB_PATH}/src
+					)
+
+			target_link_libraries(tinyusb_pico_pio_usb INTERFACE
+					hardware_dma
+					hardware_pio
+					pico_multicore
+					)
+
+			target_compile_definitions(tinyusb_pico_pio_usb INTERFACE
+					PIO_USB_USE_TINYUSB
+					)
+
+			pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_tx.pio)
+			pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_rx.pio)
+		endif()
+	endif()
+endfunction()
+
+# Try to add Pico-PIO_USB support now for the case where this file is included directly
+# after Pico SDK initialization, but without using the family_ functions (as is the case
+# when included by the SDK itself)
+check_and_add_pico_pio_usb_support()
+
+
+function(family_initialize_project PROJECT DIR)
+	# call the original version of this function from family_common.cmake
+	_family_initialize_project(${PROJECT} ${DIR})
+	enable_language(C CXX ASM)
+	pico_sdk_init()
+
+	# now re-check for adding Pico-PIO_USB support now SDK is definitely available
+	check_and_add_pico_pio_usb_support()
+endfunction()
+
+
+# This method must be called from the project scope to suppress known warnings in TinyUSB source files
+function(suppress_tinyusb_warnings)
+	# some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior
+	if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+		if (CMAKE_C_COMPILER_VERSION VERSION_LESS 10.0)
+			set(CONVERSION_WARNING_FILES
+				${PICO_TINYUSB_PATH}/src/tusb.c
+				${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
+				${PICO_TINYUSB_PATH}/src/device/usbd.c
+				${PICO_TINYUSB_PATH}/src/device/usbd_control.c
+				${PICO_TINYUSB_PATH}/src/host/usbh.c
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
+				${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
+				${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
+				${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
+				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c
+				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
+				${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
+				${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
+				${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+				)
+			foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES)
+				set_source_files_properties(
+						${SOURCE_FILE}
+						PROPERTIES
+						COMPILE_FLAGS "-Wno-conversion")
+			endforeach()
+		endif()
+		if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0)
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
+					COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds")
+		endif()
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual")
+
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_in.c
+				${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_out.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion")
+
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/lib/networking/dnserver.c
+				${PICO_TINYUSB_PATH}/lib/networking/dhserver.c
+				${PICO_TINYUSB_PATH}/lib/networking/rndis_reports.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion -Wno-sign-conversion")
+
+		if (TARGET tinyusb_pico_pio_usb)
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_device.c
+					${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb.c
+					${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_host.c
+					${PICO_TINYUSB_PATH}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-attributes")
+		endif()
+	elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+				COMPILE_FLAGS "-Wno-unreachable-code")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
+				COMPILE_FLAGS "-Wno-unreachable-code-fallthrough")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-cast-qual")
+	endif()
+endfunction()
diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk
index cf6b53793..25d1ad9c5 100644
--- a/hw/bsp/rp2040/family.mk
+++ b/hw/bsp/rp2040/family.mk
@@ -13,9 +13,6 @@ $(BUILD):
 all: $(BUILD)
 	$(MAKE) -C $(BUILD)
 
-clean:
-	$(RM) -rf $(BUILD)
-
 flash: flash-pyocd
 flash-uf2:
 	@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2
diff --git a/hw/bsp/rp2040/rp2040-openocd.cfg b/hw/bsp/rp2040/rp2040-openocd.cfg
new file mode 100644
index 000000000..3364c595e
--- /dev/null
+++ b/hw/bsp/rp2040/rp2040-openocd.cfg
@@ -0,0 +1,3 @@
+source [find interface/cmsis-dap.cfg]
+adapter speed 5000
+source [find target/rp2040.cfg]
diff --git a/hw/bsp/rx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/rx/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..edf0a8433
--- /dev/null
+++ b/hw/bsp/rx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,177 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU								        0
+#define configENABLE_FPU								        0
+#define configENABLE_TRUSTZONE					        0
+#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+#define configRUN_FREERTOS_SECURE_ONLY          1
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      0
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+#ifdef __RX__
+/* Renesas RX series */
+#define vSoftwareInterruptISR					        INT_Excep_ICU_SWINT
+#define vTickISR								              INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ				      (configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY			  1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
+
+#else
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+#if defined(__NVIC_PRIO_BITS)
+  // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
+	#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+#elif defined(__ECLIC_INTCTLBITS)
+  // RISC-V Bumblebee core from nuclei
+  #define configPRIO_BITS       __ECLIC_INTCTLBITS
+
+#elif defined(__IASMARM__)
+  // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
+  // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
+  // IAR user must update this to correct value of the target MCU
+  #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
+  #define configPRIO_BITS       2
+
+#else
+  #error "FreeRTOS configPRIO_BITS to be defined"
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h b/hw/bsp/rx/boards/gr_citrus/board.h
similarity index 90%
rename from hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
rename to hw/bsp/rx/boards/gr_citrus/board.h
index c7940c56e..617d309c3 100644
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
+++ b/hw/bsp/rx/boards/gr_citrus/board.h
@@ -1,5 +1,5 @@
-/* 
- * The MIT License (MIT)
+/*
+* The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
  *
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: GR Citrus
+   url: https://www.renesas.com/en/products/gadget-renesas/boards/gr-citrus
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,11 +36,6 @@
  extern "C" {
 #endif
 
-#define NEOPIXEL_PIN          48
-
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/rx/boards/gr_citrus/board.mk b/hw/bsp/rx/boards/gr_citrus/board.mk
index 0eba94610..e3af8d9b0 100644
--- a/hw/bsp/rx/boards/gr_citrus/board.mk
+++ b/hw/bsp/rx/boards/gr_citrus/board.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/renesas/rx
-
 CFLAGS += \
   -mcpu=rx610 \
   -misa=v1 \
@@ -11,7 +9,7 @@ MCU_DIR = hw/mcu/renesas/rx/rx63n
 LD_FILE = $(BOARD_PATH)/r5f5631fd.ld
 
 # For freeRTOS port source
-FREERTOS_PORT = RX600
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RX600
 
 # For flash-jlink target
 JLINK_DEVICE = R5F5631F
diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
index 633ddad16..26ad4a6aa 100644
--- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
@@ -33,9 +33,9 @@
  * - Short EMLE pad and 3.3V(GR-CITRUS pin name) with a wire.
  *
  * The pads are [the back side of GR-CITRUS](https://www.slideshare.net/MinaoYamamoto/grcitrusrx631/2).
- * 
+ *
  * Connect the pins between GR-CITRUS and JLink as follows.
- * 
+ *
  * | Function  | GR-CITRUS pin | JLink pin No.| note     |
  * |:---------:|:-------------:|:------------:|:--------:|
  * | VTref     |   3.3V        |   1          |          |
@@ -52,7 +52,7 @@
  * regarding downloading.
  */
 
-#include "../board.h"
+#include "bsp/board_api.h"
 #include "iodefine.h"
 #include "interrupt_handlers.h"
 
@@ -91,7 +91,7 @@ void INT_Excep_SCI0_TXI0(void)
 {
   uint8_t *buf = sci0_buf[0].buf;
   uint32_t cnt = sci0_buf[0].cnt;
-  
+
   if (!buf || !cnt) {
     SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
     return;
@@ -201,6 +201,12 @@ void board_init(void)
   IEN(SCI0, RXI0) = 1;
   IEN(SCI0, TXI0) = 1;
   IEN(SCI0, TEI0) = 1;
+
+  /* Enable USB0 */
+  unsigned short oldPRCR = SYSTEM.PRCR.WORD;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(USB0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | oldPRCR;
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/samd11/boards/luna_d11/board.h b/hw/bsp/rx/boards/rx65n_target/board.h
similarity index 85%
rename from hw/bsp/samd11/boards/luna_d11/board.h
rename to hw/bsp/rx/boards/rx65n_target/board.h
index 1bda92934..8c8e7b95f 100644
--- a/hw/bsp/samd11/boards/luna_d11/board.h
+++ b/hw/bsp/rx/boards/rx65n_target/board.h
@@ -1,5 +1,5 @@
 /*
- * The MIT License (MIT)
+* The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
  *
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: RX65N Target Board
+   url: https://www.renesas.com/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,14 +36,6 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PIN               PIN_PA27 // pin PA22
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            PIN_PA16 // pin PB22
-#define BUTTON_STATE_ACTIVE   0
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/rx/boards/rx65n_target/board.mk b/hw/bsp/rx/boards/rx65n_target/board.mk
index fc76d79fa..90bc0efbb 100644
--- a/hw/bsp/rx/boards/rx65n_target/board.mk
+++ b/hw/bsp/rx/boards/rx65n_target/board.mk
@@ -12,7 +12,7 @@ MCU_DIR = hw/mcu/renesas/rx/rx65n
 LD_FILE = $(BOARD_PATH)/r5f565ne.ld
 
 # For freeRTOS port source
-FREERTOS_PORT = RX600
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RX600
 
 # For flash-jlink target
 JLINK_DEVICE = R5F565NE
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index f189e40e4..66a319541 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -50,7 +50,7 @@
  * regarding downloading.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "iodefine.h"
 #include "interrupt_handlers.h"
 
@@ -126,7 +126,7 @@ void INT_Excep_SCI5_TXI5(void)
 {
   uint8_t *buf = sci_buf[0].buf;
   uint32_t cnt = sci_buf[0].cnt;
-  
+
   if (!buf || !cnt) {
     SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
     return;
@@ -177,7 +177,7 @@ void INT_Excep_SCI5_RXI5(void)
 void INT_Excep_USB0_USBI0(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 #if CFG_TUD_ENABLED
   tud_int_handler(0);
@@ -248,6 +248,12 @@ void board_init(void)
   IEN(ICU,GROUPBL0)  = 1;
   EN(SCI5, TEI5)     = 1;
 
+  /* Enable USB0 */
+  unsigned short oldPRCR = SYSTEM.PRCR.WORD;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(USB0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | oldPRCR;
+
   /* setup USBI0 interrupt. */
   IR(USB0, USBI0)  = 0;
   IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
@@ -272,6 +278,7 @@ int board_uart_read(uint8_t* buf, int len)
   sci_buf[1].buf = buf;
   sci_buf[1].cnt = len;
   SCI5.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
+  // TODO change to non blocking, return -1 immediately if no data
   while (SCI5.SCR.BIT.RE) ;
   return len - sci_buf[1].cnt;
 }
diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk
index f4f8ae088..02ea0dfa4 100644
--- a/hw/bsp/rx/family.mk
+++ b/hw/bsp/rx/family.mk
@@ -16,9 +16,11 @@ CFLAGS += \
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=redundant-decls
 
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
 SRC_C += \
-	src/portable/renesas/usba/dcd_usba.c \
-	src/portable/renesas/usba/hcd_usba.c \
+	src/portable/renesas/rusb2/dcd_rusb2.c \
+	src/portable/renesas/rusb2/hcd_rusb2.c \
 	$(MCU_DIR)/vects.c
 
 INC += \
diff --git a/hw/bsp/samd11/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd11/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6c9ecae2d
--- /dev/null
+++ b/hw/bsp/samd11/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,153 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "sam.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/samd11/boards/cynthion_d11/board.cmake b/hw/bsp/samd11/boards/cynthion_d11/board.cmake
new file mode 100644
index 000000000..0456668e0
--- /dev/null
+++ b/hw/bsp/samd11/boards/cynthion_d11/board.cmake
@@ -0,0 +1,14 @@
+set(JLINK_DEVICE ATSAMD11D14)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/cynthion_d11.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD11D14AM__
+    _BOARD_REVISION_MAJOR_=1
+    _BOARD_REVISION_MINOR_=0
+    )
+
+  target_link_options(${BOARD_TARGET} PUBLIC
+    -Wl,--defsym=BOOTLOADER_SIZE=0x800
+    )
+endfunction()
diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h b/hw/bsp/samd11/boards/cynthion_d11/board.h
similarity index 77%
rename from hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
rename to hw/bsp/samd11/boards/cynthion_d11/board.h
index dcf829d9c..8916e9b83 100644
--- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
+++ b/hw/bsp/samd11/boards/cynthion_d11/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Great Scott Gadgets Cynthion
+   url: https://greatscottgadgets.com/cynthion/
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,20 +36,20 @@
  extern "C" {
 #endif
 
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
 // LED
-#define LED_PIN               _PINNUM(1, 13)
+#define LED_PIN               PIN_PA27 // pin PA22
 #define LED_STATE_ON          0
 
 // Button
-#define BUTTON_PIN            _PINNUM(0, 15)
+#if ((_BOARD_REVISION_MAJOR_ == 0) && (_BOARD_REVISION_MINOR_ < 6))
+#define BUTTON_PIN            PIN_PA16 // pin PB22
+#define BUTTON_PULL_MODE      GPIO_PULL_UP
+#else
+#define BUTTON_PIN            PIN_PA02
+#define BUTTON_PULL_MODE      GPIO_PULL_OFF
+#endif
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
-#define UART_RX_PIN     25
-#define UART_TX_PIN     24
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/samd11/boards/cynthion_d11/board.mk b/hw/bsp/samd11/boards/cynthion_d11/board.mk
new file mode 100644
index 000000000..b1e842ace
--- /dev/null
+++ b/hw/bsp/samd11/boards/cynthion_d11/board.mk
@@ -0,0 +1,22 @@
+BOARD_REVISION_MAJOR ?= 1
+BOARD_REVISION_MINOR ?= 0
+
+CFLAGS += -D__SAMD11D14AM__ \
+	-D_BOARD_REVISION_MAJOR_=$(BOARD_REVISION_MAJOR) \
+	-D_BOARD_REVISION_MINOR_=$(BOARD_REVISION_MINOR)
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/cynthion_d11.ld
+
+# Default bootloader size is now 2K, allow to specify other
+ifeq ($(BOOTLOADER_SIZE), )
+	BOOTLOADER_SIZE := 0x800
+endif
+LDFLAGS += -Wl,--defsym=BOOTLOADER_SIZE=$(BOOTLOADER_SIZE)
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAMD11D14
+
+# flash using dfu-util
+flash: $(BUILD)/$(PROJECT).bin
+	dfu-util -a 0 -d 1d50:615c -D $< || dfu-util -a 0 -d 16d0:05a5 -D $<
diff --git a/hw/bsp/samd11/boards/luna_d11/samd11d14am_flash.ld b/hw/bsp/samd11/boards/cynthion_d11/cynthion_d11.ld
similarity index 95%
rename from hw/bsp/samd11/boards/luna_d11/samd11d14am_flash.ld
rename to hw/bsp/samd11/boards/cynthion_d11/cynthion_d11.ld
index cb633c195..0754e40e1 100644
--- a/hw/bsp/samd11/boards/luna_d11/samd11d14am_flash.ld
+++ b/hw/bsp/samd11/boards/cynthion_d11/cynthion_d11.ld
@@ -32,15 +32,17 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 SEARCH_DIR(.)
 
+ENTRY(Reset_Handler)
+
 /* Memory Spaces Definitions */
 MEMORY
 {
-  rom      (rx)  : ORIGIN = 0x00000000 + 4K, LENGTH = 0x00004000 - 4K
+  rom      (rx)  : ORIGIN = 0x00000000 + BOOTLOADER_SIZE, LENGTH = 0x00004000 - BOOTLOADER_SIZE
   ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/samd11/boards/luna_d11/board.mk b/hw/bsp/samd11/boards/luna_d11/board.mk
deleted file mode 100644
index ad9cfb25d..000000000
--- a/hw/bsp/samd11/boards/luna_d11/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -D__SAMD11D14AM__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/samd11d14am_flash.ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD11D14
-
-# flash using dfu-util
-flash: $(BUILD)/$(PROJECT).bin
-	dfu-util -a 0 -d 1d50:615c -D $< || dfu-util -a 0 -d 16d0:05a5 -D $<
diff --git a/hw/bsp/samd11/boards/samd11_xplained/board.cmake b/hw/bsp/samd11/boards/samd11_xplained/board.cmake
new file mode 100644
index 000000000..13a6e3af7
--- /dev/null
+++ b/hw/bsp/samd11/boards/samd11_xplained/board.cmake
@@ -0,0 +1,8 @@
+set(JLINK_DEVICE ATSAMD11D14)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/samd11d14am_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD11D14AM__
+    )
+endfunction()
diff --git a/hw/bsp/samd11/boards/samd11_xplained/board.h b/hw/bsp/samd11/boards/samd11_xplained/board.h
index cfeac673c..13045ac1d 100644
--- a/hw/bsp/samd11/boards/samd11_xplained/board.h
+++ b/hw/bsp/samd11/boards/samd11_xplained/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: SAMD11 Xplained Pro
+   url: https://www.microchip.com/en-us/development-tool/ATSAMD11-XPRO
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -38,6 +43,7 @@
 // Button
 #define BUTTON_PIN            PIN_PA14 // pin PB22
 #define BUTTON_STATE_ACTIVE   0
+#define BUTTON_PULL_MODE      GPIO_PULL_UP
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld b/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld
index 8b3124c0e..3a35914e2 100644
--- a/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld
+++ b/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -32,6 +32,8 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 SEARCH_DIR(.)
 
+ENTRY(Reset_Handler)
+
 /* Memory Spaces Definitions */
 MEMORY
 {
@@ -40,7 +42,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/samd11/family.c b/hw/bsp/samd11/family.c
index 8d9633971..79ca9de02 100644
--- a/hw/bsp/samd11/family.c
+++ b/hw/bsp/samd11/family.c
@@ -24,9 +24,17 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Microchip
+*/
+
 #include "sam.h"
-#include "bsp/board.h"
-#include "board.h"
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#endif
 
 #include "hal/include/hal_gpio.h"
 #include "hal/include/hal_init.h"
@@ -36,6 +44,14 @@
 #include "hpl_pm_config.h"
 #include "hpl/pm/hpl_pm_base.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -78,7 +94,7 @@ void board_init(void)
 
   // Button init
   gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
+  gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_PULL_MODE);
 
   /* USB Clock init
    * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
diff --git a/hw/bsp/samd11/family.cmake b/hw/bsp/samd11/family.cmake
new file mode 100644
index 000000000..965b1cfb5
--- /dev/null
+++ b/hw/bsp/samd11/family.cmake
@@ -0,0 +1,115 @@
+include_guard()
+
+set(SAM_FAMILY samd11)
+set(SDK_DIR ${TOP}/hw/mcu/microchip/${SAM_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS SAMD11 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -c \"transport select swd\" -f target/at91samdXX.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
+  endif ()
+
+  set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_${SAM_FAMILY}.c)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/gcc/system_${SAM_FAMILY}.c
+    ${SDK_DIR}/hal/src/hal_atomic.c
+    ${SDK_DIR}/hpl/gclk/hpl_gclk.c
+    ${SDK_DIR}/hpl/pm/hpl_pm.c
+    ${SDK_DIR}/hpl/sysctrl/hpl_sysctrl.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}
+    ${SDK_DIR}/config
+    ${SDK_DIR}/include
+    ${SDK_DIR}/hal/include
+    ${SDK_DIR}/hal/utils/include
+    ${SDK_DIR}/hpl/pm
+    ${SDK_DIR}/hpl/port
+    ${SDK_DIR}/hri
+    ${CMSIS_5}/CMSIS/Core/Include
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CONF_DFLL_OVERWRITE_CALIBRATION=0
+    OSC32K_OVERWRITE_CALIBRATION=0
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_SAMD11)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/microchip/samd/dcd_samd.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_openocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index 85cc136a6..c41a0dd37 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -1,27 +1,31 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
   -nostdlib -nostartfiles \
   -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
   -DOSC32K_OVERWRITE_CALIBRATION=0 \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD11
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
-	hw/mcu/microchip/samd11/gcc/gcc/startup_samd11.c \
 	hw/mcu/microchip/samd11/gcc/system_samd11.c \
+	hw/mcu/microchip/samd11/gcc/gcc/startup_samd11.c \
+	hw/mcu/microchip/samd11/hal/src/hal_atomic.c \
 	hw/mcu/microchip/samd11/hpl/gclk/hpl_gclk.c \
 	hw/mcu/microchip/samd11/hpl/pm/hpl_pm.c \
 	hw/mcu/microchip/samd11/hpl/sysctrl/hpl_sysctrl.c \
-	hw/mcu/microchip/samd11/hal/src/hal_atomic.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
@@ -35,6 +39,3 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd11/hri \
 	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Include \
 	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Core/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
diff --git a/hw/bsp/samd21/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd21/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6c9ecae2d
--- /dev/null
+++ b/hw/bsp/samd21/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,153 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "sam.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.cmake b/hw/bsp/samd21/boards/atsamd21_xpro/board.cmake
new file mode 100644
index 000000000..46a3880ed
--- /dev/null
+++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21J18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/samd21j18a_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21J18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.h b/hw/bsp/samd21/boards/atsamd21_xpro/board.h
index a3e03997c..6d2e40c56 100644
--- a/hw/bsp/samd21/boards/atsamd21_xpro/board.h
+++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: SAMD21 Xplained Pro
+   url: https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMD21-XPRO
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/samd21j18a_flash.ld b/hw/bsp/samd21/boards/atsamd21_xpro/samd21j18a_flash.ld
index e2f93416d..d9b086f9c 100644
--- a/hw/bsp/samd21/boards/atsamd21_xpro/samd21j18a_flash.ld
+++ b/hw/bsp/samd21/boards/atsamd21_xpro/samd21j18a_flash.ld
@@ -40,7 +40,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.cmake b/hw/bsp/samd21/boards/circuitplayground_express/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/circuitplayground_express/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.h b/hw/bsp/samd21/boards/circuitplayground_express/board.h
index 2d7da1c0b..6a4ec32a9 100644
--- a/hw/bsp/samd21/boards/circuitplayground_express/board.h
+++ b/hw/bsp/samd21/boards/circuitplayground_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit Circuit Playground Express
+   url: https://www.adafruit.com/product/3333
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd21/boards/circuitplayground_express/circuitplayground_express.ld b/hw/bsp/samd21/boards/circuitplayground_express/circuitplayground_express.ld
index f0c93340c..ce7aff80b 100644
--- a/hw/bsp/samd21/boards/circuitplayground_express/circuitplayground_express.ld
+++ b/hw/bsp/samd21/boards/circuitplayground_express/circuitplayground_express.ld
@@ -40,7 +40,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.cmake b/hw/bsp/samd21/boards/curiosity_nano/board.cmake
new file mode 100644
index 000000000..ff779c0fd
--- /dev/null
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.cmake
@@ -0,0 +1,10 @@
+set(JLINK_DEVICE atsamd21g17a)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/samd21g17a_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G17A__
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.h b/hw/bsp/samd21/boards/curiosity_nano/board.h
index 67924d809..78d701ec9 100644
--- a/hw/bsp/samd21/boards/curiosity_nano/board.h
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: SAMD21 Curiosty Nano
+   url: https://www.microchip.com/en-us/development-tool/dm320119
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd21/boards/curiosity_nano/samd21g17a_flash.ld b/hw/bsp/samd21/boards/curiosity_nano/samd21g17a_flash.ld
index 153f0cbb9..e03a4ce60 100644
--- a/hw/bsp/samd21/boards/curiosity_nano/samd21g17a_flash.ld
+++ b/hw/bsp/samd21/boards/curiosity_nano/samd21g17a_flash.ld
@@ -40,7 +40,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/samd21/boards/cynthion_d21/board.cmake b/hw/bsp/samd21/boards/cynthion_d21/board.cmake
new file mode 100644
index 000000000..fb54b7561
--- /dev/null
+++ b/hw/bsp/samd21/boards/cynthion_d21/board.cmake
@@ -0,0 +1,12 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/samd21g18a_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+  target_link_options(${TARGET} PUBLIC
+    "LINKER:--defsym=BOOTLOADER_SIZE=0x800"
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/luna_d21/board.h b/hw/bsp/samd21/boards/cynthion_d21/board.h
similarity index 93%
rename from hw/bsp/samd21/boards/luna_d21/board.h
rename to hw/bsp/samd21/boards/cynthion_d21/board.h
index 2e0a2a60f..6a2b8c5c6 100644
--- a/hw/bsp/samd21/boards/luna_d21/board.h
+++ b/hw/bsp/samd21/boards/cynthion_d21/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Great Scott Gadgets Cynthion
+   url: https://greatscottgadgets.com/cynthion/
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd21/boards/luna_d21/board.mk b/hw/bsp/samd21/boards/cynthion_d21/board.mk
similarity index 61%
rename from hw/bsp/samd21/boards/luna_d21/board.mk
rename to hw/bsp/samd21/boards/cynthion_d21/board.mk
index 27a634e3a..52c9d60cb 100644
--- a/hw/bsp/samd21/boards/luna_d21/board.mk
+++ b/hw/bsp/samd21/boards/cynthion_d21/board.mk
@@ -2,10 +2,15 @@ CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/samd21g18a_flash.ld
 
+# Default bootloader size is now 2K, allow to specify other
+ifeq ($(BOOTLOADER_SIZE), )
+	BOOTLOADER_SIZE := 0x800
+endif
+LDFLAGS += -Wl,--defsym=BOOTLOADER_SIZE=$(BOOTLOADER_SIZE)
+
 # For flash-jlink target
 JLINK_DEVICE = ATSAMD21G18
 
 # flash using dfu-util
 flash: $(BUILD)/$(PROJECT).bin
 	dfu-util -a 0 -d 1d50:615c -D $< || dfu-util -a 0 -d 16d0:05a5 -D $<
-
diff --git a/hw/bsp/samd21/boards/luna_d21/samd21g18a_flash.ld b/hw/bsp/samd21/boards/cynthion_d21/samd21g18a_flash.ld
similarity index 95%
rename from hw/bsp/samd21/boards/luna_d21/samd21g18a_flash.ld
rename to hw/bsp/samd21/boards/cynthion_d21/samd21g18a_flash.ld
index 158593036..95d71b9e3 100644
--- a/hw/bsp/samd21/boards/luna_d21/samd21g18a_flash.ld
+++ b/hw/bsp/samd21/boards/cynthion_d21/samd21g18a_flash.ld
@@ -35,12 +35,12 @@ SEARCH_DIR(.)
 /* Memory Spaces Definitions */
 MEMORY
 {
-  rom      (rx)  : ORIGIN = 0x00000000 + 4K, LENGTH = 0x00040000 - 4K
+  rom      (rx)  : ORIGIN = 0x00000000 + BOOTLOADER_SIZE, LENGTH = 0x00040000 - BOOTLOADER_SIZE
   ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.cmake b/hw/bsp/samd21/boards/feather_m0_express/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/feather_m0_express/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.h b/hw/bsp/samd21/boards/feather_m0_express/board.h
index b9292b9af..a7f9122ee 100644
--- a/hw/bsp/samd21/boards/feather_m0_express/board.h
+++ b/hw/bsp/samd21/boards/feather_m0_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit Feather M0 Express
+   url: https://www.adafruit.com/product/3403
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -43,6 +48,21 @@
 #define UART_RX_PIN           4
 #define UART_TX_PIN           5
 
+// SPI for USB host shield
+#define MAX3421_SERCOM_ID       4       // SERCOM4
+#define MAX3421_SERCOM_FUNCTION 3       // function D (Sercom Alt)
+
+#define MAX3421_SCK_PIN         (32+11)
+#define MAX3421_MOSI_PIN        (32+10)
+#define MAX3421_MISO_PIN        12
+#define MAX3421_TX_PAD          1 // MOSI = PAD_2, SCK = PAD_3
+#define MAX3421_RX_PAD          0 // MISO = PAD_2
+
+#define MAX3421_CS_PIN          18     // D10
+
+#define MAX3421_INTR_PIN        7      // D10
+#define MAX3421_INTR_EIC_ID     7      // EIC7
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/samd21/boards/feather_m0_express/feather_m0_express.ld b/hw/bsp/samd21/boards/feather_m0_express/feather_m0_express.ld
index f0c93340c..ce7aff80b 100644
--- a/hw/bsp/samd21/boards/feather_m0_express/feather_m0_express.ld
+++ b/hw/bsp/samd21/boards/feather_m0_express/feather_m0_express.ld
@@ -40,7 +40,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.cmake b/hw/bsp/samd21/boards/itsybitsy_m0/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.h b/hw/bsp/samd21/boards/itsybitsy_m0/board.h
index 177fb695e..15a0afb15 100644
--- a/hw/bsp/samd21/boards/itsybitsy_m0/board.h
+++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit ItsyBitsy M0
+   url: https://www.adafruit.com/product/3727
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/itsybitsy_m0.ld b/hw/bsp/samd21/boards/itsybitsy_m0/itsybitsy_m0.ld
index f0c93340c..ce7aff80b 100644
--- a/hw/bsp/samd21/boards/itsybitsy_m0/itsybitsy_m0.ld
+++ b/hw/bsp/samd21/boards/itsybitsy_m0/itsybitsy_m0.ld
@@ -40,7 +40,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.cmake b/hw/bsp/samd21/boards/metro_m0_express/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/metro_m0_express/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h
index 13b7556b0..405c92b02 100644
--- a/hw/bsp/samd21/boards/metro_m0_express/board.h
+++ b/hw/bsp/samd21/boards/metro_m0_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit Metro M0 Express
+   url: https://www.adafruit.com/product/3505
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -43,6 +48,22 @@
 #define UART_RX_PIN           4
 #define UART_TX_PIN           5
 
+// SPI for USB host shield
+#define MAX3421_SERCOM_ID       4       // SERCOM4
+#define MAX3421_SERCOM_FUNCTION 3       // function D (Sercom Alt)
+
+#define MAX3421_SCK_PIN         (32+11)
+#define MAX3421_MOSI_PIN        (32+10)
+#define MAX3421_MISO_PIN        12
+#define MAX3421_TX_PAD          1 // MOSI = PAD_2, SCK = PAD_3
+#define MAX3421_RX_PAD          0 // MISO = PAD_2
+
+#define MAX3421_CS_PIN          18      // D10
+
+#define MAX3421_INTR_PIN        7       // D9
+#define MAX3421_INTR_EIC_ID     7       // EIC7
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/samd21/boards/metro_m0_express/metro_m0_express.ld b/hw/bsp/samd21/boards/metro_m0_express/metro_m0_express.ld
index f0c93340c..ce7aff80b 100644
--- a/hw/bsp/samd21/boards/metro_m0_express/metro_m0_express.ld
+++ b/hw/bsp/samd21/boards/metro_m0_express/metro_m0_express.ld
@@ -40,7 +40,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd21/boards/qtpy/board.cmake b/hw/bsp/samd21/boards/qtpy/board.cmake
new file mode 100644
index 000000000..f6cd446dd
--- /dev/null
+++ b/hw/bsp/samd21/boards/qtpy/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21E18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21E18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/qtpy/board.h b/hw/bsp/samd21/boards/qtpy/board.h
index 6f8325e49..29a9f727f 100644
--- a/hw/bsp/samd21/boards/qtpy/board.h
+++ b/hw/bsp/samd21/boards/qtpy/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit QT Py
+   url: https://www.adafruit.com/product/4600
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd21/boards/qtpy/qtpy.ld b/hw/bsp/samd21/boards/qtpy/qtpy.ld
index f0c93340c..ce7aff80b 100644
--- a/hw/bsp/samd21/boards/qtpy/qtpy.ld
+++ b/hw/bsp/samd21/boards/qtpy/qtpy.ld
@@ -40,7 +40,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.cmake b/hw/bsp/samd21/boards/seeeduino_xiao/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.h b/hw/bsp/samd21/boards/seeeduino_xiao/board.h
index 0d1e9cef1..0a6d1fc7d 100644
--- a/hw/bsp/samd21/boards/seeeduino_xiao/board.h
+++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Seeeduino XIAO
+   url: https://wiki.seeedstudio.com/Seeeduino-XIAO/
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/seeeduino_xiao.ld b/hw/bsp/samd21/boards/seeeduino_xiao/seeeduino_xiao.ld
index cf11c4c35..0d0c4e6c4 100644
--- a/hw/bsp/samd21/boards/seeeduino_xiao/seeeduino_xiao.ld
+++ b/hw/bsp/samd21/boards/seeeduino_xiao/seeeduino_xiao.ld
@@ -40,7 +40,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.cmake b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.h b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h
similarity index 81%
rename from hw/bsp/samd51/boards/feather_m4_express/board.h
rename to hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h
index 1d5ed8040..85be34008 100644
--- a/hw/bsp/samd51/boards/feather_m4_express/board.h
+++ b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: SparkFun SAMD21 Mini
+   url: https://www.sparkfun.com/products/13664
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -32,16 +37,17 @@
 #endif
 
 // LED
-#define LED_PIN               23
+#define LED_PIN               /*PA*/17 /*(D13)*/
 #define LED_STATE_ON          1
 
 // Button
-#define BUTTON_PIN            16 // D5
+#define BUTTON_PIN            /*PA*/14 /*(D2)*/
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
-#define UART_TX_PIN           (32 + 17)
-#define UART_RX_PIN           (32 + 16)
+#define UART_SERCOM           0
+#define UART_RX_PIN           /*PA*/11 /*(D0)*/
+#define UART_TX_PIN           /*PA*/10 /*(D1)*/
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.mk b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.mk
new file mode 100644
index 000000000..d6c9150b3
--- /dev/null
+++ b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.mk
@@ -0,0 +1,9 @@
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/$(BOARD).ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAMD21G18
+
+flash: flash-bossac
diff --git a/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/sparkfun_samd21_mini_usb.ld b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/sparkfun_samd21_mini_usb.ld
new file mode 100644
index 000000000..0754a8e9c
--- /dev/null
+++ b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/sparkfun_samd21_mini_usb.ld
@@ -0,0 +1,146 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000-0x0004 /* 4 bytes used by bootloader to keep data between resets */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+ENTRY(Reset_Handler)
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+        end = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hw/bsp/samd21/boards/trinket_m0/board.cmake b/hw/bsp/samd21/boards/trinket_m0/board.cmake
new file mode 100644
index 000000000..f6cd446dd
--- /dev/null
+++ b/hw/bsp/samd21/boards/trinket_m0/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21E18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21E18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/trinket_m0/board.h b/hw/bsp/samd21/boards/trinket_m0/board.h
index c8692e6bd..22e7cb77f 100644
--- a/hw/bsp/samd21/boards/trinket_m0/board.h
+++ b/hw/bsp/samd21/boards/trinket_m0/board.h
@@ -23,6 +23,11 @@
  *
  */
 
+/* metadata:
+   name: Adafruit Trinket M0
+   url: https://www.adafruit.com/product/3500
+*/
+
 #pragma once
 
 // LED
@@ -31,4 +36,5 @@
 
 // UART
 #define UART_SERCOM           0
-
+#define UART_RX_PIN           7
+#define UART_TX_PIN           6
diff --git a/hw/bsp/samd21/boards/trinket_m0/board.mk b/hw/bsp/samd21/boards/trinket_m0/board.mk
index 803ffe892..6addf13b7 100644
--- a/hw/bsp/samd21/boards/trinket_m0/board.mk
+++ b/hw/bsp/samd21/boards/trinket_m0/board.mk
@@ -2,4 +2,3 @@ CFLAGS += -D__SAMD21E18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/trinket_m0.ld
-
diff --git a/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld b/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld
index f0c93340c..ce7aff80b 100644
--- a/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld
+++ b/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld
@@ -40,7 +40,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index 494dc393a..c360a4a5a 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,10 +24,20 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Microchip
+*/
+
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#endif
+
 #include "hal/include/hal_gpio.h"
 #include "hal/include/hal_init.h"
 #include "hri/hri_nvmctrl_d21.h"
@@ -36,18 +46,9 @@
 #include "hpl_pm_config.h"
 #include "hpl/pm/hpl_pm_base.h"
 
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_Handler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// UART support
-//--------------------------------------------------------------------+
-static void uart_init(void);
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
@@ -59,8 +60,26 @@ static void uart_init(void);
 /* Not referenced GCLKs, initialized last */
 #define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
 
-void board_init(void)
-{
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_Handler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// Implementation
+//--------------------------------------------------------------------+
+static void uart_init(void);
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+#define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
+
+static void max3421_init(void);
+
+#endif
+
+void board_init(void) {
   // Clock init ( follow hpl_init.c )
   hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
 
@@ -75,7 +94,7 @@ void board_init(void)
   // Update SystemCoreClock since it is hard coded with asf4 and not correct
   // Init 1ms tick timer (samd SystemCoreClock may not correct)
   SystemCoreClock = CONF_CPU_FREQUENCY;
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
   SysTick_Config(CONF_CPU_FREQUENCY / 1000);
 #endif
 
@@ -93,7 +112,7 @@ void board_init(void)
 
   uart_init();
 
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
@@ -124,22 +143,24 @@ void board_init(void)
 
   gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3);
   _gclk_enable_channel(TCC0_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+  max3421_init();
+#endif
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  (void)state;
+void board_led_write(bool state) {
+  (void) state;
 #ifdef LED_PIN
-  gpio_set_pin_level(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  gpio_set_pin_level(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 #endif
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
 #ifdef BUTTON_PIN
   return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
 #else
@@ -155,8 +176,21 @@ uint32_t board_button_read(void)
 static void uart_init(void)
 {
 #if UART_SERCOM == 0
-  gpio_set_pin_function(PIN_PA06, PINMUX_PA06D_SERCOM0_PAD2);
-  gpio_set_pin_function(PIN_PA07, PINMUX_PA07D_SERCOM0_PAD3);
+  #if UART_TX_PIN == 6
+    gpio_set_pin_function(PIN_PA06, PINMUX_PA06D_SERCOM0_PAD2);
+  #elif UART_TX_PIN == 10
+    gpio_set_pin_function(PIN_PA10, PINMUX_PA10C_SERCOM0_PAD2);
+  #else
+    #error "UART_TX_PIN not supported"
+  #endif
+
+  #if UART_RX_PIN == 7
+    gpio_set_pin_function(PIN_PA07, PINMUX_PA07D_SERCOM0_PAD3);
+  #elif UART_RX_PIN == 11
+    gpio_set_pin_function(PIN_PA11, PINMUX_PA11C_SERCOM0_PAD3);
+  #else
+    #error "UART_RX_PIN not supported"
+#endif
 
   // setup clock (48MHz)
   _pm_enable_bus_clock(PM_BUS_APBC, SERCOM0);
@@ -177,6 +211,7 @@ static void uart_init(void)
     SERCOM_USART_CTRLB_TXEN | /* tx enabled */
     SERCOM_USART_CTRLB_RXEN;  /* rx enabled */
 
+  /* 115200 */
   SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26);
 
   SERCOM0->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
@@ -217,33 +252,191 @@ int board_uart_write(void const * buf, int len)
 }
 
 #else // ! defined(UART_SERCOM)
-static void uart_init(void)
-{
 
+static void uart_init(void) {
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
+
 #endif
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+static void max3421_init(void) {
+  //------------- SPI Init -------------//
+  // MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz
+  uint32_t const baudrate = 12000000u;
+
+  // Enable the APB clock for SERCOM
+  PM->APBCMASK.reg |= 1u << (PM_APBCMASK_SERCOM0_Pos + MAX3421_SERCOM_ID);
+
+  // Configure GCLK for SERCOM
+//  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOM4_CORE | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val + MAX3421_SERCOM_ID) |
+                      GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+  while (GCLK->STATUS.bit.SYNCBUSY);
+
+  Sercom* sercom = MAX3421_SERCOM;
+
+  // Disable the SPI module
+  sercom->SPI.CTRLA.bit.ENABLE = 0;
+
+  // Reset the SPI module
+  sercom->SPI.CTRLA.bit.SWRST = 1;
+  while (sercom->SPI.SYNCBUSY.bit.SWRST);
+
+  // Set up SPI in master mode, MSB first, SPI mode 0
+  sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
+                          SERCOM_SPI_CTRLA_MODE(3);
+
+  sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
+  while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
+
+  // Set the baud rate
+  sercom->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) - 1);
+
+  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
+  gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_SCK_PIN, MAX3421_SERCOM_FUNCTION);
+
+  gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MOSI_PIN, MAX3421_SERCOM_FUNCTION);
+
+  gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MISO_PIN, MAX3421_SERCOM_FUNCTION);
+
+  // CS pin
+  gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(MAX3421_CS_PIN, 1);
+
+  // Enable the SPI module
+  sercom->SPI.CTRLA.bit.ENABLE = 1;
+  while (sercom->SPI.SYNCBUSY.bit.ENABLE);
+
+  //------------- External Interrupt -------------//
+
+  // Enable the APB clock for EIC (External Interrupt Controller)
+  PM->APBAMASK.reg |= PM_APBAMASK_EIC;
+
+  // Configure GCLK for EIC
+  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+  while (GCLK->STATUS.bit.SYNCBUSY);
+
+  // Configure PA20 as an input with function A (external interrupt)
+  gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
+  gpio_set_pin_function(MAX3421_INTR_PIN, 0);
+
+  // Disable EIC
+  EIC->CTRL.bit.ENABLE = 0;
+  while (EIC->STATUS.bit.SYNCBUSY);
+
+  // Configure EIC to trigger on falling edge
+  uint8_t const sense_shift = MAX3421_INTR_EIC_ID * 4;
+  EIC->CONFIG[0].reg &= ~(7 << sense_shift);
+  EIC->CONFIG[0].reg |= 2 << sense_shift;
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(EIC_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  // Enable External Interrupt
+  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+  // Enable EIC
+  EIC->CTRL.bit.ENABLE = 1;
+  while (EIC->STATUS.bit.SYNCBUSY);
+}
+
+void EIC_Handler(void) {
+  // Clear the interrupt flag
+  EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+  // Call the TinyUSB interrupt handler
+  tuh_int_handler(1, true);
+}
+
+// API to enable/disable MAX3421 INTR pin interrupt
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+
+  if (enabled) {
+    NVIC_EnableIRQ(EIC_IRQn);
+  } else {
+    NVIC_DisableIRQ(EIC_IRQn);
+  }
+}
+
+// API to control MAX3421 SPI CS
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+  (void) rhport;
+
+  Sercom* sercom = MAX3421_SERCOM;
+
+  for (size_t count = 0; count < xfer_bytes; count++) {
+    // Wait for the transmit buffer to be empty
+    while (!sercom->SPI.INTFLAG.bit.DRE);
+
+    // Write data to be transmitted
+    uint8_t data = 0x00;
+    if (tx_buf) {
+      data = tx_buf[count];
+    }
+
+    sercom->SPI.DATA.reg = (uint32_t) data;
+
+    // Wait for the receive buffer to be filled
+    while (!sercom->SPI.INTFLAG.bit.RXC);
+
+    // Read received data
+    data = (uint8_t) sercom->SPI.DATA.reg;
+    if (rx_buf) {
+      rx_buf[count] = data;
+    }
+  }
+
+  // wait for bus idle and clear flags
+  while (!(sercom->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
+  sercom->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
+
+  return true;
+}
+
 #endif
diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake
new file mode 100644
index 000000000..4a10d6224
--- /dev/null
+++ b/hw/bsp/samd21/family.cmake
@@ -0,0 +1,109 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/microchip/samd21)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS SAMD21 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -c \"transport select swd\" -f target/at91samdXX.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
+  endif ()
+
+  set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_samd21.c)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/gcc/system_samd21.c
+    ${SDK_DIR}/hpl/gclk/hpl_gclk.c
+    ${SDK_DIR}/hpl/pm/hpl_pm.c
+    ${SDK_DIR}/hpl/sysctrl/hpl_sysctrl.c
+    ${SDK_DIR}/hal/src/hal_atomic.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}
+    ${SDK_DIR}/config
+    ${SDK_DIR}/include
+    ${SDK_DIR}/hal/include
+    ${SDK_DIR}/hal/utils/include
+    ${SDK_DIR}/hpl/pm
+    ${SDK_DIR}/hpl/port
+    ${SDK_DIR}/hri
+    ${SDK_DIR}/CMSIS/Include
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CONF_DFLL_OVERWRITE_CALIBRATION=0
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_SAMD21)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/microchip/samd/dcd_samd.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_openocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index 95421e753..08c5c5b0e 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -1,43 +1,46 @@
 UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += hw/mcu/microchip
+SDK_DIR = hw/mcu/microchip/samd21
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -nostdlib -nostartfiles \
   -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD21
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
+
+LDFLAGS_CLANG +=
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
-	hw/mcu/microchip/samd21/gcc/gcc/startup_samd21.c \
-	hw/mcu/microchip/samd21/gcc/system_samd21.c \
-	hw/mcu/microchip/samd21/hpl/gclk/hpl_gclk.c \
-	hw/mcu/microchip/samd21/hpl/pm/hpl_pm.c \
-	hw/mcu/microchip/samd21/hpl/sysctrl/hpl_sysctrl.c \
-	hw/mcu/microchip/samd21/hal/src/hal_atomic.c
+	${SDK_DIR}/gcc/gcc/startup_samd21.c \
+	${SDK_DIR}/gcc/system_samd21.c \
+	${SDK_DIR}/hal/src/hal_atomic.c \
+	${SDK_DIR}/hpl/gclk/hpl_gclk.c \
+	${SDK_DIR}/hpl/pm/hpl_pm.c \
+	${SDK_DIR}/hpl/sysctrl/hpl_sysctrl.c \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/hw/mcu/microchip/samd21/ \
-	$(TOP)/hw/mcu/microchip/samd21/config \
-	$(TOP)/hw/mcu/microchip/samd21/include \
-	$(TOP)/hw/mcu/microchip/samd21/hal/include \
-	$(TOP)/hw/mcu/microchip/samd21/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/samd21/hpl/pm/ \
-	$(TOP)/hw/mcu/microchip/samd21/hpl/port \
-	$(TOP)/hw/mcu/microchip/samd21/hri \
-	$(TOP)/hw/mcu/microchip/samd21/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+	$(TOP)/${SDK_DIR} \
+	$(TOP)/${SDK_DIR}/config \
+	$(TOP)/${SDK_DIR}/include \
+	$(TOP)/${SDK_DIR}/hal/include \
+	$(TOP)/${SDK_DIR}/hal/utils/include \
+	$(TOP)/${SDK_DIR}/hpl/pm/ \
+	$(TOP)/${SDK_DIR}/hpl/port \
+	$(TOP)/${SDK_DIR}/hri \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
deleted file mode 100644
index 020e638c4..000000000
--- a/hw/bsp/samd51/family.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "sam.h"
-#include "bsp/board.h"
-#include "board.h"
-
-#include "hal/include/hal_gpio.h"
-#include "hal/include/hal_init.h"
-#include "hpl/gclk/hpl_gclk_base.h"
-#include "hpl_mclk_config.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_0_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-void USB_1_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-void USB_2_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-void USB_3_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-/* Referenced GCLKs, should be initialized firstly */
-#define _GCLK_INIT_1ST 0xFFFFFFFF
-
-/* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
-
-void board_init(void)
-{
-  // Clock init ( follow hpl_init.c )
-  hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, 0);
-
-  _osc32kctrl_init_sources();
-  _oscctrl_init_sources();
-  _mclk_init();
-#if _GCLK_INIT_1ST
-  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
-#endif
-  _oscctrl_init_referenced_generators();
-  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
-
-  // Update SystemCoreClock since it is hard coded with asf4 and not correct
-  // Init 1ms tick timer (samd SystemCoreClock may not correct)
-  SystemCoreClock = CONF_CPU_FREQUENCY;
-  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-
-  // Led init
-  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(LED_PIN, 0);
-
-  // Button init
-  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  /* USB Clock init
-   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-   * for low speed and full speed operation. */
-  hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
-  hri_mclk_set_AHBMASK_USB_bit(MCLK);
-  hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
-  // USB Pin Init
-  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA24, false);
-  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA25, false);
-  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-  gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
-  gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  gpio_set_pin_level(LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  // button is active low
-  return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
deleted file mode 100644
index 783bed82a..000000000
--- a/hw/bsp/samd51/family.mk
+++ /dev/null
@@ -1,50 +0,0 @@
-UF2_FAMILY_ID = 0x55114460
-DEPS_SUBMODULES += hw/mcu/microchip
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_SAMD51
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
-
-SRC_C += \
-	src/portable/microchip/samd/dcd_samd.c \
-	hw/mcu/microchip/samd51/gcc/gcc/startup_samd51.c \
-	hw/mcu/microchip/samd51/gcc/system_samd51.c \
-	hw/mcu/microchip/samd51/hpl/gclk/hpl_gclk.c \
-	hw/mcu/microchip/samd51/hpl/mclk/hpl_mclk.c \
-	hw/mcu/microchip/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c \
-	hw/mcu/microchip/samd51/hpl/oscctrl/hpl_oscctrl.c \
-	hw/mcu/microchip/samd51/hal/src/hal_atomic.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/hw/mcu/microchip/samd51/ \
-	$(TOP)/hw/mcu/microchip/samd51/config \
-	$(TOP)/hw/mcu/microchip/samd51/include \
-	$(TOP)/hw/mcu/microchip/samd51/hal/include \
-	$(TOP)/hw/mcu/microchip/samd51/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/samd51/hpl/port \
-	$(TOP)/hw/mcu/microchip/samd51/hri \
-	$(TOP)/hw/mcu/microchip/samd51/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# flash using bossac at least version 1.8
-# can be found in arduino15/packages/arduino/tools/bossac/
-# Add it to your PATH or change BOSSAC variable to match your installation
-BOSSAC = bossac
-
-flash-bossac: $(BUILD)/$(PROJECT).bin
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(BOSSAC) --port=$(SERIAL) -U -i --offset=0x4000 -e -w $^ -R
diff --git a/hw/bsp/samd5x_e5x/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd5x_e5x/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..a283560fe
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "sam.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*6*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/samd5x_e5x/boards/d5035_01/board.cmake b/hw/bsp/samd5x_e5x/boards/d5035_01/board.cmake
new file mode 100644
index 000000000..adf4f6a6d
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/d5035_01/board.cmake
@@ -0,0 +1,13 @@
+set(SAM_FAMILY same51)
+
+set(JLINK_DEVICE ATSAME51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/same51j19a_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAME51J19A__
+    SVC_Handler=SVCall_Handler
+    CONF_CPU_FREQUENCY=80000000
+    CONF_GCLK_USB_FREQUENCY=48000000
+    )
+endfunction()
diff --git a/hw/bsp/samd5x_e5x/boards/d5035_01/board.h b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h
new file mode 100644
index 000000000..4eb4a4ebe
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h
@@ -0,0 +1,203 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: D5035-01
+   url: https://github.com/RudolphRiedel/USB_CAN-FD
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PIN               PIN_PA02
+#define LED_STATE_ON          1
+
+// Button: no button
+
+// UART: HWREV < 3: SERCOM5 on PB02, otherwise SERCOM0 on PA08
+// XTAL configure is also different for HWREV as well
+
+#if 0
+static inline void init_clock(void) {
+  /* AUTOWS is enabled by default in REG_NVMCTRL_CTRLA - no need to change the number of wait states when changing the core clock */
+#if HWREV == 1
+  /* configure XOSC1 for a 16MHz crystal connected to XIN1/XOUT1 */
+  OSCCTRL->XOSCCTRL[1].reg =
+    OSCCTRL_XOSCCTRL_STARTUP(6) |    // 1,953 ms
+    OSCCTRL_XOSCCTRL_RUNSTDBY |
+    OSCCTRL_XOSCCTRL_ENALC |
+    OSCCTRL_XOSCCTRL_IMULT(4) |
+    OSCCTRL_XOSCCTRL_IPTAT(3) |
+    OSCCTRL_XOSCCTRL_XTALEN |
+    OSCCTRL_XOSCCTRL_ENABLE;
+  while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
+
+  OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 8, input = XOSC1 */
+  OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
+  OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
+  while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
+
+  OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 16, input = XOSC1 */
+  OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
+  OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
+  while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
+#else // HWREV >= 1
+  /* configure XOSC0 for a 16MHz crystal connected to XIN0/XOUT0 */
+  OSCCTRL->XOSCCTRL[0].reg =
+      OSCCTRL_XOSCCTRL_STARTUP(6) |    // 1,953 ms
+      OSCCTRL_XOSCCTRL_RUNSTDBY |
+      OSCCTRL_XOSCCTRL_ENALC |
+      OSCCTRL_XOSCCTRL_IMULT(4) |
+      OSCCTRL_XOSCCTRL_IPTAT(3) |
+      OSCCTRL_XOSCCTRL_XTALEN |
+      OSCCTRL_XOSCCTRL_ENABLE;
+  while (0 == OSCCTRL->STATUS.bit.XOSCRDY0);
+
+  OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(
+      OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 8, input = XOSC1 */
+  OSCCTRL->Dpll[0].DPLLRATIO.reg =
+      OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
+  OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
+  while (0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
+
+  OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(
+      OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 16, input = XOSC1 */
+  OSCCTRL->Dpll[1].DPLLRATIO.reg =
+      OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
+  OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
+  while (0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
+#endif // HWREV
+
+  /* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
+  GCLK->GENCTRL[0].reg =
+      GCLK_GENCTRL_DIV(0) |
+      GCLK_GENCTRL_RUNSTDBY |
+      GCLK_GENCTRL_GENEN |
+      GCLK_GENCTRL_SRC_DPLL0 |  /* DPLL0 */
+      GCLK_GENCTRL_IDC;
+  while (1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
+
+  /* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */
+  GCLK->GENCTRL[1].reg =
+      GCLK_GENCTRL_DIV(0) |
+      GCLK_GENCTRL_RUNSTDBY |
+      GCLK_GENCTRL_GENEN |
+      GCLK_GENCTRL_SRC_DPLL1 |
+      GCLK_GENCTRL_IDC;
+  while (1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */
+
+  /* configure clock-generator 2 to use DPLL0 as source -> for use with SERCOM */
+  GCLK->GENCTRL[2].reg =
+      GCLK_GENCTRL_DIV(1) |  /* 80MHz */
+      GCLK_GENCTRL_RUNSTDBY |
+      GCLK_GENCTRL_GENEN |
+      GCLK_GENCTRL_SRC_DPLL0 |
+      GCLK_GENCTRL_IDC;
+  while (1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
+}
+
+static inline void uart_init(void) {
+#if HWREV < 3
+  /* configure SERCOM5 on PB02 */
+  PORT->Group[1].WRCONFIG.reg =
+      PORT_WRCONFIG_WRPINCFG |
+      PORT_WRCONFIG_WRPMUX |
+      PORT_WRCONFIG_PMUX(3) |    /* function D */
+      PORT_WRCONFIG_DRVSTR |
+      PORT_WRCONFIG_PINMASK(0x0004) | /* PB02 */
+      PORT_WRCONFIG_PMUXEN;
+
+  MCLK->APBDMASK.bit.SERCOM5_ = 1;
+  GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg =
+      GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
+
+  SERCOM5->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
+  while (SERCOM5->USART.SYNCBUSY.bit.ENABLE);
+
+  SERCOM5->USART.CTRLA.reg =  /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
+      SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
+      //    SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
+      SERCOM_USART_CTRLA_DORD | /* LSB first */
+      SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
+      SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
+      SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
+
+  SERCOM5->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
+      SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
+  SERCOM5->USART.CTRLC.reg = 0x00;
+  // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
+  SERCOM5->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
+
+//  SERCOM5->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+  SERCOM5->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
+  while (SERCOM5->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
+#else
+  /* configure SERCOM0 on PA08 */
+    PORT->Group[0].WRCONFIG.reg =
+      PORT_WRCONFIG_WRPINCFG |
+      PORT_WRCONFIG_WRPMUX |
+      PORT_WRCONFIG_PMUX(2) |    /* function C */
+      PORT_WRCONFIG_DRVSTR |
+      PORT_WRCONFIG_PINMASK(0x0100) | /* PA08 */
+      PORT_WRCONFIG_PMUXEN;
+
+    MCLK->APBAMASK.bit.SERCOM0_ = 1;
+    GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
+
+    SERCOM0->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
+    while(SERCOM0->USART.SYNCBUSY.bit.ENABLE);
+
+    SERCOM0->USART.CTRLA.reg  =  /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
+      SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
+  //    SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
+      SERCOM_USART_CTRLA_DORD | /* LSB first */
+      SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
+      SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
+      SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
+
+    SERCOM0->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
+      SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
+    SERCOM0->USART.CTRLC.reg = 0x00;
+    // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
+    SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
+
+  //  SERCOM0->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+    SERCOM0->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
+    while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
+#endif
+}
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/samd5x_e5x/boards/d5035_01/board.mk b/hw/bsp/samd5x_e5x/boards/d5035_01/board.mk
new file mode 100644
index 000000000..4aa6b89fe
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/d5035_01/board.mk
@@ -0,0 +1,21 @@
+SAM_FAMILY = same51
+
+HWREV ?= 1
+
+CFLAGS += \
+  -D__SAME51J19A__ \
+  -DCONF_CPU_FREQUENCY=80000000 \
+  -DCONF_GCLK_USB_FREQUENCY=48000000 \
+  -DD5035_01=1 \
+  -DBOARD_NAME="\"D5035-01\"" \
+  -DSVC_Handler=SVCall_Handler \
+  -DHWREV=$(HWREV)
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/same51j19a_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAME51J19
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/d5035_01/same51j19a_flash.ld b/hw/bsp/samd5x_e5x/boards/d5035_01/same51j19a_flash.ld
similarity index 97%
rename from hw/bsp/d5035_01/same51j19a_flash.ld
rename to hw/bsp/samd5x_e5x/boards/d5035_01/same51j19a_flash.ld
index a8dd44336..59afb604b 100644
--- a/hw/bsp/d5035_01/same51j19a_flash.ld
+++ b/hw/bsp/samd5x_e5x/boards/d5035_01/same51j19a_flash.ld
@@ -42,7 +42,9 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+ENTRY(Reset_Handler)
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.cmake b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.cmake
new file mode 100644
index 000000000..86d12ca24
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.cmake
@@ -0,0 +1,10 @@
+set(SAM_FAMILY samd51)
+
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h
new file mode 100644
index 000000000..edb965c9d
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h
@@ -0,0 +1,72 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Adafruit Feather M4 Express
+   url: https://www.adafruit.com/product/3857
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define _PINNUM(port, pin)    ((port)*32 + (pin))
+
+// LED
+#define LED_PIN               23
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PIN            16 // D5
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_TX_PIN           (32 + 17)
+#define UART_RX_PIN           (32 + 16)
+
+// SPI for USB host shield
+#define MAX3421_SERCOM_ID       1  // SERCOM2
+#define MAX3421_SERCOM_FUNCTION 2  // function C
+
+#define MAX3421_SCK_PIN         _PINNUM(0, 17)
+#define MAX3421_MOSI_PIN        _PINNUM(1, 23)
+#define MAX3421_MISO_PIN        _PINNUM(1, 22)
+#define MAX3421_TX_PAD          2 // MOSI = PAD_3, SCK = PAD_1
+#define MAX3421_RX_PAD          2 // MISO = PAD_2
+
+#define MAX3421_CS_PIN          20 // D10
+
+#define MAX3421_INTR_PIN        19 // D9
+#define MAX3421_INTR_EIC_ID     3  // EIC3
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.mk b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.mk
similarity index 86%
rename from hw/bsp/samd51/boards/feather_m4_express/board.mk
rename to hw/bsp/samd5x_e5x/boards/feather_m4_express/board.mk
index a8a98a987..811c5f4e3 100644
--- a/hw/bsp/samd51/boards/feather_m4_express/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
 CFLAGS += -D__SAMD51J19A__
 
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd51/boards/feather_m4_express/feather_m4_express.ld b/hw/bsp/samd5x_e5x/boards/feather_m4_express/feather_m4_express.ld
similarity index 97%
rename from hw/bsp/samd51/boards/feather_m4_express/feather_m4_express.ld
rename to hw/bsp/samd5x_e5x/boards/feather_m4_express/feather_m4_express.ld
index f1a021d75..1408c3018 100644
--- a/hw/bsp/samd51/boards/feather_m4_express/feather_m4_express.ld
+++ b/hw/bsp/samd5x_e5x/boards/feather_m4_express/feather_m4_express.ld
@@ -42,7 +42,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.cmake b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.cmake
new file mode 100644
index 000000000..86d12ca24
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.cmake
@@ -0,0 +1,10 @@
+set(SAM_FAMILY samd51)
+
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/board.h b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h
similarity index 94%
rename from hw/bsp/samd51/boards/itsybitsy_m4/board.h
rename to hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h
index 0760d4288..d41ca4ac3 100644
--- a/hw/bsp/samd51/boards/itsybitsy_m4/board.h
+++ b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit ItsyBitsy M4
+   url: https://www.adafruit.com/product/3800
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.mk b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.mk
similarity index 90%
rename from hw/bsp/samd51/boards/metro_m4_express/board.mk
rename to hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.mk
index d7953cc24..eba7070c1 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
 CFLAGS += -D__SAMD51J19A__
 
 # All source paths should be relative to the top level.
@@ -7,4 +9,3 @@ LD_FILE = $(BOARD_PATH)/$(BOARD).ld
 JLINK_DEVICE = ATSAMD51J19
 
 flash: flash-bossac
-
diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/itsybitsy_m4.ld b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/itsybitsy_m4.ld
similarity index 97%
rename from hw/bsp/samd51/boards/itsybitsy_m4/itsybitsy_m4.ld
rename to hw/bsp/samd5x_e5x/boards/itsybitsy_m4/itsybitsy_m4.ld
index f1a021d75..1408c3018 100644
--- a/hw/bsp/samd51/boards/itsybitsy_m4/itsybitsy_m4.ld
+++ b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/itsybitsy_m4.ld
@@ -42,7 +42,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake
new file mode 100644
index 000000000..ebc32b1f7
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake
@@ -0,0 +1,13 @@
+set(SAM_FAMILY samd51)
+
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+# force max3421e for testing with hardware-in-the-loop
+set(MAX3421_HOST 1)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h
new file mode 100644
index 000000000..b2eaaa54d
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h
@@ -0,0 +1,71 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Adafruit Metro M4 Express
+   url: https://www.adafruit.com/product/3382
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PIN               16
+#define LED_STATE_ON          1
+
+// Button: D5
+#define BUTTON_PIN            (32+14)
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_TX_PIN           23
+#define UART_RX_PIN           22
+
+// SPI for USB host shield
+#define MAX3421_SERCOM_ID       2  // SERCOM2
+#define MAX3421_SERCOM_FUNCTION 2  // function C
+
+#define MAX3421_SCK_PIN         13
+#define MAX3421_MOSI_PIN        12
+#define MAX3421_MISO_PIN        14
+#define MAX3421_TX_PAD          0 // MOSI = PAD_0, SCK = PAD_1
+#define MAX3421_RX_PAD          2 // MISO = PAD_2
+
+#define MAX3421_CS_PIN          18 // D10
+
+#define MAX3421_INTR_PIN        20 // D9
+#define MAX3421_INTR_EIC_ID     4  // EIC4
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/board.mk b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.mk
similarity index 90%
rename from hw/bsp/samd51/boards/itsybitsy_m4/board.mk
rename to hw/bsp/samd5x_e5x/boards/metro_m4_express/board.mk
index 57a680e91..eba7070c1 100644
--- a/hw/bsp/samd51/boards/itsybitsy_m4/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
 CFLAGS += -D__SAMD51J19A__
 
 # All source paths should be relative to the top level.
diff --git a/hw/bsp/samd51/boards/metro_m4_express/metro_m4_express.ld b/hw/bsp/samd5x_e5x/boards/metro_m4_express/metro_m4_express.ld
similarity index 97%
rename from hw/bsp/samd51/boards/metro_m4_express/metro_m4_express.ld
rename to hw/bsp/samd5x_e5x/boards/metro_m4_express/metro_m4_express.ld
index f1a021d75..1408c3018 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/metro_m4_express.ld
+++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/metro_m4_express.ld
@@ -42,7 +42,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd5x_e5x/boards/pybadge/board.cmake b/hw/bsp/samd5x_e5x/boards/pybadge/board.cmake
new file mode 100644
index 000000000..86d12ca24
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/pybadge/board.cmake
@@ -0,0 +1,10 @@
+set(SAM_FAMILY samd51)
+
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd51/boards/pybadge/board.h b/hw/bsp/samd5x_e5x/boards/pybadge/board.h
similarity index 94%
rename from hw/bsp/samd51/boards/pybadge/board.h
rename to hw/bsp/samd5x_e5x/boards/pybadge/board.h
index 1d5ed8040..a5d447db6 100644
--- a/hw/bsp/samd51/boards/pybadge/board.h
+++ b/hw/bsp/samd5x_e5x/boards/pybadge/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit PyBadge
+   url: https://www.adafruit.com/product/4200
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd51/boards/pybadge/board.mk b/hw/bsp/samd5x_e5x/boards/pybadge/board.mk
similarity index 86%
rename from hw/bsp/samd51/boards/pybadge/board.mk
rename to hw/bsp/samd5x_e5x/boards/pybadge/board.mk
index a8a98a987..811c5f4e3 100644
--- a/hw/bsp/samd51/boards/pybadge/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/pybadge/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
 CFLAGS += -D__SAMD51J19A__
 
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd51/boards/pybadge/pybadge.ld b/hw/bsp/samd5x_e5x/boards/pybadge/pybadge.ld
similarity index 97%
rename from hw/bsp/samd51/boards/pybadge/pybadge.ld
rename to hw/bsp/samd5x_e5x/boards/pybadge/pybadge.ld
index f1a021d75..1408c3018 100644
--- a/hw/bsp/samd51/boards/pybadge/pybadge.ld
+++ b/hw/bsp/samd5x_e5x/boards/pybadge/pybadge.ld
@@ -42,7 +42,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd5x_e5x/boards/pyportal/board.cmake b/hw/bsp/samd5x_e5x/boards/pyportal/board.cmake
new file mode 100644
index 000000000..86d12ca24
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/pyportal/board.cmake
@@ -0,0 +1,10 @@
+set(SAM_FAMILY samd51)
+
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd51/boards/pyportal/board.h b/hw/bsp/samd5x_e5x/boards/pyportal/board.h
similarity index 94%
rename from hw/bsp/samd51/boards/pyportal/board.h
rename to hw/bsp/samd5x_e5x/boards/pyportal/board.h
index 9e51ded32..e635e1375 100644
--- a/hw/bsp/samd51/boards/pyportal/board.h
+++ b/hw/bsp/samd5x_e5x/boards/pyportal/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit PyPortal
+   url: https://www.adafruit.com/product/4116
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/samd51/boards/pyportal/board.mk b/hw/bsp/samd5x_e5x/boards/pyportal/board.mk
similarity index 86%
rename from hw/bsp/samd51/boards/pyportal/board.mk
rename to hw/bsp/samd5x_e5x/boards/pyportal/board.mk
index a8a98a987..811c5f4e3 100644
--- a/hw/bsp/samd51/boards/pyportal/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/pyportal/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
 CFLAGS += -D__SAMD51J19A__
 
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd51/boards/pyportal/pyportal.ld b/hw/bsp/samd5x_e5x/boards/pyportal/pyportal.ld
similarity index 97%
rename from hw/bsp/samd51/boards/pyportal/pyportal.ld
rename to hw/bsp/samd5x_e5x/boards/pyportal/pyportal.ld
index f1a021d75..1408c3018 100644
--- a/hw/bsp/samd51/boards/pyportal/pyportal.ld
+++ b/hw/bsp/samd5x_e5x/boards/pyportal/pyportal.ld
@@ -42,7 +42,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
 
 ENTRY(Reset_Handler)
 
diff --git a/hw/bsp/samd5x_e5x/boards/same54_xplained/board.cmake b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.cmake
new file mode 100644
index 000000000..4d98205bc
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.cmake
@@ -0,0 +1,10 @@
+set(SAM_FAMILY same54)
+
+set(JLINK_DEVICE ATSAME54P20)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/same54p20a_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAME54P20A__
+    )
+endfunction()
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h
similarity index 82%
rename from hw/bsp/samd51/boards/metro_m4_express/board.h
rename to hw/bsp/samd5x_e5x/boards/same54_xplained/board.h
index ab10ae4f8..6c252f9d0 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: SAME54 Xplained Pro
+   url: https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAME54-XPRO
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -32,16 +37,16 @@
 #endif
 
 // LED
-#define LED_PIN               16
+#define LED_PIN               PIN_PC18
 #define LED_STATE_ON          1
 
 // Button: D5
-#define BUTTON_PIN            (32+14)
+#define BUTTON_PIN            PIN_PB31
 #define BUTTON_STATE_ACTIVE   0
 
-// UART
-#define UART_TX_PIN           23
-#define UART_RX_PIN           22
+// UART: SERCOM2
+//#define UART_TX_PIN           23
+//#define UART_RX_PIN           22
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/samd5x_e5x/boards/same54_xplained/board.mk b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.mk
new file mode 100644
index 000000000..d10e9e34c
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.mk
@@ -0,0 +1,9 @@
+SAM_FAMILY = same54
+
+CFLAGS += -D__SAME54P20A__
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/same54p20a_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAME54P20
diff --git a/hw/bsp/same54xplainedpro/same54p20a_flash.ld b/hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_flash.ld
similarity index 97%
rename from hw/bsp/same54xplainedpro/same54p20a_flash.ld
rename to hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_flash.ld
index 97072bfe6..8a9fd7d9f 100644
--- a/hw/bsp/same54xplainedpro/same54p20a_flash.ld
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_flash.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -42,7 +42,9 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
+
+ENTRY(Reset_Handler)
 
 /* Section Definitions */
 SECTIONS
@@ -160,4 +162,5 @@ SECTIONS
 
     . = ALIGN(4);
     _end = . ;
+    end = .;
 }
diff --git a/hw/bsp/same54xplainedpro/same54p20a_sram.ld b/hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_sram.ld
similarity index 97%
rename from hw/bsp/same54xplainedpro/same54p20a_sram.ld
rename to hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_sram.ld
index 6219f4afe..c88617729 100644
--- a/hw/bsp/same54xplainedpro/same54p20a_sram.ld
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_sram.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -41,7 +41,9 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
+
+ENTRY(Reset_Handler)
 
 /* Section Definitions */
 SECTIONS
@@ -159,4 +161,5 @@ SECTIONS
 
     . = ALIGN(4);
     _end = . ;
+    end = .;
 }
diff --git a/hw/bsp/samd5x_e5x/family.c b/hw/bsp/samd5x_e5x/family.c
new file mode 100644
index 000000000..8ceddb1be
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/family.c
@@ -0,0 +1,452 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: Microchip
+*/
+
+#include "sam.h"
+#include "bsp/board_api.h"
+#include "board.h"
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#endif
+
+#include "hal_gpio.h"
+#include "hal_init.h"
+#include "hpl/gclk/hpl_gclk_base.h"
+#include "hpl_mclk_config.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+/* Referenced GCLKs, should be initialized firstly */
+#define _GCLK_INIT_1ST 0xFFFFFFFF
+
+/* Not referenced GCLKs, initialized last */
+#define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_0_Handler(void) {
+  tud_int_handler(0);
+}
+
+void USB_1_Handler(void) {
+  tud_int_handler(0);
+}
+
+void USB_2_Handler(void) {
+  tud_int_handler(0);
+}
+
+void USB_3_Handler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// Implementation
+//--------------------------------------------------------------------+
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+
+#define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
+#define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler)
+
+static void max3421_init(void);
+#endif
+
+void board_init(void) {
+  // Clock init ( follow hpl_init.c )
+  hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, 0);
+
+  _osc32kctrl_init_sources();
+  _oscctrl_init_sources();
+  _mclk_init();
+#if _GCLK_INIT_1ST
+  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+  _oscctrl_init_referenced_generators();
+  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+
+  // Update SystemCoreClock since it is hard coded with asf4 and not correct
+  // Init 1ms tick timer (samd SystemCoreClock may not correct)
+  SystemCoreClock = CONF_CPU_FREQUENCY;
+  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
+
+  // Led init
+  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(LED_PIN, 0);
+
+#ifdef BUTTON_PIN
+  // Button init
+  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  /* USB Clock init
+   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
+   * for low speed and full speed operation. */
+  hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
+  hri_mclk_set_AHBMASK_USB_bit(MCLK);
+  hri_mclk_set_APBBMASK_USB_bit(MCLK);
+
+  // USB Pin Init
+  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(PIN_PA24, false);
+  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
+  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(PIN_PA25, false);
+  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
+
+  gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
+  gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+  max3421_init();
+#endif
+}
+
+void board_init_after_tusb(void) {
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  gpio_set_pin_level(LED_PIN, state);
+}
+
+uint32_t board_button_read(void) {
+  // button is active low
+  #ifdef BUTTON_PIN
+  return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
+  #else
+  return 0;
+  #endif
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+
+  uint32_t did_addr[4] = {0x008061FC, 0x00806010, 0x00806014, 0x00806018};
+
+  for (int i = 0; i < 4; i++) {
+    uint32_t did = *((uint32_t const*) did_addr[i]);
+    did = TU_BSWAP32(did); // swap endian to match samd51 uf2 bootloader
+    memcpy(id + i * 4, &did, 4);
+  }
+
+  return 16;
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+#if 0
+/* Initialize SERCOM2 for 115200 bps 8N1 using a 48 MHz clock */
+static inline void uart_init(void) {
+  gpio_set_pin_function(PIN_PB24, PINMUX_PB24D_SERCOM2_PAD1);
+  gpio_set_pin_function(PIN_PB25, PINMUX_PB25D_SERCOM2_PAD0);
+
+  MCLK->APBBMASK.bit.SERCOM2_ = 1;
+  GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
+
+  BOARD_SERCOM->USART.CTRLA.bit.SWRST = 1; /* reset and disable SERCOM -> enable configuration */
+  while (BOARD_SERCOM->USART.SYNCBUSY.bit.SWRST);
+
+  BOARD_SERCOM->USART.CTRLA.reg =
+      SERCOM_USART_CTRLA_SAMPR(0) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
+      SERCOM_USART_CTRLA_SAMPA(0) | /* 16x over sampling */
+      SERCOM_USART_CTRLA_FORM(0) | /* 0x0 USART frame, 0x1 USART frame with parity, ... */
+      SERCOM_USART_CTRLA_DORD | /* LSB first */
+      SERCOM_USART_CTRLA_MODE(1) | /* 0x0 USART with external clock, 0x1 USART with internal clock */
+      SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
+      SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
+
+  BOARD_SERCOM->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
+      SERCOM_USART_CTRLB_TXEN | /* transmitter enabled */
+      SERCOM_USART_CTRLB_RXEN; /* receiver enabled */
+  // BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26); /* 48000000/(16*115200) = 26.041666667 */
+  BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_BAUD(63019); /* 65536*(1−16*115200/48000000) */
+
+  BOARD_SERCOM->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
+  while (BOARD_SERCOM->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
+}
+
+static inline void uart_send_buffer(uint8_t const* text, size_t len) {
+  for (size_t i = 0; i < len; ++i) {
+    BOARD_SERCOM->USART.DATA.reg = text[i];
+    while ((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
+  }
+}
+
+static inline void uart_send_str(const char* text) {
+  while (*text) {
+    BOARD_SERCOM->USART.DATA.reg = *text++;
+    while ((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
+  }
+}
+
+#endif
+
+#endif
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+
+static void max3421_init(void) {
+  //------------- SPI Init -------------//
+
+  // MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz
+  uint32_t const baudrate = 12000000u;
+
+  struct {
+    volatile uint32_t* mck_apb;
+    uint32_t mask;
+    uint8_t gclk_id_core;
+    uint8_t gclk_id_slow;
+  } const sercom_clock[] = {
+      { &MCLK->APBAMASK.reg, MCLK_APBAMASK_SERCOM0, SERCOM0_GCLK_ID_CORE, SERCOM0_GCLK_ID_SLOW },
+      { &MCLK->APBAMASK.reg, MCLK_APBAMASK_SERCOM1, SERCOM1_GCLK_ID_CORE, SERCOM1_GCLK_ID_SLOW },
+      { &MCLK->APBBMASK.reg, MCLK_APBBMASK_SERCOM2, SERCOM2_GCLK_ID_CORE, SERCOM2_GCLK_ID_SLOW },
+      { &MCLK->APBBMASK.reg, MCLK_APBBMASK_SERCOM3, SERCOM3_GCLK_ID_CORE, SERCOM3_GCLK_ID_SLOW },
+      { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM4, SERCOM4_GCLK_ID_CORE, SERCOM4_GCLK_ID_SLOW },
+      { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM5, SERCOM5_GCLK_ID_CORE, SERCOM5_GCLK_ID_SLOW },
+      #ifdef SERCOM6_GCLK_ID_CORE
+      { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM6, SERCOM6_GCLK_ID_CORE, SERCOM6_GCLK_ID_SLOW },
+      #endif
+      #ifdef SERCOM7_GCLK_ID_CORE
+      { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM7, SERCOM7_GCLK_ID_CORE, SERCOM7_GCLK_ID_SLOW },
+      #endif
+  };
+
+  Sercom* sercom = MAX3421_SERCOM;
+
+  // Enable the APB clock for SERCOM
+  *sercom_clock[MAX3421_SERCOM_ID].mck_apb |= sercom_clock[MAX3421_SERCOM_ID].mask;
+
+  // Configure GCLK for SERCOM
+  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg =
+      GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg =
+      GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+  // Disable the SPI module
+  sercom->SPI.CTRLA.bit.ENABLE = 0;
+
+  // Reset the SPI module
+  sercom->SPI.CTRLA.bit.SWRST = 1;
+  while (sercom->SPI.SYNCBUSY.bit.SWRST);
+
+  // Set up SPI in master mode, MSB first, SPI mode 0
+  sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
+                          SERCOM_SPI_CTRLA_MODE(3);
+
+  sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
+  while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
+
+  // Set the baud rate
+  uint8_t baud_reg = (uint8_t) (SystemCoreClock / (2 * baudrate));
+  if (baud_reg) {
+    baud_reg--;
+  }
+
+  sercom->SPI.BAUD.reg = baud_reg;
+
+  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
+  gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_SCK_PIN, MAX3421_SERCOM_FUNCTION);
+
+  gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MOSI_PIN, MAX3421_SERCOM_FUNCTION);
+
+  gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MISO_PIN, MAX3421_SERCOM_FUNCTION);
+
+  // CS pin
+  gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(MAX3421_CS_PIN, 1);
+
+  // Enable the SPI module
+  sercom->SPI.CTRLA.bit.ENABLE = 1;
+  while (sercom->SPI.SYNCBUSY.bit.ENABLE) {}
+
+  //------------- External Interrupt -------------//
+
+  // Enable the APB clock for EIC (External Interrupt Controller)
+  MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+
+  // Configure GCLK for EIC
+  GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+  // Configure PA20 as an input with function A (external interrupt)
+  gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
+  gpio_set_pin_function(MAX3421_INTR_PIN, 0);
+
+  // Disable EIC
+  EIC->CTRLA.bit.ENABLE = 0;
+  while (EIC->SYNCBUSY.bit.ENABLE);
+
+  // Configure EIC to trigger on falling edge
+  volatile uint32_t* eic_config;
+  uint8_t sense_shift;
+  if (MAX3421_INTR_EIC_ID < 8) {
+    eic_config = &EIC->CONFIG[0].reg;
+    sense_shift = MAX3421_INTR_EIC_ID * 4;
+  } else {
+    eic_config = &EIC->CONFIG[1].reg;
+    sense_shift = (MAX3421_INTR_EIC_ID - 8) * 4;
+  }
+
+  *eic_config &= ~(7 << sense_shift);
+  *eic_config |= 2 << sense_shift;
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(EIC_0_IRQn + MAX3421_INTR_EIC_ID, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  // Enable External Interrupt
+  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+  // Enable EIC
+  EIC->CTRLA.bit.ENABLE = 1;
+  while (EIC->SYNCBUSY.bit.ENABLE);
+}
+
+void MAX3421_EIC_Handler(void) {
+  // Clear the interrupt flag
+  EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+  // Call the TinyUSB interrupt handler
+  tuh_int_handler(1, true);
+}
+
+// API to enable/disable MAX3421 INTR pin interrupt
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+
+  const IRQn_Type irq = EIC_0_IRQn + MAX3421_INTR_EIC_ID;
+  if (enabled) {
+    NVIC_EnableIRQ(irq);
+  } else {
+    NVIC_DisableIRQ(irq);
+  }
+}
+
+// API to control MAX3421 SPI CS
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+  (void) rhport;
+
+  Sercom* sercom = MAX3421_SERCOM;
+
+  for (size_t count = 0; count < xfer_bytes; count++) {
+    // Wait for the transmit buffer to be empty
+    while (!sercom->SPI.INTFLAG.bit.DRE);
+
+    // Write data to be transmitted
+    uint8_t data = 0x00;
+    if (tx_buf) {
+      data = tx_buf[count];
+    }
+
+    sercom->SPI.DATA.reg = (uint32_t) data;
+
+    // Wait for the receive buffer to be filled
+    while (!sercom->SPI.INTFLAG.bit.RXC);
+
+    // Read received data
+    data = (uint8_t) sercom->SPI.DATA.reg;
+    if (rx_buf) {
+      rx_buf[count] = data;
+    }
+  }
+
+  // wait for bus idle and clear flags
+  while (!(sercom->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
+  sercom->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
+
+  return true;
+}
+
+#endif
+
+void HardFault_Handler(void) {
+  __BKPT(0);
+  while (1);
+}
diff --git a/hw/bsp/samd5x_e5x/family.cmake b/hw/bsp/samd5x_e5x/family.cmake
new file mode 100644
index 000000000..50e0ec66d
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/family.cmake
@@ -0,0 +1,106 @@
+include_guard()
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(SDK_DIR ${TOP}/hw/mcu/microchip/${SAM_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS SAMD51 SAME54 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -c \"transport select swd\" -c \"set CHIPNAME samd51\" -f target/atsame5x.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
+  endif ()
+
+  set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_${SAM_FAMILY}.c)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/gcc/system_${SAM_FAMILY}.c
+    ${SDK_DIR}/hal/src/hal_atomic.c
+    ${SDK_DIR}/hpl/gclk/hpl_gclk.c
+    ${SDK_DIR}/hpl/mclk/hpl_mclk.c
+    ${SDK_DIR}/hpl/osc32kctrl/hpl_osc32kctrl.c
+    ${SDK_DIR}/hpl/oscctrl/hpl_oscctrl.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}
+    ${SDK_DIR}/config
+    ${SDK_DIR}/include
+    ${SDK_DIR}/hal/include
+    ${SDK_DIR}/hal/utils/include
+    ${SDK_DIR}/hpl/port
+    ${SDK_DIR}/hri
+    ${CMSIS_5}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_SAMD51)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/microchip/samd/dcd_samd.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_openocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/samd5x_e5x/family.mk b/hw/bsp/samd5x_e5x/family.mk
new file mode 100644
index 000000000..9b1a23db4
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/family.mk
@@ -0,0 +1,51 @@
+UF2_FAMILY_ID = 0x55114460
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
+SDK_DIR = hw/mcu/microchip/${SAM_FAMILY}
+
+CFLAGS += \
+  -flto \
+  -DCFG_TUSB_MCU=OPT_MCU_SAMD51
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+SRC_C += \
+	src/portable/microchip/samd/dcd_samd.c \
+	${SDK_DIR}/gcc/gcc/startup_${SAM_FAMILY}.c \
+	${SDK_DIR}/gcc/system_${SAM_FAMILY}.c \
+	${SDK_DIR}/hpl/gclk/hpl_gclk.c \
+	${SDK_DIR}/hpl/mclk/hpl_mclk.c \
+	${SDK_DIR}/hpl/osc32kctrl/hpl_osc32kctrl.c \
+	${SDK_DIR}/hpl/oscctrl/hpl_oscctrl.c \
+	${SDK_DIR}/hal/src/hal_atomic.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/${SDK_DIR} \
+	$(TOP)/${SDK_DIR}/config \
+	$(TOP)/${SDK_DIR}/include \
+	$(TOP)/${SDK_DIR}/hal/include \
+	$(TOP)/${SDK_DIR}/hal/utils/include \
+	$(TOP)/${SDK_DIR}/hpl/port \
+	$(TOP)/${SDK_DIR}/hri \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+
+# flash using bossac at least version 1.8
+# can be found in arduino15/packages/arduino/tools/bossac/
+# Add it to your PATH or change BOSSAC variable to match your installation
+BOSSAC = bossac
+
+flash-bossac: $(BUILD)/$(PROJECT).bin
+	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
+	$(BOSSAC) --port=$(SERIAL) -U -i --offset=0x4000 -e -w $^ -R
+
+# flash using edbg from https://github.com/ataradov/edbg
+flash-edbg: $(BUILD)/$(PROJECT).bin
+	edbg --verbose -t $(MCU) -pv -f $<
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
deleted file mode 100644
index 2d0d928ff..000000000
--- a/hw/bsp/same54xplainedpro/board.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
-CONF_CPU_FREQUENCY ?= 48000000
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mlong-calls \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__SAME54P20A__ \
-  -DCONF_CPU_FREQUENCY=$(CONF_CPU_FREQUENCY) \
-  -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
-  -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
-
-SRC_C += \
-  src/portable/microchip/samd/dcd_samd.c \
-  hw/mcu/microchip/same54/gcc/gcc/startup_same54.c \
-  hw/mcu/microchip/same54/gcc/system_same54.c \
-  hw/mcu/microchip/same54/hal/utils/src/utils_syscalls.c
-
-INC += \
-	$(TOP)/hw/mcu/microchip/same54/ \
-	$(TOP)/hw/mcu/microchip/same54/config \
-	$(TOP)/hw/mcu/microchip/same54/include \
-	$(TOP)/hw/mcu/microchip/same54/hal/include \
-	$(TOP)/hw/mcu/microchip/same54/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/same54/hpl/port \
-	$(TOP)/hw/mcu/microchip/same54/hri \
-	$(TOP)/hw/mcu/microchip/same54/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAME54P20
-
-# flash using edbg from https://github.com/ataradov/edbg
-flash: $(BUILD)/$(PROJECT).bin
-	edbg --verbose -t same54 -pv -f $<
diff --git a/hw/bsp/same54xplainedpro/same54xplainedpro.c b/hw/bsp/same54xplainedpro/same54xplainedpro.c
deleted file mode 100644
index ba1eec38b..000000000
--- a/hw/bsp/same54xplainedpro/same54xplainedpro.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021 Jean Gressmann <jean@0x42.de>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include <sam.h>
-#include "bsp/board.h"
-
-#include <hal/include/hal_gpio.h>
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_0_Handler(void)
-{
-	tud_int_handler(0);
-}
-
-void USB_1_Handler(void)
-{
-	tud_int_handler(0);
-}
-
-void USB_2_Handler(void)
-{
-	tud_int_handler(0);
-}
-
-void USB_3_Handler(void)
-{
-	tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define LED_PIN PIN_PC18
-#define BUTTON_PIN PIN_PB31
-#define BOARD_SERCOM SERCOM2
-
-/** Initializes the clocks from the external 12 MHz crystal
- *
- * The goal of this setup is to preserve the second PLL
- * for the application code while still having a reasonable
- * 48 MHz clock for USB / UART.
- *
- * GCLK0:   CONF_CPU_FREQUENCY (default 120 MHz) from PLL0
- * GCLK1:   unused
- * GCLK2:   12 MHz from XOSC1
- * DFLL48M: closed loop from GLCK2
- * GCLK3:   48 MHz
- */
-static inline void init_clock_xtal(void)
-{
-	/* configure for a 12MHz crystal connected to XIN1/XOUT1 */
-	OSCCTRL->XOSCCTRL[1].reg =
-		OSCCTRL_XOSCCTRL_STARTUP(6) | // 1.953 ms
-		OSCCTRL_XOSCCTRL_RUNSTDBY |
-		OSCCTRL_XOSCCTRL_ENALC |
-		OSCCTRL_XOSCCTRL_IMULT(4) | OSCCTRL_XOSCCTRL_IPTAT(3) | // 8MHz to 16MHz
-		OSCCTRL_XOSCCTRL_XTALEN |
-		OSCCTRL_XOSCCTRL_ENABLE;
-	while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
-
-	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(2) | OSCCTRL_DPLLCTRLB_REFCLK_XOSC1; /* 12MHz / 6 = 2Mhz, input = XOSC1 */
-	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR((CONF_CPU_FREQUENCY / 1000000 / 2) - 1); /* multiply to get CONF_CPU_FREQUENCY (default = 120MHz) */
-	OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
-
-	/* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
-	GCLK->GENCTRL[0].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DPLL0 |
-		GCLK_GENCTRL_IDC;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
-
-	// configure GCLK2 for 12MHz from XOSC1
-	GCLK->GENCTRL[2].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_XOSC1 |
-		GCLK_GENCTRL_IDC;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
-
-	 /* setup DFLL48M to use GLCK2 */
-	GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN;
-
-	OSCCTRL->DFLLCTRLA.reg = 0;
-	while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
-
-	OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_MODE | OSCCTRL_DFLLCTRLB_WAITLOCK;
-	OSCCTRL->DFLLMUL.bit.MUL = 4; // 4 * 12MHz -> 48MHz
-
-	OSCCTRL->DFLLCTRLA.reg =
-		OSCCTRL_DFLLCTRLA_ENABLE |
-		OSCCTRL_DFLLCTRLA_RUNSTDBY;
-	while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
-
-	// setup 48 MHz GCLK3 from DFLL48M
-	GCLK->GENCTRL[3].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DFLL |
-		GCLK_GENCTRL_IDC;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL3);
-}
-
-/* Initialize SERCOM2 for 115200 bps 8N1 using a 48 MHz clock */
-static inline void uart_init(void)
-{
-	gpio_set_pin_function(PIN_PB24, PINMUX_PB24D_SERCOM2_PAD1);
-	gpio_set_pin_function(PIN_PB25, PINMUX_PB25D_SERCOM2_PAD0);
-
-	MCLK->APBBMASK.bit.SERCOM2_ = 1;
-	GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
-
-	BOARD_SERCOM->USART.CTRLA.bit.SWRST = 1; /* reset and disable SERCOM -> enable configuration */
-	while (BOARD_SERCOM->USART.SYNCBUSY.bit.SWRST);
-
-	BOARD_SERCOM->USART.CTRLA.reg  =
-		SERCOM_USART_CTRLA_SAMPR(0) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
-		SERCOM_USART_CTRLA_SAMPA(0) | /* 16x over sampling */
-		SERCOM_USART_CTRLA_FORM(0) | /* 0x0 USART frame, 0x1 USART frame with parity, ... */
-		SERCOM_USART_CTRLA_DORD | /* LSB first */
-		SERCOM_USART_CTRLA_MODE(1) | /* 0x0 USART with external clock, 0x1 USART with internal clock */
-		SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
-		SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
-
-	BOARD_SERCOM->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
-		SERCOM_USART_CTRLB_TXEN | /* transmitter enabled */
-		SERCOM_USART_CTRLB_RXEN; /* receiver enabled */
-	// BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26); /* 48000000/(16*115200) = 26.041666667 */
-	BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_BAUD(63019); /* 65536*(1−16*115200/48000000) */
-
-	BOARD_SERCOM->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
-	while (BOARD_SERCOM->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
-}
-
-static inline void uart_send_buffer(uint8_t const *text, size_t len)
-{
-	for (size_t i = 0; i < len; ++i) {
-		BOARD_SERCOM->USART.DATA.reg = text[i];
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
-	}
-}
-
-static inline void uart_send_str(const char* text)
-{
-	while (*text) {
-		BOARD_SERCOM->USART.DATA.reg = *text++;
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
-	}
-}
-
-
-void board_init(void)
-{
-	// Uncomment this line and change the GCLK for UART/USB to run off the XTAL.
-	// init_clock_xtal();
-
-	SystemCoreClock = CONF_CPU_FREQUENCY;
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-	SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-#endif
-
-	uart_init();
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " UART initialized\n");
-	tu_printf(BOARD_NAME " reset cause %#02x\n", RSTC->RCAUSE.reg);
-#endif
-
-	// LED0 init
-	gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
-	gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-	board_led_write(0);
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " LED pin configured\n");
-#endif
-
-	// BTN0 init
-	gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
-	gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-	gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " Button pin configured\n");
-#endif
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-	// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-	NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-
-#if CFG_TUD_ENABLED
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " USB device enabled\n");
-#endif
-
-	/* USB clock init
-	 * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-	 * for low speed and full speed operation.
-	 */
-	hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN);
-	hri_mclk_set_AHBMASK_USB_bit(MCLK);
-	hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
-	// USB pin init
-	gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(PIN_PA24, false);
-	gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-	gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(PIN_PA25, false);
-	gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-	gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
-	gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
-
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " USB device configured\n");
-#endif
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-	gpio_set_pin_level(LED_PIN, !state);
-}
-
-uint32_t board_button_read(void)
-{
-	return (PORT->Group[1].IN.reg & 0x80000000) != 0x80000000;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-	if (len < 0) {
-		uart_send_str(buf);
-	} else {
-		uart_send_buffer(buf, len);
-	}
-	return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void)
-{
-	system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-	return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
index 2aa09f5dd..281a947f3 100644
--- a/hw/bsp/same70_qmtech/board.mk
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -1,4 +1,5 @@
 DEPS_SUBMODULES += hw/mcu/microchip
+ASF_DIR = hw/mcu/microchip/same70
 
 CFLAGS += \
   -mthumb \
@@ -11,9 +12,12 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant-decls
 
-ASF_DIR = hw/mcu/microchip/same70
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
 
 # All source paths should be relative to the top level.
 LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
@@ -44,7 +48,7 @@ INC += \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM7
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7
 
 # For flash-jlink target
 JLINK_DEVICE = SAME70N19B
diff --git a/hw/bsp/same70_qmtech/same70_qmtech.c b/hw/bsp/same70_qmtech/same70_qmtech.c
index 6e6ad0602..e5f0da198 100644
--- a/hw/bsp/same70_qmtech/same70_qmtech.c
+++ b/hw/bsp/same70_qmtech/same70_qmtech.c
@@ -24,7 +24,7 @@
  */
 
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include "peripheral_clk_config.h"
 #include "hpl/usart/hpl_usart_base.h"
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index cbc51e6b0..3edc128a5 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -1,4 +1,5 @@
 DEPS_SUBMODULES += hw/mcu/microchip
+ASF_DIR = hw/mcu/microchip/same70
 
 CFLAGS += \
   -mthumb \
@@ -11,9 +12,12 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant-decls
 
-ASF_DIR = hw/mcu/microchip/same70
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
 
 # All source paths should be relative to the top level.
 LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
@@ -44,7 +48,7 @@ INC += \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM7
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7
 
 # For flash-jlink target
 JLINK_DEVICE = SAME70Q21B
@@ -53,4 +57,4 @@ JLINK_DEVICE = SAME70Q21B
 # Note: SAME70's GPNVM1 must be set to 1 to boot from flash with
 # 	edbg -t same70 -F w0,1,1
 flash: $(BUILD)/$(PROJECT).bin
-	edbg --verbose -t same70 -pv -f $< 
+	edbg --verbose -t same70 -pv -f $<
diff --git a/hw/bsp/same70_xplained/same70_xplained.c b/hw/bsp/same70_xplained/same70_xplained.c
index e6e7db0f3..f532c6927 100644
--- a/hw/bsp/same70_xplained/same70_xplained.c
+++ b/hw/bsp/same70_xplained/same70_xplained.c
@@ -24,7 +24,7 @@
  */
 
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include "peripheral_clk_config.h"
 #include "hpl/usart/hpl_usart_base.h"
diff --git a/hw/bsp/samg/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samg/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..02223f766
--- /dev/null
+++ b/hw/bsp/samg/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*6*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/samg/boards/samg55_xplained/board.cmake b/hw/bsp/samg/boards/samg55_xplained/board.cmake
new file mode 100644
index 000000000..2635987dc
--- /dev/null
+++ b/hw/bsp/samg/boards/samg55_xplained/board.cmake
@@ -0,0 +1,8 @@
+set(JLINK_DEVICE ATSAMG55J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/samg55j19_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMG55J19__
+    )
+endfunction()
diff --git a/hw/bsp/samg/boards/samg55_xplained/board.h b/hw/bsp/samg/boards/samg55_xplained/board.h
new file mode 100644
index 000000000..53c557ef0
--- /dev/null
+++ b/hw/bsp/samg/boards/samg55_xplained/board.h
@@ -0,0 +1,17 @@
+/* metadata:
+   name: SAMG55 Xplained Pro
+   url: https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMG55-XPRO
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PIN               GPIO(GPIO_PORTA, 6)
+
+#define BUTTON_PIN            GPIO(GPIO_PORTA, 2)
+#define BUTTON_STATE_ACTIVE   0
+
+#define UART_TX_PIN           GPIO(GPIO_PORTA, 28)
+#define UART_RX_PIN           GPIO(GPIO_PORTA, 27)
+
+#endif
diff --git a/hw/bsp/samg/boards/samg55_xplained/board.mk b/hw/bsp/samg/boards/samg55_xplained/board.mk
new file mode 100644
index 000000000..8751ff63e
--- /dev/null
+++ b/hw/bsp/samg/boards/samg55_xplained/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += -D__SAMG55J19__
+
+JLINK_DEVICE = ATSAMG55J19
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/samg55j19_flash.ld
+
+OPENOCD_OPTION = -f board/atmel_samg55_xplained_pro.cfg
+
+flash: flash-openocd
diff --git a/hw/bsp/samg55xplained/samg55j19_flash.ld b/hw/bsp/samg/boards/samg55_xplained/samg55j19_flash.ld
similarity index 95%
rename from hw/bsp/samg55xplained/samg55j19_flash.ld
rename to hw/bsp/samg/boards/samg55_xplained/samg55j19_flash.ld
index 21c0b5bcd..954248114 100644
--- a/hw/bsp/samg55xplained/samg55j19_flash.ld
+++ b/hw/bsp/samg/boards/samg55_xplained/samg55j19_flash.ld
@@ -32,6 +32,8 @@
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 
+ENTRY(Reset_Handler)
+
 /* Memory Spaces Definitions */
 MEMORY
 {
@@ -40,10 +42,10 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
 
 /* The heapsize used by the application. NOTE: you need to adjust according to your application. */
-HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/samg55xplained/samg55xplained.c b/hw/bsp/samg/family.c
similarity index 58%
rename from hw/bsp/samg55xplained/samg55xplained.c
rename to hw/bsp/samg/family.c
index 027c88e2f..8db429e79 100644
--- a/hw/bsp/samg55xplained/samg55xplained.c
+++ b/hw/bsp/samg/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, hathach (tinyusb.org)
@@ -23,8 +23,18 @@
  *
  */
 
+/* metadata:
+   manufacturer: Microchip
+*/
+
 #include "sam.h"
-#include "bsp/board.h"
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
 
 #include "peripheral_clk_config.h"
 #include "hal/include/hal_init.h"
@@ -32,54 +42,53 @@
 #include "hpl/pmc/hpl_pmc.h"
 #include "hal/include/hal_gpio.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
-
-#define LED_PIN               GPIO(GPIO_PORTA, 6)
-
-#define BUTTON_PIN            GPIO(GPIO_PORTA, 2)
-#define BUTTON_STATE_ACTIVE   0
-
-#define UART_TX_PIN           GPIO(GPIO_PORTA, 28)
-#define UART_RX_PIN           GPIO(GPIO_PORTA, 27)
-
 struct _usart_sync_device edbg_com;
 
 //------------- IMPLEMENTATION -------------//
-void board_init(void)
-{
-	init_mcu();
+void board_init(void) {
+  init_mcu();
 
-	_pmc_enable_periph_clock(ID_PIOA);
+  _pmc_enable_periph_clock(ID_PIOA);
 
-	/* Disable Watchdog */
-	hri_wdt_set_MR_WDDIS_bit(WDT);
+  /* Disable Watchdog */
+  hri_wdt_set_MR_WDDIS_bit(WDT);
 
-	// LED
-	gpio_set_pin_level(LED_PIN, false);
-	gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-	gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
+  // LED
+  gpio_set_pin_level(LED_PIN, false);
+  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
 
-	// Button
-	gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-	gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-	gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
+  // Button
+  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
+  gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
 
-	// Uart via EDBG Com
-	_pmc_enable_periph_clock(ID_FLEXCOM7);
-	gpio_set_pin_function(UART_RX_PIN, MUX_PA27B_FLEXCOM7_RXD);
-	gpio_set_pin_function(UART_TX_PIN, MUX_PA28B_FLEXCOM7_TXD);
+  // Uart via EDBG Com
+  _pmc_enable_periph_clock(ID_FLEXCOM7);
+  gpio_set_pin_function(UART_RX_PIN, MUX_PA27B_FLEXCOM7_RXD);
+  gpio_set_pin_function(UART_TX_PIN, MUX_PA28B_FLEXCOM7_TXD);
 
-	_usart_sync_init(&edbg_com, FLEXCOM7);
-	_usart_sync_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
-	_usart_sync_set_mode(&edbg_com, USART_MODE_ASYNCHRONOUS);
-	_usart_sync_enable(&edbg_com);
+  _usart_sync_init(&edbg_com, FLEXCOM7);
+  _usart_sync_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
+  _usart_sync_set_mode(&edbg_com, USART_MODE_ASYNCHRONOUS);
+  _usart_sync_enable(&edbg_com);
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer (samd SystemCoreClock may not correct)
   SysTick_Config(CONF_CPU_FREQUENCY / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  NVIC_SetPriority(UDP_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   // USB Pin, Clock init
@@ -90,17 +99,16 @@ void board_init(void)
   // Enable clock
   _pmc_enable_periph_clock(ID_UDP);
 
-	/* USB Device mode & Transceiver active */
-	hri_matrix_write_CCFG_USBMR_reg(MATRIX, CCFG_USBMR_USBMODE);
+  /* USB Device mode & Transceiver active */
+  hri_matrix_write_CCFG_USBMR_reg(MATRIX, CCFG_USBMR_USBMODE);
 }
 
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
-void UDP_Handler(void)
-{
+void UDP_Handler(void) {
   #if CFG_TUD_ENABLED
-    tud_int_handler(0);
+  tud_int_handler(0);
   #endif
 }
 
@@ -108,50 +116,44 @@ void UDP_Handler(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   gpio_set_pin_level(LED_PIN, state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const * buf8 = (uint8_t const *) buf;
-  for(int i=0; i<len; i++)
-  {
-    while ( !_usart_sync_is_ready_to_send(&edbg_com) ) {}
+int board_uart_write(void const* buf, int len) {
+  uint8_t const* buf8 = (uint8_t const*) buf;
+  for (int i = 0; i < len; i++) {
+    while (!_usart_sync_is_ready_to_send(&edbg_com)) {}
     _usart_sync_write_byte(&edbg_com, buf8[i]);
   }
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 
-void SysTick_Handler (void)
-{
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 
 }
diff --git a/hw/bsp/samg/family.cmake b/hw/bsp/samg/family.cmake
new file mode 100644
index 000000000..eb00c8c52
--- /dev/null
+++ b/hw/bsp/samg/family.cmake
@@ -0,0 +1,113 @@
+include_guard()
+
+set(SAM_FAMILY samg55)
+set(SDK_DIR ${TOP}/hw/mcu/microchip/samg55)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS SAMG CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f board/atmel_samg55_xplained_pro.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
+  endif ()
+
+  set(STARTUP_FILE_GNU ${SDK_DIR}/${SAM_FAMILY}/gcc/gcc/startup_${SAM_FAMILY}.c)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/${SAM_FAMILY}/gcc/system_${SAM_FAMILY}.c
+    ${SDK_DIR}/hal/src/hal_atomic.c
+    ${SDK_DIR}/hpl/core/hpl_init.c
+    ${SDK_DIR}/hpl/usart/hpl_usart.c
+    ${SDK_DIR}/hpl/pmc/hpl_pmc.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${SDK_DIR}
+    ${SDK_DIR}/config
+    ${SDK_DIR}/samg55/include
+    ${SDK_DIR}/hal/include
+    ${SDK_DIR}/hal/utils/include
+    ${SDK_DIR}/hpl/core
+    ${SDK_DIR}/hpl/pio
+    ${SDK_DIR}/hpl/pmc
+    ${SDK_DIR}/hri
+    ${SDK_DIR}/CMSIS/Core/Include
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_SAMG)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/microchip/samg/dcd_samg.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  family_flash_openocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/samg/family.mk b/hw/bsp/samg/family.mk
new file mode 100644
index 000000000..d5d2e6122
--- /dev/null
+++ b/hw/bsp/samg/family.mk
@@ -0,0 +1,45 @@
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
+SDK_DIR = hw/mcu/microchip/samg55
+
+CFLAGS += \
+  -flto \
+  -DCFG_TUSB_MCU=OPT_MCU_SAMG
+
+# suppress following warnings from mcu driver
+CFLAGS += -Wno-error=undef -Wno-error=null-dereference -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
+
+SRC_C += \
+	src/portable/microchip/samg/dcd_samg.c \
+	${SDK_DIR}/samg55/gcc/gcc/startup_samg55.c \
+	${SDK_DIR}/samg55/gcc/system_samg55.c \
+	${SDK_DIR}/hal/src/hal_atomic.c \
+	${SDK_DIR}/hpl/core/hpl_init.c \
+	${SDK_DIR}/hpl/usart/hpl_usart.c \
+	${SDK_DIR}/hpl/pmc/hpl_pmc.c \
+
+INC += \
+  $(TOP)/$(FAMILY_PATH) \
+  $(TOP)/$(BOARD_PATH) \
+	$(TOP)/${SDK_DIR} \
+	$(TOP)/${SDK_DIR}/config \
+	$(TOP)/${SDK_DIR}/samg55/include \
+	$(TOP)/${SDK_DIR}/hal/include \
+	$(TOP)/${SDK_DIR}/hal/utils/include \
+	$(TOP)/${SDK_DIR}/hpl/core \
+	$(TOP)/${SDK_DIR}/hpl/pio \
+	$(TOP)/${SDK_DIR}/hpl/pmc \
+	$(TOP)/${SDK_DIR}/hri \
+	$(TOP)/${SDK_DIR}/CMSIS/Core/Include
+
+# flash using edbg from https://github.com/ataradov/edbg
+flash-edbg: $(BUILD)/$(PROJECT).bin
+	edbg --verbose -t samg55 -pv -f $<
diff --git a/hw/bsp/samg55xplained/hpl_usart_config.h b/hw/bsp/samg/hpl_usart_config.h
similarity index 100%
rename from hw/bsp/samg55xplained/hpl_usart_config.h
rename to hw/bsp/samg/hpl_usart_config.h
diff --git a/hw/bsp/samg55xplained/peripheral_clk_config.h b/hw/bsp/samg/peripheral_clk_config.h
similarity index 96%
rename from hw/bsp/samg55xplained/peripheral_clk_config.h
rename to hw/bsp/samg/peripheral_clk_config.h
index 6d390f388..2fd817e89 100644
--- a/hw/bsp/samg55xplained/peripheral_clk_config.h
+++ b/hw/bsp/samg/peripheral_clk_config.h
@@ -32,13 +32,17 @@
  * \def CONF_SLCK_FREQUENCY
  * \brief Slow Clock frequency
  */
+#ifndef CONF_SLCK_FREQUENCY
 #define CONF_SLCK_FREQUENCY 32768
+#endif
 
 /**
  * \def CONF_MCK_FREQUENCY
  * \brief Master Clock frequency
  */
+#ifndef CONF_MCK_FREQUENCY
 #define CONF_MCK_FREQUENCY 8000000
+#endif
 
 // <o> USB Clock Source
 // <0=> USB Clock Controller (USB_48M)
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
deleted file mode 100644
index d0d0ade01..000000000
--- a/hw/bsp/samg55xplained/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__SAMG55J19__ \
-  -DCFG_TUSB_MCU=OPT_MCU_SAMG
-
-# suppress following warnings from mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=cast-qual -Wno-error=null-dereference -Wno-error=redundant-decls
-
-ASF_DIR = hw/mcu/microchip/samg55
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/samg55j19_flash.ld
-
-SRC_C += \
-	src/portable/microchip/samg/dcd_samg.c \
-	$(ASF_DIR)/samg55/gcc/gcc/startup_samg55.c \
-	$(ASF_DIR)/samg55/gcc/system_samg55.c \
-	$(ASF_DIR)/hpl/core/hpl_init.c \
-	$(ASF_DIR)/hpl/usart/hpl_usart.c \
-	$(ASF_DIR)/hpl/pmc/hpl_pmc.c \
-	$(ASF_DIR)/hal/src/hal_atomic.c
-
-INC += \
-  $(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(ASF_DIR) \
-	$(TOP)/$(ASF_DIR)/config \
-	$(TOP)/$(ASF_DIR)/samg55/include \
-	$(TOP)/$(ASF_DIR)/hal/include \
-	$(TOP)/$(ASF_DIR)/hal/utils/include \
-	$(TOP)/$(ASF_DIR)/hpl/core \
-	$(TOP)/$(ASF_DIR)/hpl/pio \
-	$(TOP)/$(ASF_DIR)/hpl/pmc \
-	$(TOP)/$(ASF_DIR)/hri \
-	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMG55J19
-
-# flash using edbg from https://github.com/ataradov/edbg
-flash: $(BUILD)/$(PROJECT).bin
-	edbg --verbose -t samg55 -pv -f $< 
diff --git a/hw/bsp/saml2x/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/saml2x/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6c9ecae2d
--- /dev/null
+++ b/hw/bsp/saml2x/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,153 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "sam.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.cmake b/hw/bsp/saml2x/boards/atsaml21_xpro/board.cmake
new file mode 100644
index 000000000..874b741cc
--- /dev/null
+++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.cmake
@@ -0,0 +1,9 @@
+set(SAM_FAMILY saml21)
+set(JLINK_DEVICE ATSAML21J18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/saml21j18b_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAML21J18B__
+    )
+endfunction()
diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
index a3e03997c..b93b4e591 100644
--- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
+++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: SAML21 Xplained Pro
+   url: https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
index 5b9acb90b..4ebfa7e71 100644
--- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
+++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
@@ -1,6 +1,6 @@
-CFLAGS += -D__SAML21J18B__ -DCFG_EXAMPLE_VIDEO_READONLY
+SAM_FAMILY = saml21
 
-SAML_VARIANT = saml21
+CFLAGS += -D__SAML21J18B__
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/saml21j18b_flash.ld
diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld b/hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
index 7f6b7fa99..f9523451b 100644
--- a/hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
+++ b/hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
@@ -31,6 +31,8 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 SEARCH_DIR(.)
 
+ENTRY(Reset_Handler)
+
 /* Memory Spaces Definitions */
 MEMORY
 {
@@ -40,7 +42,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.cmake b/hw/bsp/saml2x/boards/saml22_feather/board.cmake
new file mode 100644
index 000000000..7fd79d2ce
--- /dev/null
+++ b/hw/bsp/saml2x/boards/saml22_feather/board.cmake
@@ -0,0 +1,9 @@
+set(SAM_FAMILY saml22)
+set(JLINK_DEVICE ATSAML22J18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAML22J18A__
+    )
+endfunction()
diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.h b/hw/bsp/saml2x/boards/saml22_feather/board.h
index 13a326000..f8660c3f8 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/board.h
+++ b/hw/bsp/saml2x/boards/saml22_feather/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: SAML22 Feather
+   url: https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.mk b/hw/bsp/saml2x/boards/saml22_feather/board.mk
index 0adfdd62c..c7817ff70 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/board.mk
+++ b/hw/bsp/saml2x/boards/saml22_feather/board.mk
@@ -1,6 +1,6 @@
-CFLAGS += -D__SAML22J18A__ -DCFG_EXAMPLE_VIDEO_READONLY
+SAM_FAMILY = saml22
 
-SAML_VARIANT = saml22
+CFLAGS += -D__SAML22J18A__
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld b/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
index d1aaa44fc..a04305be7 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
+++ b/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -32,6 +32,8 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 SEARCH_DIR(.)
 
+ENTRY(Reset_Handler)
+
 /* Memory Spaces Definitions */
 MEMORY
 {
@@ -40,9 +42,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-ENTRY(Reset_Handler)
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.cmake b/hw/bsp/saml2x/boards/sensorwatch_m0/board.cmake
new file mode 100644
index 000000000..67d26475f
--- /dev/null
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.cmake
@@ -0,0 +1,9 @@
+set(SAM_FAMILY saml22)
+set(JLINK_DEVICE ATSAML21J18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAML22J18A__
+    )
+endfunction()
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
index 7fc690ab2..502c799db 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: SensorWatch
+   url: https://github.com/joeycastillo/Sensor-Watch
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
index 0adfdd62c..c7817ff70 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
@@ -1,6 +1,6 @@
-CFLAGS += -D__SAML22J18A__ -DCFG_EXAMPLE_VIDEO_READONLY
+SAM_FAMILY = saml22
 
-SAML_VARIANT = saml22
+CFLAGS += -D__SAML22J18A__
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld b/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
index d1aaa44fc..a04305be7 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -32,6 +32,8 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 SEARCH_DIR(.)
 
+ENTRY(Reset_Handler)
+
 /* Memory Spaces Definitions */
 MEMORY
 {
@@ -40,9 +42,7 @@ MEMORY
 }
 
 /* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-ENTRY(Reset_Handler)
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
 
 /* Section Definitions */
 SECTIONS
diff --git a/hw/bsp/saml2x/family.c b/hw/bsp/saml2x/family.c
index 470fde750..cdc65baf1 100644
--- a/hw/bsp/saml2x/family.c
+++ b/hw/bsp/saml2x/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,20 +24,34 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Microchip
+*/
+
 #include "sam.h"
-#include "bsp/board.h"
-#include "board.h"
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#endif
 
 #include "hal/include/hal_gpio.h"
 #include "hal/include/hal_init.h"
 #include "hpl/gclk/hpl_gclk_base.h"
 #include "hpl_mclk_config.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_Handler(void)
-{
+void USB_Handler(void) {
   tud_int_handler(0);
 }
 
@@ -50,8 +64,7 @@ void USB_Handler(void)
 /* Not referenced GCLKs, initialized last */
 #define _GCLK_INIT_LAST 0x0000001F
 
-void board_init(void)
-{
+void board_init(void) {
   // Clock init ( follow hpl_init.c )
   hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
 
@@ -84,7 +97,7 @@ void board_init(void)
   gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
   gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP);
 
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
@@ -121,43 +134,39 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   gpio_set_pin_level(LED_PIN, state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   // button is active low
   return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler (void)
-{
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
-void _init(void)
-{
+
+void _init(void) {
 
 }
diff --git a/hw/bsp/saml2x/family.cmake b/hw/bsp/saml2x/family.cmake
new file mode 100644
index 000000000..49f2e3e75
--- /dev/null
+++ b/hw/bsp/saml2x/family.cmake
@@ -0,0 +1,115 @@
+include_guard()
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(SDK_DIR ${TOP}/hw/mcu/microchip/${SAM_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS SAML21 SAML22 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -c \"transport select swd\" -f target/at91samdXX.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
+  endif ()
+
+  set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_${SAM_FAMILY}.c)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/gcc/system_${SAM_FAMILY}.c
+    ${SDK_DIR}/hal/src/hal_atomic.c
+    ${SDK_DIR}/hpl/gclk/hpl_gclk.c
+    ${SDK_DIR}/hpl/mclk/hpl_mclk.c
+    ${SDK_DIR}/hpl/osc32kctrl/hpl_osc32kctrl.c
+    ${SDK_DIR}/hpl/oscctrl/hpl_oscctrl.c
+    ${SDK_DIR}/hpl/pm/hpl_pm.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}
+    ${SDK_DIR}/config
+    ${SDK_DIR}/include
+    ${SDK_DIR}/hal/include
+    ${SDK_DIR}/hal/utils/include
+    ${SDK_DIR}/hpl/pm
+    ${SDK_DIR}/hpl/port
+    ${SDK_DIR}/hri
+    ${CMSIS_5}/CMSIS/Core/Include
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CONF_OSC32K_CALIB_ENABLE=0
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_SAML22)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/microchip/samd/dcd_samd.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_openocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index afb0afc03..65dfe5032 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -1,45 +1,47 @@
 UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/microchip
+SDK_DIR = hw/mcu/microchip/$(SAM_FAMILY)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
-
-MCU_DIR = hw/mcu/microchip/$(SAML_VARIANT)
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -nostdlib -nostartfiles \
+  -flto \
   -DCONF_OSC32K_CALIB_ENABLE=0 \
-  -DCFG_TUSB_MCU=OPT_MCU_SAML22
+  -DCFG_TUSB_MCU=OPT_MCU_SAML22 \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
-	$(MCU_DIR)/gcc/gcc/startup_$(SAML_VARIANT).c \
-	$(MCU_DIR)/gcc/system_$(SAML_VARIANT).c \
-	$(MCU_DIR)/hpl/gclk/hpl_gclk.c \
-	$(MCU_DIR)/hpl/mclk/hpl_mclk.c \
-	$(MCU_DIR)/hpl/pm/hpl_pm.c \
-	$(MCU_DIR)/hpl/osc32kctrl/hpl_osc32kctrl.c \
-	$(MCU_DIR)/hpl/oscctrl/hpl_oscctrl.c \
-	$(MCU_DIR)/hal/src/hal_atomic.c
+	$(SDK_DIR)/gcc/gcc/startup_$(SAM_FAMILY).c \
+	$(SDK_DIR)/gcc/system_$(SAM_FAMILY).c \
+	$(SDK_DIR)/hal/src/hal_atomic.c \
+	$(SDK_DIR)/hpl/gclk/hpl_gclk.c \
+	$(SDK_DIR)/hpl/mclk/hpl_mclk.c \
+	$(SDK_DIR)/hpl/osc32kctrl/hpl_osc32kctrl.c \
+	$(SDK_DIR)/hpl/oscctrl/hpl_oscctrl.c \
+	$(SDK_DIR)/hpl/pm/hpl_pm.c \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/ \
-	$(TOP)/$(MCU_DIR)/config \
-	$(TOP)/$(MCU_DIR)/include \
-	$(TOP)/$(MCU_DIR)/hal/include \
-	$(TOP)/$(MCU_DIR)/hal/utils/include \
-	$(TOP)/$(MCU_DIR)/hpl/port \
-	$(TOP)/$(MCU_DIR)/hri \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+	$(TOP)/${SDK_DIR} \
+	$(TOP)/${SDK_DIR}/config \
+	$(TOP)/${SDK_DIR}/include \
+	$(TOP)/${SDK_DIR}/hal/include \
+	$(TOP)/${SDK_DIR}/hal/utils/include \
+	$(TOP)/${SDK_DIR}/hpl/pm/ \
+	$(TOP)/${SDK_DIR}/hpl/port \
+	$(TOP)/${SDK_DIR}/hri \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index ddafa8a2b..687761364 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -19,12 +19,16 @@ SILABS_CMSIS = hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)/Device/SiliconLabs/$(she
 DEPS_SUBMODULES += hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)
 DEPS_SUBMODULES += lib/CMSIS_5
 
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
 # All source paths should be relative to the top level.
 LD_FILE = $(SILABS_CMSIS)/Source/GCC/$(SILABS_FAMILY).ld
 
 SRC_C += \
   $(SILABS_CMSIS)/Source/system_$(SILABS_FAMILY).c \
-	src/portable/synopsys/dwc2/dcd_dwc2.c
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
 
 SRC_S += \
   $(SILABS_CMSIS)/Source/GCC/startup_$(SILABS_FAMILY).S
@@ -35,7 +39,7 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = EFM32GG12B810F1024
diff --git a/hw/bsp/sltb009a/sltb009a.c b/hw/bsp/sltb009a/sltb009a.c
index b929adb13..23ef6d7cd 100644
--- a/hw/bsp/sltb009a/sltb009a.c
+++ b/hw/bsp/sltb009a/sltb009a.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Rafael Silva (@perigoso)
@@ -25,7 +25,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#include "../board_api.h"
 
 #include "em_device.h"
 
@@ -397,7 +397,7 @@ void cmu_init(void)
     CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO;
     while((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) != CMU_HFCLKSTATUS_SELECTED_HFXO);
 
-    // Calibrate HFRCO for 72MHz and enable tunning by PLL
+    // Calibrate HFRCO for 72MHz and enable tuning by PLL
     cmu_hfrco_calib((DEVINFO->HFRCOCAL16) | CMU_HFRCOCTRL_FINETUNINGEN);
 
     // Setup the PLL
@@ -712,7 +712,7 @@ uint32_t board_millis(void)
   * @retval None
   */
 void assert_failed(char *file, uint32_t line)
-{ 
+{
   /* USER CODE BEGIN 6 */
   /* User can add his own implementation to report the file name and line number,
      tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk
index 78d7f6a66..15fa0ff20 100644
--- a/hw/bsp/spresense/board.mk
+++ b/hw/bsp/spresense/board.mk
@@ -38,6 +38,8 @@ CFLAGS += \
 # lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration
 CFLAGS += -Wno-error=shadow  -Wno-error=redundant-decls
 
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
 SPRESENSE_SDK = $(TOP)/hw/mcu/sony/cxd56/spresense-exported-sdk
 
 SRC_C += src/portable/sony/cxd56/dcd_cxd56.c
diff --git a/hw/bsp/spresense/board_spresense.c b/hw/bsp/spresense/board_spresense.c
index 256bccd15..8cd04a49d 100644
--- a/hw/bsp/spresense/board_spresense.c
+++ b/hw/bsp/spresense/board_spresense.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright 2019 Sony Semiconductor Solutions Corporation
@@ -29,7 +29,7 @@
 #include <arch/board/board.h>
 #include <arch/chip/pin.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
@@ -64,7 +64,7 @@ void board_led_write(bool state)
 // a '1' means active (pressed), a '0' means inactive.
 uint32_t board_button_read(void)
 {
-  if (board_gpio_read(BUTTON_PIN)) 
+  if (board_gpio_read(BUTTON_PIN))
   {
     return 0;
   }
@@ -96,7 +96,7 @@ uint32_t board_millis(void)
     /* Wait until RTC is available */
     while (g_rtc_enabled == false);
 
-    if (clock_gettime(CLOCK_MONOTONIC, &tp)) 
+    if (clock_gettime(CLOCK_MONOTONIC, &tp))
     {
         return 0;
     }
diff --git a/hw/bsp/stm32c0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32c0/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..4996b06cf
--- /dev/null
+++ b/hw/bsp/stm32c0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32c0xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        0
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 200 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTx_FLASH.ld b/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTx_FLASH.ld
new file mode 100644
index 000000000..8acd49f9d
--- /dev/null
+++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTx_FLASH.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for NUCLEO-C071RB Board embedding STM32C071RBTx Device from stm32c0 series
+**                      128KBytes FLASH
+**                      24KBytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 24K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 128K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab :
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM :
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake
new file mode 100644
index 000000000..2a319a73c
--- /dev/null
+++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32c071xx)
+set(JLINK_DEVICE stm32c071rb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32C071RBTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32C071xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h
new file mode 100644
index 000000000..c7d809717
--- /dev/null
+++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h
@@ -0,0 +1,63 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2023, HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32C071 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-g071rb.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+// Green LED
+#define GREEN_LED_PORT         GPIOA
+#define GREEN_LED_PIN          GPIO_PIN_5
+#define GREEN_LED_STATE_ON     1
+
+// Blue LED
+#define BLUE_LED_PORT          GPIOC
+#define BLUE_LED_PIN           GPIO_PIN_9
+#define BLUE_LED_STATE_ON      0
+
+// Generic LED
+#define LED_PORT GREEN_LED_PORT
+#define LED_PIN GREEN_LED_PIN
+#define LED_STATE_ON GREEN_LED_STATE_ON
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   0
+
+// Enable UART serial communication with the ST-Link
+#define UART_DEV              USART2
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF1_USART2
+#define UART_TX_PIN           GPIO_PIN_2
+#define UART_RX_PIN           GPIO_PIN_3
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk
new file mode 100644
index 000000000..67a9b59a8
--- /dev/null
+++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk
@@ -0,0 +1,13 @@
+CFLAGS += \
+	-DSTM32C071xx
+
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32c071xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32C071RBTx_FLASH.ld
+
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32c071xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32c071xx_flash.icf
+
+# For flash-jlink target
+JLINK_DEVICE = stm32c071rb
diff --git a/hw/bsp/stm32c0/family.c b/hw/bsp/stm32c0/family.c
new file mode 100644
index 000000000..ace3f2a71
--- /dev/null
+++ b/hw/bsp/stm32c0/family.c
@@ -0,0 +1,203 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
+#include "stm32c0xx_hal.h"
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_DRD_FS_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+// Startup code generated by STM32CubeIDE uses USB_IRQHandler, while
+// stm32c071xx.s from cmsis_device_c0 uses USB_DRD_FS_IRQHandler.
+void USB_IRQHandler(void) {
+  USB_DRD_FS_IRQHandler();
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+UART_HandleTypeDef UartHandle;
+
+void board_init(void) {
+  HAL_Init();
+
+  // Enable the HSIUSB48 48 MHz oscillator.
+  RCC->CR |= RCC_CR_HSIUSB48ON;
+
+  // Wait for HSIUSB48 to be ready.
+  while (!(RCC->CR & RCC_CR_HSIUSB48RDY)) { }
+
+  // Change the SYSCLK source to HSIUSB48.
+  RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_SYSCLKSOURCE_HSIUSB48;
+
+  // Wait for the SYSCLK source to change.
+  while ((RCC->CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_Pos != RCC_SYSCLKSOURCE_HSIUSB48) { }
+
+  // Disable HSI48 to save power.
+  RCC->CR &= ~RCC_CR_HSION;
+
+  // Enable peripheral clocks.
+  RCC->APBENR1 = RCC_APBENR1_USBEN | RCC_APBENR1_CRSEN | RCC_APBENR1_USART2EN;
+  RCC->APBENR2 = RCC_APBENR2_USART1EN;
+
+  // Enable all GPIO clocks.
+  RCC->IOPENR = 0x2F;
+
+  // Turn on CRS to make the HSIUSB48 clock more precise when USB is connected.
+  CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_DRD_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  // LED
+  {
+    GPIO_InitTypeDef gpio_init = { 0 };
+    gpio_init.Pin = LED_PIN;
+    gpio_init.Mode = GPIO_MODE_OUTPUT_PP;
+    HAL_GPIO_Init(LED_PORT, &gpio_init);
+    board_led_write(false);
+  }
+
+  // Button
+  {
+    GPIO_InitTypeDef gpio_init = { 0 };
+    gpio_init.Pin = BUTTON_PIN;
+    gpio_init.Mode = GPIO_MODE_INPUT;
+    gpio_init.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+    HAL_GPIO_Init(BUTTON_PORT, &gpio_init);
+  }
+
+#ifdef UART_DEV
+  // UART
+  {
+    GPIO_InitTypeDef gpio_init = { 0 };
+    gpio_init.Pin = UART_TX_PIN | UART_RX_PIN;
+    gpio_init.Mode = GPIO_MODE_AF_PP;
+    gpio_init.Pull = GPIO_PULLUP;
+    gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+    gpio_init.Alternate = UART_GPIO_AF;
+    HAL_GPIO_Init(UART_GPIO_PORT, &gpio_init);
+  }
+
+  UartHandle = (UART_HandleTypeDef){
+    .Instance = UART_DEV,
+    .Init.BaudRate = CFG_BOARD_UART_BAUDRATE,
+    .Init.WordLength = UART_WORDLENGTH_8B,
+    .Init.StopBits = UART_STOPBITS_1,
+    .Init.Parity = UART_PARITY_NONE,
+    .Init.HwFlowCtl = UART_HWCONTROL_NONE,
+    .Init.Mode = UART_MODE_TX_RX,
+    .Init.OverSampling = UART_OVERSAMPLING_16,
+    .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT
+  };
+  HAL_UART_Init(&UartHandle);
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  return len;
+#else
+  (void) buf;
+  (void) len;
+  (void) UartHandle;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+  HAL_IncTick();
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+
+}
diff --git a/hw/bsp/stm32c0/family.cmake b/hw/bsp/stm32c0/family.cmake
new file mode 100644
index 000000000..c6a90fff6
--- /dev/null
+++ b/hw/bsp/stm32c0/family.cmake
@@ -0,0 +1,119 @@
+include_guard()
+
+set(ST_FAMILY c0)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32C0 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f interface/stlink.cfg -f target/stm32c0x.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32C0)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  family_flash_stlink(${TARGET})
+  #family_flash_openocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32c0/family.mk b/hw/bsp/stm32c0/family.mk
new file mode 100644
index 000000000..9ff3a2fdf
--- /dev/null
+++ b/hw/bsp/stm32c0/family.mk
@@ -0,0 +1,53 @@
+ST_FAMILY = c0
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32C0 \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
+
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+
+# suppress warning caused by vendor mcu driver
+CFLAGS_GCC += -Wno-error=cast-align -Wno-error=unused-parameter
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
+
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32c0/stm32c0xx_hal_conf.h b/hw/bsp/stm32c0/stm32c0xx_hal_conf.h
new file mode 100644
index 000000000..678b6ee0d
--- /dev/null
+++ b/hw/bsp/stm32c0/stm32c0xx_hal_conf.h
@@ -0,0 +1,284 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32c0xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32c0xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_CONF_H
+#define STM32C0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_I2C_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+  * @brief Set below the peripheral configuration  to "1U" to add the support
+  *        of HAL callback registration/unregistration feature for the HAL
+  *        driver(s). This allows user application to provide specific callback
+  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+  *        the default weak callback functions (see each stm32c0xx_hal_ppp.h file
+  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+  *        for each PPP peripheral).
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS         0U  /* ADC register callback disabled      */
+#define USE_HAL_I2C_REGISTER_CALLBACKS         0U  /* I2C register callback disabled      */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS        0U  /* IRDA register callback disabled     */
+#define USE_HAL_I2S_REGISTER_CALLBACKS         0U  /* I2S register callback disabled      */
+#define USE_HAL_IWDG_REGISTER_CALLBACKS        0U  /* IWDG register callback disabled     */
+#define USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    (8000000U)         /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    (100UL)         /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    (48000000UL)            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  (32000UL)                /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+#if !defined  (LSI_STARTUP_TIME)
+#define LSI_STARTUP_TIME    130UL      /*!< Time out for LSI start up, in ms */
+#endif /* LSI_STARTUP_TIME */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    (32768UL)               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    (5000UL)      /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S1 peripheral
+  *        This value is used by the RCC HAL module to compute the I2S1 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_I2S1_CLOCK_VALUE)
+#define EXTERNAL_I2S1_CLOCK_VALUE    (12288000UL) /*!< Value of the I2S1 External clock source in Hz*/
+#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    (3300UL)                                        /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            3U /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              0U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include modules header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32c0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32c0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32c0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32c0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32c0xx_hal_adc.h"
+  #include "stm32c0xx_hal_adc_ex.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32c0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32c0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32c0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32c0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32c0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32c0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32c0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32c0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32c0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32c0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32c0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32c0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32c0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32c0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32c0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32c0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32c0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32c0xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for functions parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..999dbfe9e
--- /dev/null
+++ b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f0xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        0
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 200 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.cmake b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.cmake
new file mode 100644
index 000000000..61fec0d30
--- /dev/null
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32f070xb)
+set(JLINK_DEVICE stm32f070rb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32F070rbtx_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F070xB
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h
index 7c527e2c2..82ad309a3 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F070 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-f070rb.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
index 7c0ee40b6..63f6a31c2 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
@@ -1,8 +1,9 @@
+MCU_VARIANT = stm32f070xb
+
 CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY
 
-LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/stm32F070rbtx_flash.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f070rb
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
index 59e18f375..6bb9d33cb 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
@@ -102,12 +102,12 @@ SECTIONS
     . = ALIGN(4);
   } >FLASH
 
-  .ARM.extab   : { 
+  .ARM.extab   : {
   	. = ALIGN(4);
   	*(.ARM.extab* .gnu.linkonce.armextab.*)
   	. = ALIGN(4);
   } >FLASH
-  
+
   .ARM : {
     . = ALIGN(4);
     __exidx_start = .;
@@ -124,7 +124,7 @@ SECTIONS
     PROVIDE_HIDDEN (__preinit_array_end = .);
     . = ALIGN(4);
   } >FLASH
-  
+
   .init_array :
   {
     . = ALIGN(4);
@@ -134,7 +134,7 @@ SECTIONS
     PROVIDE_HIDDEN (__init_array_end = .);
     . = ALIGN(4);
   } >FLASH
-  
+
   .fini_array :
   {
     . = ALIGN(4);
@@ -149,7 +149,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections into "RAM" Ram type memory */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -158,14 +158,14 @@ SECTIONS
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
-    
+
   } >RAM AT> FLASH
-  
+
   /* Uninitialized data section into "RAM" Ram type memory */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
index 8d31f6a00..8715e0723 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.cmake b/hw/bsp/stm32f0/boards/stm32f072disco/board.cmake
new file mode 100644
index 000000000..287593f43
--- /dev/null
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32f072xb)
+set(JLINK_DEVICE stm32f072rb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F072RBTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F072xB
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.h b/hw/bsp/stm32f0/boards/stm32f072disco/board.h
index 0b1824b8e..3ca1b3641 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.h
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F072 Discovery
+   url: https://www.st.com/en/evaluation-tools/32f072bdiscovery.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
index 7c72d8f4c..57c658629 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
@@ -1,8 +1,9 @@
+MCU_VARIANT = stm32f072xb
+
 CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY
 
-LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f072rb
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/STM32F072VBTx_FLASH.ld b/hw/bsp/stm32f0/boards/stm32f072eval/STM32F072VBTx_FLASH.ld
index 581613a5f..0eaf15186 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/STM32F072VBTx_FLASH.ld
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/STM32F072VBTx_FLASH.ld
@@ -27,12 +27,6 @@
 /* Entry Point */
 ENTRY(Reset_Handler)
 
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
-
-_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
-_Min_Stack_Size = 0x400 ;	/* required amount of stack */
-
 /* Memories definition */
 MEMORY
 {
@@ -40,6 +34,12 @@ MEMORY
   FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 128K
 }
 
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
 /* Sections */
 SECTIONS
 {
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.cmake b/hw/bsp/stm32f0/boards/stm32f072eval/board.cmake
new file mode 100644
index 000000000..42d778cb5
--- /dev/null
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT stm32f072xb)
+set(JLINK_DEVICE stm32f072vb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F072VBTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F072xB
+    LSI_VALUE=40000
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.h b/hw/bsp/stm32f0/boards/stm32f072eval/board.h
index 8869d5dc9..2828000b9 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.h
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F072 Eval
+   url: https://www.st.com/en/evaluation-tools/stm32072b-eval.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
index b625c3ebd..bab889524 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
@@ -1,8 +1,9 @@
+MCU_VARIANT = stm32f072xb
+
 CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY
 
-LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f072vb
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index 8de3147e2..ea1373e6c 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,15 +24,18 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32f0xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -41,8 +44,7 @@ void USB_IRQHandler(void)
 //--------------------------------------------------------------------+
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
   board_stm32f0_clock_init();
 
   // Enable All GPIOs clocks
@@ -68,7 +70,7 @@ void board_init(void)
 #endif
 
   // LED
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_PULLUP;
@@ -83,20 +85,20 @@ void board_init(void)
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
   // Uart
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
-  UartHandle.Instance        = UART_DEV;
-  UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
+  UartHandle.Instance = UART_DEV;
+  UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
   UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits   = UART_STOPBITS_1;
-  UartHandle.Init.Parity     = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode       = UART_MODE_TX_RX;
+  UartHandle.Init.StopBits = UART_STOPBITS_1;
+  UartHandle.Init.Parity = UART_PARITY_NONE;
+  UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  UartHandle.Init.Mode = UART_MODE_TX_RX;
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   HAL_UART_Init(&UartHandle);
 
@@ -116,55 +118,60 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
 
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+  HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
+  buf, len, 0xffff);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 #ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
+void assert_failed(const char* file, uint32_t line)
 {
   (void) file; (void) line;
   /* USER CODE BEGIN 6 */
@@ -176,7 +183,5 @@ void assert_failed(uint8_t* file, uint32_t line)
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake
new file mode 100644
index 000000000..12c7b592c
--- /dev/null
+++ b/hw/bsp/stm32f0/family.cmake
@@ -0,0 +1,115 @@
+include_guard()
+
+set(ST_FAMILY f0)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F0 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  #target_compile_options(${BOARD_TARGET} PUBLIC)
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_READONLY
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F0)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 39831e154..431709de0 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -6,19 +6,29 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0 \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F0
 
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=cast-align
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# ------------------------
+# All source paths should be relative to the top level.
+# ------------------------
 
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
@@ -28,7 +38,9 @@ SRC_C += \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
@@ -36,5 +48,9 @@ INC += \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
index cfa66b366..b205464f3 100644
--- a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
+++ b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F0xx_HAL_CONF_H
@@ -30,9 +30,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 /*#define HAL_ADC_MODULE_ENABLED   */
 /*#define HAL_CAN_MODULE_ENABLED   */
 /*#define HAL_CEC_MODULE_ENABLED   */
@@ -65,15 +65,15 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE            8000000U  /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 /**
-  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+  *        Timeout value
   */
 #if !defined  (HSE_STARTUP_TIMEOUT)
   #define HSE_STARTUP_TIMEOUT  100U      /*!< Time out for HSE start up, in ms */
@@ -82,24 +82,24 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE            8000000U  /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
-  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+  *        Timeout value
   */
-#if !defined  (HSI_STARTUP_TIMEOUT) 
+#if !defined  (HSI_STARTUP_TIMEOUT)
   #define HSI_STARTUP_TIMEOUT  5000U     /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */  
+#endif /* HSI_STARTUP_TIMEOUT */
 
 /**
   * @brief Internal High Speed oscillator for ADC (HSI14) value.
   */
-#if !defined  (HSI14_VALUE) 
+#if !defined  (HSI14_VALUE)
   #define HSI14_VALUE          14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -108,7 +108,7 @@
 /**
   * @brief Internal High Speed oscillator for USB (HSI48) value.
   */
-#if !defined  (HSI48_VALUE) 
+#if !defined  (HSI48_VALUE)
   #define HSI48_VALUE          48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -117,8 +117,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
-  #define LSI_VALUE            32000U    
+#if !defined  (LSI_VALUE)
+  #define LSI_VALUE            32000U
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -127,7 +127,7 @@
   */
 #if !defined  (LSE_VALUE)
   #define LSE_VALUE            32768U    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */     
+#endif /* LSE_VALUE */
 
 /**
   * @brief Time out for LSE start up value in ms.
@@ -143,8 +143,8 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    3300U  /*!< Value of VDD in mv */           
+  */
+#define  VDD_VALUE                    3300U  /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default)             */
                                                                               /*  Warning: Must be set to higher priority for HAL_Delay()  */
                                                                               /*  and HAL_GetTick() usage under interrupt context          */
@@ -175,14 +175,14 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
- #define USE_FULL_ASSERT   1 
+ #define USE_FULL_ASSERT   1
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -299,17 +299,17 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed(__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+  void assert_failed(const char* file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */    
-    
+#endif /* USE_FULL_ASSERT */
+
 #ifdef __cplusplus
 }
 #endif
@@ -318,4 +318,3 @@
 
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..c08a590a7
--- /dev/null
+++ b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f1xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        0
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
index ca1804905..95836522e 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake
new file mode 100644
index 000000000..87b8458a2
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT stm32f103xb)
+set(JLINK_DEVICE stm32f103c8)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F103X8_FLASH.ld)
+set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32f103x8_flash.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F103xB
+    HSE_VALUE=8000000U
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
index 57a607ed5..c8a74337f 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F103 Bluepill
+   url: https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -42,12 +47,12 @@
 #define BUTTON_STATE_ACTIVE   1
 
 // UART
-//#define UART_DEV              USART1
-//#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-//#define UART_GPIO_PORT        GPIOA
+#define UART_DEV              USART1
+#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
 //#define UART_GPIO_AF          GPIO_AF1_USART1
-//#define UART_TX_PIN           GPIO_PIN_9
-//#define UART_RX_PIN           GPIO_PIN_10
+#define UART_TX_PIN           GPIO_PIN_9
+#define UART_RX_PIN           GPIO_PIN_10
 
 //--------------------------------------------------------------------+
 // RCC Clock
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
index db64b3a3f..6c5f34501 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
@@ -1,8 +1,10 @@
+MCU_VARIANT = stm32f103xb
+
 CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U -DCFG_EXAMPLE_VIDEO_READONLY
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F103X8_FLASH.ld
+LD_FILE_IAR = $(BOARD_PATH)/stm32f103x8_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f103c8
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf b/hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf
new file mode 100644
index 000000000..07601c2e8
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20004FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
index da40d1eb2..524ac7c03 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake
new file mode 100644
index 000000000..67a96c4d1
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT stm32f103xb)
+set(JLINK_DEVICE stm32f103rc)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F103XC_FLASH.ld)
+set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32f103xc_flash.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F103xB
+    HSE_VALUE=8000000U
+    )
+endfunction()
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
index bedce7f14..d4824686f 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F103 Mini v2
+   url: https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
index eeda87080..7e95c1fe1 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
@@ -1,8 +1,10 @@
+MCU_VARIANT = stm32f103xb
+
 CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F103XC_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F103XC_FLASH.ld
+LD_FILE_IAR = $(BOARD_PATH)/stm32f103xc_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f103rc
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/stm32f103xc_flash.icf b/hw/bsp/stm32f1/boards/stm32f103_mini_2/stm32f103xc_flash.icf
new file mode 100644
index 000000000..5f8a5ecad
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/stm32f103xc_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.cmake b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.cmake
new file mode 100644
index 000000000..7672ff338
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT stm32f103xe)
+set(JLINK_DEVICE stm32f103ze)
+#set(JLINK_OPTION "-USB 320000338")
+
+string(TOUPPER ${MCU_VARIANT} MCU_VARIANT_UPPER)
+
+set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT_UPPER}_FLASH.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F103xE
+    HSE_VALUE=8000000U
+    )
+endfunction()
diff --git a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h
new file mode 100644
index 000000000..1253c5a48
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h
@@ -0,0 +1,102 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: IAR STM32 F103ze starter kit
+   url: n/a
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOF
+#define LED_PIN               GPIO_PIN_6
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOG
+#define BUTTON_PIN            GPIO_PIN_8
+#define BUTTON_STATE_ACTIVE   0
+
+// USB Connect
+#define USB_CONNECT_PORT      GPIOG
+#define USB_CONNECT_PIN       GPIO_PIN_11
+#define USB_CONNECT_STATE     0
+
+// UART
+//#define UART_DEV              USART1
+//#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
+//#define UART_GPIO_PORT        GPIOA
+//#define UART_GPIO_AF          GPIO_AF1_USART1
+//#define UART_TX_PIN           GPIO_PIN_9
+//#define UART_RX_PIN           GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32f1_clock_init(void)
+{
+  RCC_ClkInitTypeDef clkinitstruct = {0};
+  RCC_OscInitTypeDef oscinitstruct = {0};
+  RCC_PeriphCLKInitTypeDef rccperiphclkinit = {0};
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  oscinitstruct.OscillatorType  = RCC_OSCILLATORTYPE_HSE;
+  oscinitstruct.HSEState        = RCC_HSE_ON;
+  oscinitstruct.HSEPredivValue  = RCC_HSE_PREDIV_DIV1;
+  oscinitstruct.PLL.PLLMUL      = RCC_PLL_MUL9;
+  oscinitstruct.PLL.PLLState    = RCC_PLL_ON;
+  oscinitstruct.PLL.PLLSource   = RCC_PLLSOURCE_HSE;
+  HAL_RCC_OscConfig(&oscinitstruct);
+
+  /* USB clock selection */
+  rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  rccperiphclkinit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+  HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  clkinitstruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  clkinitstruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  clkinitstruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  clkinitstruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  clkinitstruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&clkinitstruct, FLASH_LATENCY_2);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.mk b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.mk
new file mode 100644
index 000000000..5b17d8036
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.mk
@@ -0,0 +1,13 @@
+MCU_VARIANT = stm32f103xe
+
+CFLAGS += -DSTM32F103xE -DHSE_VALUE=8000000U
+
+# Linker
+LD_FILE_GCC = ${ST_CMSIS}/Source/Templates/gcc/linker/STM32F103XE_FLASH.ld
+LD_FILE_IAR = ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f103ze
+
+# flash target ROM bootloader
+flash: flash-jlink
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 8fcf9ebd6..29785397f 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,43 +24,57 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32f1xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_HP_IRQHandler(void)
-{
+void USB_HP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB_LP_IRQHandler(void)
-{
+void USB_LP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USBWakeUp_IRQHandler(void)
-{
+void USBWakeUp_IRQHandler(void) {
   tud_int_handler(0);
 }
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
+UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
   board_stm32f1_clock_init();
-  
+
   // Enable All GPIOs clocks
   __HAL_RCC_GPIOA_CLK_ENABLE();
   __HAL_RCC_GPIOB_CLK_ENABLE();
   __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#ifdef __HAL_RCC_GPIOE_CLK_ENABLE
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+#endif
+
+#ifdef __HAL_RCC_GPIOF_CLK_ENABLE
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+#endif
+
+#ifdef __HAL_RCC_GPIOG_CLK_ENABLE
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+#endif
+
+
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
@@ -70,9 +84,9 @@ void board_init(void)
   NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
-  
+
   // LED
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = LED_STATE_ON ? GPIO_PULLDOWN : GPIO_PULLUP;
@@ -86,10 +100,42 @@ void board_init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
+#ifdef UART_DEV
+  // UART
+  UART_CLK_EN();
+
+  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  //GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle = (UART_HandleTypeDef) {
+      .Instance        = UART_DEV,
+      .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+      .Init.WordLength = UART_WORDLENGTH_8B,
+      .Init.StopBits   = UART_STOPBITS_1,
+      .Init.Parity     = UART_PARITY_NONE,
+      .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+      .Init.Mode       = UART_MODE_TX_RX,
+      .Init.OverSampling = UART_OVERSAMPLING_16
+  };
+  HAL_UART_Init(&UartHandle);
+#endif
+
+#ifdef USB_CONNECT_PIN
+  GPIO_InitStruct.Pin = USB_CONNECT_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(USB_CONNECT_PORT, &GPIO_InitStruct);
+#endif
+
   // USB Pins
   // Configure USB DM and DP pins.
   GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
@@ -98,60 +144,76 @@ void board_init(void)
   __HAL_RCC_USB_CLK_ENABLE();
 }
 
+#ifdef USB_CONNECT_PIN
+void dcd_disconnect(uint8_t rhport) {
+  (void)rhport;
+  HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, 1-USB_CONNECT_STATE);
+}
+
+void dcd_connect(uint8_t rhport) {
+  (void)rhport;
+  HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, USB_CONNECT_STATE);
+}
+#endif
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
+int board_uart_write(void const *buf, int len) {
+  HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff);
+  return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 #ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(char *file, uint32_t line)
-{ 
+void assert_failed(const char *file, uint32_t line)
+{
   /* USER CODE BEGIN 6 */
   /* User can add his own implementation to report the file name and line number,
      tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
@@ -161,7 +223,5 @@ void assert_failed(char *file, uint32_t line)
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake
new file mode 100644
index 000000000..cbb9c3568
--- /dev/null
+++ b/hw/bsp/stm32f1/family.cmake
@@ -0,0 +1,114 @@
+include_guard()
+
+set(ST_FAMILY f1)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F1 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+# Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if (NOT DEFINED LD_FILE_IAR)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  #target_compile_options(${BOARD_TARGET} PUBLIC)
+  #target_compile_definitions(${BOARD_TARGET} PUBLIC)
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F1)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index 3fb2e6e70..364616304 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -1,45 +1,51 @@
 ST_FAMILY = f1
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_${ST_FAMILY} hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver
 
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+ST_CMSIS = hw/mcu/st/cmsis_device_${ST_FAMILY}
+ST_HAL_DRIVER = hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver
 
-include $(TOP)/$(BOARD_PATH)/board.mk
+include ${TOP}/${BOARD_PATH}/board.mk
+CPU_CORE ?= cortex-m3
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F1
 
-# mcu driver cause following warnings
-#CFLAGS += -Wno-error=unused-parameter
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
 
+# mcu driver cause following warnings
+CFLAGS_GCC += -Wno-error=cast-align
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  -specs=nosys.specs -specs=nano.specs
+
+# ------------------------
 # All source paths should be relative to the top level.
+# ------------------------
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
+  ${ST_CMSIS}/Source/Templates/system_stm32${ST_FAMILY}xx.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_cortex.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_rcc.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_rcc_ex.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_gpio.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_uart.c
 
 INC += \
-  $(TOP)/$(BOARD_PATH) \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc
+  ${TOP}/${BOARD_PATH} \
+  ${TOP}/lib/CMSIS_5/CMSIS/Core/Include \
+  ${TOP}/${ST_CMSIS}/Include \
+  ${TOP}/${ST_HAL_DRIVER}/Inc
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+# Startup
+SRC_S_GCC += ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s
+SRC_S_IAR += ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s
 
-# For flash-jlink target
-JLINK_DEVICE = stm32f103c8
-
-# flash target ROM bootloader
-flash-dfu-util: $(BUILD)/$(PROJECT).bin
-	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
+# flash target ROM bootloader: flash-dfu-util
+DFU_UTIL_OPTION = -a 0 --dfuse-address 0x08000000
diff --git a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
index a4a3f3086..0fce774e1 100644
--- a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
+++ b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
@@ -32,13 +32,13 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
 #define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED */
 /* #define HAL_CAN_MODULE_ENABLED */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_CRC_MODULE_ENABLED */
 /* #define HAL_DAC_MODULE_ENABLED */
 #define HAL_DMA_MODULE_ENABLED
@@ -69,9 +69,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
 #if defined(USE_STM3210C_EVAL)
   #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
 #else
@@ -86,7 +86,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE              8000000U  /*!< Value of the Internal oscillator in Hz */
@@ -95,7 +95,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */
 #endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
                                                 The real value may vary depending on the variations
@@ -119,7 +119,7 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY            0x00U /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
@@ -151,7 +151,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -168,7 +168,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    8U                  /* 8 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -176,9 +176,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -190,7 +190,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -205,13 +205,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -233,7 +233,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -243,7 +243,7 @@
 #ifdef HAL_GPIO_MODULE_ENABLED
  #include "stm32f1xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
-   
+
 #ifdef HAL_EXTI_MODULE_ENABLED
   #include "stm32f1xx_hal_exti.h"
 #endif /* HAL_EXTI_MODULE_ENABLED */
@@ -251,7 +251,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f1xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CAN_MODULE_ENABLED
  #include "stm32f1xx_hal_can.h"
 #endif /* HAL_CAN_MODULE_ENABLED */
@@ -310,15 +310,15 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
  #include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+#endif /* HAL_PCCARD_MODULE_ENABLED */
 
 #ifdef HAL_SD_MODULE_ENABLED
  #include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */  
+#endif /* HAL_SD_MODULE_ENABLED */
 
 #ifdef HAL_SDRAM_MODULE_ENABLED
  #include "stm32f1xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */     
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_SPI_MODULE_ENABLED
  #include "stm32f1xx_hal_spi.h"
@@ -358,17 +358,17 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr: If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed(__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+  void assert_failed(const char* file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */    
-    
+#endif /* USE_FULL_ASSERT */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32f2/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f2/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..edbdba4b5
--- /dev/null
+++ b/hw/bsp/stm32f2/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f2xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        0
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld b/hw/bsp/stm32f2/boards/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
similarity index 99%
rename from hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
rename to hw/bsp/stm32f2/boards/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
index 29e387f28..3fce1b578 100644
--- a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.cmake b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.cmake
new file mode 100644
index 000000000..8f78e6295
--- /dev/null
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f207xx)
+set(JLINK_DEVICE stm32f207zg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F207ZGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F207xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h
new file mode 100644
index 000000000..8d8c52f60
--- /dev/null
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h
@@ -0,0 +1,63 @@
+
+/* metadata:
+   name: STM32 F207 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-f207zg.html
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_14
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (HSE)
+  *            SYSCLK(Hz)                     = 120000000
+  *            HCLK(Hz)                       = 120000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 4
+  *            APB2 Prescaler                 = 2
+  *            HSE Frequency(Hz)              = 8000000
+  *            PLL_M                          = HSE_VALUE/1000000
+  *            PLL_N                          = 240
+  *            PLL_P                          = 2
+  *            PLL_Q                          = 5
+  *            VDD(V)                         = 3.3
+  *            Flash Latency(WS)              = 3
+  * @param  None
+  * @retval None
+  */
+static inline void SystemClock_Config(void) {
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000;
+  RCC_OscInitStruct.PLL.PLLN = 240;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 5;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+     clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
+}
+
+#endif
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
new file mode 100644
index 000000000..ba185d199
--- /dev/null
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+  -DSTM32F207xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32F207ZGTx_FLASH.ld
+
+SRC_S += \
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f207zg
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c b/hw/bsp/stm32f2/family.c
similarity index 57%
rename from hw/bsp/stm32f207nucleo/stm32f207nucleo.c
rename to hw/bsp/stm32f2/family.c
index 619c90d68..c1333382a 100644
--- a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
+++ b/hw/bsp/stm32f2/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,15 +24,18 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
 
 #include "stm32f2xx_hal.h"
+#include "bsp/board_api.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
+void OTG_FS_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -40,81 +43,24 @@ void OTG_FS_IRQHandler(void)
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-
 // enable all LED, Button, Uart, USB clock
-static void all_rcc_clk_enable(void)
-{
+static void all_rcc_clk_enable(void) {
   __HAL_RCC_GPIOA_CLK_ENABLE();  // USB D+, D-
   __HAL_RCC_GPIOB_CLK_ENABLE();  // LED
   __HAL_RCC_GPIOC_CLK_ENABLE();  // Button
 }
 
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (HSE)
-  *            SYSCLK(Hz)                     = 120000000
-  *            HCLK(Hz)                       = 120000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 4
-  *            APB2 Prescaler                 = 2
-  *            HSE Frequency(Hz)              = 8000000
-  *            PLL_M                          = HSE_VALUE/1000000
-  *            PLL_N                          = 240
-  *            PLL_P                          = 2
-  *            PLL_Q                          = 5
-  *            VDD(V)                         = 3.3
-  *            Flash Latency(WS)              = 3
-  * @param  None
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 240;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 5;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
-}
-
-void board_init(void)
-{
+void board_init(void) {
   SystemClock_Config();
-  
-  #if CFG_TUSB_OS  == OPT_OS_NONE
+
+  #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
   #endif
 
-
   all_rcc_clk_enable();
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
 
   // LED
   GPIO_InitStruct.Pin = LED_PIN;
@@ -165,49 +111,45 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32f2/family.cmake b/hw/bsp/stm32f2/family.cmake
new file mode 100644
index 000000000..dc6bc2885
--- /dev/null
+++ b/hw/bsp/stm32f2/family.cmake
@@ -0,0 +1,116 @@
+include_guard()
+
+set(ST_FAMILY f2)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F2 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if (NOT DEFINED LD_FILE_IAR)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  #target_compile_options(${BOARD_TARGET} PUBLIC)
+  #target_compile_definitions(${BOARD_TARGET} PUBLIC)
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F2)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f2/family.mk
similarity index 53%
rename from hw/bsp/stm32f207nucleo/board.mk
rename to hw/bsp/stm32f2/family.mk
index fa7d28399..7af9a76a0 100644
--- a/hw/bsp/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f2/family.mk
@@ -1,27 +1,33 @@
 ST_FAMILY = f2
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
+DEPS_SUBMODULES += \
+	lib/CMSIS_5 \
+	$(ST_CMSIS) \
+	$(ST_HAL_DRIVER)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
+
 CFLAGS += \
+	-DCFG_TUSB_MCU=OPT_MCU_STM32F2
+
+CFLAGS_GCC += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
-  -DSTM32F207xx \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F2
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=sign-compare
+CFLAGS_GCC += -Wno-error=sign-compare
 
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32F207ZGTx_FLASH.ld
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
 
 SRC_C += \
   src/portable/synopsys/dwc2/dcd_dwc2.c \
+  src/portable/synopsys/dwc2/hcd_dwc2.c \
+  src/portable/synopsys/dwc2/dwc2_common.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -29,20 +35,8 @@ SRC_C += \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
-
 INC += \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f207zg
-
-# flash target using on-board stlink
-flash: flash-stlink
+  $(TOP)/$(BOARD_PATH)
diff --git a/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h b/hw/bsp/stm32f2/stm32f2xx_hal_conf.h
similarity index 96%
rename from hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
rename to hw/bsp/stm32f2/stm32f2xx_hal_conf.h
index 2ab46b260..b38a9d951 100644
--- a/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
+++ b/hw/bsp/stm32f2/stm32f2xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_CONF_H
@@ -30,9 +30,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED   */
 /* #define HAL_CAN_MODULE_ENABLED   */
 /* #define HAL_CRC_MODULE_ENABLED   */
@@ -42,7 +42,7 @@
 /* #define HAL_DMA_MODULE_ENABLED */
 /* #define HAL_ETH_MODULE_ENABLED */
 #define HAL_EXTI_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED */
 /* #define HAL_NOR_MODULE_ENABLED */
 /* #define HAL_PCCARD_MODULE_ENABLED */
@@ -52,8 +52,8 @@
 /* #define HAL_I2C_MODULE_ENABLED */
 /* #define HAL_I2S_MODULE_ENABLED    */
 /* #define HAL_IWDG_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED   
-#define HAL_RCC_MODULE_ENABLED 
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED    */
 /* #define HAL_RTC_MODULE_ENABLED */
 /* #define HAL_SD_MODULE_ENABLED   */
@@ -65,7 +65,7 @@
 /* #define HAL_SMARTCARD_MODULE_ENABLED  */
 /* #define HAL_WWDG_MODULE_ENABLED   */
 #define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED 
+#define HAL_PCD_MODULE_ENABLED
 /* #define HAL_HCD_MODULE_ENABLED */
 
 
@@ -73,9 +73,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE                     8000000U       /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -86,7 +86,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE                    16000000U       /*!< Value of the Internal oscillator in Hz*/
@@ -95,7 +95,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE                        32000U       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                                 /*!< Value of the Internal Low Speed oscillator in Hz
                                                             The real value may vary depending on the variations
@@ -113,8 +113,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE       12288000U        /*!< Value of the Internal oscillator in Hz*/
@@ -126,7 +126,7 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                      3300U /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY              0x0FU /*!< tick interrupt priority */
 #define  USE_RTOS                          0U
@@ -163,7 +163,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -180,7 +180,7 @@
 #define MAC_ADDR4                         0U
 #define MAC_ADDR5                         0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                       5U       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -190,7 +190,7 @@
 
 /* LAN8742A PHY Address*/
 #define LAN8742A_PHY_ADDRESS            0x00U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -202,7 +202,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -217,7 +217,7 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
@@ -228,7 +228,7 @@
 
 #define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
 #define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
- 
+
 /* ################## SPI peripheral configuration ########################## */
 
 /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
@@ -240,7 +240,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -258,7 +258,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f2xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f2xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -276,7 +276,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f2xx_hal_cryp.h" 
+  #include "stm32f2xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DAC_MODULE_ENABLED
@@ -294,7 +294,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f2xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f2xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -309,7 +309,7 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f2xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+#endif /* HAL_PCCARD_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f2xx_hal_hash.h"
@@ -378,14 +378,14 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f2xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr: If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
@@ -402,6 +402,6 @@
 #endif
 
 #endif /* __STM32F2xx_HAL_CONF_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f3/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f3/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..06b45856c
--- /dev/null
+++ b/hw/bsp/stm32f3/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f3xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        0
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld b/hw/bsp/stm32f3/boards/stm32f303disco/STM32F303VCTx_FLASH.ld
similarity index 98%
rename from hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
rename to hw/bsp/stm32f3/boards/stm32f303disco/STM32F303VCTx_FLASH.ld
index ca9046d29..981107af1 100644
--- a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/STM32F303VCTx_FLASH.ld
@@ -115,7 +115,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -128,11 +128,11 @@ SECTIONS
 
   _siccmram = LOADADDR(.ccmram);
 
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
   * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
+  * the startup code needs to be modified to copy the init-values.
   */
   .ccmram :
   {
@@ -140,17 +140,17 @@ SECTIONS
     _sccmram = .;       /* create a global symbol at ccmram start */
     *(.ccmram)
     *(.ccmram*)
-    
+
     . = ALIGN(4);
     _eccmram = .;       /* create a global symbol at ccmram end */
   } >CCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -173,7 +173,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.cmake b/hw/bsp/stm32f3/boards/stm32f303disco/board.cmake
new file mode 100644
index 000000000..7e02a7910
--- /dev/null
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f303xc)
+set(JLINK_DEVICE stm32f303vc)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F303VCTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F303xC
+    )
+endfunction()
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.h b/hw/bsp/stm32f3/boards/stm32f303disco/board.h
new file mode 100644
index 000000000..c79dea945
--- /dev/null
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.h
@@ -0,0 +1,67 @@
+
+/* metadata:
+   name: STM32 F303 Discovery
+   url: https://www.st.com/en/evaluation-tools/stm32f3discovery.html
+*/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PORT              GPIOE
+#define LED_PIN               GPIO_PIN_9
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   1
+
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (HSE)
+  *            SYSCLK(Hz)                     = 72000000
+  *            HCLK(Hz)                       = 72000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 2
+  *            APB2 Prescaler                 = 1
+  *            HSE Frequency(Hz)              = 8000000
+  *            HSE PREDIV                     = 1
+  *            PLLMUL                         = RCC_PLL_MUL9 (9)
+  *            Flash Latency(WS)              = 2
+  * @param  None
+  * @retval None
+  */
+static inline void SystemClock_Config(void) {
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Configures the USB clock */
+  HAL_RCCEx_GetPeriphCLKConfig(&RCC_PeriphClkInit);
+  RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+  clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  /* Enable Power Clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+}
+
+#endif
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.mk b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk
new file mode 100644
index 000000000..e387f2d54
--- /dev/null
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+  -DSTM32F303xC \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32F303VCTx_FLASH.ld
+
+SRC_S += \
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f303vc
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f303disco/stm32f303disco.c b/hw/bsp/stm32f3/family.c
similarity index 57%
rename from hw/bsp/stm32f303disco/stm32f303disco.c
rename to hw/bsp/stm32f3/family.c
index 33552bc07..84612d416 100644
--- a/hw/bsp/stm32f303disco/stm32f303disco.c
+++ b/hw/bsp/stm32f3/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,8 +24,13 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32f3xx_hal.h"
+#include "bsp/board_api.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -38,23 +43,20 @@
 // USB high-priority interrupt (Channel 74): Triggered only by a correct
 // transfer event for isochronous and double-buffer bulk transfer to reach
 // the highest possible transfer rate.
-void USB_HP_IRQHandler(void)
-{
+void USB_HP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
 // USB low-priority interrupt (Channel 75): Triggered by all USB events
 // (Correct transfer, USB reset, etc.). The firmware has to check the
 // interrupt source before serving the interrupt.
-void USB_LP_IRQHandler(void)
-{
+void USB_LP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
 // USB wakeup interrupt (Channel 76): Triggered by the wakeup event from the USB
 // Suspend mode.
-void USBWakeUp_RMP_IRQHandler(void)
-{
+void USBWakeUp_RMP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -62,69 +64,11 @@ void USBWakeUp_RMP_IRQHandler(void)
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define LED_PORT              GPIOE
-#define LED_PIN               GPIO_PIN_9
-#define LED_STATE_ON          1
 
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (HSE)
-  *            SYSCLK(Hz)                     = 72000000
-  *            HCLK(Hz)                       = 72000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 2
-  *            APB2 Prescaler                 = 1
-  *            HSE Frequency(Hz)              = 8000000
-  *            HSE PREDIV                     = 1
-  *            PLLMUL                         = RCC_PLL_MUL9 (9)
-  *            Flash Latency(WS)              = 2
-  * @param  None
-  * @retval None
-  */
-static void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef  RCC_PeriphClkInit;
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Configures the USB clock */
-  HAL_RCCEx_GetPeriphCLKConfig(&RCC_PeriphClkInit);
-  RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
-  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-  clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
-
-  /* Enable Power Clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-}
-
-void board_init(void)
-{
+void board_init(void) {
   SystemClock_Config();
 
-  #if CFG_TUSB_OS  == OPT_OS_NONE
+  #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
   #endif
@@ -135,7 +79,7 @@ void board_init(void)
 
   // LED
   __HAL_RCC_GPIOE_CLK_ENABLE();
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_PULLUP;
@@ -167,49 +111,60 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  asm("bkpt 0");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 
 }
diff --git a/hw/bsp/stm32f3/family.cmake b/hw/bsp/stm32f3/family.cmake
new file mode 100644
index 000000000..0ba2920d5
--- /dev/null
+++ b/hw/bsp/stm32f3/family.cmake
@@ -0,0 +1,112 @@
+include_guard()
+
+set(ST_FAMILY f3)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F3 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  #target_compile_options(${BOARD_TARGET} PUBLIC)
+  #target_compile_definitions(${BOARD_TARGET} PUBLIC)
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F3)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f303disco/board.mk b/hw/bsp/stm32f3/family.mk
similarity index 58%
rename from hw/bsp/stm32f303disco/board.mk
rename to hw/bsp/stm32f3/family.mk
index 9dd27a857..4fe3aa99d 100644
--- a/hw/bsp/stm32f303disco/board.mk
+++ b/hw/bsp/stm32f3/family.mk
@@ -1,25 +1,26 @@
 ST_FAMILY = f3
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
+DEPS_SUBMODULES += \
+	lib/CMSIS_5 \
+	$(ST_CMSIS) \
+	$(ST_HAL_DRIVER)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DSTM32F303xC \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F3
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
 
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32F303VCTx_FLASH.ld
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
 
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
@@ -30,20 +31,8 @@ SRC_C += \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
-
 INC += \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f303vc
-
-# flash target using on-board stlink
-flash: flash-stlink
+  $(TOP)/$(BOARD_PATH)
diff --git a/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h b/hw/bsp/stm32f3/stm32f3xx_hal_conf.h
similarity index 96%
rename from hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
rename to hw/bsp/stm32f3/stm32f3xx_hal_conf.h
index 0abcbb019..82d3765af 100644
--- a/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
+++ b/hw/bsp/stm32f3/stm32f3xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F3xx_HAL_CONF_H
@@ -30,9 +30,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED */
 /* #define HAL_CAN_MODULE_ENABLED */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED */
@@ -57,7 +57,7 @@
 /* #define HAL_OPAMP_MODULE_ENABLED */
 /* #define HAL_PCD_MODULE_ENABLED */
 /* #define HAL_PWR_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED 
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RTC_MODULE_ENABLED */
 /* #define HAL_SDADC_MODULE_ENABLED */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
@@ -73,15 +73,15 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 /**
-  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+  *        Timeout value
   */
 #if !defined  (HSE_STARTUP_TIMEOUT)
   #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
@@ -90,25 +90,25 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (8000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
-  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+  *        Timeout value
   */
-#if !defined  (HSI_STARTUP_TIMEOUT) 
+#if !defined  (HSI_STARTUP_TIMEOUT)
  #define HSI_STARTUP_TIMEOUT   (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */  
+#endif /* HSI_STARTUP_TIMEOUT */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (40000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (40000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -124,11 +124,11 @@
   */
 #if !defined  (LSE_STARTUP_TIMEOUT)
   #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */     
+#endif /* LSE_STARTUP_TIMEOUT */
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
   *        frequency, this source is inserted directly through I2S_CKIN pad.
   *        - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
   *        - External clock not generated on EVAL 373
@@ -256,8 +256,8 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_HRTIM_MODULE_ENABLED
  #include "stm32f3xx_hal_hrtim.h"
 #endif /* HAL_HRTIM_MODULE_ENABLED */
diff --git a/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..e9828cbb2
--- /dev/null
+++ b/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f4xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
index 57ef61e26..0dc2879a4 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
@@ -115,7 +115,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -128,11 +128,11 @@ SECTIONS
 
   _siccmram = LOADADDR(.ccmram);
 
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
   * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
+  * the startup code needs to be modified to copy the init-values.
   */
   .ccmram :
   {
@@ -140,17 +140,17 @@ SECTIONS
     _sccmram = .;       /* create a global symbol at ccmram start */
     *(.ccmram)
     *(.ccmram*)
-    
+
     . = ALIGN(4);
     _eccmram = .;       /* create a global symbol at ccmram end */
   } >CCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -173,7 +173,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake b/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake
new file mode 100644
index 000000000..4910d3a88
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f405xx)
+set(JLINK_DEVICE stm32f405rg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F405RGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F405xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
index 19d0a1ea4..11e976a42 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Adafruit Feather STM32F405
+   url: https://www.adafruit.com/product/4382
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,22 +36,35 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PIN_1
-#define LED_STATE_ON          1
-
-// Button: Pin D5
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_7
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
 #define UART_DEV              USART3
-#define UART_GPIO_PORT        GPIOB
-#define UART_GPIO_AF          GPIO_AF7_USART3
-#define UART_TX_PIN           GPIO_PIN_10
-#define UART_RX_PIN           GPIO_PIN_11
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_1, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // BUTTON
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // UART TX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+};
 
 //--------------------------------------------------------------------+
 // RCC Clock
@@ -84,17 +102,20 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
 
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
+  // Enable clocks for Uart
   __HAL_RCC_USART3_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+static inline void board_vbus_sense_init(uint8_t rhport) {
+  if  (rhport == 0) {
+    // Enable VBUS sense (B device) via pin PA9
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  }
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport; (void) state;
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk b/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
index 1de56fe5a..cfd1d8b3b 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F405xx
 
-LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f405xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f405xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f405rg
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
index 57ef61e26..0dc2879a4 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
@@ -115,7 +115,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -128,11 +128,11 @@ SECTIONS
 
   _siccmram = LOADADDR(.ccmram);
 
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
   * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
+  * the startup code needs to be modified to copy the init-values.
   */
   .ccmram :
   {
@@ -140,17 +140,17 @@ SECTIONS
     _sccmram = .;       /* create a global symbol at ccmram start */
     *(.ccmram)
     *(.ccmram*)
-    
+
     . = ALIGN(4);
     _eccmram = .;       /* create a global symbol at ccmram end */
   } >CCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -173,7 +173,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.cmake b/hw/bsp/stm32f4/boards/pyboardv11/board.cmake
new file mode 100644
index 000000000..4910d3a88
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/pyboardv11/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f405xx)
+set(JLINK_DEVICE stm32f405rg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F405RGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F405xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.h b/hw/bsp/stm32f4/boards/pyboardv11/board.h
index 685919c57..9583a924b 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/board.h
+++ b/hw/bsp/stm32f4/boards/pyboardv11/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Pyboard v1.1
+   url: https://www.adafruit.com/product/2390
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,22 +36,35 @@
  extern "C" {
 #endif
 
-// Blue LED is chosen because the other LEDs are connected to ST-LINK lines.
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_4
-#define LED_STATE_ON          1
+#define UART_DEV              USART2
 
-#define BUTTON_PORT           GPIOB
-#define BUTTON_PIN            GPIO_PIN_3
-#define BUTTON_STATE_ACTIVE   1
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
 
-// Enable PA2 as the debug log UART
-// It is not routed to the ST/Link on the Discovery board.
-//#define UART_DEV              USART2
-//#define UART_GPIO_PORT        GPIOA
-//#define UART_GPIO_AF          GPIO_AF7_USART2
-//#define UART_TX_PIN           GPIO_PIN_2
-//#define UART_RX_PIN           GPIO_PIN_3
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // BUTTON
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+};
 
 //--------------------------------------------------------------------+
 // RCC Clock
@@ -84,15 +102,20 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
 
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOB_CLK_ENABLE();
+  // Enable clocks for Uart
+  __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+static inline void board_vbus_sense_init(uint8_t rhport) {
+  if  (rhport == 0) {
+    // Enable VBUS sense (B device) via pin PA9
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  }
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport; (void) state;
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.mk b/hw/bsp/stm32f4/boards/pyboardv11/board.mk
index 02dcd1219..4c52e004a 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/board.mk
+++ b/hw/bsp/stm32f4/boards/pyboardv11/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F405xx
 
-LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f405xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f405xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f405rg
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
index f51f1ab41..b91f456ca 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake
new file mode 100644
index 000000000..fab6a42d2
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f401xc)
+set(JLINK_DEVICE stm32f401cc)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F401VCTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F405xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
index 0f820512c..8a3fe8409 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F401 Blackpill
+   url: https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,23 +36,36 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PIN_13
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   0
-
 // Enable PA2 as the debug log UART
-//#define UART_DEV              USART2
-//#define UART_GPIO_PORT        GPIOA
-//#define UART_GPIO_AF          GPIO_AF7_USART2
-//#define UART_TX_PIN           GPIO_PIN_2
-//#define UART_RX_PIN           GPIO_PIN_3
+#define UART_DEV              USART2
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // BUTTON
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+};
 
 //--------------------------------------------------------------------+
 // RCC Clock
@@ -85,18 +103,21 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
 
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  //__HAL_RCC_USART2_CLK_ENABLE();
+  // Enable clocks for Uart
+  __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Blackpill doens't use VBUS sense (B device) explicitly disable it
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+static inline void board_vbus_sense_init(uint8_t rhport) {
+  // Blackpill doesn't use VBUS sense (B device) explicitly disable it
+  if  (rhport == 0) {
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+  }
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport; (void) state;
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
index de0f3d4c7..3285bd232 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F401xC
 
-LD_FILE = $(BOARD_PATH)/STM32F401VCTx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f401xc.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F401VCTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f401xc.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f401xc.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f401xc_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f401cc
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
index 2ab9a1d57..16f081cfb 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (25000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETx_FLASH.ld
new file mode 100644
index 000000000..2e97c633a
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETx_FLASH.ld
@@ -0,0 +1,177 @@
+/**
+ ******************************************************************************
+ * @file      LinkerScript.ld
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     Linker script for STM32F407VETx Device from STM32F4 series
+ *                      512Kbytes FLASH
+ *                      64Kbytes CCMRAM
+ *                      128Kbytes RAM
+ *
+ *            Set heap size, stack size and stack location according
+ *            to application requirements.
+ *
+ *            Set memory bank area and size if external memory is used
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  CCMRAM    (xrw)    : ORIGIN = 0x10000000,   LENGTH = 64K
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 128K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake
new file mode 100644
index 000000000..50e6b1592
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32f407xx)
+set(JLINK_DEVICE stm32f407ve)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F407VETx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F407xx
+    HSE_VALUE=8000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
new file mode 100644
index 000000000..effbf2be8
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
@@ -0,0 +1,126 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 F407 Blackvet
+   url: https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// Enable PA2 as the debug log UART
+#define UART_DEV              USART2
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // BUTTON
+    .port = GPIOE,
+    .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+};
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* Enable Power Control clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* The voltage scaling allows optimizing the power consumption when the device is
+     clocked below the maximum system frequency, to update the voltage scaling value
+     regarding system frequency refer to product datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/2000000;
+  RCC_OscInitStruct.PLL.PLLN = 168;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+     clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+
+  // Enable clocks for LED, Button, Uart
+  __HAL_RCC_USART2_CLK_ENABLE();
+}
+
+static inline void board_vbus_sense_init(uint8_t rhport) {
+  if (rhport == 0) {
+    // Black F407VET6 doesn't use VBUS sense (B device) explicitly disable it
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+  }
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport; (void) state;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk
new file mode 100644
index 000000000..c46a78f81
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk
@@ -0,0 +1,16 @@
+CFLAGS += -DSTM32F407xx
+
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F407VETx_FLASH.ld
+
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf
+
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f407vg
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h
similarity index 66%
rename from hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h
rename to hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h
index 581f0e46a..e24e782ea 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h
@@ -1,12 +1,12 @@
 /**
   ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
+  * @file    stm32f4xx_hal_conf_template.h
   * @author  MCD Application Team
-  * @brief   HAL configuration file.
+  * @brief   HAL configuration file
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
@@ -18,8 +18,8 @@
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -33,52 +33,54 @@
   * @brief This is the list of modules to be used in the HAL driver
   */
 #define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
+/* #define HAL_ADC_MODULE_ENABLED      */
+/* #define HAL_CAN_MODULE_ENABLED      */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
 #define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
+/* #define HAL_DMA2D_MODULE_ENABLED    */
+/* #define HAL_ETH_MODULE_ENABLED      */
 #define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED     */
+/* #define HAL_NOR_MODULE_ENABLED      */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED     */
+/* #define HAL_SDRAM_MODULE_ENABLED    */
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
+/* #define HAL_EXTI_MODULE_ENABLED     */
+/* #define HAL_I2C_MODULE_ENABLED      */
+/* #define HAL_SMBUS_MODULE_ENABLED    */
+/* #define HAL_I2S_MODULE_ENABLED      */
+/* #define HAL_IWDG_MODULE_ENABLED     */
+/* #define HAL_LTDC_MODULE_ENABLED     */
+/* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
+/* #define HAL_QSPI_MODULE_ENABLED     */
 #define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
+/* #define HAL_RNG_MODULE_ENABLED      */
+/* #define HAL_RTC_MODULE_ENABLED      */
+/* #define HAL_SAI_MODULE_ENABLED      */
+/* #define HAL_SD_MODULE_ENABLED       */
+// #define HAL_SPI_MODULE_ENABLED
+/* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED    */
+/* #define HAL_IRDA_MODULE_ENABLED     */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED     */
 #define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
+/* #define HAL_PCD_MODULE_ENABLED      */
+/* #define HAL_HCD_MODULE_ENABLED      */
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED  */
+/* #define HAL_DFSDM_MODULE_ENABLED    */
+/* #define HAL_LPTIM_MODULE_ENABLED    */
+/* #define HAL_MMC_MODULE_ENABLED      */
 
 /* ########################## HSE/HSI Values adaptation ##################### */
 /**
@@ -87,11 +89,11 @@
   *        (when HSE is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
@@ -100,14 +102,14 @@
   *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
 #if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -115,11 +117,11 @@
   * @brief External Low Speed oscillator (LSE) value.
   */
 #if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+ #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
 #endif /* LSE_VALUE */
 
 #if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
 /**
@@ -128,7 +130,7 @@
   *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
+  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
 #endif /* EXTERNAL_CLOCK_VALUE */
 
 /* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -138,11 +140,12 @@
 /**
   * @brief This is the HAL system configuration section
   */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
 
 #define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
 #define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
@@ -157,15 +160,15 @@
 #define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
 #define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
 #define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
 #define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
 #define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
 #define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
 #define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
 #define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
 #define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
 #define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
 #define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
 #define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
 #define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
@@ -188,9 +191,9 @@
   * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
-/* #define USE_FULL_ASSERT    1 */
+/* #define USE_FULL_ASSERT    1U */
 
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
+/* ################## Ethernet peripheral configuration ##################### */
 
 /* Section 1 : Ethernet peripheral configuration */
 
@@ -205,24 +208,25 @@
 /* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
+#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
 
 /* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
 
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
 
 /* Section 3: Common PHY Registers */
 
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
 
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
@@ -241,14 +245,19 @@
 
 /* Section 4: Extended PHY Registers */
 
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
+#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
 
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
 
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
 
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
 
 /* ################## SPI peripheral configuration ########################## */
 
@@ -265,196 +274,208 @@
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
+  #include "stm32f4xx_hal_rcc.h"
 #endif /* HAL_RCC_MODULE_ENABLED */
 
 #ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
+  #include "stm32f4xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
 
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
 #ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
+  #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
 
 #ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
+  #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
 
 #ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
+  #include "stm32f4xx_hal_adc.h"
 #endif /* HAL_ADC_MODULE_ENABLED */
 
 #ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
+  #include "stm32f4xx_hal_can.h"
 #endif /* HAL_CAN_MODULE_ENABLED */
 
 #ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
+  #include "stm32f4xx_hal_can_legacy.h"
 #endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
 
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
 #ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
+  #include "stm32f4xx_hal_crc.h"
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
+  #include "stm32f4xx_hal_dma2d.h"
 #endif /* HAL_DMA2D_MODULE_ENABLED */
 
 #ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
+  #include "stm32f4xx_hal_dac.h"
 #endif /* HAL_DAC_MODULE_ENABLED */
 
 #ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
+  #include "stm32f4xx_hal_dcmi.h"
 #endif /* HAL_DCMI_MODULE_ENABLED */
 
 #ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
+  #include "stm32f4xx_hal_eth.h"
 #endif /* HAL_ETH_MODULE_ENABLED */
 
 #ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
+  #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
 
 #ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
+  #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
 
 #ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
+  #include "stm32f4xx_hal_nor.h"
 #endif /* HAL_NOR_MODULE_ENABLED */
 
 #ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
+  #include "stm32f4xx_hal_nand.h"
 #endif /* HAL_NAND_MODULE_ENABLED */
 
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
+  #include "stm32f4xx_hal_sdram.h"
 #endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
+ #include "stm32f4xx_hal_hash.h"
 #endif /* HAL_HASH_MODULE_ENABLED */
 
 #ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
+ #include "stm32f4xx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
 #ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
+ #include "stm32f4xx_hal_i2s.h"
 #endif /* HAL_I2S_MODULE_ENABLED */
 
 #ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
+ #include "stm32f4xx_hal_iwdg.h"
 #endif /* HAL_IWDG_MODULE_ENABLED */
 
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
 #ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
+ #include "stm32f4xx_hal_ltdc.h"
 #endif /* HAL_LTDC_MODULE_ENABLED */
 
 #ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
+ #include "stm32f4xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
 
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
 #ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
+ #include "stm32f4xx_hal_rng.h"
 #endif /* HAL_RNG_MODULE_ENABLED */
 
 #ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
+ #include "stm32f4xx_hal_rtc.h"
 #endif /* HAL_RTC_MODULE_ENABLED */
 
 #ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
+ #include "stm32f4xx_hal_sai.h"
 #endif /* HAL_SAI_MODULE_ENABLED */
 
 #ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
+ #include "stm32f4xx_hal_sd.h"
 #endif /* HAL_SD_MODULE_ENABLED */
 
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
 #ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
+ #include "stm32f4xx_hal_spi.h"
 #endif /* HAL_SPI_MODULE_ENABLED */
 
 #ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
+ #include "stm32f4xx_hal_tim.h"
 #endif /* HAL_TIM_MODULE_ENABLED */
 
 #ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
+ #include "stm32f4xx_hal_uart.h"
 #endif /* HAL_UART_MODULE_ENABLED */
 
 #ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
+ #include "stm32f4xx_hal_usart.h"
 #endif /* HAL_USART_MODULE_ENABLED */
 
 #ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
+ #include "stm32f4xx_hal_irda.h"
 #endif /* HAL_IRDA_MODULE_ENABLED */
 
 #ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
+ #include "stm32f4xx_hal_smartcard.h"
 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
 
 #ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
+ #include "stm32f4xx_hal_wwdg.h"
 #endif /* HAL_WWDG_MODULE_ENABLED */
 
 #ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
+ #include "stm32f4xx_hal_pcd.h"
 #endif /* HAL_PCD_MODULE_ENABLED */
 
 #ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
+ #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
 
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
 #ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
+ #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
 
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
 
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
 
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
   * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
+  * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
   *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
   void assert_failed(uint8_t* file, uint32_t line);
 #else
@@ -466,7 +487,7 @@
 }
 #endif
 
-#endif /* __STM32F7xx_HAL_CONF_H */
+#endif /* __STM32F4xx_HAL_CONF_H */
 
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
index c41602720..549787945 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
@@ -115,7 +115,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -128,11 +128,11 @@ SECTIONS
 
   _siccmram = LOADADDR(.ccmram);
 
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
   * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
+  * the startup code needs to be modified to copy the init-values.
   */
   .ccmram :
   {
@@ -140,17 +140,17 @@ SECTIONS
     _sccmram = .;       /* create a global symbol at ccmram start */
     *(.ccmram)
     *(.ccmram*)
-    
+
     . = ALIGN(4);
     _eccmram = .;       /* create a global symbol at ccmram end */
   } >CCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -173,7 +173,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake
new file mode 100644
index 000000000..c8f0330ed
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f407xx)
+set(JLINK_DEVICE stm32f407vg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F407VGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F407xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.h b/hw/bsp/stm32f4/boards/stm32f407disco/board.h
index 693e0393f..19a029768 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F407 Discovery
+   url: https://www.st.com/en/evaluation-tools/stm32f4discovery.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,23 +36,43 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PORT              GPIOD
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
 // Enable PA2 as the debug log UART
 // It is not routed to the ST/Link on the Discovery board.
 #define UART_DEV              USART2
-#define UART_GPIO_PORT        GPIOA
-#define UART_GPIO_AF          GPIO_AF7_USART2
-#define UART_TX_PIN           GPIO_PIN_2
-#define UART_RX_PIN           GPIO_PIN_3
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // BUTTON
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // VBUS0 EN
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  }
+};
 
 //--------------------------------------------------------------------+
 // RCC Clock
@@ -85,17 +110,23 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
 
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
+  // Enable clocks Uart
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+static inline void board_vbus_sense_init(uint8_t rhport) {
+  if (rhport == 0) {
+    // Enable VBUS sense (B device) via pin PA9
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  }
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  if (rhport == 0) {
+    board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+  }
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.mk b/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
index 212b924b4..4de656b0c 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
@@ -1,8 +1,13 @@
 CFLAGS += -DSTM32F407xx
 
-LD_FILE = $(BOARD_PATH)/STM32F407VGTx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F407VGTx_FLASH.ld
+
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f407vg
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
index 7864f8d5f..e24e782ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
index efea1e067..45912ac32 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(4);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake
new file mode 100644
index 000000000..d16db508f
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f411xe)
+set(JLINK_DEVICE stm32f411ce)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F411CEUx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F411xE
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
index 0f820512c..61e5de70d 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F411 Blackpill
+   url: https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,23 +36,35 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PIN_13
-#define LED_STATE_ON          0
+#define UART_DEV              USART2
 
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   0
-
-// Enable PA2 as the debug log UART
-//#define UART_DEV              USART2
-//#define UART_GPIO_PORT        GPIOA
-//#define UART_GPIO_AF          GPIO_AF7_USART2
-//#define UART_TX_PIN           GPIO_PIN_2
-//#define UART_RX_PIN           GPIO_PIN_3
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
 
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // BUTTON
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+};
 
 //--------------------------------------------------------------------+
 // RCC Clock
@@ -85,18 +102,21 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
 
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  //__HAL_RCC_USART2_CLK_ENABLE();
+  // Enable clocks for Uart
+  __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Blackpill doens't use VBUS sense (B device) explicitly disable it
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+static inline void board_vbus_sense_init(uint8_t rhport) {
+  // Blackpill doesn't use VBUS sense (B device) explicitly disable it
+  if  (rhport == 0) {
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+  }
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport; (void) state;
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
index 78be4348a..7af7ca47c 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F411xE
 
-LD_FILE = $(BOARD_PATH)/STM32F411CEUx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F411CEUx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f411xe.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f411xe_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f411ce
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
index 2ab9a1d57..16f081cfb 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (25000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
index 3a0ce526f..85bf5c4c4 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake
new file mode 100644
index 000000000..d7c32c27d
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f411xe)
+set(JLINK_DEVICE stm32f411ve)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F411VETx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F411xE
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.h b/hw/bsp/stm32f4/boards/stm32f411disco/board.h
index 008a94a5d..d7b02e79d 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F411 Discovery
+   url: https://www.st.com/en/evaluation-tools/32f411ediscovery.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,28 +36,46 @@
  extern "C" {
 #endif
 
-// Orange LED
-#define LED_PORT              GPIOD
-#define LED_PIN               GPIO_PIN_13
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-// Enable PA2 as the debug log UART
 #define UART_DEV              USART2
-#define UART_GPIO_PORT        GPIOA
-#define UART_GPIO_AF          GPIO_AF7_USART2
-#define UART_TX_PIN           GPIO_PIN_2
-#define UART_RX_PIN           GPIO_PIN_3
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // BUTTON
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // VBUS0 EN
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  }
+};
 
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
+static inline void board_clock_init(void) {
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
 
@@ -84,17 +107,23 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
 
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
+  // Enable clocks for UART
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(void)
-{
+static inline void board_vbus_sense_init(uint8_t rhport) {
   // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  if (rhport == 0) {
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  }
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  if (rhport == 0) {
+    board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+  }
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.mk b/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
index 48272acff..09fa50bd3 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F411xE
 
-LD_FILE = $(BOARD_PATH)/STM32F411VETx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F411VETx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f411xe.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f411xe_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f411ve
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
index 7864f8d5f..e24e782ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
index b00b5dbe0..38dd3d321 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake
new file mode 100644
index 000000000..59c1c3a7b
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32f412zx)
+set(JLINK_DEVICE stm32f412zg)
+# set(JLINK_OPTION "-USB 000771775987")
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F412ZGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F412Zx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/hw/bsp/stm32f4/boards/stm32f412disco/board.h
index 7f4a4fa15..d5146ae3c 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F412 Discovery
+   url: https://www.st.com/en/evaluation-tools/32f412gdiscovery.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,28 +36,47 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PORT              GPIOE
-#define LED_PIN               GPIO_PIN_2
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
 // UART Enable PA2 as the debug log UART
 #define UART_DEV              USART2
-#define UART_GPIO_PORT        GPIOA
-#define UART_GPIO_AF          GPIO_AF7_USART2
-#define UART_TX_PIN           GPIO_PIN_2
-#define UART_RX_PIN           GPIO_PIN_3
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOE,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // BUTTON
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 },
+    .active_state = 0
+  },
+  { // VBUS0 EN
+    .port = GPIOG,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  }
+};
 
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
+static inline void board_clock_init(void) {
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
@@ -99,18 +123,25 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
 
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOE_CLK_ENABLE();
+  // Enable clocks for Uart
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+static inline void board_vbus_sense_init(uint8_t rhport) {
+  if (rhport == 0) {
+    // Enable VBUS sense (B device) via pin PA9
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+  }
 }
 
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  if (rhport == 0) {
+    board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+  }
+}
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.mk b/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
index 50973f737..f767ac6c4 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F412Zx
 
-LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f412zx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f412zx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f412zg
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
index 7864f8d5f..e24e782ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
index b00b5dbe0..38dd3d321 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.cmake b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.cmake
new file mode 100644
index 000000000..f9e834409
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32f412zx)
+set(JLINK_DEVICE stm32f412zg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F412ZGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F412Zx
+    BOARD_TUD_RHPORT=0
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
index 73c5f83b9..f7026ce61 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F412 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-f412zg.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,22 +36,42 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
 // UART Enable for STLink VCOM
 #define UART_DEV              USART3
-#define UART_GPIO_PORT        GPIOD
-#define UART_GPIO_AF          GPIO_AF7_USART3
-#define UART_TX_PIN           GPIO_PIN_8
-#define UART_RX_PIN           GPIO_PIN_9
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // BUTTON
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // VBUS0 EN
+    .port = GPIOG,
+    .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  }
+};
 
 //--------------------------------------------------------------------+
 // RCC Clock
@@ -99,17 +124,22 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
 
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
+  // Enable clocks for Uart
   __HAL_RCC_USART3_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+static inline void board_vbus_sense_init(uint8_t rhport) {
+  if (rhport == 0) {
+    // Enable VBUS sense (B device) via pin PA9
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+  }
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  if (rhport == 0) {
+    board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+  }
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
index 50973f737..f767ac6c4 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F412Zx
 
-LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f412zx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f412zx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f412zg
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
index 7864f8d5f..e24e782ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/STM32F439ZITX_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f439nucleo/STM32F439ZITX_FLASH.ld
index 2dc277c77..cc098b533 100644
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/STM32F439ZITX_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/STM32F439ZITX_FLASH.ld
@@ -36,12 +36,6 @@
 /* Entry Point */
 ENTRY(Reset_Handler)
 
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
-
-_Min_Heap_Size = 0x200; /* required amount of heap */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
 /* Memories definition */
 MEMORY
 {
@@ -50,6 +44,12 @@ MEMORY
   FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
 }
 
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
 /* Sections */
 SECTIONS
 {
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.cmake b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.cmake
new file mode 100644
index 000000000..524ff8786
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32f439xx)
+set(JLINK_DEVICE stm32f439zi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F439ZITX_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F439xx
+    BOARD_TUD_RHPORT=0
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
index e5a822426..9a348f33f 100644
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F439 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-f439zi.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,22 +36,43 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
 
 // UART Enable for STLink VCOM
 #define UART_DEV              USART3
-#define UART_GPIO_PORT        GPIOD
-#define UART_GPIO_AF          GPIO_AF7_USART3
-#define UART_TX_PIN           GPIO_PIN_8
-#define UART_RX_PIN           GPIO_PIN_9
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // BUTTON
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // VBUS0 EN
+    .port = GPIOG,
+    .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  }
+};
 
 //--------------------------------------------------------------------+
 // RCC Clock
@@ -87,18 +113,23 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
 
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
+  // Enable clocks Uart
   __HAL_RCC_USART3_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+static inline void board_vbus_sense_init(uint8_t rhport) {
+  if (rhport == 0) {
+    // Enable VBUS sense (B device) via pin PA9
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  }
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  if (rhport == 0) {
+    board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+  }
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
index b7b36a8a6..2ab32b7f3 100644
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F439xx
 
-LD_FILE = $(BOARD_PATH)/STM32F439ZITX_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f439xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F439ZITX_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f439xx.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f439xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f439xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f439zi
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
index a2c11d717..7bbd6b54f 100644
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -263,7 +263,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -281,7 +281,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -303,7 +303,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -325,7 +325,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -340,11 +340,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -425,7 +425,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -464,7 +464,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index 82d4957e7..3a1507dbf 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,33 +24,78 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32f4xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
+
+typedef struct {
+  GPIO_TypeDef* port;
+  GPIO_InitTypeDef pin_init;
+  uint8_t active_state;
+} board_pindef_t;
+
 #include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
+void OTG_FS_IRQHandler(void) {
+  tusb_int_handler(0, true);
 }
 
-void OTG_HS_IRQHandler(void)
-{
-  tud_int_handler(1);
+void OTG_HS_IRQHandler(void) {
+  tusb_int_handler(1, true);
 }
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
-UART_HandleTypeDef UartHandle;
+UART_HandleTypeDef UartHandle = {
+    .Instance = UART_DEV,
+    .Init = {
+      .BaudRate   = CFG_BOARD_UART_BAUDRATE,
+      .WordLength = UART_WORDLENGTH_8B,
+      .StopBits   = UART_STOPBITS_1,
+      .Parity     = UART_PARITY_NONE,
+      .HwFlowCtl  = UART_HWCONTROL_NONE,
+      .Mode       = UART_MODE_TX_RX,
+      .OverSampling = UART_OVERSAMPLING_16
+    }
+};
 
-void board_init(void)
-{
+void board_init(void) {
   board_clock_init();
   //SystemCoreClockUpdate();
 
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+#ifdef __HAL_RCC_GPIOE_CLK_ENABLE
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+#endif
+#ifdef __HAL_RCC_GPIOF_CLK_ENABLE
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+#endif
+#ifdef __HAL_RCC_GPIOG_CLK_ENABLE
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+#endif
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+#ifdef __HAL_RCC_GPIOI_CLK_ENABLE
+  __HAL_RCC_GPIOI_CLK_ENABLE();
+#endif
+#ifdef __HAL_RCC_GPIOJ_CLK_ENABLE
+  __HAL_RCC_GPIOJ_CLK_ENABLE();
+#endif
+
+  for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
+    HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
+  }
+
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -62,48 +107,14 @@ void board_init(void)
   NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
   board_led_write(false);
 
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
 #ifdef UART_DEV
-  // UART
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
-
-  UartHandle = (UART_HandleTypeDef){
-    .Instance        = UART_DEV,
-    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
-    .Init.WordLength = UART_WORDLENGTH_8B,
-    .Init.StopBits   = UART_STOPBITS_1,
-    .Init.Parity     = UART_PARITY_NONE,
-    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
-    .Init.Mode       = UART_MODE_TX_RX,
-    .Init.OverSampling = UART_OVERSAMPLING_16
-  };
   HAL_UART_Init(&UartHandle);
 #endif
 
-  /* Configure USB FS GPIOs */
-  __HAL_RCC_GPIOA_CLK_ENABLE();
+  //------------- USB FS -------------//
+  GPIO_InitTypeDef GPIO_InitStruct;
 
   /* Configure USB D+ D- Pins */
   GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
@@ -127,6 +138,36 @@ void board_init(void)
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
+  // Enable USB OTG clock
+  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+
+  //------------- USB HS -------------//
+#ifdef __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+  GPIO_InitStruct.Pin = GPIO_PIN_14 | GPIO_PIN_15;
+  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* Configure VBUS Pin */
+  GPIO_InitStruct.Pin = GPIO_PIN_13;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* ID Pin */
+  GPIO_InitStruct.Pin = GPIO_PIN_12;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  // Enable USB OTG clock
+  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+#endif
+
 #ifdef STM32F412Zx
   /* Configure POWER_SWITCH IO pin */
   __HAL_RCC_GPIOG_CLK_ENABLE();
@@ -136,38 +177,60 @@ void board_init(void)
   HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 #endif
 
-  // Enable USB OTG clock
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+#if CFG_TUD_ENABLED
+  board_vbus_sense_init(BOARD_TUD_RHPORT);
+#endif
 
-//  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
-
-  board_vbus_sense_init();
+#if CFG_TUH_ENABLED
+  board_vbus_set(BOARD_TUD_RHPORT, true);
+#endif
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+#ifdef PINID_LED
+  board_pindef_t* pindef = &board_pindef[PINID_LED];
+  GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET;
+  HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state);
+#else
+  (void) state;
+#endif
 }
 
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+uint32_t board_button_read(void) {
+#ifdef PINID_BUTTON
+  board_pindef_t* pindef = &board_pindef[PINID_BUTTON];
+  return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin);
+#else
+  return 0;
+#endif
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t *stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t *id32 = (uint32_t *) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
 #ifdef UART_DEV
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff);
   return len;
 #else
   (void) buf; (void) len; (void) UartHandle;
@@ -175,27 +238,25 @@ int board_uart_write(void const * buf, int len)
 #endif
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake
new file mode 100644
index 000000000..db5736192
--- /dev/null
+++ b/hw/bsp/stm32f4/family.cmake
@@ -0,0 +1,142 @@
+include_guard()
+
+set(ST_FAMILY f4)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F4 CACHE INTERNAL "")
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif ()
+
+if (NOT DEFINED RHPORT_SPEED)
+  # Most F7 does not has built-in HS PHY
+  set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+    BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+    BOARD_TUH_RHPORT=${RHPORT_HOST}
+    BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F4)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 9811d3371..51ff43a60 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -6,28 +6,69 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
+
+# Determine RHPORT_DEVICE_SPEED if not defined
+ifndef RHPORT_DEVICE_SPEED
+ifeq ($(RHPORT_DEVICE), 0)
+  RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
+# Determine RHPORT_HOST_SPEED if not defined
+ifndef RHPORT_HOST_SPEED
+ifeq ($(RHPORT_HOST), 0)
+  RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F4 \
+	-DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
+	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
+	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
+	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
+
+# GCC Flags
+CFLAGS_GCC += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F4
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=cast-align
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
 INC += \
@@ -36,8 +77,5 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h b/hw/bsp/stm32f4/stm32f4xx_hal_conf.h
similarity index 66%
rename from hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h
rename to hw/bsp/stm32f4/stm32f4xx_hal_conf.h
index 03dec8f0d..e24e782ea 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h
+++ b/hw/bsp/stm32f4/stm32f4xx_hal_conf.h
@@ -1,12 +1,12 @@
 /**
   ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
+  * @file    stm32f4xx_hal_conf_template.h
   * @author  MCD Application Team
-  * @brief   HAL configuration file.
+  * @brief   HAL configuration file
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
@@ -18,8 +18,8 @@
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -33,52 +33,54 @@
   * @brief This is the list of modules to be used in the HAL driver
   */
 #define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
+/* #define HAL_ADC_MODULE_ENABLED      */
+/* #define HAL_CAN_MODULE_ENABLED      */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
 #define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
+/* #define HAL_DMA2D_MODULE_ENABLED    */
+/* #define HAL_ETH_MODULE_ENABLED      */
 #define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED     */
+/* #define HAL_NOR_MODULE_ENABLED      */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED     */
+/* #define HAL_SDRAM_MODULE_ENABLED    */
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
+/* #define HAL_EXTI_MODULE_ENABLED     */
+/* #define HAL_I2C_MODULE_ENABLED      */
+/* #define HAL_SMBUS_MODULE_ENABLED    */
+/* #define HAL_I2S_MODULE_ENABLED      */
+/* #define HAL_IWDG_MODULE_ENABLED     */
+/* #define HAL_LTDC_MODULE_ENABLED     */
+/* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
+/* #define HAL_QSPI_MODULE_ENABLED     */
 #define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
+/* #define HAL_RNG_MODULE_ENABLED      */
+/* #define HAL_RTC_MODULE_ENABLED      */
+/* #define HAL_SAI_MODULE_ENABLED      */
+/* #define HAL_SD_MODULE_ENABLED       */
+// #define HAL_SPI_MODULE_ENABLED
+/* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED    */
+/* #define HAL_IRDA_MODULE_ENABLED     */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED     */
 #define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
+/* #define HAL_PCD_MODULE_ENABLED      */
+/* #define HAL_HCD_MODULE_ENABLED      */
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED  */
+/* #define HAL_DFSDM_MODULE_ENABLED    */
+/* #define HAL_LPTIM_MODULE_ENABLED    */
+/* #define HAL_MMC_MODULE_ENABLED      */
 
 /* ########################## HSE/HSI Values adaptation ##################### */
 /**
@@ -87,11 +89,11 @@
   *        (when HSE is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
@@ -100,14 +102,14 @@
   *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
 #if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -115,11 +117,11 @@
   * @brief External Low Speed oscillator (LSE) value.
   */
 #if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+ #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
 #endif /* LSE_VALUE */
 
 #if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
 /**
@@ -128,7 +130,7 @@
   *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
+  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
 #endif /* EXTERNAL_CLOCK_VALUE */
 
 /* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -138,11 +140,12 @@
 /**
   * @brief This is the HAL system configuration section
   */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
 
 #define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
 #define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
@@ -157,15 +160,15 @@
 #define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
 #define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
 #define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
 #define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
 #define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
 #define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
 #define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
 #define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
 #define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
 #define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
 #define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
 #define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
 #define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
@@ -188,9 +191,9 @@
   * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
-/* #define USE_FULL_ASSERT    1 */
+/* #define USE_FULL_ASSERT    1U */
 
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
+/* ################## Ethernet peripheral configuration ##################### */
 
 /* Section 1 : Ethernet peripheral configuration */
 
@@ -205,24 +208,25 @@
 /* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
+#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
 
 /* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
 
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
 
 /* Section 3: Common PHY Registers */
 
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
 
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
@@ -241,14 +245,19 @@
 
 /* Section 4: Extended PHY Registers */
 
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
+#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
 
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
 
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
 
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
 
 /* ################## SPI peripheral configuration ########################## */
 
@@ -265,196 +274,208 @@
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
+  #include "stm32f4xx_hal_rcc.h"
 #endif /* HAL_RCC_MODULE_ENABLED */
 
 #ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
+  #include "stm32f4xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
 
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
 #ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
+  #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
 
 #ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
+  #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
 
 #ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
+  #include "stm32f4xx_hal_adc.h"
 #endif /* HAL_ADC_MODULE_ENABLED */
 
 #ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
+  #include "stm32f4xx_hal_can.h"
 #endif /* HAL_CAN_MODULE_ENABLED */
 
 #ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
+  #include "stm32f4xx_hal_can_legacy.h"
 #endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
 
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
 #ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
+  #include "stm32f4xx_hal_crc.h"
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
+  #include "stm32f4xx_hal_dma2d.h"
 #endif /* HAL_DMA2D_MODULE_ENABLED */
 
 #ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
+  #include "stm32f4xx_hal_dac.h"
 #endif /* HAL_DAC_MODULE_ENABLED */
 
 #ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
+  #include "stm32f4xx_hal_dcmi.h"
 #endif /* HAL_DCMI_MODULE_ENABLED */
 
 #ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
+  #include "stm32f4xx_hal_eth.h"
 #endif /* HAL_ETH_MODULE_ENABLED */
 
 #ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
+  #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
 
 #ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
+  #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
 
 #ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
+  #include "stm32f4xx_hal_nor.h"
 #endif /* HAL_NOR_MODULE_ENABLED */
 
 #ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
+  #include "stm32f4xx_hal_nand.h"
 #endif /* HAL_NAND_MODULE_ENABLED */
 
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
+  #include "stm32f4xx_hal_sdram.h"
 #endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
+ #include "stm32f4xx_hal_hash.h"
 #endif /* HAL_HASH_MODULE_ENABLED */
 
 #ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
+ #include "stm32f4xx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
 #ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
+ #include "stm32f4xx_hal_i2s.h"
 #endif /* HAL_I2S_MODULE_ENABLED */
 
 #ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
+ #include "stm32f4xx_hal_iwdg.h"
 #endif /* HAL_IWDG_MODULE_ENABLED */
 
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
 #ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
+ #include "stm32f4xx_hal_ltdc.h"
 #endif /* HAL_LTDC_MODULE_ENABLED */
 
 #ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
+ #include "stm32f4xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
 
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
 #ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
+ #include "stm32f4xx_hal_rng.h"
 #endif /* HAL_RNG_MODULE_ENABLED */
 
 #ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
+ #include "stm32f4xx_hal_rtc.h"
 #endif /* HAL_RTC_MODULE_ENABLED */
 
 #ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
+ #include "stm32f4xx_hal_sai.h"
 #endif /* HAL_SAI_MODULE_ENABLED */
 
 #ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
+ #include "stm32f4xx_hal_sd.h"
 #endif /* HAL_SD_MODULE_ENABLED */
 
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
 #ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
+ #include "stm32f4xx_hal_spi.h"
 #endif /* HAL_SPI_MODULE_ENABLED */
 
 #ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
+ #include "stm32f4xx_hal_tim.h"
 #endif /* HAL_TIM_MODULE_ENABLED */
 
 #ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
+ #include "stm32f4xx_hal_uart.h"
 #endif /* HAL_UART_MODULE_ENABLED */
 
 #ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
+ #include "stm32f4xx_hal_usart.h"
 #endif /* HAL_USART_MODULE_ENABLED */
 
 #ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
+ #include "stm32f4xx_hal_irda.h"
 #endif /* HAL_IRDA_MODULE_ENABLED */
 
 #ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
+ #include "stm32f4xx_hal_smartcard.h"
 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
 
 #ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
+ #include "stm32f4xx_hal_wwdg.h"
 #endif /* HAL_WWDG_MODULE_ENABLED */
 
 #ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
+ #include "stm32f4xx_hal_pcd.h"
 #endif /* HAL_PCD_MODULE_ENABLED */
 
 #ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
+ #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
 
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
 #ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
+ #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
 
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
 
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
 
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
   * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
+  * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
   *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
   void assert_failed(uint8_t* file, uint32_t line);
 #else
@@ -466,7 +487,7 @@
 }
 #endif
 
-#endif /* __STM32F7xx_HAL_CONF_H */
+#endif /* __STM32F4xx_HAL_CONF_H */
 
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..31fb7942f
--- /dev/null
+++ b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f7xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld b/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld
index 8645ce5c5..f4be85703 100644
--- a/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake b/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake
new file mode 100644
index 000000000..6a1132ef8
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake
@@ -0,0 +1,20 @@
+set(MCU_VARIANT stm32f723xx)
+set(JLINK_DEVICE stm32f723xx)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F723xE_FLASH.ld)
+
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F723xx
+    HSE_VALUE=25000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h
index d0ef6625f..06adb79ad 100644
--- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Stlink-v3 mini
+   url: https://www.st.com/en/development-tools/stlink-v3mini.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,29 +36,37 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOA
-#define LED_PIN               GPIO_PIN_10
-#define LED_STATE_ON          1
-
-// No physical button is populated
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
 #define UART_DEV              USART6
 #define UART_CLK_EN           __HAL_RCC_USART6_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF8_USART6
-
-#define UART_TX_PORT          GPIOG
-#define UART_TX_PIN           GPIO_PIN_9
-
-#define UART_RX_PORT          GPIOG
-#define UART_RX_PIN           GPIO_PIN_14
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
 #define OTG_HS_VBUS_SENSE     0
 
+#define PINID_LED      0
+#define PINID_UART_TX  1
+#define PINID_UART_RX  2
+//#define PINID_VBUS0_EN 4
+//#define PINID_VBUS1_EN 5
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOG,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF8_USART6 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOG,
+    .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF8_USART6 },
+    .active_state = 0
+  }
+};
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -92,8 +105,15 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
+
+  UART_CLK_EN();
 }
 
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+ (void) rhport; (void) state;
+}
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
index a18b3231d..a19e455c7 100644
--- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
@@ -1,4 +1,10 @@
+MCU_VARIANT = stm32f723xx
+
 # Only OTG-HS has a connector on this board
+RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 1
+
 PORT ?= 1
 SPEED ?= high
 
@@ -6,9 +12,8 @@ CFLAGS += \
   -DSTM32F723xx \
   -DHSE_VALUE=25000000 \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F723xE_FLASH.ld
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld
index 8645ce5c5..f4be85703 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake
new file mode 100644
index 000000000..eb3ed407b
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT stm32f723xx)
+set(JLINK_DEVICE stm32f723ie)
+#set(JLINK_OPTION "-USB 000776606156")
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F723xE_FLASH.ld)
+
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+# For Hardware test: device default to PORT 0, Host to port 1
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F723xx
+    HSE_VALUE=25000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h
index 93d83efc6..35102c1f2 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F723 Discovery
+   url: https://www.st.com/en/evaluation-tools/32f723ediscovery.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,33 +36,57 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_1
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
 #define UART_DEV              USART6
 #define UART_CLK_EN           __HAL_RCC_USART6_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF8_USART6
-
-#define UART_TX_PORT          GPIOC
-#define UART_TX_PIN           GPIO_PIN_6
-
-#define UART_RX_PORT          GPIOC
-#define UART_RX_PIN           GPIO_PIN_7
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
 #define OTG_HS_VBUS_SENSE     0
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+#define PINID_VBUS1_EN 5
+
+static board_pindef_t board_pindef[] = {
+{ // LED
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_1, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+{ // Button
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+{ // UART TX
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF8_USART6 },
+    .active_state = 0
+  },
+{ // UART RX
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF8_USART6 },
+    .active_state = 0
+  },
+{ // VBUS0 EN
+    .port = GPIOG,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+{ // VBUS1 EN
+    .port = GPIOH,
+    .pin_init = { .Pin = GPIO_PIN_12, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+};
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
+static inline void board_clock_init(void) {
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
 
@@ -74,7 +103,7 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000;
   RCC_OscInitStruct.PLL.PLLN = 432;
   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
   RCC_OscInitStruct.PLL.PLLQ = 9;
@@ -91,12 +120,14 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
+
+  UART_CLK_EN();
 }
 
-//static inline void board_vbus_sense_init(void)
-//{
-//
-//}
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  board_pindef_t* pindef = &board_pindef[rhport ? PINID_VBUS1_EN : PINID_VBUS0_EN];
+  HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+}
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
index 66d9ff8fb..9b8e7a969 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
@@ -1,12 +1,16 @@
-PORT ?= 1
-SPEED ?= high
+MCU_VARIANT = stm32f723xx
+
+# For Hardware test: device default to PORT 0, Host to port 1
+RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 1
 
 CFLAGS += \
   -DSTM32F723xx \
   -DHSE_VALUE=25000000 \
 
-LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F723xE_FLASH.ld
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld
index 045ec76f9..eeb0e29f3 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake
new file mode 100644
index 000000000..bc26c6ef4
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT stm32f746xx)
+set(JLINK_DEVICE stm32f746xx)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F746ZGTx_FLASH.ld)
+
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F746xx
+    HSE_VALUE=25000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.h b/hw/bsp/stm32f7/boards/stm32f746disco/board.h
index ee342b9f5..2964ebada 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F746 Discovery
+   url: https://www.st.com/en/evaluation-tools/32f746gdiscovery.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,28 +36,43 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOI
-#define LED_PIN               GPIO_PIN_1
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOI
-#define BUTTON_PIN            GPIO_PIN_11
-#define BUTTON_STATE_ACTIVE   1
-
 #define UART_DEV              USART1
 #define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF7_USART1
-
-#define UART_TX_PORT          GPIOA
-#define UART_TX_PIN           GPIO_PIN_9
-
-#define UART_RX_PORT          GPIOB
-#define UART_RX_PIN           GPIO_PIN_7
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     0
 #define OTG_HS_VBUS_SENSE     0
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+//#define PINID_VBUS0_EN 4
+//#define PINID_VBUS1_EN 5
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOI,
+    .pin_init = { .Pin = GPIO_PIN_1, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+   .port = GPIOI,
+   .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+   .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART1 },
+    .active_state = 0
+  },
+  { // UART RX
+   .port = GPIOB,
+   .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART1 },
+   .active_state = 0
+  },
+};
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -91,8 +111,15 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
+
+  UART_CLK_EN();
 }
 
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+ (void) rhport; (void) state;
+}
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
index 2ba59f67a..c2b54406e 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
@@ -1,3 +1,9 @@
+MCU_VARIANT = stm32f746xx
+
+RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
+
 PORT ?= 1
 SPEED ?= high
 
@@ -5,8 +11,8 @@ CFLAGS += \
   -DSTM32F746xx \
   -DHSE_VALUE=25000000
 
-LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
index b434a01b7..eeb0e29f3 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake
new file mode 100644
index 000000000..fd5c1ef11
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT stm32f746xx)
+set(JLINK_DEVICE stm32f746xx)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F746ZGTx_FLASH.ld)
+
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F746xx
+    HSE_VALUE=8000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
index 92c109a72..b039f5543 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F746 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-f746zg.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,27 +36,43 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
 #define UART_DEV              USART3
 #define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF7_USART3
-
-#define UART_TX_PORT          GPIOD
-#define UART_TX_PIN           GPIO_PIN_8
-#define UART_RX_PORT          GPIOD
-#define UART_RX_PIN           GPIO_PIN_9
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
 #define OTG_HS_VBUS_SENSE     0
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+//#define PINID_VBUS0_EN 4
+//#define PINID_VBUS1_EN 5
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+};
+
 static inline void board_clock_init(void)
 {
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
@@ -89,6 +110,12 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
+
+  UART_CLK_EN();
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+ (void) rhport; (void) state;
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
index 3dcf4817e..fe7104eca 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
@@ -1,3 +1,8 @@
+MCU_VARIANT = stm32f746xx
+
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
+
 PORT ?= 0
 SPEED ?= full
 
@@ -5,8 +10,8 @@ CFLAGS += \
   -DSTM32F746xx \
   -DHSE_VALUE=8000000
 
-LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
deleted file mode 100644
index 234191b00..000000000
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED 
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
index 0b6d5a494..520a75539 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake
new file mode 100644
index 000000000..e4cf4c5f5
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT stm32f767xx)
+set(JLINK_DEVICE stm32f767zi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F767ZITx_FLASH.ld)
+
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F767xx
+    HSE_VALUE=8000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h
index 1283f2313..b5b3841f1 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F767 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-f767zi.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,28 +36,43 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
 #define UART_DEV              USART3
 #define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF7_USART3
-
-#define UART_TX_PORT          GPIOD
-#define UART_TX_PIN           GPIO_PIN_8
-
-#define UART_RX_PORT          GPIOD
-#define UART_RX_PIN           GPIO_PIN_9
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
 #define OTG_HS_VBUS_SENSE     0
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+//#define PINID_VBUS0_EN 4
+//#define PINID_VBUS1_EN 5
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+};
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -92,8 +112,13 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
+
+  UART_CLK_EN();
 }
 
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+ (void) rhport; (void) state;
+}
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
index 7710619e5..d61e0a00d 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
@@ -1,12 +1,17 @@
+MCU_VARIANT = stm32f767xx
+
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
+
 PORT ?= 0
-SPEED ?= full 
+SPEED ?= full
 
 CFLAGS += \
   -DSTM32F767xx \
 	-DHSE_VALUE=8000000 \
 
-LD_FILE = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f767zi
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
deleted file mode 100644
index 234191b00..000000000
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED 
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld
index 378ed80dd..520a75539 100644
--- a/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake
new file mode 100644
index 000000000..2335b869e
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake
@@ -0,0 +1,20 @@
+set(MCU_VARIANT stm32f769xx)
+set(JLINK_DEVICE stm32f769ni)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F769ZITx_FLASH.ld)
+
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F769xx
+    HSE_VALUE=25000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.h b/hw/bsp/stm32f7/boards/stm32f769disco/board.h
index 5ec217f5f..8ac520619 100644
--- a/hw/bsp/stm32f7/boards/stm32f769disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 F769 Discovery
+   url: https://www.st.com/en/evaluation-tools/32f769idiscovery.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,28 +36,43 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOJ
-#define LED_PIN               GPIO_PIN_12
-#define LED_STATE_ON          5
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
 #define UART_DEV              USART1
 #define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF7_USART1
-
-#define UART_TX_PORT          GPIOA
-#define UART_TX_PIN           GPIO_PIN_9
-
-#define UART_RX_PORT          GPIOA
-#define UART_RX_PIN           GPIO_PIN_10
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
 #define OTG_HS_VBUS_SENSE     0
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+//#define PINID_VBUS0_EN 4
+//#define PINID_VBUS1_EN 5
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOJ,
+    .pin_init = { .Pin = GPIO_PIN_12, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART1 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART1 },
+    .active_state = 0
+  },
+};
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -92,6 +112,12 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
+
+  UART_CLK_EN();
+}
+
+static inline void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport; (void) state;
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
index 45b4a78c7..e756c9727 100644
--- a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
@@ -1,4 +1,10 @@
+MCU_VARIANT = stm32f769xx
+
 # Only OTG-HS has a connector on this board
+RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 1
+
 PORT ?= 1
 SPEED ?= high
 
@@ -6,8 +12,10 @@ CFLAGS += \
   -DSTM32F769xx \
   -DHSE_VALUE=25000000 \
 
-LD_FILE = $(BOARD_PATH)/STM32F769ZITx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f769xx.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F769ZITx_FLASH.ld
+
+JLINK_DEVICE = stm32f769ni
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h
deleted file mode 100644
index 581f0e46a..000000000
--- a/hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index 425e6e1bc..5f63834d0 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -26,33 +26,58 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32f7xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
+
+typedef struct {
+  GPIO_TypeDef* port;
+  GPIO_InitTypeDef pin_init;
+  uint8_t active_state;
+} board_pindef_t;
+
 #include "board.h"
 
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+#ifdef UART_DEV
+UART_HandleTypeDef UartHandle = {
+  .Instance = UART_DEV,
+  .Init = {
+    .BaudRate = CFG_BOARD_UART_BAUDRATE,
+    .WordLength = UART_WORDLENGTH_8B,
+    .StopBits = UART_STOPBITS_1,
+    .Parity = UART_PARITY_NONE,
+    .HwFlowCtl = UART_HWCONTROL_NONE,
+    .Mode = UART_MODE_TX_RX,
+    .OverSampling = UART_OVERSAMPLING_16,
+  }
+};
+#endif
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
+void OTG_FS_IRQHandler(void) {
+  tusb_int_handler(0, true);
 }
 
 // Despite being call USB2_OTG
 // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-void OTG_HS_IRQHandler(void)
-{
-  tud_int_handler(1);
+void OTG_HS_IRQHandler(void) {
+  tusb_int_handler(1, true);
 }
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-UART_HandleTypeDef UartHandle;
-
-void board_init(void)
-{
+void board_init(void) {
   board_clock_init();
 
   // Enable All GPIOs clocks
@@ -63,12 +88,13 @@ void board_init(void)
   __HAL_RCC_GPIOG_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE();  // ULPI NXT
   __HAL_RCC_GPIOI_CLK_ENABLE();  // ULPI NXT
-
 #ifdef __HAL_RCC_GPIOJ_CLK_ENABLE
   __HAL_RCC_GPIOJ_CLK_ENABLE();
 #endif
 
-  UART_CLK_EN();
+  for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
+    HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
+  }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -83,51 +109,13 @@ void board_init(void)
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // Uart TX
-  GPIO_InitStruct.Pin       = UART_TX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_TX_PORT, &GPIO_InitStruct);
-
-  // Uart RX
-  GPIO_InitStruct.Pin       = UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_RX_PORT, &GPIO_InitStruct);
-
-  UartHandle.Instance          = UART_DEV;
-  UartHandle.Init.BaudRate     = CFG_BOARD_UART_BAUDRATE;
-  UartHandle.Init.WordLength   = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits     = UART_STOPBITS_1;
-  UartHandle.Init.Parity       = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl    = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode         = UART_MODE_TX_RX;
-  UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
+#ifdef UART_DEV
   HAL_UART_Init(&UartHandle);
+#endif
 
-#if BOARD_TUD_RHPORT == 0
-  // OTG_FS
+  GPIO_InitTypeDef GPIO_InitStruct;
 
+  //------------- rhport0: OTG_FS -------------//
   /* Configure DM DP Pins */
   GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
   GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -143,9 +131,19 @@ void board_init(void)
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wshadow"
+#endif
+
   /* Enable USB FS Clocks */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #if OTG_FS_VBUS_SENSE
   /* Configure VBUS Pin */
   GPIO_InitStruct.Pin = GPIO_PIN_9;
@@ -164,10 +162,8 @@ void board_init(void)
   USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 #endif // vbus sense
 
-#else
-  // OTG_HS
-
-  #ifdef USB_HS_PHYC
+  //------------- rhport1: OTG_HS -------------//
+#ifdef USB_HS_PHYC
   // MCU with built-in HS PHY such as F723, F733, F730
 
   /* Configure DM DP Pins */
@@ -175,7 +171,7 @@ void board_init(void)
   GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
   GPIO_InitStruct.Pull      = GPIO_NOPULL;
   GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
+  GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
   // Enable HS VBUS sense (B device) via pin PB13
@@ -185,59 +181,59 @@ void board_init(void)
   GPIO_InitStruct.Pin       = GPIO_PIN_13;
   GPIO_InitStruct.Mode      = GPIO_MODE_AF_OD;
   GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+  GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
   /* Enable PHYC Clocks */
   __HAL_RCC_OTGPHYC_CLK_ENABLE();
 
-  #else
-  // MUC with external ULPI PHY
+#else
+  // MCU with external ULPI PHY
 
   /* ULPI CLK */
-  GPIO_InitStruct.Pin       = GPIO_PIN_5;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
   /* ULPI D0 */
-  GPIO_InitStruct.Pin       = GPIO_PIN_3;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = GPIO_PIN_3;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
   /* ULPI D1 D2 D3 D4 D5 D6 D7 */
-  GPIO_InitStruct.Pin       = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_5;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
   /* ULPI STP */
-  GPIO_InitStruct.Pin       = GPIO_PIN_0 | GPIO_PIN_2;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_2;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 
   /* NXT */
-  GPIO_InitStruct.Pin       = GPIO_PIN_4;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
+  GPIO_InitStruct.Pin = GPIO_PIN_4;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
 
   /* ULPI DIR */
-  GPIO_InitStruct.Pin       = GPIO_PIN_11;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
+  GPIO_InitStruct.Pin = GPIO_PIN_11;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
-  #endif // USB_HS_PHYC
+#endif // USB_HS_PHYC
 
   // Enable USB HS & ULPI Clocks
   __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
@@ -254,61 +250,83 @@ void board_init(void)
   USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 #endif
 
-  // Force device mode
-  USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
-  USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
-
-#endif // BOARD_TUD_RHPORT
-
+  // Turn on host vbus
+#if CFG_TUH_ENABLED
+  board_vbus_set(BOARD_TUH_RHPORT, true);
+#endif
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+#ifdef PINID_LED
+  board_pindef_t* pindef = &board_pindef[PINID_LED];
+  GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET;
+  HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state);
+#else
+  (void) state;
+#endif
 }
 
-uint32_t board_button_read(void)
-{
-  return HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+uint32_t board_button_read(void) {
+#ifdef PINID_BUTTON
+  board_pindef_t* pindef = &board_pindef[PINID_BUTTON];
+  return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin);
+#else
   return 0;
+#endif
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff);
+  return len;
+#else
+  (void) buf; (void) len;
+  return -1;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake
new file mode 100644
index 000000000..1a3365332
--- /dev/null
+++ b/hw/bsp/stm32f7/family.cmake
@@ -0,0 +1,144 @@
+include_guard()
+
+set(ST_FAMILY f7)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m7-fpsp CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F7 CACHE INTERNAL "")
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif ()
+
+if (NOT DEFINED RHPORT_SPEED)
+  # Most F7 does not has built-in HS PHY
+  set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+    BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+    BOARD_TUH_RHPORT=${RHPORT_HOST}
+    BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F7)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index b8a5d7ead..abeea784c 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -6,38 +6,79 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m7-fpsp
 
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F7 \
-  -DBOARD_TUD_RHPORT=$(PORT)
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
 
-ifeq ($(PORT), 1)
-  ifeq ($(SPEED), high)
-    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    $(info "Using OTG_HS in HighSpeed mode")
-  else
-    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
-    $(info "Using OTG_HS in FullSpeed mode")
-  endif
+# Determine RHPORT_DEVICE_SPEED if not defined
+ifndef RHPORT_DEVICE_SPEED
+ifeq ($(RHPORT_DEVICE), 0)
+  RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED))
 else
-  $(info "Using OTG_FS")
+  RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED))
+endif
 endif
 
+# Determine RHPORT_HOST_SPEED if not defined
+ifndef RHPORT_HOST_SPEED
+ifeq ($(RHPORT_HOST), 0)
+  RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F7 \
+	-DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
+	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
+	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
+	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
+
+#ifeq ($(PORT), 1)
+#  ifeq ($(SPEED), high)
+#    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+#    $(info "Using OTG_HS in HighSpeed mode")
+#  else
+#    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+#    $(info "Using OTG_HS in FullSpeed mode")
+#  endif
+#else
+#  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+#  $(info "Using OTG_FS")
+#endif
+
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=shadow -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=cast-align
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
@@ -50,5 +91,9 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/stm32f7xx_hal_conf.h
similarity index 100%
rename from hw/bsp/stm32f7/boards/stlinkv3mini/stm32f7xx_hal_conf.h
rename to hw/bsp/stm32f7/stm32f7xx_hal_conf.h
diff --git a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..76133ea2d
--- /dev/null
+++ b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32g0xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        0
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 200 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld
new file mode 100644
index 000000000..b6fab16cf
--- /dev/null
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld
@@ -0,0 +1,188 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Author		: STM32CubeMX
+**
+**  Abstract    : Linker script for STM32G0B1RETx series
+**                512Kbytes FLASH and 144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 144K
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 512K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
new file mode 100644
index 000000000..8874b0526
--- /dev/null
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32g0b1xx)
+set(JLINK_DEVICE stm32g0b1re)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32G0B1xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
new file mode 100644
index 000000000..14d309da1
--- /dev/null
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
@@ -0,0 +1,168 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2023, HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 G0B1 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// G0B1RE Nucleo does not has usb connection. We need to manually connect
+// - PA12 for D+, CN10.12
+// - PA11 for D-, CN10.14
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   0
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART2
+#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF1_USART2
+#define UART_TX_PIN           GPIO_PIN_2
+#define UART_RX_PIN           GPIO_PIN_3
+
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+#if 1
+// Clock configure for STM32G0B1RE Nucleo
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure. */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /** Initializes the CPU, AHB and APB buses clocks */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  // Configure CRS clock source
+  __HAL_RCC_CRS_CLK_ENABLE();
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
+  RCC_CRSInitStruct.ErrorLimitValue = 34;
+  RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
+  /* Select HSI48 as USB clock source */
+  RCC_PeriphCLKInitTypeDef usb_clk = {0 };
+  usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&usb_clk);
+
+  // Enable HSI48
+  RCC_OscInitTypeDef osc_hsi48 = {0};
+  osc_hsi48.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  osc_hsi48.HSI48State = RCC_HSI48_ON;
+  HAL_RCC_OscConfig(&osc_hsi48);
+}
+#else
+
+// Clock configure for STM32G0 nucleo with B0 mcu variant for someone that is skilled enough
+// to rework and solder the B0 chip. Note: SB17 may need to be soldered as well (check user manual)
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = { 0 };
+
+  /** Configure the main internal regulator output voltage */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure. */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 12;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Select HSI48 as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /** Initializes the CPU, AHB and APB buses clocks */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+}
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk
new file mode 100644
index 000000000..6a6078d5f
--- /dev/null
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk
@@ -0,0 +1,13 @@
+CFLAGS += \
+	-DSTM32G0B1xx
+
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g0b1xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32G0B1RETx_FLASH.ld
+
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32g0b1xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32g0b1xx_flash.icf
+
+# For flash-jlink target
+JLINK_DEVICE = stm32g0b1re
diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c
new file mode 100644
index 000000000..67b0b3f1c
--- /dev/null
+++ b/hw/bsp/stm32g0/family.c
@@ -0,0 +1,197 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
+#include "stm32g0xx_hal.h"
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_UCPD1_2_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+#ifdef UART_DEV
+UART_HandleTypeDef UartHandle;
+#endif
+
+void board_init(void) {
+  HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS
+  board_clock_init();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_UCPD1_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  board_led_write(false);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+#ifdef UART_DEV
+  UART_CLK_EN();
+
+  // UART
+  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_PULLUP;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle = (UART_HandleTypeDef){
+    .Instance        = UART_DEV,
+    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+    .Init.WordLength = UART_WORDLENGTH_8B,
+    .Init.StopBits   = UART_STOPBITS_1,
+    .Init.Parity     = UART_PARITY_NONE,
+    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+    .Init.Mode       = UART_MODE_TX_RX,
+    .Init.OverSampling = UART_OVERSAMPLING_16,
+    .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT
+  };
+  HAL_UART_Init(&UartHandle);
+#endif
+
+  // USB Pins TODO double check USB clock and pin setup
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB_CLK_ENABLE();
+
+  /* Enable VDDUSB */
+  HAL_PWREx_EnableVddUSB();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  return len;
+#else
+  (void) buf;
+  (void) len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+  HAL_IncTick();
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+
+}
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
new file mode 100644
index 000000000..4da26f27e
--- /dev/null
+++ b/hw/bsp/stm32g0/family.cmake
@@ -0,0 +1,118 @@
+include_guard()
+
+set(ST_FAMILY g0)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32G0 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f interface/stlink.cfg -f target/stm32g0x.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+#    target_compile_options(${BOARD_TARGET} PUBLIC)
+#    target_compile_definitions(${BOARD_TARGET} PUBLIC)
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32G0)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  family_flash_stlink(${TARGET})
+  #family_flash_openocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk
new file mode 100644
index 000000000..95b8e537d
--- /dev/null
+++ b/hw/bsp/stm32g0/family.mk
@@ -0,0 +1,52 @@
+ST_FAMILY = g0
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32G0
+
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+
+# suppress warning caused by vendor mcu driver
+CFLAGS_GCC += -Wno-error=cast-align
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
+
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32g0/stm32g0xx_hal_conf.h b/hw/bsp/stm32g0/stm32g0xx_hal_conf.h
new file mode 100644
index 000000000..b2e335676
--- /dev/null
+++ b/hw/bsp/stm32g0/stm32g0xx_hal_conf.h
@@ -0,0 +1,351 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018-2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_CONF_H
+#define STM32G0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_EXTI_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_I2C_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+  * @brief This is the list of modules where register callback can be used
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS    0u
+#define USE_HAL_CEC_REGISTER_CALLBACKS    0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS   0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS   0u
+#define USE_HAL_DAC_REGISTER_CALLBACKS    0u
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS  0u
+#define USE_HAL_HCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS    0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS   0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS  0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS    0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS    0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS  0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS    0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS    0u
+#define USE_HAL_UART_REGISTER_CALLBACKS   0u
+#define USE_HAL_USART_REGISTER_CALLBACKS  0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS   0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    (8000000UL)         /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    (100UL)         /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    (16000000UL)            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                               The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+#endif
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  (32000UL)                /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    (32768UL)               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    (5000UL)      /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S1 peripheral
+  *        This value is used by the RCC HAL module to compute the I2S1 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_I2S1_CLOCK_VALUE)
+#define EXTERNAL_I2S1_CLOCK_VALUE    (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
+#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
+
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+/**
+  * @brief External clock source for I2S2 peripheral
+  *        This value is used by the RCC HAL module to compute the I2S2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_I2S2_CLOCK_VALUE)
+  #define EXTERNAL_I2S2_CLOCK_VALUE    48000U /*!< Value of the I2S2 External clock source in Hz*/
+#endif /* EXTERNAL_I2S2_CLOCK_VALUE */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    (3300UL)                                        /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME     1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include modules header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32g0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32g0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32g0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32g0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32g0xx_hal_adc.h"
+#include "stm32g0xx_hal_adc_ex.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+#include "stm32g0xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32g0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32g0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32g0xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32g0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32g0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32g0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32g0xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32g0xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32g0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32g0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32g0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32g0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32g0xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32g0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32g0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32g0xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32g0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32g0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32g0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32g0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32g0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32g0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32g0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32g0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for functions parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_CONF_H */
diff --git a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..891ea4b79
--- /dev/null
+++ b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32g4xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 200 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/b_g474e_dpow1/STM32G474RETx_FLASH.ld
new file mode 100644
index 000000000..25a104bc2
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/STM32G474RETx_FLASH.ld
@@ -0,0 +1,200 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32G474RETx Device from stm32g4 series
+**                      512Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 128K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x1000 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x1000 ;	/* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
new file mode 100644
index 000000000..7a276b20d
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32g474xx)
+set(JLINK_DEVICE stm32g474re)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32G474xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
new file mode 100644
index 000000000..d569783fc
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
@@ -0,0 +1,139 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 B-G474E-DPOW1 Discovery kit
+   url: https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// G474RE Nucleo does not has usb connection. We need to manually connect
+// - PA12 for D+, CN10.12
+// - PA11 for D-, CN10.14
+
+// LED
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   0
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOC
+#define UART_GPIO_AF          GPIO_AF7_USART3
+#define UART_TX_PIN           GPIO_PIN_10
+#define UART_RX_PIN           GPIO_PIN_11
+
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+// CPU Frequency (Core Clock) is 170 MHz
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  // Configure the main internal regulator output voltage
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+
+  /* Activate PLL with HSI as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 85;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV10;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  // Initializes the CPU, AHB and APB buses clocks
+  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
+                                     RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
+
+  //------------- HSI48 and CRS for USB -------------//
+  RCC_OscInitTypeDef osc_hsi48 = {0};
+  osc_hsi48.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  osc_hsi48.HSI48State = RCC_HSI48_ON;
+  osc_hsi48.PLL.PLLState = RCC_PLL_NONE;
+  HAL_RCC_OscConfig(&osc_hsi48);
+
+  /*Enable CRS Clock*/
+  RCC_CRSInitTypeDef RCC_CRSInitStruct= {0};
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+  /* Set the TRIM[5:0] to the default value */
+  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInit.UsbClockSelection    = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk
new file mode 100644
index 000000000..6266b3ccc
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk
@@ -0,0 +1,10 @@
+MCU_VARIANT = stm32g474xx
+
+CFLAGS += \
+	-DSTM32G474xx \
+
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
+
+# For flash-jlink target
+JLINK_DEVICE = stm32g474re
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/b_g474e_dpow1.ioc b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/b_g474e_dpow1.ioc
new file mode 100644
index 000000000..c15011896
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/b_g474e_dpow1.ioc
@@ -0,0 +1,194 @@
+#MicroXplorer Configuration settings - do not modify
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+Dma.Request0=UCPD1_RX
+Dma.Request1=UCPD1_TX
+Dma.RequestsNb=2
+Dma.UCPD1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
+Dma.UCPD1_RX.0.EventEnable=DISABLE
+Dma.UCPD1_RX.0.Instance=DMA1_Channel1
+Dma.UCPD1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UCPD1_RX.0.MemInc=DMA_MINC_ENABLE
+Dma.UCPD1_RX.0.Mode=DMA_NORMAL
+Dma.UCPD1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UCPD1_RX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.UCPD1_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.UCPD1_RX.0.Priority=DMA_PRIORITY_HIGH
+Dma.UCPD1_RX.0.RequestNumber=1
+Dma.UCPD1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.UCPD1_RX.0.SignalID=NONE
+Dma.UCPD1_RX.0.SyncEnable=DISABLE
+Dma.UCPD1_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.UCPD1_RX.0.SyncRequestNumber=1
+Dma.UCPD1_RX.0.SyncSignalID=NONE
+Dma.UCPD1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
+Dma.UCPD1_TX.1.EventEnable=DISABLE
+Dma.UCPD1_TX.1.Instance=DMA1_Channel2
+Dma.UCPD1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UCPD1_TX.1.MemInc=DMA_MINC_ENABLE
+Dma.UCPD1_TX.1.Mode=DMA_NORMAL
+Dma.UCPD1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UCPD1_TX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.UCPD1_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.UCPD1_TX.1.Priority=DMA_PRIORITY_HIGH
+Dma.UCPD1_TX.1.RequestNumber=1
+Dma.UCPD1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.UCPD1_TX.1.SignalID=NONE
+Dma.UCPD1_TX.1.SyncEnable=DISABLE
+Dma.UCPD1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.UCPD1_TX.1.SyncRequestNumber=1
+Dma.UCPD1_TX.1.SyncSignalID=NONE
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=true
+Mcu.CPN=STM32G474RET3
+Mcu.Family=STM32G4
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IP4=UCPD1
+Mcu.IP5=USART3
+Mcu.IPNb=6
+Mcu.Name=STM32G474R(B-C-E)Tx
+Mcu.Package=LQFP64
+Mcu.Pin0=PC10
+Mcu.Pin1=PC11
+Mcu.Pin2=PB4
+Mcu.Pin3=PB6
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.Pin5=VP_SYS_VS_DBSignals
+Mcu.PinsNb=6
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32G474RETx
+MxCube.Version=6.8.1
+MxDb.Version=DB.6.0.81
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
+NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
+PB4.Mode=Sink_AllSignals
+PB4.Signal=UCPD1_CC2
+PB6.Mode=Sink_AllSignals
+PB6.Signal=UCPD1_CC1
+PC10.GPIOParameters=GPIO_PuPd
+PC10.GPIO_PuPd=GPIO_PULLUP
+PC10.Mode=Asynchronous
+PC10.Signal=USART3_TX
+PC11.GPIOParameters=GPIO_PuPd
+PC11.GPIO_PuPd=GPIO_PULLUP
+PC11.Mode=Asynchronous
+PC11.Signal=USART3_RX
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32G474RETx
+ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.1
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=b_g474e_dpow1.ioc
+ProjectManager.ProjectName=b_g474e_dpow1
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=Makefile
+ProjectManager.ToolChainLocation=Src
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_UCPD1_Init-UCPD1-false-LL-true
+RCC.ADC12Freq_Value=150000000
+RCC.ADC345Freq_Value=150000000
+RCC.AHBFreq_Value=150000000
+RCC.APB1Freq_Value=150000000
+RCC.APB1TimFreq_Value=150000000
+RCC.APB2Freq_Value=150000000
+RCC.APB2TimFreq_Value=150000000
+RCC.CRSFreq_Value=48000000
+RCC.CortexFreq_Value=150000000
+RCC.EXTERNAL_CLOCK_VALUE=12288000
+RCC.FCLKCortexFreq_Value=150000000
+RCC.FDCANFreq_Value=150000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=150000000
+RCC.HRTIM1Freq_Value=150000000
+RCC.HSE_VALUE=24000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=150000000
+RCC.I2C2Freq_Value=150000000
+RCC.I2C3Freq_Value=150000000
+RCC.I2C4Freq_Value=150000000
+RCC.I2SFreq_Value=150000000
+RCC.IPParameters=ADC12Freq_Value,ADC345Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=150000000
+RCC.LPUART1Freq_Value=150000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLM=RCC_PLLM_DIV4
+RCC.PLLN=75
+RCC.PLLPoutputFreq_Value=150000000
+RCC.PLLQ=RCC_PLLQ_DIV4
+RCC.PLLQoutputFreq_Value=75000000
+RCC.PLLRCLKFreq_Value=150000000
+RCC.PWRFreq_Value=150000000
+RCC.QSPIFreq_Value=150000000
+RCC.RNGFreq_Value=75000000
+RCC.SAI1Freq_Value=150000000
+RCC.SYSCLKFreq_VALUE=150000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART4Freq_Value=150000000
+RCC.UART5Freq_Value=150000000
+RCC.USART1Freq_Value=150000000
+RCC.USART2Freq_Value=150000000
+RCC.USART3Freq_Value=150000000
+RCC.USBFreq_Value=75000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=300000000
+USART3.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
+USART3.BaudRate=115200
+USART3.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
+USART3.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
+USART3.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
+USART3.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
+USART3.Mode=MODE_TX_RX
+USART3.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+USART3.OverSampling=UART_OVERSAMPLING_16
+USART3.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
+USART3.Parity=PARITY_ODD
+USART3.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
+USART3.StopBits=STOPBITS_1
+USART3.SwapParam=ADVFEATURE_SWAP_DISABLE
+USART3.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
+USART3.VirtualMode-Asynchronous=VM_ASYNC
+USART3.WordLength=WORDLENGTH_8B
+VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals
+VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
index 935d97c87..25a104bc2 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
@@ -1,13 +1,13 @@
 /*
 ******************************************************************************
 **
-
 **  File        : LinkerScript.ld
 **
-**  Author		: Auto-generated by Ac6 System Workbench
+**  Author		: Auto-generated by STM32CubeIDE
 **
-**  Abstract    : Linker script for STM32G474RETx series
-**                512Kbytes FLASH and 160Kbytes RAM
+**  Abstract    : Linker script for STM32G474RETx Device from stm32g4 series
+**                      512Kbytes FLASH
+**                      128Kbytes RAM
 **
 **                Set heap size, stack size and stack location according
 **                to application requirements.
@@ -16,13 +16,13 @@
 **
 **  Target      : STMicroelectronics STM32
 **
-**  Distribution: The file is distributed “as is,” without any warranty
+**  Distribution: The file is distributed as is without any warranty
 **                of any kind.
 **
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
+** <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
 **
 ** Redistribution and use in source and binary forms, with or without modification,
 ** are permitted provided that the following conditions are met:
@@ -31,7 +31,7 @@
 **   2. Redistributions in binary form must reproduce the above copyright notice,
 **      this list of conditions and the following disclaimer in the documentation
 **      and/or other materials provided with the distribution.
-**   3. Neither the name of Ac6 nor the names of its contributors
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
 **      may be used to endorse or promote products derived from this software
 **      without specific prior written permission.
 **
@@ -52,24 +52,23 @@
 /* Entry Point */
 ENTRY(Reset_Handler)
 
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
+/* Memories definition */
 MEMORY
 {
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-CCMSRAM (xrw)      : ORIGIN = 0x10000000, LENGTH = 32K
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 128K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
 }
 
-/* Define output sections */
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x1000 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x1000 ;	/* required amount of stack */
+
+/* Sections */
 SECTIONS
 {
-  /* The startup code goes first into FLASH */
+  /* The startup code into "FLASH" Rom type memory */
   .isr_vector :
   {
     . = ALIGN(4);
@@ -77,7 +76,7 @@ SECTIONS
     . = ALIGN(4);
   } >FLASH
 
-  /* The program code and other data goes into FLASH */
+  /* The program code and other data into "FLASH" Rom type memory */
   .text :
   {
     . = ALIGN(4);
@@ -94,7 +93,7 @@ SECTIONS
     _etext = .;        /* define a global symbols at end of code */
   } >FLASH
 
-  /* Constant data goes into FLASH */
+  /* Constant data into "FLASH" Rom type memory */
   .rodata :
   {
     . = ALIGN(4);
@@ -103,39 +102,54 @@ SECTIONS
     . = ALIGN(4);
   } >FLASH
 
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
   .ARM : {
+    . = ALIGN(4);
     __exidx_start = .;
     *(.ARM.exidx*)
     __exidx_end = .;
+    . = ALIGN(4);
   } >FLASH
 
   .preinit_array     :
   {
+    . = ALIGN(4);
     PROVIDE_HIDDEN (__preinit_array_start = .);
     KEEP (*(.preinit_array*))
     PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
   } >FLASH
+
   .init_array :
   {
+    . = ALIGN(4);
     PROVIDE_HIDDEN (__init_array_start = .);
     KEEP (*(SORT(.init_array.*)))
     KEEP (*(.init_array*))
     PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
   } >FLASH
+
   .fini_array :
   {
+    . = ALIGN(4);
     PROVIDE_HIDDEN (__fini_array_start = .);
     KEEP (*(SORT(.fini_array.*)))
     KEEP (*(.fini_array*))
     PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
   } >FLASH
 
-  /* used by the startup to initialize data */
+  /* Used by the startup to initialize data */
   _sidata = LOADADDR(.data);
 
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -144,14 +158,14 @@ SECTIONS
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
+
   } >RAM AT> FLASH
 
-  
-  /* Uninitialized data section */
+  /* Uninitialized data section into "RAM" Ram type memory */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -163,7 +177,7 @@ SECTIONS
     __bss_end__ = _ebss;
   } >RAM
 
-  /* User_heap_stack section, used to check that there is enough RAM left */
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
   ._user_heap_stack :
   {
     . = ALIGN(8);
@@ -174,9 +188,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
-
-  /* Remove information from the standard libraries */
+  /* Remove information from the compiler libraries */
   /DISCARD/ :
   {
     libc.a ( * )
@@ -186,5 +198,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
new file mode 100644
index 000000000..11c76863f
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32g474xx)
+set(JLINK_DEVICE stm32g474re)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32G474xx
+    HSE_VALUE=24000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
index eab0bd5f0..cfef1c09f 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 G474 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-g474re.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -66,7 +71,7 @@ static inline void board_clock_init(void)
   // Configure the main internal regulator output voltage
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
 
-  // Initializes the CPU, AHB and APB busses clocks
+  // Initializes the CPU, AHB and APB buses clocks
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
   RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
@@ -79,7 +84,7 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.PLL.PLLR       = RCC_PLLR_DIV2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
-  // Initializes the CPU, AHB and APB busses clocks
+  // Initializes the CPU, AHB and APB buses clocks
   RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
index e41edd3b7..dc46af1d1 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
@@ -1,10 +1,11 @@
+MCU_VARIANT = stm32g474xx
+
 CFLAGS += \
 	-DSTM32G474xx \
 	-DHSE_VALUE=24000000
 
-LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g474xx.s
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32g474re
diff --git a/hw/bsp/stm32g4/boards/stm32g491nucleo/STM32G491RETX_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g491nucleo/STM32G491RETX_FLASH.ld
new file mode 100644
index 000000000..88ef666c7
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g491nucleo/STM32G491RETX_FLASH.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for NUCLEO-G491RE Board embedding STM32G491RETx Device from stm32g4 series
+**                      512KBytes FLASH
+**                      112KBytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 112K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32g4/boards/stm32g491nucleo/board.cmake b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.cmake
new file mode 100644
index 000000000..e37544499
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32g491xx)
+set(JLINK_DEVICE stm32g491re)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G491RETX_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32G491xx
+    HSE_VALUE=24000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h
new file mode 100644
index 000000000..be3d44645
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h
@@ -0,0 +1,109 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 G491 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-g491re.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// G474RE Nucleo does not has usb connection. We need to manually connect
+// - PA12 for D+, CN10.12
+// - PA11 for D-, CN10.14
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+// UART Enable for STLink VCOM
+#define UART_DEV              LPUART1
+#define UART_CLK_EN           __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF12_LPUART1
+#define UART_TX_PIN           GPIO_PIN_2
+#define UART_RX_PIN           GPIO_PIN_3
+
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  // Configure the main internal regulator output voltage
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+
+  // Initializes the CPU, AHB and APB buses clocks
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM       = RCC_PLLM_DIV6;
+  RCC_OscInitStruct.PLL.PLLN       = 85;
+  RCC_OscInitStruct.PLL.PLLP       = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ       = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR       = RCC_PLLR_DIV2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  // Initializes the CPU, AHB and APB buses clocks
+  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInit.UsbClockSelection    = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) ;
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32g4/boards/stm32g491nucleo/board.mk b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.mk
new file mode 100644
index 000000000..c0f876331
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = stm32g491xx
+
+CFLAGS += \
+	-DSTM32G491xx \
+	-DHSE_VALUE=24000000
+
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32G491RETX_FLASH.ld
+
+# For flash-jlink target
+JLINK_DEVICE = stm32g491re
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index a2312b0d8..49ef86db9 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,35 +24,45 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32g4xx_hal.h"
-#include "bsp/board.h"
+#include "stm32g4xx_ll_bus.h"
+
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_HP_IRQHandler(void)
-{
+void USB_HP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB_LP_IRQHandler(void)
-{
+void USB_LP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USBWakeUp_IRQHandler(void)
-{
+void USBWakeUp_IRQHandler(void) {
   tud_int_handler(0);
 }
 
+// USB PD
+void UCPD1_IRQHandler(void) {
+  tuc_int_handler(0);
+}
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
+#ifdef UART_DEV
 UART_HandleTypeDef UartHandle;
+#endif
 
-void board_init(void)
-{
+void board_init(void) {
+  HAL_Init();
   board_clock_init();
 
   // Enable All GPIOs clocks
@@ -63,8 +73,6 @@ void board_init(void)
   __HAL_RCC_GPIOE_CLK_ENABLE();
   __HAL_RCC_GPIOG_CLK_ENABLE();
 
-  UART_CLK_EN();
-
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -78,9 +86,10 @@ void board_init(void)
   NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
 
   // LED
+  memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct));
   GPIO_InitStruct.Pin = LED_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_PULLUP;
@@ -90,6 +99,7 @@ void board_init(void)
   board_led_write(false);
 
   // Button
+  memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct));
   GPIO_InitStruct.Pin = BUTTON_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
@@ -97,7 +107,10 @@ void board_init(void)
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
 #ifdef UART_DEV
+  UART_CLK_EN();
+
   // UART
+  memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct));
   GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
   GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
   GPIO_InitStruct.Pull      = GPIO_PULLUP;
@@ -120,6 +133,7 @@ void board_init(void)
 
   // USB Pins TODO double check USB clock and pin setup
   // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+  memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct));
   GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -129,60 +143,84 @@ void board_init(void)
   __HAL_RCC_USB_CLK_ENABLE();
 
   board_vbus_sense_init();
+
+#if 1
+  // USB PD
+  // Default CC1/CC2 is PB4/PB6
+
+  // Enable pwr for disabling dead battery feature in Power's CR3
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_RCC_CRC_CLK_ENABLE();
+  __HAL_RCC_UCPD1_CLK_ENABLE();
+
+  // Enable DMA for USB PD
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
+#endif
+
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
 #ifdef UART_DEV
   HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 #else
-  (void) buf; (void) len; (void) UartHandle;
+  (void) buf;
+  (void) len;
   return 0;
 #endif
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
new file mode 100644
index 000000000..5ec9926fe
--- /dev/null
+++ b/hw/bsp/stm32g4/family.cmake
@@ -0,0 +1,113 @@
+include_guard()
+
+set(ST_FAMILY g4)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32G4 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32G4)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
index 04222f3bb..0abd73532 100644
--- a/hw/bsp/stm32g4/family.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -1,27 +1,35 @@
 UF2_FAMILY_ID = 0x4c71240a
 ST_FAMILY = g4
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32G4
 
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=cast-align
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
 
 SRC_C += \
 	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	src/portable/st/typec/typec_stm32.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -29,6 +37,7 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
 INC += \
@@ -37,8 +46,12 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32g4/stm32g4xx_hal_conf.h b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
index ad5f7dbd4..632c4f0ac 100644
--- a/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
+++ b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef STM32G4xx_HAL_CONF_H
@@ -30,10 +30,10 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-  
-#define HAL_MODULE_ENABLED  
+
+#define HAL_MODULE_ENABLED
 
   /*#define HAL_ADC_MODULE_ENABLED   */
 /*#define HAL_COMP_MODULE_ENABLED   */
@@ -111,9 +111,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (24000000UL) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -124,7 +124,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
@@ -145,10 +145,10 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
 /*!< Value of the Internal Low Speed oscillator in Hz
 The real value may vary depending on the variations in voltage and temperature.*/
-#define LSI_VALUE  (32000UL)     /*!< LSI Typical Value in Hz*/    
+#define LSI_VALUE  (32000UL)     /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */
 /**
   * @brief External Low Speed oscillator (LSE) value.
@@ -156,7 +156,7 @@ The real value may vary depending on the variations in voltage and temperature.*
   */
 #if !defined  (LSE_VALUE)
 #define LSE_VALUE  (32768UL)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */     
+#endif /* LSE_VALUE */
 
 #if !defined  (LSE_STARTUP_TIMEOUT)
 #define LSE_STARTUP_TIMEOUT    (5000UL)   /*!< Time out for LSE start up, in ms */
@@ -177,10 +177,10 @@ The real value may vary depending on the variations in voltage and temperature.*
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 
 #define  VDD_VALUE                   (3300UL) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY           (0UL)    /*!< tick interrupt priority (lowest by default)  */            
+#define  TICK_INT_PRIORITY           (0UL)    /*!< tick interrupt priority (lowest by default)  */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              0U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@ The real value may vary depending on the variations in voltage and temperature.*
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
diff --git a/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..c621b48bb
--- /dev/null
+++ b/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32h5xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 200 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
+    defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY       ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY  2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY               ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY          ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake
new file mode 100644
index 000000000..1a44c3f1d
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake
@@ -0,0 +1,9 @@
+set(MCU_VARIANT stm32h503xx)
+set(JLINK_DEVICE stm32h503rb)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H503xx
+    HSE_VALUE=24000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h
new file mode 100644
index 000000000..c8b5e31f5
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h
@@ -0,0 +1,127 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2023, HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 H503 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-h503rb.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   0
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART3
+#define UART_CLK_EN           __USART3_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF13_USART3
+
+#define UART_TX_PIN           GPIO_PIN_3
+#define UART_RX_PIN           GPIO_PIN_4
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 12;
+  RCC_OscInitStruct.PLL.PLLN = 250;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                                |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                                |RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+
+  // Configure CRS clock source
+  __HAL_RCC_CRS_CLK_ENABLE();
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = 34;
+  RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
+  /* Select HSI48 as USB clock source */
+  RCC_PeriphCLKInitTypeDef usb_clk = {0 };
+  usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&usb_clk);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB_CLK_ENABLE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk
new file mode 100644
index 000000000..0292353ae
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk
@@ -0,0 +1,8 @@
+MCU_VARIANT = stm32h503xx
+
+CFLAGS += \
+	-DSTM32H503xx \
+	-DHSE_VALUE=24000000 \
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h503rb
diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake
new file mode 100644
index 000000000..0077bf235
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake
@@ -0,0 +1,9 @@
+set(MCU_VARIANT stm32h563xx)
+set(JLINK_DEVICE stm32h563zi)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H563xx
+    HSE_VALUE=8000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h
new file mode 100644
index 000000000..adc3d751a
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h
@@ -0,0 +1,135 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2023, HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 H563 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-h563zi.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOG
+#define LED_PIN               GPIO_PIN_4
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   0
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART1
+#define UART_CLK_EN           __USART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF7_USART1
+
+#define UART_TX_PIN           GPIO_PIN_9
+#define UART_RX_PIN           GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 4;
+  RCC_OscInitStruct.PLL.PLLN = 250;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure the programming delay
+  */
+  __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
+
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE;
+  PeriphClkInitStruct.PLL3.PLL3M = 1;
+  PeriphClkInitStruct.PLL3.PLL3N = 18;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 3;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+  PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1;
+  PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0;
+  PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk
new file mode 100644
index 000000000..a7ccbdf39
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk
@@ -0,0 +1,8 @@
+MCU_VARIANT = stm32h563xx
+
+CFLAGS += \
+	-DSTM32H563xx \
+	-DHSE_VALUE=8000000 \
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h563zi
diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc b/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc
new file mode 100644
index 000000000..b9b9605c1
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc
@@ -0,0 +1,410 @@
+#MicroXplorer Configuration settings - do not modify
+BOOTPATH.BootPathName=LEGACY
+BOOTPATH.IPParameters=BootPathName
+BOOTPATH.UserSelectedBootPath=LEGACY
+BSP_IP_NAME=NUCLEO-H563ZI
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+CORTEX_M33_NS.userName=CORTEX_M33
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+MMTAppRegionsCount=0
+MMTConfigApplied=false
+Mcu.CPN=STM32H563ZIT6
+Mcu.ContextProject=TrustZoneDisabled
+Mcu.Family=STM32H5
+Mcu.IP0=BOOTPATH
+Mcu.IP1=CORTEX_M33_NS
+Mcu.IP10=NUCLEO-H563ZI
+Mcu.IP2=DEBUG
+Mcu.IP3=ICACHE
+Mcu.IP4=MEMORYMAP
+Mcu.IP5=NVIC
+Mcu.IP6=PWR
+Mcu.IP7=RCC
+Mcu.IP8=SYS
+Mcu.IP9=USB
+Mcu.IPNb=11
+Mcu.Name=STM32H563ZITx
+Mcu.Package=LQFP144
+Mcu.Pin0=PE2
+Mcu.Pin1=PE3
+Mcu.Pin10=PC1
+Mcu.Pin11=PA1
+Mcu.Pin12=PA2
+Mcu.Pin13=PA4
+Mcu.Pin14=PA7
+Mcu.Pin15=PC4
+Mcu.Pin16=PC5
+Mcu.Pin17=PB0
+Mcu.Pin18=PB13
+Mcu.Pin19=PB14
+Mcu.Pin2=PE4
+Mcu.Pin20=PB15
+Mcu.Pin21=PD8
+Mcu.Pin22=PD9
+Mcu.Pin23=PG4
+Mcu.Pin24=PG7
+Mcu.Pin25=PA9
+Mcu.Pin26=PA11
+Mcu.Pin27=PA12
+Mcu.Pin28=PA13(JTMS/SWDIO)
+Mcu.Pin29=PA14(JTCK/SWCLK)
+Mcu.Pin3=PE5
+Mcu.Pin30=PA15(JTDI)
+Mcu.Pin31=PG11
+Mcu.Pin32=PG13
+Mcu.Pin33=PB3(JTDO/TRACESWO)
+Mcu.Pin34=PB6
+Mcu.Pin35=PB7
+Mcu.Pin36=VP_ICACHE_VS_ICACHE
+Mcu.Pin37=VP_PWR_VS_SECSignals
+Mcu.Pin38=VP_PWR_VS_LPOM
+Mcu.Pin39=VP_PWR_VS_DBSignals
+Mcu.Pin4=PE6
+Mcu.Pin40=VP_SYS_VS_Systick
+Mcu.Pin41=VP_BOOTPATH_VS_BOOTPATH
+Mcu.Pin42=VP_MEMORYMAP_VS_MEMORYMAP
+Mcu.Pin5=PC13
+Mcu.Pin6=PC14-OSC32_IN(OSC32_IN)
+Mcu.Pin7=PC15-OSC32_OUT(OSC32_OUT)
+Mcu.Pin8=PF4
+Mcu.Pin9=PH0-OSC_IN(PH0)
+Mcu.PinsNb=43
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H563ZITx
+MxCube.Version=6.12.1
+MxDb.Version=DB.6.0.121
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.EXTI13_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA1.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PA1.GPIO_Label=RMII_REF_CLK
+PA1.GPIO_Mode=GPIO_MODE_AF_PP
+PA1.GPIO_PuPd=GPIO_NOPULL
+PA1.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA1.Locked=true
+PA1.Signal=ETH_REF_CLK
+PA11.GPIOParameters=GPIO_Label
+PA11.GPIO_Label=USB_FS_N
+PA11.Locked=true
+PA11.Mode=Device
+PA11.Signal=USB_DM
+PA12.GPIOParameters=GPIO_Label
+PA12.GPIO_Label=USB_FS_P
+PA12.Locked=true
+PA12.Mode=Device
+PA12.Signal=USB_DP
+PA13(JTMS/SWDIO).GPIOParameters=GPIO_Label
+PA13(JTMS/SWDIO).GPIO_Label=SWDIO
+PA13(JTMS/SWDIO).Locked=true
+PA13(JTMS/SWDIO).Mode=Trace_Synchro_4bits_JTAG
+PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
+PA14(JTCK/SWCLK).GPIOParameters=GPIO_Label
+PA14(JTCK/SWCLK).GPIO_Label=SWCLK
+PA14(JTCK/SWCLK).Locked=true
+PA14(JTCK/SWCLK).Mode=Trace_Synchro_4bits_JTAG
+PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
+PA15(JTDI).GPIOParameters=GPIO_Label
+PA15(JTDI).GPIO_Label=T_JTDI
+PA15(JTDI).Locked=true
+PA15(JTDI).Mode=Trace_Synchro_4bits_JTAG
+PA15(JTDI).Signal=DEBUG_JTDI
+PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PA2.GPIO_Label=RMII_MDIO
+PA2.GPIO_Mode=GPIO_MODE_AF_PP
+PA2.GPIO_PuPd=GPIO_NOPULL
+PA2.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA2.Locked=true
+PA2.Signal=ETH_MDIO
+PA4.GPIOParameters=GPIO_Label
+PA4.GPIO_Label=VBUS_SENSE
+PA4.Locked=true
+PA4.Signal=ADCx_INP18
+PA7.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PA7.GPIO_Label=RMII_CRS_DV
+PA7.GPIO_Mode=GPIO_MODE_AF_PP
+PA7.GPIO_PuPd=GPIO_NOPULL
+PA7.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA7.Locked=true
+PA7.Signal=ETH_CRS_DV
+PA9.GPIOParameters=GPIO_Label
+PA9.GPIO_Label=UCDP_DBn
+PA9.Locked=true
+PA9.Signal=UCPD1_DB1
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PB13.GPIOParameters=GPIO_Label
+PB13.GPIO_Label=UCPD_CC1
+PB13.Locked=true
+PB13.Signal=UCPD1_CC1
+PB14.GPIOParameters=GPIO_Label
+PB14.GPIO_Label=UCPD_CC2
+PB14.Locked=true
+PB14.Signal=UCPD1_CC2
+PB15.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PB15.GPIO_Label=RMII_TXD1
+PB15.GPIO_Mode=GPIO_MODE_AF_PP
+PB15.GPIO_PuPd=GPIO_NOPULL
+PB15.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PB15.Locked=true
+PB15.Signal=ETH_TXD1
+PB3(JTDO/TRACESWO).GPIOParameters=GPIO_Label
+PB3(JTDO/TRACESWO).GPIO_Label=SWO
+PB3(JTDO/TRACESWO).Locked=true
+PB3(JTDO/TRACESWO).Mode=Trace_Synchro_4bits_JTAG
+PB3(JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO
+PB6.GPIOParameters=GPIO_Label
+PB6.GPIO_Label=ARD_D1_TX
+PB6.Locked=true
+PB6.Signal=LPUART1_TX
+PB7.GPIOParameters=GPIO_Label
+PB7.GPIO_Label=ARD_D0_RX
+PB7.Locked=true
+PB7.Signal=LPUART1_RX
+PC1.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PC1.GPIO_Label=RMII_MDC
+PC1.GPIO_Mode=GPIO_MODE_AF_PP
+PC1.GPIO_PuPd=GPIO_NOPULL
+PC1.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PC1.Locked=true
+PC1.Signal=ETH_MDC
+PC13.Locked=true
+PC13.Signal=GPXTI13
+PC14-OSC32_IN(OSC32_IN).Locked=true
+PC14-OSC32_IN(OSC32_IN).Mode=LSE-External-Oscillator
+PC14-OSC32_IN(OSC32_IN).Signal=RCC_OSC32_IN
+PC15-OSC32_OUT(OSC32_OUT).Locked=true
+PC15-OSC32_OUT(OSC32_OUT).Mode=LSE-External-Oscillator
+PC15-OSC32_OUT(OSC32_OUT).Signal=RCC_OSC32_OUT
+PC4.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PC4.GPIO_Label=RMII_RXD0
+PC4.GPIO_Mode=GPIO_MODE_AF_PP
+PC4.GPIO_PuPd=GPIO_NOPULL
+PC4.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PC4.Locked=true
+PC4.Signal=ETH_RXD0
+PC5.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PC5.GPIO_Label=RMII_RXD1
+PC5.GPIO_Mode=GPIO_MODE_AF_PP
+PC5.GPIO_PuPd=GPIO_NOPULL
+PC5.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PC5.Locked=true
+PC5.Signal=ETH_RXD1
+PD8.Locked=true
+PD8.Signal=USART3_TX
+PD9.Locked=true
+PD9.Signal=USART3_RX
+PE2.GPIOParameters=GPIO_Label
+PE2.GPIO_Label=TRACE_CK
+PE2.Locked=true
+PE2.Mode=Trace_Synchro_4bits_JTAG
+PE2.Signal=DEBUG_TRACECLK
+PE3.GPIOParameters=GPIO_Label
+PE3.GPIO_Label=TRACE_D0
+PE3.Locked=true
+PE3.Mode=Trace_Synchro_4bits_JTAG
+PE3.Signal=DEBUG_TRACED0
+PE4.GPIOParameters=GPIO_Label
+PE4.GPIO_Label=TRACE_D1
+PE4.Locked=true
+PE4.Mode=Trace_Synchro_4bits_JTAG
+PE4.Signal=DEBUG_TRACED1
+PE5.GPIOParameters=GPIO_Label
+PE5.GPIO_Label=TRACE_D2
+PE5.Locked=true
+PE5.Mode=Trace_Synchro_4bits_JTAG
+PE5.Signal=DEBUG_TRACED2
+PE6.GPIOParameters=GPIO_Label
+PE6.GPIO_Label=TRACE_D3
+PE6.Locked=true
+PE6.Mode=Trace_Synchro_4bits_JTAG
+PE6.Signal=DEBUG_TRACED3
+PF4.Locked=true
+PF4.Signal=GPIO_Output
+PG11.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PG11.GPIO_Label=RMII_TXT_EN
+PG11.GPIO_Mode=GPIO_MODE_AF_PP
+PG11.GPIO_PuPd=GPIO_NOPULL
+PG11.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PG11.Locked=true
+PG11.Signal=ETH_TX_EN
+PG13.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PG13.GPIO_Label=RMI_TXD0
+PG13.GPIO_Mode=GPIO_MODE_AF_PP
+PG13.GPIO_PuPd=GPIO_NOPULL
+PG13.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PG13.Locked=true
+PG13.Signal=ETH_TXD0
+PG4.Locked=true
+PG4.Signal=GPIO_Output
+PG7.GPIOParameters=GPIO_Label
+PG7.GPIO_Label=UCPD_FLT
+PG7.Locked=true
+PG7.Signal=GPXTI7
+PH0-OSC_IN(PH0).GPIOParameters=GPIO_Label
+PH0-OSC_IN(PH0).GPIO_Label=STLK_MCO
+PH0-OSC_IN(PH0).Locked=true
+PH0-OSC_IN(PH0).Mode=HSE-External-Clock-Source
+PH0-OSC_IN(PH0).Signal=RCC_OSC_IN
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H563ZITx
+ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.3.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=stm32h563nucleo.ioc
+ProjectManager.ProjectName=stm32h563nucleo
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=Makefile
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USB_PCD_Init-USB-false-HAL-true,4-MX_ICACHE_Init-ICACHE-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
+RCC.ADCFreq_Value=250000000
+RCC.AHBFreq_Value=250000000
+RCC.APB1Freq_Value=250000000
+RCC.APB1TimFreq_Value=250000000
+RCC.APB2Freq_Value=250000000
+RCC.APB2TimFreq_Value=250000000
+RCC.APB3Freq_Value=250000000
+RCC.CECFreq_Value=32000
+RCC.CKPERFreq_Value=64000000
+RCC.CRSFreq_Value=48000000
+RCC.CSI_VALUE=4000000
+RCC.CortexFreq_Value=250000000
+RCC.DACFreq_Value=32768
+RCC.EPOD_VALUE=8000000
+RCC.ETHFreq_Value=250000000
+RCC.FCLKCortexFreq_Value=250000000
+RCC.FDCANFreq_Value=8000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=250000000
+RCC.HSE_VALUE=8000000
+RCC.HSI48_VALUE=48000000
+RCC.HSIDiv=RCC_HSI_DIV1
+RCC.HSI_VALUE=64000000
+RCC.I2C1Freq_Value=250000000
+RCC.I2C2Freq_Value=250000000
+RCC.I2C3Freq_Value=250000000
+RCC.I2C4Freq_Value=250000000
+RCC.I3C1Freq_Value=250000000
+RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CECFreq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,ETHFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPTIM6Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL2Source,PLL3FRACN,PLL3N,PLL3PoutputFreq_Value,PLL3Q,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLL3Source,PLLFRACN,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART12Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,UCPD1outputFreq_Value,USART10Freq_Value,USART11Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBCLockSelection,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value
+RCC.LPTIM1Freq_Value=250000000
+RCC.LPTIM2Freq_Value=250000000
+RCC.LPTIM3Freq_Value=250000000
+RCC.LPTIM4Freq_Value=250000000
+RCC.LPTIM5Freq_Value=250000000
+RCC.LPTIM6Freq_Value=250000000
+RCC.LPUART1Freq_Value=250000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSIRC_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=250000000
+RCC.OCTOSPIMFreq_Value=250000000
+RCC.PLL2PoutputFreq_Value=516000000
+RCC.PLL2QoutputFreq_Value=516000000
+RCC.PLL2RoutputFreq_Value=516000000
+RCC.PLL2Source=RCC_PLL2_SOURCE_HSE
+RCC.PLL3FRACN=0
+RCC.PLL3N=18
+RCC.PLL3PoutputFreq_Value=72000000
+RCC.PLL3Q=3
+RCC.PLL3QoutputFreq_Value=48000000
+RCC.PLL3RoutputFreq_Value=72000000
+RCC.PLL3Source=RCC_PLL3_SOURCE_HSE
+RCC.PLLFRACN=0
+RCC.PLLM=4
+RCC.PLLN=250
+RCC.PLLPoutputFreq_Value=250000000
+RCC.PLLQoutputFreq_Value=250000000
+RCC.PLLSourceVirtual=RCC_PLL1_SOURCE_HSE
+RCC.PWRFreq_Value=250000000
+RCC.RNGFreq_Value=48000000
+RCC.SAI1Freq_Value=516000000
+RCC.SAI2Freq_Value=516000000
+RCC.SDMMC1Freq_Value=250000000
+RCC.SDMMC2Freq_Value=250000000
+RCC.SPI1Freq_Value=250000000
+RCC.SPI2Freq_Value=250000000
+RCC.SPI3Freq_Value=250000000
+RCC.SPI4Freq_Value=250000000
+RCC.SPI5Freq_Value=250000000
+RCC.SPI6Freq_Value=250000000
+RCC.SYSCLKFreq_VALUE=250000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART12Freq_Value=250000000
+RCC.UART4Freq_Value=250000000
+RCC.UART5Freq_Value=250000000
+RCC.UART7Freq_Value=250000000
+RCC.UART8Freq_Value=250000000
+RCC.UART9Freq_Value=250000000
+RCC.UCPD1outputFreq_Value=16000000
+RCC.USART10Freq_Value=250000000
+RCC.USART11Freq_Value=250000000
+RCC.USART1Freq_Value=250000000
+RCC.USART2Freq_Value=250000000
+RCC.USART3Freq_Value=250000000
+RCC.USART6Freq_Value=250000000
+RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3Q
+RCC.USBFreq_Value=48000000
+RCC.VCOInput2Freq_Value=8000000
+RCC.VCOInput3Freq_Value=8000000
+RCC.VCOInputFreq_Value=2000000
+RCC.VCOOutputFreq_Value=500000000
+RCC.VCOPLL2OutputFreq_Value=1032000000
+RCC.VCOPLL3OutputFreq_Value=144000000
+SH.ADCx_INP18.0=ADC1_INP18
+SH.ADCx_INP18.ConfNb=1
+SH.GPXTI13.0=GPIO_EXTI13
+SH.GPXTI13.ConfNb=1
+SH.GPXTI7.0=GPIO_EXTI7
+SH.GPXTI7.ConfNb=1
+USB.IPParameters=VirtualMode
+USB.VirtualMode=Device_Only
+VP_BOOTPATH_VS_BOOTPATH.Mode=BP_Activate
+VP_BOOTPATH_VS_BOOTPATH.Signal=BOOTPATH_VS_BOOTPATH
+VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache
+VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE
+VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
+VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
+VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals
+VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals
+VP_PWR_VS_LPOM.Mode=PowerOptimisation
+VP_PWR_VS_LPOM.Signal=PWR_VS_LPOM
+VP_PWR_VS_SECSignals.Mode=Security/Privilege
+VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=NUCLEO-H563ZI
+boardIOC=true
diff --git a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.cmake b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.cmake
new file mode 100644
index 000000000..92d6d98f0
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32h573xx)
+set(JLINK_DEVICE stm32h573ii)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H573xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h
new file mode 100644
index 000000000..d75114397
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h
@@ -0,0 +1,120 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2023, HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 H573i Discovery
+   url: https://www.st.com/en/evaluation-tools/stm32h573i-dk.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOI
+#define LED_PIN               GPIO_PIN_9
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART1
+#define UART_CLK_EN           __USART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF7_USART1
+
+#define UART_TX_PIN           GPIO_PIN_9
+#define UART_RX_PIN           GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  Freq 250MHZ */
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 100;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 10;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /** Initializes the CPU, AHB and APB buses clocks */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+
+  // Configure CRS clock source
+  __HAL_RCC_CRS_CLK_ENABLE();
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = 34;
+  RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
+  /* Select HSI48 as USB clock source */
+  RCC_PeriphCLKInitTypeDef usb_clk = {0 };
+  usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&usb_clk);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB_CLK_ENABLE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.mk b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.mk
new file mode 100644
index 000000000..b24acf89f
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = stm32h573xx
+
+CFLAGS += \
+	-DSTM32H573xx
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h573ii
diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c
new file mode 100644
index 000000000..26ba34ac3
--- /dev/null
+++ b/hw/bsp/stm32h5/family.c
@@ -0,0 +1,223 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wundef"
+#endif
+
+#include "stm32h5xx_hal.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+
+TU_ATTR_UNUSED static void Error_Handler(void) {
+}
+
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_DRD_FS_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+#ifdef UART_DEV
+UART_HandleTypeDef UartHandle;
+#endif
+
+void board_init(void) {
+  HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS
+  SystemClock_Config(); // implemented in board.h
+  SystemCoreClockUpdate();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+
+  #ifdef __HAL_RCC_GPIOE_CLK_ENABLE
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  #endif
+  #ifdef __HAL_RCC_GPIOG_CLK_ENABLE
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  #endif
+  #ifdef __HAL_RCC_GPIOI_CLK_ENABLE
+  __HAL_RCC_GPIOI_CLK_ENABLE();
+  #endif
+
+  #if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+  #elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_DRD_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
+
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  board_led_write(false);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+  #ifdef UART_DEV
+  UART_CLK_EN();
+
+  // UART
+  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle = (UART_HandleTypeDef) {
+      .Instance        = UART_DEV,
+      .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+      .Init.WordLength = UART_WORDLENGTH_8B,
+      .Init.StopBits   = UART_STOPBITS_1,
+      .Init.Parity     = UART_PARITY_NONE,
+      .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+      .Init.Mode       = UART_MODE_TX_RX,
+      .Init.OverSampling = UART_OVERSAMPLING_16,
+      .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT
+  };
+  HAL_UART_Init(&UartHandle);
+  #endif
+
+  // USB Pins TODO double check USB clock and pin setup
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB_CLK_ENABLE();
+
+  /* Enable VDDUSB */
+  #if defined (PWR_USBSCR_USB33DEN)
+  HAL_PWREx_EnableVddUSB();
+  #endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t* stm32_uuid = (volatile uint32_t*) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  #ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t*) (uintptr_t) buf, len, 0xffff);
+  return len;
+  #else
+  (void) buf;
+  (void) len;
+  return 0;
+  #endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+  HAL_IncTick();
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+
+}
diff --git a/hw/bsp/stm32h5/family.cmake b/hw/bsp/stm32h5/family.cmake
new file mode 100644
index 000000000..1df6bcb90
--- /dev/null
+++ b/hw/bsp/stm32h5/family.cmake
@@ -0,0 +1,117 @@
+include_guard()
+
+set(ST_FAMILY h5)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32H5 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  string(REPLACE "stm32h" "STM32H" MCU_VARIANT_UPPER ${MCU_VARIANT})
+  set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT_UPPER}_FLASH.ld)
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32H5)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32h5/family.mk b/hw/bsp/stm32h5/family.mk
new file mode 100644
index 000000000..792edb2bb
--- /dev/null
+++ b/hw/bsp/stm32h5/family.mk
@@ -0,0 +1,66 @@
+ST_FAMILY = h5
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
+
+MCU_VARIANT_UPPER = $(subst stm32h,STM32H,$(MCU_VARIANT))
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32H5
+
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+
+# suppress warning caused by vendor mcu driver
+CFLAGS_GCC += \
+  -Wno-error=cast-align \
+  -Wno-error=undef \
+  -Wno-error=unused-parameter \
+
+CFLAGS_CLANG += \
+  -Wno-error=parentheses-equality
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
+
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
+LD_FILE_GCC = $(FAMILY_PATH)/linker/$(MCU_VARIANT_UPPER)_FLASH.ld
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32h5/linker/STM32H503xx_FLASH.ld b/hw/bsp/stm32h5/linker/STM32H503xx_FLASH.ld
new file mode 100644
index 000000000..abf618233
--- /dev/null
+++ b/hw/bsp/stm32h5/linker/STM32H503xx_FLASH.ld
@@ -0,0 +1,188 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H503xx Device from STM32H5 series
+ **                      128Kbytes FLASH
+ **                      32Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 32K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 128K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h5/linker/STM32H523xx_FLASH.ld b/hw/bsp/stm32h5/linker/STM32H523xx_FLASH.ld
new file mode 100644
index 000000000..b799892c6
--- /dev/null
+++ b/hw/bsp/stm32h5/linker/STM32H523xx_FLASH.ld
@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H523xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 272K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h5/linker/STM32H533xx_FLASH.ld b/hw/bsp/stm32h5/linker/STM32H533xx_FLASH.ld
new file mode 100644
index 000000000..dece7a003
--- /dev/null
+++ b/hw/bsp/stm32h5/linker/STM32H533xx_FLASH.ld
@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H533xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 272K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h5/linker/STM32H562xx_FLASH.ld b/hw/bsp/stm32h5/linker/STM32H562xx_FLASH.ld
new file mode 100644
index 000000000..aee2774a4
--- /dev/null
+++ b/hw/bsp/stm32h5/linker/STM32H562xx_FLASH.ld
@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H562xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 640K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h5/linker/STM32H563xx_FLASH.ld b/hw/bsp/stm32h5/linker/STM32H563xx_FLASH.ld
new file mode 100644
index 000000000..129ed5170
--- /dev/null
+++ b/hw/bsp/stm32h5/linker/STM32H563xx_FLASH.ld
@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H563xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 640K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h5/linker/STM32H573xx_FLASH.ld b/hw/bsp/stm32h5/linker/STM32H573xx_FLASH.ld
new file mode 100644
index 000000000..eb98f3163
--- /dev/null
+++ b/hw/bsp/stm32h5/linker/STM32H573xx_FLASH.ld
@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H573xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 640K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h5/stm32h5xx_hal_conf.h b/hw/bsp/stm32h5/stm32h5xx_hal_conf.h
new file mode 100644
index 000000000..d017bb06b
--- /dev/null
+++ b/hw/bsp/stm32h5/stm32h5xx_hal_conf.h
@@ -0,0 +1,355 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h5xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018-2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32h5xx_HAL_CONF_H
+#define STM32h5xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_EXTI_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_I2C_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+  * @brief This is the list of modules where register callback can be used
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS    0u
+#define USE_HAL_CEC_REGISTER_CALLBACKS    0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS   0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS   0u
+#define USE_HAL_DAC_REGISTER_CALLBACKS    0u
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS  0u
+#define USE_HAL_HCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS    0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS   0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS  0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS    0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS    0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS  0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS    0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS    0u
+#define USE_HAL_UART_REGISTER_CALLBACKS   0u
+#define USE_HAL_USART_REGISTER_CALLBACKS  0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS   0u
+
+
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Core Speed oscillator (CSI) default value.
+  *        This value is the default CSI range value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+#define CSI_VALUE              4000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE              64000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE             48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                                  The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  32000UL    /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+
+#if !defined  (LSI_STARTUP_TIME)
+#define LSI_STARTUP_TIME          130UL      /*!< Time out for LSI start up, in ms */
+#endif /* LSI_STARTUP_TIME */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  32768UL    /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000UL     /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SPI/SAI peripheral
+  *        This value is used by the SPI/SAI HAL module to compute the SPI/SAI clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000UL /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ############################################ System Configuration ################################################ */
+
+/**
+  * @brief This is the HAL system configuration section
+  */
+
+#define  VDD_VALUE                  3300UL /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY          (15UL)  /*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                   0U
+#define  PREFETCH_ENABLE            0U               /*!< Enable prefetch */
+
+
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME     1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include modules header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32h5xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32h5xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32h5xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32h5xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32h5xx_hal_adc.h"
+#include "stm32h5xx_hal_adc_ex.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+#include "stm32h5xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32h5xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32h5xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32h5xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32h5xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32h5xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32h5xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32h5xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32h5xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32h5xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32h5xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32h5xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32h5xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h5xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32h5xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32h5xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32h5xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32h5xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32h5xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32h5xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32h5xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32h5xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32h5xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32h5xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32h5xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for functions parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32h5xx_HAL_CONF_H */
diff --git a/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..8bbeefcc7
--- /dev/null
+++ b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32h7xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.cmake b/hw/bsp/stm32h7/boards/daisyseed/board.cmake
new file mode 100644
index 000000000..ff22b3e22
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT stm32h750xx)
+set(JLINK_DEVICE stm32h750ibk6_m7)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32h750ibkx_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H750xx
+    HSE_VALUE=16000000
+    CORE_CM7
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.h b/hw/bsp/stm32h7/boards/daisyseed/board.h
new file mode 100644
index 000000000..300ecb8b2
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.h
@@ -0,0 +1,162 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Daisy Seed
+   url: https://electro-smith.com/products/daisy-seed
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// UART
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     0
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  }
+};
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void) {
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+
+  /*!< Supply configuration update enable */
+  /* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */
+//  HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+  /* The voltage scaling allows optimizing the power consumption when the
+     device is clocked below the maximum system frequency, to update the
+     voltage scaling value regarding system frequency refer to product
+     datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+  /* PLL1 for System Clock */
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 160;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* PLL3 for USB Clock */
+  PeriphClkInitStruct.PLL3.PLL3M = 25;
+  PeriphClkInitStruct.PLL3.PLL3N = 336;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 7;
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure  bus clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
+  RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
+
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  /*activate CSI clock mondatory for I/O Compensation Cell*/
+  __HAL_RCC_CSI_ENABLE() ;
+
+  /* Enable SYSCFG clock mondatory for I/O Compensation Cell */
+  __HAL_RCC_SYSCFG_CLK_ENABLE() ;
+
+  /* Enables the I/O Compensation Cell */
+  HAL_EnableCompensationCell();
+}
+
+static inline void board_init2(void) {
+  // For this board does nothing
+}
+
+void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport; (void) state;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.mk b/hw/bsp/stm32h7/boards/daisyseed/board.mk
new file mode 100644
index 000000000..bb254cfc2
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.mk
@@ -0,0 +1,10 @@
+MCU_VARIANT = stm32h750xx
+CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=16000000
+
+LD_FILE_GCC = $(BOARD_PATH)/stm32h750ibkx_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h750ibk6_m7
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld
similarity index 85%
rename from hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
rename to hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld
index 73d2dedb2..e2bde9338 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
+++ b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld
@@ -6,7 +6,7 @@
 **  Author      : STM32CubeIDE
 **
 **  Abstract    : Linker script for STM32H7 series
-**                2048Kbytes FLASH and 192Kbytes RAM
+**                128Kbytes FLASH and 1056Kbytes RAM
 **
 **                Set heap size, stack size and stack location according
 **                to application requirements.
@@ -21,13 +21,12 @@
 *****************************************************************************
 ** @attention
 **
-** Copyright (c) 2019 STMicroelectronics.
+** Copyright (c) 2022 STMicroelectronics.
 ** All rights reserved.
 **
-** This software component is licensed by ST under BSD 3-Clause license,
-** the "License"; You may not use this file except in compliance with the
-** License. You may obtain a copy of the License at:
-**                        opensource.org/licenses/BSD-3-Clause
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
 **
 ****************************************************************************
 */
@@ -35,23 +34,23 @@
 /* Entry Point */
 ENTRY(Reset_Handler)
 
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x2000 ;  /* required amount of heap  */
-_Min_Stack_Size = 0x2000 ; /* required amount of stack */
-
 /* Specify the memory areas */
 MEMORY
 {
-  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 2048K
-  RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 128K
+  DTCMRAM (xrw)  : ORIGIN = 0x20000000, LENGTH = 128K
   RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH = 512K
   RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
   RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
   ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
 }
 
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x2000 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x4000 ; /* required amount of stack */
+
 /* Define output sections */
 SECTIONS
 {
@@ -102,6 +101,7 @@ SECTIONS
     KEEP (*(.preinit_array*))
     PROVIDE_HIDDEN (__preinit_array_end = .);
   } >FLASH
+
   .init_array :
   {
     PROVIDE_HIDDEN (__init_array_start = .);
@@ -109,6 +109,7 @@ SECTIONS
     KEEP (*(.init_array*))
     PROVIDE_HIDDEN (__init_array_end = .);
   } >FLASH
+
   .fini_array :
   {
     PROVIDE_HIDDEN (__fini_array_start = .);
@@ -132,13 +133,13 @@ SECTIONS
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
+  } >RAM_D1 AT> FLASH
 
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -148,7 +149,7 @@ SECTIONS
     . = ALIGN(4);
     _ebss = .;         /* define a global symbol at bss end */
     __bss_end__ = _ebss;
-  } >RAM
+  } >RAM_D1
 
   /* User_heap_stack section, used to check that there is enough RAM left */
   ._user_heap_stack :
@@ -159,7 +160,7 @@ SECTIONS
     . = . + _Min_Heap_Size;
     . = . + _Min_Stack_Size;
     . = ALIGN(8);
-  } >RAM
+  } >RAM_D1
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -171,5 +172,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_ram.ld b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_ram.ld
new file mode 100644
index 000000000..03d9aaba3
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_ram.ld
@@ -0,0 +1,173 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld (debug in RAM dedicated)
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32H7 series
+**                128Kbytes RAM_EXEC and 544Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Specify the memory areas */
+MEMORY
+{
+  RAM_EXEC (xrw)  : ORIGIN = 0x24000000, LENGTH = 128K
+  DTCMRAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 128K
+  RAM_D2 (xrw)    : ORIGIN = 0x30000000, LENGTH = 288K
+  RAM_D3 (xrw)    : ORIGIN = 0x38000000, LENGTH = 64K
+  ITCMRAM (xrw)   : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x2000 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x4000 ; /* required amount of stack */
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into RAM_EXEC */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM_EXEC
+
+  /* The program code and other data goes into RAM_EXEC */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM_EXEC
+
+  /* Constant data goes into RAM_EXEC */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM_EXEC
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >RAM_EXEC
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >RAM_EXEC
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >RAM_EXEC
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >RAM_EXEC
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >DTCMRAM AT> RAM_EXEC
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >DTCMRAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >DTCMRAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake
new file mode 100644
index 000000000..a6f0a5c45
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32h723xx)
+set(JLINK_DEVICE stm32h723zg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H723xx
+    HSE_VALUE=8000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
new file mode 100644
index 000000000..f623149bd
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
@@ -0,0 +1,163 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 H723 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-h723zg.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     0
+
+// STM32F723 has only one USB HS peripheral
+// Nucleo board does not have ULPI so USB will operate in FS mode only
+// For the rest of the synopsys driver it is FS device however there
+// is only USB_OTG_HS defined. Here are required conversions to
+// make peripheral FS.
+#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE __HAL_RCC_USB1_OTG_HS_CLK_ENABLE
+#define GPIO_AF10_OTG2_HS               GPIO_AF10_OTG1_HS
+#define USB_OTG_FS                      USB_OTG_HS
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // VBUS0 EN
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  }
+};
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+
+  /* The PWR block is always enabled on the H7 series- there is no clock
+     enable. For now, use the default VOS3 scale mode (lowest) and limit clock
+     frequencies to avoid potential current draw problems from bus
+     power when using the max clock speeds throughout the chip. */
+
+  /* Enable HSE Oscillator and activate PLL1 with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
+  RCC_OscInitStruct.PLL.PLLN = 336;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  RCC_OscInitStruct.PLL.PLLR = 2; /* Unused */
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \
+    RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \
+    RCC_CLOCKTYPE_D3PCLK1);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
+
+  /* Unlike on the STM32F4 family, it appears the maximum APB frequencies are
+     device-dependent- 120 MHz for this board according to Figure 2 of
+     the datasheet. Dividing by half will be safe for now. */
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+  /* 4 wait states required for 168MHz and VOS3. */
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  /* Like on F4, on H7, USB's actual peripheral clock and bus clock are
+     separate. However, the main system PLL (PLL1) doesn't have a direct
+     connection to the USB peripheral clock to generate 48 MHz, so we do this
+     dance. This will connect PLL1's Q output to the USB peripheral clock. */
+  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
+
+  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
+}
+
+static inline void board_init2(void) {
+  // For this board does nothing
+}
+
+void board_vbus_set(uint8_t rhport, bool state) {
+  if (rhport == 0) {
+    board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+  }
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
new file mode 100644
index 000000000..c1a98a025
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
@@ -0,0 +1,10 @@
+MCU_VARIANT = stm32h723xx
+CFLAGS += -DSTM32H723xx -DHSE_VALUE=8000000
+
+LD_FILE_GCC = $(FAMILY_PATH)/linker/${MCU_VARIANT}_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h723zg
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake
new file mode 100644
index 000000000..02c6bf5fa
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake
@@ -0,0 +1,29 @@
+set(MCU_VARIANT stm32h743xx)
+set(JLINK_DEVICE stm32h743xi)
+#set(JLINK_OPTION "-USB jtrace")
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
+
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${ST_MFXSTM32L152}/mfxstm32l152.c
+    ${ST_MFXSTM32L152}/mfxstm32l152_reg.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    ${ST_MFXSTM32L152}
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H743xx
+    HSE_VALUE=25000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
index af2063ce0..334876e51 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 H743 Eval
+   url: https://www.st.com/en/evaluation-tools/stm32h743i-eval.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,22 +36,11 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOA
-#define LED_PIN               GPIO_PIN_4
-#define LED_STATE_ON          1
-
-// Tamper push-button
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   0
+#include "mfxstm32l152.h"
 
 // Need to change jumper setting J7 and J8 from RS-232 to STLink
 #define UART_DEV              USART1
 #define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOB
-#define UART_GPIO_AF          GPIO_AF4_USART1
-#define UART_TX_PIN           GPIO_PIN_14
-#define UART_RX_PIN           GPIO_PIN_15
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
@@ -58,14 +52,51 @@
   {GPIOB, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_10}, {GPIOB, GPIO_PIN_11}, {GPIOB, GPIO_PIN_12}, \
   {GPIOB, GPIO_PIN_13}, {GPIOC, GPIO_PIN_0 }, {GPIOH, GPIO_PIN_4 }, {GPIOI, GPIO_PIN_11}
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // UART TX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_USART1 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_15, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_USART1 },
+    .active_state = 0
+  },
+  { // I2C SCL for MFX VBUS
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_I2C1 },
+    .active_state = 0
+  },
+  { // I2C SDA for MFX VBUS
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_I2C1 },
+    .active_state = 1
+  },
+};
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+static inline void SystemClock_Config(void) {
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
 
   /*!< Supply configuration update enable */
   HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
@@ -75,7 +106,7 @@ static inline void board_stm32h7_clock_init(void)
      regarding system frequency refer to product datasheet.  */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
-  while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
+  while ( (PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY ) {}
 
   /* Enable HSE Oscillator and activate PLL with HSE as source */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
@@ -85,55 +116,143 @@ static inline void board_stm32h7_clock_init(void)
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 
-  /* PLL1 for System Clock */
+  // PLL1 for System Clock (400Mhz)
+  // From H743 eval manual ETM can only work at 50 MHz clock by default because ETM signals
+  // are shared with other peripherals. Trace CLK = PLL1R.
   RCC_OscInitStruct.PLL.PLLM = 5;
   RCC_OscInitStruct.PLL.PLLN = 160;
-  RCC_OscInitStruct.PLL.PLLFRACN = 0;
   RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLR = 2;
   RCC_OscInitStruct.PLL.PLLQ = 4;
-
+  RCC_OscInitStruct.PLL.PLLR = 6; // Trace clock is 400/6 = 66.67 MHz (larger than 50 MHz but work well)
   RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
   RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
-  /* PLL3 for USB Clock */
-  PeriphClkInitStruct.PLL3.PLL3M = 25;
-  PeriphClkInitStruct.PLL3.PLL3N = 336;
-  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
-  PeriphClkInitStruct.PLL3.PLL3P = 2;
-  PeriphClkInitStruct.PLL3.PLL3R = 2;
-  PeriphClkInitStruct.PLL3.PLL3Q = 7;
 
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select PLL as system clock source and configure  bus clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
-  RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
+  /* Select PLL as system clock source and configure bus clocks dividers */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 |
+                                RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1;
 
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
-  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  /* PLL3 for USB Clock */
+  PeriphClkInitStruct.PLL3.PLL3M = 25;
+  PeriphClkInitStruct.PLL3.PLL3N = 336;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 7;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
   /*activate CSI clock mondatory for I/O Compensation Cell*/
-  __HAL_RCC_CSI_ENABLE() ;
+  __HAL_RCC_CSI_ENABLE();
 
   /* Enable SYSCFG clock mondatory for I/O Compensation Cell */
-  __HAL_RCC_SYSCFG_CLK_ENABLE() ;
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
 
   /* Enables the I/O Compensation Cell */
   HAL_EnableCompensationCell();
 }
 
-static inline void board_stm32h7_post_init(void)
-{
-  // For this board does nothing
+//--------------------------------------------------------------------+
+// MFX
+//--------------------------------------------------------------------+
+static I2C_HandleTypeDef i2c_handle = {
+  .Instance = I2C1,
+  .Init = {
+    .Timing = 0x10C0ECFF,
+    .OwnAddress1 = 0,
+    .AddressingMode = I2C_ADDRESSINGMODE_7BIT,
+    .DualAddressMode = I2C_DUALADDRESS_DISABLE,
+    .OwnAddress2 = 0,
+    .OwnAddress2Masks = I2C_OA2_NOMASK,
+    .GeneralCallMode = I2C_GENERALCALL_DISABLE,
+    .NoStretchMode = I2C_NOSTRETCH_DISABLE,
+  }
+};
+static MFXSTM32L152_Object_t  mfx_obj = { 0 };
+static MFXSTM32L152_IO_Mode_t* mfx_io = NULL;
+static uint32_t mfx_vbus_pin[2] = { MFXSTM32L152_GPIO_PIN_7, MFXSTM32L152_GPIO_PIN_9 };
+
+int32_t board_i2c_init(void) {
+  __HAL_RCC_I2C1_CLK_ENABLE();
+  __HAL_RCC_I2C1_FORCE_RESET();
+  __HAL_RCC_I2C1_RELEASE_RESET();
+  if (HAL_I2C_Init(&i2c_handle) != HAL_OK) {
+    return HAL_ERROR;
+  }
+  if (HAL_I2CEx_ConfigAnalogFilter(&i2c_handle, I2C_ANALOGFILTER_ENABLE) != HAL_OK) {
+    return HAL_ERROR;
+  }
+  if (HAL_I2CEx_ConfigDigitalFilter(&i2c_handle, 0) != HAL_OK) {
+    return HAL_ERROR;
+  }
+  return 0;
+}
+
+int32_t board_i2c_deinit(void) {
+  return 0;
+}
+
+int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
+  TU_ASSERT (HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
+  return 0;
+}
+
+int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
+  TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
+  return 0;
+}
+
+static inline void board_init2(void) {
+  // IO control via MFX
+  MFXSTM32L152_IO_t io_ctx;
+  io_ctx.Init        = board_i2c_init;
+  io_ctx.DeInit      = board_i2c_deinit;
+  io_ctx.ReadReg     = i2c_readreg;
+  io_ctx.WriteReg    = i2c_writereg;
+  io_ctx.GetTick     = (MFXSTM32L152_GetTick_Func) HAL_GetTick;
+
+  uint16_t i2c_addr[] = { 0x84, 0x86 };
+  for(uint8_t i = 0U; i < 2U; i++) {
+    uint32_t mfx_id;
+    io_ctx.Address = i2c_addr[i];
+    TU_ASSERT(MFXSTM32L152_RegisterBusIO(&mfx_obj, &io_ctx) == MFXSTM32L152_OK, );
+    TU_ASSERT(MFXSTM32L152_ReadID(&mfx_obj, &mfx_id) == MFXSTM32L152_OK, );
+    if ((mfx_id == MFXSTM32L152_ID) || (mfx_id == MFXSTM32L152_ID_2)) {
+      TU_ASSERT(MFXSTM32L152_Init(&mfx_obj) == MFXSTM32L152_OK, );
+      break;
+    }
+  }
+
+  mfx_io = &MFXSTM32L152_IO_Driver;
+  mfx_io->IO_Start(&mfx_obj, MFXSTM32L152_GPIO_PINS_ALL);
+
+  for(uint32_t i=0; i<2; i++) {
+    MFXSTM32L152_IO_Init_t io_init = {
+      .Pin = mfx_vbus_pin[i],
+      .Mode = MFXSTM32L152_GPIO_MODE_OUTPUT_PP,
+      .Pull = MFXSTM32L152_GPIO_PULLUP,
+    };
+    mfx_io->Init(&mfx_obj, &io_init);
+  }
+}
+
+// VBUS1 is actually controlled by USB3320C PHY (using dwc2 drivebus signal)
+void board_vbus_set(uint8_t rhport, bool state) {
+  if (mfx_io) {
+    mfx_io->IO_WritePin(&mfx_obj, mfx_vbus_pin[rhport], state);
+  }
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
index b768a0ee6..67b403932 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
@@ -1,11 +1,17 @@
+MCU_VARIANT = stm32h743xx
 CFLAGS += -DSTM32H743xx -DHSE_VALUE=25000000
 
-# Default is Highspeed port
-PORT ?= 1
-SPEED ?= high
+RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
+LD_FILE_GCC = $(FAMILY_PATH)/linker/${MCU_VARIANT}_flash.ld
+
+SRC_C += \
+  ${ST_MFXSTM32L152}/mfxstm32l152.c \
+  ${ST_MFXSTM32L152}/mfxstm32l152_reg.c \
+
+INC += $(TOP)/${ST_MFXSTM32L152}
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h743xi
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
new file mode 100644
index 000000000..0e5a4cc00
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
@@ -0,0 +1,1134 @@
+#MicroXplorer Configuration settings - do not modify
+CAD.formats=[]
+CAD.pinconfig=Project naming
+CAD.provider=
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+I2C1.IPParameters=Timing
+I2C1.Timing=0x10C0ECFF
+KeepUserPlacement=false
+Mcu.CPN=STM32H743XIH6
+Mcu.Family=STM32H7
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=DEBUG
+Mcu.IP2=I2C1
+Mcu.IP3=NVIC
+Mcu.IP4=RCC
+Mcu.IP5=SYS
+Mcu.IP6=USB_OTG_FS
+Mcu.IP7=USB_OTG_HS
+Mcu.IPNb=8
+Mcu.Name=STM32H743XIHx
+Mcu.Package=TFBGA240
+Mcu.Pin0=PI6
+Mcu.Pin1=PI5
+Mcu.Pin10=PA15 (JTDI)
+Mcu.Pin100=PC1
+Mcu.Pin101=PC2
+Mcu.Pin102=PC3
+Mcu.Pin103=PJ9
+Mcu.Pin104=PH2
+Mcu.Pin105=PA2
+Mcu.Pin106=PA1
+Mcu.Pin107=PJ0
+Mcu.Pin108=PE10
+Mcu.Pin109=PJ8
+Mcu.Pin11=PI1
+Mcu.Pin110=PJ7
+Mcu.Pin111=PJ6
+Mcu.Pin112=PH3
+Mcu.Pin113=PH4
+Mcu.Pin114=PH5
+Mcu.Pin115=PI15
+Mcu.Pin116=PJ1
+Mcu.Pin117=PF13
+Mcu.Pin118=PF14
+Mcu.Pin119=PE9
+Mcu.Pin12=PI0
+Mcu.Pin120=PE11
+Mcu.Pin121=PB10
+Mcu.Pin122=PB11
+Mcu.Pin123=PH10
+Mcu.Pin124=PH11
+Mcu.Pin125=PD15
+Mcu.Pin126=PD14
+Mcu.Pin127=PA6
+Mcu.Pin128=PA7
+Mcu.Pin129=PB2
+Mcu.Pin13=PI7
+Mcu.Pin130=PF12
+Mcu.Pin131=PF15
+Mcu.Pin132=PE12
+Mcu.Pin133=PE15
+Mcu.Pin134=PJ5
+Mcu.Pin135=PH9
+Mcu.Pin136=PH12
+Mcu.Pin137=PD11
+Mcu.Pin138=PD12
+Mcu.Pin139=PD13
+Mcu.Pin14=PE1
+Mcu.Pin140=PA0_C
+Mcu.Pin141=PA5
+Mcu.Pin142=PC4
+Mcu.Pin143=PB1
+Mcu.Pin144=PJ2
+Mcu.Pin145=PF11
+Mcu.Pin146=PG0
+Mcu.Pin147=PE8
+Mcu.Pin148=PE13
+Mcu.Pin149=PH6
+Mcu.Pin15=PB6
+Mcu.Pin150=PH8
+Mcu.Pin151=PB12
+Mcu.Pin152=PB15
+Mcu.Pin153=PD10
+Mcu.Pin154=PD9
+Mcu.Pin155=PA3
+Mcu.Pin156=PA4
+Mcu.Pin157=PC5
+Mcu.Pin158=PB0
+Mcu.Pin159=PJ3
+Mcu.Pin16=PB4 (NJTRST)
+Mcu.Pin160=PJ4
+Mcu.Pin161=PG1
+Mcu.Pin162=PE7
+Mcu.Pin163=PE14
+Mcu.Pin164=PH7
+Mcu.Pin165=PB13
+Mcu.Pin166=PB14
+Mcu.Pin167=PD8
+Mcu.Pin168=VP_SYS_VS_Systick
+Mcu.Pin17=PK4
+Mcu.Pin18=PG11
+Mcu.Pin19=PJ15
+Mcu.Pin2=PI4
+Mcu.Pin20=PD6
+Mcu.Pin21=PD3
+Mcu.Pin22=PC11
+Mcu.Pin23=PA14 (JTCK/SWCLK)
+Mcu.Pin24=PI2
+Mcu.Pin25=PH15
+Mcu.Pin26=PH14
+Mcu.Pin27=PC15-OSC32_OUT (OSC32_OUT)
+Mcu.Pin28=PC14-OSC32_IN (OSC32_IN)
+Mcu.Pin29=PE2
+Mcu.Pin3=PB5
+Mcu.Pin30=PE0
+Mcu.Pin31=PB7
+Mcu.Pin32=PB3 (JTDO/TRACESWO)
+Mcu.Pin33=PK6
+Mcu.Pin34=PK3
+Mcu.Pin35=PG12
+Mcu.Pin36=PD7
+Mcu.Pin37=PC12
+Mcu.Pin38=PI3
+Mcu.Pin39=PA13 (JTMS/SWDIO)
+Mcu.Pin4=PK5
+Mcu.Pin40=PE5
+Mcu.Pin41=PE4
+Mcu.Pin42=PE3
+Mcu.Pin43=PB9
+Mcu.Pin44=PB8
+Mcu.Pin45=PG15
+Mcu.Pin46=PK7
+Mcu.Pin47=PG14
+Mcu.Pin48=PG13
+Mcu.Pin49=PJ14
+Mcu.Pin5=PG10
+Mcu.Pin50=PJ12
+Mcu.Pin51=PD2
+Mcu.Pin52=PD0
+Mcu.Pin53=PA10
+Mcu.Pin54=PA9
+Mcu.Pin55=PH13
+Mcu.Pin56=PI9
+Mcu.Pin57=PC13
+Mcu.Pin58=PI8
+Mcu.Pin59=PE6
+Mcu.Pin6=PG9
+Mcu.Pin60=PJ13
+Mcu.Pin61=PD1
+Mcu.Pin62=PC8
+Mcu.Pin63=PC9
+Mcu.Pin64=PA8
+Mcu.Pin65=PA12
+Mcu.Pin66=PA11
+Mcu.Pin67=PI10
+Mcu.Pin68=PI11
+Mcu.Pin69=PC7
+Mcu.Pin7=PD5
+Mcu.Pin70=PC6
+Mcu.Pin71=PG8
+Mcu.Pin72=PG7
+Mcu.Pin73=PF2
+Mcu.Pin74=PF1
+Mcu.Pin75=PF0
+Mcu.Pin76=PG5
+Mcu.Pin77=PG6
+Mcu.Pin78=PI12
+Mcu.Pin79=PI13
+Mcu.Pin8=PD4
+Mcu.Pin80=PI14
+Mcu.Pin81=PF3
+Mcu.Pin82=PG4
+Mcu.Pin83=PG3
+Mcu.Pin84=PG2
+Mcu.Pin85=PK2
+Mcu.Pin86=PH1-OSC_OUT (PH1)
+Mcu.Pin87=PH0-OSC_IN (PH0)
+Mcu.Pin88=PF5
+Mcu.Pin89=PF4
+Mcu.Pin9=PC10
+Mcu.Pin90=PK0
+Mcu.Pin91=PK1
+Mcu.Pin92=PF6
+Mcu.Pin93=PF7
+Mcu.Pin94=PF8
+Mcu.Pin95=PJ11
+Mcu.Pin96=PC0
+Mcu.Pin97=PF10
+Mcu.Pin98=PF9
+Mcu.Pin99=PJ10
+Mcu.PinsNb=169
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H743XIHx
+MxCube.Version=6.10.0
+MxDb.Version=DB.6.0.100
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+PA0_C.GPIOParameters=GPIO_Label
+PA0_C.GPIO_Label=Potentiometer
+PA0_C.Locked=true
+PA0_C.Signal=ADCx_INN1
+PA1.GPIOParameters=GPIO_Label
+PA1.GPIO_Label=RMII_REF_CLK [LAN8742A_REFCLK0]
+PA1.Locked=true
+PA1.Signal=ETH_REF_CLK
+PA10.GPIOParameters=GPIO_Label
+PA10.GPIO_Label=USB_FS1_ID
+PA10.Locked=true
+PA10.Signal=USB_OTG_FS_ID
+PA11.GPIOParameters=GPIO_Label
+PA11.GPIO_Label=USB_FS1_DM
+PA11.Locked=true
+PA11.Mode=Device_Only
+PA11.Signal=USB_OTG_FS_DM
+PA12.GPIOParameters=GPIO_Label
+PA12.GPIO_Label=USB_FS1_DP
+PA12.Locked=true
+PA12.Mode=Device_Only
+PA12.Signal=USB_OTG_FS_DP
+PA13\ (JTMS/SWDIO).Locked=true
+PA13\ (JTMS/SWDIO).Mode=Trace_Synchro_4bits_SW
+PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
+PA14\ (JTCK/SWCLK).Locked=true
+PA14\ (JTCK/SWCLK).Mode=Trace_Synchro_4bits_SW
+PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
+PA15\ (JTDI).GPIOParameters=GPIO_Label
+PA15\ (JTDI).GPIO_Label=TDI
+PA15\ (JTDI).Locked=true
+PA15\ (JTDI).Signal=DEBUG_JTDI
+PA2.GPIOParameters=GPIO_Label
+PA2.GPIO_Label=ETH_MDIO [LAN8742A_MDIO]
+PA2.Locked=true
+PA2.Signal=ETH_MDIO
+PA3.GPIOParameters=GPIO_Label
+PA3.GPIO_Label=ULPI_D0 [USB3320C_D0]
+PA3.Locked=true
+PA3.Mode=Device_HS
+PA3.Signal=USB_OTG_HS_ULPI_D0
+PA4.GPIOParameters=GPIO_Label
+PA4.GPIO_Label=LED3_RGB [LD3_Red]
+PA4.Locked=true
+PA4.Signal=GPIO_Output
+PA5.GPIOParameters=GPIO_Label
+PA5.GPIO_Label=ULPI_CK  [USB3320C_CLKOUT]
+PA5.Locked=true
+PA5.Mode=Device_HS
+PA5.Signal=USB_OTG_HS_ULPI_CK
+PA6.GPIOParameters=GPIO_Label
+PA6.GPIO_Label=LCD_BL_CTRL
+PA6.Locked=true
+PA6.Signal=GPIO_Output
+PA7.GPIOParameters=GPIO_Label
+PA7.GPIO_Label=RMII_CRS_DV [LAN8742A_CRS_DV]
+PA7.Locked=true
+PA7.Signal=ETH_CRS_DV
+PA8.GPIOParameters=GPIO_Label
+PA8.GPIO_Label=MCO
+PA8.Locked=true
+PA8.Signal=RCC_MCO_1
+PA9.GPIOParameters=GPIO_Label
+PA9.GPIO_Label=VBUS_FS1
+PA9.Locked=true
+PA9.Signal=USB_OTG_FS_VBUS
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=ULPI_D1 [USB3320C_D1]
+PB0.Locked=true
+PB0.Mode=Device_HS
+PB0.Signal=USB_OTG_HS_ULPI_D1
+PB1.GPIOParameters=GPIO_Label
+PB1.GPIO_Label=ULPI_D2 [USB3320C_D2]
+PB1.Locked=true
+PB1.Mode=Device_HS
+PB1.Signal=USB_OTG_HS_ULPI_D2
+PB10.GPIOParameters=GPIO_Label
+PB10.GPIO_Label=ULPI_D3 [USB3320C_D3]
+PB10.Locked=true
+PB10.Mode=Device_HS
+PB10.Signal=USB_OTG_HS_ULPI_D3
+PB11.GPIOParameters=GPIO_Label
+PB11.GPIO_Label=ULPI_D4 [USB3320C_D4]
+PB11.Locked=true
+PB11.Mode=Device_HS
+PB11.Signal=USB_OTG_HS_ULPI_D4
+PB12.GPIOParameters=GPIO_Label
+PB12.GPIO_Label=ULPI_D5 [USB3320C_D5]
+PB12.Locked=true
+PB12.Mode=Device_HS
+PB12.Signal=USB_OTG_HS_ULPI_D5
+PB13.GPIOParameters=GPIO_Label
+PB13.GPIO_Label=ULPI_D6 [USB3320C_D6]
+PB13.Locked=true
+PB13.Mode=Device_HS
+PB13.Signal=USB_OTG_HS_ULPI_D6
+PB14.GPIOParameters=GPIO_Label
+PB14.GPIO_Label=RS232_TX [ST3241EBPR_T2IN]
+PB14.Locked=true
+PB14.Signal=USART1_TX
+PB15.GPIOParameters=GPIO_Label
+PB15.GPIO_Label=RS_232RX [ST3241EBPR_R3OUT]
+PB15.Locked=true
+PB15.Signal=USART1_RX
+PB2.GPIOParameters=GPIO_Label
+PB2.GPIO_Label=QSPI_CLK [MT25TL01GHBA8ESF_CLK_1]
+PB2.Locked=true
+PB2.Signal=QUADSPI_CLK
+PB3\ (JTDO/TRACESWO).Locked=true
+PB3\ (JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO
+PB4\ (NJTRST).GPIOParameters=GPIO_Label
+PB4\ (NJTRST).GPIO_Label=TRST
+PB4\ (NJTRST).Locked=true
+PB4\ (NJTRST).Signal=DEBUG_JTRST
+PB5.GPIOParameters=GPIO_Label
+PB5.GPIO_Label=ULPI_D7 [USB3320C_D7]
+PB5.Locked=true
+PB5.Mode=Device_HS
+PB5.Signal=USB_OTG_HS_ULPI_D7
+PB6.GPIOParameters=GPIO_Label
+PB6.GPIO_Label=I2C1_SCL [STM32L152CCT6_I2C_SCL]
+PB6.Locked=true
+PB6.Mode=I2C
+PB6.Signal=I2C1_SCL
+PB7.GPIOParameters=GPIO_Label
+PB7.GPIO_Label=I2C1_SDA [STM32L152CCT6_I2C_SDA]
+PB7.Locked=true
+PB7.Mode=I2C
+PB7.Signal=I2C1_SDA
+PB8.GPIOParameters=GPIO_Label
+PB8.GPIO_Label=SDIO1_CKIN
+PB8.Locked=true
+PB8.Signal=SDMMC1_CKIN
+PB9.GPIOParameters=GPIO_Label
+PB9.GPIO_Label=SDIO1_CDIR
+PB9.Locked=true
+PB9.Signal=SDMMC1_CDIR
+PC0.GPIOParameters=GPIO_Label
+PC0.GPIO_Label=ULPI_STP [USB3320C_STP]
+PC0.Locked=true
+PC0.Mode=Device_HS
+PC0.Signal=USB_OTG_HS_ULPI_STP
+PC1.GPIOParameters=GPIO_Label
+PC1.GPIO_Label=RMII_MDC [LAN8742A_MDC]
+PC1.Locked=true
+PC1.Signal=ETH_MDC
+PC10.GPIOParameters=GPIO_Label
+PC10.GPIO_Label=SDIO1_D2
+PC10.Locked=true
+PC10.Signal=SDMMC1_D2
+PC11.GPIOParameters=GPIO_Label
+PC11.GPIO_Label=SDIO1_D3
+PC11.Locked=true
+PC11.Signal=SDMMC1_D3
+PC12.GPIOParameters=GPIO_Label
+PC12.GPIO_Label=SDIO1_CLK
+PC12.Locked=true
+PC12.Signal=SDMMC1_CK
+PC13.GPIOParameters=GPIO_Label
+PC13.GPIO_Label=TAMPER_KEY [B1]
+PC13.Locked=true
+PC13.Signal=RTC_TAMP1
+PC14-OSC32_IN\ (OSC32_IN).Locked=true
+PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN
+PC15-OSC32_OUT\ (OSC32_OUT).Locked=true
+PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT
+PC2.GPIOParameters=GPIO_Label
+PC2.GPIO_Label=DFSDM_CLK
+PC2.Locked=true
+PC2.Signal=S_CKOUTDFSDM1
+PC3.GPIOParameters=GPIO_Label
+PC3.GPIO_Label=DFSM_DAT1
+PC3.Locked=true
+PC3.Signal=S_DATAIN1DFSDM1
+PC4.GPIOParameters=GPIO_Label
+PC4.GPIO_Label=RMII_RXD0 [LAN8742A_RXD0]
+PC4.Locked=true
+PC4.Signal=ETH_RXD0
+PC5.GPIOParameters=GPIO_Label
+PC5.GPIO_Label=RMII_RXD1 [LAN8742A_RXD1]
+PC5.Locked=true
+PC5.Signal=ETH_RXD1
+PC6.GPIOParameters=GPIO_Label
+PC6.GPIO_Label=SDIO1_D0DIR
+PC6.Locked=true
+PC6.Signal=SDMMC1_D0DIR
+PC7.Locked=true
+PC7.Signal=DEBUG_TRGIO
+PC8.GPIOParameters=GPIO_Label
+PC8.GPIO_Label=SDIO1_D0
+PC8.Locked=true
+PC8.Signal=SDMMC1_D0
+PC9.GPIOParameters=GPIO_Label
+PC9.GPIO_Label=SDIO1_D1
+PC9.Locked=true
+PC9.Signal=SDMMC1_D1
+PD0.GPIOParameters=GPIO_Label
+PD0.GPIO_Label=D2 [IS42S32800G_DQ2]
+PD0.Locked=true
+PD0.Signal=FMC_D2_DA2
+PD1.GPIOParameters=GPIO_Label
+PD1.GPIO_Label=D3 [IS42S32800G_DQ3]
+PD1.Locked=true
+PD1.Signal=FMC_D3_DA3
+PD10.GPIOParameters=GPIO_Label
+PD10.GPIO_Label=D15 [IS42S32800G_DQ15]
+PD10.Locked=true
+PD10.Signal=FMC_D15_DA15
+PD11.GPIOParameters=GPIO_Label
+PD11.GPIO_Label=A16 [PC28F128M29EWLA_A16]
+PD11.Locked=true
+PD11.Signal=FMC_A16_CLE
+PD12.GPIOParameters=GPIO_Label
+PD12.GPIO_Label=A17 [PC28F128M29EWLA_A17]
+PD12.Locked=true
+PD12.Signal=FMC_A17_ALE
+PD13.GPIOParameters=GPIO_Label
+PD13.GPIO_Label=A18 [PC28F128M29EWLA_A18]
+PD13.Locked=true
+PD13.Signal=FMC_A18
+PD14.GPIOParameters=GPIO_Label
+PD14.GPIO_Label=D0 [IS42S32800G_DQ0]
+PD14.Locked=true
+PD14.Signal=FMC_D0_DA0
+PD15.GPIOParameters=GPIO_Label
+PD15.GPIO_Label=D1 [IS42S32800G_DQ1]
+PD15.Locked=true
+PD15.Signal=FMC_D1_DA1
+PD2.GPIOParameters=GPIO_Label
+PD2.GPIO_Label=SDIO1_CMD
+PD2.Locked=true
+PD2.Signal=SDMMC1_CMD
+PD3.GPIOParameters=GPIO_Label
+PD3.GPIO_Label=FDCAN1_STBY [MCP2562FD_STBY]
+PD3.Locked=true
+PD3.Signal=GPIO_Output
+PD4.GPIOParameters=GPIO_Label
+PD4.GPIO_Label=FMC_NOE [IS61WV102416BLL_OE]
+PD4.Locked=true
+PD4.Signal=FMC_NOE
+PD5.GPIOParameters=GPIO_Label
+PD5.GPIO_Label=FMC_NWE [IS61WV102416BLL_WE]
+PD5.Locked=true
+PD5.Signal=FMC_NWE
+PD6.GPIOParameters=GPIO_Label
+PD6.GPIO_Label=FMC_NWAIT [PC28F128M29EWLA_RB]
+PD6.Locked=true
+PD6.Signal=FMC_NWAIT
+PD7.GPIOParameters=GPIO_Label
+PD7.GPIO_Label=FMC_NE1 [PC28F128M29EWLA_E]
+PD7.Locked=true
+PD7.Signal=FMC_NE1
+PD8.GPIOParameters=GPIO_Label
+PD8.GPIO_Label=D13 [IS42S32800G_DQ13]
+PD8.Locked=true
+PD8.Signal=FMC_D13_DA13
+PD9.GPIOParameters=GPIO_Label
+PD9.GPIO_Label=D14 [IS42S32800G_DQ14]
+PD9.Locked=true
+PD9.Signal=FMC_D14_DA14
+PE0.GPIOParameters=GPIO_Label
+PE0.GPIO_Label=FMC_NBL0 [IS42S32800G_DQM0]
+PE0.Locked=true
+PE0.Signal=FMC_NBL0
+PE1.GPIOParameters=GPIO_Label
+PE1.GPIO_Label=FMC_NBL1 [IS42S32800G_DQM1]
+PE1.Locked=true
+PE1.Signal=FMC_NBL1
+PE10.GPIOParameters=GPIO_Label
+PE10.GPIO_Label=D7 [IS42S32800G_DQ7]
+PE10.Locked=true
+PE10.Signal=FMC_D7_DA7
+PE11.GPIOParameters=GPIO_Label
+PE11.GPIO_Label=D8 [IS42S32800G_DQ8]
+PE11.Locked=true
+PE11.Signal=FMC_D8_DA8
+PE12.GPIOParameters=GPIO_Label
+PE12.GPIO_Label=D9 [IS42S32800G_DQ9]
+PE12.Locked=true
+PE12.Signal=FMC_D9_DA9
+PE13.GPIOParameters=GPIO_Label
+PE13.GPIO_Label=D10 [IS42S32800G_DQ10]
+PE13.Locked=true
+PE13.Signal=FMC_D10_DA10
+PE14.GPIOParameters=GPIO_Label
+PE14.GPIO_Label=D11 [IS42S32800G_DQ11]
+PE14.Locked=true
+PE14.Signal=FMC_D11_DA11
+PE15.GPIOParameters=GPIO_Label
+PE15.GPIO_Label=D12 [IS42S32800G_DQ12]
+PE15.Locked=true
+PE15.Signal=FMC_D12_DA12
+PE2.Locked=true
+PE2.Mode=Trace_Synchro_4bits_SW
+PE2.Signal=DEBUG_TRACECLK
+PE3.Locked=true
+PE3.Mode=Trace_Synchro_4bits_SW
+PE3.Signal=DEBUG_TRACED0
+PE4.Locked=true
+PE4.Mode=Trace_Synchro_4bits_SW
+PE4.Signal=DEBUG_TRACED1
+PE5.Locked=true
+PE5.Mode=Trace_Synchro_4bits_SW
+PE5.Signal=DEBUG_TRACED2
+PE6.Locked=true
+PE6.Mode=Trace_Synchro_4bits_SW
+PE6.Signal=DEBUG_TRACED3
+PE7.GPIOParameters=GPIO_Label
+PE7.GPIO_Label=D4 [IS42S32800G_DQ4]
+PE7.Locked=true
+PE7.Signal=FMC_D4_DA4
+PE8.GPIOParameters=GPIO_Label
+PE8.GPIO_Label=D5 [IS42S32800G_DQ5]
+PE8.Locked=true
+PE8.Signal=FMC_D5_DA5
+PE9.GPIOParameters=GPIO_Label
+PE9.GPIO_Label=D6 [IS42S32800G_DQ6]
+PE9.Locked=true
+PE9.Signal=FMC_D6_DA6
+PF0.GPIOParameters=GPIO_Label
+PF0.GPIO_Label=A0 [PC28F128M29EWLA_A0]
+PF0.Locked=true
+PF0.Signal=FMC_A0
+PF1.GPIOParameters=GPIO_Label
+PF1.GPIO_Label=A1 [PC28F128M29EWLA_A1]
+PF1.Locked=true
+PF1.Signal=FMC_A1
+PF10.GPIOParameters=GPIO_Label
+PF10.GPIO_Label=LED1_RGB [LD1_Green]
+PF10.Locked=true
+PF10.Signal=GPIO_Output
+PF11.GPIOParameters=GPIO_Label
+PF11.GPIO_Label=SNDRAS [IS42S32800G_RAS]
+PF11.Locked=true
+PF11.Signal=FMC_SDNRAS
+PF12.GPIOParameters=GPIO_Label
+PF12.GPIO_Label=A6 [PC28F128M29EWLA_A6]
+PF12.Locked=true
+PF12.Signal=FMC_A6
+PF13.GPIOParameters=GPIO_Label
+PF13.GPIO_Label=A7 [PC28F128M29EWLA_A7]
+PF13.Locked=true
+PF13.Signal=FMC_A7
+PF14.GPIOParameters=GPIO_Label
+PF14.GPIO_Label=A8 [PC28F128M29EWLA_A8]
+PF14.Locked=true
+PF14.Signal=FMC_A8
+PF15.GPIOParameters=GPIO_Label
+PF15.GPIO_Label=A9 [PC28F128M29EWLA_A9]
+PF15.Locked=true
+PF15.Signal=FMC_A9
+PF2.GPIOParameters=GPIO_Label
+PF2.GPIO_Label=A2 [PC28F128M29EWLA_A2]
+PF2.Locked=true
+PF2.Signal=FMC_A2
+PF3.GPIOParameters=GPIO_Label
+PF3.GPIO_Label=A3 [PC28F128M29EWLA_A3]
+PF3.Locked=true
+PF3.Signal=FMC_A3
+PF4.GPIOParameters=GPIO_Label
+PF4.GPIO_Label=A4 [PC28F128M29EWLA_A4]
+PF4.Locked=true
+PF4.Signal=FMC_A4
+PF5.GPIOParameters=GPIO_Label
+PF5.GPIO_Label=A5 [PC28F128M29EWLA_A5]
+PF5.Locked=true
+PF5.Signal=FMC_A5
+PF6.GPIOParameters=GPIO_Label
+PF6.GPIO_Label=QSPI_BK1_IO3 [MT25TL01GHBA8ESF_DQ3]
+PF6.Locked=true
+PF6.Signal=QUADSPI_BK1_IO3
+PF7.GPIOParameters=GPIO_Label
+PF7.GPIO_Label=QSPI_BK1_IO2 [MT25TL01GHBA8ESF_DQ2]
+PF7.Locked=true
+PF7.Signal=QUADSPI_BK1_IO2
+PF8.GPIOParameters=GPIO_Label
+PF8.GPIO_Label=QSPI_BK1_IO0 [MT25TL01GHBA8ESF_DQ0]
+PF8.Locked=true
+PF8.Signal=QUADSPI_BK1_IO0
+PF9.GPIOParameters=GPIO_Label
+PF9.GPIO_Label=QSPI_BK1_IO1 [MT25TL01GHBA8ESF_DQ1]
+PF9.Locked=true
+PF9.Signal=QUADSPI_BK1_IO1
+PG0.GPIOParameters=GPIO_Label
+PG0.GPIO_Label=A10 [PC28F128M29EWLA_A10]
+PG0.Locked=true
+PG0.Signal=FMC_A10
+PG1.GPIOParameters=GPIO_Label
+PG1.GPIO_Label=A11 [PC28F128M29EWLA_A11]
+PG1.Locked=true
+PG1.Signal=FMC_A11
+PG10.GPIOParameters=GPIO_Label
+PG10.GPIO_Label=FMC_NE3 [IS61WV102416BLL_CE]
+PG10.Locked=true
+PG10.Signal=FMC_NE3
+PG11.GPIOParameters=GPIO_Label
+PG11.GPIO_Label=RMII_TX_EN [LAN8742A_TXEN]
+PG11.Locked=true
+PG11.Signal=ETH_TX_EN
+PG12.GPIOParameters=GPIO_Label
+PG12.GPIO_Label=RMII_TXD1 [LAN8742A_TXD1]
+PG12.Locked=true
+PG12.Signal=ETH_TXD1
+PG13.GPIOParameters=GPIO_Label
+PG13.GPIO_Label=RMII_TXD0 [LAN8742A_TXD0]
+PG13.Locked=true
+PG13.Signal=ETH_TXD0
+PG14.GPIOParameters=GPIO_Label
+PG14.GPIO_Label=QSPI_BK2_IO3 [MT25TL01GHBA8ESF_DQ7]
+PG14.Locked=true
+PG14.Signal=QUADSPI_BK2_IO3
+PG15.GPIOParameters=GPIO_Label
+PG15.GPIO_Label=SDNCAS [IS42S32800G_CAS]
+PG15.Locked=true
+PG15.Signal=FMC_SDNCAS
+PG2.GPIOParameters=GPIO_Label
+PG2.GPIO_Label=A12 [PC28F128M29EWLA_A12]
+PG2.Locked=true
+PG2.Signal=FMC_A12
+PG3.GPIOParameters=GPIO_Label
+PG3.GPIO_Label=A13 [PC28F128M29EWLA_A13]
+PG3.Locked=true
+PG3.Signal=FMC_A13
+PG4.Locked=true
+PG4.Signal=FMC_A14_BA0
+PG5.Locked=true
+PG5.Signal=FMC_A15_BA1
+PG6.GPIOParameters=GPIO_Label
+PG6.GPIO_Label=QSPI_BK1_NCS [MT25TL01GHBA8ESF_CS]
+PG6.Locked=true
+PG6.Signal=QUADSPI_BK1_NCS
+PG7.GPIOParameters=GPIO_Label
+PG7.GPIO_Label=SAI1_MCLKA [WM8994ECS_MCLK1]
+PG7.Locked=true
+PG7.Signal=SAI1_MCLK_A
+PG8.GPIOParameters=GPIO_Label
+PG8.GPIO_Label=SDCLK [IS42S32800G_CLK]
+PG8.Locked=true
+PG8.Signal=FMC_SDCLK
+PG9.GPIOParameters=GPIO_Label
+PG9.GPIO_Label=QSPI_BK2_IO2 [MT25TL01GHBA8ESF_DQ6]
+PG9.Locked=true
+PG9.Signal=QUADSPI_BK2_IO2
+PH0-OSC_IN\ (PH0).Locked=true
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT\ (PH1).Locked=true
+PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
+PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
+PH10.GPIOParameters=GPIO_Label
+PH10.GPIO_Label=D18 [IS42S32800G_DQ18]
+PH10.Locked=true
+PH10.Signal=FMC_D18
+PH11.GPIOParameters=GPIO_Label
+PH11.GPIO_Label=D19 [IS42S32800G_DQ19]
+PH11.Locked=true
+PH11.Signal=FMC_D19
+PH12.GPIOParameters=GPIO_Label
+PH12.GPIO_Label=D20 [IS42S32800G_DQ20]
+PH12.Locked=true
+PH12.Signal=FMC_D20
+PH13.GPIOParameters=GPIO_Label
+PH13.GPIO_Label=D21 [IS42S32800G_DQ21]
+PH13.Locked=true
+PH13.Signal=FMC_D21
+PH14.GPIOParameters=GPIO_Label
+PH14.GPIO_Label=D22 [IS42S32800G_DQ22]
+PH14.Locked=true
+PH14.Signal=FMC_D22
+PH15.GPIOParameters=GPIO_Label
+PH15.GPIO_Label=D23 [IS42S32800G_DQ23]
+PH15.Locked=true
+PH15.Signal=FMC_D23
+PH2.GPIOParameters=GPIO_Label
+PH2.GPIO_Label=QSPI_BK2_IO0 [MT25TL01GHBA8ESF_DQ4]
+PH2.Locked=true
+PH2.Signal=QUADSPI_BK2_IO0
+PH3.GPIOParameters=GPIO_Label
+PH3.GPIO_Label=QSPI_BK2_IO1 [MT25TL01GHBA8ESF_DQ5]
+PH3.Locked=true
+PH3.Signal=QUADSPI_BK2_IO1
+PH4.GPIOParameters=GPIO_Label
+PH4.GPIO_Label=ULPI_NXT [USB3320C_NXT]
+PH4.Locked=true
+PH4.Mode=Device_HS
+PH4.Signal=USB_OTG_HS_ULPI_NXT
+PH5.GPIOParameters=GPIO_Label
+PH5.GPIO_Label=SDNWE [IS42S32800G_WE]
+PH5.Locked=true
+PH5.Signal=FMC_SDNWE
+PH6.GPIOParameters=GPIO_Label
+PH6.GPIO_Label=SDNE1 [IS42S32800G_CS]
+PH6.Locked=true
+PH6.Signal=FMC_SDNE1
+PH7.GPIOParameters=GPIO_Label
+PH7.GPIO_Label=SDCKE1 [IS42S32800G_CKE]
+PH7.Locked=true
+PH7.Signal=FMC_SDCKE1
+PH8.GPIOParameters=GPIO_Label
+PH8.GPIO_Label=D16 [IS42S32800G_DQ16]
+PH8.Locked=true
+PH8.Signal=FMC_D16
+PH9.GPIOParameters=GPIO_Label
+PH9.GPIO_Label=D17 [IS42S32800G_DQ17]
+PH9.Locked=true
+PH9.Signal=FMC_D17
+PI0.GPIOParameters=GPIO_Label
+PI0.GPIO_Label=D24 [IS42S32800G_DQ24]
+PI0.Locked=true
+PI0.Signal=FMC_D24
+PI1.GPIOParameters=GPIO_Label
+PI1.GPIO_Label=D25 [IS42S32800G_DQ25]
+PI1.Locked=true
+PI1.Signal=FMC_D25
+PI10.GPIOParameters=GPIO_Label
+PI10.GPIO_Label=D31 [IS42S32800G_DQ31]
+PI10.Locked=true
+PI10.Signal=FMC_D31
+PI11.GPIOParameters=GPIO_Label
+PI11.GPIO_Label=ULPI_DIR [USB3320C_DIR]
+PI11.Locked=true
+PI11.Mode=Device_HS
+PI11.Signal=USB_OTG_HS_ULPI_DIR
+PI12.GPIOParameters=GPIO_Label
+PI12.GPIO_Label=LCD_HSYNC
+PI12.Locked=true
+PI12.Signal=LTDC_HSYNC
+PI13.GPIOParameters=GPIO_Label
+PI13.GPIO_Label=LCD_VSYNC
+PI13.Locked=true
+PI13.Signal=LTDC_VSYNC
+PI14.GPIOParameters=GPIO_Label
+PI14.GPIO_Label=LCD_CLK
+PI14.Locked=true
+PI14.Signal=LTDC_CLK
+PI15.GPIOParameters=GPIO_Label
+PI15.GPIO_Label=LCD_R0
+PI15.Locked=true
+PI15.Signal=LTDC_R0
+PI2.GPIOParameters=GPIO_Label
+PI2.GPIO_Label=D26 [IS42S32800G_DQ26]
+PI2.Locked=true
+PI2.Signal=FMC_D26
+PI3.GPIOParameters=GPIO_Label
+PI3.GPIO_Label=D27 [IS42S32800G_DQ27
+PI3.Locked=true
+PI3.Signal=FMC_D27
+PI4.GPIOParameters=GPIO_Label
+PI4.GPIO_Label=FMC_NBL2 [IS42S32800G_DQM2]
+PI4.Locked=true
+PI4.Signal=FMC_NBL2
+PI5.GPIOParameters=GPIO_Label
+PI5.GPIO_Label=FMC_NBL3 [IS42S32800G_DQM3]
+PI5.Locked=true
+PI5.Signal=FMC_NBL3
+PI6.GPIOParameters=GPIO_Label
+PI6.GPIO_Label=D28 [IS42S32800G_DQ28]
+PI6.Locked=true
+PI6.Signal=FMC_D28
+PI7.GPIOParameters=GPIO_Label
+PI7.GPIO_Label=D29 [IS42S32800G_DQ29]
+PI7.Locked=true
+PI7.Signal=FMC_D29
+PI8.GPIOParameters=GPIO_Label
+PI8.GPIO_Label=MFX_IRQOUT [MFX_V3_IRQOUT]
+PI8.Locked=true
+PI8.Signal=GPXTI8
+PI9.GPIOParameters=GPIO_Label
+PI9.GPIO_Label=D30 [IS42S32800G_DQ30]
+PI9.Locked=true
+PI9.Signal=FMC_D30
+PJ0.GPIOParameters=GPIO_Label
+PJ0.GPIO_Label=LCD_R1
+PJ0.Locked=true
+PJ0.Signal=LTDC_R1
+PJ1.GPIOParameters=GPIO_Label
+PJ1.GPIO_Label=LCD_R2
+PJ1.Locked=true
+PJ1.Signal=LTDC_R2
+PJ10.GPIOParameters=GPIO_Label
+PJ10.GPIO_Label=LCd_G3
+PJ10.Locked=true
+PJ10.Signal=LTDC_G3
+PJ11.GPIOParameters=GPIO_Label
+PJ11.GPIO_Label=LCD_G4
+PJ11.Locked=true
+PJ11.Signal=LTDC_G4
+PJ12.Locked=true
+PJ12.Signal=DEBUG_TRGOUT
+PJ13.GPIOParameters=GPIO_Label
+PJ13.GPIO_Label=LCD_B1
+PJ13.Locked=true
+PJ13.Signal=LTDC_B1
+PJ14.GPIOParameters=GPIO_Label
+PJ14.GPIO_Label=LCD_B2
+PJ14.Locked=true
+PJ14.Signal=LTDC_B2
+PJ15.GPIOParameters=GPIO_Label
+PJ15.GPIO_Label=LCD_B3
+PJ15.Locked=true
+PJ15.Signal=LTDC_B3
+PJ2.GPIOParameters=GPIO_Label
+PJ2.GPIO_Label=LCD_R3
+PJ2.Locked=true
+PJ2.Signal=LTDC_R3
+PJ3.GPIOParameters=GPIO_Label
+PJ3.GPIO_Label=LCD_R4
+PJ3.Locked=true
+PJ3.Signal=LTDC_R4
+PJ4.GPIOParameters=GPIO_Label
+PJ4.GPIO_Label=LCD_R5
+PJ4.Locked=true
+PJ4.Signal=LTDC_R5
+PJ5.GPIOParameters=GPIO_Label
+PJ5.GPIO_Label=LCD_R6
+PJ5.Locked=true
+PJ5.Signal=LTDC_R6
+PJ6.GPIOParameters=GPIO_Label
+PJ6.GPIO_Label=LCD_R7
+PJ6.Locked=true
+PJ6.Signal=LTDC_R7
+PJ7.Locked=true
+PJ7.Signal=DEBUG_TRGIN
+PJ8.GPIOParameters=GPIO_Label
+PJ8.GPIO_Label=LCD_G1
+PJ8.Locked=true
+PJ8.Signal=LTDC_G1
+PJ9.GPIOParameters=GPIO_Label
+PJ9.GPIO_Label=LCD_G2
+PJ9.Locked=true
+PJ9.Signal=LTDC_G2
+PK0.GPIOParameters=GPIO_Label
+PK0.GPIO_Label=LCD_G5
+PK0.Locked=true
+PK0.Signal=LTDC_G5
+PK1.GPIOParameters=GPIO_Label
+PK1.GPIO_Label=LCD_G6
+PK1.Locked=true
+PK1.Signal=LTDC_G6
+PK2.GPIOParameters=GPIO_Label
+PK2.GPIO_Label=LCD_G7
+PK2.Locked=true
+PK2.Signal=LTDC_G7
+PK3.GPIOParameters=GPIO_Label
+PK3.GPIO_Label=LCD_B4
+PK3.Locked=true
+PK3.Signal=LTDC_B4
+PK4.GPIOParameters=GPIO_Label
+PK4.GPIO_Label=LCD_B5
+PK4.Locked=true
+PK4.Signal=LTDC_B5
+PK5.GPIOParameters=GPIO_Label
+PK5.GPIO_Label=LCD_B6
+PK5.Locked=true
+PK5.Signal=LTDC_B6
+PK6.GPIOParameters=GPIO_Label
+PK6.GPIO_Label=LCD_B7
+PK6.Locked=true
+PK6.Signal=LTDC_B7
+PK7.GPIOParameters=GPIO_Label
+PK7.GPIO_Label=LCD_DE
+PK7.Locked=true
+PK7.Signal=LTDC_DE
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H743XIHx
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=false
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=stm32h743eval.ioc
+ProjectManager.ProjectName=stm32h743eval
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=Makefile
+ProjectManager.ToolChainLocation=Src/
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.ADCFreq_Value=50390625
+RCC.AHB12Freq_Value=200000000
+RCC.AHB4Freq_Value=200000000
+RCC.APB1Freq_Value=100000000
+RCC.APB2Freq_Value=100000000
+RCC.APB3Freq_Value=100000000
+RCC.APB4Freq_Value=100000000
+RCC.AXIClockFreq_Value=200000000
+RCC.CECFreq_Value=32000
+RCC.CKPERFreq_Value=64000000
+RCC.CortexFreq_Value=400000000
+RCC.CpuClockFreq_Value=400000000
+RCC.D1CPREFreq_Value=400000000
+RCC.D1PPRE=RCC_APB3_DIV2
+RCC.D2PPRE1=RCC_APB1_DIV2
+RCC.D2PPRE2=RCC_APB2_DIV2
+RCC.D3PPRE=RCC_APB4_DIV2
+RCC.DFSDMACLkFreq_Value=200000000
+RCC.DFSDMFreq_Value=100000000
+RCC.DIVM1=5
+RCC.DIVM3=25
+RCC.DIVN1=160
+RCC.DIVN3=336
+RCC.DIVP1Freq_Value=400000000
+RCC.DIVP2Freq_Value=50390625
+RCC.DIVP3Freq_Value=168000000
+RCC.DIVQ1=4
+RCC.DIVQ1Freq_Value=200000000
+RCC.DIVQ2Freq_Value=50390625
+RCC.DIVQ3=7
+RCC.DIVQ3Freq_Value=48000000
+RCC.DIVR1=6
+RCC.DIVR1Freq_Value=133333333.33333333
+RCC.DIVR2Freq_Value=50390625
+RCC.DIVR3Freq_Value=168000000
+RCC.EnbaleCSS=true
+RCC.FDCANFreq_Value=200000000
+RCC.FMCFreq_Value=200000000
+RCC.FamilyName=M
+RCC.HCLK3ClockFreq_Value=200000000
+RCC.HCLKFreq_Value=200000000
+RCC.HPRE=RCC_HCLK_DIV2
+RCC.HPREFreq_Value=64000000
+RCC.HRTIMFreq_Value=200000000
+RCC.HSICalibrationValue=32
+RCC.I2C123Freq_Value=100000000
+RCC.I2C4Freq_Value=100000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HPREFreq_Value,HRTIMFreq_Value,HSICalibrationValue,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=100000000
+RCC.LPTIM2Freq_Value=100000000
+RCC.LPTIM345Freq_Value=100000000
+RCC.LPUART1Freq_Value=100000000
+RCC.LTDCFreq_Value=168000000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=400000000
+RCC.PLL2FRACN=0
+RCC.PLL3FRACN=0
+RCC.PLLFRACN=0
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1
+RCC.QSPIFreq_Value=200000000
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=200000000
+RCC.SAI23Freq_Value=200000000
+RCC.SAI4AFreq_Value=200000000
+RCC.SAI4BFreq_Value=200000000
+RCC.SDMMCFreq_Value=200000000
+RCC.SPDIFRXFreq_Value=200000000
+RCC.SPI123Freq_Value=200000000
+RCC.SPI45Freq_Value=100000000
+RCC.SPI6Freq_Value=100000000
+RCC.SWPMI1Freq_Value=100000000
+RCC.SYSCLKFreq_VALUE=400000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.Tim1OutputFreq_Value=200000000
+RCC.Tim2OutputFreq_Value=200000000
+RCC.TraceFreq_Value=133333333.33333333
+RCC.USART16Freq_Value=100000000
+RCC.USART234578Freq_Value=100000000
+RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3
+RCC.USBFreq_Value=48000000
+RCC.VCO1OutputFreq_Value=800000000
+RCC.VCO2OutputFreq_Value=100781250
+RCC.VCO3OutputFreq_Value=336000000
+RCC.VCOInput1Freq_Value=5000000
+RCC.VCOInput2Freq_Value=781250
+RCC.VCOInput3Freq_Value=1000000
+SH.ADCx_INN1.0=ADC1_INN1
+SH.ADCx_INN1.ConfNb=1
+SH.FMC_A0.0=FMC_A0
+SH.FMC_A0.ConfNb=1
+SH.FMC_A1.0=FMC_A1
+SH.FMC_A1.ConfNb=1
+SH.FMC_A10.0=FMC_A10
+SH.FMC_A10.ConfNb=1
+SH.FMC_A11.0=FMC_A11
+SH.FMC_A11.ConfNb=1
+SH.FMC_A12.0=FMC_A12
+SH.FMC_A12.ConfNb=1
+SH.FMC_A13.0=FMC_A13
+SH.FMC_A13.ConfNb=1
+SH.FMC_A14_BA0.0=FMC_BA0
+SH.FMC_A14_BA0.1=FMC_A14
+SH.FMC_A14_BA0.ConfNb=2
+SH.FMC_A15_BA1.0=FMC_BA1
+SH.FMC_A15_BA1.1=FMC_A15
+SH.FMC_A15_BA1.ConfNb=2
+SH.FMC_A16_CLE.0=FMC_A16
+SH.FMC_A16_CLE.ConfNb=1
+SH.FMC_A17_ALE.0=FMC_A17
+SH.FMC_A17_ALE.ConfNb=1
+SH.FMC_A18.0=FMC_A18
+SH.FMC_A18.ConfNb=1
+SH.FMC_A2.0=FMC_A2
+SH.FMC_A2.ConfNb=1
+SH.FMC_A3.0=FMC_A3
+SH.FMC_A3.ConfNb=1
+SH.FMC_A4.0=FMC_A4
+SH.FMC_A4.ConfNb=1
+SH.FMC_A5.0=FMC_A5
+SH.FMC_A5.ConfNb=1
+SH.FMC_A6.0=FMC_A6
+SH.FMC_A6.ConfNb=1
+SH.FMC_A7.0=FMC_A7
+SH.FMC_A7.ConfNb=1
+SH.FMC_A8.0=FMC_A8
+SH.FMC_A8.ConfNb=1
+SH.FMC_A9.0=FMC_A9
+SH.FMC_A9.ConfNb=1
+SH.FMC_D0_DA0.0=FMC_D0
+SH.FMC_D0_DA0.ConfNb=1
+SH.FMC_D10_DA10.0=FMC_D10
+SH.FMC_D10_DA10.ConfNb=1
+SH.FMC_D11_DA11.0=FMC_D11
+SH.FMC_D11_DA11.ConfNb=1
+SH.FMC_D12_DA12.0=FMC_D12
+SH.FMC_D12_DA12.ConfNb=1
+SH.FMC_D13_DA13.0=FMC_D13
+SH.FMC_D13_DA13.ConfNb=1
+SH.FMC_D14_DA14.0=FMC_D14
+SH.FMC_D14_DA14.ConfNb=1
+SH.FMC_D15_DA15.0=FMC_D15
+SH.FMC_D15_DA15.ConfNb=1
+SH.FMC_D16.0=FMC_D16
+SH.FMC_D16.ConfNb=1
+SH.FMC_D17.0=FMC_D17
+SH.FMC_D17.ConfNb=1
+SH.FMC_D18.0=FMC_D18
+SH.FMC_D18.ConfNb=1
+SH.FMC_D19.0=FMC_D19
+SH.FMC_D19.ConfNb=1
+SH.FMC_D1_DA1.0=FMC_D1
+SH.FMC_D1_DA1.ConfNb=1
+SH.FMC_D20.0=FMC_D20
+SH.FMC_D20.ConfNb=1
+SH.FMC_D21.0=FMC_D21
+SH.FMC_D21.ConfNb=1
+SH.FMC_D22.0=FMC_D22
+SH.FMC_D22.ConfNb=1
+SH.FMC_D23.0=FMC_D23
+SH.FMC_D23.ConfNb=1
+SH.FMC_D24.0=FMC_D24
+SH.FMC_D24.ConfNb=1
+SH.FMC_D25.0=FMC_D25
+SH.FMC_D25.ConfNb=1
+SH.FMC_D26.0=FMC_D26
+SH.FMC_D26.ConfNb=1
+SH.FMC_D27.0=FMC_D27
+SH.FMC_D27.ConfNb=1
+SH.FMC_D28.0=FMC_D28
+SH.FMC_D28.ConfNb=1
+SH.FMC_D29.0=FMC_D29
+SH.FMC_D29.ConfNb=1
+SH.FMC_D2_DA2.0=FMC_D2
+SH.FMC_D2_DA2.ConfNb=1
+SH.FMC_D30.0=FMC_D30
+SH.FMC_D30.ConfNb=1
+SH.FMC_D31.0=FMC_D31
+SH.FMC_D31.ConfNb=1
+SH.FMC_D3_DA3.0=FMC_D3
+SH.FMC_D3_DA3.ConfNb=1
+SH.FMC_D4_DA4.0=FMC_D4
+SH.FMC_D4_DA4.ConfNb=1
+SH.FMC_D5_DA5.0=FMC_D5
+SH.FMC_D5_DA5.ConfNb=1
+SH.FMC_D6_DA6.0=FMC_D6
+SH.FMC_D6_DA6.ConfNb=1
+SH.FMC_D7_DA7.0=FMC_D7
+SH.FMC_D7_DA7.ConfNb=1
+SH.FMC_D8_DA8.0=FMC_D8
+SH.FMC_D8_DA8.ConfNb=1
+SH.FMC_D9_DA9.0=FMC_D9
+SH.FMC_D9_DA9.ConfNb=1
+SH.FMC_NBL0.0=FMC_NBL0
+SH.FMC_NBL0.ConfNb=1
+SH.FMC_NBL1.0=FMC_NBL1
+SH.FMC_NBL1.ConfNb=1
+SH.FMC_NBL2.0=FMC_NBL2
+SH.FMC_NBL2.ConfNb=1
+SH.FMC_NBL3.0=FMC_NBL3
+SH.FMC_NBL3.ConfNb=1
+SH.FMC_NOE.0=FMC_NOE
+SH.FMC_NOE.ConfNb=1
+SH.FMC_NWAIT.0=FMC_NWAIT
+SH.FMC_NWAIT.ConfNb=1
+SH.FMC_NWE.0=FMC_NWE
+SH.FMC_NWE.ConfNb=1
+SH.FMC_SDCLK.0=FMC_SDCLK
+SH.FMC_SDCLK.ConfNb=1
+SH.FMC_SDNCAS.0=FMC_SDNCAS
+SH.FMC_SDNCAS.ConfNb=1
+SH.FMC_SDNRAS.0=FMC_SDNRAS
+SH.FMC_SDNRAS.ConfNb=1
+SH.FMC_SDNWE.0=FMC_SDNWE
+SH.FMC_SDNWE.ConfNb=1
+SH.GPXTI8.0=GPIO_EXTI8
+SH.GPXTI8.ConfNb=1
+SH.S_CKOUTDFSDM1.0=DFSDM1_CKOUT
+SH.S_CKOUTDFSDM1.ConfNb=1
+SH.S_DATAIN1DFSDM1.0=DFSDM1_DATIN1
+SH.S_DATAIN1DFSDM1.ConfNb=1
+USB_OTG_FS.IPParameters=VirtualMode
+USB_OTG_FS.VirtualMode=Device_Only
+USB_OTG_HS.IPParameters=VirtualMode-Device_HS
+USB_OTG_HS.VirtualMode-Device_HS=Device_HS
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=STM32H743I-EVAL2
+boardIOC=true
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug
new file mode 100644
index 000000000..0ab078319
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug
@@ -0,0 +1,245 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd");
+  Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd");
+  Project.AddSvdFile ("./STM32H743.svd");
+
+  Project.SetDevice ("STM32H743XI");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+  // timing delay for trace pins in pico seconds, default is 2 nano seconds
+  Project.SetTraceTiming (100, 100, 100, 100);
+
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-stm32h743eval/cdc_msc.elf");
+}
+
+/*********************************************************************
+*0
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging a RAM program on a Cortex-M target device
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  Exec.Reset();
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//
+//    Util.Log("Resetting Program.");
+//
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+
+void BeforeTargetConnect (void) {
+  //
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+  //
+  //Project.SetJLinkScript("./ST_STM32H743_Traceconfig.pex");
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+  Util.Log("___");
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake
new file mode 100644
index 000000000..021799775
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32h743xx)
+set(JLINK_DEVICE stm32h743xi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H743xx
+    HSE_VALUE=8000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
index 06148c875..0277d05c7 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 H743 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-h743zi.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,89 +36,127 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_0
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
 #define UART_DEV              USART3
 #define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOD
-#define UART_GPIO_AF          GPIO_AF7_USART3
-#define UART_TX_PIN           GPIO_PIN_8
-#define UART_RX_PIN           GPIO_PIN_9
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
 #define OTG_HS_VBUS_SENSE     0
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // VBUS0 EN
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  }
+};
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
+static inline void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /* The PWR block is always enabled on the H7 series- there is no clock
-     enable. For now, use the default VOS3 scale mode (lowest) and limit clock
-     frequencies to avoid potential current draw problems from bus
-     power when using the max clock speeds throughout the chip. */
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
 
-  /* Enable HSE Oscillator and activate PLL1 with HSE as source */
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
-  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 336;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 100;
   RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 7;
-  RCC_OscInitStruct.PLL.PLLR = 2; /* Unused */
-  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0;
-  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
   RCC_OscInitStruct.PLL.PLLFRACN = 0;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
 
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \
-    RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \
-    RCC_CLOCKTYPE_D3PCLK1);
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                                |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                                |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
-
-  /* Unlike on the STM32F4 family, it appears the maximum APB frequencies are
-     device-dependent- 120 MHz for this board according to Figure 2 of
-     the datasheet. Dividing by half will be safe for now. */
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
   RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
   RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 
-  /* 4 wait states required for 168MHz and VOS3. */
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 
-  /* Like on F4, on H7, USB's actual peripheral clock and bus clock are
-     separate. However, the main system PLL (PLL1) doesn't have a direct
-     connection to the USB peripheral clock to generate 48 MHz, so we do this
-     dance. This will connect PLL1's Q output to the USB peripheral clock. */
-  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
-
-  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
-  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
+  // Initialize USB clock
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.PLL3.PLL3M = 1;
+  PeriphClkInitStruct.PLL3.PLL3N = 24;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 4;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+  PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
-static inline void board_stm32h7_post_init(void)
-{
+static inline void board_init2(void) {
   // For this board does nothing
 }
 
+void board_vbus_set(uint8_t rhport, bool state) {
+  if (rhport == 0) {
+    board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+  }
+}
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
index fc670fe76..d904de6d2 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
@@ -1,10 +1,7 @@
+MCU_VARIANT = stm32h743xx
 CFLAGS += -DSTM32H743xx -DHSE_VALUE=8000000
 
-# Default is FulSpeed port
-PORT ?= 0
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
+LD_FILE_GCC = $(FAMILY_PATH)/linker/${MCU_VARIANT}_flash.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h743zi
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/cubemx/stm32h743nucleo.ioc b/hw/bsp/stm32h7/boards/stm32h743nucleo/cubemx/stm32h743nucleo.ioc
new file mode 100644
index 000000000..bc269a852
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/cubemx/stm32h743nucleo.ioc
@@ -0,0 +1,274 @@
+#MicroXplorer Configuration settings - do not modify
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+ETH.IPParameters=MediaInterface
+ETH.MediaInterface=HAL_ETH_RMII_MODE
+File.Version=6
+KeepUserPlacement=false
+Mcu.CPN=STM32H743ZIT6
+Mcu.Family=STM32H7
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=ETH
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IP5=USART3
+Mcu.IP6=USB_OTG_FS
+Mcu.IPNb=7
+Mcu.Name=STM32H743ZITx
+Mcu.Package=LQFP144
+Mcu.Pin0=PC13
+Mcu.Pin1=PC14-OSC32_IN (OSC32_IN)
+Mcu.Pin10=PC5
+Mcu.Pin11=PB0
+Mcu.Pin12=PB13
+Mcu.Pin13=PB14
+Mcu.Pin14=PD8
+Mcu.Pin15=PD9
+Mcu.Pin16=PD10
+Mcu.Pin17=PG7
+Mcu.Pin18=PA8
+Mcu.Pin19=PA9
+Mcu.Pin2=PC15-OSC32_OUT (OSC32_OUT)
+Mcu.Pin20=PA11
+Mcu.Pin21=PA12
+Mcu.Pin22=PG11
+Mcu.Pin23=PG13
+Mcu.Pin24=PE1
+Mcu.Pin25=VP_SYS_VS_Systick
+Mcu.Pin3=PH0-OSC_IN (PH0)
+Mcu.Pin4=PH1-OSC_OUT (PH1)
+Mcu.Pin5=PC1
+Mcu.Pin6=PA1
+Mcu.Pin7=PA2
+Mcu.Pin8=PA7
+Mcu.Pin9=PC4
+Mcu.PinsNb=26
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H743ZITx
+MxCube.Version=6.9.2
+MxDb.Version=DB.6.0.92
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA1.Locked=true
+PA1.Mode=RMII
+PA1.Signal=ETH_REF_CLK
+PA11.Locked=true
+PA11.Mode=Device_Only
+PA11.Signal=USB_OTG_FS_DM
+PA12.Locked=true
+PA12.Mode=Device_Only
+PA12.Signal=USB_OTG_FS_DP
+PA2.Locked=true
+PA2.Mode=RMII
+PA2.Signal=ETH_MDIO
+PA7.Locked=true
+PA7.Mode=RMII
+PA7.Signal=ETH_CRS_DV
+PA8.Locked=true
+PA8.Mode=Activate_SOF_FS
+PA8.Signal=USB_OTG_FS_SOF
+PA9.Locked=true
+PA9.Mode=Activate_VBUS
+PA9.Signal=USB_OTG_FS_VBUS
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=LD1 [Green Led]
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PB13.Locked=true
+PB13.Mode=RMII
+PB13.Signal=ETH_TXD1
+PB14.GPIOParameters=GPIO_Label
+PB14.GPIO_Label=LD3 [Red Led]
+PB14.Locked=true
+PB14.Signal=GPIO_Output
+PC1.Locked=true
+PC1.Mode=RMII
+PC1.Signal=ETH_MDC
+PC13.GPIOParameters=GPIO_Label
+PC13.GPIO_Label=B1 [Blue PushButton]
+PC13.Locked=true
+PC13.Signal=GPIO_Input
+PC14-OSC32_IN\ (OSC32_IN).Locked=true
+PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator
+PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN
+PC15-OSC32_OUT\ (OSC32_OUT).Locked=true
+PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator
+PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT
+PC4.Locked=true
+PC4.Mode=RMII
+PC4.Signal=ETH_RXD0
+PC5.Locked=true
+PC5.Mode=RMII
+PC5.Signal=ETH_RXD1
+PD10.GPIOParameters=GPIO_Label
+PD10.GPIO_Label=USB_OTG_FS_PWR_EN
+PD10.Locked=true
+PD10.Signal=GPIO_Output
+PD8.GPIOParameters=GPIO_Label
+PD8.GPIO_Label=STLINK_RX
+PD8.Locked=true
+PD8.Mode=Asynchronous
+PD8.Signal=USART3_TX
+PD9.GPIOParameters=GPIO_Label
+PD9.GPIO_Label=STLINK_TX
+PD9.Locked=true
+PD9.Mode=Asynchronous
+PD9.Signal=USART3_RX
+PE1.GPIOParameters=GPIO_Label
+PE1.GPIO_Label=LD2 [Yellow Led]
+PE1.Locked=true
+PE1.Signal=GPIO_Output
+PG11.Locked=true
+PG11.Mode=RMII
+PG11.Signal=ETH_TX_EN
+PG13.Locked=true
+PG13.Mode=RMII
+PG13.Signal=ETH_TXD0
+PG7.GPIOParameters=GPIO_Label
+PG7.GPIO_Label=USB_OTG_FS_OVCR
+PG7.Locked=true
+PG7.Signal=GPXTI7
+PH0-OSC_IN\ (PH0).Locked=true
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Clock-Source
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT\ (PH1).Locked=true
+PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H743ZITx
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.1
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=STM32CubeIDE
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=stm32h743nucleo.ioc
+ProjectManager.ProjectName=stm32h743nucleo
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=Makefile
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,false-3-MX_ETH_Init-ETH-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.ADCFreq_Value=16125000
+RCC.AHB12Freq_Value=200000000
+RCC.AHB4Freq_Value=200000000
+RCC.APB1Freq_Value=100000000
+RCC.APB2Freq_Value=100000000
+RCC.APB3Freq_Value=100000000
+RCC.APB4Freq_Value=100000000
+RCC.AXIClockFreq_Value=200000000
+RCC.CECFreq_Value=32000
+RCC.CKPERFreq_Value=64000000
+RCC.CortexFreq_Value=400000000
+RCC.CpuClockFreq_Value=400000000
+RCC.D1CPREFreq_Value=400000000
+RCC.D1PPRE=RCC_APB3_DIV2
+RCC.D2PPRE1=RCC_APB1_DIV2
+RCC.D2PPRE2=RCC_APB2_DIV2
+RCC.D3PPRE=RCC_APB4_DIV2
+RCC.DFSDMACLkFreq_Value=200000000
+RCC.DFSDMFreq_Value=100000000
+RCC.DIVM1=1
+RCC.DIVM3=1
+RCC.DIVN1=100
+RCC.DIVN3=24
+RCC.DIVP1Freq_Value=400000000
+RCC.DIVP2Freq_Value=16125000
+RCC.DIVP3Freq_Value=96000000
+RCC.DIVQ1=4
+RCC.DIVQ1Freq_Value=200000000
+RCC.DIVQ2Freq_Value=16125000
+RCC.DIVQ3=4
+RCC.DIVQ3Freq_Value=48000000
+RCC.DIVR1Freq_Value=400000000
+RCC.DIVR2Freq_Value=16125000
+RCC.DIVR3Freq_Value=96000000
+RCC.FDCANFreq_Value=200000000
+RCC.FMCFreq_Value=200000000
+RCC.FamilyName=M
+RCC.HCLK3ClockFreq_Value=200000000
+RCC.HCLKFreq_Value=200000000
+RCC.HPRE=RCC_HCLK_DIV2
+RCC.HRTIMFreq_Value=200000000
+RCC.HSE_VALUE=8000000
+RCC.I2C123Freq_Value=100000000
+RCC.I2C4Freq_Value=100000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=100000000
+RCC.LPTIM2Freq_Value=100000000
+RCC.LPTIM345Freq_Value=100000000
+RCC.LPUART1Freq_Value=100000000
+RCC.LTDCFreq_Value=96000000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=400000000
+RCC.PLL2FRACN=0
+RCC.PLL3FRACN=0
+RCC.PLLFRACN=0
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1
+RCC.QSPIFreq_Value=200000000
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=200000000
+RCC.SAI23Freq_Value=200000000
+RCC.SAI4AFreq_Value=200000000
+RCC.SAI4BFreq_Value=200000000
+RCC.SDMMCFreq_Value=200000000
+RCC.SPDIFRXFreq_Value=200000000
+RCC.SPI123Freq_Value=200000000
+RCC.SPI45Freq_Value=100000000
+RCC.SPI6Freq_Value=100000000
+RCC.SWPMI1Freq_Value=100000000
+RCC.SYSCLKFreq_VALUE=400000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.Tim1OutputFreq_Value=200000000
+RCC.Tim2OutputFreq_Value=200000000
+RCC.TraceFreq_Value=64000000
+RCC.USART16Freq_Value=100000000
+RCC.USART234578Freq_Value=100000000
+RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3
+RCC.USBFreq_Value=48000000
+RCC.VCO1OutputFreq_Value=800000000
+RCC.VCO2OutputFreq_Value=32250000
+RCC.VCO3OutputFreq_Value=192000000
+RCC.VCOInput1Freq_Value=8000000
+RCC.VCOInput2Freq_Value=250000
+RCC.VCOInput3Freq_Value=8000000
+SH.GPXTI7.0=GPIO_EXTI7
+SH.GPXTI7.ConfNb=1
+USART3.IPParameters=VirtualMode-Asynchronous
+USART3.VirtualMode-Asynchronous=VM_ASYNC
+USB_OTG_FS.IPParameters=VirtualMode
+USB_OTG_FS.VirtualMode=Device_Only
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=NUCLEO-H743ZI2
+boardIOC=true
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
new file mode 100644
index 000000000..39a9d5798
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT stm32h745xx)
+set(JLINK_DEVICE stm32h745xi_m7)
+
+set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_CM7.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash_CM7.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H745xx
+    HSE_VALUE=25000000
+    CORE_CM7
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.h b/hw/bsp/stm32h7/boards/stm32h745disco/board.h
index d33e0c8eb..ebdd5a17a 100644
--- a/hw/bsp/stm32h7/boards/stm32h745disco/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 H745 Discovery
+   url: https://www.st.com/en/evaluation-tools/stm32h745i-disco.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -31,35 +36,56 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOJ
-#define LED_PIN               GPIO_PIN_2
-#define LED_STATE_ON          1
-
-// Blue push-button
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
 // UART
 #define UART_DEV              USART3
 #define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOB
-#define UART_GPIO_AF          GPIO_AF7_USART3
-#define UART_TX_PIN           GPIO_PIN_10
-#define UART_RX_PIN           GPIO_PIN_11
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
 #define OTG_HS_VBUS_SENSE     0
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOJ,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // VBUS0 EN
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_5, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  }
+};
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
+static inline void SystemClock_Config(void)
 {
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
 
   /*!< Supply configuration update enable */
   /* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */
@@ -127,11 +153,17 @@ static inline void board_stm32h7_clock_init(void)
   HAL_EnableCompensationCell();
 }
 
-static inline void board_stm32h7_post_init(void)
-{
+static inline void board_init2(void) {
   // For this board does nothing
 }
 
+void board_vbus_set(uint8_t rhport, bool state) {
+  if (rhport == 0) {
+    board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+  }
+}
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
index 384065bde..588620ce2 100644
--- a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
@@ -1,17 +1,16 @@
 # STM32H745I-DISCO uses OTG_FS
 # FIXME: Reset enumerates, un/replug USB plug does not enumerate
-
+MCU_VARIANT = stm32h745xx
 CFLAGS += -DSTM32H745xx -DCORE_CM7 -DHSE_VALUE=25000000
 
 # Default is FulSpeed port
 PORT ?= 0
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h745xx.s
-LD_FILE = $(ST_CMSIS)/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld
+LD_FILE_GCC = $(ST_CMSIS)/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h745xi_m7
 
 # flash target using on-board stlink
 flash: flash-stlink
-
diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake b/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake
new file mode 100644
index 000000000..6eab26c07
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT stm32h750xx)
+set(JLINK_DEVICE stm32h750vb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${MCU_VARIANT}_flash_CM7.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H750xx
+    HSE_VALUE=25000000
+    CORE_CM7
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h
new file mode 100644
index 000000000..e11a55103
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h
@@ -0,0 +1,156 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 H750 WeAct
+   url: https://www.adafruit.com/product/5032
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// UART
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     0
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOE,
+    .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  }
+};
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  // Supply configuration update enable
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+  // Configure the main internal regulator output voltage
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  // Configure the PLL clock source
+  __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
+
+  // Initializes the CPU, AHB and APB busses clocks
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 96;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  // Initializes the CPU, AHB and APB busses clocks
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_SPI4
+                              |RCC_PERIPHCLK_SPI1|RCC_PERIPHCLK_USB
+                              |RCC_PERIPHCLK_QSPI;
+  PeriphClkInitStruct.PLL3.PLL3M = 10;
+  PeriphClkInitStruct.PLL3.PLL3N = 96;
+  PeriphClkInitStruct.PLL3.PLL3P = 5;
+  PeriphClkInitStruct.PLL3.PLL3Q = 5;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+  PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1;
+  PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK;
+  PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
+  PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  // Enable USB Voltage detector
+  HAL_PWREx_EnableUSBVoltageDetector();
+}
+
+static inline void board_init2(void) {
+  // For this board does nothing
+}
+
+void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport; (void) state;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk b/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk
new file mode 100644
index 000000000..988fed804
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk
@@ -0,0 +1,12 @@
+# STM32H745I-DISCO uses OTG_FS
+# FIXME: Reset enumerates, un/replug USB plug does not enumerate
+MCU_VARIANT = stm32h750xx
+CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=25000000
+
+LD_FILE_GCC = $(BOARD_PATH)/stm32h750xx_flash_CM7.ld
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h750vb
+
+# flash target using on-board stlink
+flash: flash-jlink
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld
similarity index 78%
rename from hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
rename to hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld
index 59b9ff4df..30f220a42 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
+++ b/hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld
@@ -1,11 +1,12 @@
 /*
-*****************************************************************************
+******************************************************************************
 **
 
 **  File        : LinkerScript.ld
 **
-**  Abstract    : Linker script for STM32H743XIHx Device with
-**                2048KByte FLASH, 128KByte RAM
+**
+**  Abstract    : Linker script for STM32H7 series
+**                128Kbytes FLASH and 1Mbytes RAM
 **
 **                Set heap size, stack size and stack location according
 **                to application requirements.
@@ -14,19 +15,21 @@
 **
 **  Target      : STMicroelectronics STM32
 **
-**
-**  Distribution: The file is distributed as is, without any warranty
+**  Distribution: The file is distributed īŋŊas is,īŋŊ without any warranty
 **                of any kind.
 **
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
 *****************************************************************************
+** @attention
+**
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+****************************************************************************
 */
 
 /* Entry Point */
@@ -41,12 +44,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 /* Specify the memory areas */
 MEMORY
 {
-DTCMRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-RAM_D1 (xrw)      : ORIGIN = 0x24000000, LENGTH = 512K
-RAM_D2 (xrw)      : ORIGIN = 0x30000000, LENGTH = 288K
-RAM_D3 (xrw)      : ORIGIN = 0x38000000, LENGTH = 64K
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 1M
 ITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K
 }
 
 /* Define output sections */
@@ -118,7 +118,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -127,14 +127,14 @@ SECTIONS
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
-  } >DTCMRAM AT> FLASH
+  } >RAM AT> FLASH
+
 
-  
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -144,7 +144,7 @@ SECTIONS
     . = ALIGN(4);
     _ebss = .;         /* define a global symbol at bss end */
     __bss_end__ = _ebss;
-  } >DTCMRAM
+  } >RAM
 
   /* User_heap_stack section, used to check that there is enough RAM left */
   ._user_heap_stack :
@@ -155,9 +155,8 @@ SECTIONS
     . = . + _Min_Heap_Size;
     . = . + _Min_Stack_Size;
     . = ALIGN(8);
-  } >DTCMRAM
+  } >RAM
 
-  
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -169,5 +168,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake
new file mode 100644
index 000000000..72a139ab6
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT stm32h750xx)
+set(JLINK_DEVICE stm32h750xb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${MCU_VARIANT}_flash_CM7.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H750xx
+    HSE_VALUE=25000000
+    CORE_CM7
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.h b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h
new file mode 100644
index 000000000..ac417601b
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h
@@ -0,0 +1,169 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 H750b Discovery Kit
+   url: https://www.st.com/en/evaluation-tools/stm32h750b-dk.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// UART
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     0
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_VBUS0_EN 4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOJ,
+    .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // VBUS0 EN
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_5, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  }
+};
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+
+  /*!< Supply configuration update enable */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+  /* The voltage scaling allows optimizing the power consumption when the
+     device is clocked below the maximum system frequency, to update the
+     voltage scaling value regarding system frequency refer to product
+     datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+  /* PLL1 for System Clock */
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 160;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* PLL3 for USB Clock */
+  PeriphClkInitStruct.PLL3.PLL3M = 25;
+  PeriphClkInitStruct.PLL3.PLL3N = 336;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 7;
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure  bus clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
+  RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
+
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  /*activate CSI clock mondatory for I/O Compensation Cell*/
+  __HAL_RCC_CSI_ENABLE() ;
+
+  /* Enable SYSCFG clock mondatory for I/O Compensation Cell */
+  __HAL_RCC_SYSCFG_CLK_ENABLE() ;
+
+  /* Enables the I/O Compensation Cell */
+  HAL_EnableCompensationCell();
+}
+
+static inline void board_init2(void) {
+  // For this board does nothing
+}
+
+void board_vbus_set(uint8_t rhport, bool state) {
+  if (rhport == 0) {
+    board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+  }
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk
new file mode 100644
index 000000000..6eb3eb498
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk
@@ -0,0 +1,12 @@
+# STM32H745I-DISCO uses OTG_FS
+# FIXME: Reset enumerates, un/replug USB plug does not enumerate
+MCU_VARIANT = stm32h750xx
+CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=25000000
+
+LD_FILE_GCC = $(BOARD_PATH)/stm32h750xx_flash_CM7.ld
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h750xb
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/stm32h750xx_flash_CM7.ld b/hw/bsp/stm32h7/boards/stm32h750bdk/stm32h750xx_flash_CM7.ld
new file mode 100644
index 000000000..30f220a42
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h750bdk/stm32h750xx_flash_CM7.ld
@@ -0,0 +1,170 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**
+**  Abstract    : Linker script for STM32H7 series
+**                128Kbytes FLASH and 1Mbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed īŋŊas is,īŋŊ without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 1M
+ITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake
new file mode 100644
index 000000000..3aaa81612
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake
@@ -0,0 +1,26 @@
+set(MCU_VARIANT stm32h743xx)
+set(JLINK_DEVICE stm32h743xi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
+
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H743xx
+    HSE_VALUE=8000000
+    HAL_TIM_MODULE_ENABLED
+    )
+  target_sources(${TARGET} PUBLIC
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_tim.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_tim_ex.c
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
index 09442c233..bfaf42784 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
@@ -26,6 +26,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: Waveshare Open H743i
+   url: https://www.waveshare.com/openh743i-c-standard.htm
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -70,22 +75,9 @@
  extern "C" {
 #endif
 
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_6
-#define LED_STATE_ON          1
-
-// Tamper push-button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
 // Need to change jumper setting J7 and J8 from RS-232 to STLink
 #define UART_DEV              USART3
 #define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOD
-#define UART_GPIO_AF          GPIO_AF7_USART3
-#define UART_TX_PIN           GPIO_PIN_8
-#define UART_RX_PIN           GPIO_PIN_9
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
@@ -101,10 +93,49 @@
 #define ULPI_RST_PORT GPIOD
 #define ULPI_RST_PIN GPIO_PIN_14
 
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+
+  { // I2C SCL for MFX VBUS
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_I2C1 },
+    .active_state = 0
+  },
+  { // I2C SDA for MFX VBUS
+    .port = GPIOB,
+    .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_I2C1 },
+    .active_state = 1
+  },
+};
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
+static inline void SystemClock_Config(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
@@ -178,20 +209,27 @@ static inline void board_stm32h7_clock_init(void)
 static inline void timer_board_delay(TIM_HandleTypeDef* tim_hdl, uint32_t ms)
 {
   uint32_t startMs = __HAL_TIM_GET_COUNTER(tim_hdl);
-  while ((__HAL_TIM_GET_COUNTER(tim_hdl) - startMs) < ms)
-  {
+  while ((__HAL_TIM_GET_COUNTER(tim_hdl) - startMs) < ms) {
     asm("nop"); //do nothing
   }
 }
 
-static inline void board_stm32h7_post_init(void)
+static inline void board_init2(void)
 {
-  // walkaround for reseting the ULPI PHY using Timer since systick is not
+  // walkaround for resetting the ULPI PHY using Timer since systick is not
   // available when RTOS is used.
 
   // Init timer
   TIM_HandleTypeDef tim2Handle;
   TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  GPIO_InitTypeDef  GPIO_InitStruct;
+
+  // ULPI_RST
+  GPIO_InitStruct.Pin   = ULPI_RST_PIN;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull  = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = 0;
+  HAL_GPIO_Init(ULPI_RST_PORT, &GPIO_InitStruct);
 
   __HAL_RCC_TIM2_CLK_ENABLE();
 
@@ -212,9 +250,9 @@ static inline void board_stm32h7_post_init(void)
 
   // Reset PHY, change the delays as you see fit
   timer_board_delay(&tim2Handle, 5U);
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 1U);
+  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, GPIO_PIN_SET);
   timer_board_delay(&tim2Handle, 20U);
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 0U);
+  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, GPIO_PIN_RESET);
   timer_board_delay(&tim2Handle, 20U);
 
   //Disable the timer used for delays
@@ -222,6 +260,11 @@ static inline void board_stm32h7_post_init(void)
   __HAL_RCC_TIM2_CLK_DISABLE();
 }
 
+// need to short a jumper
+void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport; (void) state;
+}
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
index 4dfcc1cac..5ff2f4165 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
@@ -1,10 +1,11 @@
+MCU_VARIANT = stm32h743xx
 CFLAGS += -DSTM32H743xx -DHSE_VALUE=8000000
 
-# Default is HS port
-PORT ?= 1
+RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/STM32H743IITX_FLASH.ld
+LD_FILE_GCC = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
 
 # Use Timer module for ULPI PHY reset
 CFLAGS += -DHAL_TIM_MODULE_ENABLED
@@ -16,4 +17,4 @@ SRC_C += \
 JLINK_DEVICE = stm32h743ii
 
 # flash target using jlink
-flash: flash-jlink
\ No newline at end of file
+flash: flash-jlink
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 3964f427a..e5228b29b 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -27,53 +27,99 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32h7xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
+
+TU_ATTR_UNUSED static void Error_Handler(void) { }
+
+typedef struct {
+  GPIO_TypeDef* port;
+  GPIO_InitTypeDef pin_init;
+  uint8_t active_state;
+} board_pindef_t;
+
 #include "board.h"
 
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-
-// Despite being call USB2_OTG
-// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-// Despite being call USB2_OTG
-// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-void OTG_HS_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-UART_HandleTypeDef UartHandle;
+#ifdef UART_DEV
+UART_HandleTypeDef UartHandle = {
+  .Instance = UART_DEV,
+  .Init = {
+    .BaudRate = CFG_BOARD_UART_BAUDRATE,
+    .WordLength = UART_WORDLENGTH_8B,
+    .StopBits = UART_STOPBITS_1,
+    .Parity = UART_PARITY_NONE,
+    .HwFlowCtl = UART_HWCONTROL_NONE,
+    .Mode = UART_MODE_TX_RX,
+    .OverSampling = UART_OVERSAMPLING_16,
+  }
+};
+#endif
 
-void board_init(void)
-{
-  board_stm32h7_clock_init();
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+// Despite being call USB2_OTG_FS on some MCUs
+// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
+void OTG_FS_IRQHandler(void) {
+  tusb_int_handler(0, true);
+}
+
+// Despite being call USB1_OTG_HS on some MCUs
+// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
+void OTG_HS_IRQHandler(void) {
+  tusb_int_handler(1, true);
+}
+
+#ifdef TRACE_ETM
+void trace_etm_init(void) {
+  // H7 trace pin is PE2 to PE6
+  GPIO_InitTypeDef  gpio_init;
+  gpio_init.Pin       = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6;
+  gpio_init.Mode      = GPIO_MODE_AF_PP;
+  gpio_init.Pull      = GPIO_PULLUP;
+  gpio_init.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_init.Alternate = GPIO_AF0_TRACE;
+  HAL_GPIO_Init(GPIOE, &gpio_init);
+
+  // Enable trace clk, also in D1 and D3 domain
+  DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN;
+}
+#else
+  #define trace_etm_init()
+#endif
+
+void board_init(void) {
+  // Implemented in board.h
+  SystemClock_Config();
 
   // Enable All GPIOs clocks
   __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE(); // USB ULPI NXT
-  __HAL_RCC_GPIOC_CLK_ENABLE(); // USB ULPI NXT
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
   __HAL_RCC_GPIOE_CLK_ENABLE();
-  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
   __HAL_RCC_GPIOG_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE(); // USB ULPI NXT
-  __HAL_RCC_GPIOI_CLK_ENABLE(); // USB ULPI NXT
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+#ifdef __HAL_RCC_GPIOI_CLK_ENABLE
+  __HAL_RCC_GPIOI_CLK_ENABLE();
+#endif
   __HAL_RCC_GPIOJ_CLK_ENABLE();
 
-  // Enable UART Clock
-  UART_CLK_EN();
+  trace_etm_init();
+
+  for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
+    HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
+  }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -84,45 +130,21 @@ void board_init(void)
   SysTick->CTRL &= ~1U;
 
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  #ifdef USB_OTG_FS_PERIPH_BASE
   NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  #endif
+
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
-  
-  GPIO_InitTypeDef  GPIO_InitStruct;
 
-  // LED
-  GPIO_InitStruct.Pin   = LED_PIN;
-  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull  = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+  GPIO_InitTypeDef GPIO_InitStruct;
 
-  // Button
-  GPIO_InitStruct.Pin   = BUTTON_PIN;
-  GPIO_InitStruct.Mode  = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull  = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // Uart
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
-
-  UartHandle.Instance        = UART_DEV;
-  UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
-  UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits   = UART_STOPBITS_1;
-  UartHandle.Init.Parity     = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode       = UART_MODE_TX_RX;
-  UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
+#ifdef UART_DEV
+  UART_CLK_EN();
   HAL_UART_Init(&UartHandle);
+#endif
 
-#if BOARD_TUD_RHPORT == 0
+  //------------- USB FS -------------//
   // Despite being call USB2_OTG
   // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
   // PA9 VUSB, PA10 ID, PA11 DM, PA12 DP
@@ -166,20 +188,18 @@ void board_init(void)
   USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 #endif // vbus sense
 
-#elif BOARD_TUD_RHPORT == 1
+  //------------- USB HS -------------//
+#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
   // Despite being call USB2_OTG
   // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-
   struct {
     GPIO_TypeDef* port;
     uint32_t pin;
-  } const ulpi_pins[] =
-  {
+  } const ulpi_pins[] = {
     ULPI_PINS
   };
 
-  for (uint8_t i=0; i < sizeof(ulpi_pins)/sizeof(ulpi_pins[0]); i++)
-  {
+  for (uint8_t i=0; i < sizeof(ulpi_pins)/sizeof(ulpi_pins[0]); i++) {
     GPIO_InitStruct.Pin       = ulpi_pins[i].pin;
     GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull      = GPIO_NOPULL;
@@ -206,12 +226,15 @@ void board_init(void)
   // Force device mode
   USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
   USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+#endif
 
   HAL_PWREx_EnableUSBVoltageDetector();
 
-  // For waveshare openh743 ULPI PHY reset walkaround
-  board_stm32h7_post_init();
-#endif // rhport = 1
+  board_init2(); // optional init
+
+#if CFG_TUH_ENABLED
+  board_vbus_set(BOARD_TUH_RHPORT, 1);
+#endif
 
 }
 
@@ -219,50 +242,74 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+#ifdef PINID_LED
+  board_pindef_t* pindef = &board_pindef[PINID_LED];
+  GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET;
+  HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state);
+#else
+  (void) state;
+#endif
 }
 
-uint32_t board_button_read(void)
-{
-  return (BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN)) ? 1 : 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+uint32_t board_button_read(void) {
+#ifdef PINID_BUTTON
+  board_pindef_t* pindef = &board_pindef[PINID_BUTTON];
+  return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin);
+#else
   return 0;
+#endif
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
   return len;
 }
 
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
+  buf, len, 0xffff);
+  return len;
+#else
+  (void) buf; (void) len;
+  return -1;
+#endif
+}
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler(void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
new file mode 100644
index 000000000..b4f0bebbf
--- /dev/null
+++ b/hw/bsp/stm32h7/family.cmake
@@ -0,0 +1,149 @@
+include_guard()
+
+set(ST_FAMILY h7)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(ST_MFXSTM32L152 ${TOP}/hw/mcu/st/stm32-mfxstm32l152)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m7 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32H7 CACHE INTERNAL "")
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif ()
+
+if (NOT DEFINED RHPORT_SPEED)
+  # Most F7 does not has built-in HS PHY
+  set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if(NOT DEFINED LD_FILE_IAR)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+  endif()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+    BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+    BOARD_TUH_RHPORT=${RHPORT_HOST}
+    BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32H7)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index a1cd93b27..29b83cf7d 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -1,50 +1,83 @@
-UF2_FAMILY_ID = 0x6db66082
 ST_FAMILY = h7
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
+ST_PREFIX = stm32${ST_FAMILY}xx
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver
+ST_MFXSTM32L152 = hw/mcu/st/stm32-mfxstm32l152
+
+UF2_FAMILY_ID = 0x6db66082
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m7
 
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32H7 \
-	-DBOARD_TUD_RHPORT=$(PORT)
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
 
-ifeq ($(PORT), 1)
-  ifeq ($(SPEED), high)
-    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    $(info "Using OTG_HS in HighSpeed mode")
-  else
-    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
-    $(info "Using OTG_HS in FullSpeed mode")
-  endif
+# Determine RHPORT_DEVICE_SPEED if not defined
+ifndef RHPORT_DEVICE_SPEED
+ifeq ($(RHPORT_DEVICE), 0)
+  RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED))
 else
-  $(info "Using OTG_FS")
+  RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED))
+endif
 endif
 
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+# Determine RHPORT_HOST_SPEED if not defined
+ifndef RHPORT_HOST_SPEED
+ifeq ($(RHPORT_HOST), 0)
+  RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
 
-# All source paths should be relative to the top level.
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32H7 \
+	-DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
+	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
+	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
+	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
+
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+
+# suppress warning caused by vendor mcu driver
+CFLAGS_GCC += \
+  -Wno-error=cast-align \
+  -Wno-error=unused-parameter \
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
+	$(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \
+  ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c \
+  ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c_ex.c \
+  $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
@@ -52,6 +85,9 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
 
+# Linker
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32h7/linker/stm32h723xx_flash.ld b/hw/bsp/stm32h7/linker/stm32h723xx_flash.ld
new file mode 100644
index 000000000..b779c0d35
--- /dev/null
+++ b/hw/bsp/stm32h7/linker/stm32h723xx_flash.ld
@@ -0,0 +1,192 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32H7 series
+**                1024Kbytes FLASH and 560Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Specify the memory areas */
+MEMORY
+{
+  ITCMRAM (xrw)    : ORIGIN = 0x00000000,   LENGTH = 64K
+  DTCMRAM (xrw)    : ORIGIN = 0x20000000,   LENGTH = 128K
+  FLASH    (rx)    : ORIGIN = 0x08000000,   LENGTH = 1024K
+  RAM_D1  (xrw)    : ORIGIN = 0x24000000,   LENGTH = 320K
+  RAM_D2  (xrw)    : ORIGIN = 0x30000000,   LENGTH = 32K
+  RAM_D3  (xrw)    : ORIGIN = 0x38000000,   LENGTH = 16K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM_D1 AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM_D1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM_D1
+
+  .usbx_data 0x24027000 (NOLOAD):
+  {
+    *(.UsbHpcdSection)
+
+  } >RAM_D1
+
+  .uart_bss 0x24028000 (NOLOAD):
+  {
+    *(.UsbxAppSection)
+
+  } >RAM_D1
+
+  .usbx_bss 0x24029000 (NOLOAD):
+  {
+    *(.UsbxPoolSection)
+
+  } >RAM_D1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld b/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld
similarity index 90%
rename from hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
rename to hw/bsp/stm32h7/linker/stm32h743xx_flash.ld
index 59b9ff4df..ba18c8cd1 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
+++ b/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld
@@ -32,23 +32,24 @@
 /* Entry Point */
 ENTRY(Reset_Handler)
 
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
 /* Specify the memory areas */
 MEMORY
 {
-DTCMRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-RAM_D1 (xrw)      : ORIGIN = 0x24000000, LENGTH = 512K
-RAM_D2 (xrw)      : ORIGIN = 0x30000000, LENGTH = 288K
-RAM_D3 (xrw)      : ORIGIN = 0x38000000, LENGTH = 64K
-ITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K
+    DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
+    RAM_D1 (xrw)  : ORIGIN = 0x24000000, LENGTH = 512K
+    RAM_D2 (xrw)  : ORIGIN = 0x30000000, LENGTH = 288K
+    RAM_D3 (xrw)  : ORIGIN = 0x38000000, LENGTH = 64K
+    ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
+    FLASH (rx)    : ORIGIN = 0x08000000, LENGTH = 2048K
+
 }
 
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
 /* Define output sections */
 SECTIONS
 {
@@ -118,7 +119,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -127,14 +128,14 @@ SECTIONS
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
-  } >DTCMRAM AT> FLASH
+  } >RAM_D1 AT> FLASH
+
 
-  
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -144,7 +145,9 @@ SECTIONS
     . = ALIGN(4);
     _ebss = .;         /* define a global symbol at bss end */
     __bss_end__ = _ebss;
-  } >DTCMRAM
+  } >RAM_D1
+
+
 
   /* User_heap_stack section, used to check that there is enough RAM left */
   ._user_heap_stack :
@@ -155,9 +158,7 @@ SECTIONS
     . = . + _Min_Heap_Size;
     . = . + _Min_Stack_Size;
     . = ALIGN(8);
-  } >DTCMRAM
-
-  
+  } >RAM_D1
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -169,5 +170,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32h7/stm32h7xx_hal_conf.h b/hw/bsp/stm32h7/stm32h7xx_hal_conf.h
index a7cc6d826..303dcc137 100644
--- a/hw/bsp/stm32h7/stm32h7xx_hal_conf.h
+++ b/hw/bsp/stm32h7/stm32h7xx_hal_conf.h
@@ -1,7 +1,7 @@
 /**
   ******************************************************************************
   * @file    stm32h7xx_hal_conf_template.h
-  * @brief   HAL configuration template file. 
+  * @brief   HAL configuration template file.
   *          This file should be copied to the application folder and renamed
   *          to stm32h7xx_hal_conf.h.
   ******************************************************************************
@@ -32,7 +32,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32H7xx_HAL_CONF_H
@@ -70,7 +70,7 @@
 /* #define HAL_HCD_MODULE_ENABLED */
 /* #define HAL_HRTIM_MODULE_ENABLED */
 /* #define HAL_HSEM_MODULE_ENABLED */
-/* #define HAL_I2C_MODULE_ENABLED */
+#define HAL_I2C_MODULE_ENABLED
 /* #define HAL_I2S_MODULE_ENABLED */
 /* #define HAL_IRDA_MODULE_ENABLED */
 /* #define HAL_IWDG_MODULE_ENABLED */
@@ -478,6 +478,6 @@
 #endif
 
 #endif /* __STM32H7xx_HAL_CONF_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32l0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32l0/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..40146e73a
--- /dev/null
+++ b/hw/bsp/stm32l0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32l0xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        0
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
index 1bc16cc7b..d4d5b6ca5 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.cmake b/hw/bsp/stm32l0/boards/stm32l052dap52/board.cmake
new file mode 100644
index 000000000..56b58f626
--- /dev/null
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32l052xx)
+set(JLINK_DEVICE stm32l052k8)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L052K8Ux_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L052xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
index 8ad3e43c8..50bbafadb 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 L052 DAP
+   url: n/a
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -54,47 +59,48 @@
 //--------------------------------------------------------------------+
 static inline void board_stm32l0_clock_init(void)
 {
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
-  static RCC_CRSInitTypeDef RCC_CRSInitStruct;
-  
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = {0};
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+
   /* Enable HSI Oscillator to be used as System clock source
      Enable HSI48 Oscillator to be used as USB clock source */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
   RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct); 
- 
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
   /* Select HSI48 as USB clock source */
   PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
   PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-  
-  /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2 
+
+  /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2
      clock dividers */
   RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;  
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;  
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-    
+
   /*Configure the clock recovery system (CRS)**********************************/
-  
+
   /*Enable CRS Clock*/
-  __HAL_RCC_CRS_CLK_ENABLE(); 
-  
+  __HAL_RCC_CRS_CLK_ENABLE();
+
   /* Default Synchro Signal division factor (not divided) */
-  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;  
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
   /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
-  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;  
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
   /* HSI48 is synchronized with USB SOF at 1KHz rate */
   RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
-  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;  
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
   /* Set the TRIM[5:0] to the default value*/
-  RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;   
-  /* Start automatic synchronization */ 
+  RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
+  /* Start automatic synchronization */
   HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct);
 }
 
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
index 84662344d..0b1348474 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
@@ -1,4 +1,5 @@
-CFLAGS += -DSTM32L052xx -DCFG_EXAMPLE_VIDEO_READONLY
+CFLAGS += \
+	-DSTM32L052xx
 
 LD_FILE = $(BOARD_PATH)/STM32L052K8Ux_FLASH.ld
 
diff --git a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld b/hw/bsp/stm32l0/boards/stm32l0538disco/STM32L053C8Tx_FLASH.ld
similarity index 99%
rename from hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
rename to hw/bsp/stm32l0/boards/stm32l0538disco/STM32L053C8Tx_FLASH.ld
index 787418e09..033dcc0ad 100644
--- a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/STM32L053C8Tx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake b/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake
new file mode 100644
index 000000000..895bbb3ab
--- /dev/null
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32l053xx)
+set(JLINK_DEVICE stm32l053r8)
+#set(JLINK_OPTION "-USB 778921770")
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L053C8Tx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L053xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.h b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
new file mode 100644
index 000000000..29402f00a
--- /dev/null
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
@@ -0,0 +1,115 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 L0538 Discovery
+   url: https://www.st.com/en/evaluation-tools/32l0538discovery.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   1
+
+// UART
+//#define UART_DEV              USART2
+//#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
+//#define UART_GPIO_PORT        GPIOA
+//#define UART_GPIO_AF          GPIO_AF4_USART2
+//#define UART_TX_PIN           GPIO_PIN_2
+//#define UART_RX_PIN           GPIO_PIN_3
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32l0_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = {0};
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+
+  /* Enable HSI Oscillator to be used as System clock source
+     Enable HSI48 Oscillator to be used as USB clock source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Select HSI48 as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2
+     clock dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+  /*Configure the clock recovery system (CRS)**********************************/
+
+  /*Enable CRS Clock*/
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+  /* Set the TRIM[5:0] to the default value*/
+  RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk b/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk
new file mode 100644
index 000000000..deed519ba
--- /dev/null
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+  -DSTM32L053xx
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32L053C8Tx_FLASH.ld
+
+SRC_S += \
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l053xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = STM32L053R8
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c
index 80a7c7435..b28903e00 100644
--- a/hw/bsp/stm32l0/family.c
+++ b/hw/bsp/stm32l0/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,36 +24,31 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32l0xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   tud_int_handler(0);
 }
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
+#ifdef UART_DEV
 UART_HandleTypeDef UartHandle;
+#endif
 
-void board_init(void)
-{
+void board_init(void) {
   board_stm32l0_clock_init();
 
-  // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-
-  // Enable UART Clock
-  UART_CLK_EN();
-
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -66,14 +61,22 @@ void board_init(void)
   NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
   // LED
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_PULLUP;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
 
+  board_led_write(false);
+
   // Button
   GPIO_InitStruct.Pin = BUTTON_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
@@ -81,7 +84,10 @@ void board_init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
-  // Uart
+#ifdef UART_DEV
+  // Enable UART Clock
+  UART_CLK_EN();
+
   GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
   GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
   GPIO_InitStruct.Pull      = GPIO_PULLUP;
@@ -98,13 +104,14 @@ void board_init(void)
   UartHandle.Init.Mode       = UART_MODE_TX_RX;
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   HAL_UART_Init(&UartHandle);
+#endif
 
   // USB Pins
   // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
   GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
   // USB Clock enable
@@ -115,67 +122,68 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
 
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  return len;
+#else
+  (void) buf;
+  (void) len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 #ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
+void assert_failed(uint8_t* file, uint32_t line) {
   (void) file; (void) line;
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line number,
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-  /* USER CODE END 6 */
 }
 #endif /* USE_FULL_ASSERT */
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32l0/family.cmake b/hw/bsp/stm32l0/family.cmake
new file mode 100644
index 000000000..954bdb158
--- /dev/null
+++ b/hw/bsp/stm32l0/family.cmake
@@ -0,0 +1,116 @@
+include_guard()
+
+set(ST_FAMILY l0)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32L0 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  #target_compile_options(${BOARD_TARGET} PUBLIC)
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32L0)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32l0/family.mk b/hw/bsp/stm32l0/family.mk
index 622fa61e0..fe7561fc2 100644
--- a/hw/bsp/stm32l0/family.mk
+++ b/hw/bsp/stm32l0/family.mk
@@ -1,24 +1,37 @@
 ST_FAMILY = l0
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += \
+	lib/CMSIS_5 \
+	hw/mcu/st/cmsis_device_$(ST_FAMILY) \
+	hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L0
 
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-align -Wno-error=maybe-uninitialized
+# mcu driver cause following warnings
+CFLAGS_GCC += \
+	-Wno-error=unused-parameter \
+	-Wno-error=redundant-decls \
+	-Wno-error=cast-align \
+
+ifeq ($(TOOLCHAIN),gcc)
+CFLAGS_GCC += -Wno-error=maybe-uninitialized
+endif
+
+CFLAGS_CLANG += \
+  -Wno-error=parentheses-equality
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
 
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
@@ -35,6 +48,3 @@ INC += \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
diff --git a/hw/bsp/stm32l0/stm32l0xx_hal_conf.h b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
index cc20ea8e0..fd109bc8c 100644
--- a/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
+++ b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
@@ -2,22 +2,44 @@
   ******************************************************************************
   * @file    stm32l0xx_hal_conf.h
   * @author  MCD Application Team
-  * @brief   HAL configuration template file. 
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l0xx_hal_conf.h.
+  * @brief   HAL configuration file.
   ******************************************************************************
-  * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2016 STMicroelectronics International N.V. All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted, provided that the following conditions are met:
+  *
+  * 1. Redistribution of source code must retain the above copyright notice,
+  *    this list of conditions and the following disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice,
+  *    this list of conditions and the following disclaimer in the documentation
+  *    and/or other materials provided with the distribution.
+  * 3. Neither the name of STMicroelectronics nor the names of other
+  *    contributors to this software may be used to endorse or promote products
+  *    derived from this software without specific written permission.
+  * 4. This software, including modifications and/or derivative works of this
+  *    software, must execute solely and exclusively on microcontroller or
+  *    microprocessor devices manufactured by or for STMicroelectronics.
+  * 5. Redistribution and use of this software other than as permitted under
+  *    this license is void and will automatically terminate your rights under
+  *    this license.
+  *
+  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
+  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
+  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
+  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L0xx_HAL_CONF_H
@@ -32,46 +54,48 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
-/*#define HAL_ADC_MODULE_ENABLED */
-/*#define HAL_COMP_MODULE_ENABLED */
-/*#define HAL_CRC_MODULE_ENABLED */
-/*#define HAL_CRYP_MODULE_ENABLED */
-/*#define HAL_DAC_MODULE_ENABLED */
+#define HAL_MODULE_ENABLED
+// #define HAL_ADC_MODULE_ENABLED
+/* #define HAL_COMP_MODULE_ENABLED */
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
 #define HAL_DMA_MODULE_ENABLED
-/*#define HAL_FIREWALL_MODULE_ENABLED */
+/* #define HAL_FIREWALL_MODULE_ENABLED */
 #define HAL_FLASH_MODULE_ENABLED
 #define HAL_GPIO_MODULE_ENABLED
-/*#define HAL_I2C_MODULE_ENABLED */
-/*#define HAL_I2S_MODULE_ENABLED */
-/*#define HAL_IWDG_MODULE_ENABLED */
-/*#define HAL_LCD_MODULE_ENABLED */
-/*#define HAL_LPTIM_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LCD_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
 #define HAL_PWR_MODULE_ENABLED
 #define HAL_RCC_MODULE_ENABLED
-/*#define HAL_RNG_MODULE_ENABLED */
-/*#define HAL_RTC_MODULE_ENABLED */
-/*#define HAL_SPI_MODULE_ENABLED */
-/*#define HAL_TIM_MODULE_ENABLED */
-/*#define HAL_TSC_MODULE_ENABLED */
+//#define HAL_RNG_MODULE_ENABLED
+/* #define HAL_RTC_MODULE_ENABLED */
+//#define HAL_SPI_MODULE_ENABLED
+/* #define HAL_TIM_MODULE_ENABLED */
+/* #define HAL_TSC_MODULE_ENABLED */
 #define HAL_UART_MODULE_ENABLED
-/*#define HAL_USART_MODULE_ENABLED */
-/*#define HAL_IRDA_MODULE_ENABLED */
-/*#define HAL_SMARTCARD_MODULE_ENABLED */
-/*#define HAL_SMBUS_MODULE_ENABLED */
-/*#define HAL_WWDG_MODULE_ENABLED */
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+//#define HAL_PCD_MODULE_ENABLED
 #define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_PCD_MODULE_ENABLED */
+
 
 /* ########################## Oscillator Values adaptation ####################*/
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -90,7 +114,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -99,7 +123,7 @@
 /**
   * @brief Internal High Speed oscillator for USB (HSI48) value.
   */
-#if !defined  (HSI48_VALUE) 
+#if !defined  (HSI48_VALUE)
 #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -108,7 +132,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -128,24 +152,24 @@
   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
-   
+
 /* Tip: To avoid modifying this file each time you need to use different HSE,
    ===  you can define the HSE value in your toolchain compiler preprocessor. */
 
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U)    /*!< tick interrupt priority */            
-#define  USE_RTOS                     0U     
-#define  PREFETCH_ENABLE              1U              
+#define  TICK_INT_PRIORITY            (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U)    /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
 #define  PREREAD_ENABLE               0U
 #define  BUFFER_CACHE_DISABLE         0U
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -191,13 +215,13 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
   #include "stm32l0xx_hal_rcc.h"
 #endif /* HAL_RCC_MODULE_ENABLED */
-  
+
 #ifdef HAL_GPIO_MODULE_ENABLED
   #include "stm32l0xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
@@ -233,11 +257,11 @@
 #ifdef HAL_FIREWALL_MODULE_ENABLED
   #include "stm32l0xx_hal_firewall.h"
 #endif /* HAL_FIREWALL_MODULE_ENABLED */
- 
+
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32l0xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_I2C_MODULE_ENABLED
  #include "stm32l0xx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
@@ -257,7 +281,7 @@
 #ifdef HAL_LPTIM_MODULE_ENABLED
 #include "stm32l0xx_hal_lptim.h"
 #endif /* HAL_LPTIM_MODULE_ENABLED */
-   
+
 #ifdef HAL_PWR_MODULE_ENABLED
  #include "stm32l0xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
@@ -316,13 +340,13 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+  void assert_failed(uint8_t *file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */
@@ -332,7 +356,6 @@
 #endif
 
 #endif /* __STM32L0xx_HAL_CONF_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk
deleted file mode 100644
index 69f09075a..000000000
--- a/hw/bsp/stm32l0538disco/board.mk
+++ /dev/null
@@ -1,54 +0,0 @@
-ST_FAMILY = l0
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
-  -DSTM32L053xx \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_EXAMPLE_VIDEO_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32L0
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=redundant-decls
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32L053C8Tx_FLASH.ld
-
-SRC_C += \
-  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l053xx.s
-
-INC += \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = STM32L053R8
-
-# Path to STM32 Cube Programmer CLI, should be added into system path 
-STM32Prog = STM32_Programmer_CLI
-
-# flash target using on-board stlink
-flash: $(BUILD)/$(PROJECT).elf
-	$(STM32Prog) --connect port=swd --write $< --go
diff --git a/hw/bsp/stm32l0538disco/stm32l0538disco.c b/hw/bsp/stm32l0538disco/stm32l0538disco.c
deleted file mode 100644
index f0f1d028b..000000000
--- a/hw/bsp/stm32l0538disco/stm32l0538disco.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-#include "stm32l0xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              GPIOA
-#define LED_PIN               GPIO_PIN_5
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow:
-  *         HSI48 used as USB clock source
-  *              - System Clock source            = HSI
-  *              - HSI Frequency(Hz)              = 16000000
-  *              - SYSCLK(Hz)                     = 16000000
-  *              - HCLK(Hz)                       = 16000000
-  *              - AHB Prescaler                  = 1
-  *              - APB1 Prescaler                 = 1
-  *              - APB2 Prescaler                 = 1
-  *              - Flash Latency(WS)              = 0
-  *              - Main regulator output voltage  = Scale1 mode
-  * @param  None
-  * @retval None
-  */
-static void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
-  static RCC_CRSInitTypeDef RCC_CRSInitStruct;
-
-  /* Enable HSI Oscillator to be used as System clock source
-     Enable HSI48 Oscillator to be used as USB clock source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select HSI48 as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clock dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-
-  /*Configure the clock recovery system (CRS)**********************************/
-
-  /*Enable CRS Clock*/
-  __HAL_RCC_CRS_CLK_ENABLE();
-
-  /* Default Synchro Signal division factor (not divided) */
-  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
-  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
-  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
-  /* HSI48 is synchronized with USB SOF at 1KHz rate */
-  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
-  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
-  /* Set the TRIM[5:0] to the default value*/
-  RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
-  /* Start automatic synchronization */
-  HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct);
-}
-
-void board_init(void)
-{
-  SystemClock_Config();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  board_led_write(false);
-
-  // Button
-  //__HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // USB
-  /* Configure DM DP Pins */
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Enable USB FS Clock */
-  __HAL_RCC_USB_CLK_ENABLE();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h b/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h
deleted file mode 100644
index 773b74e29..000000000
--- a/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  *
-  * Copyright (c) 2016 STMicroelectronics International N.V. All rights reserved.
-  *
-  * Redistribution and use in source and binary forms, with or without 
-  * modification, are permitted, provided that the following conditions are met:
-  *
-  * 1. Redistribution of source code must retain the above copyright notice, 
-  *    this list of conditions and the following disclaimer.
-  * 2. Redistributions in binary form must reproduce the above copyright notice,
-  *    this list of conditions and the following disclaimer in the documentation
-  *    and/or other materials provided with the distribution.
-  * 3. Neither the name of STMicroelectronics nor the names of other 
-  *    contributors to this software may be used to endorse or promote products 
-  *    derived from this software without specific written permission.
-  * 4. This software, including modifications and/or derivative works of this 
-  *    software, must execute solely and exclusively on microcontroller or
-  *    microprocessor devices manufactured by or for STMicroelectronics.
-  * 5. Redistribution and use of this software other than as permitted under 
-  *    this license is void and will automatically terminate your rights under 
-  *    this license. 
-  *
-  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 
-  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 
-  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
-  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
-  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 
-  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
-  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
-  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
-  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_CONF_H
-#define __STM32L0xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-// #define HAL_ADC_MODULE_ENABLED
-/* #define HAL_COMP_MODULE_ENABLED */ 
-/* #define HAL_CRC_MODULE_ENABLED */  
-/* #define HAL_CRYP_MODULE_ENABLED */ 
-/* #define HAL_DAC_MODULE_ENABLED */   
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_FIREWALL_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED 
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */   
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LCD_MODULE_ENABLED */ 
-/* #define HAL_LPTIM_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED  
-#define HAL_RCC_MODULE_ENABLED 
-//#define HAL_RNG_MODULE_ENABLED
-/* #define HAL_RTC_MODULE_ENABLED */
-//#define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED */   
-/* #define HAL_TSC_MODULE_ENABLED */
-/* #define HAL_UART_MODULE_ENABLED */ 
-/* #define HAL_USART_MODULE_ENABLED */ 
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */   
-/* #define HAL_WWDG_MODULE_ENABLED */ 
-//#define HAL_PCD_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator for USB (HSI48) value.
-  */
-#if !defined  (HSI48_VALUE) 
-#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI48_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-/**
-  * @brief Time out for LSE start up value in ms.
-  */
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-   
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */ 
-#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */           
-#define  USE_RTOS                     0U     
-#define  PREFETCH_ENABLE              1U              
-#define  PREREAD_ENABLE               1U
-#define  BUFFER_CACHE_DISABLE         0U
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                   1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32l0xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32l0xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l0xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32l0xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32l0xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l0xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-   
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32l0xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32l0xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32l0xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
-  #include "stm32l0xx_hal_firewall.h"
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32l0xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l0xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32l0xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l0xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l0xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32l0xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-   
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l0xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l0xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-  #include "stm32l0xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l0xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l0xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
-  #include "stm32l0xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l0xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l0xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l0xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l0xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l0xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l0xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l0xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..23ba069aa
--- /dev/null
+++ b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32l4xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
index 28cd96131..4ae4a4cf4 100644
--- a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
@@ -83,8 +83,8 @@ SECTIONS
     . = ALIGN(8);
   } >FLASH
 
-  .ARM.extab   : 
-  { 
+  .ARM.extab   :
+  {
   . = ALIGN(8);
   *(.ARM.extab* .gnu.linkonce.armextab.*)
   . = ALIGN(8);
@@ -105,7 +105,7 @@ SECTIONS
     PROVIDE_HIDDEN (__preinit_array_end = .);
 	. = ALIGN(8);
   } >FLASH
-  
+
   .init_array :
   {
 	. = ALIGN(8);
@@ -129,7 +129,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(8);
     _sdata = .;        /* create a global symbol at data start */
@@ -140,12 +140,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -168,7 +168,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -180,5 +180,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.cmake b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.cmake
new file mode 100644
index 000000000..e979a7378
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32l412xx)
+set(JLINK_DEVICE stm32l412kb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L412KBUx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L412xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
index 704d742cc..980e1e321 100644
--- a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 L412 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-l412kb.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -94,7 +99,7 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.PLL.PLLN = 10;
   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
-  
+
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
   /** Initializes the CPU, AHB and APB buses clocks
@@ -122,7 +127,7 @@ static inline void board_clock_init(void)
   RCC_CRSInitStruct.HSI48CalibrationValue = 32;
 
   HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
-  
+
   /* Select HSI48 output as USB clock source */
   PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
   PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
index 841ee4948..87b333500 100644
--- a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
@@ -1,10 +1,13 @@
 CFLAGS += \
   -DSTM32L412xx \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32L412KBUx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l412xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32L412KBUx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l412xx.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l412xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l412xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l412kb
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
index 98f468ac0..3bb13ed85 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
@@ -82,8 +82,8 @@ SECTIONS
     . = ALIGN(8);
   } >FLASH
 
-  .ARM.extab   : 
-  { 
+  .ARM.extab   :
+  {
   . = ALIGN(8);
   *(.ARM.extab* .gnu.linkonce.armextab.*)
   . = ALIGN(8);
@@ -104,7 +104,7 @@ SECTIONS
     PROVIDE_HIDDEN (__preinit_array_end = .);
 	. = ALIGN(8);
   } >FLASH
-  
+
   .init_array :
   {
 	. = ALIGN(8);
@@ -128,7 +128,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(8);
     _sdata = .;        /* create a global symbol at data start */
@@ -139,12 +139,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -167,7 +167,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -179,5 +179,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake
new file mode 100644
index 000000000..fd1c931c2
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32l476xx)
+set(JLINK_DEVICE stm32l476vg)
+# set(JLINK_OPTION "-USB 000777632258")
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L476VGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L476xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.h b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
index 42c657d5e..8c766d8ea 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 L476 Disco
+   url: https://www.st.com/en/evaluation-tools/32l476gdiscovery.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.mk b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
index e7b8557a5..3ba9ab444 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
@@ -1,10 +1,13 @@
 CFLAGS += \
   -DSTM32L476xx \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l476xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l476xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l476vg
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
index c1a490a70..6a2eaa0f7 100644
--- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
@@ -52,12 +52,6 @@
 /* Entry Point */
 ENTRY(Reset_Handler)
 
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM) + 0x0001FFFF;	/* end of "SRAM1" Ram type memory */
-
-_Min_Heap_Size = 0x200;	/* required amount of heap  */
-_Min_Stack_Size = 0x400;	/* required amount of stack */
-
 /* Memories definition */
 MEMORY
 {
@@ -65,6 +59,12 @@ MEMORY
   ROM	(rx)	: ORIGIN = 0x08000000,	LENGTH = 1024K
 }
 
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + 0x0001FFFF;	/* end of "SRAM1" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
 /* Sections */
 SECTIONS
 {
@@ -102,12 +102,12 @@ SECTIONS
     . = ALIGN(4);
   } >ROM
 
-  .ARM.extab   : { 
+  .ARM.extab   : {
     . = ALIGN(4);
     *(.ARM.extab* .gnu.linkonce.armextab.*)
     . = ALIGN(4);
   } >ROM
-  
+
   .ARM : {
     . = ALIGN(4);
     __exidx_start = .;
@@ -124,7 +124,7 @@ SECTIONS
     PROVIDE_HIDDEN (__preinit_array_end = .);
     . = ALIGN(4);
   } >ROM
-  
+
   .init_array :
   {
     . = ALIGN(4);
@@ -134,7 +134,7 @@ SECTIONS
     PROVIDE_HIDDEN (__init_array_end = .);
     . = ALIGN(4);
   } >ROM
-  
+
   .fini_array :
   {
     . = ALIGN(4);
@@ -149,7 +149,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections into "RAM" Ram type memory */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -158,7 +158,7 @@ SECTIONS
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
-    
+
   } >RAM AT> ROM
 
   /* Uninitialized data section into "RAM" Ram type memory */
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.cmake b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.cmake
new file mode 100644
index 000000000..ead241e32
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32l4p5xx)
+set(JLINK_DEVICE stm32l4p5zg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L4P5ZGTX_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L4P5xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
index 1df389aed..f522e7522 100644
--- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 L4P5 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
index 8252dd838..84f831878 100644
--- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
@@ -1,10 +1,13 @@
 CFLAGS += \
   -DSTM32L4P5xx \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l4p5xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l4p5xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l4p5zg
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
index f93a16041..267a87a8b 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,12 +125,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.cmake b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.cmake
new file mode 100644
index 000000000..d4bbe6a94
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32l4r5xx)
+set(JLINK_DEVICE stm32l4r5zi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L4RXxI_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L4R5xx
+    HSE_VALUE=8000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
index 1df389aed..c181f5d4a 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 L4R5 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
index 3d7fa227b..ad5bfba38 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
@@ -2,10 +2,13 @@ CFLAGS += \
   -DHSE_VALUE=8000000 \
   -DSTM32L4R5xx \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l4r5xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l4r5xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l4r5zi
diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index 0b1443aa0..2b555b5c2 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -26,8 +26,12 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32l4xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
@@ -48,8 +52,7 @@ void USB_IRQHandler(void)
 
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
   board_clock_init();
 
   // Enable All GPIOs clocks
@@ -177,49 +180,59 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
 
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+  HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt 0x10");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 
 }
diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake
new file mode 100644
index 000000000..eebcff4f3
--- /dev/null
+++ b/hw/bsp/stm32l4/family.cmake
@@ -0,0 +1,119 @@
+include_guard()
+
+set(ST_FAMILY l4)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32L4 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+#    target_compile_options(${BOARD_TARGET} PUBLIC)
+#    target_compile_definitions(${BOARD_TARGET} PUBLIC)
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS})
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index 1361e184c..950b6f9cb 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -5,33 +5,47 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L4
 
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+  -Wno-error=cast-align \
+
+ifeq ($(TOOLCHAIN),gcc)
+CFLAGS_GCC += -Wno-error=maybe-uninitialized
+endif
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
 
-#src/portable/st/synopsys/dcd_synopsys.c
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
-    src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c
 
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
@@ -39,8 +53,5 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc \
 	$(TOP)/$(BOARD_PATH)
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32l4/stm32l4xx_hal_conf.h b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h
index 312f86da1..25dbc0523 100644
--- a/hw/bsp/stm32l4/stm32l4xx_hal_conf.h
+++ b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h
@@ -50,7 +50,7 @@
 /* #define HAL_NAND_MODULE_ENABLED */
 // #define HAL_NOR_MODULE_ENABLED
 // #define HAL_SRAM_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */ 
+/* #define HAL_HCD_MODULE_ENABLED */
 #define HAL_GPIO_MODULE_ENABLED
 //#define HAL_I2C_MODULE_ENABLED
 /* #define HAL_IRDA_MODULE_ENABLED */
@@ -115,7 +115,7 @@
   *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
   *        which is subject to manufacturing process variations.
   */
-#if !defined  (HSI48_VALUE) 
+#if !defined  (HSI48_VALUE)
  #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
                                               The real value my vary depending on manufacturing process variations.*/
 #endif /* HSI48_VALUE */
@@ -123,7 +123,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE  32000U                 /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -142,7 +142,7 @@
 
 /**
   * @brief External clock source for SAI1 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
   *        frequency.
   */
 #if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
@@ -151,7 +151,7 @@
 
 /**
   * @brief External clock source for SAI2 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
   *        frequency.
   */
 #if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
diff --git a/hw/bsp/stm32u5/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32u5/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..b51020590
--- /dev/null
+++ b/hw/bsp/stm32u5/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32u5xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake
new file mode 100644
index 000000000..1cb92d710
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32u585xx)
+set(JLINK_DEVICE stm32u585zi)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32U585xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
new file mode 100644
index 000000000..cf3f63ea5
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
@@ -0,0 +1,117 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 B-U585i IOT2A Discovery kit
+   url: https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LED GREEN
+#define LED_PORT GPIOH
+#define LED_PIN GPIO_PIN_7
+#define LED_STATE_ON 0
+
+// BUTTON
+#define BUTTON_PORT GPIOC
+#define BUTTON_PIN GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for STLink VCOM
+#define UART_DEV USART1
+#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
+#define UART_GPIO_PORT GPIOA
+#define UART_GPIO_AF GPIO_AF7_USART1
+#define UART_TX_PIN GPIO_PIN_9
+#define UART_RX_PIN GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+static void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
+
+  /* Enable Power Clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /** Configure the main internal regulator output voltage
+   */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 10;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 1;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+  PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+   */
+  RCC_ClkInitStruct.ClockType =
+      RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+}
+
+static void SystemPower_Config(void) {
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk
new file mode 100644
index 000000000..ae63afef3
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += \
+  -DSTM32U585xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
+
+MCU_VARIANT = stm32u585xx
+# For flash-jlink target
+JLINK_DEVICE = stm32u585zi
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake
new file mode 100644
index 000000000..d42501948
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32u545xx)
+set(JLINK_DEVICE stm32u545re)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32U545xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
new file mode 100644
index 000000000..0c3439b2c
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
@@ -0,0 +1,117 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 U545 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LED GREEN
+#define LED_PORT GPIOA
+#define LED_PIN GPIO_PIN_5
+#define LED_STATE_ON 1
+
+// BUTTON
+#define BUTTON_PORT GPIOC
+#define BUTTON_PIN GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for STLink VCOM
+#define UART_DEV LPUART1
+#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT GPIOA
+#define UART_GPIO_AF GPIO_AF8_LPUART1
+#define UART_TX_PIN GPIO_PIN_2
+#define UART_RX_PIN GPIO_PIN_3
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+static void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
+
+  /* Enable Power Clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /** Configure the main internal regulator output voltage
+   */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 10;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 1;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+  PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+   */
+  RCC_ClkInitStruct.ClockType =
+      RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+}
+
+static void SystemPower_Config(void) {
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk
new file mode 100644
index 000000000..072c595fb
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += \
+  -DSTM32U545xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = ${FAMILY_PATH}/linker/STM32U545xx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u545xx.s
+
+MCU_VARIANT = stm32u545xx
+# For flash-jlink target
+JLINK_DEVICE = stm32u545re
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.cmake b/hw/bsp/stm32u5/boards/stm32u575eval/board.cmake
new file mode 100644
index 000000000..dc2f42d94
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32u575xx)
+set(JLINK_DEVICE stm32u575ai)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32U575xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
index 5c348b812..b11f6a747 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
@@ -25,6 +25,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 U575 Eval
+   url: https://www.st.com/en/evaluation-tools/stm32u575i-ev.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -55,12 +60,10 @@ extern "C"
 // RCC Clock
 //--------------------------------------------------------------------+
 
-static inline void board_clock_init(void)
-{
-
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+static void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
 
   /* Enable Power Clock*/
   __HAL_RCC_PWR_CLK_ENABLE();
@@ -69,7 +72,7 @@ static inline void board_clock_init(void)
    */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
 
-  /** Initializes the CPU, AHB and APB busses clocks
+  /** Initializes the CPU, AHB and APB buses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -92,9 +95,10 @@ static inline void board_clock_init(void)
 
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
 
-  /** Initializes the CPU, AHB and APB busses clocks
+  /** Initializes the CPU, AHB and APB buses clocks
    */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.ClockType =
+      RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
@@ -104,6 +108,8 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 }
 
+static void SystemPower_Config(void) {
+}
 
 #ifdef __cplusplus
 }
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
index 19cd2a5b0..fee56f2ba 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
@@ -2,9 +2,10 @@ CFLAGS += \
   -DSTM32U575xx \
 
 # All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32U575AIIXQ_FLASH.ld
+LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
 
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
 
+MCU_VARIANT = stm32u575xx
 # For flash-jlink target
-JLINK_DEVICE = stm32u575
+JLINK_DEVICE = stm32u575ai
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.cmake
new file mode 100644
index 000000000..76285c08f
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32u575xx)
+set(JLINK_DEVICE stm32u575zi)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32U575xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
new file mode 100644
index 000000000..be037b68a
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
@@ -0,0 +1,117 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 U575 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LED GREEN
+#define LED_PORT GPIOC
+#define LED_PIN GPIO_PIN_7
+#define LED_STATE_ON 1
+
+// BUTTON
+#define BUTTON_PORT GPIOA
+#define BUTTON_PIN GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for STLink VCOM
+#define UART_DEV LPUART1
+#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT GPIOG
+#define UART_GPIO_AF GPIO_AF8_LPUART1
+#define UART_TX_PIN GPIO_PIN_7
+#define UART_RX_PIN GPIO_PIN_8
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+static void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
+
+  /* Enable Power Clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /** Configure the main internal regulator output voltage
+   */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 10;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 1;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+  PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+   */
+  RCC_ClkInitStruct.ClockType =
+      RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+}
+
+static void SystemPower_Config(void) {
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
new file mode 100644
index 000000000..c83ec3999
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += \
+  -DSTM32U575xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
+
+MCU_VARIANT = stm32u575xx
+# For flash-jlink target
+JLINK_DEVICE = stm32u575zi
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld
new file mode 100644
index 000000000..2d1028cbe
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld
@@ -0,0 +1,167 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U5A5xJ Device from STM32U5 series
+**                      4096Kbytes FLASH
+**                      2512Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM   (xrw) : ORIGIN = 0x20000000, LENGTH = 2496K
+  SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 4096K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
new file mode 100644
index 000000000..230c3b722
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32u5a5xx)
+set(JLINK_DEVICE stm32u5a5zj)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32U5A5ZJTXQ_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32U5A5xx
+    HSE_VALUE=16000000UL
+    )
+endfunction()
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
new file mode 100644
index 000000000..0785fb36b
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
@@ -0,0 +1,149 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 U5a5 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LED GREEN
+#define LED_PORT GPIOC
+#define LED_PIN GPIO_PIN_7
+#define LED_STATE_ON 1
+
+// BUTTON
+#define BUTTON_PORT GPIOC
+#define BUTTON_PIN GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for STLink VCOM
+#define UART_DEV USART1
+#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
+#define UART_GPIO_PORT GPIOA
+#define UART_GPIO_AF GPIO_AF7_USART1
+#define UART_TX_PIN GPIO_PIN_9
+#define UART_RX_PIN GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+static void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+
+  __HAL_RCC_PWR_CLK_ENABLE();
+  HAL_PWREx_EnableVddA();
+
+  /** Configure the main internal regulator output voltage
+  */
+  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 20;
+  RCC_OscInitStruct.PLL.PLLP = 8;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+                                | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  // USB Clock
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  RCC_PeriphCLKInitTypeDef usb_clk_init = { 0};
+  usb_clk_init.PeriphClockSelection = RCC_PERIPHCLK_USBPHY;
+  usb_clk_init.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE;
+  if (HAL_RCCEx_PeriphCLKConfig(&usb_clk_init) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Set the OTG PHY reference clock selection
+  */
+  HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1);
+
+  // USART clock
+  RCC_PeriphCLKInitTypeDef uart_clk_init = { 0};
+  uart_clk_init.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+  uart_clk_init.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  if (HAL_RCCEx_PeriphCLKConfig(&uart_clk_init) != HAL_OK) {
+    Error_Handler();
+  }
+}
+
+static void SystemPower_Config(void) {
+  HAL_PWREx_EnableVddIO2();
+
+  /*
+   * Switch to SMPS regulator instead of LDO
+   */
+  if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK) {
+    Error_Handler();
+  }
+/* USER CODE BEGIN PWR */
+/* USER CODE END PWR */
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
new file mode 100644
index 000000000..4bebe3330
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
@@ -0,0 +1,12 @@
+CFLAGS += \
+  -DSTM32U5A5xx \
+  -DHSE_VALUE=16000000UL \
+
+# All source paths should be relative to the top level.
+LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s
+
+MCU_VARIANT = stm32u5a5xx
+# For flash-jlink target
+JLINK_DEVICE = stm32u575zi
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc
new file mode 100644
index 000000000..289734040
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc
@@ -0,0 +1,352 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_2
+ADC1.IPParameters=Rank-1\#ChannelRegularConversion,master,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,MonitoredBy-1\#ChannelRegularConversion,NbrOfConversionFlag
+ADC1.MonitoredBy-1\#ChannelRegularConversion=__NULL
+ADC1.NbrOfConversionFlag=1
+ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.Rank-1\#ChannelRegularConversion=1
+ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_5CYCLE
+ADC1.master=1
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+CORTEX_M33_NS.userName=CORTEX_M33
+File.Version=6
+GPDMA1.DIRECTION_GPDMACH0=DMA_MEMORY_TO_PERIPH
+GPDMA1.DIRECTION_GPDMACH3=DMA_MEMORY_TO_PERIPH
+GPDMA1.IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0=__NULL
+GPDMA1.IPHANDLE_GPDMACH3-SIMPLEREQUEST_GPDMACH3=__NULL
+GPDMA1.IPHANDLE_GPDMACH5-SIMPLEREQUEST_GPDMACH5=__NULL
+GPDMA1.IPParameters=IPHANDLE_GPDMACH5-SIMPLEREQUEST_GPDMACH5,REQUEST_GPDMACH5,IPHANDLE_GPDMACH3-SIMPLEREQUEST_GPDMACH3,REQUEST_GPDMACH3,DIRECTION_GPDMACH3,IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0,REQUEST_GPDMACH0,DIRECTION_GPDMACH0,SRCINC_GPDMACH0
+GPDMA1.REQUEST_GPDMACH0=GPDMA1_REQUEST_USART1_TX
+GPDMA1.REQUEST_GPDMACH3=GPDMA1_REQUEST_UCPD1_TX
+GPDMA1.REQUEST_GPDMACH5=GPDMA1_REQUEST_UCPD1_RX
+GPDMA1.SRCINC_GPDMACH0=DMA_SINC_INCREMENTED
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+MMTAppReg1.MEMORYMAP.AP=RW_priv_only
+MMTAppReg1.MEMORYMAP.AppRegionName=RAM
+MMTAppReg1.MEMORYMAP.ContextName=CortexM33
+MMTAppReg1.MEMORYMAP.CoreName=ARM Cortex-M33
+MMTAppReg1.MEMORYMAP.DefaultDataRegion=true
+MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,AP
+MMTAppReg1.MEMORYMAP.Name=RAM
+MMTAppReg1.MEMORYMAP.Size=2555904
+MMTAppReg1.MEMORYMAP.StartAddress=0x20000000
+MMTAppReg2.MEMORYMAP.AppRegionName=RAM Reserved Alias Region
+MMTAppReg2.MEMORYMAP.CoreName=ARM Cortex-M33
+MMTAppReg2.MEMORYMAP.DefaultDataRegion=false
+MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ReservedRegion,Name
+MMTAppReg2.MEMORYMAP.Name=RAM Reserved Alias Region
+MMTAppReg2.MEMORYMAP.ReservedRegion=true
+MMTAppReg2.MEMORYMAP.Size=2555904
+MMTAppReg2.MEMORYMAP.StartAddress=0x0A000000
+MMTAppReg3.MEMORYMAP.AP=RO_priv_only
+MMTAppReg3.MEMORYMAP.AppRegionName=FLASH
+MMTAppReg3.MEMORYMAP.Cacheability=WTRA
+MMTAppReg3.MEMORYMAP.ContextName=CortexM33
+MMTAppReg3.MEMORYMAP.CoreName=ARM Cortex-M33
+MMTAppReg3.MEMORYMAP.DefaultCodeRegion=true
+MMTAppReg3.MEMORYMAP.DefaultDataRegion=false
+MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion
+MMTAppReg3.MEMORYMAP.MemType=ROM
+MMTAppReg3.MEMORYMAP.Name=FLASH
+MMTAppReg3.MEMORYMAP.Size=4194304
+MMTAppReg3.MEMORYMAP.StartAddress=0x08000000
+MMTAppRegionsCount=3
+MMTConfigApplied=false
+Mcu.CPN=STM32U5A5ZJT6Q
+Mcu.ContextProject=TrustZoneDisabled
+Mcu.Family=STM32U5
+Mcu.IP0=ADC1
+Mcu.IP1=CORTEX_M33_NS
+Mcu.IP10=UCPD1
+Mcu.IP11=USART1
+Mcu.IP12=USBPD
+Mcu.IP13=USBX
+Mcu.IP14=USB_OTG_HS
+Mcu.IP2=GPDMA1
+Mcu.IP3=ICACHE
+Mcu.IP4=MEMORYMAP
+Mcu.IP5=NVIC
+Mcu.IP6=PWR
+Mcu.IP7=RCC
+Mcu.IP8=SYS
+Mcu.IP9=THREADX
+Mcu.IPNb=15
+Mcu.Name=STM32U5A5ZJTxQ
+Mcu.Package=LQFP144
+Mcu.Pin0=PH0-OSC_IN (PH0)
+Mcu.Pin1=PH1-OSC_OUT (PH1)
+Mcu.Pin10=VP_GPDMA1_VS_GPDMACH0
+Mcu.Pin11=VP_GPDMA1_VS_GPDMACH3
+Mcu.Pin12=VP_GPDMA1_VS_GPDMACH5
+Mcu.Pin13=VP_ICACHE_VS_ICACHE
+Mcu.Pin14=VP_PWR_VS_DBSignals
+Mcu.Pin15=VP_PWR_VS_SECSignals
+Mcu.Pin16=VP_PWR_VS_LPOM
+Mcu.Pin17=VP_SYS_VS_tim6
+Mcu.Pin18=VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault
+Mcu.Pin19=VP_USBPD_VS_USBPD1
+Mcu.Pin2=PC1
+Mcu.Pin20=VP_USBPD_VS_PD3TYPEC
+Mcu.Pin21=VP_USBPD_VS_usbpd_tim2
+Mcu.Pin22=VP_USBPD_VS_usbpd_usb_cohabitation
+Mcu.Pin23=VP_USBX_Core_System
+Mcu.Pin24=VP_USBX_UX Device CoreStack_HS
+Mcu.Pin25=VP_USBX_UX Device Controller_HS
+Mcu.Pin26=VP_USBX_UX Device CDC ACM Class_HS
+Mcu.Pin27=VP_MEMORYMAP_VS_MEMORYMAP
+Mcu.Pin3=PB15
+Mcu.Pin4=PG2
+Mcu.Pin5=PA9
+Mcu.Pin6=PA10
+Mcu.Pin7=PA11
+Mcu.Pin8=PA12
+Mcu.Pin9=PA15 (JTDI)
+Mcu.PinsNb=28
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32U5A5ZJTxQ
+MxCube.Version=6.9.2
+MxDb.Version=DB.6.0.92
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.GPDMA1_Channel0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.GPDMA1_Channel3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.GPDMA1_Channel5_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.OTG_HS_IRQn=true\:7\:0\:true\:false\:true\:false\:true\:true\:true
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
+NVIC.SavedPendsvIrqHandlerGenerated=true
+NVIC.SavedSvcallIrqHandlerGenerated=true
+NVIC.SavedSystickIrqHandlerGenerated=true
+NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:false\:false\:false\:true\:false
+NVIC.TIM6_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true
+NVIC.TimeBase=TIM6_IRQn
+NVIC.TimeBaseIP=TIM6
+NVIC.UCPD1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:false\:true
+NVIC.USART1_IRQn=true\:6\:0\:true\:false\:true\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+PA10.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA10.GPIO_PuPd=GPIO_PULLUP
+PA10.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA11.GPIOParameters=GPIO_Speed
+PA11.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA11.Mode=Internal_Phy_Device
+PA11.Signal=USB_OTG_HS_DM
+PA12.GPIOParameters=GPIO_Speed
+PA12.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA12.Mode=Internal_Phy_Device
+PA12.Signal=USB_OTG_HS_DP
+PA15\ (JTDI).Mode=Sink_AllSignals
+PA15\ (JTDI).Signal=UCPD1_CC1
+PA9.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA9.GPIO_PuPd=GPIO_PULLUP
+PA9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PB15.Mode=Sink_AllSignals
+PB15.Signal=UCPD1_CC2
+PC1.Mode=IN2-Single-Ended
+PC1.Signal=ADC1_IN2
+PG2.GPIOParameters=GPIO_Label
+PG2.GPIO_Label=LED_RED
+PG2.Locked=true
+PG2.Signal=GPIO_Output
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
+PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
+PWR.IPParameters=PowerMode
+PWR.PowerMode=PWR_SMPS_SUPPLY
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32U5A5ZJTxQ
+ProjectManager.Example=Ux_Device_CDC_ACM
+ProjectManager.ExampleSource=MxCubeFw
+ProjectManager.FirmwarePackage=STM32Cube FW_U5 V1.3.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LPBAM.generateCode=
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=stm32u5a5nucleo.ioc
+ProjectManager.ProjectName=stm32u5a5nucleo
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_GPDMA1_Init-GPDMA1-false-HAL-true,4-MX_ICACHE_Init-ICACHE-false-HAL-true,5-MX_USART1_UART_Init-USART1-false-HAL-false,6-MX_UCPD1_Init-UCPD1-false-LL-true,7-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-true-HAL-false,8-MX_USBPD_Init-USBPD-false-HAL-false,9-MX_USBX_Init-USBX-false-HAL-false,10-MX_ADC1_Init-ADC1-false-HAL-true,11-MX_MEMORYMAP_Init-MEMORYMAP-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
+RCC.ADCFreq_Value=16000000
+RCC.ADF1Freq_Value=160000000
+RCC.AHBFreq_Value=160000000
+RCC.APB1Freq_Value=160000000
+RCC.APB1TimFreq_Value=160000000
+RCC.APB2Freq_Value=160000000
+RCC.APB2TimFreq_Value=160000000
+RCC.APB3Freq_Value=160000000
+RCC.CK48Freq_Value=48000000
+RCC.CRSFreq_Value=48000000
+RCC.CortexFreq_Value=160000000
+RCC.DACCLockSelectionVirtual=RCC_DAC1CLKSOURCE_LSI
+RCC.DACFreq_Value=32000
+RCC.EPOD_VALUE=16000000
+RCC.FCLKCortexFreq_Value=160000000
+RCC.FDCANFreq_Value=160000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=160000000
+RCC.HSE_VALUE=16000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=160000000
+RCC.I2C2Freq_Value=160000000
+RCC.I2C3Freq_Value=160000000
+RCC.I2C4Freq_Value=160000000
+RCC.I2C5Freq_Value=160000000
+RCC.I2C6Freq_Value=160000000
+RCC.IPParameters=ADCFreq_Value,ADF1Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CK48Freq_Value,CRSFreq_Value,CortexFreq_Value,DACCLockSelectionVirtual,DACFreq_Value,EPOD_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2C5Freq_Value,I2C6Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIDIV_VALUE,LSI_VALUE,MCO1PinFreq_Value,MDF1Freq_Value,MSIClockRange,MSI_VALUE,OCTOSPIMFreq_Value,PLL1P,PLL2FRACN,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3FRACN,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLFRACN,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAESFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBPHYCLockSelection,USBPHYFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value
+RCC.LPTIM2Freq_Value=160000000
+RCC.LPUART1Freq_Value=160000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSIDIV_VALUE=32000
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=160000000
+RCC.MDF1Freq_Value=160000000
+RCC.MSIClockRange=RCC_MSIRANGE_0
+RCC.MSI_VALUE=48000000
+RCC.OCTOSPIMFreq_Value=160000000
+RCC.PLL1P=8
+RCC.PLL2FRACN=0
+RCC.PLL2PoutputFreq_Value=3096000000
+RCC.PLL2QoutputFreq_Value=3096000000
+RCC.PLL2RoutputFreq_Value=3096000000
+RCC.PLL3FRACN=0
+RCC.PLL3PoutputFreq_Value=3096000000
+RCC.PLL3QoutputFreq_Value=3096000000
+RCC.PLL3RoutputFreq_Value=3096000000
+RCC.PLLFRACN=0
+RCC.PLLN=20
+RCC.PLLPoutputFreq_Value=40000000
+RCC.PLLQoutputFreq_Value=160000000
+RCC.PLLRCLKFreq_Value=160000000
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.RNGFreq_Value=48000000
+RCC.SAESFreq_Value=48000000
+RCC.SAI1Freq_Value=3096000000
+RCC.SAI2Freq_Value=3096000000
+RCC.SDMMCFreq_Value=40000000
+RCC.SPI1Freq_Value=160000000
+RCC.SPI2Freq_Value=160000000
+RCC.SPI3Freq_Value=160000000
+RCC.SYSCLKFreq_VALUE=160000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART4Freq_Value=160000000
+RCC.UART5Freq_Value=160000000
+RCC.USART1Freq_Value=160000000
+RCC.USART2Freq_Value=160000000
+RCC.USART3Freq_Value=160000000
+RCC.USART6Freq_Value=160000000
+RCC.USBPHYCLockSelection=RCC_USBPHYCLKSOURCE_HSE
+RCC.USBPHYFreq_Value=16000000
+RCC.VCOInput2Freq_Value=48000000
+RCC.VCOInput3Freq_Value=48000000
+RCC.VCOInputFreq_Value=16000000
+RCC.VCOOutputFreq_Value=320000000
+RCC.VCOPLL2OutputFreq_Value=6192000000
+RCC.VCOPLL3OutputFreq_Value=6192000000
+USART1.IPParameters=VirtualMode-Asynchronous
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USBX.BSP.number=1
+USBX.Core_System=1
+USBX.IPParameters=Core_System,UX_Device_CoreStack,UX_Device_Controller,UX_DEVICE_CDC_ACM,USBD_CDCACM_EPIN_ADDR,USBD_CDCACM_EPOUT_HS_MPS,USBD_CDCACM_EPIN_HS_MPS,UX_DEVICE_APP_MEM_POOL_SIZE,USBD_PRODUCT_STRING,UX_SLAVE_REQUEST_DATA_MAX_LENGTH,USBX_DEVICE_SYS_SIZE,USBD_PID,USBD_SERIAL_NUMBER,UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH,USBD_CDCACM_EPINCMD_ADDR,MAX_POWER_IN_MILLI_AMPER
+USBX.MAX_POWER_IN_MILLI_AMPER=0
+USBX.USBD_CDCACM_EPINCMD_ADDR=2
+USBX.USBD_CDCACM_EPIN_ADDR=1
+USBX.USBD_CDCACM_EPIN_HS_MPS=512
+USBX.USBD_CDCACM_EPOUT_HS_MPS=512
+USBX.USBD_PID=22336
+USBX.USBD_PRODUCT_STRING=STM32 Virtual ComPort
+USBX.USBD_SERIAL_NUMBER=CDC_ACM001
+USBX.USBX_DEVICE_SYS_SIZE=4*1024
+USBX.UX_DEVICE_APP_MEM_POOL_SIZE=8192
+USBX.UX_DEVICE_CDC_ACM=1
+USBX.UX_Device_Controller=1
+USBX.UX_Device_CoreStack=1
+USBX.UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH=256
+USBX.UX_SLAVE_REQUEST_DATA_MAX_LENGTH=512
+USBX0.BSP.STBoard=false
+USBX0.BSP.api=Unknown
+USBX0.BSP.component=
+USBX0.BSP.condition=
+USBX0.BSP.instance=USB_OTG_HS
+USBX0.BSP.ip=USB_OTG_HS
+USBX0.BSP.mode=Device_Only
+USBX0.BSP.name=USBDevice
+USBX0.BSP.semaphore=
+USBX0.BSP.solution=USB_OTG_HS
+USB_OTG_HS.IPParameters=VirtualMode
+USB_OTG_HS.VirtualMode=Device_HS
+VP_GPDMA1_VS_GPDMACH0.Mode=SIMPLEREQUEST_GPDMACH0
+VP_GPDMA1_VS_GPDMACH0.Signal=GPDMA1_VS_GPDMACH0
+VP_GPDMA1_VS_GPDMACH3.Mode=SIMPLEREQUEST_GPDMACH3
+VP_GPDMA1_VS_GPDMACH3.Signal=GPDMA1_VS_GPDMACH3
+VP_GPDMA1_VS_GPDMACH5.Mode=SIMPLEREQUEST_GPDMACH5
+VP_GPDMA1_VS_GPDMACH5.Signal=GPDMA1_VS_GPDMACH5
+VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache
+VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE
+VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
+VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
+VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals
+VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals
+VP_PWR_VS_LPOM.Mode=PowerOptimisation
+VP_PWR_VS_LPOM.Signal=PWR_VS_LPOM
+VP_PWR_VS_SECSignals.Mode=Security/Privilege
+VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals
+VP_SYS_VS_tim6.Mode=TIM6
+VP_SYS_VS_tim6.Signal=SYS_VS_tim6
+VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Mode=Core_Default
+VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Signal=THREADX_VS_RTOSJjThreadXJjCoreJjDefault
+VP_USBPD_VS_PD3TYPEC.Mode=PD3_TypeC
+VP_USBPD_VS_PD3TYPEC.Signal=USBPD_VS_PD3TYPEC
+VP_USBPD_VS_USBPD1.Mode=USBPD_P0
+VP_USBPD_VS_USBPD1.Signal=USBPD_VS_USBPD1
+VP_USBPD_VS_usbpd_tim2.Mode=TIM2
+VP_USBPD_VS_usbpd_tim2.Signal=USBPD_VS_usbpd_tim2
+VP_USBPD_VS_usbpd_usb_cohabitation.Mode=Enable USB Support
+VP_USBPD_VS_usbpd_usb_cohabitation.Signal=USBPD_VS_usbpd_usb_cohabitation
+VP_USBX_Core_System.Mode=Core_System
+VP_USBX_Core_System.Signal=USBX_Core_System
+VP_USBX_UX\ Device\ CDC\ ACM\ Class_HS.Mode=UX_Device_class_CDC_ACM_HS
+VP_USBX_UX\ Device\ CDC\ ACM\ Class_HS.Signal=USBX_UX Device CDC ACM Class_HS
+VP_USBX_UX\ Device\ Controller_HS.Mode=UX_Device_Controller_HS
+VP_USBX_UX\ Device\ Controller_HS.Signal=USBX_UX Device Controller_HS
+VP_USBX_UX\ Device\ CoreStack_HS.Mode=UX_Device_CoreStack_HS
+VP_USBX_UX\ Device\ CoreStack_HS.Signal=USBX_UX Device CoreStack_HS
+board=NUCLEO-U5A5ZJ-Q
+boardIOC=true
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index 9bc94cfa3..032c01f34 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -25,15 +25,37 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wundef"
+#endif
+
 #include "stm32u5xx_hal.h"
-#include "bsp/board.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+
+TU_ATTR_UNUSED static void Error_Handler(void) {
+}
+
 #include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
+void OTG_FS_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+void OTG_HS_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -43,10 +65,10 @@ void OTG_FS_IRQHandler(void)
 
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
-
-  board_clock_init();
+void board_init(void) {
+  // Init clock, implemented in board.h
+  SystemClock_Config();
+  SystemPower_Config();
 
   // Enable All GPIOs clocks
   __HAL_RCC_GPIOA_CLK_ENABLE();
@@ -54,18 +76,20 @@ void board_init(void)
   __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
   __HAL_RCC_GPIOE_CLK_ENABLE();
+#ifdef GPIOF
   __HAL_RCC_GPIOF_CLK_ENABLE();
+#endif
   __HAL_RCC_GPIOG_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE();
 
   UART_CLK_EN();
 
+  /* Enable Instruction cache */
+  HAL_ICACHE_Enable();
+
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   GPIO_InitTypeDef GPIO_InitStruct;
@@ -89,7 +113,7 @@ void board_init(void)
   GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
@@ -104,10 +128,9 @@ void board_init(void)
   UartHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
   UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
   UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
-
   HAL_UART_Init(&UartHandle);
 
-  /* Configure USB FS GPIOs */
+  /* Configure USB GPIOs */
   /* Configure DM DP Pins */
   GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
   GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -123,8 +146,25 @@ void board_init(void)
   GPIO_InitStruct.Alternate = GPIO_AF10_USB;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
-#if OTG_FS_VBUS_SENSE
-  // Configure VBUS Pin
+#ifdef USB_DRD_FS
+  // STM32U535/STM32U545
+
+  /* Enable USB power on Pwrctrl CR2 register */
+  HAL_PWREx_EnableVddUSB();
+
+  /* USB clock enable */
+  __HAL_RCC_USB_FS_CLK_ENABLE();
+
+#endif
+
+#ifdef USB_OTG_FS
+  #if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
+
+  #if defined(OTG_FS_VBUS_SENSE) && OTG_FS_VBUS_SENSE
+  // Configure VBUS Pin OTG_FS_VBUS_SENSE
   GPIO_InitStruct.Pin = GPIO_PIN_9;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -132,69 +172,107 @@ void board_init(void)
 
   // Enable VBUS sense (B device) via pin PA9
   USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
+  #else
   // Disable VBUS sense (B device) via pin PA9
   USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 
   // B-peripheral session valid override enable
   USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
   USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif // vbus sense
+  #endif // vbus sense
 
   /* Enable USB power on Pwrctrl CR2 register */
   HAL_PWREx_EnableVddUSB();
 
-  /* USB_OTG_FS clock enable */
+  /* USB clock enable */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+
+#endif
+
+#ifdef USB_OTG_HS
+  // STM59x/Ax/Fx/Gx only have 1 USB HS port
+
+  #if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
+
+  /* USB clock enable */
+  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+  __HAL_RCC_USBPHYC_CLK_ENABLE();
+
+  /* Enable USB power on Pwrctrl CR2 register */
+  HAL_PWREx_EnableVddUSB();
+  HAL_PWREx_EnableUSBHSTranceiverSupply();
+
+  /*Configuring the SYSCFG registers OTG_HS PHY*/
+  HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
+
+  // Disable VBUS sense (B device)
+  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+  // B-peripheral session valid override enable
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+#endif // USB_OTG_FS
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t *buf, int len)
-{
-  (void)buf;
-  (void)len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t *stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t *id32 = (uint32_t *) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const *buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t *)(uintptr_t)buf, len, 0xffff);
+int board_uart_write(void const *buf, int len) {
+  HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff);
   return len;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler(void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  asm("bkpt 1");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 }
diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake
new file mode 100644
index 000000000..7a5935961
--- /dev/null
+++ b/hw/bsp/stm32u5/family.cmake
@@ -0,0 +1,120 @@
+include_guard()
+
+set(ST_FAMILY u5)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32U5 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  string(REPLACE "stm32u" "STM32U" MCU_VARIANT_UPPER ${MCU_VARIANT})
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT_UPPER}_FLASH.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_icache.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32U5)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    #${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index 1cfb81e43..05fe4608a 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -5,41 +5,57 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
 
 CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m33 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
-  -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32U5
 
-# suppress warning caused by vendor mcu driver 
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=undef -Wno-error=unused-parameter
+# suppress warning caused by vendor mcu driver
+CFLAGS_GCC += \
+  -flto \
+  -Wno-error=cast-align \
+  -Wno-error=undef \
+  -Wno-error=unused-parameter \
+  -Wno-error=type-limits \
+
+ifeq ($(TOOLCHAIN),gcc)
+CFLAGS_GCC += -Wno-error=maybe-uninitialized
+endif
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
 
-#src/portable/st/synopsys/dcd_synopsys.c
 SRC_C += \
-	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
 
+ifeq ($(MCU_VARIANT),stm32u545xx)
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+else ifeq ($(MCU_VARIANT),stm32u535xx)
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+else
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c
+endif
+
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc \
 	$(TOP)/$(BOARD_PATH)
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U535xx_FLASH.ld
similarity index 94%
rename from hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld
rename to hw/bsp/stm32u5/linker/STM32U535xx_FLASH.ld
index 03c022bc2..6ac1479a3 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld
+++ b/hw/bsp/stm32u5/linker/STM32U535xx_FLASH.ld
@@ -5,9 +5,9 @@
 **
 **  Author      : STM32CubeIDE
 **
-**  Abstract    : Linker script for STM32U575xI Device from STM32U5 series
-**                      2048Kbytes FLASH
-**                      784Kbytes RAM
+**  Abstract    : Linker script for STM32U535xE Device from STM32U5 series
+**                      512Kbytes FLASH
+**                      272Kbytes RAM
 **
 **                Set heap size, stack size and stack location according
 **                to application requirements.
@@ -35,20 +35,20 @@
 /* Entry Point */
 ENTRY(Reset_Handler)
 
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 256K
+  SRAM4	(xrw)	: ORIGIN = 0x28000000,	LENGTH = 16K
+  FLASH	(rx)	: ORIGIN = 0x08000000,	LENGTH = 512K
+}
+
 /* Highest address of the user mode stack */
 _estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
 
 _Min_Heap_Size = 0x200 ;	/* required amount of heap  */
 _Min_Stack_Size = 0x400 ;	/* required amount of stack */
 
-/* Memories definition */
-MEMORY
-{
-  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 768K
-  SRAM4	(xrw)	: ORIGIN = 0x28000000,	LENGTH = 16K
-  FLASH	(rx)	: ORIGIN = 0x08000000,	LENGTH = 2048K
-}
-
 /* Sections */
 SECTIONS
 {
diff --git a/hw/bsp/stm32u5/linker/STM32U545xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U545xx_FLASH.ld
new file mode 100644
index 000000000..ce370c643
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U545xx_FLASH.ld
@@ -0,0 +1,167 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U545xE Device from STM32U5 series
+**                      512Kbytes FLASH
+**                      272Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 256K
+  SRAM4	(xrw)	: ORIGIN = 0x28000000,	LENGTH = 16K
+  FLASH	(rx)	: ORIGIN = 0x08000000,	LENGTH = 512K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/linker/STM32U575xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U575xx_FLASH.ld
new file mode 100644
index 000000000..b24c533de
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U575xx_FLASH.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U575xx Device from STM32U5 series
+**                      2048Kbytes ROM
+**                      784Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 768K
+  ROM	(rx)	: ORIGIN = 0x08000000,	LENGTH = 2048K
+  SRAM4	(xrw)	: ORIGIN = 0x28000000,	LENGTH = 16K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : {
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> ROM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/linker/STM32U585xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U585xx_FLASH.ld
new file mode 100644
index 000000000..15b8054bc
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U585xx_FLASH.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U585xx Device from STM32U5 series
+**                      2048Kbytes ROM
+**                      784Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 768K
+  ROM	(rx)	: ORIGIN = 0x08000000,	LENGTH = 2048K
+  SRAM4 (xrw)   : ORIGIN = 0x28000000,  LENGTH = 16K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : {
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> ROM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/linker/STM32U595xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U595xx_FLASH.ld
new file mode 100644
index 000000000..100ee14a5
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U595xx_FLASH.ld
@@ -0,0 +1,168 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U595xJ Device from STM32U5 series
+**                      4096Kbytes FLASH
+**                      2528Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM   (xrw) : ORIGIN = 0x20000000, LENGTH = 2496K
+  SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 4096K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/linker/STM32U599xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U599xx_FLASH.ld
new file mode 100644
index 000000000..55997bf40
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U599xx_FLASH.ld
@@ -0,0 +1,168 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U599xJ Device from STM32U5 series
+**                      4096Kbytes FLASH
+**                      2528Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 2496K
+  SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 4096K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/linker/STM32U5A9xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U5A9xx_FLASH.ld
new file mode 100644
index 000000000..a5f7d3405
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U5A9xx_FLASH.ld
@@ -0,0 +1,168 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U5A9xJ Device from STM32U5 series
+**                      4096Kbytes FLASH
+**                      2528Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 2496K
+  SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 4096K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/linker/STM32U5F7xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U5F7xx_FLASH.ld
new file mode 100644
index 000000000..bb9953440
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U5F7xx_FLASH.ld
@@ -0,0 +1,168 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U5F7xJ Device from STM32U5 series
+**                      4096Kbytes FLASH
+**                      2528Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 2496K
+  SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 4096K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/linker/STM32U5F9xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U5F9xx_FLASH.ld
new file mode 100644
index 000000000..d8f1f4c5f
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U5F9xx_FLASH.ld
@@ -0,0 +1,168 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U5F9xJ Device from STM32U5 series
+**                      4096Kbytes FLASH
+**                      2528Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 2496K
+  SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 4096K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/linker/STM32U5G7xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U5G7xx_FLASH.ld
new file mode 100644
index 000000000..d02d6ebf1
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U5G7xx_FLASH.ld
@@ -0,0 +1,168 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U5G7xJ Device from STM32U5 series
+**                      4096Kbytes FLASH
+**                      2528Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 2496K
+  SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 4096K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/linker/STM32U5G9xx_FLASH.ld b/hw/bsp/stm32u5/linker/STM32U5G9xx_FLASH.ld
new file mode 100644
index 000000000..1b072fdd4
--- /dev/null
+++ b/hw/bsp/stm32u5/linker/STM32U5G9xx_FLASH.ld
@@ -0,0 +1,168 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U5G9xJ Device from STM32U5 series
+**                      4096Kbytes FLASH
+**                      2528Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Memories definition */
+MEMORY
+{
+  RAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 2496K
+  SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 4096K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
index 15dffa813..87c3683de 100644
--- a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
+++ b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
@@ -503,4 +503,3 @@
 #endif
 
 #endif /* STM32U5xx_HAL_CONF_H */
-
diff --git a/hw/bsp/stm32wb/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32wb/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6ad115f60
--- /dev/null
+++ b/hw/bsp/stm32wb/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,153 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32wbxx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.cmake b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.cmake
new file mode 100644
index 000000000..5512aa2ee
--- /dev/null
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32wb55xx)
+set(JLINK_DEVICE STM32WB55RG)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32wb55xx_flash_cm4.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32WB55xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h
index f42c7d6dd..704592506 100644
--- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: STM32 P-NUCLEO-WB55
+   url: https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
@@ -59,7 +64,7 @@ static inline void board_clock_init(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  // Initializes the CPU, AHB and APB busses clocks
+  // Initializes the CPU, AHB and APB buses clocks
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
   RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
@@ -72,7 +77,7 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.PLL.PLLR       = RCC_PLLR_DIV3;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
-  // Initializes the CPU, AHB and APB busses clocks
+  // Initializes the CPU, AHB and APB buses clocks
   RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.mk b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.mk
index d6adc6b63..009883f30 100644
--- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.mk
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.mk
@@ -1,9 +1,7 @@
+MCU_VARIANT = stm32wb55xx
+
 CFLAGS += \
 	-DSTM32WB55xx
 
-LD_FILE = $(BOARD_PATH)/stm32wb55xx_flash_cm4.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32wb55xx_cm4.s
-
 # For flash-jlink target
 JLINK_DEVICE = STM32WB55RG
diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
index 660f30161..916f11866 100644
--- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
@@ -113,7 +113,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -124,7 +124,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM1 AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -152,7 +152,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM1
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -167,5 +167,3 @@ SECTIONS
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
    MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
-
-
diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c
index 9f1f46f4d..ba37b7cc3 100644
--- a/hw/bsp/stm32wb/family.c
+++ b/hw/bsp/stm32wb/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2022 Jerzy Kasenberg
@@ -24,30 +24,33 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include "stm32wbxx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_HP_IRQHandler(void)
-{
+void USB_HP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB_LP_IRQHandler(void)
-{
+void USB_LP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
+#ifdef UART_DEV
 UART_HandleTypeDef UartHandle;
+#endif
 
-void board_init(void)
-{
+void board_init(void) {
   board_clock_init();
 
   // Enable All GPIOs clocks
@@ -57,8 +60,6 @@ void board_init(void)
   __HAL_RCC_GPIOD_CLK_ENABLE();
   __HAL_RCC_GPIOE_CLK_ENABLE();
 
-  UART_CLK_EN();
-
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -71,7 +72,7 @@ void board_init(void)
   NVIC_SetPriority(USB_LP_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
 
   // LED
   GPIO_InitStruct.Pin = LED_PIN;
@@ -101,23 +102,25 @@ void board_init(void)
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
 #ifdef UART_DEV
+  UART_CLK_EN();
+
   // UART
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
-  UartHandle = (UART_HandleTypeDef){
-    .Instance        = UART_DEV,
-    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
-    .Init.WordLength = UART_WORDLENGTH_8B,
-    .Init.StopBits   = UART_STOPBITS_1,
-    .Init.Parity     = UART_PARITY_NONE,
-    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
-    .Init.Mode       = UART_MODE_TX_RX,
-    .Init.OverSampling = UART_OVERSAMPLING_16
+  UartHandle = (UART_HandleTypeDef) {
+      .Instance        = UART_DEV,
+      .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+      .Init.WordLength = UART_WORDLENGTH_8B,
+      .Init.StopBits   = UART_STOPBITS_1,
+      .Init.Parity     = UART_PARITY_NONE,
+      .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+      .Init.Mode       = UART_MODE_TX_RX,
+      .Init.OverSampling = UART_OVERSAMPLING_16
   };
   HAL_UART_Init(&UartHandle);
 #endif
@@ -138,54 +141,51 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
 #ifdef UART_DEV
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*) (uintptr_t) buf, len, 0xffff);
   return len;
 #else
-  (void) buf; (void) len; (void) UartHandle;
+  (void) buf; (void) len;
   return 0;
 #endif
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
+void HardFault_Handler(void) {
+  asm("bkpt 1");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 
 }
diff --git a/hw/bsp/stm32wb/family.cmake b/hw/bsp/stm32wb/family.cmake
new file mode 100644
index 000000000..0ea937257
--- /dev/null
+++ b/hw/bsp/stm32wb/family.cmake
@@ -0,0 +1,119 @@
+include_guard()
+
+set(ST_FAMILY wb)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32WB CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}_cm4.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}_cm4.s)
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_cm4.ld)
+  endif()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash_cm4.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+#    target_compile_options(${BOARD_TARGET} PUBLIC)
+#    target_compile_definitions(${BOARD_TARGET} PUBLIC)
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS})
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32wb/family.mk b/hw/bsp/stm32wb/family.mk
index f85c5badd..de8372eea 100644
--- a/hw/bsp/stm32wb/family.mk
+++ b/hw/bsp/stm32wb/family.mk
@@ -1,35 +1,37 @@
 UF2_FAMILY_ID = 0x70d16653
 ST_FAMILY = wb
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
+ST_PREFIX = stm32${ST_FAMILY}xx
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32WB
 
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=cast-align -Wno-unused-parameter
 
+LD_FILE ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_cm4.ld
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
 SRC_C += \
 	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
+	$(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}_cm4.s
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
@@ -37,8 +39,5 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/tm4c/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/tm4c/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..454b085e9
--- /dev/null
+++ b/hw/bsp/tm4c/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "TM4C123.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.cmake b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.cmake
new file mode 100644
index 000000000..b8df9f189
--- /dev/null
+++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_SUB_VARIANT 123)
+
+set(JLINK_DEVICE TM4C123GH6PM)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/tm4c123.ld)
+
+set(OPENOCD_OPTION "-f board/ti_ek-tm4c123gxl.cfg")
+set(UNIFLASH_OPTION "-c ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ccxml -r 1")
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    TM4C123GH6PM
+    )
+endfunction()
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h
similarity index 94%
rename from hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h
rename to hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h
index 5732056ae..c0ceb4cd8 100644
--- a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h
+++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: TM4C123G LaunchPad
+   url: https://www.ti.com/tool/EK-TM4C123GXL
+*/
+
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.mk
similarity index 70%
rename from hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
rename to hw/bsp/tm4c/boards/ek_tm4c123gxl/board.mk
index d60365d1d..b3ded8007 100644
--- a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
+++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.mk
@@ -1,5 +1,7 @@
+MCU_SUB_VARIANT = 123
+
 CFLAGS += -DTM4C123GH6PM
- 
+
 LD_FILE = $(BOARD_PATH)/tm4c123.ld
 
 # For flash-jlink target
@@ -8,4 +10,6 @@ JLINK_DEVICE = TM4C123GH6PM
 # flash using openocd
 OPENOCD_OPTION = -f board/ti_ek-tm4c123gxl.cfg
 
+UNIFLASH_OPTION = -c ${TOP}/${BOARD_PATH}/${BOARD}.ccxml -r 1
+
 flash: flash-openocd
diff --git a/hw/bsp/tm4c/boards/ek_tm4c123gxl/ek_tm4c123gxl.ccxml b/hw/bsp/tm4c/boards/ek_tm4c123gxl/ek_tm4c123gxl.ccxml
new file mode 100644
index 000000000..426a6f368
--- /dev/null
+++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/ek_tm4c123gxl.ccxml
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configurations XML_version="1.2" id="configurations_0">
+<configuration XML_version="1.2" id="configuration_0">
+        <instance XML_version="1.2" desc="Stellaris In-Circuit Debug Interface" href="connections/Stellaris_ICDI_Connection.xml" id="Stellaris In-Circuit Debug Interface" xml="Stellaris_ICDI_Connection.xml" xmlpath="connections"/>
+        <connection XML_version="1.2" id="Stellaris In-Circuit Debug Interface">
+
+        		   <instance XML_version="1.2" href="drivers/stellaris_cs_dap.xml" id="drivers" xml="stellaris_cs_dap.xml" xmlpath="drivers"/>
+
+        		   <instance XML_version="1.2" href="drivers/stellaris_cortex_m4.xml" id="drivers" xml="stellaris_cortex_m4.xml" xmlpath="drivers"/>
+
+
+            <platform XML_version="1.2" id="platform_0">
+                <instance XML_version="1.2" desc="Tiva TM4C123GH6PM" href="devices/tm4c123gh6pm.xml" id="Tiva TM4C123GH6PM" xml="tm4c123gh6pm.xml" xmlpath="devices"/>
+            </platform>
+        </connection>
+    </configuration>
+</configurations>
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld
similarity index 62%
rename from hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
rename to hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld
index e2720a9ac..11e9608cc 100644
--- a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
+++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld
@@ -6,37 +6,38 @@ _Min_Heap_Size = 0;      /* required amount of heap  */
 _Min_Stack_Size = 0x1000; /* required amount of stack */
 
 
-MEMORY 
+MEMORY
 {
     FLASH(rx) : ORIGIN = 0x00000000, LENGTH = 256K
     SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K
 }
 
-SECTIONS 
+SECTIONS
 {
-    .text : 
+    .text :
     {
         . = ALIGN(4) ;
-        *(.vectors) 
-        *(.text) 
+        *(.vectors)
+        *(.text)
         *(.text.*)
         *(.init)
         *(.fini)
         *(.rodata)
         *(.rodata.*)
-        . = ALIGN(4) ; 
-        __end_text = . ; 
+        *(.ARM.exidx*)
+        . = ALIGN(4) ;
+        __end_text = . ;
     } >FLASH
-    
+
     .data : AT(ADDR(.text) + SIZEOF(.text))
     {
         . = ALIGN(4);
-        __start_data = . ; 
+        __start_data = . ;
         __la_data = LOADADDR(.data);
-        *(.data) 
+        *(.data)
         *(.data.*)
         . = ALIGN(4);
-        __end_data = . ; 
+        __end_data = . ;
 
     } >SRAM
 
@@ -47,19 +48,19 @@ SECTIONS
         __bss_start__ = __start_bss;
         *(.bss)
         *(.bss.*)
-        *(.COMMON) 
+        *(.COMMON)
         __end_bss = . ;
         . = ALIGN(4);
     }>SRAM
 
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >SRAM
+    /* User_heap_stack section, used to check that there is enough RAM left */
+    ._user_heap_stack :
+    {
+        . = ALIGN(8);
+        PROVIDE ( end = . );
+        PROVIDE ( _end = . );
+        . = . + _Min_Heap_Size;
+        . = . + _Min_Stack_Size;
+        . = ALIGN(8);
+    } >SRAM
 }
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c/family.c
similarity index 70%
rename from hw/bsp/tm4c123/family.c
rename to hw/bsp/tm4c/family.c
index b0947d6c4..4e5491005 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c/family.c
@@ -1,14 +1,17 @@
+/* metadata:
+   manufacturer: Texas Instruments
+*/
+
 #include "TM4C123.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB0_Handler(void)
-{
+void USB0_Handler(void) {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 
 #if CFG_TUD_ENABLED
@@ -20,8 +23,7 @@ void USB0_Handler(void)
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-static void board_uart_init (void)
-{
+static void board_uart_init(void) {
   SYSCTL->RCGCUART |= (1 << 0);                // Enable the clock to UART0
   SYSCTL->RCGCGPIO |= (1 << 0);                // Enable the clock to GPIOA
 
@@ -39,16 +41,15 @@ static void board_uart_init (void)
   UART0->LCRH = (0x3 << 5);                    // 8-bit, no parity, 1 stop bit
   UART0->CC = 0x0;                             // Configure the UART clock source as system clock
 
-  UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Recieve Enable
+  UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Receive Enable
 }
 
-static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk)
-{
+static void initialize_board_led(GPIOA_Type* port, uint8_t PinMsk, uint8_t dirmsk) {
   /* Enable PortF Clock */
   SYSCTL->RCGCGPIO |= (1 << 5);
 
   /* Let the clock stabilize */
-  while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) {}
+  while (!((SYSCTL->PRGPIO) & (1 << 5))) {}
 
   /* Port Digital Enable */
   port->DEN |= PinMsk;
@@ -57,46 +58,33 @@ static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirm
   port->DIR = dirmsk;
 }
 
-static void board_switch_init (void)
-{
-  GPIOF->DIR &= ~(1 << BOARD_BTN);
-  GPIOF->PUR |= (1 << BOARD_BTN);
-  GPIOF->DEN |= (1 << BOARD_BTN);
-}
-
-static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state)
-{
-  if ( state )
-  {
+static void WriteGPIOPin(GPIOA_Type* port, uint8_t PinMsk, bool state) {
+  if (state) {
     port->DATA |= PinMsk;
-  }
-  else
-  {
+  } else {
     port->DATA &= ~(PinMsk);
   }
 }
 
-static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk)
-{
+static uint32_t ReadGPIOPin(GPIOA_Type* port, uint8_t pinMsk) {
   return (port->DATA & pinMsk);
 }
 
-void board_init (void)
-{
+void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
-    // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-    NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
   /* Reset USB */
   SYSCTL->SRCR2 |= (1u << 16);
 
-  for ( volatile uint8_t i = 0; i < 20; i++ ) {}
+  for (volatile uint8_t i = 0; i < 20; i++) {}
 
   SYSCTL->SRCR2 &= ~(1u << 16);
 
@@ -110,7 +98,7 @@ void board_init (void)
   SYSCTL->RCGCGPIO |= (1u << 3);
 
   /* Let the clock stabilize */
-  while ( !(SYSCTL->PRGPIO & (1u << 3)) ) {}
+  while (!(SYSCTL->PRGPIO & (1u << 3))) {}
 
   /* USB IOs to Analog Mode */
   GPIOD->AFSEL &= ~((1u << 4) | (1u << 5));
@@ -124,7 +112,9 @@ void board_init (void)
   initialize_board_led(LED_PORT, leds, dirmsk);
 
   /* Configure GPIO for board switch */
-  board_switch_init();
+  GPIOF->DIR &= ~(1 << BOARD_BTN);
+  GPIOF->PUR |= (1 << BOARD_BTN);
+  GPIOF->DEN |= (1 << BOARD_BTN);
 
   /* Initialize board UART */
   board_uart_init();
@@ -132,32 +122,35 @@ void board_init (void)
   TU_LOG1_INT(SystemCoreClock);
 }
 
-void board_led_write (bool state)
-{
+void board_led_write(bool state) {
   WriteGPIOPin(LED_PORT, (1 << LED_PIN_BLUE), state);
 }
 
-uint32_t board_button_read (void)
-{
+uint32_t board_button_read(void) {
   uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk);
   return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value;
 }
 
-int board_uart_write (void const *buf, int len)
-{
-  uint8_t const * data = buf;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  uint8_t const len = 8;
+  // Note: DID0, DID1 are variant ID, they aer used since TM4C123 does not have unique ID
+  memcpy(id, (void*)(uintptr_t) &SYSCTL->DID0, len);
+  return len;
+}
 
-  for ( int i = 0; i < len; i++ )
-  {
-    while ( (UART0->FR & (1 << 5)) != 0 ) {} // Poll until previous data was shofted out
-    UART0->DR = data[i];                     // Write UART0 DATA REGISTER
+int board_uart_write(void const* buf, int len) {
+  uint8_t const* data = buf;
+
+  for (int i = 0; i < len; i++) {
+    while ((UART0->FR & (1 << 5)) != 0) {} // Poll until previous data was shofted out
+    UART0->DR = data[i];                   // Write UART0 DATA REGISTER
   }
 
   return len;
 }
 
-int board_uart_read (uint8_t *buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
@@ -165,14 +158,13 @@ int board_uart_read (uint8_t *buf, int len)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis (void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
-#endif
 
+#endif
diff --git a/hw/bsp/tm4c/family.cmake b/hw/bsp/tm4c/family.cmake
new file mode 100644
index 000000000..e1cf94e96
--- /dev/null
+++ b/hw/bsp/tm4c/family.cmake
@@ -0,0 +1,95 @@
+include_guard()
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(MCU_VARIANT tm4c${MCU_SUB_VARIANT})
+set(MCU_VARIANT_UPPER TM4C${MCU_SUB_VARIANT})
+
+set(SDK_DIR ${TOP}/hw/mcu/ti/${MCU_VARIANT}xx)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS TM4C123 CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  set(STARTUP_FILE_GNU ${SDK_DIR}/Source/GCC/${MCU_VARIANT}_startup.c)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/Source/system_${MCU_VARIANT_UPPER}.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/Include/${MCU_VARIANT_UPPER}
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      -uvectors
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_TM4C123)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/mentor/musb/dcd_musb.c
+    ${TOP}/src/portable/mentor/musb/hcd_musb.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_openocd(${TARGET})
+  family_flash_uniflash(${TARGET})
+endfunction()
diff --git a/hw/bsp/tm4c/family.mk b/hw/bsp/tm4c/family.mk
new file mode 100644
index 000000000..76ae785b2
--- /dev/null
+++ b/hw/bsp/tm4c/family.mk
@@ -0,0 +1,28 @@
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
+MCU_VARIANT = tm4c${MCU_SUB_VARIANT}
+MCU_VARIANT_UPPER = TM4C${MCU_SUB_VARIANT}
+
+SDK_DIR = hw/mcu/ti/${MCU_VARIANT}xx
+
+CFLAGS += \
+  -flto \
+  -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \
+  -uvectors \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
+
+LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
+
+INC += \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/Include/${MCU_VARIANT_UPPER} \
+	$(TOP)/$(BOARD_PATH)
+
+SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
+	src/portable/mentor/musb/hcd_musb.c \
+	$(SDK_DIR)/Source/system_${MCU_VARIANT_UPPER}.c \
+	$(SDK_DIR)/Source/GCC/${MCU_VARIANT}_startup.c
diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk
deleted file mode 100644
index 751076196..000000000
--- a/hw/bsp/tm4c123/family.mk
+++ /dev/null
@@ -1,36 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/ti
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \
-  -uvectors \
-  -DTM4C123GH6PM
-  
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
-
-MCU_DIR=hw/mcu/ti/tm4c123xx/
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/tm4c123.ld
-
-INC += \
-	$(TOP)/$(MCU_DIR)/CMSIS/5.7.0/CMSIS/Include \
-	$(TOP)/$(MCU_DIR)/Include/TM4C123 \
-	$(TOP)/$(BOARD_PATH)
-
-SRC_C += \
-	src/portable/mentor/musb/dcd_musb.c \
-	src/portable/mentor/musb/hcd_musb.c \
-	$(MCU_DIR)/Source/system_TM4C123.c \
-	$(MCU_DIR)/Source/GCC/tm4c123_startup.c
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
diff --git a/hw/bsp/xmc4000/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/xmc4000/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..76eacea39
--- /dev/null
+++ b/hw/bsp/xmc4000/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "xmc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       6
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake b/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake
new file mode 100644
index 000000000..e18741a9b
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT XMC4500)
+
+set(JLINK_DEVICE XMC4500-1024)
+#set(JLINK_OPTION "-USB 000551005307")
+set(LD_FILE_GNU ${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    XMC4500_F100x1024
+    )
+endfunction()
diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
index 3e2cb9583..3d0e92b2c 100644
--- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -24,6 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   name: XMC4500 relax kit
+   url: https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc45_relax_v1/
+*/
+
 #ifndef BOARD_H_
 #define BOARD_H_
 
diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
index 371adff91..a74fb9cd5 100644
--- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
@@ -3,9 +3,9 @@ CFLAGS += \
   -DXMC4500_F100x1024 \
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=stringop-overread
+CFLAGS += -Wno-stringop-overread
 
-LD_FILE = $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld
+LD_FILE = $(SDK_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld
 
 JLINK_DEVICE = XMC4500-1024
 
diff --git a/hw/bsp/xmc4000/boards/xmc4700_relax/board.cmake b/hw/bsp/xmc4000/boards/xmc4700_relax/board.cmake
new file mode 100644
index 000000000..3b74ab0a9
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4700_relax/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT XMC4700)
+
+set(JLINK_DEVICE XMC4700-2048)
+set(LD_FILE_GNU ${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Source/TOOLCHAIN_GCC_ARM/XMC4700x2048.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    XMC4700_F144x2048
+    )
+endfunction()
diff --git a/hw/bsp/xmc4000/boards/xmc4700_relax/board.h b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h
new file mode 100644
index 000000000..f3972980c
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h
@@ -0,0 +1,86 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: XMC4700 relax kit
+   url: https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc47_relax_v1/
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PIN               P5_9
+#define LED_STATE_ON          1
+
+#define BUTTON_PIN            P15_13
+#define BUTTON_STATE_ACTIVE   0
+
+#define UART_DEV              XMC_UART0_CH0
+#define UART_TX_PIN           P1_5
+#define UART_TX_PIN_AF        P1_5_AF_U0C0_DOUT0
+#define UART_RX_PIN           P1_4
+#define UART_RX_INPUT         USIC0_C0_DX0_P1_4
+
+static inline void board_clock_init(void)
+{
+  /* Clock configuration */
+  /* fPLL = 144MHz */
+  /* fSYS = 144MHz */
+  /* fUSB = 48MHz */
+  const XMC_SCU_CLOCK_CONFIG_t clock_config =
+  {
+    .syspll_config.p_div  = 2,
+    .syspll_config.n_div  = 48,
+    .syspll_config.k_div  = 1,
+    .syspll_config.mode   = XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL,
+    .syspll_config.clksrc = XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP,
+    .enable_oschp         = true,
+    .calibration_mode     = XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY,
+    .fsys_clksrc          = XMC_SCU_CLOCK_SYSCLKSRC_PLL,
+    .fsys_clkdiv          = 2,
+    .fcpu_clkdiv          = 1,
+    .fccu_clkdiv          = 1,
+    .fperipheral_clkdiv   = 1
+  };
+
+  /* Setup settings for USB clock */
+  XMC_SCU_CLOCK_Init(&clock_config);
+
+  XMC_SCU_CLOCK_SetUsbClockDivider(6);
+  XMC_SCU_CLOCK_SetUsbClockSource(XMC_SCU_CLOCK_USBCLKSRC_SYSPLL);
+  XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_USB);
+}
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/xmc4000/boards/xmc4700_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4700_relax/board.mk
new file mode 100644
index 000000000..f9e2d6a1d
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4700_relax/board.mk
@@ -0,0 +1,12 @@
+MCU_VARIANT = XMC4700
+CFLAGS += \
+  -DXMC4700_F144x2048 \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-stringop-overread
+
+LD_FILE = $(SDK_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4700x2048.ld
+
+JLINK_DEVICE = XMC4700-2048
+
+flash: flash-jlink
diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c
index bf6684736..1acce024b 100644
--- a/hw/bsp/xmc4000/family.c
+++ b/hw/bsp/xmc4000/family.c
@@ -24,38 +24,55 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Infineon
+*/
+
 #include "xmc_gpio.h"
 #include "xmc_scu.h"
+#include "xmc_uart.h"
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB0_0_IRQHandler(void)
-{
+void USB0_0_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void board_init(void)
-{
+void board_init(void) {
   board_clock_init();
   SystemCoreClockUpdate();
 
   // LED
-  XMC_GPIO_CONFIG_t led_cfg;
+  XMC_GPIO_CONFIG_t led_cfg = {0};
   led_cfg.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
   led_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;
   led_cfg.output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM;
   XMC_GPIO_Init(LED_PIN, &led_cfg);
 
   // Button
-  XMC_GPIO_CONFIG_t button_cfg;
+  XMC_GPIO_CONFIG_t button_cfg = {0};
   button_cfg.mode = XMC_GPIO_MODE_INPUT_TRISTATE;
   XMC_GPIO_Init(BUTTON_PIN, &button_cfg);
 
+#ifdef UART_DEV
+  XMC_UART_CH_CONFIG_t uart_cfg = {0};
+  uart_cfg.baudrate = CFG_BOARD_UART_BAUDRATE;
+  uart_cfg.data_bits = 8;
+  uart_cfg.stop_bits = 1;
+  XMC_UART_CH_Init(UART_DEV, &uart_cfg);
+
+  XMC_GPIO_SetMode(UART_RX_PIN, XMC_GPIO_MODE_INPUT_PULL_UP);
+  XMC_UART_CH_SetInputSource(UART_DEV, XMC_UART_CH_INPUT_RXD, UART_RX_INPUT);
+
+  XMC_UART_CH_Start(UART_DEV);
+  XMC_GPIO_SetMode(UART_TX_PIN, (XMC_GPIO_MODE_t)(XMC_GPIO_MODE_OUTPUT_PUSH_PULL | UART_TX_PIN_AF));
+#endif
+
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -69,6 +86,9 @@ void board_init(void)
 #endif
 
   // USB Power Enable
+#if(UC_SERIES != XMC45)
+  XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0);
+#endif
   XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0);
   XMC_SCU_POWER_EnableUsb();
 }
@@ -77,54 +97,63 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  uint32_t is_high = state ? LED_STATE_ON : (1-LED_STATE_ON);
+void board_led_write(bool state) {
+  uint32_t is_high = state ? LED_STATE_ON : (1 - LED_STATE_ON);
 
   XMC_GPIO_SetOutputLevel(LED_PIN, is_high ? XMC_GPIO_OUTPUT_LEVEL_HIGH : XMC_GPIO_OUTPUT_LEVEL_LOW);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == XMC_GPIO_GetInput(BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  uint8_t const len = tu_min8(16, max_len);
+  memcpy(id, g_chipid, len);
+  return len;
+}
+
+int board_uart_read(uint8_t* buf, int len) {
 #ifdef UART_DEV
   for(int i=0;i<len;i++) {
-    buf[i] = uart_getc(uart_inst);
+    buf[i] = XMC_UART_CH_GetReceivedData(UART_DEV);
   }
   return len;
 #else
-  (void) buf; (void) len;
+  (void) buf;
+  (void) len;
   return 0;
 #endif
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
 #ifdef UART_DEV
   char const* bufch = (char const*) buf;
   for(int i=0;i<len;i++) {
-    uart_putc(uart_inst, bufch[i]);
+    XMC_UART_CH_Transmit(UART_DEV, bufch[i]);
   }
   return len;
 #else
-  (void) buf; (void) len;
+  (void) buf;
+  (void) len;
   return 0;
 #endif
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+//void _init(void) {
+//}
diff --git a/hw/bsp/xmc4000/family.cmake b/hw/bsp/xmc4000/family.cmake
new file mode 100644
index 000000000..6edd72caf
--- /dev/null
+++ b/hw/bsp/xmc4000/family.cmake
@@ -0,0 +1,99 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/infineon/mtb-xmclib-cat3)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS XMC4000 CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  set(STARTUP_FILE_GNU ${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Source/TOOLCHAIN_GCC_ARM/startup_${MCU_VARIANT}.S)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Source/system_${MCU_VARIANT}.c
+    ${SDK_DIR}/XMCLib/src/xmc_gpio.c
+    ${SDK_DIR}/XMCLib/src/xmc4_gpio.c
+    ${SDK_DIR}/XMCLib/src/xmc4_scu.c
+    ${SDK_DIR}/XMCLib/src/xmc_usic.c
+    ${SDK_DIR}/XMCLib/src/xmc_uart.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Include
+    ${SDK_DIR}/XMCLib/inc
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    ${SDK_DIR}/Newlib/syscalls.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_XMC4000)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
index 0b32bdeb5..a1679a2f0 100644
--- a/hw/bsp/xmc4000/family.mk
+++ b/hw/bsp/xmc4000/family.mk
@@ -1,40 +1,35 @@
 UF2_FAMILY_ID = 0x00
-MCU_DIR = hw/mcu/infineon/mtb-xmclib-cat3
+SDK_DIR = hw/mcu/infineon/mtb-xmclib-cat3
 
-DEPS_SUBMODULES += $(MCU_DIR)
+DEPS_SUBMODULES += ${SDK_DIR}
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_XMC4000
 
 # mcu driver cause following warnings
 #CFLAGS += -Wno-error=shadow -Wno-error=cast-align
 
-SKIP_NANOLIB = 1
-
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
-	$(MCU_DIR)/Newlib/syscalls.c \
-	$(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/system_$(MCU_VARIANT).c \
-	$(MCU_DIR)/XMCLib/src/xmc4_gpio.c \
-	$(MCU_DIR)/XMCLib/src/xmc4_scu.c
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
+	${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Source/system_${MCU_VARIANT}.c \
+	${SDK_DIR}/Newlib/syscalls.c \
+	${SDK_DIR}/XMCLib/src/xmc_gpio.c \
+	${SDK_DIR}/XMCLib/src/xmc4_gpio.c \
+	${SDK_DIR}/XMCLib/src/xmc4_scu.c \
+	${SDK_DIR}/XMCLib/src/xmc_usic.c \
+	${SDK_DIR}/XMCLib/src/xmc_uart.c
 
-
-SRC_S += $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/startup_$(MCU_VARIANT).S
+SRC_S += ${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Source/TOOLCHAIN_GCC_ARM/startup_${MCU_VARIANT}.S
 
 INC += \
   $(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/CMSIS/Core/Include \
-	$(TOP)/$(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Include \
-	$(TOP)/$(MCU_DIR)/XMCLib/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+	$(TOP)/${SDK_DIR}/CMSIS/Core/Include \
+	$(TOP)/${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Include \
+	$(TOP)/${SDK_DIR}/XMCLib/inc
diff --git a/hw/bsp/zephyr_board_aliases.cmake b/hw/bsp/zephyr_board_aliases.cmake
new file mode 100644
index 000000000..91ffc3a39
--- /dev/null
+++ b/hw/bsp/zephyr_board_aliases.cmake
@@ -0,0 +1 @@
+set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840)
diff --git a/hw/mcu/allwinner b/hw/mcu/allwinner
deleted file mode 160000
index 8e5e89e8e..000000000
--- a/hw/mcu/allwinner
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 8e5e89e8e132c0fd90e72d5422e5d3d68232b756
diff --git a/hw/mcu/bridgetek/ft9xx/Readme.md b/hw/mcu/bridgetek/ft9xx/Readme.md
index 1db91058c..adf8fc765 100644
--- a/hw/mcu/bridgetek/ft9xx/Readme.md
+++ b/hw/mcu/bridgetek/ft9xx/Readme.md
@@ -2,6 +2,6 @@
 
 **BridgeTek** provides a hardware abstraction library with software source code for the SDKs for FT9xx software family.
 
-Whole SDK repository is installed as part of the FT9xx Toolchain and can be downloaded from BridgeTek web page `https://www.brtchip.com`. 
+Whole SDK repository is installed as part of the FT9xx Toolchain and can be downloaded from BridgeTek web page `https://www.brtchip.com`.
 
-Registers definition files, and included peripheral register definition files have licenses that allow for redistribution.  
+Registers definition files, and included peripheral register definition files have licenses that allow for redistribution.
diff --git a/hw/mcu/bridgetek/ft9xx/ft90x-sdk b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
deleted file mode 160000
index e8122eb6b..000000000
--- a/hw/mcu/bridgetek/ft9xx/ft90x-sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit e8122eb6bd6286a1fe31f175a3e3eb0e7770c3e3
diff --git a/hw/mcu/bridgetek/ft9xx/scripts/crt0.S b/hw/mcu/bridgetek/ft9xx/scripts/crt0.S
index 62fa266ee..380b31c37 100644
--- a/hw/mcu/bridgetek/ft9xx/scripts/crt0.S
+++ b/hw/mcu/bridgetek/ft9xx/scripts/crt0.S
@@ -50,11 +50,11 @@ _start:
 
 codestart:
         jmp    init
-        
+
 .global _exithook
 _exithook:               # Debugger uses '_exithook' at 0x90 to catch program exit
         return
-        
+
 init:
         # Disable all interrupts
         ldk     $r0,0x80
@@ -63,12 +63,12 @@ init:
 .else
         sta.b   0x100e3,$r0
 .endif
-        
+
         # Reset all peripherals
         # lda.l   $r0, 0x10018
         # bins.l  $r0, $r0, 0x23F  # Set bit 31
         # sta.l   0x10018, $r0
-        
+
         # Initialize DATA by copying from program memory
         ldk.l   $r0,__data_load_start
         ldk.l   $r1,__data_load_end
diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom
deleted file mode 160000
index 083700860..000000000
--- a/hw/mcu/broadcom
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 08370086080759ed54ac1136d62d2ad24c6fa267
diff --git a/hw/mcu/dialog/README.md b/hw/mcu/dialog/README.md
index 69676f081..33d270aac 100644
--- a/hw/mcu/dialog/README.md
+++ b/hw/mcu/dialog/README.md
@@ -3,7 +3,5 @@
 **Dialog Semiconductors** provides SDKs for DA146x MCU family.
 Most of the files there can't be redistributed.
 Registers definition file `DA1469xAB.h` and some **ARM** originated headers are have licenses that allow
-for redistribution.  
+for redistribution.
 Whole SDK repository can be downloaded from Dialog Semiconductor web page `https://www.dialog.com`
-
-
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
index b324eb286..7e8067a6f 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
@@ -24,4 +24,3 @@
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
-
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
index fa2ca5d94..faf8b852a 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
@@ -954,11 +954,11 @@ typedef struct {                                /*!< (@ 0x50030A00) LRA Structur
   __IOM uint32_t  LRA_FLT_COEF3_REG;            /*!< (@ 0x00000034) LRA Filter Coefficient Register                            */
   __IOM uint32_t  LRA_BRD_LS_REG;               /*!< (@ 0x00000038) LRA Bridge Register                                        */
   __IOM uint32_t  LRA_BRD_HS_REG;               /*!< (@ 0x0000003C) LRA Bridge Register                                        */
-  __IOM uint32_t  LRA_BRD_STAT_REG;             /*!< (@ 0x00000040) LRA Bridge Staus Register                                  */
+  __IOM uint32_t  LRA_BRD_STAT_REG;             /*!< (@ 0x00000040) LRA Bridge Status Register                                  */
   __IOM uint32_t  LRA_ADC_CTRL1_REG;            /*!< (@ 0x00000044) General Purpose ADC Control Register                       */
   __IM  uint32_t  RESERVED[2];
   __IOM uint32_t  LRA_ADC_RESULT_REG;           /*!< (@ 0x00000050) General Purpose ADC Result Register                        */
-  __IOM uint32_t  LRA_LDO_REG;                  /*!< (@ 0x00000054) LRA LDO Regsiter                                           */
+  __IOM uint32_t  LRA_LDO_REG;                  /*!< (@ 0x00000054) LRA LDO Register                                           */
   __IOM uint32_t  LRA_DFT_REG;                  /*!< (@ 0x00000058) LRA test Register                                          */
 } LRA_Type;                                     /*!< Size = 92 (0x5c)                                                          */
 
@@ -1043,7 +1043,7 @@ typedef struct {                                /*!< (@ 0x50000200) PDC Structur
   __IOM uint32_t  PDC_CTRL15_REG;               /*!< (@ 0x0000003C) PDC control register                                       */
   __IM  uint32_t  RESERVED[16];
   __IOM uint32_t  PDC_ACKNOWLEDGE_REG;          /*!< (@ 0x00000080) Clear a pending PDC bit                                    */
-  __IOM uint32_t  PDC_PENDING_REG;              /*!< (@ 0x00000084) Shows any pending wakup event                              */
+  __IOM uint32_t  PDC_PENDING_REG;              /*!< (@ 0x00000084) Shows any pending wakeup event                              */
   __IOM uint32_t  PDC_PENDING_SNC_REG;          /*!< (@ 0x00000088) Shows any pending IRQ to SNC                               */
   __IOM uint32_t  PDC_PENDING_CM33_REG;         /*!< (@ 0x0000008C) Shows any pending IRQ to CM33                              */
   __IOM uint32_t  PDC_PENDING_CMAC_REG;         /*!< (@ 0x00000090) Shows any pending IRQ to CM33                              */
@@ -1752,8 +1752,8 @@ typedef struct {                                /*!< (@ 0x50000100) WAKEUP Struc
   __IOM uint32_t  WKUP_SELECT_P1_REG;           /*!< (@ 0x00000018) select which inputs from P1 port can trigger
                                                                     wkup counter                                               */
   __IM  uint32_t  RESERVED2[3];
-  __IOM uint32_t  WKUP_POL_P0_REG;              /*!< (@ 0x00000028) select the sesitivity polarity for each P0 input           */
-  __IOM uint32_t  WKUP_POL_P1_REG;              /*!< (@ 0x0000002C) select the sesitivity polarity for each P1 input           */
+  __IOM uint32_t  WKUP_POL_P0_REG;              /*!< (@ 0x00000028) select the sensitivity polarity for each P0 input           */
+  __IOM uint32_t  WKUP_POL_P1_REG;              /*!< (@ 0x0000002C) select the sensitivity polarity for each P1 input           */
   __IM  uint32_t  RESERVED3[3];
   __IOM uint32_t  WKUP_STATUS_P0_REG;           /*!< (@ 0x0000003C) Event status register for P0                               */
   __IOM uint32_t  WKUP_STATUS_P1_REG;           /*!< (@ 0x00000040) Event status register for P1                               */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
index fdb1a971c..8f871ea31 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
@@ -268,4 +268,3 @@
 
 
 #endif /* __CMSIS_COMPILER_H */
-
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
index 47a4b59d8..812c3789a 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
@@ -47,9 +47,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
-#endif                                           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
@@ -586,7 +586,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -631,7 +631,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
@@ -768,7 +768,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_get_fpscr) 
+#if __has_builtin(__builtin_arm_get_fpscr)
 // Re-enable using built-in when GCC has been fixed
 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
index e2cf6b966..a8cd3ea45 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
@@ -62,7 +62,7 @@
  */
 
 #include "cmsis_version.h"
- 
+
 /*  CMSIS CM0 definitions */
 #define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
index 7249e1331..05b61383e 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
@@ -2065,7 +2065,7 @@ typedef struct
 
 /* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
 
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
 #define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
 
 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
@@ -2080,7 +2080,7 @@ typedef struct
 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
-#else 
+#else
 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
 #endif
 
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
index bc3b05109..50bb56333 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
@@ -103,7 +103,7 @@
   (MPU_RLAR_EN_Msk))
 
 #if defined(MPU_RLAR_PXN_Pos)
-  
+
 /** \brief Region Limit Address Register with PXN value
 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
 * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
@@ -114,7 +114,7 @@
   ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
   ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
   (MPU_RLAR_EN_Msk))
-  
+
 #endif
 
 /**
@@ -124,7 +124,7 @@ typedef struct {
   uint32_t RBAR;                   /*!< Region Base Address Register value */
   uint32_t RLAR;                   /*!< Region Limit Address Register value */
 } ARM_MPU_Region_t;
-    
+
 /** Enable the MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
@@ -185,11 +185,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at
   const uint8_t reg = idx / 4U;
   const uint32_t pos = ((idx % 4U) * 8U);
   const uint32_t mask = 0xFFU << pos;
-  
+
   if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
     return; // invalid index
   }
-  
+
   mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
 }
 
@@ -236,7 +236,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
 * \param rnr Region number to be cleared.
 */
 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
-{  
+{
   ARM_MPU_ClrRegionEx(MPU_NS, rnr);
 }
 #endif
@@ -246,7 +246,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
   mpu->RNR = rnr;
@@ -258,7 +258,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
   ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
@@ -269,10 +269,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
-  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
 }
 #endif
 
@@ -284,7 +284,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
   uint32_t i;
-  for (i = 0U; i < len; ++i) 
+  for (i = 0U; i < len; ++i)
   {
     dst[i] = src[i];
   }
@@ -296,7 +296,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
   if (cnt == 1U) {
@@ -305,7 +305,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
   } else {
     uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
     uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
-    
+
     mpu->RNR = rnrBase;
     while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
       uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
@@ -316,7 +316,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
       rnrBase += MPU_TYPE_RALIASES;
       mpu->RNR = rnrBase;
     }
-    
+
     ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
   }
 }
@@ -326,7 +326,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   ARM_MPU_LoadEx(MPU, rnr, table, cnt);
 }
@@ -337,11 +337,10 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
 }
 #endif
 
 #endif
-
diff --git a/hw/mcu/dialog/da1469x/da1469x.ld b/hw/mcu/dialog/da1469x/da1469x.ld
index c91dea841..0133f3759 100644
--- a/hw/mcu/dialog/da1469x/da1469x.ld
+++ b/hw/mcu/dialog/da1469x/da1469x.ld
@@ -225,4 +225,3 @@ SECTIONS
     /* Check that intvect is at the beginning of RAM */
     ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
 }
-
diff --git a/hw/mcu/dialog/da1469x/include/mcu/mcu.h b/hw/mcu/dialog/da1469x/include/mcu/mcu.h
index 1e6736785..38961e828 100644
--- a/hw/mcu/dialog/da1469x/include/mcu/mcu.h
+++ b/hw/mcu/dialog/da1469x/include/mcu/mcu.h
@@ -162,4 +162,3 @@ void mcu_gpio_exit_sleep(void);
 #endif
 
 #endif /* __MCU_MCU_H_ */
-
diff --git a/hw/mcu/dialog/da1469x/src/system_da1469x.c b/hw/mcu/dialog/da1469x/src/system_da1469x.c
index 538bac79f..91477b553 100644
--- a/hw/mcu/dialog/da1469x/src/system_da1469x.c
+++ b/hw/mcu/dialog/da1469x/src/system_da1469x.c
@@ -34,7 +34,7 @@ SystemInit(void)
   __ISB();
 #endif
 
-  /* Freez watchdog */
+  /* Freeze watchdog */
   GPREG->SET_FREEZE_REG |= GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
   /* Initialize power domains (disable radio only) */
   CRG_TOP->PMU_CTRL_REG = CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk;
diff --git a/hw/mcu/gd/nuclei-sdk b/hw/mcu/gd/nuclei-sdk
deleted file mode 160000
index 7eb7bfa9e..000000000
--- a/hw/mcu/gd/nuclei-sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7
diff --git a/hw/mcu/infineon/mtb-xmclib-cat3 b/hw/mcu/infineon/mtb-xmclib-cat3
deleted file mode 160000
index daf5500d0..000000000
--- a/hw/mcu/infineon/mtb-xmclib-cat3
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit daf5500d03cba23e68c2f241c30af79cd9d63880
diff --git a/hw/mcu/microchip b/hw/mcu/microchip
deleted file mode 160000
index 9e8b37e30..000000000
--- a/hw/mcu/microchip
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9e8b37e307d8404033bb881623a113931e1edf27
diff --git a/hw/mcu/mindmotion/mm32sdk b/hw/mcu/mindmotion/mm32sdk
deleted file mode 160000
index 708a71529..000000000
--- a/hw/mcu/mindmotion/mm32sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 708a7152952ac595d24837069dcc0f7f59a4c30b
diff --git a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
index 76a432bfd..9ba24f458 100644
--- a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
+++ b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
@@ -539,7 +539,7 @@ SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_v
 
 
 /**@brief Remove a Vendor Specific base UUID.
- * 
+ *
  * @details This call removes a Vendor Specific base UUID that has been added with @ref sd_ble_uuid_vs_add. This function allows
  * the application to reuse memory allocated for Vendor Specific base UUIDs.
  *
diff --git a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
index c434fefb3..e11149435 100644
--- a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
+++ b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
@@ -1666,7 +1666,7 @@ SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr
  *
  * @retval ::NRF_SUCCESS                  Address successfully retrieved.
  * @retval ::NRF_ERROR_INVALID_ADDR       Invalid or NULL pointer supplied.
- * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. 
+ * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found.
  * @retval ::NRF_ERROR_INVALID_STATE      The advertising set is currently not advertising.
  */
 SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr));
diff --git a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
index edaf6641f..8cbed0fac 100644
--- a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
+++ b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
@@ -286,7 +286,7 @@ typedef struct
 /**@brief L2CAP event structure. */
 typedef struct
 {
-  uint16_t conn_handle;                                     /**< Connection Handle on which the event occured. */
+  uint16_t conn_handle;                                     /**< Connection Handle on which the event occurred. */
   uint16_t local_cid;                                       /**< Local Channel ID of the L2CAP channel, or
                                                                  @ref BLE_L2CAP_CID_INVALID if not present. */
   union
diff --git a/hw/mcu/nordic/nrfx b/hw/mcu/nordic/nrfx
deleted file mode 160000
index 281cc2e17..000000000
--- a/hw/mcu/nordic/nrfx
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 281cc2e178fd9a470d844b3afdea9eb322a0b0e8
diff --git a/hw/mcu/nordic/nrfx_config.h b/hw/mcu/nordic/nrfx_config.h
deleted file mode 100644
index 6a974ba70..000000000
--- a/hw/mcu/nordic/nrfx_config.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef NRFX_CONFIG_H__
-#define NRFX_CONFIG_H__
-
-#define NRFX_POWER_ENABLED   1
-#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  7
-
-#define NRFX_CLOCK_ENABLED   0
-
-#define NRFX_UARTE_ENABLED   1
-#define NRFX_UARTE0_ENABLED  1
-
-#define NRFX_UARTE1_ENABLED  0
-#define NRFX_UARTE2_ENABLED  0
-#define NRFX_UARTE3_ENABLED  0
-
-#define NRFX_PRS_ENABLED     0
-
-#endif // NRFX_CONFIG_H__
diff --git a/hw/mcu/nuvoton b/hw/mcu/nuvoton
deleted file mode 160000
index 2204191ec..000000000
--- a/hw/mcu/nuvoton
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2204191ec76283371419fbcec207da02e1bc22fa
diff --git a/hw/mcu/nxp/lpcopen b/hw/mcu/nxp/lpcopen
deleted file mode 160000
index 43c45c854..000000000
--- a/hw/mcu/nxp/lpcopen
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 43c45c85405a5dd114fff0ea95cca62837740c13
diff --git a/hw/mcu/nxp/mcux-sdk b/hw/mcu/nxp/mcux-sdk
deleted file mode 160000
index ae2ab01d9..000000000
--- a/hw/mcu/nxp/mcux-sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294
diff --git a/hw/mcu/nxp/nxp_sdk b/hw/mcu/nxp/nxp_sdk
deleted file mode 160000
index 845c8fc49..000000000
--- a/hw/mcu/nxp/nxp_sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 845c8fc49b6fb660f06a5c45225494eacb06f00c
diff --git a/hw/mcu/raspberry_pi/Pico-PIO-USB b/hw/mcu/raspberry_pi/Pico-PIO-USB
deleted file mode 160000
index f78dc9b2c..000000000
--- a/hw/mcu/raspberry_pi/Pico-PIO-USB
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit f78dc9b2c7fa9b82587e43babdc1d21294a32985
diff --git a/hw/mcu/renesas/rx b/hw/mcu/renesas/rx
deleted file mode 160000
index 706b4e0cf..000000000
--- a/hw/mcu/renesas/rx
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 706b4e0cf485605c32351e2f90f5698267996023
diff --git a/hw/mcu/silabs/cmsis-dfp-efm32gg12b b/hw/mcu/silabs/cmsis-dfp-efm32gg12b
deleted file mode 160000
index f1c31b788..000000000
--- a/hw/mcu/silabs/cmsis-dfp-efm32gg12b
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit f1c31b7887669cb230b3ea63f9b56769078960bc
diff --git a/hw/mcu/sony/cxd56/mkspk/mkspk.c b/hw/mcu/sony/cxd56/mkspk/mkspk.c
index c447ad7da..24e0cf77b 100644
--- a/hw/mcu/sony/cxd56/mkspk/mkspk.c
+++ b/hw/mcu/sony/cxd56/mkspk/mkspk.c
@@ -172,6 +172,7 @@ static struct elf_file *load_elf(const char *filename)
   ef = (struct elf_file *)malloc(sizeof(*ef));
   if (!ef)
     {
+      fclose(fp);
       return NULL;
     }
 
@@ -182,6 +183,8 @@ static struct elf_file *load_elf(const char *filename)
   buf = (char *)malloc(fsize);
   if (!buf)
     {
+      free(ef);
+      fclose(fp);
       return NULL;
     }
 
@@ -189,6 +192,8 @@ static struct elf_file *load_elf(const char *filename)
   fclose(fp);
   if (ret != 1)
     {
+      free(ef);
+      free(buf);
       return NULL;
     }
 
@@ -349,8 +354,12 @@ int main(int argc, char **argv)
     }
 
   spkimage = create_image(elf, args->core, args->savename, &size);
+  if(elf->data) {
+      free(elf->data);
+  }
   free(elf);
 
+
   c = cipher_init(vmk, NULL);
   cipher_calc_cmac(c, spkimage, size, (uint8_t *) spkimage + size);
   cipher_deinit(c);
diff --git a/hw/mcu/sony/cxd56/spresense-exported-sdk b/hw/mcu/sony/cxd56/spresense-exported-sdk
deleted file mode 160000
index 2ec2a1538..000000000
--- a/hw/mcu/sony/cxd56/spresense-exported-sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2ec2a1538362696118dc3fdf56f33dacaf8f4067
diff --git a/hw/mcu/sony/cxd56/tools/flash_writer.py b/hw/mcu/sony/cxd56/tools/flash_writer.py
index 840f10c32..387e679da 100755
--- a/hw/mcu/sony/cxd56/tools/flash_writer.py
+++ b/hw/mcu/sony/cxd56/tools/flash_writer.py
@@ -1,4 +1,4 @@
-#! /usr/bin/env python3
+#!/usr/bin/env python3
 
 # Copyright (C) 2018 Sony Semiconductor Solutions Corp.
 #
@@ -46,7 +46,7 @@ import xmodem
 
 import_serial_module = True
 
-# When SDK release, plase set SDK_RELEASE as True.
+# When SDK release, please set SDK_RELEASE as True.
 SDK_RELEASE = False
 
 if SDK_RELEASE :
@@ -508,7 +508,7 @@ def main():
 	do_wait_reset = True
 	if ConfigArgs.AUTO_RESET:
 		if subprocess.call("cd " + sys.path[0] + "; ./reset_board.sh", shell=True) == 0:
-			print("auto reset board sucess!!")
+			print("auto reset board success!!")
 			do_wait_reset = False
 			bootrom_msg = writer.cancel_autoboot()
 
@@ -536,7 +536,7 @@ def main():
 
 	# Remove files
 	if ConfigArgs.ERASE_NAME :
-		print(">>> Remove exisiting files ...")
+		print(">>> Remove existing files ...")
 		writer.delete_files(ConfigArgs.ERASE_NAME)
 
 	# Install files
diff --git a/hw/mcu/sony/cxd56/tools/xmodem.py b/hw/mcu/sony/cxd56/tools/xmodem.py
old mode 100644
new mode 100755
index c93430056..3ee2698f7
--- a/hw/mcu/sony/cxd56/tools/xmodem.py
+++ b/hw/mcu/sony/cxd56/tools/xmodem.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
 '''
 ===============================
  XMODEM file transfer protocol
@@ -147,7 +148,7 @@ class XMODEM(object):
     >>> modem = XMODEM(getc, putc)
 
 
-    :param getc: Function to retreive bytes from a stream
+    :param getc: Function to retrieve bytes from a stream
     :type getc: callable
     :param putc: Function to transmit bytes to a stream
     :type putc: callable
@@ -215,7 +216,7 @@ class XMODEM(object):
             >>> print modem.send(stream)
             True
 
-        Returns ``True`` upon succesful transmission or ``False`` in case of
+        Returns ``True`` upon successful transmission or ``False`` in case of
         failure.
 
         :param stream: The stream object to send data from.
diff --git a/hw/mcu/st/cmsis_device_f0 b/hw/mcu/st/cmsis_device_f0
deleted file mode 160000
index 2fc25ee22..000000000
--- a/hw/mcu/st/cmsis_device_f0
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2fc25ee22264bc27034358be0bd400b893ef837e
diff --git a/hw/mcu/st/cmsis_device_f1 b/hw/mcu/st/cmsis_device_f1
deleted file mode 160000
index 6601104a6..000000000
--- a/hw/mcu/st/cmsis_device_f1
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 6601104a6397299b7304fd5bcd9a491f56cb23a6
diff --git a/hw/mcu/st/cmsis_device_f2 b/hw/mcu/st/cmsis_device_f2
deleted file mode 160000
index 182fcb368..000000000
--- a/hw/mcu/st/cmsis_device_f2
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 182fcb3681ce116816feb41b7764f1b019ce796f
diff --git a/hw/mcu/st/cmsis_device_f3 b/hw/mcu/st/cmsis_device_f3
deleted file mode 160000
index 5e4ee5ed7..000000000
--- a/hw/mcu/st/cmsis_device_f3
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b
diff --git a/hw/mcu/st/cmsis_device_f4 b/hw/mcu/st/cmsis_device_f4
deleted file mode 160000
index 2615e866f..000000000
--- a/hw/mcu/st/cmsis_device_f4
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2615e866fa48fe1ff1af9e31c348813f2b19e7ec
diff --git a/hw/mcu/st/cmsis_device_f7 b/hw/mcu/st/cmsis_device_f7
deleted file mode 160000
index fc676ef1a..000000000
--- a/hw/mcu/st/cmsis_device_f7
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fc676ef1ad177eb874eaa06444d3d75395fc51f4
diff --git a/hw/mcu/st/cmsis_device_g0 b/hw/mcu/st/cmsis_device_g0
deleted file mode 160000
index 08258b28e..000000000
--- a/hw/mcu/st/cmsis_device_g0
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 08258b28ee95f50cb9624d152a1cbf084be1f9a5
diff --git a/hw/mcu/st/cmsis_device_g4 b/hw/mcu/st/cmsis_device_g4
deleted file mode 160000
index ce822adb1..000000000
--- a/hw/mcu/st/cmsis_device_g4
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit ce822adb1dc552b3aedd13621edbc7fdae124878
diff --git a/hw/mcu/st/cmsis_device_h7 b/hw/mcu/st/cmsis_device_h7
deleted file mode 160000
index 60dc2c913..000000000
--- a/hw/mcu/st/cmsis_device_h7
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 60dc2c913203dc8629dc233d4384dcc41c91e77f
diff --git a/hw/mcu/st/cmsis_device_l0 b/hw/mcu/st/cmsis_device_l0
deleted file mode 160000
index 06748ca1f..000000000
--- a/hw/mcu/st/cmsis_device_l0
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 06748ca1f93827befdb8b794402320d94d02004f
diff --git a/hw/mcu/st/cmsis_device_l1 b/hw/mcu/st/cmsis_device_l1
deleted file mode 160000
index 7f16ec0a1..000000000
--- a/hw/mcu/st/cmsis_device_l1
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 7f16ec0a1c4c063f84160b4cc6bf88ad554a823e
diff --git a/hw/mcu/st/cmsis_device_l4 b/hw/mcu/st/cmsis_device_l4
deleted file mode 160000
index 6ca7312fa..000000000
--- a/hw/mcu/st/cmsis_device_l4
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 6ca7312fa6a5a460b5a5a63d66da527fdd8359a6
diff --git a/hw/mcu/st/cmsis_device_l5 b/hw/mcu/st/cmsis_device_l5
deleted file mode 160000
index d922865fc..000000000
--- a/hw/mcu/st/cmsis_device_l5
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit d922865fc0326a102c26211c44b8e42f52c1e53d
diff --git a/hw/mcu/st/cmsis_device_u5 b/hw/mcu/st/cmsis_device_u5
deleted file mode 160000
index bc00f3c9d..000000000
--- a/hw/mcu/st/cmsis_device_u5
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit bc00f3c9d8a4e25220f84c26d414902cc6bdf566
diff --git a/hw/mcu/st/cmsis_device_wb b/hw/mcu/st/cmsis_device_wb
deleted file mode 160000
index 9c5d1920d..000000000
--- a/hw/mcu/st/cmsis_device_wb
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9c5d1920dd9fabbe2548e10561d63db829bb744f
diff --git a/hw/mcu/st/stm32f0xx_hal_driver b/hw/mcu/st/stm32f0xx_hal_driver
deleted file mode 160000
index 0e95cd886..000000000
--- a/hw/mcu/st/stm32f0xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0e95cd88657030f640a11e690a8a5186c7712ea5
diff --git a/hw/mcu/st/stm32f1xx_hal_driver b/hw/mcu/st/stm32f1xx_hal_driver
deleted file mode 160000
index 1dd9d3662..000000000
--- a/hw/mcu/st/stm32f1xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29
diff --git a/hw/mcu/st/stm32f2xx_hal_driver b/hw/mcu/st/stm32f2xx_hal_driver
deleted file mode 160000
index c75ace9b9..000000000
--- a/hw/mcu/st/stm32f2xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit c75ace9b908a9aca631193ebf2466963b8ea33d0
diff --git a/hw/mcu/st/stm32f3xx_hal_driver b/hw/mcu/st/stm32f3xx_hal_driver
deleted file mode 160000
index 1761b6207..000000000
--- a/hw/mcu/st/stm32f3xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 1761b6207318ede021706e75aae78f452d72b6fa
diff --git a/hw/mcu/st/stm32f4xx_hal_driver b/hw/mcu/st/stm32f4xx_hal_driver
deleted file mode 160000
index 04e99fbda..000000000
--- a/hw/mcu/st/stm32f4xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 04e99fbdabd00ab8f370f377c66b0a4570365b58
diff --git a/hw/mcu/st/stm32f7xx_hal_driver b/hw/mcu/st/stm32f7xx_hal_driver
deleted file mode 160000
index f7ffdf6bf..000000000
--- a/hw/mcu/st/stm32f7xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit f7ffdf6bf72110e58b42c632b0a051df5997e4ee
diff --git a/hw/mcu/st/stm32g0xx_hal_driver b/hw/mcu/st/stm32g0xx_hal_driver
deleted file mode 160000
index 5b53e6cee..000000000
--- a/hw/mcu/st/stm32g0xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 5b53e6cee664a82b16c86491aa0060e2110c00cb
diff --git a/hw/mcu/st/stm32g4xx_hal_driver b/hw/mcu/st/stm32g4xx_hal_driver
deleted file mode 160000
index 8b4518417..000000000
--- a/hw/mcu/st/stm32g4xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 8b4518417706d42eef5c14e56a650005abf478a8
diff --git a/hw/mcu/st/stm32h7xx_hal_driver b/hw/mcu/st/stm32h7xx_hal_driver
deleted file mode 160000
index d8461b980..000000000
--- a/hw/mcu/st/stm32h7xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04
diff --git a/hw/mcu/st/stm32l0xx_hal_driver b/hw/mcu/st/stm32l0xx_hal_driver
deleted file mode 160000
index fbdacaf6f..000000000
--- a/hw/mcu/st/stm32l0xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b
diff --git a/hw/mcu/st/stm32l1xx_hal_driver b/hw/mcu/st/stm32l1xx_hal_driver
deleted file mode 160000
index 44efc446f..000000000
--- a/hw/mcu/st/stm32l1xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 44efc446fa69ed8344e7fd966e68ed11043b35d9
diff --git a/hw/mcu/st/stm32l4xx_hal_driver b/hw/mcu/st/stm32l4xx_hal_driver
deleted file mode 160000
index aee3d5bf2..000000000
--- a/hw/mcu/st/stm32l4xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit aee3d5bf283ae5df87532b781bdd01b7caf256fc
diff --git a/hw/mcu/st/stm32l5xx_hal_driver b/hw/mcu/st/stm32l5xx_hal_driver
deleted file mode 160000
index 675c32a75..000000000
--- a/hw/mcu/st/stm32l5xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 675c32a75df37f39d50d61f51cb0dcf53f07e1cb
diff --git a/hw/mcu/st/stm32u5xx_hal_driver b/hw/mcu/st/stm32u5xx_hal_driver
deleted file mode 160000
index 2e1d4cdb3..000000000
--- a/hw/mcu/st/stm32u5xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2e1d4cdb386e33391cb261dfff4fefa92e4aa35a
diff --git a/hw/mcu/st/stm32wbxx_hal_driver b/hw/mcu/st/stm32wbxx_hal_driver
deleted file mode 160000
index 2c5f06638..000000000
--- a/hw/mcu/st/stm32wbxx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2c5f06638be516c1b772f768456ba637f077bac8
diff --git a/hw/mcu/ti b/hw/mcu/ti
deleted file mode 160000
index 143ed6cc2..000000000
--- a/hw/mcu/ti
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 143ed6cc20a7615d042b03b21e070197d473e6e5
diff --git a/lib/CMSIS_5 b/lib/CMSIS_5
deleted file mode 160000
index 202852626..000000000
--- a/lib/CMSIS_5
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 20285262657d1b482d132d20d755c8c330d55c1f
diff --git a/lib/FreeRTOS-Kernel b/lib/FreeRTOS-Kernel
deleted file mode 160000
index 2a604f4a2..000000000
--- a/lib/FreeRTOS-Kernel
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h b/lib/SEGGER_RTT/Config/SEGGER_RTT_Conf.h
similarity index 68%
rename from lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h
rename to lib/SEGGER_RTT/Config/SEGGER_RTT_Conf.h
index 5e79d7e67..3ac38dcf1 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h
+++ b/lib/SEGGER_RTT/Config/SEGGER_RTT_Conf.h
@@ -3,7 +3,7 @@
 *                        The Embedded Experts                        *
 **********************************************************************
 *                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
+*            (c) 1995 - 2020 SEGGER Microcontroller GmbH             *
 *                                                                    *
 *       www.segger.com     Support: support@segger.com               *
 *                                                                    *
@@ -46,7 +46,7 @@ File    : SEGGER_RTT_Conf.h
 Purpose : Implementation of SEGGER real-time transfer (RTT) which
           allows real-time communication on targets which support
           debugger memory accesses while the CPU is running.
-Revision: $Rev: 18601 $
+Revision: $Rev: 24316 $
 
 */
 
@@ -63,10 +63,25 @@ Revision: $Rev: 18601 $
 *
 **********************************************************************
 */
+
+//
+// Take in and set to correct values for Cortex-A systems with CPU cache
+//
+//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE            (32)          // Largest cache line size (in bytes) in the current system
+//#define SEGGER_RTT_UNCACHED_OFF                   (0xFB000000)  // Address alias where RTT CB and buffers can be accessed uncached
+//
+// Most common case:
+// Up-channel 0: RTT
+// Up-channel 1: SystemView
+//
 #ifndef   SEGGER_RTT_MAX_NUM_UP_BUFFERS
   #define SEGGER_RTT_MAX_NUM_UP_BUFFERS             (3)     // Max. number of up-buffers (T->H) available on this target    (Default: 3)
 #endif
-
+//
+// Most common case:
+// Down-channel 0: RTT
+// Down-channel 1: SystemView
+//
 #ifndef   SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
   #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS           (3)     // Max. number of down-buffers (H->T) available on this target  (Default: 3)
 #endif
@@ -91,12 +106,12 @@ Revision: $Rev: 18601 $
 *
 *       RTT memcpy configuration
 *
-*       memcpy() is good for large amounts of data, 
+*       memcpy() is good for large amounts of data,
 *       but the overhead is big for small amounts, which are usually stored via RTT.
 *       With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead.
 *
 *       SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions.
-*       This is may be required with memory access restrictions, 
+*       This is may be required with memory access restrictions,
 *       such as on Cortex-A devices with MMU.
 */
 #ifndef   SEGGER_RTT_MEMCPY_USE_BYTELOOP
@@ -105,7 +120,7 @@ Revision: $Rev: 18601 $
 //
 // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets
 //
-//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))  
+//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))
 //  #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes)      SEGGER_memcpy((pDest), (pSrc), (NumBytes))
 //#endif
 
@@ -135,18 +150,18 @@ Revision: $Rev: 18601 $
 #if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32))
   #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                    unsigned int LockState;                                         \
+                                    unsigned int _SEGGER_RTT__LockState;                                         \
                                   __asm volatile ("mrs   %0, primask  \n\t"                         \
-                                                  "movs  r1, $1       \n\t"                         \
+                                                  "movs  r1, #1       \n\t"                         \
                                                   "msr   primask, r1  \n\t"                         \
-                                                  : "=r" (LockState)                                \
+                                                  : "=r" (_SEGGER_RTT__LockState)                                \
                                                   :                                                 \
-                                                  : "r1"                                            \
+                                                  : "r1", "cc"                                      \
                                                   );
 
     #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   primask, %0  \n\t"                         \
                                                   :                                                 \
-                                                  : "r" (LockState)                                 \
+                                                  : "r" (_SEGGER_RTT__LockState)                                 \
                                                   :                                                 \
                                                   );                                                \
                                 }
@@ -155,32 +170,32 @@ Revision: $Rev: 18601 $
       #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
     #endif
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                    unsigned int LockState;                                         \
+                                    unsigned int _SEGGER_RTT__LockState;                                         \
                                   __asm volatile ("mrs   %0, basepri  \n\t"                         \
                                                   "mov   r1, %1       \n\t"                         \
                                                   "msr   basepri, r1  \n\t"                         \
-                                                  : "=r" (LockState)                                \
+                                                  : "=r" (_SEGGER_RTT__LockState)                                \
                                                   : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY)          \
-                                                  : "r1"                                            \
+                                                  : "r1", "cc"                                      \
                                                   );
 
     #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   basepri, %0  \n\t"                         \
                                                   :                                                 \
-                                                  : "r" (LockState)                                 \
+                                                  : "r" (_SEGGER_RTT__LockState)                                 \
                                                   :                                                 \
                                                   );                                                \
                                 }
 
-  #elif defined(__ARM_ARCH_7A__)
+  #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__))
     #define SEGGER_RTT_LOCK() {                                                \
-                                 unsigned int LockState;                       \
+                                 unsigned int _SEGGER_RTT__LockState;                       \
                                  __asm volatile ("mrs r1, CPSR \n\t"           \
                                                  "mov %0, r1 \n\t"             \
                                                  "orr r1, r1, #0xC0 \n\t"      \
                                                  "msr CPSR_c, r1 \n\t"         \
-                                                 : "=r" (LockState)            \
+                                                 : "=r" (_SEGGER_RTT__LockState)            \
                                                  :                             \
-                                                 : "r1"                        \
+                                                 : "r1", "cc"                  \
                                                  );
 
     #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t"              \
@@ -190,26 +205,26 @@ Revision: $Rev: 18601 $
                                                 "orr r1, r1, r0 \n\t"          \
                                                 "msr CPSR_c, r1 \n\t"          \
                                                 :                              \
-                                                : "r" (LockState)              \
-                                                : "r0", "r1"                   \
+                                                : "r" (_SEGGER_RTT__LockState)              \
+                                                : "r0", "r1", "cc"             \
                                                 );                             \
                             }
   #elif defined(__riscv) || defined(__riscv_xlen)
     #define SEGGER_RTT_LOCK()  {                                               \
-                                 unsigned int LockState;                       \
+                                 unsigned int _SEGGER_RTT__LockState;                       \
                                  __asm volatile ("csrr  %0, mstatus  \n\t"     \
                                                  "csrci mstatus, 8   \n\t"     \
                                                  "andi  %0, %0,  8   \n\t"     \
-                                                 : "=r" (LockState)            \
+                                                 : "=r" (_SEGGER_RTT__LockState)            \
                                                  :                             \
                                                  :                             \
                                                 );
-                               
+
   #define SEGGER_RTT_UNLOCK()    __asm volatile ("csrr  a1, mstatus  \n\t"     \
                                                  "or    %0, %0, a1   \n\t"     \
                                                  "csrs  mstatus, %0  \n\t"     \
                                                  :                             \
-                                                 : "r"  (LockState)            \
+                                                 : "r"  (_SEGGER_RTT__LockState)            \
                                                  : "a1"                        \
                                                 );                             \
                                }
@@ -227,11 +242,11 @@ Revision: $Rev: 18601 $
   #if (defined (__ARM6M__)          && (__CORE__ == __ARM6M__))             ||                      \
       (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__))
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = __get_PRIMASK();                                      \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_PRIMASK();                                      \
                                   __set_PRIMASK(1);
 
-    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(LockState);                                         \
+    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(_SEGGER_RTT__LockState);                                         \
                                 }
   #elif (defined (__ARM7EM__)         && (__CORE__ == __ARM7EM__))          ||                      \
         (defined (__ARM7M__)          && (__CORE__ == __ARM7M__))           ||                      \
@@ -241,12 +256,36 @@ Revision: $Rev: 18601 $
       #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
     #endif
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = __get_BASEPRI();                                      \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_BASEPRI();                                      \
                                   __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
 
-    #define SEGGER_RTT_UNLOCK()   __set_BASEPRI(LockState);                                         \
+    #define SEGGER_RTT_UNLOCK()   __set_BASEPRI(_SEGGER_RTT__LockState);                                         \
                                 }
+  #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__))                    ||                      \
+        (defined (__ARM7R__) && (__CORE__ == __ARM7R__))
+    #define SEGGER_RTT_LOCK() {                                                                     \
+                                 unsigned int _SEGGER_RTT__LockState;                                            \
+                                 __asm volatile ("mrs r1, CPSR \n\t"                                \
+                                                 "mov %0, r1 \n\t"                                  \
+                                                 "orr r1, r1, #0xC0 \n\t"                           \
+                                                 "msr CPSR_c, r1 \n\t"                              \
+                                                 : "=r" (_SEGGER_RTT__LockState)                                 \
+                                                 :                                                  \
+                                                 : "r1", "cc"                                       \
+                                                 );
+
+    #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t"                                   \
+                                                "mrs r1, CPSR \n\t"                                 \
+                                                "bic r1, r1, #0xC0 \n\t"                            \
+                                                "and r0, r0, #0xC0 \n\t"                            \
+                                                "orr r1, r1, r0 \n\t"                               \
+                                                "msr CPSR_c, r1 \n\t"                               \
+                                                :                                                   \
+                                                : "r" (_SEGGER_RTT__LockState)                                   \
+                                                : "r0", "r1", "cc"                                  \
+                                                );                                                  \
+                            }
   #endif
 #endif
 
@@ -256,11 +295,11 @@ Revision: $Rev: 18601 $
 */
 #ifdef __ICCRX__
   #define SEGGER_RTT_LOCK()   {                                                                     \
-                                unsigned long LockState;                                            \
-                                LockState = __get_interrupt_state();                                \
+                                unsigned long _SEGGER_RTT__LockState;                                            \
+                                _SEGGER_RTT__LockState = __get_interrupt_state();                                \
                                 __disable_interrupt();
 
-  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(LockState);                                   \
+  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(_SEGGER_RTT__LockState);                                   \
                               }
 #endif
 
@@ -270,11 +309,11 @@ Revision: $Rev: 18601 $
 */
 #ifdef __ICCRL78__
   #define SEGGER_RTT_LOCK()   {                                                                     \
-                                __istate_t LockState;                                               \
-                                LockState = __get_interrupt_state();                                \
+                                __istate_t _SEGGER_RTT__LockState;                                               \
+                                _SEGGER_RTT__LockState = __get_interrupt_state();                                \
                                 __disable_interrupt();
 
-  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(LockState);                                   \
+  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(_SEGGER_RTT__LockState);                                   \
                               }
 #endif
 
@@ -285,13 +324,13 @@ Revision: $Rev: 18601 $
 #ifdef __CC_ARM
   #if (defined __TARGET_ARCH_6S_M)
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  register unsigned char PRIMASK __asm( "primask");                 \
-                                  LockState = PRIMASK;                                              \
-                                  PRIMASK = 1u;                                                     \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask");                 \
+                                  _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK;                                              \
+                                  _SEGGER_RTT__PRIMASK = 1u;                                                     \
                                   __schedule_barrier();
 
-    #define SEGGER_RTT_UNLOCK()   PRIMASK = LockState;                                              \
+    #define SEGGER_RTT_UNLOCK()   _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState;                                              \
                                   __schedule_barrier();                                             \
                                 }
   #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
@@ -299,13 +338,13 @@ Revision: $Rev: 18601 $
       #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
     #endif
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
                                   register unsigned char BASEPRI __asm( "basepri");                 \
-                                  LockState = BASEPRI;                                              \
+                                  _SEGGER_RTT__LockState = BASEPRI;                                              \
                                   BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY;                      \
                                   __schedule_barrier();
 
-    #define SEGGER_RTT_UNLOCK()   BASEPRI = LockState;                                              \
+    #define SEGGER_RTT_UNLOCK()   BASEPRI = _SEGGER_RTT__LockState;                                              \
                                   __schedule_barrier();                                             \
                                 }
   #endif
@@ -318,21 +357,21 @@ Revision: $Rev: 18601 $
 #ifdef __TI_ARM__
   #if defined (__TI_ARM_V6M0__)
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = __get_PRIMASK();                                      \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_PRIMASK();                                      \
                                   __set_PRIMASK(1);
 
-    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(LockState);                                         \
+    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(_SEGGER_RTT__LockState);                                         \
                                 }
   #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__))
     #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
       #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
     #endif
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
 
-    #define SEGGER_RTT_UNLOCK()   _set_interrupt_priority(LockState);                               \
+    #define SEGGER_RTT_UNLOCK()   _set_interrupt_priority(_SEGGER_RTT__LockState);                               \
                                 }
   #endif
 #endif
@@ -342,12 +381,13 @@ Revision: $Rev: 18601 $
 *       RTT lock configuration for CCRX
 */
 #ifdef __RX
+  #include <machine.h>
   #define SEGGER_RTT_LOCK()   {                                                                     \
-                                unsigned long LockState;                                            \
-                                LockState = get_psw() & 0x010000;                                   \
-                                clrpsw_i();                           
-                                    
-  #define SEGGER_RTT_UNLOCK()   set_psw(get_psw() | LockState);                                     \
+                                unsigned long _SEGGER_RTT__LockState;                                            \
+                                _SEGGER_RTT__LockState = get_psw() & 0x010000;                                   \
+                                clrpsw_i();
+
+  #define SEGGER_RTT_UNLOCK()   set_psw(get_psw() | _SEGGER_RTT__LockState);                                     \
                               }
 #endif
 
diff --git a/lib/SEGGER_RTT/LICENSE.md b/lib/SEGGER_RTT/LICENSE.md
new file mode 100644
index 000000000..14881c29b
--- /dev/null
+++ b/lib/SEGGER_RTT/LICENSE.md
@@ -0,0 +1,36 @@
+
+                    SEGGER Microcontroller GmbH
+                       The Embedded Experts
+
+           (c) 1995 - 2021 SEGGER Microcontroller GmbH
+          www.segger.com     Support: support@segger.com
+
+        SEGGER RTT  Real Time Transfer for embedded targets
+
+
+    All rights reserved.
+
+    SEGGER strongly recommends to not make any changes
+    to or modify the source code of this software in order to stay
+    compatible with the RTT protocol and J-Link.
+
+    Redistribution and use in source and binary forms, with or
+    without modification, are permitted provided that the following
+    condition is met:
+
+    - Redistributions of source code must retain the above copyright
+     notice, this condition and the following disclaimer.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+    CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+    INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR
+    ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+    OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+    OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+    LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+    USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+    DAMAGE.
diff --git a/lib/SEGGER_RTT/License.txt b/lib/SEGGER_RTT/License.txt
deleted file mode 100644
index e1f5f89ff..000000000
--- a/lib/SEGGER_RTT/License.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Important - Read carefully:
-
-SEGGER RTT - Real Time Transfer for embedded targets
-
-All rights reserved.
-
-SEGGER strongly recommends to not make any changes
-to or modify the source code of this software in order to stay
-compatible with the RTT protocol and J-Link.
-
-Redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following
-condition is met:
-
-o Redistributions of source code must retain the above copyright
-  notice, this condition and the following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
-CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-DAMAGE.
-
-
-(c) 2014 - 2016  SEGGER Microcontroller GmbH
-www.segger.com
diff --git a/lib/SEGGER_RTT/README.md b/lib/SEGGER_RTT/README.md
new file mode 100644
index 000000000..06349d248
--- /dev/null
+++ b/lib/SEGGER_RTT/README.md
@@ -0,0 +1,24 @@
+RTT
+===
+
+SEGGER RTT Sources
+
+https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer
+https://wiki.segger.com/RTT
+
+## Included files
+
+  * `RTT/`
+    * `SEGGER_RTT.c`               - Main module for RTT.
+    * `SEGGER_RTT.h`               - Main header for RTT.
+    * `SEGGER_RTT_ASM_ARMv7M.S`    - Assembly-optimized implementation of RTT functions for ARMv7M processors.
+    * `SEGGER_RTT_Printf.c`        - Simple implementation of printf (`SEGGER_RTT_Printf()`) to write formatted strings via RTT.
+  * `Syscalls/`
+    * `SEGGER_RTT_Syscalls_*.c`    - Low-level syscalls to retarget `printf()` to RTT with different toolchains.
+  * `Config/`
+    * `SEGGER_RTT_Conf.h`          - RTT configuration file.
+  * `Examples/`
+    * `Main_RTT_InputEchoApp.c`    - Example application which echoes input on Channel 0.
+    * `Main_RTT_MenuApp.c`         - Example application to demonstrate RTT bi-directional functionality.
+    * `Main_RTT_PrintfTest.c`      - Example application to test RTT's simple printf implementation.
+    * `Main_RTT_SpeedTestApp.c`    - Example application to measure RTT performance. (Requires embOS)
diff --git a/lib/SEGGER_RTT/README.txt b/lib/SEGGER_RTT/README.txt
deleted file mode 100644
index 49ec655c4..000000000
--- a/lib/SEGGER_RTT/README.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-README.txt for the SEGGER RTT Implementation Pack.
-
-Included files:
-===============
-Root Directory
-  - Examples
-    - Main_RTT_InputEchoApp.c    - Sample application which echoes input on Channel 0.
-    - Main_RTT_MenuApp.c         - Sample application to demonstrate RTT bi-directional functionality.
-    - Main_RTT_PrintfTest.c      - Sample application to test RTT small printf implementation.
-    - Main_RTT_SpeedTestApp.c    - Sample application for measuring RTT performance. embOS needed.
-  - RTT
-    - SEGGER_RTT.c                - The RTT implementation.
-    - SEGGER_RTT.h                - Header for RTT implementation.
-    - SEGGER_RTT_Conf.h           - Pre-processor configuration for the RTT implementation.
-    - SEGGER_RTT_Printf.c         - Simple implementation of printf to write formatted strings via RTT.
-  - Syscalls
-    - RTT_Syscalls_GCC.c          - Low-level syscalls to retarget printf() to RTT with GCC / Newlib.
-    - RTT_Syscalls_IAR.c          - Low-level syscalls to retarget printf() to RTT with IAR compiler.
-    - RTT_Syscalls_KEIL.c         - Low-level syscalls to retarget printf() to RTT with KEIL/uVision compiler.
-    - RTT_Syscalls_SES.c          - Low-level syscalls to retarget printf() to RTT with SEGGER Embedded Studio.
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
index 3ad2b1a12..811d951fd 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
@@ -46,7 +46,7 @@ File    : SEGGER_RTT.c
 Purpose : Implementation of SEGGER real-time transfer (RTT) which
           allows real-time communication on targets which support
           debugger memory accesses while the CPU is running.
-Revision: $Rev: 17697 $
+Revision: $Rev: 29668 $
 
 Additional information:
           Type "int" is assumed to be 32-bits in size
@@ -62,7 +62,7 @@ Additional information:
           WrOff == (RdOff - 1): Buffer is full
           WrOff >  RdOff:       Free space includes wrap-around
           WrOff <  RdOff:       Used space includes wrap-around
-          (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0):  
+          (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0):
                                 Buffer full and wrap-around after next byte
 
 
@@ -80,6 +80,27 @@ Additional information:
 **********************************************************************
 */
 
+#if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+  #ifdef SEGGER_RTT_CB_ALIGN
+    #error "Custom SEGGER_RTT_CB_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_BUFFER_ALIGN
+    #error "Custom SEGGER_RTT_BUFFER_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_PUT_CB_SECTION
+    #error "Custom SEGGER_RTT_PUT_CB_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_PUT_BUFFER_SECTION
+    #error "Custom SEGGER_RTT_PUT_BUFFER_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_BUFFER_ALIGNMENT
+    #error "Custom SEGGER_RTT_BUFFER_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_ALIGNMENT
+    #error "Custom SEGGER_RTT_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+#endif
+
 #ifndef   BUFFER_SIZE_UP
   #define BUFFER_SIZE_UP                                  1024  // Size of the buffer for terminal output of target, up to host
 #endif
@@ -103,11 +124,11 @@ Additional information:
 #endif
 
 #ifndef   SEGGER_RTT_ALIGNMENT
-  #define SEGGER_RTT_ALIGNMENT                            0
+  #define SEGGER_RTT_ALIGNMENT                            SEGGER_RTT_CPU_CACHE_LINE_SIZE
 #endif
 
 #ifndef   SEGGER_RTT_BUFFER_ALIGNMENT
-  #define SEGGER_RTT_BUFFER_ALIGNMENT                     0
+  #define SEGGER_RTT_BUFFER_ALIGNMENT                     SEGGER_RTT_CPU_CACHE_LINE_SIZE
 #endif
 
 #ifndef   SEGGER_RTT_MODE_DEFAULT
@@ -127,7 +148,7 @@ Additional information:
 #endif
 
 #ifndef   STRCPY
-  #define STRCPY(pDest, pSrc, NumBytes)                   strcpy((pDest), (pSrc))
+  #define STRCPY(pDest, pSrc)                             strcpy((pDest), (pSrc))
 #endif
 
 #ifndef   SEGGER_RTT_MEMCPY_USE_BYTELOOP
@@ -143,17 +164,17 @@ Additional information:
 #endif
 
 #ifndef   MIN
-  #define MIN(a, b)         (((a) < (b)) ? (a) : (b))
+  #define MIN(a, b)                                       (((a) < (b)) ? (a) : (b))
 #endif
 
 #ifndef   MAX
-  #define MAX(a, b)         (((a) > (b)) ? (a) : (b))
+  #define MAX(a, b)                                       (((a) > (b)) ? (a) : (b))
 #endif
 //
 // For some environments, NULL may not be defined until certain headers are included
 //
 #ifndef NULL
-  #define NULL 0
+  #define NULL                                            0
 #endif
 
 /*********************************************************************
@@ -162,12 +183,17 @@ Additional information:
 *
 **********************************************************************
 */
+#ifdef __GNUC__
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wcast-align"
+#endif
+
 #if (defined __ICCARM__) || (defined __ICCRX__)
   #define RTT_PRAGMA(P) _Pragma(#P)
 #endif
 
 #if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT
-  #if (defined __GNUC__)
+  #if ((defined __GNUC__) || (defined __clang__))
     #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment)))
   #elif (defined __ICCARM__) || (defined __ICCRX__)
     #define PRAGMA(A) _Pragma(#A)
@@ -183,7 +209,7 @@ Additional information:
 #endif
 
 #if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION)
-  #if (defined __GNUC__)
+  #if ((defined __GNUC__) || (defined __clang__))
     #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var
   #elif (defined __ICCARM__) || (defined __ICCRX__)
 #define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \
@@ -197,7 +223,6 @@ Additional information:
   #define SEGGER_RTT_PUT_SECTION(Var, Section) Var
 #endif
 
-
 #if SEGGER_RTT_ALIGNMENT
   #define SEGGER_RTT_CB_ALIGN(Var)  SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT)
 #else
@@ -230,7 +255,7 @@ Additional information:
 **********************************************************************
 */
 
-static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
+static const unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
 
 /*********************************************************************
 *
@@ -238,13 +263,30 @@ static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7'
 *
 **********************************************************************
 */
+
 //
 // RTT Control Block and allocate buffers for channel 0
 //
-SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT));
-
-SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer  [BUFFER_SIZE_UP]));
-SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN]));
+#if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+  #if ((defined __GNUC__) || (defined __clang__))
+    SEGGER_RTT_CB _SEGGER_RTT                                                             __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE)));
+    static char   _acUpBuffer  [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)]   __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE)));
+    static char   _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE)));
+  #elif (defined __ICCARM__)
+    #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    SEGGER_RTT_CB _SEGGER_RTT;
+    #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    static char   _acUpBuffer  [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)];
+    #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    static char   _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)];
+  #else
+    #error "Don't know how to place _SEGGER_RTT, _acUpBuffer, _acDownBuffer cache-line aligned"
+  #endif
+#else
+  SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT));
+  SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer  [BUFFER_SIZE_UP]));
+  SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN]));
+#endif
 
 static unsigned char _ActiveTerminal;
 
@@ -261,18 +303,29 @@ static unsigned char _ActiveTerminal;
 *
 *  Function description
 *    Initializes the control block an buffers.
-*    May only be called via INIT() to avoid overriding settings.
 *
+*  Notes
+*    (1) May only be called via INIT() to avoid overriding settings.
+*        The only exception is SEGGER_RTT_Init(), to make an intentional override possible.
 */
-#define INIT()  do {                                            \
-                  if (_SEGGER_RTT.acID[0] == '\0') { _DoInit(); }  \
-                } while (0)
+  #define INIT()                                                                             \
+    do {                                                                                     \
+      volatile SEGGER_RTT_CB* pRTTCBInit;                                                    \
+      pRTTCBInit = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \
+      if (pRTTCBInit->acID[0] != 'S') {                                                      \
+        _DoInit();                                                                           \
+      }                                                                                      \
+    } while (0)
+
 static void _DoInit(void) {
-  SEGGER_RTT_CB* p;
+  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
+  static const char _aInitStr[] = "\0\0\0\0\0\0TTR REGGES";  // Init complete ID string to make sure that things also work if RTT is linked to a no-init memory area
+  unsigned i;
   //
   // Initialize control block
   //
-  p = &_SEGGER_RTT;
+  p                     = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
+  memset((SEGGER_RTT_CB*)p, 0, sizeof(_SEGGER_RTT));         // Make sure that the RTT CB is always zero initialized.
   p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
   p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
   //
@@ -280,7 +333,7 @@ static void _DoInit(void) {
   //
   p->aUp[0].sName         = "Terminal";
   p->aUp[0].pBuffer       = _acUpBuffer;
-  p->aUp[0].SizeOfBuffer  = sizeof(_acUpBuffer);
+  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
   p->aUp[0].RdOff         = 0u;
   p->aUp[0].WrOff         = 0u;
   p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
@@ -289,18 +342,20 @@ static void _DoInit(void) {
   //
   p->aDown[0].sName         = "Terminal";
   p->aDown[0].pBuffer       = _acDownBuffer;
-  p->aDown[0].SizeOfBuffer  = sizeof(_acDownBuffer);
+  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
   p->aDown[0].RdOff         = 0u;
   p->aDown[0].WrOff         = 0u;
   p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
   //
   // Finish initialization of the control block.
-  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
-  // in initializer memory (usually flash) by J-Link
+  // Copy Id string backwards to make sure that "SEGGER RTT" is not found in initializer memory (usually flash),
+  // as this would cause J-Link to "find" the control block at a wrong address.
   //
-  STRCPY(&p->acID[7], "RTT", 9);
-  STRCPY(&p->acID[0], "SEGGER", 7);
-  p->acID[6] = ' ';
+  RTT__DMB();                       // Force order of memory accesses for cores that may perform out-of-order memory accesses
+  for (i = 0; i < sizeof(_aInitStr) - 1; ++i) {
+    p->acID[i] = _aInitStr[sizeof(_aInitStr) - 2 - i];  // Skip terminating \0 at the end of the array
+  }
+  RTT__DMB();                       // Force order of memory accesses for cores that may perform out-of-order memory accesses
 }
 
 /*********************************************************************
@@ -327,9 +382,7 @@ static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer,
   unsigned NumBytesWritten;
   unsigned RdOff;
   unsigned WrOff;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  char*    pDst;
-#endif
+  volatile char* pDst;
   //
   // Write data to buffer and handle wrap-around if necessary
   //
@@ -344,8 +397,8 @@ static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer,
     }
     NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff));      // Number of bytes that can be written until buffer wrap-around
     NumBytesToWrite = MIN(NumBytesToWrite, NumBytes);
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pDst = pRing->pBuffer + WrOff;
     NumBytesWritten += NumBytesToWrite;
     NumBytes        -= NumBytesToWrite;
     WrOff           += NumBytesToWrite;
@@ -353,7 +406,7 @@ static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer,
       *pDst++ = *pBuffer++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pBuffer, NumBytesToWrite);
+    SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite);
     NumBytesWritten += NumBytesToWrite;
     pBuffer         += NumBytesToWrite;
     NumBytes        -= NumBytesToWrite;
@@ -362,9 +415,9 @@ static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer,
     if (WrOff == pRing->SizeOfBuffer) {
       WrOff = 0u;
     }
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
   } while (NumBytes);
-  //
   return NumBytesWritten;
 }
 
@@ -390,9 +443,7 @@ static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsign
   unsigned NumBytesAtOnce;
   unsigned WrOff;
   unsigned Rem;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  char*    pDst;
-#endif
+  volatile char* pDst;
 
   WrOff = pRing->WrOff;
   Rem = pRing->SizeOfBuffer - WrOff;
@@ -400,15 +451,17 @@ static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsign
     //
     // All data fits before wrap around
     //
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pDst = pRing->pBuffer + WrOff;
     WrOff += NumBytes;
     while (NumBytes--) {
       *pDst++ = *pData++;
     };
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
 #else
-    SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytes);
+    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes);
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff + NumBytes;
 #endif
   } else {
@@ -416,22 +469,26 @@ static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsign
     // We reach the end of the buffer, so need to wrap around
     //
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pDst = pRing->pBuffer + WrOff;
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
     NumBytesAtOnce = Rem;
     while (NumBytesAtOnce--) {
       *pDst++ = *pData++;
     };
-    pDst = pRing->pBuffer;
+    pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
     NumBytesAtOnce = NumBytes - Rem;
     while (NumBytesAtOnce--) {
       *pDst++ = *pData++;
     };
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = NumBytes - Rem;
 #else
     NumBytesAtOnce = Rem;
-    SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytesAtOnce);
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce);
     NumBytesAtOnce = NumBytes - Rem;
-    SEGGER_RTT_MEMCPY(pRing->pBuffer, pData + Rem, NumBytesAtOnce);
+    pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
+    SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce);
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = NumBytesAtOnce;
 #endif
   }
@@ -496,6 +553,7 @@ static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) {
 *
 **********************************************************************
 */
+
 /*********************************************************************
 *
 *       SEGGER_RTT_ReadUpBufferNoLock()
@@ -504,7 +562,7 @@ static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) {
 *    Reads characters from SEGGER real-time-terminal control block
 *    which have been previously stored by the application.
 *    Do not lock against interrupts and multiple access.
-*    Used to do the same operation that J-Link does, to transfer 
+*    Used to do the same operation that J-Link does, to transfer
 *    RTT data via other channels, such as TCP/IP or UART.
 *
 *  Parameters
@@ -525,12 +583,10 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
   unsigned                WrOff;
   unsigned char*          pBuffer;
   SEGGER_RTT_BUFFER_UP*   pRing;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  const char*             pSrc;
-#endif
-  //
+  volatile char*          pSrc;
+
   INIT();
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   pBuffer = (unsigned char*)pData;
   RdOff = pRing->RdOff;
   WrOff = pRing->WrOff;
@@ -541,8 +597,8 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
   if (RdOff > WrOff) {
     NumBytesRem = pRing->SizeOfBuffer - RdOff;
     NumBytesRem = MIN(NumBytesRem, BufferSize);
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pSrc = pRing->pBuffer + RdOff;
     NumBytesRead += NumBytesRem;
     BufferSize   -= NumBytesRem;
     RdOff        += NumBytesRem;
@@ -550,7 +606,7 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
       *pBuffer++ = *pSrc++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
     NumBytesRead += NumBytesRem;
     pBuffer      += NumBytesRem;
     BufferSize   -= NumBytesRem;
@@ -569,8 +625,8 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
   NumBytesRem = WrOff - RdOff;
   NumBytesRem = MIN(NumBytesRem, BufferSize);
   if (NumBytesRem > 0u) {
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pSrc = pRing->pBuffer + RdOff;
     NumBytesRead += NumBytesRem;
     BufferSize   -= NumBytesRem;
     RdOff        += NumBytesRem;
@@ -578,7 +634,7 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
       *pBuffer++ = *pSrc++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
     NumBytesRead += NumBytesRem;
     pBuffer      += NumBytesRem;
     BufferSize   -= NumBytesRem;
@@ -619,12 +675,10 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
   unsigned                WrOff;
   unsigned char*          pBuffer;
   SEGGER_RTT_BUFFER_DOWN* pRing;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  const char*             pSrc;
-#endif
+  volatile char*          pSrc;
   //
   INIT();
-  pRing = &_SEGGER_RTT.aDown[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   pBuffer = (unsigned char*)pData;
   RdOff = pRing->RdOff;
   WrOff = pRing->WrOff;
@@ -635,8 +689,8 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
   if (RdOff > WrOff) {
     NumBytesRem = pRing->SizeOfBuffer - RdOff;
     NumBytesRem = MIN(NumBytesRem, BufferSize);
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pSrc = pRing->pBuffer + RdOff;
     NumBytesRead += NumBytesRem;
     BufferSize   -= NumBytesRem;
     RdOff        += NumBytesRem;
@@ -644,7 +698,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
       *pBuffer++ = *pSrc++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
     NumBytesRead += NumBytesRem;
     pBuffer      += NumBytesRem;
     BufferSize   -= NumBytesRem;
@@ -663,8 +717,8 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
   NumBytesRem = WrOff - RdOff;
   NumBytesRem = MIN(NumBytesRem, BufferSize);
   if (NumBytesRem > 0u) {
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pSrc = pRing->pBuffer + RdOff;
     NumBytesRead += NumBytesRem;
     BufferSize   -= NumBytesRem;
     RdOff        += NumBytesRem;
@@ -672,7 +726,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
       *pBuffer++ = *pSrc++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
     NumBytesRead += NumBytesRem;
     pBuffer      += NumBytesRem;
     BufferSize   -= NumBytesRem;
@@ -693,7 +747,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
 *  Function description
 *    Reads characters from SEGGER real-time-terminal control block
 *    which have been previously stored by the application.
-*    Used to do the same operation that J-Link does, to transfer 
+*    Used to do the same operation that J-Link does, to transfer
 *    RTT data via other channels, such as TCP/IP or UART.
 *
 *  Parameters
@@ -708,12 +762,12 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
 *    This function must not be called when J-Link might also do RTT.
 *    This function locks against all other RTT operations. I.e. during
 *    the read operation, writing is also locked.
-*    If only one consumer reads from the up buffer, 
+*    If only one consumer reads from the up buffer,
 *    call sEGGER_RTT_ReadUpBufferNoLock() instead.
 */
 unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) {
   unsigned NumBytesRead;
-  //
+
   SEGGER_RTT_LOCK();
   //
   // Call the non-locking read function
@@ -745,7 +799,7 @@ unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned B
 */
 unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) {
   unsigned NumBytesRead;
-  //
+
   SEGGER_RTT_LOCK();
   //
   // Call the non-locking read function
@@ -766,7 +820,7 @@ unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSiz
 *  Function description
 *    Stores a specified number of characters in SEGGER RTT
 *    control block.
-*    SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application 
+*    SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application
 *    and overwrites data if the data does not fit into the buffer.
 *
 *  Parameters
@@ -779,22 +833,19 @@ unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSiz
 *    (2) For performance reasons this function does not call Init()
 *        and may only be called after RTT has been initialized.
 *        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
-*    (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link 
+*    (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link
 *        connection reads RTT data.
 */
 void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
   const char*           pData;
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned              Avail;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  char*                 pDst;
-#endif
-
-  pData = (const char *)pBuffer;
+  volatile char*        pDst;
   //
   // Get "to-host" ring buffer and copy some elements into local variables.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Check if we will overwrite data and need to adjust the RdOff.
   //
@@ -820,15 +871,17 @@ void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuff
       //
       // Last round
       //
+      pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-      pDst = pRing->pBuffer + pRing->WrOff;
       Avail = NumBytes;
       while (NumBytes--) {
         *pDst++ = *pData++;
       };
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff += Avail;
 #else
-      SEGGER_RTT_MEMCPY(pRing->pBuffer + pRing->WrOff, pData, NumBytes);
+      SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes);
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff += NumBytes;
 #endif
       break;
@@ -836,16 +889,18 @@ void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuff
       //
       //  Wrap-around necessary, write until wrap-around and reset WrOff
       //
+      pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-      pDst = pRing->pBuffer + pRing->WrOff;
       NumBytes -= Avail;
       while (Avail--) {
         *pDst++ = *pData++;
       };
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff = 0;
 #else
-      SEGGER_RTT_MEMCPY(pRing->pBuffer + pRing->WrOff, pData, Avail);
+      SEGGER_RTT_MEMCPY((void*)pDst, pData, Avail);
       pData += Avail;
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff = 0;
       NumBytes -= Avail;
 #endif
@@ -889,6 +944,7 @@ unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, u
   unsigned              RdOff;
   unsigned              WrOff;
   unsigned              Rem;
+  volatile char*        pDst;
   //
   // Cases:
   //   1) RdOff <= WrOff => Space until wrap-around is sufficient
@@ -900,21 +956,22 @@ unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, u
   // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough
   //
   pData = (const char *)pBuffer;
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   RdOff = pRing->RdOff;
   WrOff = pRing->WrOff;
+  pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
   if (RdOff <= WrOff) {                                 // Case 1), 2) or 3)
     Avail = pRing->SizeOfBuffer - WrOff - 1u;           // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0)
     if (Avail >= NumBytes) {                            // Case 1)?
-CopyStraight:
-      memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
+      memcpy((void*)pDst, pData, NumBytes);
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff = WrOff + NumBytes;
       return 1;
     }
     Avail += RdOff;                                     // Space incl. wrap-around
     if (Avail >= NumBytes) {                            // Case 2? => If not, we have case 3) (does not fit)
       Rem = pRing->SizeOfBuffer - WrOff;                // Space until end of buffer
-      memcpy(pRing->pBuffer + WrOff, pData, Rem);       // Copy 1st chunk
+      memcpy((void*)pDst, pData, Rem);                  // Copy 1st chunk
       NumBytes -= Rem;
       //
       // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used
@@ -923,15 +980,20 @@ CopyStraight:
       // Therefore, check if 2nd memcpy is necessary at all
       //
       if (NumBytes) {
-        memcpy(pRing->pBuffer, pData + Rem, NumBytes);
+        pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
+        memcpy((void*)pDst, pData + Rem, NumBytes);
       }
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff = NumBytes;
       return 1;
     }
   } else {                                             // Potential case 4)
     Avail = RdOff - WrOff - 1u;
     if (Avail >= NumBytes) {                           // Case 4)? => If not, we have case 5) (does not fit)
-      goto CopyStraight;
+      memcpy((void*)pDst, pData, NumBytes);
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+      pRing->WrOff = WrOff + NumBytes;
+      return 1;
     }
   }
   return 0;     // No space in buffer
@@ -946,7 +1008,7 @@ CopyStraight:
 *    Stores a specified number of characters in SEGGER RTT
 *    control block inside a <Down> buffer.
 *    SEGGER_RTT_WriteDownBufferNoLock does not lock the application.
-*    Used to do the same operation that J-Link does, to transfer 
+*    Used to do the same operation that J-Link does, to transfer
 *    RTT data from other channels, such as TCP/IP or UART.
 *
 *  Parameters
@@ -971,13 +1033,12 @@ unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuf
   unsigned                Avail;
   const char*             pData;
   SEGGER_RTT_BUFFER_UP*   pRing;
-
-  pData = (const char *)pBuffer;
   //
   // Get "to-target" ring buffer.
   // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link.
   //
-  pRing = (SEGGER_RTT_BUFFER_UP*)&_SEGGER_RTT.aDown[BufferIndex];
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // How we output depends upon the mode...
   //
@@ -1047,12 +1108,11 @@ unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsig
   unsigned              Avail;
   const char*           pData;
   SEGGER_RTT_BUFFER_UP* pRing;
-
-  pData = (const char *)pBuffer;
   //
   // Get "to-host" ring buffer.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // How we output depends upon the mode...
   //
@@ -1116,23 +1176,16 @@ unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsig
 *    This function must not be called when J-Link might also do RTT.
 *    This function locks against all other RTT operations. I.e. during
 *    the write operation, writing from the application is also locked.
-*    If only one consumer writes to the down buffer, 
+*    If only one consumer writes to the down buffer,
 *    call SEGGER_RTT_WriteDownBufferNoLock() instead.
 */
 unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
   unsigned Status;
-  //
+
   INIT();
   SEGGER_RTT_LOCK();
-  //
-  // Call the non-locking write function
-  //
-  Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes);
-  //
-  // Finish up.
-  //
+  Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes);  // Call the non-locking write function
   SEGGER_RTT_UNLOCK();
-  //
   return Status;
 }
 
@@ -1157,18 +1210,11 @@ unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, u
 */
 unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
   unsigned Status;
-  //
+
   INIT();
   SEGGER_RTT_LOCK();
-  //
-  // Call the non-locking write function
-  //
-  Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes);
-  //
-  // Finish up.
-  //
+  Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes);  // Call the non-locking write function
   SEGGER_RTT_UNLOCK();
-  //
   return Status;
 }
 
@@ -1226,10 +1272,11 @@ unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) {
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned              WrOff;
   unsigned              Status;
+  volatile char*        pDst;
   //
   // Get "to-host" ring buffer.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Get write position and handle wrap-around if necessary
   //
@@ -1241,7 +1288,9 @@ unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) {
   // Output byte if free space is available
   //
   if (WrOff != pRing->RdOff) {
-    pRing->pBuffer[pRing->WrOff] = c;
+    pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    *pDst = c;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
     Status = 1;
   } else {
@@ -1273,6 +1322,7 @@ unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) {
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned              WrOff;
   unsigned              Status;
+  volatile char*        pDst;
   //
   // Prepare
   //
@@ -1281,7 +1331,7 @@ unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) {
   //
   // Get "to-host" ring buffer.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Get write position and handle wrap-around if necessary
   //
@@ -1293,7 +1343,9 @@ unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) {
   // Output byte if free space is available
   //
   if (WrOff != pRing->RdOff) {
-    pRing->pBuffer[pRing->WrOff] = c;
+    pDst  = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    *pDst = c;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
     Status = 1;
   } else {
@@ -1329,6 +1381,7 @@ unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned              WrOff;
   unsigned              Status;
+  volatile char*        pDst;
   //
   // Prepare
   //
@@ -1337,7 +1390,7 @@ unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
   //
   // Get "to-host" ring buffer.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Get write position and handle wrap-around if necessary
   //
@@ -1357,7 +1410,9 @@ unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
   // Output byte if free space is available
   //
   if (WrOff != pRing->RdOff) {
-    pRing->pBuffer[pRing->WrOff] = c;
+    pDst  = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    *pDst = c;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
     Status = 1;
   } else {
@@ -1367,7 +1422,6 @@ unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
   // Finish up.
   //
   SEGGER_RTT_UNLOCK();
-  //
   return Status;
 }
 
@@ -1438,12 +1492,14 @@ int SEGGER_RTT_WaitKey(void) {
 *    (1) This function is only specified for accesses to RTT buffer 0
 */
 int SEGGER_RTT_HasKey(void) {
+  SEGGER_RTT_BUFFER_DOWN* pRing;
   unsigned RdOff;
   int r;
 
   INIT();
-  RdOff = _SEGGER_RTT.aDown[0].RdOff;
-  if (RdOff != _SEGGER_RTT.aDown[0].WrOff) {
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  RdOff = pRing->RdOff;
+  if (RdOff != pRing->WrOff) {
     r = 1;
   } else {
     r = 0;
@@ -1467,7 +1523,7 @@ unsigned SEGGER_RTT_HasData(unsigned BufferIndex) {
   SEGGER_RTT_BUFFER_DOWN* pRing;
   unsigned                v;
 
-  pRing = &_SEGGER_RTT.aDown[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   v = pRing->WrOff;
   return v - pRing->RdOff;
 }
@@ -1488,7 +1544,7 @@ unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned                v;
 
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   v = pRing->RdOff;
   return pRing->WrOff - v;
 }
@@ -1507,6 +1563,7 @@ unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
 *    pBuffer      Pointer to a buffer to be used.
 *    BufferSize   Size of the buffer.
 *    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0 - O.K. Buffer Index
@@ -1514,23 +1571,26 @@ unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
 */
 int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
   int BufferIndex;
+  volatile SEGGER_RTT_CB* pRTTCB;
 
   INIT();
   SEGGER_RTT_LOCK();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   BufferIndex = 0;
   do {
-    if (_SEGGER_RTT.aDown[BufferIndex].pBuffer == NULL) {
+    if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) {
       break;
     }
     BufferIndex++;
-  } while (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers);
-  if (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers) {
-    _SEGGER_RTT.aDown[BufferIndex].sName        = sName;
-    _SEGGER_RTT.aDown[BufferIndex].pBuffer      = (char*)pBuffer;
-    _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize;
-    _SEGGER_RTT.aDown[BufferIndex].RdOff        = 0u;
-    _SEGGER_RTT.aDown[BufferIndex].WrOff        = 0u;
-    _SEGGER_RTT.aDown[BufferIndex].Flags        = Flags;
+  } while (BufferIndex < pRTTCB->MaxNumDownBuffers);
+  if (BufferIndex < pRTTCB->MaxNumDownBuffers) {
+    pRTTCB->aDown[BufferIndex].sName        = sName;
+    pRTTCB->aDown[BufferIndex].pBuffer      = (char*)pBuffer;
+    pRTTCB->aDown[BufferIndex].SizeOfBuffer = BufferSize;
+    pRTTCB->aDown[BufferIndex].RdOff        = 0u;
+    pRTTCB->aDown[BufferIndex].WrOff        = 0u;
+    pRTTCB->aDown[BufferIndex].Flags        = Flags;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
   } else {
     BufferIndex = -1;
   }
@@ -1552,6 +1612,7 @@ int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned Buffer
 *    pBuffer      Pointer to a buffer to be used.
 *    BufferSize   Size of the buffer.
 *    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0 - O.K. Buffer Index
@@ -1559,23 +1620,26 @@ int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned Buffer
 */
 int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
   int BufferIndex;
+  volatile SEGGER_RTT_CB* pRTTCB;
 
   INIT();
   SEGGER_RTT_LOCK();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   BufferIndex = 0;
   do {
-    if (_SEGGER_RTT.aUp[BufferIndex].pBuffer == NULL) {
+    if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) {
       break;
     }
     BufferIndex++;
-  } while (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers);
-  if (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers) {
-    _SEGGER_RTT.aUp[BufferIndex].sName        = sName;
-    _SEGGER_RTT.aUp[BufferIndex].pBuffer      = (char*)pBuffer;
-    _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize;
-    _SEGGER_RTT.aUp[BufferIndex].RdOff        = 0u;
-    _SEGGER_RTT.aUp[BufferIndex].WrOff        = 0u;
-    _SEGGER_RTT.aUp[BufferIndex].Flags        = Flags;
+  } while (BufferIndex < pRTTCB->MaxNumUpBuffers);
+  if (BufferIndex < pRTTCB->MaxNumUpBuffers) {
+    pRTTCB->aUp[BufferIndex].sName        = sName;
+    pRTTCB->aUp[BufferIndex].pBuffer      = (char*)pBuffer;
+    pRTTCB->aUp[BufferIndex].SizeOfBuffer = BufferSize;
+    pRTTCB->aUp[BufferIndex].RdOff        = 0u;
+    pRTTCB->aUp[BufferIndex].WrOff        = 0u;
+    pRTTCB->aUp[BufferIndex].Flags        = Flags;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
   } else {
     BufferIndex = -1;
   }
@@ -1598,6 +1662,7 @@ int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSi
 *    pBuffer      Pointer to a buffer to be used.
 *    BufferSize   Size of the buffer.
 *    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0 - O.K.
@@ -1610,18 +1675,22 @@ int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSi
 */
 int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_UP* pUp;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
     SEGGER_RTT_LOCK();
-    if (BufferIndex > 0u) {
-      _SEGGER_RTT.aUp[BufferIndex].sName        = sName;
-      _SEGGER_RTT.aUp[BufferIndex].pBuffer      = (char*)pBuffer;
-      _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize;
-      _SEGGER_RTT.aUp[BufferIndex].RdOff        = 0u;
-      _SEGGER_RTT.aUp[BufferIndex].WrOff        = 0u;
+    pUp = &pRTTCB->aUp[BufferIndex];
+    if (BufferIndex) {
+      pUp->sName        = sName;
+      pUp->pBuffer      = (char*)pBuffer;
+      pUp->SizeOfBuffer = BufferSize;
+      pUp->RdOff        = 0u;
+      pUp->WrOff        = 0u;
     }
-    _SEGGER_RTT.aUp[BufferIndex].Flags          = Flags;
+    pUp->Flags          = Flags;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1645,6 +1714,7 @@ int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBu
 *    pBuffer      Pointer to a buffer to be used.
 *    BufferSize   Size of the buffer.
 *    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0  O.K.
@@ -1657,18 +1727,23 @@ int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBu
 */
 int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_DOWN* pDown;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
     SEGGER_RTT_LOCK();
-    if (BufferIndex > 0u) {
-      _SEGGER_RTT.aDown[BufferIndex].sName        = sName;
-      _SEGGER_RTT.aDown[BufferIndex].pBuffer      = (char*)pBuffer;
-      _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize;
-      _SEGGER_RTT.aDown[BufferIndex].RdOff        = 0u;
-      _SEGGER_RTT.aDown[BufferIndex].WrOff        = 0u;
+    pDown = &pRTTCB->aDown[BufferIndex];
+    if (BufferIndex) {
+      pDown->sName        = sName;
+      pDown->pBuffer      = (char*)pBuffer;
+      pDown->SizeOfBuffer = BufferSize;
+      pDown->RdOff        = 0u;
+      pDown->WrOff        = 0u;
     }
-    _SEGGER_RTT.aDown[BufferIndex].Flags          = Flags;
+    pDown->Flags          = Flags;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1695,11 +1770,15 @@ int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* p
 */
 int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_UP* pUp;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
     SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aUp[BufferIndex].sName = sName;
+    pUp = &pRTTCB->aUp[BufferIndex];
+    pUp->sName = sName;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1726,11 +1805,15 @@ int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) {
 */
 int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_DOWN* pDown;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
     SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aDown[BufferIndex].sName = sName;
+    pDown = &pRTTCB->aDown[BufferIndex];
+    pDown->sName = sName;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1750,6 +1833,7 @@ int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) {
 *  Parameters
 *    BufferIndex  Index of the buffer.
 *    Flags        Flags to set for the buffer.
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0  O.K.
@@ -1757,11 +1841,15 @@ int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) {
 */
 int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_UP* pUp;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
     SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aUp[BufferIndex].Flags = Flags;
+    pUp = &pRTTCB->aUp[BufferIndex];
+    pUp->Flags = Flags;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1781,6 +1869,7 @@ int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) {
 *  Parameters
 *    BufferIndex  Index of the buffer to renamed.
 *    Flags        Flags to set for the buffer.
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0  O.K.
@@ -1788,11 +1877,15 @@ int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) {
 */
 int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_DOWN* pDown;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
     SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aDown[BufferIndex].Flags = Flags;
+    pDown = &pRTTCB->aDown[BufferIndex];
+    pDown->Flags = Flags;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1827,21 +1920,23 @@ void SEGGER_RTT_Init (void) {
 *  Return value
 *    >= 0  O.K.
 *     < 0  Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id)
+*
+*  Notes
+*    (1) Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed
 */
 int SEGGER_RTT_SetTerminal (unsigned char TerminalId) {
   unsigned char         ac[2];
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned Avail;
   int r;
-  //
+
   INIT();
-  //
   r = 0;
   ac[0] = 0xFFu;
   if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels
     ac[1] = _aTerminalId[TerminalId];
-    pRing = &_SEGGER_RTT.aUp[0];    // Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed
-    SEGGER_RTT_LOCK();    // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing
+    pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+    SEGGER_RTT_LOCK();                     // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing
     if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) {
       _ActiveTerminal = TerminalId;
       _WriteBlocking(pRing, (const char*)ac, 2u);
@@ -1892,7 +1987,7 @@ int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) {
     //
     // Get "to-host" ring buffer.
     //
-    pRing = &_SEGGER_RTT.aUp[0];
+    pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
     //
     // Need to be able to change terminal, write data, change back.
     // Compute the fixed and variable sizes.
@@ -1966,8 +2061,11 @@ int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) {
 *  Return value
 *    Number of bytes that are free in the selected up buffer.
 */
-unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex){
-  return _GetAvailWriteSpace(&_SEGGER_RTT.aUp[BufferIndex]);
+unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex) {
+  SEGGER_RTT_BUFFER_UP* pRing;
+
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  return _GetAvailWriteSpace(pRing);
 }
 
 
@@ -1988,16 +2086,18 @@ unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) {
   unsigned RdOff;
   unsigned WrOff;
   unsigned r;
+  volatile SEGGER_RTT_CB* pRTTCB;
   //
   // Avoid warnings regarding volatile access order.  It's not a problem
   // in this case, but dampen compiler enthusiasm.
   //
-  RdOff = _SEGGER_RTT.aUp[BufferIndex].RdOff;
-  WrOff = _SEGGER_RTT.aUp[BufferIndex].WrOff;
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  RdOff = pRTTCB->aUp[BufferIndex].RdOff;
+  WrOff = pRTTCB->aUp[BufferIndex].WrOff;
   if (RdOff <= WrOff) {
     r = WrOff - RdOff;
   } else {
-    r = _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff);
+    r = pRTTCB->aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff);
   }
   return r;
 }
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
index 3c04df55f..87f2841a5 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
@@ -44,18 +44,16 @@
 ---------------------------END-OF-HEADER------------------------------
 File    : SEGGER_RTT.h
 Purpose : Implementation of SEGGER real-time transfer which allows
-          real-time communication on targets which support debugger 
+          real-time communication on targets which support debugger
           memory accesses while the CPU is running.
-Revision: $Rev: 17697 $
+Revision: $Rev: 25842 $
 ----------------------------------------------------------------------
 */
 
 #ifndef SEGGER_RTT_H
 #define SEGGER_RTT_H
 
-#include "SEGGER_RTT_Conf.h"
-
-
+#include "../Config/SEGGER_RTT_Conf.h"
 
 /*********************************************************************
 *
@@ -63,46 +61,180 @@ Revision: $Rev: 17697 $
 *
 **********************************************************************
 */
+
 #ifndef RTT_USE_ASM
-  #if (defined __SES_ARM)                       // SEGGER Embedded Studio
+  //
+  // Some cores support out-of-order memory accesses (reordering of memory accesses in the core)
+  // For such cores, we need to define a memory barrier to guarantee the order of certain accesses to the RTT ring buffers.
+  // Needed for:
+  //   Cortex-M7 (ARMv7-M)
+  //   Cortex-M23 (ARM-v8M)
+  //   Cortex-M33 (ARM-v8M)
+  //   Cortex-A/R (ARM-v7A/R)
+  //
+  // We do not explicitly check for "Embedded Studio" as the compiler in use determines what we support.
+  // You can use an external toolchain like IAR inside ES. So there is no point in checking for "Embedded Studio"
+  //
+  #if (defined __CROSSWORKS_ARM)                  // Rowley Crossworks
     #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __CROSSWORKS_ARM)              // Rowley Crossworks
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __GNUC__)                      // GCC
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __clang__)                     // Clang compiler
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __IASMARM__)                   // IAR assembler
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __ICCARM__)                    // IAR compiler
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #else
-    #define _CC_HAS_RTT_ASM_SUPPORT 0
-  #endif
-  #if (defined __ARM_ARCH_7M__)                 // Cortex-M3/4
-    #define _CORE_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __ARM_ARCH_7EM__)              // Cortex-M7
-    #define _CORE_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __ARM_ARCH_8M_MAIN__)          // Cortex-M33
-    #define _CORE_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __ARM7M__)                     // IAR Cortex-M3/4
-    #if (__CORE__ == __ARM7M__)
+    #if (defined __ARM_ARCH_7M__)                 // Cortex-M3
       #define _CORE_HAS_RTT_ASM_SUPPORT 1
+    #elif (defined __ARM_ARCH_7EM__)              // Cortex-M4/M7
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_BASE__)          // Cortex-M23
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_MAIN__)          // Cortex-M33
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined(__ARM_ARCH_8_1M_MAIN__))       // Cortex-M85
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
     #else
       #define _CORE_HAS_RTT_ASM_SUPPORT 0
     #endif
-  #elif (defined __ARM7EM__)                    // IAR Cortex-M7
-    #if (__CORE__ == __ARM7EM__)
+  #elif (defined __ARMCC_VERSION)
+    //
+    // ARM compiler
+    // ARM compiler V6.0 and later is clang based.
+    // Our ASM part is compatible to clang.
+    //
+    #if (__ARMCC_VERSION >= 6000000)
+      #define _CC_HAS_RTT_ASM_SUPPORT 1
+    #else
+      #define _CC_HAS_RTT_ASM_SUPPORT 0
+    #endif
+    #if (defined __ARM_ARCH_6M__)                 // Cortex-M0 / M1
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0         // No ASM support for this architecture
+    #elif (defined __ARM_ARCH_7M__)               // Cortex-M3
       #define _CORE_HAS_RTT_ASM_SUPPORT 1
+    #elif (defined __ARM_ARCH_7EM__)              // Cortex-M4/M7
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_BASE__)          // Cortex-M23
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_MAIN__)          // Cortex-M33
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8_1M_MAIN__)        // Cortex-M85
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__))  // Cortex-A/R 32-bit ARMv7-A/R
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
     #else
       #define _CORE_HAS_RTT_ASM_SUPPORT 0
     #endif
+  #elif ((defined __GNUC__) || (defined __clang__))
+    //
+    // GCC / Clang
+    //
+    #define _CC_HAS_RTT_ASM_SUPPORT 1
+    // ARM 7/9: __ARM_ARCH_5__ / __ARM_ARCH_5E__ / __ARM_ARCH_5T__ / __ARM_ARCH_5T__ / __ARM_ARCH_5TE__
+    #if (defined __ARM_ARCH_7M__)                 // Cortex-M3
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+    #elif (defined __ARM_ARCH_7EM__)              // Cortex-M4/M7
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1         // Only Cortex-M7 needs a DMB but we cannot distinguish M4 and M7 here...
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_BASE__)          // Cortex-M23
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_MAIN__)          // Cortex-M33
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8_1M_MAIN__)        // Cortex-M85
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__))  // Cortex-A/R 32-bit ARMv7-A/R
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #else
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+    #endif
+  #elif ((defined __IASMARM__) || (defined __ICCARM__))
+    //
+    // IAR assembler/compiler
+    //
+    #define _CC_HAS_RTT_ASM_SUPPORT 1
+    #if (__VER__ < 6300000)
+      #define VOLATILE
+    #else
+      #define VOLATILE volatile
+    #endif
+    #if (defined __ARM7M__)                            // Needed for old versions that do not know the define yet
+      #if (__CORE__ == __ARM7M__)                      // Cortex-M3
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #endif
+    #endif
+    #if (defined __ARM7EM__)
+      #if (__CORE__ == __ARM7EM__)                     // Cortex-M4/M7
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM8M_BASELINE__)
+      #if (__CORE__ == __ARM8M_BASELINE__)             // Cortex-M23
+        #define _CORE_HAS_RTT_ASM_SUPPORT 0
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM8M_MAINLINE__)
+      #if (__CORE__ == __ARM8M_MAINLINE__)             // Cortex-M33
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM8EM_MAINLINE__)
+      #if (__CORE__ == __ARM8EM_MAINLINE__)            // Cortex-???
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM7A__)
+      #if (__CORE__ == __ARM7A__)                      // Cortex-A 32-bit ARMv7-A
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM7R__)
+      #if (__CORE__ == __ARM7R__)                      // Cortex-R 32-bit ARMv7-R
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+// TBD: __ARM8A__ => Cortex-A 64-bit ARMv8-A
+// TBD: __ARM8R__ => Cortex-R 64-bit ARMv8-R
   #else
+    //
+    // Other compilers
+    //
+    #define _CC_HAS_RTT_ASM_SUPPORT   0
     #define _CORE_HAS_RTT_ASM_SUPPORT 0
   #endif
   //
   // If IDE and core support the ASM version, enable ASM version by default
   //
+  #ifndef _CORE_HAS_RTT_ASM_SUPPORT
+    #define _CORE_HAS_RTT_ASM_SUPPORT 0              // Default for unknown cores
+  #endif
   #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT)
     #define RTT_USE_ASM                           (1)
   #else
@@ -110,9 +242,39 @@ Revision: $Rev: 17697 $
   #endif
 #endif
 
+#ifndef _CORE_NEEDS_DMB
+  #define _CORE_NEEDS_DMB 0
+#endif
+
+#ifndef RTT__DMB
+  #if _CORE_NEEDS_DMB
+    #error "Don't know how to place inline assembly for DMB"
+  #else
+    #define RTT__DMB()
+  #endif
+#endif
+
+#ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE
+  #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0)   // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here
+#endif
+
+#ifndef SEGGER_RTT_UNCACHED_OFF
+  #if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #else
+    #define SEGGER_RTT_UNCACHED_OFF (0)
+  #endif
+#endif
+#if RTT_USE_ASM
+  #if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+#endif
+
 #ifndef SEGGER_RTT_ASM  // defined when SEGGER_RTT.h is included from assembly file
 #include <stdlib.h>
 #include <stdarg.h>
+#include <stdint.h>
 
 /*********************************************************************
 *
@@ -121,6 +283,21 @@ Revision: $Rev: 17697 $
 **********************************************************************
 */
 
+//
+// Determine how much we must pad the control block to make it a multiple of a cache line in size
+// Assuming: U8 = 1B
+//           U16 = 2B
+//           U32 = 4B
+//           U8/U16/U32* = 4B
+//
+#if SEGGER_RTT_CPU_CACHE_LINE_SIZE    // Avoid division by zero in case we do not have any cache
+  #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE)
+#else
+  #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes)
+#endif
+#define SEGGER_RTT__CB_SIZE                              (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24))
+#define SEGGER_RTT__CB_PADDING                           (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE)
+
 /*********************************************************************
 *
 *       Types
@@ -138,7 +315,7 @@ typedef struct {
             unsigned SizeOfBuffer;  // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
             unsigned WrOff;         // Position of next item to be written by either target.
   volatile  unsigned RdOff;         // Position of next item to be read by host. Must be volatile since it may be modified by host.
-            unsigned Flags;         // Contains configuration flags
+            unsigned Flags;         // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 } SEGGER_RTT_BUFFER_UP;
 
 //
@@ -151,7 +328,7 @@ typedef struct {
             unsigned SizeOfBuffer;  // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
   volatile  unsigned WrOff;         // Position of next item to be written by host. Must be volatile since it may be modified by host.
             unsigned RdOff;         // Position of next item to be read by target (down-buffer).
-            unsigned Flags;         // Contains configuration flags
+            unsigned Flags;         // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 } SEGGER_RTT_BUFFER_DOWN;
 
 //
@@ -165,6 +342,9 @@ typedef struct {
   int                     MaxNumDownBuffers;                        // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2)
   SEGGER_RTT_BUFFER_UP    aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS];       // Up buffers, transferring information up from target via debug probe to host
   SEGGER_RTT_BUFFER_DOWN  aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS];   // Down buffers, transferring information down from host via debug probe to target
+#if SEGGER_RTT__CB_PADDING
+  unsigned char           aDummy[SEGGER_RTT__CB_PADDING];
+#endif
 } SEGGER_RTT_CB;
 
 /*********************************************************************
@@ -214,7 +394,7 @@ unsigned     SEGGER_RTT_GetBytesInBuffer        (unsigned BufferIndex);
 //
 // Function macro for performance optimization
 //
-#define      SEGGER_RTT_HASDATA(n)       (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff)
+#define      SEGGER_RTT_HASDATA(n)       (((SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)
 
 #if RTT_USE_ASM
   #define SEGGER_RTT_WriteSkipNoLock  SEGGER_RTT_ASM_WriteSkipNoLock
@@ -231,7 +411,7 @@ unsigned     SEGGER_RTT_ReadUpBufferNoLock      (unsigned BufferIndex, void* pDa
 unsigned     SEGGER_RTT_WriteDownBuffer         (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
 unsigned     SEGGER_RTT_WriteDownBufferNoLock   (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
 
-#define      SEGGER_RTT_HASDATA_UP(n)    (_SEGGER_RTT.aUp[n].WrOff - _SEGGER_RTT.aUp[n].RdOff)
+#define      SEGGER_RTT_HASDATA_UP(n)    (((SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)   // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
 
 /*********************************************************************
 *
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S b/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S
index 78cde4d75..85c79899e 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S
@@ -23,6 +23,7 @@ Additional information:
 *
 **********************************************************************
 */
+
 #define _CCIAR   0
 #define _CCCLANG 1
 
@@ -36,9 +37,9 @@ Additional information:
   #define _THUMB_CODE          .code 16
   #define _WORD                .word
   #define _SECTION(Sect, Type, AlignExp) .section Sect ##, "ax"
-  #define _ALIGN(Exp)          .align Exp 
+  #define _ALIGN(Exp)          .align Exp
   #define _PLACE_LITS          .ltorg
-  #define _DATA_SECT_START 
+  #define _DATA_SECT_START
   #define _C_STARTUP           _start
   #define _STACK_END           __stack_end__
   #define _RAMFUNC
@@ -58,7 +59,7 @@ Additional information:
   #define _THUMB_CODE          THUMB
   #define _WORD                DCD
   #define _SECTION(Sect, Type, AlignExp) SECTION Sect ## : ## Type ## :REORDER:NOROOT ## (AlignExp)
-  #define _ALIGN(Exp)          alignrom Exp 
+  #define _ALIGN(Exp)          alignrom Exp
   #define _PLACE_LITS
   #define _DATA_SECT_START     DATA
   #define _C_STARTUP           __iar_program_start
@@ -182,6 +183,9 @@ _LoopCopyStraight:                               // memcpy(pRing->pBuffer + WrOf
         SUBS     R2,R2,#+1
         BNE      _LoopCopyStraight
 _CSDone:
+#if _CORE_NEEDS_DMB                              // Do not slow down cores that do not need a DMB instruction here
+        DMB                                      // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
+#endif
         STR      R0,[R6, #+12]                   // pRing->WrOff = WrOff + NumBytes;
         MOVS     R0,#+1
         POP      {R4-R7}
@@ -214,6 +218,9 @@ _LoopCopyAfterWrapAround:                        // memcpy(pRing->pBuffer, pData
         SUBS     R2,R2,#+1
         BNE      _LoopCopyAfterWrapAround
 _No2ChunkNeeded:
+#if _CORE_NEEDS_DMB                              // Do not slow down cores that do not need a DMB instruction here
+        DMB                                      // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
+#endif
         STR      R4,[R6, #+12]                   // pRing->WrOff = NumBytes; => Must be written after copying data because J-Link may read control block asynchronously while writing into buffer
         MOVS     R0,#+1
         POP      {R4-R7}
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c
deleted file mode 100644
index da4a4b5f5..000000000
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* SEGGER strongly recommends to not make any changes                 *
-* to or modify the source code of this software in order to stay     *
-* compatible with the RTT protocol and J-Link.                       *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* o Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : SEGGER_RTT_Syscalls_GCC.c
-Purpose : Low-level functions for using printf() via RTT in GCC.
-          To use RTT for printf output, include this file in your 
-          application.
-Revision: $Rev: 17697 $
-----------------------------------------------------------------------
-*/
-#if (defined __GNUC__) && !(defined __SES_ARM) && !(defined __CROSSWORKS_ARM)
-
-#include <reent.h>  // required for _write_r
-#include "SEGGER_RTT.h"
-
-
-/*********************************************************************
-*
-*       Types
-*
-**********************************************************************
-*/
-//
-// If necessary define the _reent struct 
-// to match the one passed by the used standard library.
-//
-struct _reent;
-
-/*********************************************************************
-*
-*       Function prototypes
-*
-**********************************************************************
-*/
-int _write(int file, char *ptr, int len);
-int _write_r(struct _reent *r, int file, const void *ptr, int len);
-
-/*********************************************************************
-*
-*       Global functions
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-*       _write()
-*
-* Function description
-*   Low-level write function.
-*   libc subroutines will use this system routine for output to all files,
-*   including stdout.
-*   Write data via RTT.
-*/
-int _write(int file, char *ptr, int len) {
-  (void) file;  /* Not used, avoid warning */
-  SEGGER_RTT_Write(0, ptr, len);
-  return len;
-}
-
-/*********************************************************************
-*
-*       _write_r()
-*
-* Function description
-*   Low-level reentrant write function.
-*   libc subroutines will use this system routine for output to all files,
-*   including stdout.
-*   Write data via RTT.
-*/
-int _write_r(struct _reent *r, int file, const void *ptr, int len) {
-  (void) file;  /* Not used, avoid warning */
-  (void) r;     /* Not used, avoid warning */
-  SEGGER_RTT_Write(0, ptr, len);
-  return len;
-}
-
-#endif
-/****** End Of File *************************************************/
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c
deleted file mode 100644
index 4c76752b3..000000000
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* SEGGER strongly recommends to not make any changes                 *
-* to or modify the source code of this software in order to stay     *
-* compatible with the RTT protocol and J-Link.                       *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* o Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : SEGGER_RTT_Syscalls_IAR.c
-Purpose : Low-level functions for using printf() via RTT in IAR.
-          To use RTT for printf output, include this file in your
-          application and set the Library Configuration to Normal.
-Revision: $Rev: 17697 $
-----------------------------------------------------------------------
-*/
-#ifdef __IAR_SYSTEMS_ICC__
-
-//
-// Since IAR EWARM V8 and EWRX V4, yfuns.h is considered as deprecated and LowLevelIOInterface.h
-// shall be used instead. To not break any compatibility with older compiler versions, we have a
-// version check in here.
-//
-#if ((defined __ICCARM__) && (__VER__ >= 8000000)) || ((defined __ICCRX__)  && (__VER__ >= 400))
-  #include <LowLevelIOInterface.h>
-#else
-  #include <yfuns.h>
-#endif
-
-#include "SEGGER_RTT.h"
-#pragma module_name = "?__write"
-
-/*********************************************************************
-*
-*       Function prototypes
-*
-**********************************************************************
-*/
-size_t __write(int handle, const unsigned char * buffer, size_t size);
-
-/*********************************************************************
-*
-*       Global functions
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       __write()
-*
-* Function description
-*   Low-level write function.
-*   Standard library subroutines will use this system routine
-*   for output to all files, including stdout.
-*   Write data via RTT.
-*/
-size_t __write(int handle, const unsigned char * buffer, size_t size) {
-  (void) handle;  /* Not used, avoid warning */
-  SEGGER_RTT_Write(0, (const char*)buffer, size);
-  return size;
-}
-
-/*********************************************************************
-*
-*       __write_buffered()
-*
-* Function description
-*   Low-level write function.
-*   Standard library subroutines will use this system routine
-*   for output to all files, including stdout.
-*   Write data via RTT.
-*/
-size_t __write_buffered(int handle, const unsigned char * buffer, size_t size) {
-  (void) handle;  /* Not used, avoid warning */
-  SEGGER_RTT_Write(0, (const char*)buffer, size);
-  return size;
-}
-
-#endif
-/****** End Of File *************************************************/
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c
deleted file mode 100644
index f7f5aed48..000000000
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* SEGGER strongly recommends to not make any changes                 *
-* to or modify the source code of this software in order to stay     *
-* compatible with the RTT protocol and J-Link.                       *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* o Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : RTT_Syscalls_KEIL.c
-Purpose : Retargeting module for KEIL MDK-CM3.
-          Low-level functions for using printf() via RTT
-Revision: $Rev: 17697 $
-----------------------------------------------------------------------
-*/
-#ifdef __CC_ARM
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <rt_sys.h>
-#include <rt_misc.h>
-
-#include "SEGGER_RTT.h"
-/*********************************************************************
-*
-*       #pragmas
-*
-**********************************************************************
-*/
-#pragma import(__use_no_semihosting)
-
-#ifdef _MICROLIB
-  #pragma import(__use_full_stdio)
-#endif
-
-/*********************************************************************
-*
-*       Defines non-configurable
-*
-**********************************************************************
-*/
-
-/* Standard IO device handles - arbitrary, but any real file system handles must be
-   less than 0x8000. */
-#define STDIN             0x8001    // Standard Input Stream
-#define STDOUT            0x8002    // Standard Output Stream
-#define STDERR            0x8003    // Standard Error Stream
-
-/*********************************************************************
-*
-*       Public const
-*
-**********************************************************************
-*/
-#if __ARMCC_VERSION < 5000000
-//const char __stdin_name[]  = "STDIN";
-const char __stdout_name[] = "STDOUT";
-const char __stderr_name[] = "STDERR";
-#endif
-
-/*********************************************************************
-*
-*       Public code
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-*       _ttywrch
-*
-*  Function description:
-*    Outputs a character to the console
-*
-*  Parameters:
-*    c    - character to output
-*  
-*/
-void _ttywrch(int c) {
-  fputc(c, stdout); // stdout
-  fflush(stdout);
-}
-
-/*********************************************************************
-*
-*       _sys_open
-*
-*  Function description:
-*    Opens the device/file in order to do read/write operations
-*
-*  Parameters:
-*    sName        - sName of the device/file to open
-*    OpenMode    - This parameter is currently ignored
-*  
-*  Return value:
-*    != 0     - Handle to the object to open, otherwise 
-*    == 0     -"device" is not handled by this module
-*
-*/
-FILEHANDLE _sys_open(const char * sName, int OpenMode) {
-  (void)OpenMode;
-  // Register standard Input Output devices.
-  if (strcmp(sName, __stdout_name) == 0) {
-    return (STDOUT);
-  } else if (strcmp(sName, __stderr_name) == 0) {
-    return (STDERR);
-  } else
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_close
-*
-*  Function description:
-*    Closes the handle to the open device/file
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*  
-*  Return value:
-*    0     - device/file closed
-*
-*/
-int _sys_close(FILEHANDLE hFile) {
-  (void)hFile;
-  return 0;  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_write
-*
-*  Function description:
-*    Writes the data to an open handle.
-*    Currently this function only outputs data to the console
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*    pBuffer  - Pointer to the data that shall be written
-*    NumBytes      - Number of bytes to write
-*    Mode     - The Mode that shall be used
-*  
-*  Return value:
-*    Number of bytes *not* written to the file/device
-*
-*/
-int _sys_write(FILEHANDLE hFile, const unsigned char * pBuffer, unsigned NumBytes, int Mode) {
-  int r = 0;
-
-  (void)Mode;
-  if (hFile == STDOUT) {
-    SEGGER_RTT_Write(0, (const char*)pBuffer, NumBytes);
-		return 0;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       _sys_read
-*
-*  Function description:
-*    Reads data from an open handle.
-*    Currently this modules does nothing.
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*    pBuffer  - Pointer to buffer to store the read data
-*    NumBytes      - Number of bytes to read
-*    Mode     - The Mode that shall be used
-*  
-*  Return value:
-*    Number of bytes read from the file/device
-*
-*/
-int _sys_read(FILEHANDLE hFile, unsigned char * pBuffer, unsigned NumBytes, int Mode) {
-  (void)hFile;
-  (void)pBuffer;
-  (void)NumBytes;
-  (void)Mode;
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_istty
-*
-*  Function description:
-*    This function shall return whether the opened file 
-*    is a console device or not.
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*  
-*  Return value:
-*    1       - Device is     a console
-*    0       - Device is not a console
-*
-*/
-int _sys_istty(FILEHANDLE hFile) {
-  if (hFile > 0x8000) {
-    return (1);
-  }
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_seek
-*
-*  Function description:
-*    Seeks via the file to a specific position
-*
-*  Parameters:
-*    hFile  - Handle to a file opened via _sys_open
-*    Pos    - 
-*  
-*  Return value:
-*    int       - 
-*
-*/
-int _sys_seek(FILEHANDLE hFile, long Pos) {
-  (void)hFile;
-  (void)Pos;
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_ensure
-*
-*  Function description:
-*    
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*  
-*  Return value:
-*    int       - 
-*
-*/
-int _sys_ensure(FILEHANDLE hFile) {
-  (void)hFile;
-  return (-1);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_flen
-*
-*  Function description:
-*    Returns the length of the opened file handle
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*  
-*  Return value:
-*    Length of the file
-*
-*/
-long _sys_flen(FILEHANDLE hFile) {
-  (void)hFile;
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_tmpnam
-*
-*  Function description:
-*    This function converts the file number fileno for a temporary 
-*    file to a unique filename, for example, tmp0001.
-*
-*  Parameters:
-*    pBuffer    - Pointer to a buffer to store the name
-*    FileNum    - file number to convert
-*    MaxLen     - Size of the buffer
-*  
-*  Return value:
-*     1 - Error
-*     0 - Success  
-*
-*/
-int _sys_tmpnam(char * pBuffer, int FileNum, unsigned MaxLen) {
-  (void)pBuffer;
-  (void)FileNum;
-  (void)MaxLen;
-  return (1);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_command_string
-*
-*  Function description:
-*    This function shall execute a system command.
-*
-*  Parameters:
-*    cmd    - Pointer to the command string
-*    len    - Length of the string
-*  
-*  Return value:
-*    == NULL - Command was not successfully executed
-*    == sCmd - Command was passed successfully
-*
-*/
-char * _sys_command_string(char * cmd, int len) {
-  (void)len;
-  return cmd;  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_exit
-*
-*  Function description:
-*    This function is called when the application returns from main
-*
-*  Parameters:
-*    ReturnCode    - Return code from the main function
-*  
-*
-*/
-void _sys_exit(int ReturnCode) {
-  (void)ReturnCode;
-  while (1);  // Not implemented
-}
-
-#if __ARMCC_VERSION >= 5000000
-/*********************************************************************
-*
-*       stdout_putchar
-*
-*  Function description:
-*    Put a character to the stdout
-*
-*  Parameters:
-*    ch    - Character to output
-*  
-*
-*/
-int stdout_putchar(int ch) {
-  (void)ch;
-  return ch;  // Not implemented
-}
-#endif
-
-#endif
-/*************************** End of file ****************************/
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c
deleted file mode 100644
index 5ce8457e1..000000000
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* SEGGER strongly recommends to not make any changes                 *
-* to or modify the source code of this software in order to stay     *
-* compatible with the RTT protocol and J-Link.                       *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* o Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : SEGGER_RTT_Syscalls_SES.c
-Purpose : Reimplementation of printf, puts and __getchar using RTT
-          in SEGGER Embedded Studio.
-          To use RTT for printf output, include this file in your
-          application.
-Revision: $Rev: 18539 $
-----------------------------------------------------------------------
-*/
-#if (defined __SES_ARM) || (defined __SES_RISCV) || (defined __CROSSWORKS_ARM)
-
-#include "SEGGER_RTT.h"
-#include <stdarg.h>
-#include <stdio.h>
-#include "limits.h"
-#include "__libc.h"
-#include "__vfprintf.h"
-
-/*********************************************************************
-*
-*       Defines, configurable
-*
-**********************************************************************
-*/
-//
-// Select string formatting implementation.
-//
-// RTT printf formatting
-//  - Configurable stack usage. (SEGGER_RTT_PRINTF_BUFFER_SIZE in SEGGER_RTT_Conf.h)
-//  - No maximum string length.
-//  - Limited conversion specifiers and flags. (See SEGGER_RTT_printf.c)
-// Standard library printf formatting
-//  - Configurable formatting capabilities.
-//  - Full conversion specifier and flag support.
-//  - Maximum string length has to be known or (slightly) slower character-wise output.
-//
-// #define PRINTF_USE_SEGGER_RTT_FORMATTING    0 // Use standard library formatting
-// #define PRINTF_USE_SEGGER_RTT_FORMATTING    1 // Use RTT formatting
-//
-#ifndef   PRINTF_USE_SEGGER_RTT_FORMATTING
-  #define PRINTF_USE_SEGGER_RTT_FORMATTING    0
-#endif
-//
-// If using standard library formatting,
-// select maximum output string buffer size or character-wise output.
-//
-// #define PRINTF_BUFFER_SIZE                  0 // Use character-wise output
-// #define PRINTF_BUFFER_SIZE                128 // Default maximum string length
-//
-#ifndef   PRINTF_BUFFER_SIZE
-  #define PRINTF_BUFFER_SIZE                128
-#endif
-
-#if PRINTF_USE_SEGGER_RTT_FORMATTING  // Use SEGGER RTT formatting implementation
-/*********************************************************************
-*
-*       Function prototypes
-*
-**********************************************************************
-*/
-int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList);
-
-/*********************************************************************
-*
-*       Global functions, printf
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       printf()
-*
-*  Function description
-*    print a formatted string using RTT and SEGGER RTT formatting.
-*/
-int printf(const char *fmt,...) {
-  int     n;
-  va_list args;
-
-  va_start (args, fmt);
-  n = SEGGER_RTT_vprintf(0, fmt, &args);
-  va_end(args);
-  return n;
-}
-
-#elif PRINTF_BUFFER_SIZE == 0 // Use standard library formatting with character-wise output
-
-/*********************************************************************
-*
-*       Static functions
-*
-**********************************************************************
-*/
-static int _putchar(int x, __printf_tag_ptr ctx) {
-  (void)ctx;
-  SEGGER_RTT_Write(0, (char *)&x, 1);
-  return x;
-}
-
-/*********************************************************************
-*
-*       Global functions, printf
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       printf()
-*
-*  Function description
-*    print a formatted string character-wise, using RTT and standard
-*    library formatting.
-*/
-int printf(const char *fmt, ...) {
-  int         n;
-  va_list     args;
-  __printf_t  iod;
-
-  va_start(args, fmt);
-  iod.string    = 0;
-  iod.maxchars  = INT_MAX;
-  iod.output_fn = _putchar;
-  SEGGER_RTT_LOCK();
-  n = __vfprintf(&iod, fmt, args);
-  SEGGER_RTT_UNLOCK();
-  va_end(args);
-  return n;
-}
-
-#else // Use standard library formatting with static buffer
-
-/*********************************************************************
-*
-*       Global functions, printf
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       printf()
-*
-*  Function description
-*    print a formatted string using RTT and standard library formatting.
-*/
-int printf(const char *fmt,...) {
-  int     n;
-  char    aBuffer[PRINTF_BUFFER_SIZE];
-  va_list args;
-
-  va_start (args, fmt);
-  n = vsnprintf(aBuffer, sizeof(aBuffer), fmt, args);
-  if (n > (int)sizeof(aBuffer)) {
-    SEGGER_RTT_Write(0, aBuffer, sizeof(aBuffer));
-  } else if (n > 0) {
-    SEGGER_RTT_Write(0, aBuffer, n);
-  }
-  va_end(args);
-  return n;
-}
-#endif
-
-/*********************************************************************
-*
-*       Global functions
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       puts()
-*
-*  Function description
-*    print a string using RTT.
-*/
-int puts(const char *s) {
-  return SEGGER_RTT_WriteString(0, s);
-}
-
-/*********************************************************************
-*
-*       __putchar()
-*
-*  Function description
-*    Write one character via RTT.
-*/
-int __putchar(int x, __printf_tag_ptr ctx) {
-  (void)ctx;
-  SEGGER_RTT_Write(0, (char *)&x, 1);
-  return x;
-}
-
-/*********************************************************************
-*
-*       __getchar()
-*
-*  Function description
-*    Wait for and get a character via RTT.
-*/
-int __getchar() {
-  return SEGGER_RTT_WaitKey();
-}
-
-#endif
-/****** End Of File *************************************************/
diff --git a/lib/embedded-cli/embedded_cli.h b/lib/embedded-cli/embedded_cli.h
index 33354cd84..91c96f3a1 100644
--- a/lib/embedded-cli/embedded_cli.h
+++ b/lib/embedded-cli/embedded_cli.h
@@ -743,7 +743,7 @@ EmbeddedCli *embeddedCliNew(EmbeddedCliConfig *config) {
 
     bool allocated = false;
     if (config->cliBuffer == NULL) {
-        config->cliBuffer = (CLI_UINT *) malloc(totalSize); // malloc guarantees alignment.
+//        config->cliBuffer = (CLI_UINT *) malloc(totalSize); // malloc guarantees alignment.
         if (config->cliBuffer == NULL)
             return NULL;
         allocated = true;
@@ -887,7 +887,7 @@ void embeddedCliFree(EmbeddedCli *cli) {
     PREPARE_IMPL(cli);
     if (IS_FLAG_SET(impl->flags, CLI_FLAG_ALLOCATED)) {
         // allocation is done in single call to malloc, so need only single free
-        free(cli);
+//        free(cli);
     }
 }
 
diff --git a/lib/fatfs/source/00history.txt b/lib/fatfs/source/00history.txt
index 7a153a229..f7898cbd9 100644
--- a/lib/fatfs/source/00history.txt
+++ b/lib/fatfs/source/00history.txt
@@ -366,4 +366,3 @@ R0.15 (November 6, 2022)
   Fixed f_mkfs() creates broken exFAT volume when the size of volume is >= 2^32 sectors.
   Fixed string functions cannot write the unicode characters not in BMP when FF_LFN_UNICODE == 2 (UTF-8).
   Fixed a compatibility issue in identification of GPT header.
-
diff --git a/lib/fatfs/source/00readme.txt b/lib/fatfs/source/00readme.txt
index 3de3aeaa2..48c02a42d 100644
--- a/lib/fatfs/source/00readme.txt
+++ b/lib/fatfs/source/00readme.txt
@@ -18,4 +18,3 @@ FILES
   module is only a generic file system layer and it does not depend on any specific
   storage device. You need to provide a low level disk I/O module written to
   control the storage device that attached to the target system.
-
diff --git a/lib/fatfs/source/diskio.c b/lib/fatfs/source/diskio.c
index 179e387a2..3cb423db3 100644
--- a/lib/fatfs/source/diskio.c
+++ b/lib/fatfs/source/diskio.c
@@ -226,4 +226,3 @@ DRESULT disk_ioctl (
 
 	return RES_PARERR;
 }
-
diff --git a/lib/fatfs/source/ff.c b/lib/fatfs/source/ff.c
index 6d412fa0e..05ca02f0a 100644
--- a/lib/fatfs/source/ff.c
+++ b/lib/fatfs/source/ff.c
@@ -7081,4 +7081,3 @@ FRESULT f_setcp (
 	return FR_OK;
 }
 #endif	/* FF_CODE_PAGE == 0 */
-
diff --git a/lib/fatfs/source/ffsystem.c b/lib/fatfs/source/ffsystem.c
index d5c5134bf..bc0047dce 100644
--- a/lib/fatfs/source/ffsystem.c
+++ b/lib/fatfs/source/ffsystem.c
@@ -205,4 +205,3 @@ void ff_mutex_give (
 }
 
 #endif	/* FF_FS_REENTRANT */
-
diff --git a/lib/lwip b/lib/lwip
deleted file mode 160000
index 159e31b68..000000000
--- a/lib/lwip
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 159e31b689577dbf69cf0683bbaffbd71fa5ee10
diff --git a/lib/networking/dhserver.c b/lib/networking/dhserver.c
index def431f75..2f14f7a09 100644
--- a/lib/networking/dhserver.c
+++ b/lib/networking/dhserver.c
@@ -2,17 +2,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@@ -86,7 +86,7 @@ typedef struct
     uint8_t  dp_giaddr[4];    /* gateway IP address */
     uint8_t  dp_chaddr[16];   /* client hardware address */
     uint8_t  dp_legacy[192];
-    uint8_t  dp_magic[4];     
+    uint8_t  dp_magic[4];
     uint8_t  dp_options[275]; /* options area */
 } DHCP_TYPE;
 
@@ -242,7 +242,11 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 	memcpy(&dhcp_data, p->payload, n);
 
 	ptr = find_dhcp_option(dhcp_data.dp_options, sizeof(dhcp_data.dp_options), DHCP_MESSAGETYPE);
-	if (ptr == NULL) return;
+	if (ptr == NULL)
+	{
+		pbuf_free(p);
+		return;
+	}
 
 	switch (ptr[2])
 	{
@@ -263,7 +267,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 				DHCP_OFFER,
 				config->domain,
 				config->dns,
-				entry->lease, 
+				entry->lease,
 				*netif_ip4_addr(netif),
 				config->router,
 				*netif_ip4_netmask(netif));
@@ -305,7 +309,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 				DHCP_ACK,
 				config->domain,
 				config->dns,
-				entry->lease, 
+				entry->lease,
 				*netif_ip4_addr(netif),
 				config->router,
 				*netif_ip4_netmask(netif));
diff --git a/lib/networking/dhserver.h b/lib/networking/dhserver.h
index 2a0b15854..6a443b220 100644
--- a/lib/networking/dhserver.h
+++ b/lib/networking/dhserver.h
@@ -2,17 +2,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@@ -56,7 +56,13 @@ typedef struct dhcp_config
 	dhcp_entry_t *entries;
 } dhcp_config_t;
 
-err_t dhserv_init(const dhcp_config_t *config);
+#ifdef __cplusplus
+extern "C" {
+#endif
+err_t dhserv_init(const dhcp_config_t *c);
 void dhserv_free(void);
+#ifdef __cplusplus
+}
+#endif
 
 #endif /* DHSERVER_H */
diff --git a/lib/networking/dnserver.c b/lib/networking/dnserver.c
index e4e7c3492..25bbf4875 100644
--- a/lib/networking/dnserver.c
+++ b/lib/networking/dnserver.c
@@ -2,17 +2,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@@ -93,11 +93,11 @@ static uint16_t get_uint16(const uint8_t *pnt)
 static int parse_next_query(void *data, int size, dns_query_t *query)
 {
 	int len;
-	int lables;
+	int labels;
 	uint8_t *ptr;
 
 	len = 0;
-	lables = 0;
+	labels = 0;
 	ptr = (uint8_t *)data;
 
 	while (true)
@@ -107,7 +107,7 @@ static int parse_next_query(void *data, int size, dns_query_t *query)
 		lable_len = *ptr++;
 		size--;
 		if (lable_len == 0) break;
-		if (lables > 0)
+		if (labels > 0)
 		{
 			if (len == DNS_MAX_HOST_NAME_LEN) return -2;
 			query->name[len++] = '.';
@@ -118,7 +118,7 @@ static int parse_next_query(void *data, int size, dns_query_t *query)
 		len += lable_len;
 		ptr += lable_len;
 		size -= lable_len;
-		lables++;
+		labels++;
 	}
 
 	if (size < 4) return -1;
@@ -165,7 +165,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 	answer->ttl = htonl(32);
 	answer->len = htons(4);
 	answer->addr = host_addr.addr;
-	
+
 	udp_sendto(upcb, out, addr, port);
 	pbuf_free(out);
 
@@ -192,7 +192,7 @@ err_t dnserv_init(const ip_addr_t *bind, uint16_t port, dns_query_proc_t qp)
 	return ERR_OK;
 }
 
-void dnserv_free()
+void dnserv_free(void)
 {
 	if (pcb == NULL) return;
 	udp_remove(pcb);
diff --git a/lib/networking/dnserver.h b/lib/networking/dnserver.h
index a062e3aa7..a7a7f9acb 100644
--- a/lib/networking/dnserver.h
+++ b/lib/networking/dnserver.h
@@ -2,17 +2,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@@ -41,7 +41,13 @@
 
 typedef bool (*dns_query_proc_t)(const char *name, ip4_addr_t *addr);
 
+#ifdef __cplusplus
+extern "C" {
+#endif
 err_t dnserv_init(const ip_addr_t *bind, uint16_t port, dns_query_proc_t query_proc);
 void  dnserv_free(void);
+#ifdef __cplusplus
+}
+#endif
 
 #endif
diff --git a/lib/networking/ndis.h b/lib/networking/ndis.h
index 1c737574c..29b07749c 100644
--- a/lib/networking/ndis.h
+++ b/lib/networking/ndis.h
@@ -16,14 +16,14 @@
  */
 
 /*
- * ndis.h 
- * 
+ * ndis.h
+ *
  * Modified by Colin O'Flynn <coflynn@newae.com>
  * ntddndis.h modified by Benedikt Spranger <b.spranger@pengutronix.de>
- * 
- * Thanks to the cygwin development team, 
- * espacially to Casper S. Hornstrup <chorns@users.sourceforge.net>
- * 
+ *
+ * Thanks to the cygwin development team,
+ * especially to Casper S. Hornstrup <chorns@users.sourceforge.net>
+ *
  * THIS SOFTWARE IS NOT COPYRIGHTED
  *
  * This source code is offered for use in the public domain. You may
diff --git a/lib/networking/rndis_protocol.h b/lib/networking/rndis_protocol.h
index b45860eeb..3d07d6fa3 100644
--- a/lib/networking/rndis_protocol.h
+++ b/lib/networking/rndis_protocol.h
@@ -39,7 +39,7 @@
 #ifndef _RNDIS_H
 #define _RNDIS_H
 
-/** 
+/**
   \addtogroup RNDIS
   @{
   */
@@ -112,7 +112,7 @@ typedef struct{
 	rndis_MinorVersion_t	MinorVersion;
 	rndis_MaxTransferSize_t	MaxTransferSize;
 	} rndis_initialize_msg_t;
-	
+
 /* Response: */
 typedef struct{
 	rndis_MessageType_t		MessageType;
@@ -129,7 +129,7 @@ typedef struct{
 	rndis_AfListOffset_t	AfListOffset;
 	rndis_AfListSize_t		AfListSize;
 	} rndis_initialize_cmplt_t;
-	
+
 
 /*** Remote NDIS Halt Message ***/
 typedef struct{
@@ -137,7 +137,7 @@ typedef struct{
 	rndis_MessageLength_t	MessageLength;
 	rndis_RequestId_t		RequestId;
 	} rndis_halt_msg_t;
-	
+
 typedef uint32_t rndis_Oid_t;
 typedef uint32_t rndis_InformationBufferLength_t;
 typedef uint32_t rndis_InformationBufferOffset_t;
@@ -153,7 +153,7 @@ typedef struct{
 	rndis_InformationBufferOffset_t	InformationBufferOffset;
 	rndis_DeviceVcHandle_t			DeviceVcHandle;
 	}  rndis_query_msg_t;
-	
+
 /* Response: */
 
 typedef struct{
@@ -164,7 +164,7 @@ typedef struct{
 	rndis_InformationBufferLength_t	InformationBufferLength;
 	rndis_InformationBufferOffset_t	InformationBufferOffset;
 	} rndis_query_cmplt_t;
-	
+
 /*** Remote NDIS Set Message ***/
 typedef struct{
 	rndis_MessageType_t		MessageType;
@@ -175,7 +175,7 @@ typedef struct{
 	rndis_InformationBufferOffset_t	InformationBufferOffset;
 	rndis_DeviceVcHandle_t			DeviceVcHandle;
 	} rndis_set_msg_t;
-	
+
 /* Response */
 typedef struct{
 	rndis_MessageType_t		MessageType;
@@ -199,9 +199,9 @@ typedef struct{
 	rndis_ParameterNameLength_t		ParameterNameLength;
 	rndis_ParameterType_t			ParameterType;
 	rndis_ParameterValueOffset_t	ParameterValueOffset;
-	rndis_ParameterValueLength_t	ParameterValueLength;	
+	rndis_ParameterValueLength_t	ParameterValueLength;
 	}rndis_config_parameter_t;
-	
+
 typedef uint32_t rndis_Reserved_t;
 
 /*** Remote NDIS Soft Reset Message ***/
@@ -210,7 +210,7 @@ typedef struct{
 	rndis_MessageLength_t	MessageLength;
 	rndis_Reserved_t		Reserved;
 	} rndis_reset_msg_t;
-	
+
 typedef uint32_t rndis_AddressingReset_t;
 
 /* Response: */
@@ -220,7 +220,7 @@ typedef struct{
 	rndis_Status_t			Status;
 	rndis_AddressingReset_t	AddressingReset;
 	}  rndis_reset_cmplt_t;
-	
+
 /*** Remote NDIS Indicate Status Message ***/
 typedef struct{
 	rndis_MessageType_t		MessageType;
@@ -229,7 +229,7 @@ typedef struct{
 	rndis_Status_t			StatusBufferLength;
 	rndis_Status_t			StatusBufferOffset;
 	}  rndis_indicate_status_t;
-	
+
 typedef uint32_t rndis_DiagStatus_t;
 typedef uint32_t rndis_ErrorOffset_t;
 
@@ -237,14 +237,14 @@ typedef struct {
 	rndis_DiagStatus_t		DiagStatus;
 	rndis_ErrorOffset_t		ErrorOffset;
 	}rndis_diagnostic_info_t;
-	
+
 /*** Remote NDIS Keepalive Message */
 typedef struct{
 	rndis_MessageType_t		MessageType;
 	rndis_MessageLength_t	MessageLength;
 	rndis_RequestId_t		RequestId;
 	}rndis_keepalive_msg_t;
-	
+
 /* Response: */
 typedef struct{
 	rndis_MessageType_t		MessageType;
diff --git a/lib/networking/rndis_reports.c b/lib/networking/rndis_reports.c
index ee611c883..451d5405b 100644
--- a/lib/networking/rndis_reports.c
+++ b/lib/networking/rndis_reports.c
@@ -7,17 +7,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@@ -43,9 +43,7 @@ static usb_eth_stat_t usb_eth_stat = { 0, 0, 0, 0 };
 static uint32_t oid_packet_filter = 0x0000000;
 static rndis_state_t rndis_state;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t ndis_report[8] = { 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
-
-static const uint32_t OIDSupportedList[] = 
+static const uint32_t OIDSupportedList[] =
 {
   OID_GEN_SUPPORTED_LIST,
   OID_GEN_HARDWARE_STATUS,
@@ -76,8 +74,8 @@ static const uint32_t OIDSupportedList[] =
 
 static void *encapsulated_buffer;
 
-static void rndis_report(void)
-{
+static void rndis_report(void) {
+  uint8_t ndis_report[8] = { 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
   netd_report(ndis_report, sizeof(ndis_report));
 }
 
@@ -203,8 +201,8 @@ static void rndis_handle_set_msg(void)
       {
         rndis_packetFilter(oid_packet_filter);
         rndis_state = rndis_data_initialized;
-      } 
-      else 
+      }
+      else
       {
         rndis_state = rndis_initialized;
       }
@@ -220,7 +218,7 @@ static void rndis_handle_set_msg(void)
     case OID_802_3_MULTICAST_LIST:
       break;
 
-    /* Power Managment: fails for now */
+    /* Power Management: fails for now */
     case OID_PNP_ADD_WAKE_UP_PATTERN:
     case OID_PNP_REMOVE_WAKE_UP_PATTERN:
     case OID_PNP_ENABLE_WAKE_UP:
@@ -266,7 +264,7 @@ void rndis_class_set_handler(uint8_t *data, int size)
     case REMOTE_NDIS_QUERY_MSG:
       rndis_query();
       break;
-      
+
     case REMOTE_NDIS_SET_MSG:
       rndis_handle_set_msg();
       break;
diff --git a/lib/rt-thread/SConscript b/lib/rt-thread/SConscript
new file mode 100644
index 000000000..34399fd45
--- /dev/null
+++ b/lib/rt-thread/SConscript
@@ -0,0 +1,56 @@
+import rtconfig
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Split("""
+../../src/tusb.c
+../../src/common/tusb_fifo.c
+./tusb_rt_thread_port.c
+""")
+path = [cwd, cwd + "/../../src"]
+
+LOCAL_CFLAGS = ''
+
+# for device stack
+if GetDepend(["PKG_TINYUSB_DEVICE_ENABLE"]):
+    src += ["../../src/device/usbd.c",
+            "../../src/device/usbd_control.c"]
+    # BSP
+    if GetDepend(["SOC_FAMILY_STM32"]):
+        src += ["../../src/portable/synopsys/dwc2/dcd_dwc2.c",
+                "../../src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c"]
+
+    if GetDepend(["SOC_NRF52840"]):
+        src += ["../../src/portable/nordic/nrf5x/dcd_nrf5x.c"]
+
+    if GetDepend(["SOC_FAMILY_RENESAS"]):
+        src += ["../../src/portable/renesas/rusb2/dcd_rusb2.c",
+                "../../src/portable/renesas/rusb2/rusb2_common.c"]
+
+    # Device class
+    if GetDepend(["PKG_TINYUSB_DEVICE_UVC"]):
+        src += ["../../src/class/video/video_device.c"]
+    if GetDepend(["PKG_TINYUSB_DEVICE_CDC"]):
+        src += ["../../src/class/cdc/cdc_device.c"]
+    if GetDepend(["PKG_TINYUSB_DEVICE_MSC"]):
+        src += ["../../src/class/msc/msc_device.c", "port/msc_device_port.c"]
+    if GetDepend(["PKG_TINYUSB_DEVICE_HID"]):
+        src += ["../../src/class/hid/hid_device.c"]
+
+# for host stack
+if GetDepend(["PKG_TINYUSB_HOST_ENABLE"]):
+    src += ["../../src/host/usbh.c", "../../src/host/hub.c"]
+
+    if GetDepend(["SOC_FAMILY_RENESAS"]):
+        src += ["../../src/portable/renesas/rusb2/hcd_rusb2.c",
+                "../../src/portable/renesas/rusb2/rusb2_common.c"]
+
+
+if rtconfig.PLATFORM == 'gcc' or rtconfig.PLATFORM == 'armclang': # GCC or Keil AC6
+    LOCAL_CFLAGS += ' -std=c99'
+elif rtconfig.PLATFORM == 'armcc': # Keil AC5
+    LOCAL_CFLAGS += ' --c99 --gnu'
+
+group = DefineGroup('TinyUSB', src, depend = ['PKG_USING_TINYUSB'], CPPPATH = path, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')
diff --git a/lib/rt-thread/port/msc_device_port.c b/lib/rt-thread/port/msc_device_port.c
new file mode 100644
index 000000000..c7e8c508e
--- /dev/null
+++ b/lib/rt-thread/port/msc_device_port.c
@@ -0,0 +1,171 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#ifdef __RTTHREAD__
+#include <tusb.h>
+#include <stdint.h>
+
+#include <board.h>
+#include <rtdevice.h>
+
+static bool ejected = false;
+static rt_device_t flash_device;
+static struct rt_device_blk_geometry blk_geom;
+
+#ifdef __CC_ARM
+uint16_t __builtin_bswap16(uint16_t x)
+{
+    return (x << 8) | (x >> 8);
+}
+#endif
+
+void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4])
+{
+    (void) lun;
+
+    const char vid[] = PKG_TINYUSB_DEVICE_MSC_VID;
+    const char pid[] = PKG_TINYUSB_DEVICE_MSC_PID;
+    const char rev[] = PKG_TINYUSB_DEVICE_MSC_REV;
+
+    memcpy(vendor_id, vid, strlen(vid));
+    memcpy(product_id, pid, strlen(pid));
+    memcpy(product_rev, rev, strlen(rev));
+}
+
+bool tud_msc_test_unit_ready_cb(uint8_t lun)
+{
+    (void) lun;
+
+    if (ejected)
+    {
+        tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3a, 0x00);
+        return false;
+    }
+
+    if (flash_device == NULL)
+    {
+        flash_device = rt_device_find(PKG_TINYUSB_DEVICE_MSC_NAME);
+    }
+    if (flash_device != NULL)
+    {
+        static uint8_t open_flg = 0;
+        if (!open_flg)
+        {
+            open_flg = 1;
+            rt_device_open(flash_device, 0);
+        }
+
+        rt_device_control(flash_device, RT_DEVICE_CTRL_BLK_GETGEOME, &blk_geom);
+        return true;
+    }
+
+    return false;
+}
+
+void tud_msc_capacity_cb(uint8_t lun, uint32_t *block_count, uint16_t *block_size)
+{
+    (void) lun;
+
+    *block_count = blk_geom.sector_count;
+    *block_size  = blk_geom.bytes_per_sector;
+}
+
+bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject)
+{
+    (void) lun;
+    (void) power_condition;
+
+    if (load_eject)
+    {
+        if (start)
+        {
+            ejected = false;
+        } else {
+            // unload disk storage
+            ejected = true;
+        }
+    }
+
+    return true;
+}
+
+int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize)
+{
+    (void) lun;
+    (void) offset;
+    (void) bufsize;
+
+    return (int32_t) rt_device_read(flash_device, (rt_off_t) lba, buffer, 1) * blk_geom.bytes_per_sector;
+}
+
+int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize)
+{
+    (void) lun;
+    (void) offset;
+    (void) bufsize;
+
+    return (int32_t) rt_device_write(flash_device, (rt_off_t) lba, buffer, 1) * blk_geom.bytes_per_sector;
+}
+
+int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, uint16_t bufsize)
+{
+    void const *response = NULL;
+    uint16_t resplen = 0;
+
+    // most scsi handled is input
+    bool in_xfer = true;
+
+    switch (scsi_cmd[0])
+    {
+        case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
+            // Host is about to read/write etc ... better not to disconnect disk
+            resplen = 0;
+            break;
+
+        default:
+            // Set Sense = Invalid Command Operation
+            tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+
+            // negative means error -> tinyusb could stall and/or response with failed status
+            resplen = -1;
+            break;
+    }
+
+    // return resplen must not larger than bufsize
+    if (resplen > bufsize) resplen = bufsize;
+
+    if (response && (resplen > 0))
+    {
+        if (in_xfer)
+        {
+            memcpy(buffer, response, resplen);
+        } else {
+            // SCSI output
+        }
+    }
+
+    return resplen;
+}
+#endif /*__RTTHREAD__*/
diff --git a/lib/rt-thread/tusb_config.h b/lib/rt-thread/tusb_config.h
new file mode 100644
index 000000000..11dc21983
--- /dev/null
+++ b/lib/rt-thread/tusb_config.h
@@ -0,0 +1,218 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __RTTHREAD__
+#include <rtconfig.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+#if   defined(SOC_SERIES_STM32F0)
+#define CFG_TUSB_MCU    OPT_MCU_STM32F0
+#elif defined(SOC_SERIES_STM32F1)
+#define CFG_TUSB_MCU    OPT_MCU_STM32F1
+#elif defined(SOC_SERIES_STM32F2)
+#define CFG_TUSB_MCU    OPT_MCU_STM32F2
+#elif defined(SOC_SERIES_STM32F3)
+#define CFG_TUSB_MCU    OPT_MCU_STM32F3
+#elif defined(SOC_SERIES_STM32F4)
+#define CFG_TUSB_MCU    OPT_MCU_STM32F4
+#elif defined(SOC_SERIES_STM32F7)
+#define CFG_TUSB_MCU    OPT_MCU_STM32F7
+#elif defined(SOC_SERIES_STM32H7)
+#define CFG_TUSB_MCU    OPT_MCU_STM32H7
+#elif defined(SOC_SERIES_STM32L0)
+#define CFG_TUSB_MCU    OPT_MCU_STM32L0
+#elif defined(SOC_SERIES_STM32L1)
+#define CFG_TUSB_MCU    OPT_MCU_STM32L1
+#elif defined(SOC_SERIES_STM32L4)
+#define CFG_TUSB_MCU    OPT_MCU_STM32L4
+#elif defined(SOC_NRF52840)
+#define CFG_TUSB_MCU    OPT_MCU_NRF5X
+#elif defined(SOC_HPM6000)
+#define CFG_TUSB_MCU    OPT_MCU_HPM
+#elif defined(SOC_RP2040)
+#define CFG_TUSB_MCU    OPT_MCU_RP2040
+#elif defined(SOC_FAMILY_RENESAS)
+#define CFG_TUSB_MCU    OPT_MCU_RAXXX
+#else
+#error "Not support for current MCU"
+#endif
+
+#define CFG_TUSB_OS OPT_OS_RTTHREAD
+
+//--------------------------------------------------------------------
+// DEBUG CONFIGURATION
+//--------------------------------------------------------------------
+#ifdef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG_PRINTF rt_kprintf
+#endif /* CFG_TUSB_DEBUG */
+
+#ifndef BOARD_DEVICE_RHPORT_NUM
+#define BOARD_DEVICE_RHPORT_NUM     PKG_TINYUSB_RHPORT_NUM
+#endif
+
+#ifndef BOARD_DEVICE_RHPORT_SPEED
+#define BOARD_DEVICE_RHPORT_SPEED   PKG_TINYUSB_DEVICE_PORT_SPEED
+#endif
+
+#if   BOARD_DEVICE_RHPORT_NUM == 0
+#define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#elif BOARD_DEVICE_RHPORT_NUM == 1
+#define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#else
+  #error "Incorrect RHPort configuration"
+#endif
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION        rt_section(PKG_TINYUSB_MEM_SECTION)
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          rt_align(PKG_TINYUSB_MEM_ALIGN)
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+#if defined(PKG_TINYUSB_DEVICE_ENABLE)
+  #define CFG_TUD_ENABLED             (1)
+#else
+  #define CFG_TUD_ENABLED             (0)
+#endif
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE        PKG_TINYUSB_EDPT0_SIZE
+#endif
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE        PKG_TINYUSB_DEVICE_CDC_RX_BUFSIZE
+#define CFG_TUD_CDC_TX_BUFSIZE        PKG_TINYUSB_DEVICE_CDC_TX_BUFSIZE
+
+#define CFG_TUD_MSC_EP_BUFSIZE        PKG_TINYUSB_DEVICE_MSC_EP_BUFSIZE
+
+#define CFG_TUD_HID_EP_BUFSIZE        PKG_TINYUSB_DEVICE_HID_EP_BUFSIZE
+
+#ifndef PKG_TINYUSB_DEVICE_CDC_STRING
+#define PKG_TINYUSB_DEVICE_CDC_STRING ""
+#endif
+
+#ifndef PKG_TINYUSB_DEVICE_MSC_STRING
+#define PKG_TINYUSB_DEVICE_MSC_STRING ""
+#endif
+
+#ifndef PKG_TINYUSB_DEVICE_HID_STRING
+#define PKG_TINYUSB_DEVICE_HID_STRING ""
+#endif
+
+//--------------------------------------------------------------------
+// HOST CONFIGURATION
+//--------------------------------------------------------------------
+#if defined(PKG_TINYUSB_HOST_ENABLE)
+  #define CFG_TUH_ENABLED             (1)
+#else
+  #define CFG_TUH_ENABLED             (0)
+#endif
+
+#if (PKG_TINYUSB_HOST_PORT == 0) && defined(PKG_TINYUSB_HOST_ENABLE)
+#undef CFG_TUSB_RHPORT0_MODE
+#define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_HOST | PKG_TINYUSB_HOST_PORT_SPEED)
+#endif
+
+#if (PKG_TINYUSB_HOST_PORT == 1) && defined(PKG_TINYUSB_HOST_ENABLE)
+#undef CFG_TUSB_RHPORT1_MODE
+#define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_HOST | PKG_TINYUSB_HOST_PORT_SPEED)
+#endif
+
+#define BOARD_TUH_RHPORT            PKG_TINYUSB_HOST_PORT // FULL SPEED
+#define BOARD_TUH_MAX_SPEED         PKG_TINYUSB_HOST_PORT_SPEED
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED           BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB                 2 // number of supported hubs
+#define CFG_TUH_CDC                 0 // CDC ACM
+#define CFG_TUH_CDC_FTDI            0 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CP210X          0 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CH34X           0 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_HID                 0 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_MSC                 0
+//#define CFG_TUH_VENDOR              3
+
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
+
+//------------- HID -------------//
+#define CFG_TUH_HID_EPIN_BUFSIZE    64
+#define CFG_TUH_HID_EPOUT_BUFSIZE   64
+
+//------------- CDC -------------//
+
+// Set Line Control state on enumeration/mounted:
+// DTR ( bit 0), RTS (bit 1)
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+
+// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
+// bit rate = 115200, 1 stop bit, no parity, 8 bit data width
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__RTTHREAD__*/
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/lib/rt-thread/tusb_rt_thread_port.c b/lib/rt-thread/tusb_rt_thread_port.c
new file mode 100644
index 000000000..7e04d2453
--- /dev/null
+++ b/lib/rt-thread/tusb_rt_thread_port.c
@@ -0,0 +1,86 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#ifdef __RTTHREAD__
+#include <rtthread.h>
+
+#define  DBG_TAG  "TinyUSB"
+#define  DBG_LVL  DBG_INFO
+#include <rtdbg.h>
+#include <tusb.h>
+
+#ifndef RT_USING_HEAP
+/* if there is not enable heap, we should use static thread and stack. */
+static rt_uint8_t tusb_stack[PKG_TINYUSB_STACK_SIZE];
+static struct rt_thread tusb_thread;
+#endif /* RT_USING_HEAP */
+
+extern int tusb_board_init(void);
+
+static void tusb_thread_entry(void *parameter)
+{
+    (void) parameter;
+    while (1)
+    {
+#if CFG_TUH_ENABLED
+        tuh_task();
+#endif
+#if CFG_TUD_ENABLED
+        tud_task();
+#endif
+    }
+}
+
+static int init_tinyusb(void)
+{
+    rt_thread_t tid;
+
+    tusb_board_init();
+    tusb_init();
+
+#ifdef RT_USING_HEAP
+    tid = rt_thread_create("tusb", tusb_thread_entry, RT_NULL,
+                           PKG_TINYUSB_STACK_SIZE,
+                           PKG_TINYUSB_THREAD_PRIORITY, 10);
+    if (tid == RT_NULL)
+#else
+    rt_err_t result;
+
+    tid = &tusb_thread;
+    result = rt_thread_init(tid, "tusb", tusb_thread_entry, RT_NULL,
+                            tusb_stack, sizeof(tusb_stack), 4, 10);
+    if (result != RT_EOK)
+#endif /* RT_USING_HEAP */
+    {
+        LOG_E("Fail to create TinyUSB thread");
+        return -1;
+    }
+
+    rt_thread_startup(tid);
+
+    return 0;
+}
+INIT_APP_EXPORT(init_tinyusb);
+#endif /*__RTTHREAD__*/
diff --git a/lib/sct_neopixel b/lib/sct_neopixel
deleted file mode 160000
index e73e04ca6..000000000
--- a/lib/sct_neopixel
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit e73e04ca63495672d955f9268e003cffe168fcd8
diff --git a/library.json b/library.json
new file mode 100644
index 000000000..f1bfd6387
--- /dev/null
+++ b/library.json
@@ -0,0 +1,23 @@
+{
+    "name": "TinyUSB",
+    "version": "0.18.0",
+    "description": "TinyUSB is an open-source cross-platform USB Host/Device stack for embedded system, designed to be memory-safe with no dynamic allocation and thread-safe with all interrupt events are deferred then handled in the non-ISR task function.",
+    "keywords": "usb, host, device",
+    "repository":
+    {
+      "type": "git",
+      "url": "https://github.com/hathach/tinyusb.git"
+    },
+    "authors":
+    [
+      {
+        "name": "Ha Thach",
+        "email": "thach@tinyusb.org",
+        "maintainer": true
+      }
+    ],
+    "license": "MIT",
+    "homepage": "https://www.tinyusb.org/",
+    "frameworks": "*",
+    "platforms": "*"
+}
diff --git a/pkg.yml b/pkg.yml
index 331445024..841307847 100644
--- a/pkg.yml
+++ b/pkg.yml
@@ -1,5 +1,5 @@
 pkg.name: tinyusb
-pkg.description: A silly USB stack for embedded
+pkg.description: An open source cross-platform USB stack for embedded system
 pkg.author: "Ha Thach <thach@tinyusb.org>"
 pkg.homepage: "https://github.com/hathach/tinyusb"
 pkg.keywords:
diff --git a/repository.yml b/repository.yml
index dc341a3c1..31c9eddc5 100644
--- a/repository.yml
+++ b/repository.yml
@@ -12,7 +12,9 @@ repo.versions:
     "0.12.0": "0.12.0"
     "0.13.0": "0.13.0"
     "0.14.0": "0.14.0"
-
-    "0-dev": "0.0.0"        # master
-    "0-latest": "0.14.0"    # latest stable release
-
+    "0.15.0": "0.15.0"
+    "0.16.0": "0.16.0"
+    "0.17.0": "0.17.0"
+    "0.18.0": "0.18.0"
+    "0-latest": "0.18.0"
+    "0-dev": "0.0.0"
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
new file mode 100644
index 000000000..7b3ab4d42
--- /dev/null
+++ b/src/CMakeLists.txt
@@ -0,0 +1,42 @@
+# TODO more docs and example on how to use this file
+# TINYUSB_TARGET_PREFIX and TINYUSB_TARGET_SUFFIX can be used to change the name of the target
+
+cmake_minimum_required(VERSION 3.20)
+
+# Add tinyusb to a existing target
+function(tinyusb_target_add TARGET)
+  target_sources(${TARGET} PRIVATE
+    # common
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c
+    # device
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c
+    # host
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/host/usbh.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/host/hub.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_host.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_host.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_host.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_host.c
+    # typec
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/typec/usbc.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    # TODO for net driver, should be removed/changed
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../lib/networking
+    )
+endfunction()
diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h
index 6f9c1a6b5..2f97c0f23 100644
--- a/src/class/audio/audio.h
+++ b/src/class/audio/audio.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -489,7 +489,7 @@ typedef enum
   AUDIO_DATA_FORMAT_TYPE_I_IEEE_FLOAT     = (uint32_t) (1 << 2),
   AUDIO_DATA_FORMAT_TYPE_I_ALAW           = (uint32_t) (1 << 3),
   AUDIO_DATA_FORMAT_TYPE_I_MULAW          = (uint32_t) (1 << 4),
-  AUDIO_DATA_FORMAT_TYPE_I_RAW_DATA       = 0x80000000,
+  AUDIO_DATA_FORMAT_TYPE_I_RAW_DATA       = 0x80000000u,
 } audio_data_format_type_I_t;
 
 /// All remaining definitions are taken from the descriptor descriptions in the UAC2 main specification
@@ -640,7 +640,7 @@ typedef enum
   AUDIO_CHANNEL_CONFIG_BOTTOM_CENTER              = 0x01000000,
   AUDIO_CHANNEL_CONFIG_BACK_LEFT_OF_CENTER        = 0x02000000,
   AUDIO_CHANNEL_CONFIG_BACK_RIGHT_OF_CENTER       = 0x04000000,
-  AUDIO_CHANNEL_CONFIG_RAW_DATA                   = 0x80000000,
+  AUDIO_CHANNEL_CONFIG_RAW_DATA                   = 0x80000000u,
 } audio_channel_config_t;
 
 /// AUDIO Channel Cluster Descriptor (4.1)
@@ -721,11 +721,13 @@ typedef struct TU_ATTR_PACKED
   uint8_t bLength            ; ///< Size of this descriptor, in bytes: 17.
   uint8_t bDescriptorType    ; ///< Descriptor Type. Value: TUSB_DESC_CS_INTERFACE.
   uint8_t bDescriptorSubType ; ///< Descriptor SubType. Value: AUDIO_CS_AC_INTERFACE_INPUT_TERMINAL.
+  uint8_t bTerminalID        ; ///< Constant uniquely identifying the Terminal within the audio function. This value is used in all requests to address this terminal.
   uint16_t wTerminalType     ; ///< Constant characterizing the type of Terminal. See: audio_terminal_type_t for USB streaming and audio_terminal_input_type_t for other input types.
   uint8_t bAssocTerminal     ; ///< ID of the Output Terminal to which this Input Terminal is associated.
   uint8_t bCSourceID         ; ///< ID of the Clock Entity to which this Input Terminal is connected.
   uint8_t bNrChannels        ; ///< Number of logical output channels in the Terminal’s output audio channel cluster.
   uint32_t bmChannelConfig   ; ///< Describes the spatial location of the logical channels. See:audio_channel_config_t.
+  uint8_t iChannelNames      ; ///< Index of a string descriptor, describing the name of the first logical channel.
   uint16_t bmControls        ; ///< See: audio_terminal_input_control_pos_t.
   uint8_t iTerminal          ; ///< Index of a string descriptor, describing the Input Terminal.
 } audio_desc_input_terminal_t;
@@ -822,10 +824,10 @@ typedef struct TU_ATTR_PACKED
             uint8_t type      :  2; ///< Request type tusb_request_type_t.
             uint8_t direction :  1; ///< Direction type. tusb_dir_t
         } bmRequestType_bit;
-        
+
         uint8_t bmRequestType;
     };
-    
+
     uint8_t bRequest;  ///< Request type audio_cs_req_t
     uint8_t bChannelNumber;
     uint8_t bControlSelector;
@@ -922,6 +924,31 @@ typedef struct TU_ATTR_PACKED {
     } subrange[numSubRanges];                   \
 }
 
+// 6.1 Interrupt Data Message Format
+typedef struct TU_ATTR_PACKED
+{
+  uint8_t bInfo;
+  uint8_t bAttribute;
+  union
+  {
+    uint16_t wValue;
+    struct
+    {
+      uint8_t wValue_cn_or_mcn;
+      uint8_t wValue_cs;
+    };
+  };
+  union
+  {
+    uint16_t wIndex;
+    struct
+    {
+      uint8_t wIndex_ep_or_int;
+      uint8_t wIndex_entity_id;
+    };
+  };
+} audio_interrupt_data_t;
+
 /** @} */
 
 #ifdef __cplusplus
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 698fba566..8a130b7e2 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1,7 +1,8 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Reinhard Panhuber, Jerzy Kasenberg
+ * Copyright (c) 2023 HiFiPhile
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -65,414 +66,589 @@
 //--------------------------------------------------------------------+
 
 // Use ring buffer if it's available, some MCUs need extra RAM requirements
+// For DWC2 enable ring buffer will disable DMA (if available)
 #ifndef TUD_AUDIO_PREFER_RING_BUFFER
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT
-#define TUD_AUDIO_PREFER_RING_BUFFER 0
-#else
-#define TUD_AUDIO_PREFER_RING_BUFFER 1
-#endif
+  #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX || \
+      defined(TUP_USBIP_DWC2)
+    #define TUD_AUDIO_PREFER_RING_BUFFER 0
+  #else
+    #define TUD_AUDIO_PREFER_RING_BUFFER 1
+  #endif
 #endif
 
 // Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer
 // is available or driver is would need to be changed dramatically
 
-// Only STM32 synopsys and dcd_transdimension use non-linear buffer for now
-// Synopsys detection copied from dcd_synopsys.c (refactor later on)
-#if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
-    defined (STM32F107xB) || defined (STM32F107xC)
-#define STM32F1_SYNOPSYS
-#endif
-
-#if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
-    defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
-    defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define STM32L4_SYNOPSYS
-#endif
-
-#if (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \
-    CFG_TUSB_MCU == OPT_MCU_STM32F2                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32F4                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32F7                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32H7                               || \
-    (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) || \
-    CFG_TUSB_MCU == OPT_MCU_RX63X                                 || \
-    CFG_TUSB_MCU == OPT_MCU_RX65X                                 || \
-    CFG_TUSB_MCU == OPT_MCU_RX72N                                 || \
-    CFG_TUSB_MCU == OPT_MCU_GD32VF103                             || \
-    CFG_TUSB_MCU == OPT_MCU_LPC18XX                               || \
-    CFG_TUSB_MCU == OPT_MCU_LPC43XX                               || \
-    CFG_TUSB_MCU == OPT_MCU_MIMXRT                                || \
+// Only STM32 and dcd_transdimension use non-linear buffer for now
+// dwc2 except esp32sx (since it may use dcd_esp32sx)
+// Ring buffer is incompatible with dcache, since neither address nor size is aligned to cache line
+#if (defined(TUP_USBIP_DWC2) && !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)) || \
+    defined(TUP_USBIP_FSDEV) ||                                                     \
+    CFG_TUSB_MCU == OPT_MCU_RX63X ||                                                \
+    CFG_TUSB_MCU == OPT_MCU_RX65X ||                                                \
+    CFG_TUSB_MCU == OPT_MCU_RX72N ||                                                \
+    CFG_TUSB_MCU == OPT_MCU_LPC18XX ||                                              \
+    CFG_TUSB_MCU == OPT_MCU_LPC43XX ||                                              \
+    CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX ||                                           \
     CFG_TUSB_MCU == OPT_MCU_MSP432E4
-#if TUD_AUDIO_PREFER_RING_BUFFER
-#define  USE_LINEAR_BUFFER     0
+  #if TUD_AUDIO_PREFER_RING_BUFFER && !CFG_TUD_MEM_DCACHE_ENABLE
+    #define USE_LINEAR_BUFFER 0
+  #else
+    #define USE_LINEAR_BUFFER 1
+  #endif
 #else
-#define  USE_LINEAR_BUFFER     1
-#endif
-#else
-#define  USE_LINEAR_BUFFER     1
+  #define USE_LINEAR_BUFFER 1
 #endif
 
 // Declaration of buffers
 
 // Check for maximum supported numbers
 #if CFG_TUD_AUDIO > 3
-#error Maximum number of audio functions restricted to three!
+  #error Maximum number of audio functions restricted to three!
+#endif
+
+// Put swap buffer in USB section only if necessary
+#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING
+  #define IN_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
+#else
+  #define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
+#endif
+#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING
+  #define OUT_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
+#else
+  #define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
 #endif
 
 // EP IN software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
-#if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_in_ff_mutex_wr_1;                                                             // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_in_ff_mutex_wr_2;                                                             // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_in_ff_mutex_wr_3;                                                             // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
-#endif // CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
+tu_static IN_SW_BUF_MEM_ATTR struct {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
+  TUD_EPBUF_DEF(buf_1, CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ);
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
+  TUD_EPBUF_DEF(buf_2, CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ);
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
+  TUD_EPBUF_DEF(buf_3, CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ);
+  #endif
+} ep_in_sw_buf;
+
+  #if CFG_FIFO_MUTEX
+    #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
+    tu_static osal_mutex_def_t ep_in_ff_mutex_wr_1;
+    #endif
+    #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
+    tu_static osal_mutex_def_t ep_in_ff_mutex_wr_2;
+    #endif
+    #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
+    tu_static osal_mutex_def_t ep_in_ff_mutex_wr_3;
+    #endif
+  #endif
+#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
 
 // Linear buffer TX in case:
 // - target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING)
-#if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
-#endif
-#endif // CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
+tu_static CFG_TUD_MEM_SECTION struct {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
+  TUD_EPBUF_DEF(buf_1, CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX);
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
+  TUD_EPBUF_DEF(buf_2, CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX);
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
+  TUD_EPBUF_DEF(buf_3, CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX);
+  #endif
+} lin_buf_in;
+#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // EP OUT software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
-#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_out_ff_mutex_rd_1;                                                            // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_out_ff_mutex_rd_2;                                                            // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_out_ff_mutex_rd_3;                                                            // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
-#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
+tu_static OUT_SW_BUF_MEM_ATTR struct {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
+  TUD_EPBUF_DEF(buf_1, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ);
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
+  TUD_EPBUF_DEF(buf_2, CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ);
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
+  TUD_EPBUF_DEF(buf_3, CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ);
+  #endif
+} ep_out_sw_buf;
+
+  #if CFG_FIFO_MUTEX
+    #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
+    tu_static osal_mutex_def_t ep_out_ff_mutex_rd_1;
+    #endif
+    #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
+    tu_static osal_mutex_def_t ep_out_ff_mutex_rd_2;
+    #endif
+    #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
+    tu_static osal_mutex_def_t ep_out_ff_mutex_rd_3;
+    #endif
+  #endif
+#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
 
 // Linear buffer RX in case:
 // - target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
-#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
-#endif
-#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
+tu_static CFG_TUD_MEM_SECTION struct {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
+  TUD_EPBUF_DEF(buf_1, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX);
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
+  TUD_EPBUF_DEF(buf_2, CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX);
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
+  TUD_EPBUF_DEF(buf_3, CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX);
+  #endif
+} lin_buf_out;
+#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // Control buffers
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
+tu_static uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
+
 #if CFG_TUD_AUDIO > 1
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
+tu_static uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
 #endif
+
 #if CFG_TUD_AUDIO > 2
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
+tu_static uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
 #endif
 
 // Active alternate setting of interfaces
-uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
+tu_static uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
+
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_N_AS_INT > 0
-uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
+tu_static uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
 #endif
+
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_N_AS_INT > 0
-uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
+tu_static uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 #endif
 
 // Software encoding/decoding support FIFOs
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
-#if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
-tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
-tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
-tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif
+  #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
+    tu_static TU_ATTR_ALIGNED(4) uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
+    tu_static tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    tu_static osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];// No need for read mutex as only USB driver reads from FIFO
+    #endif
+  #endif
+
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
+    tu_static TU_ATTR_ALIGNED(4) uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
+    tu_static tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    tu_static osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];// No need for read mutex as only USB driver reads from FIFO
+    #endif
+  #endif
+
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
+    tu_static TU_ATTR_ALIGNED(4) uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
+    tu_static tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    tu_static osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];// No need for read mutex as only USB driver reads from FIFO
+    #endif
+  #endif
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
-#if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
-tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
-tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
-tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
+  #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
+    tu_static TU_ATTR_ALIGNED(4) uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
+    tu_static tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    tu_static osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];// No need for write mutex as only USB driver writes into FIFO
+    #endif
+  #endif
+
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
+    tu_static TU_ATTR_ALIGNED(4) uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
+    tu_static tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    tu_static osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];// No need for write mutex as only USB driver writes into FIFO
+    #endif
+  #endif
+
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
+    tu_static TU_ATTR_ALIGNED(4) uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
+    tu_static tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    tu_static osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];// No need for write mutex as only USB driver writes into FIFO
+    #endif
+  #endif
 #endif
+
+// Aligned buffer for feedback EP
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+tu_static CFG_TUD_MEM_SECTION struct {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
+  TUD_EPBUF_TYPE_DEF(uint32_t, buf_1);
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
+  TUD_EPBUF_TYPE_DEF(uint32_t, buf_2);
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
+  TUD_EPBUF_TYPE_DEF(uint32_t, buf_3);
+  #endif
+} fb_ep_buf;
 #endif
+
+// Aligned buffer for interrupt EP
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+tu_static CFG_TUD_MEM_SECTION struct {
+  TUD_EPBUF_DEF(buf, CFG_TUD_AUDIO_INTERRUPT_EP_SZ);
+} int_ep_buf[CFG_TUD_AUDIO];
 #endif
 
 typedef struct
 {
   uint8_t rhport;
-  uint8_t const * p_desc;       // Pointer pointing to Standard AC Interface Descriptor(4.7.1) - Audio Control descriptor defining audio function
+  uint8_t const *p_desc;// Pointer pointing to Standard AC Interface Descriptor(4.7.1) - Audio Control descriptor defining audio function
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
-  uint8_t ep_in;                // TX audio data EP.
-  uint16_t ep_in_sz;            // Current size of TX EP
-  uint8_t ep_in_as_intf_num;    // Corresponding Standard AS Interface Descriptor (4.9.1) belonging to output terminal to which this EP belongs - 0 is invalid (this fits to UAC2 specification since AS interfaces can not have interface number equal to zero)
+  uint8_t ep_in;            // TX audio data EP.
+  uint16_t ep_in_sz;        // Current size of TX EP
+  uint8_t ep_in_as_intf_num;// Corresponding Standard AS Interface Descriptor (4.9.1) belonging to output terminal to which this EP belongs - 0 is invalid (this fits to UAC2 specification since AS interfaces can not have interface number equal to zero)
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-  uint8_t ep_out;               // Incoming (into uC) audio data EP.
-  uint16_t ep_out_sz;           // Current size of RX EP
-  uint8_t ep_out_as_intf_num;   // Corresponding Standard AS Interface Descriptor (4.9.1) belonging to input terminal to which this EP belongs - 0 is invalid (this fits to UAC2 specification since AS interfaces can not have interface number equal to zero)
+  uint8_t ep_out;            // Incoming (into uC) audio data EP.
+  uint16_t ep_out_sz;        // Current size of RX EP
+  uint8_t ep_out_as_intf_num;// Corresponding Standard AS Interface Descriptor (4.9.1) belonging to input terminal to which this EP belongs - 0 is invalid (this fits to UAC2 specification since AS interfaces can not have interface number equal to zero)
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-  uint8_t ep_fb;                // Feedback EP.
-#endif
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  uint8_t ep_fb;// Feedback EP.
+  #endif
 
 #endif
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  uint8_t ep_int_ctr;           // Audio control interrupt EP.
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+  uint8_t ep_int;// Audio control interrupt EP.
 #endif
 
-  /*------------- From this point, data is not cleared by bus reset -------------*/
+  bool mounted;// Device opened
 
-  uint16_t desc_length;         // Length of audio function descriptor
-
-  // Buffer for control requests
-  uint8_t * ctrl_buf;
-  uint8_t ctrl_buf_sz;
-
-  // Current active alternate settings
-  uint8_t * alt_setting;   // We need to save the current alternate setting this way, because it is possible that there are AS interfaces which do not have an EP!
-
-  // EP Transfer buffers and FIFOs
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
-#if !CFG_TUD_AUDIO_ENABLE_DECODING
-  tu_fifo_t ep_out_ff;
-#endif
+  uint16_t desc_length;// Length of audio function descriptor
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
   struct {
-    uint32_t value;       // Feedback value for asynchronous mode (in 16.16 format).
-    uint32_t min_value;   // min value according to UAC2 FMT-2.0 section 2.3.1.1.
-    uint32_t max_value;   // max value according to UAC2 FMT-2.0 section 2.3.1.1.
+    uint32_t value;    // Feedback value for asynchronous mode (in 16.16 format).
+    uint32_t min_value;// min value according to UAC2 FMT-2.0 section 2.3.1.1.
+    uint32_t max_value;// max value according to UAC2 FMT-2.0 section 2.3.1.1.
 
-    uint8_t frame_shift;  // bInterval-1 in unit of frame (FS), micro-frame (HS)
+    uint8_t frame_shift;// bInterval-1 in unit of frame (FS), micro-frame (HS)
     uint8_t compute_method;
-
+    bool format_correction;
     union {
-      uint8_t power_of_2; // pre-computed power of 2 shift
-      float float_const;  // pre-computed float constant
+      uint8_t power_of_2;// pre-computed power of 2 shift
+      float float_const; // pre-computed float constant
 
       struct {
         uint32_t sample_freq;
         uint32_t mclk_freq;
-      }fixed;
+      } fixed;
 
-#if 0 // implement later
       struct {
-        uint32_t nominal_value;
-        uint32_t threshold_bytes;
-      }fifo_count;
-#endif
-    }compute;
+        uint32_t nom_value;    // In 16.16 format
+        uint32_t fifo_lvl_avg; // In 16.16 format
+        uint16_t fifo_lvl_thr; // fifo level threshold
+        uint16_t rate_const[2];// pre-computed feedback/fifo_depth rate
+      } fifo_count;
+    } compute;
 
   } feedback;
-#endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+#endif// CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
+// Decoding parameters - parameters are set when alternate AS interface is set by host
+// Coding is currently only supported for EP. Software coding corresponding to AS interfaces without EPs are not supported currently.
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
+  audio_format_type_t format_type_rx;
+  uint8_t n_channels_rx;
+
+  #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+  audio_data_format_type_I_t format_type_I_rx;
+  uint8_t n_bytes_per_sample_rx;
+  uint8_t n_ff_used_rx;
+  #endif
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  uint32_t sample_rate_tx;
+  uint16_t packet_sz_tx[3];
+  uint8_t bclock_id_tx;
+  uint8_t interval_tx;
+#endif
+
+// Encoding parameters - parameters are set when alternate AS interface is set by host
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL)
+  audio_format_type_t format_type_tx;
+  uint8_t n_channels_tx;
+  uint8_t n_bytes_per_sample_tx;
+
+  #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+  audio_data_format_type_I_t format_type_I_tx;
+  uint8_t n_ff_used_tx;
+  #endif
+#endif
+
+  /*------------- From this point, data is not cleared by bus reset -------------*/
+
+  // Buffer for control requests
+  uint8_t *ctrl_buf;
+  uint8_t ctrl_buf_sz;
+
+  // Current active alternate settings
+  uint8_t *alt_setting;// We need to save the current alternate setting this way, because it is possible that there are AS interfaces which do not have an EP!
+
+// EP Transfer buffers and FIFOs
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
+  tu_fifo_t ep_out_ff;
+#endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
   tu_fifo_t ep_in_ff;
 #endif
 
-  // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
-#endif
-
-  // Decoding parameters - parameters are set when alternate AS interface is set by host
-  // Coding is currently only supported for EP. Software coding corresponding to AS interfaces without EPs are not supported currently.
+// Support FIFOs for software encoding and decoding
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
-  audio_format_type_t format_type_rx;
-  uint8_t n_channels_rx;
-
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
-  audio_data_format_type_I_t format_type_I_rx;
-  uint8_t n_bytes_per_sampe_rx;
-  uint8_t n_channels_per_ff_rx;
-  uint8_t n_ff_used_rx;
-#endif
-#endif
-
-  // Encoding parameters - parameters are set when alternate AS interface is set by host
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
-  audio_format_type_t format_type_tx;
-  uint8_t n_channels_tx;
-
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
-  audio_data_format_type_I_t format_type_I_tx;
-  uint8_t n_bytes_per_sampe_tx;
-  uint8_t n_channels_per_ff_tx;
-  uint8_t n_ff_used_tx;
-#endif
-#endif
-
-  // Support FIFOs for software encoding and decoding
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
-  tu_fifo_t * rx_supp_ff;
+  tu_fifo_t *rx_supp_ff;
   uint8_t n_rx_supp_ff;
   uint16_t rx_supp_ff_sz_max;
+  #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+  uint8_t n_channels_per_ff_rx;
+  #endif
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
-  tu_fifo_t * tx_supp_ff;
+  tu_fifo_t *tx_supp_ff;
   uint8_t n_tx_supp_ff;
   uint16_t tx_supp_ff_sz_max;
+  #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+  uint8_t n_channels_per_ff_tx;
+  #endif
 #endif
 
-  // Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR the support FIFOs are used
+// Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR the support FIFOs are used
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
-  uint8_t * lin_buf_out;
-#define USE_LINEAR_BUFFER_RX   1
+  uint8_t *lin_buf_out;
+  #define USE_LINEAR_BUFFER_RX 1
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING)
-  uint8_t * lin_buf_in;
-#define USE_LINEAR_BUFFER_TX   1
+  uint8_t *lin_buf_in;
+  #define USE_LINEAR_BUFFER_TX 1
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  uint32_t *fb_buf;
+#endif
 } audiod_function_t;
 
 #ifndef USE_LINEAR_BUFFER_TX
-#define USE_LINEAR_BUFFER_TX   0
+  #define USE_LINEAR_BUFFER_TX 0
 #endif
 
 #ifndef USE_LINEAR_BUFFER_RX
-#define USE_LINEAR_BUFFER_RX   0
+  #define USE_LINEAR_BUFFER_RX 0
 #endif
 
-#define ITF_MEM_RESET_SIZE   offsetof(audiod_function_t, ctrl_buf)
+#define ITF_MEM_RESET_SIZE offsetof(audiod_function_t, ctrl_buf)
 
 //--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
+// WEAK FUNCTION STUBS
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO];
-
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
-static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received);
-#endif
-
-#if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT
-static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received);
-#endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
-static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t* audio);
+TU_ATTR_WEAK bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting) {
+  (void) rhport;
+  (void) func_id;
+  (void) ep_in;
+  (void) cur_alt_setting;
+  return true;
+}
+
+TU_ATTR_WEAK bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting) {
+  (void) rhport;
+  (void) n_bytes_copied;
+  (void) func_id;
+  (void) ep_in;
+  (void) cur_alt_setting;
+  return true;
+}
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN
-static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audio);
-#endif
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+TU_ATTR_WEAK bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting) {
+  (void) rhport;
+  (void) n_bytes_received;
+  (void) func_id;
+  (void) ep_out;
+  (void) cur_alt_setting;
+  return true;
+}
 
-static bool audiod_get_interface(uint8_t rhport, tusb_control_request_t const * p_request);
-static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * p_request);
-
-static bool audiod_get_AS_interface_index_global(uint8_t itf, uint8_t *func_id, uint8_t *idxItf, uint8_t const **pp_desc_int);
-static bool audiod_get_AS_interface_index(uint8_t itf, audiod_function_t * audio, uint8_t *idxItf, uint8_t const **pp_desc_int);
-static bool audiod_verify_entity_exists(uint8_t itf, uint8_t entityID, uint8_t *func_id);
-static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id);
-static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id);
-static uint8_t audiod_get_audio_fct_idx(audiod_function_t * audio);
-
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
-static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * p_desc, uint8_t const * p_desc_end, uint8_t const as_itf);
-
-static inline uint8_t tu_desc_subtype(void const* desc)
-{
-  return ((uint8_t const*) desc)[2];
+TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting) {
+  (void) rhport;
+  (void) n_bytes_received;
+  (void) func_id;
+  (void) ep_out;
+  (void) cur_alt_setting;
+  return true;
 }
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq);
+TU_ATTR_WEAK void tud_audio_fb_done_cb(uint8_t func_id) {
+  (void) func_id;
+}
+
+TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t *feedback_param) {
+  (void) func_id;
+  (void) alt_itf;
+  feedback_param->method = AUDIO_FEEDBACK_METHOD_DISABLED;
+}
+
+TU_ATTR_WEAK bool tud_audio_feedback_format_correction_cb(uint8_t func_id) {
+  (void) func_id;
+  return CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION;
+}
+
+TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift) {
+  (void) func_id;
+  (void) frame_number;
+  (void) interval_shift;
+}
 #endif
 
-bool tud_audio_n_mounted(uint8_t func_id)
-{
-  TU_VERIFY(func_id < CFG_TUD_AUDIO);
-  audiod_function_t* audio = &_audiod_fct[func_id];
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+TU_ATTR_WEAK void tud_audio_int_done_cb(uint8_t rhport) {
+  (void) rhport;
+}
+#endif
+
+// Invoked when audio set interface request received
+TU_ATTR_WEAK bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const *p_request) {
+  (void) rhport;
+  (void) p_request;
+  return true;
+}
+
+// Invoked when audio set interface request received which closes an EP
+TU_ATTR_WEAK bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const *p_request) {
+  (void) rhport;
+  (void) p_request;
+  return true;
+}
+
+// Invoked when audio class specific set request received for an EP
+TU_ATTR_WEAK bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const *p_request, uint8_t *pBuff) {
+  (void) rhport;
+  (void) p_request;
+  (void) pBuff;
+  TU_LOG2("  No EP set request callback available!\r\n");
+  return false;// In case no callback function is present or request can not be conducted we stall it
+}
+
+// Invoked when audio class specific set request received for an interface
+TU_ATTR_WEAK bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const *p_request, uint8_t *pBuff) {
+  (void) rhport;
+  (void) p_request;
+  (void) pBuff;
+  TU_LOG2("  No interface set request callback available!\r\n");
+  return false;// In case no callback function is present or request can not be conducted we stall it
+}
+
+// Invoked when audio class specific set request received for an entity
+TU_ATTR_WEAK bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request, uint8_t *pBuff) {
+  (void) rhport;
+  (void) p_request;
+  (void) pBuff;
+  TU_LOG2("  No entity set request callback available!\r\n");
+  return false;// In case no callback function is present or request can not be conducted we stall it
+}
+
+// Invoked when audio class specific get request received for an EP
+TU_ATTR_WEAK bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const *p_request) {
+  (void) rhport;
+  (void) p_request;
+  TU_LOG2("  No EP get request callback available!\r\n");
+  return false;// Stall
+}
+
+// Invoked when audio class specific get request received for an interface
+TU_ATTR_WEAK bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const *p_request) {
+  (void) rhport;
+  (void) p_request;
+  TU_LOG2("  No interface get request callback available!\r\n");
+  return false;// Stall
+}
+
+// Invoked when audio class specific get request received for an entity
+TU_ATTR_WEAK bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request) {
+  (void) rhport;
+  (void) p_request;
+  TU_LOG2("  No entity get request callback available!\r\n");
+  return false;// Stall
+}
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+tu_static CFG_TUD_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO];
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-  if (audio->ep_out == 0) return false;
+static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received);
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT
+static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received);
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
-  if (audio->ep_in == 0) return false;
+static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio);
 #endif
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  if (audio->ep_int_ctr == 0) return false;
+#if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN
+static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t *audio);
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-  if (audio->ep_fb == 0) return false;
+static bool audiod_get_interface(uint8_t rhport, tusb_control_request_t const *p_request);
+static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p_request);
+
+static bool audiod_get_AS_interface_index_global(uint8_t itf, uint8_t *func_id, uint8_t *idxItf, uint8_t const **pp_desc_int);
+static bool audiod_get_AS_interface_index(uint8_t itf, audiod_function_t *audio, uint8_t *idxItf, uint8_t const **pp_desc_int);
+static bool audiod_verify_entity_exists(uint8_t itf, uint8_t entityID, uint8_t *func_id);
+static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id);
+static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id);
+static uint8_t audiod_get_audio_fct_idx(audiod_function_t *audio);
+
+#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING)
+static void audiod_parse_for_AS_params(audiod_function_t *audio, uint8_t const *p_desc, uint8_t const *p_desc_end, uint8_t const as_itf);
+
+static inline uint8_t tu_desc_subtype(void const *desc) {
+  return ((uint8_t const *) desc)[2];
+}
 #endif
 
-  return true;
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+static bool audiod_calc_tx_packet_sz(audiod_function_t *audio);
+static uint16_t audiod_tx_packet_size(const uint16_t *norminal_size, uint16_t data_count, uint16_t fifo_depth, uint16_t max_size);
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+static bool audiod_set_fb_params_freq(audiod_function_t *audio, uint32_t sample_freq, uint32_t mclk_freq);
+static void audiod_fb_fifo_count_update(audiod_function_t *audio, uint16_t lvl_new);
+#endif
+
+bool tud_audio_n_mounted(uint8_t func_id) {
+  TU_VERIFY(func_id < CFG_TUD_AUDIO);
+  audiod_function_t *audio = &_audiod_fct[func_id];
+
+  return audio->mounted;
 }
 
 //--------------------------------------------------------------------+
@@ -481,27 +657,23 @@ bool tud_audio_n_mounted(uint8_t func_id)
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
 
-uint16_t tud_audio_n_available(uint8_t func_id)
-{
+uint16_t tud_audio_n_available(uint8_t func_id) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
   return tu_fifo_count(&_audiod_fct[func_id].ep_out_ff);
 }
 
-uint16_t tud_audio_n_read(uint8_t func_id, void* buffer, uint16_t bufsize)
-{
+uint16_t tud_audio_n_read(uint8_t func_id, void *buffer, uint16_t bufsize) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
   return tu_fifo_read_n(&_audiod_fct[func_id].ep_out_ff, buffer, bufsize);
 }
 
-bool tud_audio_n_clear_ep_out_ff(uint8_t func_id)
-{
+bool tud_audio_n_clear_ep_out_ff(uint8_t func_id) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
   return tu_fifo_clear(&_audiod_fct[func_id].ep_out_ff);
 }
 
-tu_fifo_t* tud_audio_n_get_ep_out_ff(uint8_t func_id)
-{
-  if(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL) return &_audiod_fct[func_id].ep_out_ff;
+tu_fifo_t *tud_audio_n_get_ep_out_ff(uint8_t func_id) {
+  if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL) return &_audiod_fct[func_id].ep_out_ff;
   return NULL;
 }
 
@@ -509,27 +681,23 @@ tu_fifo_t* tud_audio_n_get_ep_out_ff(uint8_t func_id)
 
 #if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT
 // Delete all content in the support RX FIFOs
-bool tud_audio_n_clear_rx_support_ff(uint8_t func_id, uint8_t ff_idx)
-{
+bool tud_audio_n_clear_rx_support_ff(uint8_t func_id, uint8_t ff_idx) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_rx_supp_ff);
   return tu_fifo_clear(&_audiod_fct[func_id].rx_supp_ff[ff_idx]);
 }
 
-uint16_t tud_audio_n_available_support_ff(uint8_t func_id, uint8_t ff_idx)
-{
+uint16_t tud_audio_n_available_support_ff(uint8_t func_id, uint8_t ff_idx) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_rx_supp_ff);
   return tu_fifo_count(&_audiod_fct[func_id].rx_supp_ff[ff_idx]);
 }
 
-uint16_t tud_audio_n_read_support_ff(uint8_t func_id, uint8_t ff_idx, void* buffer, uint16_t bufsize)
-{
+uint16_t tud_audio_n_read_support_ff(uint8_t func_id, uint8_t ff_idx, void *buffer, uint16_t bufsize) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_rx_supp_ff);
   return tu_fifo_read_n(&_audiod_fct[func_id].rx_supp_ff[ff_idx], buffer, bufsize);
 }
 
-tu_fifo_t* tud_audio_n_get_rx_support_ff(uint8_t func_id, uint8_t ff_idx)
-{
-  if(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_rx_supp_ff) return &_audiod_fct[func_id].rx_supp_ff[ff_idx];
+tu_fifo_t *tud_audio_n_get_rx_support_ff(uint8_t func_id, uint8_t ff_idx) {
+  if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_rx_supp_ff) return &_audiod_fct[func_id].rx_supp_ff[ff_idx];
   return NULL;
 }
 #endif
@@ -539,28 +707,20 @@ tu_fifo_t* tud_audio_n_get_rx_support_ff(uint8_t func_id, uint8_t ff_idx)
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
 
-static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received)
-{
+static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received) {
   uint8_t idxItf = 0;
   uint8_t const *dummy2;
   uint8_t idx_audio_fct = 0;
 
-  if (tud_audio_rx_done_pre_read_cb || tud_audio_rx_done_post_read_cb)
-  {
-    idx_audio_fct = audiod_get_audio_fct_idx(audio);
-    TU_VERIFY(audiod_get_AS_interface_index(audio->ep_out_as_intf_num, audio, &idxItf, &dummy2));
-  }
+  idx_audio_fct = audiod_get_audio_fct_idx(audio);
+  TU_VERIFY(audiod_get_AS_interface_index(audio->ep_out_as_intf_num, audio, &idxItf, &dummy2));
 
   // Call a weak callback here - a possibility for user to get informed an audio packet was received and data gets now loaded into EP FIFO (or decoded into support RX software FIFO)
-  if (tud_audio_rx_done_pre_read_cb)
-  {
-    TU_VERIFY(tud_audio_rx_done_pre_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
-  }
+  TU_VERIFY(tud_audio_rx_done_pre_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
 
-#if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT
+  #if CFG_TUD_AUDIO_ENABLE_DECODING
 
-  switch (audio->format_type_rx)
-  {
+  switch (audio->format_type_rx) {
     case AUDIO_FORMAT_TYPE_UNDEFINED:
       // INDIVIDUAL DECODING PROCEDURE REQUIRED HERE!
       TU_LOG2("  Desired CFG_TUD_AUDIO_FORMAT encoding not implemented!\r\n");
@@ -569,8 +729,7 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 
     case AUDIO_FORMAT_TYPE_I:
 
-      switch (audio->format_type_I_rx)
-      {
+      switch (audio->format_type_I_rx) {
         case AUDIO_DATA_FORMAT_TYPE_I_PCM:
           TU_VERIFY(audiod_decode_type_I_pcm(rhport, audio, n_bytes_received));
           break;
@@ -583,41 +742,44 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
       }
       break;
 
-        default:
-          // Desired CFG_TUD_AUDIO_FORMAT_TYPE_RX not implemented!
-          TU_LOG2("  Desired CFG_TUD_AUDIO_FORMAT_TYPE_RX not implemented!\r\n");
-          TU_BREAKPOINT();
-          break;
+    default:
+      // Desired CFG_TUD_AUDIO_FORMAT_TYPE_RX not implemented!
+      TU_LOG2("  Desired CFG_TUD_AUDIO_FORMAT_TYPE_RX not implemented!\r\n");
+      TU_BREAKPOINT();
+      break;
   }
 
   // Prepare for next transmission
   TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false);
 
-#else
+  #else
 
-#if USE_LINEAR_BUFFER_RX
+    #if USE_LINEAR_BUFFER_RX
   // Data currently is in linear buffer, copy into EP OUT FIFO
   TU_VERIFY(tu_fifo_write_n(&audio->ep_out_ff, audio->lin_buf_out, n_bytes_received));
 
   // Schedule for next receive
   TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false);
-#else
+    #else
   // Data is already placed in EP FIFO, schedule for next receive
   TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_out, &audio->ep_out_ff, audio->ep_out_sz), false);
-#endif
+    #endif
 
-#endif
+    #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  if (audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FIFO_COUNT) {
+    audiod_fb_fifo_count_update(audio, tu_fifo_count(&audio->ep_out_ff));
+  }
+    #endif
+
+  #endif
 
   // Call a weak callback here - a possibility for user to get informed decoding was completed
-  if (tud_audio_rx_done_post_read_cb)
-  {
-    TU_VERIFY(tud_audio_rx_done_post_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
-  }
+  TU_VERIFY(tud_audio_rx_done_post_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
 
   return true;
 }
 
-#endif //CFG_TUD_AUDIO_ENABLE_EP_OUT
+#endif//CFG_TUD_AUDIO_ENABLE_EP_OUT
 
 // The following functions are used in case CFG_TUD_AUDIO_ENABLE_DECODING != 0
 #if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -625,107 +787,74 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 // Decoding according to 2.3.1.5 Audio Streams
 
 // Helper function
-static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used)
-{
+static inline void *audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesPerSample, void *dst, const void *dst_end, void *src, uint8_t const n_ff_used) {
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2)
+  uint16_t *dst16 = dst;
+  uint16_t *src16 = src;
+  const uint16_t *dst_end16 = dst_end;
+  uint32_t *dst32 = dst;
+  uint32_t *src32 = src;
+  const uint32_t *dst_end32 = dst_end;
 
-  // This function is an optimized version of
-  //  while((uint8_t *)dst < dst_end)
-  //  {
-  //    memcpy(dst, src, nBytesToCopy);
-  //    dst = (uint8_t *)dst + nBytesToCopy;
-  //    src += nBytesToCopy * n_ff_used;
-  //  }
-
-  // Optimize for fast half word copies
-  typedef struct{
-    uint16_t val;
-  } __attribute((__packed__)) unaligned_uint16_t;
-
-  // Optimize for fast word copies
-  typedef struct{
-    uint32_t val;
-  } __attribute((__packed__)) unaligned_uint32_t;
-
-  switch (nBytesToCopy)
+  if (nBytesPerSample == 1) {
+    while (dst16 < dst_end16) {
+      *dst16++ = *src16++;
+      src16 += n_ff_used - 1;
+    }
+    return src16;
+  } else if (nBytesPerSample == 2) {
+    while (dst32 < dst_end32) {
+      *dst32++ = *src32++;
+      src32 += n_ff_used - 1;
+    }
+    return src32;
+  } else if (nBytesPerSample == 3) {
+    while (dst16 < dst_end16) {
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      src16 += 3 * (n_ff_used - 1);
+    }
+    return src16;
+  } else// nBytesPerSample == 4
   {
-    case 1:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(uint8_t *)dst++ = *src;
-        src += n_ff_used;
-      }
-      break;
-
-    case 2:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(unaligned_uint16_t*)dst = *(unaligned_uint16_t*)src;
-        dst += 2;
-        src += 2 * n_ff_used;
-      }
-      break;
-
-    case 3:
-      while((uint8_t *)dst < dst_end)
-      {
-        //        memcpy(dst, src, 3);
-        //        dst = (uint8_t *)dst + 3;
-        //        src += 3 * n_ff_used;
-
-        // TODO: Is there a faster way to copy 3 bytes?
-        *(uint8_t *)dst++ = *src++;
-        *(uint8_t *)dst++ = *src++;
-        *(uint8_t *)dst++ = *src++;
-
-        src += 3 * (n_ff_used - 1);
-      }
-      break;
-
-    case 4:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(unaligned_uint32_t*)dst = *(unaligned_uint32_t*)src;
-        dst += 4;
-        src += 4 * n_ff_used;
-      }
-      break;
+    while (dst32 < dst_end32) {
+      *dst32++ = *src32++;
+      *dst32++ = *src32++;
+      src32 += 2 * (n_ff_used - 1);
+    }
+    return src32;
   }
-
-  return src;
 }
 
-static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received)
-{
+static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received) {
   (void) rhport;
 
   // Determine amount of samples
-  uint8_t const n_ff_used               = audio->n_ff_used_rx;
-  uint16_t const nBytesPerFFToRead      = n_bytes_received / n_ff_used;
+  uint8_t const n_ff_used = audio->n_ff_used_rx;
+  uint16_t const nBytesPerFFToRead = n_bytes_received / n_ff_used;
   uint8_t cnt_ff;
 
   // Decode
-  uint8_t * src;
-  uint8_t * dst_end;
+  uint8_t *src;
+  uint8_t *dst_end;
 
   tu_fifo_buffer_info_t info;
 
-  for (cnt_ff = 0; cnt_ff < n_ff_used; cnt_ff++)
-  {
+  for (cnt_ff = 0; cnt_ff < n_ff_used; cnt_ff++) {
     tu_fifo_get_write_info(&audio->rx_supp_ff[cnt_ff], &info);
 
-    if (info.len_lin != 0)
-    {
+    if (info.len_lin != 0) {
       info.len_lin = tu_min16(nBytesPerFFToRead, info.len_lin);
-      src = &audio->lin_buf_out[cnt_ff*audio->n_channels_per_ff_rx * audio->n_bytes_per_sampe_rx];
+      src = &audio->lin_buf_out[cnt_ff * audio->n_channels_per_ff_rx * audio->n_bytes_per_sample_rx];
       dst_end = info.ptr_lin + info.len_lin;
-      src = audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sampe_rx, info.ptr_lin, dst_end, src, n_ff_used);
+      src = audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sample_rx, info.ptr_lin, dst_end, src, n_ff_used);
 
       // Handle wrapped part of FIFO
       info.len_wrap = tu_min16(nBytesPerFFToRead - info.len_lin, info.len_wrap);
-      if (info.len_wrap != 0)
-      {
+      if (info.len_wrap != 0) {
         dst_end = info.ptr_wrap + info.len_wrap;
-        audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sampe_rx, info.ptr_wrap, dst_end, src, n_ff_used);
+        audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sample_rx, info.ptr_wrap, dst_end, src, n_ff_used);
       }
       tu_fifo_advance_write_pointer(&audio->rx_supp_ff[cnt_ff], info.len_lin + info.len_wrap);
     }
@@ -734,9 +863,15 @@ static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, u
   // Number of bytes should be a multiple of CFG_TUD_AUDIO_N_BYTES_PER_SAMPLE_RX * CFG_TUD_AUDIO_N_CHANNELS_RX but checking makes no sense - no way to correct it
   // TU_VERIFY(cnt != n_bytes);
 
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  if (audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FIFO_COUNT) {
+    audiod_fb_fifo_count_update(audio, tu_fifo_count(&audio->rx_supp_ff[0]));
+  }
+  #endif
+
   return true;
 }
-#endif //CFG_TUD_AUDIO_ENABLE_DECODING
+#endif//CFG_TUD_AUDIO_ENABLE_DECODING
 
 //--------------------------------------------------------------------+
 // WRITE API
@@ -755,21 +890,19 @@ static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, u
  * \param[in]       len: # of array elements to copy
  * \return          Number of bytes actually written
  */
-uint16_t tud_audio_n_write(uint8_t func_id, const void * data, uint16_t len)
-{
+uint16_t tud_audio_n_write(uint8_t func_id, const void *data, uint16_t len) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
   return tu_fifo_write_n(&_audiod_fct[func_id].ep_in_ff, data, len);
 }
 
-bool tud_audio_n_clear_ep_in_ff(uint8_t func_id)                          // Delete all content in the EP IN FIFO
+bool tud_audio_n_clear_ep_in_ff(uint8_t func_id)// Delete all content in the EP IN FIFO
 {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
   return tu_fifo_clear(&_audiod_fct[func_id].ep_in_ff);
 }
 
-tu_fifo_t* tud_audio_n_get_ep_in_ff(uint8_t func_id)
-{
-  if(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL) return &_audiod_fct[func_id].ep_in_ff;
+tu_fifo_t *tud_audio_n_get_ep_in_ff(uint8_t func_id) {
+  if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL) return &_audiod_fct[func_id].ep_in_ff;
   return NULL;
 }
 
@@ -777,73 +910,68 @@ tu_fifo_t* tud_audio_n_get_ep_in_ff(uint8_t func_id)
 
 #if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN
 
-uint16_t tud_audio_n_flush_tx_support_ff(uint8_t func_id)                 // Force all content in the support TX FIFOs to be written into linear buffer and schedule a transmit
+uint16_t tud_audio_n_flush_tx_support_ff(uint8_t func_id)// Force all content in the support TX FIFOs to be written into linear buffer and schedule a transmit
 {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
-  audiod_function_t* audio = &_audiod_fct[func_id];
+  audiod_function_t *audio = &_audiod_fct[func_id];
 
   uint16_t n_bytes_copied = tu_fifo_count(&audio->tx_supp_ff[0]);
 
   TU_VERIFY(audiod_tx_done_cb(audio->rhport, audio));
 
   n_bytes_copied -= tu_fifo_count(&audio->tx_supp_ff[0]);
-  n_bytes_copied = n_bytes_copied*audio->tx_supp_ff[0].item_size;
+  n_bytes_copied = n_bytes_copied * audio->tx_supp_ff[0].item_size;
 
   return n_bytes_copied;
 }
 
-bool tud_audio_n_clear_tx_support_ff(uint8_t func_id, uint8_t ff_idx)
-{
+bool tud_audio_n_clear_tx_support_ff(uint8_t func_id, uint8_t ff_idx) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_tx_supp_ff);
   return tu_fifo_clear(&_audiod_fct[func_id].tx_supp_ff[ff_idx]);
 }
 
-uint16_t tud_audio_n_write_support_ff(uint8_t func_id, uint8_t ff_idx, const void * data, uint16_t len)
-{
+uint16_t tud_audio_n_write_support_ff(uint8_t func_id, uint8_t ff_idx, const void *data, uint16_t len) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_tx_supp_ff);
   return tu_fifo_write_n(&_audiod_fct[func_id].tx_supp_ff[ff_idx], data, len);
 }
 
-tu_fifo_t* tud_audio_n_get_tx_support_ff(uint8_t func_id, uint8_t ff_idx)
-{
-  if(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_tx_supp_ff) return &_audiod_fct[func_id].tx_supp_ff[ff_idx];
+tu_fifo_t *tud_audio_n_get_tx_support_ff(uint8_t func_id, uint8_t ff_idx) {
+  if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_tx_supp_ff) return &_audiod_fct[func_id].tx_supp_ff[ff_idx];
   return NULL;
 }
 
 #endif
 
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-
-// If no interrupt transmit is pending bytes get written into buffer and a transmit is scheduled - once transmit completed tud_audio_int_ctr_done_cb() is called in inform user
-uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint16_t len)
-{
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+// If no interrupt transmit is pending bytes get written into buffer and a transmit is scheduled - once transmit completed tud_audio_int_done_cb() is called in inform user
+bool tud_audio_int_n_write(uint8_t func_id, const audio_interrupt_data_t *data) {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
+  TU_VERIFY(_audiod_fct[func_id].ep_int != 0);
+
   // We write directly into the EP's buffer - abort if previous transfer not complete
-  TU_VERIFY(!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int_ctr));
+  TU_VERIFY(usbd_edpt_claim(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int));
 
   // Check length
-  TU_VERIFY(len <= CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE);
-
-  memcpy(_audiod_fct[func_id].ep_int_ctr_buf, buffer, len);
-
-  // Schedule transmit
-  TU_VERIFY(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int_ctr, _audiod_fct[func_id].ep_int_ctr_buf, len));
+  if (tu_memcpy_s(int_ep_buf[func_id].buf, sizeof(int_ep_buf[func_id].buf), data, sizeof(audio_interrupt_data_t)) == 0) {
+    // Schedule transmit
+    TU_ASSERT(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int, int_ep_buf[func_id].buf, sizeof(int_ep_buf[func_id].buf)), 0);
+  } else {
+    // Release endpoint since we don't make any transfer
+    usbd_edpt_release(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int);
+  }
 
   return true;
 }
-
 #endif
 
-
 // This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission.
 // If you prefer your own (more efficient) implementation suiting your purpose set CFG_TUD_AUDIO_ENABLE_ENCODING = 0 and use tud_audio_n_write.
 
 // n_bytes_copied - Informs caller how many bytes were loaded. In case n_bytes_copied = 0, a ZLP is scheduled to inform host no data is available for current frame.
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
-static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
-{
+static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio) {
   uint8_t idxItf;
   uint8_t const *dummy2;
 
@@ -855,15 +983,14 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
 
   // Call a weak callback here - a possibility for user to get informed former TX was completed and data gets now loaded into EP in buffer (in case FIFOs are used) or
   // if no FIFOs are used the user may use this call back to load its data into the EP IN buffer by use of tud_audio_n_write_ep_in_buffer().
-  if (tud_audio_tx_done_pre_load_cb) TU_VERIFY(tud_audio_tx_done_pre_load_cb(rhport, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf]));
+  TU_VERIFY(tud_audio_tx_done_pre_load_cb(rhport, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf]));
 
   // Send everything in ISO EP FIFO
   uint16_t n_bytes_tx;
 
   // If support FIFOs are used, encode and schedule transmit
-#if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN
-  switch (audio->format_type_tx)
-  {
+  #if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN
+  switch (audio->format_type_tx) {
     case AUDIO_FORMAT_TYPE_UNDEFINED:
       // INDIVIDUAL ENCODING PROCEDURE REQUIRED HERE!
       TU_LOG2("  Desired CFG_TUD_AUDIO_FORMAT encoding not implemented!\r\n");
@@ -873,8 +1000,7 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
 
     case AUDIO_FORMAT_TYPE_I:
 
-      switch (audio->format_type_I_tx)
-      {
+      switch (audio->format_type_I_tx) {
         case AUDIO_DATA_FORMAT_TYPE_I_PCM:
 
           n_bytes_tx = audiod_encode_type_I_pcm(rhport, audio);
@@ -889,38 +1015,41 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
       }
       break;
 
-        default:
-          // Desired CFG_TUD_AUDIO_FORMAT_TYPE_TX not implemented!
-          TU_LOG2("  Desired CFG_TUD_AUDIO_FORMAT_TYPE_TX not implemented!\r\n");
-          TU_BREAKPOINT();
-          n_bytes_tx = 0;
-          break;
+    default:
+      // Desired CFG_TUD_AUDIO_FORMAT_TYPE_TX not implemented!
+      TU_LOG2("  Desired CFG_TUD_AUDIO_FORMAT_TYPE_TX not implemented!\r\n");
+      TU_BREAKPOINT();
+      n_bytes_tx = 0;
+      break;
   }
 
   TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_in, audio->lin_buf_in, n_bytes_tx));
 
-#else
-  // No support FIFOs, if no linear buffer required schedule transmit, else put data into linear buffer and schedule
-
-  n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);      // Limit up to max packet size, more can not be done for ISO
-
-#if USE_LINEAR_BUFFER_TX
+  #else
+    // No support FIFOs, if no linear buffer required schedule transmit, else put data into linear buffer and schedule
+    #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  // packet_sz_tx is based on total packet size, here we want size for each support buffer.
+  n_bytes_tx = audiod_tx_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, audio->ep_in_sz);
+    #else
+  n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);// Limit up to max packet size, more can not be done for ISO
+    #endif
+    #if USE_LINEAR_BUFFER_TX
   tu_fifo_read_n(&audio->ep_in_ff, audio->lin_buf_in, n_bytes_tx);
   TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_in, audio->lin_buf_in, n_bytes_tx));
-#else
+    #else
   // Send everything in ISO EP FIFO
   TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_in, &audio->ep_in_ff, n_bytes_tx));
-#endif
+    #endif
 
-#endif
+  #endif
 
   // Call a weak callback here - a possibility for user to get informed former TX was completed and how many bytes were loaded for the next frame
-  if (tud_audio_tx_done_post_load_cb) TU_VERIFY(tud_audio_tx_done_post_load_cb(rhport, n_bytes_tx, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf]));
+  TU_VERIFY(tud_audio_tx_done_post_load_cb(rhport, n_bytes_tx, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf]));
 
   return true;
 }
 
-#endif //CFG_TUD_AUDIO_ENABLE_EP_IN
+#endif//CFG_TUD_AUDIO_ENABLE_EP_IN
 
 #if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN
 // Take samples from the support buffer and encode them into the IN EP software FIFO
@@ -941,68 +1070,47 @@ range [-1, +1)
  * */
 
 // Helper function
-static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, uint8_t * src, uint8_t * src_end, uint8_t * dst, uint8_t const n_ff_used)
-{
-  // Optimize for fast half word copies
-  typedef struct{
-    uint16_t val;
-  } __attribute((__packed__)) unaligned_uint16_t;
+static inline void *audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesPerSample, void *src, const void *src_end, void *dst, uint8_t const n_ff_used) {
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2)
+  uint16_t *dst16 = dst;
+  uint16_t *src16 = src;
+  const uint16_t *src_end16 = src_end;
+  uint32_t *dst32 = dst;
+  uint32_t *src32 = src;
+  const uint32_t *src_end32 = src_end;
 
-  // Optimize for fast word copies
-  typedef struct{
-    uint32_t val;
-  } __attribute((__packed__)) unaligned_uint32_t;
-
-  switch (nBytesToCopy)
+  if (nBytesPerSample == 1) {
+    while (src16 < src_end16) {
+      *dst16++ = *src16++;
+      dst16 += n_ff_used - 1;
+    }
+    return dst16;
+  } else if (nBytesPerSample == 2) {
+    while (src32 < src_end32) {
+      *dst32++ = *src32++;
+      dst32 += n_ff_used - 1;
+    }
+    return dst32;
+  } else if (nBytesPerSample == 3) {
+    while (src16 < src_end16) {
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      dst16 += 3 * (n_ff_used - 1);
+    }
+    return dst16;
+  } else// nBytesPerSample == 4
   {
-    case 1:
-      while(src < src_end)
-      {
-        *dst = *src++;
-        dst += n_ff_used;
-      }
-      break;
-
-    case 2:
-      while(src < src_end)
-      {
-        *(unaligned_uint16_t*)dst = *(unaligned_uint16_t*)src;
-        src += 2;
-        dst += 2 * n_ff_used;
-      }
-      break;
-
-    case 3:
-      while(src < src_end)
-      {
-        //        memcpy(dst, src, 3);
-        //        src = (uint8_t *)src + 3;
-        //        dst += 3 * n_ff_used;
-
-        // TODO: Is there a faster way to copy 3 bytes?
-        *dst++ = *src++;
-        *dst++ = *src++;
-        *dst++ = *src++;
-
-        dst += 3 * (n_ff_used - 1);
-      }
-      break;
-
-    case 4:
-      while(src < src_end)
-      {
-        *(unaligned_uint32_t*)dst = *(unaligned_uint32_t*)src;
-        src += 4;
-        dst += 4 * n_ff_used;
-      }
-      break;
+    while (src32 < src_end32) {
+      *dst32++ = *src32++;
+      *dst32++ = *src32++;
+      dst32 += 2 * (n_ff_used - 1);
+    }
+    return dst32;
   }
-
-  return dst;
 }
 
-static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audio)
-{
+static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t *audio) {
   // This function relies on the fact that the length of the support FIFOs was configured to be a multiple of the active sample size in bytes s.t. no sample is split within a wrap
   // This is ensured within set_interface, where the FIFOs are reconfigured according to this size
 
@@ -1010,56 +1118,58 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
   TU_VERIFY(!usbd_edpt_busy(rhport, audio->ep_in));
 
   // Determine amount of samples
-  uint8_t const n_ff_used               = audio->n_ff_used_tx;
-  uint16_t const nBytesToCopy           = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx;
-  uint16_t const capPerFF               = audio->ep_in_sz / n_ff_used;                                        // Sample capacity per FIFO in bytes
-  uint16_t nBytesPerFFToSend            = tu_fifo_count(&audio->tx_supp_ff[0]);
+  uint8_t const n_ff_used = audio->n_ff_used_tx;
+  uint16_t nBytesPerFFToSend = tu_fifo_count(&audio->tx_supp_ff[0]);
   uint8_t cnt_ff;
 
-  for (cnt_ff = 1; cnt_ff < n_ff_used; cnt_ff++)
-  {
+  for (cnt_ff = 1; cnt_ff < n_ff_used; cnt_ff++) {
     uint16_t const count = tu_fifo_count(&audio->tx_supp_ff[cnt_ff]);
-    if (count < nBytesPerFFToSend)
-    {
+    if (count < nBytesPerFFToSend) {
       nBytesPerFFToSend = count;
     }
   }
 
-  // Check if there is enough
-  if (nBytesPerFFToSend == 0)    return 0;
-
+  #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  const uint16_t norm_packet_sz_tx[3] = {audio->packet_sz_tx[0] / n_ff_used,
+                                         audio->packet_sz_tx[1] / n_ff_used,
+                                         audio->packet_sz_tx[2] / n_ff_used};
+  // packet_sz_tx is based on total packet size, here we want size for each support buffer.
+  nBytesPerFFToSend = audiod_tx_packet_size(norm_packet_sz_tx, nBytesPerFFToSend, audio->tx_supp_ff[0].depth, audio->ep_in_sz / n_ff_used);
+  // Check if there is enough data
+  if (nBytesPerFFToSend == 0) return 0;
+  #else
+  // Check if there is enough data
+  if (nBytesPerFFToSend == 0) return 0;
   // Limit to maximum sample number - THIS IS A POSSIBLE ERROR SOURCE IF TOO MANY SAMPLE WOULD NEED TO BE SENT BUT CAN NOT!
-  nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, capPerFF);
-
+  nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, audio->ep_in_sz / n_ff_used);
   // Round to full number of samples (flooring)
-  nBytesPerFFToSend = (nBytesPerFFToSend / nBytesToCopy) * nBytesToCopy;
+  uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx;
+  nBytesPerFFToSend = (nBytesPerFFToSend / nSlotSize) * nSlotSize;
+  #endif
 
   // Encode
-  uint8_t * dst;
-  uint8_t * src_end;
+  uint8_t *dst;
+  uint8_t *src_end;
 
   tu_fifo_buffer_info_t info;
 
-  for (cnt_ff = 0; cnt_ff < n_ff_used; cnt_ff++)
-  {
-    dst = &audio->lin_buf_in[cnt_ff*audio->n_channels_per_ff_tx*audio->n_bytes_per_sampe_tx];
+  for (cnt_ff = 0; cnt_ff < n_ff_used; cnt_ff++) {
+    dst = &audio->lin_buf_in[cnt_ff * audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx];
 
     tu_fifo_get_read_info(&audio->tx_supp_ff[cnt_ff], &info);
 
-    if (info.len_lin != 0)
-    {
-      info.len_lin = tu_min16(nBytesPerFFToSend, info.len_lin);       // Limit up to desired length
-      src_end = (uint8_t *)info.ptr_lin + info.len_lin;
-      dst = audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sampe_tx, info.ptr_lin, src_end, dst, n_ff_used);
+    if (info.len_lin != 0) {
+      info.len_lin = tu_min16(nBytesPerFFToSend, info.len_lin);// Limit up to desired length
+      src_end = (uint8_t *) info.ptr_lin + info.len_lin;
+      dst = audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sample_tx, info.ptr_lin, src_end, dst, n_ff_used);
 
       // Limit up to desired length
       info.len_wrap = tu_min16(nBytesPerFFToSend - info.len_lin, info.len_wrap);
 
       // Handle wrapped part of FIFO
-      if (info.len_wrap != 0)
-      {
-        src_end = (uint8_t *)info.ptr_wrap + info.len_wrap;
-        audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sampe_tx, info.ptr_wrap, src_end, dst, n_ff_used);
+      if (info.len_wrap != 0) {
+        src_end = (uint8_t *) info.ptr_wrap + info.len_wrap;
+        audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sample_tx, info.ptr_wrap, src_end, dst, n_ff_used);
       }
 
       tu_fifo_advance_read_pointer(&audio->tx_supp_ff[cnt_ff], info.len_lin + info.len_wrap);
@@ -1068,31 +1178,54 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
 
   return nBytesPerFFToSend * n_ff_used;
 }
-#endif //CFG_TUD_AUDIO_ENABLE_ENCODING
+#endif//CFG_TUD_AUDIO_ENABLE_ENCODING
 
 // This function is called once a transmit of a feedback packet was successfully completed. Here, we get the next feedback value to be sent
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-static inline bool audiod_fb_send(uint8_t rhport, audiod_function_t *audio)
-{
-  return usbd_edpt_xfer(rhport, audio->ep_fb, (uint8_t *) &audio->feedback.value, 4);
+static inline bool audiod_fb_send(audiod_function_t *audio) {
+  bool apply_correction = (TUSB_SPEED_FULL == tud_speed_get()) && audio->feedback.format_correction;
+  // Format the feedback value
+  if (apply_correction) {
+    uint8_t *fb = (uint8_t *) audio->fb_buf;
+
+    // For FS format is 10.14
+    *(fb++) = (audio->feedback.value >> 2) & 0xFF;
+    *(fb++) = (audio->feedback.value >> 10) & 0xFF;
+    *(fb++) = (audio->feedback.value >> 18) & 0xFF;
+    *fb = 0;
+  } else {
+    *audio->fb_buf = audio->feedback.value;
+  }
+
+  // About feedback format on FS
+  //
+  // 3 variables: Format | packetSize | sendSize | Working OS:
+  //              16.16    4            4          Linux, Windows
+  //              16.16    4            3          Linux
+  //              16.16    3            4          Linux
+  //              16.16    3            3          Linux
+  //              10.14    4            4          Linux
+  //              10.14    4            3          Linux
+  //              10.14    3            4          Linux, OSX
+  //              10.14    3            3          Linux, OSX
+  //
+  // We send 3 bytes since sending packet larger than wMaxPacketSize is pretty ugly
+  return usbd_edpt_xfer(audio->rhport, audio->ep_fb, (uint8_t *) audio->fb_buf, apply_correction ? 3 : 4);
 }
 #endif
 
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void audiod_init(void)
-{
+void audiod_init(void) {
   tu_memclr(_audiod_fct, sizeof(_audiod_fct));
 
-  for(uint8_t i=0; i<CFG_TUD_AUDIO; i++)
-  {
-    audiod_function_t* audio = &_audiod_fct[i];
+  for (uint8_t i = 0; i < CFG_TUD_AUDIO; i++) {
+    audiod_function_t *audio = &_audiod_fct[i];
 
     // Initialize control buffers
-    switch (i)
-    {
+    switch (i) {
       case 0:
         audio->ctrl_buf = ctrl_buf_1;
         audio->ctrl_buf_sz = CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ;
@@ -1112,8 +1245,7 @@ void audiod_init(void)
     }
 
     // Initialize active alternate interface buffers
-    switch (i)
-    {
+    switch (i) {
 #if CFG_TUD_AUDIO_FUNC_1_N_AS_INT > 0
       case 0:
         audio->alt_setting = alt_setting_1;
@@ -1131,277 +1263,285 @@ void audiod_init(void)
 #endif
     }
 
-    // Initialize IN EP FIFO if required
+      // Initialize IN EP FIFO if required
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
 
-    switch (i)
-    {
-#if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
+    switch (i) {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
       case 0:
-        tu_fifo_config(&audio->ep_in_ff, audio_ep_in_sw_buf_1, CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+        tu_fifo_config(&audio->ep_in_ff, ep_in_sw_buf.buf_1, CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ, 1, true);
+    #if CFG_FIFO_MUTEX
         tu_fifo_config_mutex(&audio->ep_in_ff, osal_mutex_create(&ep_in_ff_mutex_wr_1), NULL);
-#endif
+    #endif
         break;
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
       case 1:
-        tu_fifo_config(&audio->ep_in_ff, audio_ep_in_sw_buf_2, CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+        tu_fifo_config(&audio->ep_in_ff, ep_in_sw_buf.buf_2, CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ, 1, true);
+    #if CFG_FIFO_MUTEX
         tu_fifo_config_mutex(&audio->ep_in_ff, osal_mutex_create(&ep_in_ff_mutex_wr_2), NULL);
-#endif
+    #endif
         break;
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
       case 2:
-        tu_fifo_config(&audio->ep_in_ff, audio_ep_in_sw_buf_3, CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+        tu_fifo_config(&audio->ep_in_ff, ep_in_sw_buf.buf_3, CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ, 1, true);
+    #if CFG_FIFO_MUTEX
         tu_fifo_config_mutex(&audio->ep_in_ff, osal_mutex_create(&ep_in_ff_mutex_wr_3), NULL);
-#endif
+    #endif
         break;
-#endif
+  #endif
     }
-#endif // CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
+#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
 
-    // Initialize linear buffers
+      // Initialize linear buffers
 #if USE_LINEAR_BUFFER_TX
-    switch (i)
-    {
-#if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
+    switch (i) {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
       case 0:
-        audio->lin_buf_in = lin_buf_in_1;
+        audio->lin_buf_in = lin_buf_in.buf_1;
         break;
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
       case 1:
-        audio->lin_buf_in = lin_buf_in_2;
+        audio->lin_buf_in = lin_buf_in.buf_2;
         break;
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
       case 2:
-        audio->lin_buf_in = lin_buf_in_3;
+        audio->lin_buf_in = lin_buf_in.buf_3;
         break;
-#endif
+  #endif
     }
-#endif // USE_LINEAR_BUFFER_TX
+#endif// USE_LINEAR_BUFFER_TX
 
-    // Initialize OUT EP FIFO if required
+      // Initialize OUT EP FIFO if required
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
 
-    switch (i)
-    {
-#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
+    switch (i) {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
       case 0:
-        tu_fifo_config(&audio->ep_out_ff, audio_ep_out_sw_buf_1, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+        tu_fifo_config(&audio->ep_out_ff, ep_out_sw_buf.buf_1, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ, 1, true);
+    #if CFG_FIFO_MUTEX
         tu_fifo_config_mutex(&audio->ep_out_ff, NULL, osal_mutex_create(&ep_out_ff_mutex_rd_1));
-#endif
+    #endif
         break;
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
       case 1:
-        tu_fifo_config(&audio->ep_out_ff, audio_ep_out_sw_buf_2, CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+        tu_fifo_config(&audio->ep_out_ff, ep_out_sw_buf.buf_2, CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ, 1, true);
+    #if CFG_FIFO_MUTEX
         tu_fifo_config_mutex(&audio->ep_out_ff, NULL, osal_mutex_create(&ep_out_ff_mutex_rd_2));
-#endif
+    #endif
         break;
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
       case 2:
-        tu_fifo_config(&audio->ep_out_ff, audio_ep_out_sw_buf_3, CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+        tu_fifo_config(&audio->ep_out_ff, ep_out_sw_buf.buf_3, CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ, 1, true);
+    #if CFG_FIFO_MUTEX
         tu_fifo_config_mutex(&audio->ep_out_ff, NULL, osal_mutex_create(&ep_out_ff_mutex_rd_3));
-#endif
+    #endif
         break;
-#endif
+  #endif
     }
-#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
+#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
 
-    // Initialize linear buffers
+      // Initialize linear buffers
 #if USE_LINEAR_BUFFER_RX
-    switch (i)
-    {
-#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
+    switch (i) {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
       case 0:
-        audio->lin_buf_out = lin_buf_out_1;
+        audio->lin_buf_out = lin_buf_out.buf_1;
         break;
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
       case 1:
-        audio->lin_buf_out = lin_buf_out_2;
+        audio->lin_buf_out = lin_buf_out.buf_2;
         break;
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
       case 2:
-        audio->lin_buf_out = lin_buf_out_3;
+        audio->lin_buf_out = lin_buf_out.buf_3;
         break;
-#endif
+  #endif
     }
-#endif // USE_LINEAR_BUFFER_TX
+#endif// USE_LINEAR_BUFFER_RX
 
-    // Initialize TX support FIFOs if required
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+    switch (i) {
+  #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
+      case 0:
+        audio->fb_buf = &fb_ep_buf.buf_1;
+        break;
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
+      case 1:
+        audio->fb_buf = &fb_ep_buf.buf_2;
+        break;
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
+      case 2:
+        audio->fb_buf = &fb_ep_buf.buf_3;
+        break;
+  #endif
+    }
+#endif// CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+
+      // Initialize TX support FIFOs if required
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
 
-    switch (i)
-    {
-#if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
+    switch (i) {
+  #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
       case 0:
         audio->tx_supp_ff = tx_supp_ff_1;
         audio->n_tx_supp_ff = CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO;
         audio->tx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ;
-        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; cnt++)
-        {
+        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; cnt++) {
           tu_fifo_config(&tx_supp_ff_1[cnt], tx_supp_ff_buf_1[cnt], CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+    #if CFG_FIFO_MUTEX
           tu_fifo_config_mutex(&tx_supp_ff_1[cnt], osal_mutex_create(&tx_supp_ff_mutex_wr_1[cnt]), NULL);
-#endif
+    #endif
         }
 
         break;
-#endif // CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
+  #endif// CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
 
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
       case 1:
         audio->tx_supp_ff = tx_supp_ff_2;
         audio->n_tx_supp_ff = CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO;
         audio->tx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ;
-        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO; cnt++)
-        {
+        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO; cnt++) {
           tu_fifo_config(&tx_supp_ff_2[cnt], tx_supp_ff_buf_2[cnt], CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+    #if CFG_FIFO_MUTEX
           tu_fifo_config_mutex(&tx_supp_ff_2[cnt], osal_mutex_create(&tx_supp_ff_mutex_wr_2[cnt]), NULL);
-#endif
+    #endif
         }
 
         break;
-#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
+  #endif// CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
 
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
       case 2:
         audio->tx_supp_ff = tx_supp_ff_3;
         audio->n_tx_supp_ff = CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO;
         audio->tx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ;
-        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO; cnt++)
-        {
+        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO; cnt++) {
           tu_fifo_config(&tx_supp_ff_3[cnt], tx_supp_ff_buf_3[cnt], CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+    #if CFG_FIFO_MUTEX
           tu_fifo_config_mutex(&tx_supp_ff_3[cnt], osal_mutex_create(&tx_supp_ff_mutex_wr_3[cnt]), NULL);
-#endif
+    #endif
         }
 
         break;
-#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
+  #endif// CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
     }
-#endif // CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
+#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
 
-    // Set encoding parameters for Type_I formats
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
-    switch (i)
-    {
-#if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
+      // Set encoding parameters for Type_I formats
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+    switch (i) {
+  #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
       case 0:
         audio->n_channels_per_ff_tx = CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX;
         break;
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
       case 1:
         audio->n_channels_per_ff_tx = CFG_TUD_AUDIO_FUNC_2_CHANNEL_PER_FIFO_TX;
         break;
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
       case 2:
         audio->n_channels_per_ff_tx = CFG_TUD_AUDIO_FUNC_3_CHANNEL_PER_FIFO_TX;
         break;
-#endif
+  #endif
     }
-#endif // CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+#endif// CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
 
-    // Initialize RX support FIFOs if required
+      // Initialize RX support FIFOs if required
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
 
-    switch (i)
-    {
-#if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
+    switch (i) {
+  #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
       case 0:
         audio->rx_supp_ff = rx_supp_ff_1;
         audio->n_rx_supp_ff = CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO;
         audio->rx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ;
-        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO; cnt++)
-        {
+        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO; cnt++) {
           tu_fifo_config(&rx_supp_ff_1[cnt], rx_supp_ff_buf_1[cnt], CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+    #if CFG_FIFO_MUTEX
           tu_fifo_config_mutex(&rx_supp_ff_1[cnt], osal_mutex_create(&rx_supp_ff_mutex_rd_1[cnt]), NULL);
-#endif
+    #endif
         }
 
         break;
-#endif // CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
+  #endif// CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
 
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
       case 1:
         audio->rx_supp_ff = rx_supp_ff_2;
         audio->n_rx_supp_ff = CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO;
         audio->rx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ;
-        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO; cnt++)
-        {
+        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO; cnt++) {
           tu_fifo_config(&rx_supp_ff_2[cnt], rx_supp_ff_buf_2[cnt], CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+    #if CFG_FIFO_MUTEX
           tu_fifo_config_mutex(&rx_supp_ff_2[cnt], osal_mutex_create(&rx_supp_ff_mutex_rd_2[cnt]), NULL);
-#endif
+    #endif
         }
 
         break;
-#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
+  #endif// CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
 
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
       case 2:
         audio->rx_supp_ff = rx_supp_ff_3;
         audio->n_rx_supp_ff = CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO;
         audio->rx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ;
-        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO; cnt++)
-        {
+        for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO; cnt++) {
           tu_fifo_config(&rx_supp_ff_3[cnt], rx_supp_ff_buf_3[cnt], CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ, 1, true);
-#if CFG_FIFO_MUTEX
+    #if CFG_FIFO_MUTEX
           tu_fifo_config_mutex(&rx_supp_ff_3[cnt], osal_mutex_create(&rx_supp_ff_mutex_rd_3[cnt]), NULL);
-#endif
+    #endif
         }
 
         break;
-#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
+  #endif// CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
     }
-#endif // CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
+#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
 
-    // Set encoding parameters for Type_I formats
+      // Set encoding parameters for Type_I formats
 #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
-    switch (i)
-    {
-#if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
+    switch (i) {
+  #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
       case 0:
         audio->n_channels_per_ff_rx = CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_RX;
         break;
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
+  #endif
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
       case 1:
         audio->n_channels_per_ff_rx = CFG_TUD_AUDIO_FUNC_2_CHANNEL_PER_FIFO_RX;
         break;
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
+  #endif
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
       case 2:
         audio->n_channels_per_ff_rx = CFG_TUD_AUDIO_FUNC_3_CHANNEL_PER_FIFO_RX;
         break;
-#endif
+  #endif
     }
-#endif // CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+#endif// CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
   }
 }
 
-void audiod_reset(uint8_t rhport)
-{
+bool audiod_deinit(void) {
+  return false;// TODO not implemented yet
+}
+
+void audiod_reset(uint8_t rhport) {
   (void) rhport;
 
-  for(uint8_t i=0; i<CFG_TUD_AUDIO; i++)
-  {
-    audiod_function_t* audio = &_audiod_fct[i];
+  for (uint8_t i = 0; i < CFG_TUD_AUDIO; i++) {
+    audiod_function_t *audio = &_audiod_fct[i];
     tu_memclr(audio, ITF_MEM_RESET_SIZE);
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
@@ -1413,35 +1553,32 @@ void audiod_reset(uint8_t rhport)
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
-    for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
-    {
+    for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++) {
       tu_fifo_clear(&audio->tx_supp_ff[cnt]);
     }
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
-    for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++)
-    {
+    for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++) {
       tu_fifo_clear(&audio->rx_supp_ff[cnt]);
     }
 #endif
   }
 }
 
-uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
+uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
   (void) max_len;
 
-  TU_VERIFY ( TUSB_CLASS_AUDIO  == itf_desc->bInterfaceClass &&
-              AUDIO_SUBCLASS_CONTROL    == itf_desc->bInterfaceSubClass);
+  TU_VERIFY(TUSB_CLASS_AUDIO == itf_desc->bInterfaceClass &&
+            AUDIO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass);
 
   // Verify version is correct - this check can be omitted
   TU_VERIFY(itf_desc->bInterfaceProtocol == AUDIO_INT_PROTOCOL_CODE_V2);
 
-  // Verify interrupt control EP is enabled if demanded by descriptor - this should be best some static check however - this check can be omitted
-  if (itf_desc->bNumEndpoints == 1) // 0 or 1 EPs are allowed
-  {
-    TU_VERIFY(CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN > 0);
+  // Verify interrupt control EP is enabled if demanded by descriptor
+  TU_ASSERT(itf_desc->bNumEndpoints <= 1);// 0 or 1 EPs are allowed
+  if (itf_desc->bNumEndpoints == 1) {
+    TU_ASSERT(CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP);
   }
 
   // Alternate setting MUST be zero - this check can be omitted
@@ -1449,16 +1586,13 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 
   // Find available audio driver interface
   uint8_t i;
-  for (i = 0; i < CFG_TUD_AUDIO; i++)
-  {
-    if (!_audiod_fct[i].p_desc)
-    {
-      _audiod_fct[i].p_desc = (uint8_t const *)itf_desc;    // Save pointer to AC descriptor which is by specification always the first one
+  for (i = 0; i < CFG_TUD_AUDIO; i++) {
+    if (!_audiod_fct[i].p_desc) {
+      _audiod_fct[i].p_desc = (uint8_t const *) itf_desc;// Save pointer to AC descriptor which is by specification always the first one
       _audiod_fct[i].rhport = rhport;
 
       // Setup descriptor lengths
-      switch (i)
-      {
+      switch (i) {
         case 0:
           _audiod_fct[i].desc_length = CFG_TUD_AUDIO_FUNC_1_DESC_LEN;
           break;
@@ -1474,21 +1608,136 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 #endif
       }
 
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+      {
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN
+        uint8_t ep_in = 0;
+        uint16_t ep_in_size = 0;
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
+        uint8_t ep_out = 0;
+        uint16_t ep_out_size = 0;
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+        uint8_t ep_fb = 0;
+  #endif
+        uint8_t const *p_desc = _audiod_fct[i].p_desc;
+        uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+        // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+        while (p_desc_end - p_desc > 0) {
+          if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) {
+            tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+            if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+              // Explicit feedback EP
+              if (desc_ep->bmAttributes.usage == 1) {
+                ep_fb = desc_ep->bEndpointAddress;
+              }
+  #endif
+              // Data EP
+              if (desc_ep->bmAttributes.usage == 0) {
+                if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN
+                  ep_in = desc_ep->bEndpointAddress;
+                  ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
+  #endif
+                } else {
+  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
+                  ep_out = desc_ep->bEndpointAddress;
+                  ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size);
+  #endif
+                }
+              }
+            }
+          }
+
+          p_desc = tu_desc_next(p_desc);
+        }
+
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN
+        if (ep_in) {
+          usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size);
+        }
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
+        if (ep_out) {
+          usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size);
+        }
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+        if (ep_fb) {
+          usbd_edpt_iso_alloc(rhport, ep_fb, 4);
+        }
+  #endif
+      }
+#endif// TUP_DCD_EDPT_ISO_ALLOC
+
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+      {
+        uint8_t const *p_desc = _audiod_fct[i].p_desc;
+        uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+        // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+        while (p_desc_end - p_desc > 0) {
+          if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) {
+            tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+            if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
+              if (desc_ep->bmAttributes.usage == 0) {
+                if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+                  _audiod_fct[i].interval_tx = desc_ep->bInterval;
+                }
+              }
+            }
+          } else if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AC_INTERFACE_OUTPUT_TERMINAL) {
+            if (tu_unaligned_read16(p_desc + 4) == AUDIO_TERM_TYPE_USB_STREAMING) {
+              _audiod_fct[i].bclock_id_tx = p_desc[8];
+            }
+          }
+          p_desc = tu_desc_next(p_desc);
+        }
+      }
+#endif// CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+      {
+        uint8_t const *p_desc = _audiod_fct[i].p_desc;
+        uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+        // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+        while (p_desc_end - p_desc > 0) {
+          // For each endpoint
+          if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) {
+            tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+            uint8_t const ep_addr = desc_ep->bEndpointAddress;
+            // If endpoint is input-direction and interrupt-type
+            if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.xfer == TUSB_XFER_INTERRUPT) {
+              // Store endpoint number and open endpoint
+              _audiod_fct[i].ep_int = ep_addr;
+              TU_ASSERT(usbd_edpt_open(_audiod_fct[i].rhport, desc_ep));
+            }
+          }
+          p_desc = tu_desc_next(p_desc);
+        }
+      }
+#endif
+
+      _audiod_fct[i].mounted = true;
       break;
     }
   }
 
   // Verify we found a free one
-  TU_ASSERT( i < CFG_TUD_AUDIO );
+  TU_ASSERT(i < CFG_TUD_AUDIO);
 
   // This is all we need so far - the EPs are setup by a later set_interface request (as per UAC2 specification)
-  uint16_t drv_len = _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;    // - TUD_AUDIO_DESC_IAD_LEN since tinyUSB already handles the IAD descriptor
+  uint16_t drv_len = _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;// - TUD_AUDIO_DESC_IAD_LEN since tinyUSB already handles the IAD descriptor
 
   return drv_len;
 }
 
-static bool audiod_get_interface(uint8_t rhport, tusb_control_request_t const * p_request)
-{
+static bool audiod_get_interface(uint8_t rhport, tusb_control_request_t const *p_request) {
   uint8_t const itf = tu_u16_low(p_request->wIndex);
 
   // Find index of audio streaming interface
@@ -1503,8 +1752,7 @@ static bool audiod_get_interface(uint8_t rhport, tusb_control_request_t const *
   return true;
 }
 
-static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * p_request)
-{
+static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p_request) {
   (void) rhport;
 
   // Here we need to do the following:
@@ -1528,62 +1776,69 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   uint8_t const *p_desc;
   TU_VERIFY(audiod_get_AS_interface_index_global(itf, &func_id, &idxItf, &p_desc));
 
-  audiod_function_t* audio = &_audiod_fct[func_id];
+  audiod_function_t *audio = &_audiod_fct[func_id];
 
-  // Look if there is an EP to be closed - for this driver, there are only 3 possible EPs which may be closed (only AS related EPs can be closed, AC EP (if present) is always open)
+// Look if there is an EP to be closed - for this driver, there are only 3 possible EPs which may be closed (only AS related EPs can be closed, AC EP (if present) is always open)
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
-  if (audio->ep_in_as_intf_num == itf)
-  {
+  if (audio->ep_in_as_intf_num == itf) {
     audio->ep_in_as_intf_num = 0;
+  #ifndef TUP_DCD_EDPT_ISO_ALLOC
     usbd_edpt_close(rhport, audio->ep_in);
+  #endif
 
     // Clear FIFOs, since data is no longer valid
-#if !CFG_TUD_AUDIO_ENABLE_ENCODING
+  #if !CFG_TUD_AUDIO_ENABLE_ENCODING
     tu_fifo_clear(&audio->ep_in_ff);
-#else
-    for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
-    {
+  #else
+    for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++) {
       tu_fifo_clear(&audio->tx_supp_ff[cnt]);
     }
-#endif
+  #endif
 
     // Invoke callback - can be used to stop data sampling
-    if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
+    TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
 
-    audio->ep_in = 0;                           // Necessary?
+    audio->ep_in = 0;// Necessary?
 
+  #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+    audio->packet_sz_tx[0] = 0;
+    audio->packet_sz_tx[1] = 0;
+    audio->packet_sz_tx[2] = 0;
+  #endif
   }
-#endif
+#endif// CFG_TUD_AUDIO_ENABLE_EP_IN
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-  if (audio->ep_out_as_intf_num == itf)
-  {
+  if (audio->ep_out_as_intf_num == itf) {
     audio->ep_out_as_intf_num = 0;
+  #ifndef TUP_DCD_EDPT_ISO_ALLOC
     usbd_edpt_close(rhport, audio->ep_out);
+  #endif
 
     // Clear FIFOs, since data is no longer valid
-#if !CFG_TUD_AUDIO_ENABLE_DECODING
+  #if !CFG_TUD_AUDIO_ENABLE_DECODING
     tu_fifo_clear(&audio->ep_out_ff);
-#else
-    for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++)
-    {
+  #else
+    for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++) {
       tu_fifo_clear(&audio->rx_supp_ff[cnt]);
     }
-#endif
+  #endif
 
     // Invoke callback - can be used to stop data sampling
-    if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
+    TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
 
-    audio->ep_out = 0;                          // Necessary?
+    audio->ep_out = 0;// Necessary?
 
     // Close corresponding feedback EP
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+    #ifndef TUP_DCD_EDPT_ISO_ALLOC
     usbd_edpt_close(rhport, audio->ep_fb);
+    #endif
     audio->ep_fb = 0;
     tu_memclr(&audio->feedback, sizeof(audio->feedback));
-#endif
+  #endif
   }
-#endif
+#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT
 
   // Save current alternative interface setting
   audio->alt_setting[idxItf] = alt;
@@ -1593,30 +1848,31 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   uint8_t const *p_desc_end = audio->p_desc + audio->desc_length - TUD_AUDIO_DESC_IAD_LEN;
 
   // p_desc starts at required interface with alternate setting zero
-  while (p_desc < p_desc_end)
-  {
+  // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+  while (p_desc_end - p_desc > 0) {
     // Find correct interface
-    if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == alt)
-    {
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
-      uint8_t const * p_desc_parse_for_params = p_desc;
+    if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const *) p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const *) p_desc)->bAlternateSetting == alt) {
+#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING)
+      uint8_t const *p_desc_parse_for_params = p_desc;
 #endif
       // From this point forward follow the EP descriptors associated to the current alternate setting interface - Open EPs if necessary
-      uint8_t foundEPs = 0, nEps = ((tusb_desc_interface_t const * )p_desc)->bNumEndpoints;
-      while (foundEPs < nEps && p_desc < p_desc_end)
-      {
-        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
-        {
-          tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+      uint8_t foundEPs = 0, nEps = ((tusb_desc_interface_t const *) p_desc)->bNumEndpoints;
+      // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+      while (foundEPs < nEps && (p_desc_end - p_desc > 0)) {
+        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) {
+          tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+          TU_ASSERT(usbd_edpt_iso_activate(rhport, desc_ep));
+#else
           TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
-
+#endif
           uint8_t const ep_addr = desc_ep->bEndpointAddress;
 
           //TODO: We need to set EP non busy since this is not taken care of right now in ep_close() - THIS IS A WORKAROUND!
           usbd_edpt_clear_stall(rhport, ep_addr);
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
-          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 0x00)   // Check if usage is data EP
+          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 0x00)// Check if usage is data EP
           {
             // Save address
             audio->ep_in = ep_addr;
@@ -1624,71 +1880,65 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             audio->ep_in_sz = tu_edpt_packet_size(desc_ep);
 
             // If software encoding is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters
-#if CFG_TUD_AUDIO_ENABLE_ENCODING
+  #if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
             audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf);
 
-            // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
-            const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / audio->n_bytes_per_sampe_tx) * audio->n_bytes_per_sampe_tx);
-            for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
-            {
+              // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
+    #if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+            const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / (audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx)) * (audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx));
+            for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++) {
               tu_fifo_config(&audio->tx_supp_ff[cnt], audio->tx_supp_ff[cnt].buffer, active_fifo_depth, 1, true);
             }
             audio->n_ff_used_tx = audio->n_channels_tx / audio->n_channels_per_ff_tx;
-            TU_ASSERT( audio->n_ff_used_tx <= audio->n_tx_supp_ff );
-#endif
-
-#endif
+            TU_ASSERT(audio->n_ff_used_tx <= audio->n_tx_supp_ff);
+    #endif
+  #endif
 
             // Schedule first transmit if alternate interface is not zero i.e. streaming is disabled - in case no sample data is available a ZLP is loaded
             // It is necessary to trigger this here since the refill is done with an RX FIFO empty interrupt which can only trigger if something was in there
             TU_VERIFY(audiod_tx_done_cb(rhport, &_audiod_fct[func_id]));
           }
-#endif // CFG_TUD_AUDIO_ENABLE_EP_IN
+#endif// CFG_TUD_AUDIO_ENABLE_EP_IN
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
 
-          if (tu_edpt_dir(ep_addr) == TUSB_DIR_OUT)     // Checking usage not necessary
+          if (tu_edpt_dir(ep_addr) == TUSB_DIR_OUT)// Checking usage not necessary
           {
             // Save address
             audio->ep_out = ep_addr;
             audio->ep_out_as_intf_num = itf;
             audio->ep_out_sz = tu_edpt_packet_size(desc_ep);
 
-#if CFG_TUD_AUDIO_ENABLE_DECODING
+  #if CFG_TUD_AUDIO_ENABLE_DECODING
             audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf);
 
-            // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
-            const uint16_t active_fifo_depth = (audio->rx_supp_ff_sz_max / audio->n_bytes_per_sampe_rx) * audio->n_bytes_per_sampe_rx;
-            for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++)
-            {
+              // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
+    #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+            const uint16_t active_fifo_depth = (audio->rx_supp_ff_sz_max / audio->n_bytes_per_sample_rx) * audio->n_bytes_per_sample_rx;
+            for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++) {
               tu_fifo_config(&audio->rx_supp_ff[cnt], audio->rx_supp_ff[cnt].buffer, active_fifo_depth, 1, true);
             }
             audio->n_ff_used_rx = audio->n_channels_rx / audio->n_channels_per_ff_rx;
-            TU_ASSERT( audio->n_ff_used_rx <= audio->n_rx_supp_ff );
-#endif
-#endif
+            TU_ASSERT(audio->n_ff_used_rx <= audio->n_rx_supp_ff);
+    #endif
+  #endif
 
             // Prepare for incoming data
-#if USE_LINEAR_BUFFER_RX
+  #if USE_LINEAR_BUFFER_RX
             TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false);
-#else
+  #else
             TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_out, &audio->ep_out_ff, audio->ep_out_sz), false);
-#endif
+  #endif
           }
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1)   // Check if usage is explicit data feedback
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1)// Check if usage is explicit data feedback
           {
             audio->ep_fb = ep_addr;
-            audio->feedback.frame_shift = desc_ep->bInterval -1;
-
-            // Enable SOF interrupt if callback is implemented
-            if (tud_audio_feedback_interval_isr) usbd_sof_enable(rhport, true);
+            audio->feedback.frame_shift = desc_ep->bInterval - 1;
           }
-#endif
-#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
+  #endif
+#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT
 
           foundEPs += 1;
         }
@@ -1698,47 +1948,59 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
       TU_VERIFY(foundEPs == nEps);
 
       // Invoke one callback for a final set interface
-      if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+      TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-      // Prepare feedback computation if callback is available
-      if (tud_audio_feedback_params_cb)
-      {
+      // Prepare feedback computation if endpoint is available
+      if (audio->ep_fb != 0) {
         audio_feedback_params_t fb_param;
 
         tud_audio_feedback_params_cb(func_id, alt, &fb_param);
         audio->feedback.compute_method = fb_param.method;
 
-        // Minimal/Maximum value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
-        uint32_t const frame_div  = (TUSB_SPEED_FULL == tud_speed_get()) ? 1000 : 8000;
-        audio->feedback.min_value = (fb_param.sample_freq/frame_div - 1) << 16;
-        audio->feedback.max_value = (fb_param.sample_freq/frame_div + 1) << 16;
+        if (TUSB_SPEED_FULL == tud_speed_get())
+          audio->feedback.format_correction = tud_audio_feedback_format_correction_cb(func_id);
 
-        switch(fb_param.method)
-        {
+        // Minimal/Maximum value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
+        uint32_t const frame_div = (TUSB_SPEED_FULL == tud_speed_get()) ? 1000 : 8000;
+        audio->feedback.min_value = ((fb_param.sample_freq - 1) / frame_div) << 16;
+        audio->feedback.max_value = (fb_param.sample_freq / frame_div + 1) << 16;
+
+        switch (fb_param.method) {
           case AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED:
           case AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT:
           case AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2:
-            set_fb_params_freq(audio, fb_param.sample_freq, fb_param.frequency.mclk_freq);
-          break;
+            audiod_set_fb_params_freq(audio, fb_param.sample_freq, fb_param.frequency.mclk_freq);
+            break;
 
-          #if 0 // implement later
-          case AUDIO_FEEDBACK_METHOD_FIFO_COUNT:
-          {
-            uint64_t fb64 = ((uint64_t) fb_param.sample_freq) << 16;
-            audio->feedback.compute.fifo_count.nominal_value = (uint32_t) (fb64 / frame_div);
-            audio->feedback.compute.fifo_count.threshold_bytes = fb_param.fifo_count.threshold_bytes;
-
-            tud_audio_fb_set(audio->feedback.compute.fifo_count.nominal_value);
-          }
-          break;
-          #endif
+          case AUDIO_FEEDBACK_METHOD_FIFO_COUNT: {
+            // Initialize the threshold level to half filled
+            uint16_t fifo_lvl_thr;
+  #if CFG_TUD_AUDIO_ENABLE_DECODING
+            fifo_lvl_thr = tu_fifo_depth(&audio->rx_supp_ff[0]) / 2;
+  #else
+            fifo_lvl_thr = tu_fifo_depth(&audio->ep_out_ff) / 2;
+  #endif
+            audio->feedback.compute.fifo_count.fifo_lvl_thr = fifo_lvl_thr;
+            audio->feedback.compute.fifo_count.fifo_lvl_avg = ((uint32_t) fifo_lvl_thr) << 16;
+            // Avoid 64bit division
+            uint32_t nominal = ((fb_param.sample_freq / 100) << 16) / (frame_div / 100);
+            audio->feedback.compute.fifo_count.nom_value = nominal;
+            audio->feedback.compute.fifo_count.rate_const[0] = (uint16_t) ((audio->feedback.max_value - nominal) / fifo_lvl_thr);
+            audio->feedback.compute.fifo_count.rate_const[1] = (uint16_t) ((nominal - audio->feedback.min_value) / fifo_lvl_thr);
+            // On HS feedback is more sensitive since packet size can vary every MSOF, could cause instability
+            if (tud_speed_get() == TUSB_SPEED_HIGH) {
+              audio->feedback.compute.fifo_count.rate_const[0] /= 8;
+              audio->feedback.compute.fifo_count.rate_const[1] /= 8;
+            }
+          } break;
 
           // nothing to do
-          default: break;
+          default:
+            break;
         }
       }
-#endif
+#endif// CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
       // We are done - abort loop
       break;
@@ -1750,16 +2012,21 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
   // Disable SOF interrupt if no driver has any enabled feedback EP
-  bool disable = true;
-  for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
-  {
-    if (_audiod_fct[i].ep_fb != 0)
-    {
-      disable = false;
+  bool enable_sof = false;
+  for (uint8_t i = 0; i < CFG_TUD_AUDIO; i++) {
+    if (_audiod_fct[i].ep_fb != 0 &&
+        (_audiod_fct[i].feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED ||
+         _audiod_fct[i].feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT ||
+         _audiod_fct[i].feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2)) {
+      enable_sof = true;
       break;
     }
   }
-  if (disable) usbd_sof_enable(rhport, false);
+  usbd_sof_enable(rhport, SOF_CONSUMER_AUDIO, enable_sof);
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  audiod_calc_tx_packet_sz(audio);
 #endif
 
   tud_control_status(rhport, p_request);
@@ -1769,76 +2036,51 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 // Invoked when class request DATA stage is finished.
 // return false to stall control EP (e.g Host send non-sense DATA)
-static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const * p_request)
-{
+static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const *p_request) {
   // Handle audio class specific set requests
-  if(p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && p_request->bmRequestType_bit.direction == TUSB_DIR_OUT)
-  {
+  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && p_request->bmRequestType_bit.direction == TUSB_DIR_OUT) {
     uint8_t func_id;
 
-    switch (p_request->bmRequestType_bit.recipient)
-    {
-      case TUSB_REQ_RCPT_INTERFACE:
-      {
+    switch (p_request->bmRequestType_bit.recipient) {
+      case TUSB_REQ_RCPT_INTERFACE: {
         uint8_t itf = TU_U16_LOW(p_request->wIndex);
         uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
 
-        if (entityID != 0)
-        {
-          if (tud_audio_set_req_entity_cb)
-          {
-            // Check if entity is present and get corresponding driver index
-            TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
-
-            // Invoke callback
-            return tud_audio_set_req_entity_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
-          }
-          else
-          {
-            TU_LOG2("  No entity set request callback available!\r\n");
-            return false;     // In case no callback function is present or request can not be conducted we stall it
-          }
-        }
-        else
-        {
-          if (tud_audio_set_req_itf_cb)
-          {
-            // Find index of audio driver structure and verify interface really exists
-            TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
-
-            // Invoke callback
-            return tud_audio_set_req_itf_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
-          }
-          else
-          {
-            TU_LOG2("  No interface set request callback available!\r\n");
-            return false;     // In case no callback function is present or request can not be conducted we stall it
-          }
-        }
-      }
-      break;
-
-      case TUSB_REQ_RCPT_ENDPOINT:
-      {
-        uint8_t ep = TU_U16_LOW(p_request->wIndex);
-
-        if (tud_audio_set_req_ep_cb)
-        {
+        if (entityID != 0) {
           // Check if entity is present and get corresponding driver index
-          TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
+          TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
+
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+          uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+          if (_audiod_fct[func_id].bclock_id_tx == entityID && ctrlSel == AUDIO_CS_CTRL_SAM_FREQ && p_request->bRequest == AUDIO_CS_REQ_CUR) {
+            _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(_audiod_fct[func_id].ctrl_buf);
+          }
+#endif
 
           // Invoke callback
-          return tud_audio_set_req_ep_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
+          return tud_audio_set_req_entity_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
+        } else {
+          // Find index of audio driver structure and verify interface really exists
+          TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
+
+          // Invoke callback
+          return tud_audio_set_req_itf_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
         }
-        else
-        {
-          TU_LOG2("  No EP set request callback available!\r\n");
-          return false;   // In case no callback function is present or request can not be conducted we stall it
-        }
-      }
-      break;
+      } break;
+
+      case TUSB_REQ_RCPT_ENDPOINT: {
+        uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+        // Check if entity is present and get corresponding driver index
+        TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
+
+        // Invoke callback
+        return tud_audio_set_req_ep_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
+      } break;
       // Unknown/Unsupported recipient
-      default: TU_BREAKPOINT(); return false;
+      default:
+        TU_BREAKPOINT();
+        return false;
     }
   }
   return true;
@@ -1846,106 +2088,75 @@ static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const
 
 // Handle class control request
 // return false to stall control endpoint (e.g unsupported request)
-static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const * p_request)
-{
+static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const *p_request) {
   (void) rhport;
 
   // Handle standard requests - standard set requests usually have no data stage so we also handle set requests here
-  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD)
-  {
-    switch (p_request->bRequest)
-    {
+  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) {
+    switch (p_request->bRequest) {
       case TUSB_REQ_GET_INTERFACE:
         return audiod_get_interface(rhport, p_request);
 
       case TUSB_REQ_SET_INTERFACE:
         return audiod_set_interface(rhport, p_request);
 
-        // Unknown/Unsupported request
-      default: TU_BREAKPOINT(); return false;
+      case TUSB_REQ_CLEAR_FEATURE:
+        return true;
+
+      // Unknown/Unsupported request
+      default:
+        TU_BREAKPOINT();
+        return false;
     }
   }
 
   // Handle class requests
-  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS)
-  {
+  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS) {
     uint8_t itf = TU_U16_LOW(p_request->wIndex);
     uint8_t func_id;
 
     // Conduct checks which depend on the recipient
-    switch (p_request->bmRequestType_bit.recipient)
-    {
-      case TUSB_REQ_RCPT_INTERFACE:
-      {
+    switch (p_request->bmRequestType_bit.recipient) {
+      case TUSB_REQ_RCPT_INTERFACE: {
         uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
 
         // Verify if entity is present
-        if (entityID != 0)
-        {
+        if (entityID != 0) {
           // Find index of audio driver structure and verify entity really exists
           TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
 
           // In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
-          if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
-          {
-            if (tud_audio_get_req_entity_cb)
-            {
-              return tud_audio_get_req_entity_cb(rhport, p_request);
-            }
-            else
-            {
-              TU_LOG2("  No entity get request callback available!\r\n");
-              return false;   // Stall
-            }
+          if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN) {
+            return tud_audio_get_req_entity_cb(rhport, p_request);
           }
-        }
-        else
-        {
+        } else {
           // Find index of audio driver structure and verify interface really exists
           TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
 
           // In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
-          if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
-          {
-            if (tud_audio_get_req_itf_cb)
-            {
-              return tud_audio_get_req_itf_cb(rhport, p_request);
-            }
-            else
-            {
-              TU_LOG2("  No interface get request callback available!\r\n");
-              return false;   // Stall
-            }
+          if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN) {
+            return tud_audio_get_req_itf_cb(rhport, p_request);
           }
         }
-      }
-      break;
+      } break;
 
-      case TUSB_REQ_RCPT_ENDPOINT:
-      {
+      case TUSB_REQ_RCPT_ENDPOINT: {
         uint8_t ep = TU_U16_LOW(p_request->wIndex);
 
         // Find index of audio driver structure and verify EP really exists
         TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
 
         // In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
-        if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
-        {
-          if (tud_audio_get_req_ep_cb)
-          {
-            return tud_audio_get_req_ep_cb(rhport, p_request);
-          }
-          else
-          {
-            TU_LOG2("  No EP get request callback available!\r\n");
-            return false;     // Stall
-          }
+        if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN) {
+          return tud_audio_get_req_ep_cb(rhport, p_request);
         }
-      }
-      break;
+      } break;
 
       // Unknown/Unsupported recipient
-      default: TU_LOG2("  Unsupported recipient: %d\r\n", p_request->bmRequestType_bit.recipient); TU_BREAKPOINT(); return false;
+      default:
+        TU_LOG2("  Unsupported recipient: %d\r\n", p_request->bmRequestType_bit.recipient);
+        TU_BREAKPOINT();
+        return false;
     }
 
     // If we end here, the received request is a set request - we schedule a receive for the data stage and return true here. We handle the rest later in audiod_control_complete() once the data stage was finished
@@ -1958,35 +2169,28 @@ static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const
   return false;
 }
 
-bool audiod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
-  if ( stage == CONTROL_STAGE_SETUP )
-  {
+bool audiod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) {
+  if (stage == CONTROL_STAGE_SETUP) {
     return audiod_control_request(rhport, request);
-  }
-  else if ( stage == CONTROL_STAGE_DATA )
-  {
+  } else if (stage == CONTROL_STAGE_DATA) {
     return audiod_control_complete(rhport, request);
   }
 
   return true;
 }
 
-bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) result;
   (void) xferred_bytes;
 
   // Search for interface belonging to given end point address and proceed as required
-  for (uint8_t func_id = 0; func_id < CFG_TUD_AUDIO; func_id++)
-  {
-    audiod_function_t* audio = &_audiod_fct[func_id];
+  for (uint8_t func_id = 0; func_id < CFG_TUD_AUDIO; func_id++) {
+    audiod_function_t *audio = &_audiod_fct[func_id];
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
 
     // Data transmission of control interrupt finished
-    if (audio->ep_int_ctr == ep_addr)
-    {
+    if (audio->ep_int == ep_addr) {
       // According to USB2 specification, maximum payload of interrupt EP is 8 bytes on low speed, 64 bytes on full speed, and 1024 bytes on high speed (but only if an alternate interface other than 0 is used - see specification p. 49)
       // In case there is nothing to send we have to return a NAK - this is taken care of by PHY ???
       // In case of an erroneous transmission a retransmission is conducted - this is taken care of by PHY ???
@@ -1994,7 +2198,8 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
       // I assume here, that things above are handled by PHY
       // All transmission is done - what remains to do is to inform job was completed
 
-      if (tud_audio_int_ctr_done_cb) TU_VERIFY(tud_audio_int_ctr_done_cb(rhport, (uint16_t) xferred_bytes));
+      tud_audio_int_done_cb(rhport);
+      return true;
     }
 
 #endif
@@ -2002,8 +2207,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
 
     // Data transmission of audio packet finished
-    if (audio->ep_in == ep_addr && audio->alt_setting != 0)
-    {
+    if (audio->ep_in == ep_addr && audio->alt_setting != 0) {
       // USB 2.0, section 5.6.4, third paragraph, states "An isochronous endpoint must specify its required bus access period. However, an isochronous endpoint must be prepared to handle poll rates faster than the one specified."
       // That paragraph goes on to say "An isochronous IN endpoint must return a zero-length packet whenever data is requested at a faster interval than the specified interval and data is not available."
       // This can only be solved reliably if we load a ZLP after every IN transmission since we can not say if the host requests samples earlier than we declared! Once all samples are collected we overwrite the loaded ZLP.
@@ -2023,27 +2227,24 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
 
     // New audio packet received
-    if (audio->ep_out == ep_addr)
-    {
+    if (audio->ep_out == ep_addr) {
       TU_VERIFY(audiod_rx_done_cb(rhport, audio, (uint16_t) xferred_bytes));
       return true;
     }
 
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
     // Transmission of feedback EP finished
-    if (audio->ep_fb == ep_addr)
-    {
-      if (tud_audio_fb_done_cb) tud_audio_fb_done_cb(func_id);
+    if (audio->ep_fb == ep_addr) {
+      tud_audio_fb_done_cb(func_id);
 
-      // Schedule a transmit with the new value if EP is not busy 
-      if (!usbd_edpt_busy(rhport, audio->ep_fb))
-      {
+      // Schedule a transmit with the new value if EP is not busy
+      if (usbd_edpt_claim(rhport, audio->ep_fb)) {
         // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent
-        return audiod_fb_send(rhport, audio);
+        return audiod_fb_send(audio);
       }
     }
-#endif
+  #endif
 #endif
   }
 
@@ -2052,8 +2253,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq)
-{
+static bool audiod_set_fb_params_freq(audiod_function_t *audio, uint32_t sample_freq, uint32_t mclk_freq) {
   // Check if frame interval is within sane limits
   // The interval value n_frames was taken from the descriptors within audiod_set_interface()
 
@@ -2062,23 +2262,19 @@ static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, u
   uint32_t const k = (TUSB_SPEED_FULL == tud_speed_get()) ? 10 : 13;
   uint32_t const n_frame = (1UL << audio->feedback.frame_shift);
 
-  if ( (((1UL << k) * sample_freq / mclk_freq) + 1) > n_frame )
-  {
-    TU_LOG1("  UAC2 feedback interval too small\r\n"); TU_BREAKPOINT(); return false;
+  if ((((1UL << k) * sample_freq / mclk_freq) + 1) > n_frame) {
+    TU_LOG1("  UAC2 feedback interval too small\r\n");
+    TU_BREAKPOINT();
+    return false;
   }
 
   // Check if parameters really allow for a power of two division
-  if ((mclk_freq % sample_freq) == 0 && tu_is_power_of_two(mclk_freq / sample_freq))
-  {
-    audio->feedback.compute_method     = AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2;
-    audio->feedback.compute.power_of_2 = 16 - audio->feedback.frame_shift - tu_log2(mclk_freq / sample_freq);
-  }
-  else if ( audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT)
-  {
-    audio->feedback.compute.float_const = (float)sample_freq / mclk_freq * (1UL << (16 - audio->feedback.frame_shift));
-  }
-  else
-  {
+  if ((mclk_freq % sample_freq) == 0 && tu_is_power_of_two(mclk_freq / sample_freq)) {
+    audio->feedback.compute_method = AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2;
+    audio->feedback.compute.power_of_2 = (uint8_t) (16 - (audio->feedback.frame_shift - 1) - tu_log2(mclk_freq / sample_freq));
+  } else if (audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT) {
+    audio->feedback.compute.float_const = (float) sample_freq / (float) mclk_freq * (1UL << (16 - (audio->feedback.frame_shift - 1)));
+  } else {
     audio->feedback.compute.fixed.sample_freq = sample_freq;
     audio->feedback.compute.fixed.mclk_freq = mclk_freq;
   }
@@ -2086,46 +2282,83 @@ static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, u
   return true;
 }
 
-uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
-{
-  audiod_function_t* audio = &_audiod_fct[func_id];
+static void audiod_fb_fifo_count_update(audiod_function_t *audio, uint16_t lvl_new) {
+  /* Low-pass (averaging) filter */
+  uint32_t lvl = audio->feedback.compute.fifo_count.fifo_lvl_avg;
+  lvl = (uint32_t) (((uint64_t) lvl * 63 + ((uint32_t) lvl_new << 16)) >> 6);
+  audio->feedback.compute.fifo_count.fifo_lvl_avg = lvl;
+
+  uint32_t const ff_lvl = lvl >> 16;
+  uint16_t const ff_thr = audio->feedback.compute.fifo_count.fifo_lvl_thr;
+  uint16_t const *rate = audio->feedback.compute.fifo_count.rate_const;
+
   uint32_t feedback;
 
-  switch (audio->feedback.compute_method)
-  {
+  if (ff_lvl < ff_thr) {
+    feedback = audio->feedback.compute.fifo_count.nom_value + (ff_thr - ff_lvl) * rate[0];
+  } else {
+    feedback = audio->feedback.compute.fifo_count.nom_value - (ff_lvl - ff_thr) * rate[1];
+  }
+
+  if (feedback > audio->feedback.max_value) feedback = audio->feedback.max_value;
+  if (feedback < audio->feedback.min_value) feedback = audio->feedback.min_value;
+  audio->feedback.value = feedback;
+
+  // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value
+  if (usbd_edpt_claim(audio->rhport, audio->ep_fb)) {
+    audiod_fb_send(audio);
+  }
+}
+
+uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles) {
+  audiod_function_t *audio = &_audiod_fct[func_id];
+  uint32_t feedback;
+
+  switch (audio->feedback.compute_method) {
     case AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2:
       feedback = (cycles << audio->feedback.compute.power_of_2);
-    break;
+      break;
 
     case AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT:
       feedback = (uint32_t) ((float) cycles * audio->feedback.compute.float_const);
-    break;
+      break;
 
-    case AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED:
-    {
-      uint64_t fb64 = (((uint64_t) cycles) * audio->feedback.compute.fixed.sample_freq) << (16 - audio->feedback.frame_shift);
+    case AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED: {
+      uint64_t fb64 = (((uint64_t) cycles) * audio->feedback.compute.fixed.sample_freq) << (16 - (audio->feedback.frame_shift - 1));
       feedback = (uint32_t) (fb64 / audio->feedback.compute.fixed.mclk_freq);
-    }
-    break;
+    } break;
 
-    default: return 0;
+    default:
+      return 0;
   }
 
   // For Windows: https://docs.microsoft.com/en-us/windows-hardware/drivers/audio/usb-2-0-audio-drivers
   // The size of isochronous packets created by the device must be within the limits specified in FMT-2.0 section 2.3.1.1.
   // This means that the deviation of actual packet size from nominal size must not exceed +/- one audio slot
   // (audio slot = channel count samples).
-  if ( feedback > audio->feedback.max_value ) feedback = audio->feedback.max_value;
-  if ( feedback < audio->feedback.min_value ) feedback = audio->feedback.min_value;
+  if (feedback > audio->feedback.max_value) feedback = audio->feedback.max_value;
+  if (feedback < audio->feedback.min_value) feedback = audio->feedback.min_value;
 
   tud_audio_n_fb_set(func_id, feedback);
 
   return feedback;
 }
+
+bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback) {
+  TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
+
+  _audiod_fct[func_id].feedback.value = feedback;
+
+  // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value
+  if (usbd_edpt_claim(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_fb)) {
+    return audiod_fb_send(&_audiod_fct[func_id]);
+  }
+
+  return true;
+}
 #endif
 
-TU_ATTR_FAST_FUNC void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
-{
+TU_ATTR_FAST_FUNC void audiod_sof_isr(uint8_t rhport, uint32_t frame_count) {
   (void) rhport;
   (void) frame_count;
 
@@ -2137,26 +2370,22 @@ TU_ATTR_FAST_FUNC void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
   // feedback = n_cycles / n_frames * f_s / f_m in 16.16 format, where n_cycles are the number of main clock cycles within fb_n_frames
 
   // Iterate over audio functions and set feedback value
-  for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
-  {
-    audiod_function_t* audio = &_audiod_fct[i];
+  for (uint8_t i = 0; i < CFG_TUD_AUDIO; i++) {
+    audiod_function_t *audio = &_audiod_fct[i];
 
-    if (audio->ep_fb != 0)
-    {
+    if (audio->ep_fb != 0) {
       // HS shift need to be adjusted since SOF event is generated for frame only
       uint8_t const hs_adjust = (TUSB_SPEED_HIGH == tud_speed_get()) ? 3 : 0;
       uint32_t const interval = 1UL << (audio->feedback.frame_shift - hs_adjust);
-      if ( 0 == (frame_count & (interval-1)) )
-      {
-        if(tud_audio_feedback_interval_isr) tud_audio_feedback_interval_isr(i, frame_count, audio->feedback.frame_shift);
+      if (0 == (frame_count & (interval - 1))) {
+        tud_audio_feedback_interval_isr(i, frame_count, audio->feedback.frame_shift);
       }
     }
   }
-#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 }
 
-bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_request_t const * p_request, void* data, uint16_t len)
-{
+bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_request_t const *p_request, void *data, uint16_t len) {
   // Handles only sending of data not receiving
   if (p_request->bmRequestType_bit.direction == TUSB_DIR_OUT) return false;
 
@@ -2165,71 +2394,73 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req
   uint8_t itf = TU_U16_LOW(p_request->wIndex);
 
   // Conduct checks which depend on the recipient
-  switch (p_request->bmRequestType_bit.recipient)
-  {
-    case TUSB_REQ_RCPT_INTERFACE:
-    {
+  switch (p_request->bmRequestType_bit.recipient) {
+    case TUSB_REQ_RCPT_INTERFACE: {
       uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
 
       // Verify if entity is present
-      if (entityID != 0)
-      {
+      if (entityID != 0) {
         // Find index of audio driver structure and verify entity really exists
         TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
-      }
-      else
-      {
+      } else {
         // Find index of audio driver structure and verify interface really exists
         TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
       }
-    }
-    break;
+    } break;
 
-    case TUSB_REQ_RCPT_ENDPOINT:
-    {
+    case TUSB_REQ_RCPT_ENDPOINT: {
       uint8_t ep = TU_U16_LOW(p_request->wIndex);
 
       // Find index of audio driver structure and verify EP really exists
       TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
-    }
-    break;
+    } break;
 
     // Unknown/Unsupported recipient
-    default: TU_LOG2("  Unsupported recipient: %d\r\n", p_request->bmRequestType_bit.recipient); TU_BREAKPOINT(); return false;
+    default:
+      TU_LOG2("  Unsupported recipient: %d\r\n", p_request->bmRequestType_bit.recipient);
+      TU_BREAKPOINT();
+      return false;
   }
 
   // Crop length
   if (len > _audiod_fct[func_id].ctrl_buf_sz) len = _audiod_fct[func_id].ctrl_buf_sz;
 
   // Copy into buffer
-  memcpy((void *)_audiod_fct[func_id].ctrl_buf, data, (size_t)len);
+  TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, _audiod_fct[func_id].ctrl_buf_sz, data, (size_t) len));
+
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  // Find data for sampling_frequency_control
+  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && p_request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE) {
+    uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+    uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+    if (_audiod_fct[func_id].bclock_id_tx == entityID && ctrlSel == AUDIO_CS_CTRL_SAM_FREQ && p_request->bRequest == AUDIO_CS_REQ_CUR) {
+      _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(_audiod_fct[func_id].ctrl_buf);
+    }
+  }
+#endif
 
   // Schedule transmit
-  return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len);
+  return tud_control_xfer(rhport, p_request, (void *) _audiod_fct[func_id].ctrl_buf, len);
 }
 
 // This helper function finds for a given audio function and AS interface number the index of the attached driver structure, the index of the interface in the audio function
 // (e.g. the std. AS interface with interface number 15 is the first AS interface for the given audio function and thus gets index zero), and
 // finally a pointer to the std. AS interface, where the pointer always points to the first alternate setting i.e. alternate interface zero.
-static bool audiod_get_AS_interface_index(uint8_t itf, audiod_function_t * audio, uint8_t *idxItf, uint8_t const **pp_desc_int)
-{
-  if (audio->p_desc)
-  {
+static bool audiod_get_AS_interface_index(uint8_t itf, audiod_function_t *audio, uint8_t *idxItf, uint8_t const **pp_desc_int) {
+  if (audio->p_desc) {
     // Get pointer at end
     uint8_t const *p_desc_end = audio->p_desc + audio->desc_length - TUD_AUDIO_DESC_IAD_LEN;
 
     // Advance past AC descriptors
     uint8_t const *p_desc = tu_desc_next(audio->p_desc);
-    p_desc += ((audio_desc_cs_ac_interface_t const *)p_desc)->wTotalLength;
+    p_desc += ((audio_desc_cs_ac_interface_t const *) p_desc)->wTotalLength;
 
     uint8_t tmp = 0;
-    while (p_desc < p_desc_end)
-    {
+    // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+    while (p_desc_end - p_desc > 0) {
       // We assume the number of alternate settings is increasing thus we return the index of alternate setting zero!
-      if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == 0)
-      {
-        if (((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf)
-        {
+      if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const *) p_desc)->bAlternateSetting == 0) {
+        if (((tusb_desc_interface_t const *) p_desc)->bInterfaceNumber == itf) {
           *idxItf = tmp;
           *pp_desc_int = p_desc;
           return true;
@@ -2246,14 +2477,11 @@ static bool audiod_get_AS_interface_index(uint8_t itf, audiod_function_t * audio
 // This helper function finds for a given AS interface number the index of the attached driver structure, the index of the interface in the audio function
 // (e.g. the std. AS interface with interface number 15 is the first AS interface for the given audio function and thus gets index zero), and
 // finally a pointer to the std. AS interface, where the pointer always points to the first alternate setting i.e. alternate interface zero.
-static bool audiod_get_AS_interface_index_global(uint8_t itf, uint8_t *func_id, uint8_t *idxItf, uint8_t const **pp_desc_int)
-{
+static bool audiod_get_AS_interface_index_global(uint8_t itf, uint8_t *func_id, uint8_t *idxItf, uint8_t const **pp_desc_int) {
   // Loop over audio driver interfaces
   uint8_t i;
-  for (i = 0; i < CFG_TUD_AUDIO; i++)
-  {
-    if (audiod_get_AS_interface_index(itf, &_audiod_fct[i], idxItf, pp_desc_int))
-    {
+  for (i = 0; i < CFG_TUD_AUDIO; i++) {
+    if (audiod_get_AS_interface_index(itf, &_audiod_fct[i], idxItf, pp_desc_int)) {
       *func_id = i;
       return true;
     }
@@ -2263,22 +2491,19 @@ static bool audiod_get_AS_interface_index_global(uint8_t itf, uint8_t *func_id,
 }
 
 // Verify an entity with the given ID exists and returns also the corresponding driver index
-static bool audiod_verify_entity_exists(uint8_t itf, uint8_t entityID, uint8_t *func_id)
-{
+static bool audiod_verify_entity_exists(uint8_t itf, uint8_t entityID, uint8_t *func_id) {
   uint8_t i;
-  for (i = 0; i < CFG_TUD_AUDIO; i++)
-  {
+  for (i = 0; i < CFG_TUD_AUDIO; i++) {
     // Look for the correct driver by checking if the unique standard AC interface number fits
-    if (_audiod_fct[i].p_desc && ((tusb_desc_interface_t const *)_audiod_fct[i].p_desc)->bInterfaceNumber == itf)
-    {
+    if (_audiod_fct[i].p_desc && ((tusb_desc_interface_t const *) _audiod_fct[i].p_desc)->bInterfaceNumber == itf) {
       // Get pointers after class specific AC descriptors and end of AC descriptors - entities are defined in between
-      uint8_t const *p_desc = tu_desc_next(_audiod_fct[i].p_desc);                                          // Points to CS AC descriptor
-      uint8_t const *p_desc_end = ((audio_desc_cs_ac_interface_t const *)p_desc)->wTotalLength + p_desc;
-      p_desc = tu_desc_next(p_desc);                                                                            // Get past CS AC descriptor
+      uint8_t const *p_desc = tu_desc_next(_audiod_fct[i].p_desc);// Points to CS AC descriptor
+      uint8_t const *p_desc_end = ((audio_desc_cs_ac_interface_t const *) p_desc)->wTotalLength + p_desc;
+      p_desc = tu_desc_next(p_desc);// Get past CS AC descriptor
 
-      while (p_desc < p_desc_end)
-      {
-        if (p_desc[3] == entityID)  // Entity IDs are always at offset 3
+      // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+      while (p_desc_end - p_desc > 0) {
+        if (p_desc[3] == entityID)// Entity IDs are always at offset 3
         {
           *func_id = i;
           return true;
@@ -2290,21 +2515,16 @@ static bool audiod_verify_entity_exists(uint8_t itf, uint8_t entityID, uint8_t *
   return false;
 }
 
-static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id)
-{
+static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id) {
   uint8_t i;
-  for (i = 0; i < CFG_TUD_AUDIO; i++)
-  {
-    if (_audiod_fct[i].p_desc)
-    {
+  for (i = 0; i < CFG_TUD_AUDIO; i++) {
+    if (_audiod_fct[i].p_desc) {
       // Get pointer at beginning and end
       uint8_t const *p_desc = _audiod_fct[i].p_desc;
       uint8_t const *p_desc_end = _audiod_fct[i].p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
-
-      while (p_desc < p_desc_end)
-      {
-        if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const *)_audiod_fct[i].p_desc)->bInterfaceNumber == itf)
-        {
+      // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+      while (p_desc_end - p_desc > 0) {
+        if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const *) _audiod_fct[i].p_desc)->bInterfaceNumber == itf) {
           *func_id = i;
           return true;
         }
@@ -2315,24 +2535,20 @@ static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id)
   return false;
 }
 
-static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id)
-{
+static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id) {
   uint8_t i;
-  for (i = 0; i < CFG_TUD_AUDIO; i++)
-  {
-    if (_audiod_fct[i].p_desc)
-    {
+  for (i = 0; i < CFG_TUD_AUDIO; i++) {
+    if (_audiod_fct[i].p_desc) {
       // Get pointer at end
       uint8_t const *p_desc_end = _audiod_fct[i].p_desc + _audiod_fct[i].desc_length;
 
       // Advance past AC descriptors - EP we look for are streaming EPs
       uint8_t const *p_desc = tu_desc_next(_audiod_fct[i].p_desc);
-      p_desc += ((audio_desc_cs_ac_interface_t const *)p_desc)->wTotalLength;
+      p_desc += ((audio_desc_cs_ac_interface_t const *) p_desc)->wTotalLength;
 
-      while (p_desc < p_desc_end)
-      {
-        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT && ((tusb_desc_endpoint_t const * )p_desc)->bEndpointAddress == ep)
-        {
+      // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+      while (p_desc_end - p_desc > 0) {
+        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT && ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress == ep) {
           *func_id = i;
           return true;
         }
@@ -2343,85 +2559,77 @@ static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id)
   return false;
 }
 
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
+#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING)
 // p_desc points to the AS interface of alternate setting zero
 // itf is the interface number of the corresponding interface - we check if the interface belongs to EP in or EP out to see if it is a TX or RX parameter
 // Currently, only AS interfaces with an EP (in or out) are supposed to be parsed for!
-static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * p_desc, uint8_t const * p_desc_end, uint8_t const as_itf)
-{
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
-  if (as_itf != audio->ep_in_as_intf_num && as_itf != audio->ep_out_as_intf_num) return;           // Abort, this interface has no EP, this driver does not support this currently
-#endif
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_EP_OUT
+static void audiod_parse_for_AS_params(audiod_function_t *audio, uint8_t const *p_desc, uint8_t const *p_desc_end, uint8_t const as_itf) {
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
+  if (as_itf != audio->ep_in_as_intf_num && as_itf != audio->ep_out_as_intf_num) return;// Abort, this interface has no EP, this driver does not support this currently
+  #endif
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_EP_OUT
   if (as_itf != audio->ep_in_as_intf_num) return;
-#endif
-#if !CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
+  #endif
+  #if !CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
   if (as_itf != audio->ep_out_as_intf_num) return;
-#endif
+  #endif
 
-  p_desc = tu_desc_next(p_desc);    // Exclude standard AS interface descriptor of current alternate interface descriptor
-
-  while (p_desc < p_desc_end)
-  {
+  p_desc = tu_desc_next(p_desc);// Exclude standard AS interface descriptor of current alternate interface descriptor
+  // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+  while (p_desc_end - p_desc > 0) {
     // Abort if follow up descriptor is a new standard interface descriptor - indicates the last AS descriptor was already finished
     if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) break;
 
     // Look for a Class-Specific AS Interface Descriptor(4.9.2) to verify format type and format and also to get number of physical channels
-    if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_AS_GENERAL)
-    {
-#if CFG_TUD_AUDIO_ENABLE_EP_IN
-      if (as_itf == audio->ep_in_as_intf_num)
-      {
-        audio->n_channels_tx = ((audio_desc_cs_as_interface_t const * )p_desc)->bNrChannels;
-        audio->format_type_tx = (audio_format_type_t)(((audio_desc_cs_as_interface_t const * )p_desc)->bFormatType);
+    if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_AS_GENERAL) {
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN
+      if (as_itf == audio->ep_in_as_intf_num) {
+        audio->n_channels_tx = ((audio_desc_cs_as_interface_t const *) p_desc)->bNrChannels;
+        audio->format_type_tx = (audio_format_type_t) (((audio_desc_cs_as_interface_t const *) p_desc)->bFormatType);
 
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
-        audio->format_type_I_tx = (audio_data_format_type_I_t)(((audio_desc_cs_as_interface_t const * )p_desc)->bmFormats);
-#endif
+    #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+        audio->format_type_I_tx = (audio_data_format_type_I_t) (((audio_desc_cs_as_interface_t const *) p_desc)->bmFormats);
+    #endif
       }
-#endif
+  #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
-      if (as_itf == audio->ep_out_as_intf_num)
-      {
-        audio->n_channels_rx = ((audio_desc_cs_as_interface_t const * )p_desc)->bNrChannels;
-        audio->format_type_rx = ((audio_desc_cs_as_interface_t const * )p_desc)->bFormatType;
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
-        audio->format_type_I_rx = ((audio_desc_cs_as_interface_t const * )p_desc)->bmFormats;
-#endif
+  #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
+      if (as_itf == audio->ep_out_as_intf_num) {
+        audio->n_channels_rx = ((audio_desc_cs_as_interface_t const *) p_desc)->bNrChannels;
+        audio->format_type_rx = ((audio_desc_cs_as_interface_t const *) p_desc)->bFormatType;
+    #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+        audio->format_type_I_rx = ((audio_desc_cs_as_interface_t const *) p_desc)->bmFormats;
+    #endif
       }
-#endif
+  #endif
     }
 
     // Look for a Type I Format Type Descriptor(2.3.1.6 - Audio Formats)
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING || CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
-    if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_FORMAT_TYPE && ((audio_desc_type_I_format_t const * )p_desc)->bFormatType == AUDIO_FORMAT_TYPE_I)
-    {
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
-      if (as_itf != audio->ep_in_as_intf_num && as_itf != audio->ep_out_as_intf_num) break;           // Abort loop, this interface has no EP, this driver does not support this currently
-#endif
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_EP_OUT
+  #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+    if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_FORMAT_TYPE && ((audio_desc_type_I_format_t const *) p_desc)->bFormatType == AUDIO_FORMAT_TYPE_I) {
+    #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
+      if (as_itf != audio->ep_in_as_intf_num && as_itf != audio->ep_out_as_intf_num) break;// Abort loop, this interface has no EP, this driver does not support this currently
+    #endif
+    #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_EP_OUT
       if (as_itf != audio->ep_in_as_intf_num) break;
-#endif
-#if !CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
+    #endif
+    #if !CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
       if (as_itf != audio->ep_out_as_intf_num) break;
-#endif
+    #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_IN
-      if (as_itf == audio->ep_in_as_intf_num)
-      {
-        audio->n_bytes_per_sampe_tx = ((audio_desc_type_I_format_t const * )p_desc)->bSubslotSize;
+    #if CFG_TUD_AUDIO_ENABLE_EP_IN
+      if (as_itf == audio->ep_in_as_intf_num) {
+        audio->n_bytes_per_sample_tx = ((audio_desc_type_I_format_t const *) p_desc)->bSubslotSize;
       }
-#endif
+    #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
-      if (as_itf == audio->ep_out_as_intf_num)
-      {
-        audio->n_bytes_per_sampe_rx = ((audio_desc_type_I_format_t const * )p_desc)->bSubslotSize;
+    #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
+      if (as_itf == audio->ep_out_as_intf_num) {
+        audio->n_bytes_per_sample_rx = ((audio_desc_type_I_format_t const *) p_desc)->bSubslotSize;
       }
-#endif
+    #endif
     }
-#endif
+  #endif
 
     // Other format types are not supported yet
 
@@ -2430,50 +2638,87 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
 
-bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
-{
-  TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
+static bool audiod_calc_tx_packet_sz(audiod_function_t *audio) {
+  TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I);
+  TU_VERIFY(audio->n_channels_tx);
+  TU_VERIFY(audio->n_bytes_per_sample_tx);
+  TU_VERIFY(audio->interval_tx);
+  TU_VERIFY(audio->sample_rate_tx);
 
-  // Format the feedback value
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION
-  if ( TUSB_SPEED_FULL == tud_speed_get() )
-  {
-    uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].feedback.value;
+  const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1);
 
-    // For FS format is 10.14
-    *(fb++) = (feedback >> 2) & 0xFF;
-    *(fb++) = (feedback >> 10) & 0xFF;
-    *(fb++) = (feedback >> 18) & 0xFF;
-    // 4th byte is needed to work correctly with MS Windows
-    *fb = 0;
-  }else
-#else
-  {
-    // Send value as-is, caller will choose the appropriate format
-    _audiod_fct[func_id].feedback.value = feedback;
-  }
-#endif
+  const uint16_t sample_normimal = (uint16_t) (audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000));
+  const uint16_t sample_reminder = (uint16_t) (audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000));
 
-  // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value
-  if (!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_fb))
-  {
-    return audiod_fb_send(_audiod_fct[func_id].rhport, &_audiod_fct[func_id]);
+  const uint16_t packet_sz_tx_min = (uint16_t) ((sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sample_tx);
+  const uint16_t packet_sz_tx_norm = (uint16_t) (sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sample_tx);
+  const uint16_t packet_sz_tx_max = (uint16_t) ((sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sample_tx);
+
+  // Endpoint size must larger than packet size
+  TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);
+
+  // Frmt20.pdf 2.3.1.1 USB Packets
+  if (sample_reminder) {
+    // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots
+    audio->packet_sz_tx[0] = packet_sz_tx_norm;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
+  } else {
+    // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav)
+    // (medium VFP) and INT(nav)+1 (large VFP).
+    audio->packet_sz_tx[0] = packet_sz_tx_min;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
   }
 
   return true;
 }
+
+static uint16_t audiod_tx_packet_size(const uint16_t *norminal_size, uint16_t data_count, uint16_t fifo_depth, uint16_t max_depth) {
+  // Flow control need a FIFO size of at least 4*Navg
+  if (norminal_size[1] && norminal_size[1] <= fifo_depth * 4) {
+    // Use blackout to prioritize normal size packet
+    static int ctrl_blackout = 0;
+    uint16_t packet_size;
+    uint16_t slot_size = norminal_size[2] - norminal_size[1];
+    if (data_count < norminal_size[0]) {
+      // If you get here frequently, then your I2S clock deviation is too big !
+      packet_size = 0;
+    } else if (data_count < fifo_depth / 2 - slot_size && !ctrl_blackout) {
+      packet_size = norminal_size[0];
+      ctrl_blackout = 10;
+    } else if (data_count > fifo_depth / 2 + slot_size && !ctrl_blackout) {
+      packet_size = norminal_size[2];
+      if (norminal_size[0] == norminal_size[1]) {
+        // nav > INT(nav), eg. 44.1k, 88.2k
+        ctrl_blackout = 0;
+      } else {
+        // nav = INT(nav), eg. 48k, 96k
+        ctrl_blackout = 10;
+      }
+    } else {
+      packet_size = norminal_size[1];
+      if (ctrl_blackout) {
+        ctrl_blackout--;
+      }
+    }
+    // Normally this cap is not necessary
+    return tu_min16(packet_size, max_depth);
+  } else {
+    return tu_min16(data_count, max_depth);
+  }
+}
+
 #endif
 
 // No security checks here - internal function only which should always succeed
-uint8_t audiod_get_audio_fct_idx(audiod_function_t * audio)
-{
-  for (uint8_t cnt=0; cnt < CFG_TUD_AUDIO; cnt++)
-  {
+static uint8_t audiod_get_audio_fct_idx(audiod_function_t *audio) {
+  for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO; cnt++) {
     if (&_audiod_fct[cnt] == audio) return cnt;
   }
   return 0;
 }
 
-#endif //CFG_TUD_ENABLED && CFG_TUD_AUDIO
+#endif // (CFG_TUD_ENABLED && CFG_TUD_AUDIO)
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 0ef100fa4..0a7bff212 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -1,8 +1,9 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Ha Thach (tinyusb.org)
  * Copyright (c) 2020 Reinhard Panhuber
+ * Copyright (c) 2023 HiFiPhile
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -181,24 +182,29 @@
 #endif
 #endif
 
+// (For TYPE-I format only) Flow control is necessary to allow IN ep send correct amount of data, unless it's a virtual device where data is perfectly synchronized to USB clock.
+#ifndef CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL  1
+#endif
+
 // Enable/disable feedback EP (required for asynchronous RX applications)
 #ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP                    0                             // Feedback - 0 or 1
 #endif
 
 // Enable/disable conversion from 16.16 to 10.14 format on full-speed devices. See tud_audio_n_fb_set().
+// Can be override by tud_audio_feedback_format_correction_cb()
 #ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION     0                             // 0 or 1
 #endif
 
-// Audio interrupt control EP size - disabled if 0
-#ifndef CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-#define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     0                             // Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
+// Enable/disable interrupt EP (required for notifying host of control changes)
+#ifndef CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+#define CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP                   0                             // Feedback - 0 or 1
 #endif
 
-#ifndef CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE
-#define CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE          6                             // Buffer size of audio control interrupt EP - 6 Bytes according to UAC 2 specification (p. 74)
-#endif
+// Audio control interrupt EP - 6 Bytes according to UAC 2 specification (p. 74)
+#define CFG_TUD_AUDIO_INTERRUPT_EP_SZ                       6
 
 // Use software encoding/decoding
 
@@ -241,7 +247,8 @@
 // Enable encoding/decodings - for these to work, support FIFOs need to be setup in appropriate numbers and size
 // The actual coding parameters of active AS alternate interface is parsed from the descriptors
 
-// The item size of the FIFO is always fixed to one i.e. bytes! Furthermore, the actively used FIFO depth is reconfigured such that the depth is a multiple of the current sample size in order to avoid samples to get split up in case of a wrap in the FIFO ring buffer (depth = (max_depth / sampe_sz) * sampe_sz)!
+// The item size of the FIFO is always fixed to one i.e. bytes! Furthermore, the actively used FIFO depth is reconfigured such that the depth is a multiple
+// of the current sample size in order to avoid samples to get split up in case of a wrap in the FIFO ring buffer (depth = (max_depth / sample_sz) * sample_sz)!
 // This is important to remind in case you use DMAs! If the sample sizes changes, the DMA MUST BE RECONFIGURED just like the FIFOs for a different depth!!!
 
 // For PCM encoding/decoding
@@ -388,10 +395,11 @@ uint16_t tud_audio_n_write_support_ff             (uint8_t func_id, uint8_t ff_i
 tu_fifo_t* tud_audio_n_get_tx_support_ff          (uint8_t func_id, uint8_t ff_idx);
 #endif
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-uint16_t    tud_audio_int_ctr_n_write             (uint8_t func_id, uint8_t const* buffer, uint16_t len);
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+bool    tud_audio_int_n_write                     (uint8_t func_id, const audio_interrupt_data_t * data);
 #endif
 
+
 //--------------------------------------------------------------------+
 // Application API (Interface0)
 //--------------------------------------------------------------------+
@@ -431,8 +439,8 @@ static inline tu_fifo_t* tud_audio_get_tx_support_ff        (uint8_t ff_idx);
 
 // INT CTR API
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-static inline uint16_t tud_audio_int_ctr_write              (uint8_t const* buffer, uint16_t len);
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+static inline bool tud_audio_int_write                      (const audio_interrupt_data_t * data);
 #endif
 
 // Buffer control EP data and schedule a transmit
@@ -444,63 +452,80 @@ static inline uint16_t tud_audio_int_ctr_write              (uint8_t const* buff
 bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_request_t const * p_request, void* data, uint16_t len);
 
 //--------------------------------------------------------------------+
-// Application Callback API (weak is optional)
+// Application Callback API
 //--------------------------------------------------------------------+
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
-TU_ATTR_WEAK bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting);
-TU_ATTR_WEAK bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting);
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting);
+bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting);
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-TU_ATTR_WEAK bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting);
-TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting);
+bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting);
+bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting);
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-TU_ATTR_WEAK void tud_audio_fb_done_cb(uint8_t func_id);
+void tud_audio_fb_done_cb(uint8_t func_id);
 
 
-// determined by the user itself and set by use of tud_audio_n_fb_set(). The feedback value may be determined e.g. from some fill status of some FIFO buffer. Advantage: No ISR interrupt is enabled, hence the CPU need not to handle an ISR every 1ms or 125us and thus less CPU load, disadvantage: typically a larger FIFO is needed to compensate for jitter (e.g. 8 frames), i.e. a larger delay is introduced.
+// Note about feedback calculation
+//
+// Option 1 - AUDIO_FEEDBACK_METHOD_FIFO_COUNT
+// Feedback value is calculated within the audio driver by regulating the FIFO level to half fill.
+// Advantage: No ISR interrupt is enabled, hence the CPU need not to handle an ISR every 1ms or 125us and thus less CPU load, well tested
+// (Windows, Linux, OSX) with a reliable result so far.
+// Disadvantage: A FIFO of minimal 4 frames is needed to compensate for jitter, an average delay of 2 frames is introduced.
+//
+// Option 2 - AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED / AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT
+// Feedback value is calculated within the audio driver by use of SOF interrupt. The driver needs information about the master clock f_m from
+// which the audio sample frequency f_s is derived, f_s itself, and the cycle count of f_m at time of the SOF interrupt (e.g. by use of a hardware counter).
+// See tud_audio_set_fb_params() and tud_audio_feedback_update()
+// Advantage: Reduced jitter in the feedback value computation, hence, the receive FIFO can be smaller and thus a smaller delay is possible.
+// Disadvantage: higher CPU load due to SOF ISR handling every frame i.e. 1ms or 125us. (The most critical point is the reading of the cycle counter value of f_m.
+// It is read from within the SOF ISR - see: audiod_sof() -, hence, the ISR must has a high priority such that no software dependent "random" delay i.e. jitter is introduced).
+// Long-term drift could occur since error is accumulated.
+//
+// Option 3 - manual
+// Determined by the user itself and set by use of tud_audio_n_fb_set(). The feedback value may be determined e.g. from some fill status of some FIFO buffer.
+// Advantage: No ISR interrupt is enabled, hence the CPU need not to handle an ISR every 1ms or 125us and thus less CPU load.
+// Disadvantage: typically a larger FIFO is needed to compensate for jitter (e.g. 6 frames), i.e. a larger delay is introduced.
 
-// Feedback value is calculated within the audio driver by use of SOF interrupt. The driver needs information about the master clock f_m from which the audio sample frequency f_s is derived, f_s itself, and the cycle count of f_m at time of the SOF interrupt (e.g. by use of a hardware counter) - see tud_audio_set_fb_params(). Advantage: Reduced jitter in the feedback value computation, hence, the receive FIFO can be smaller (e.g. 2 frames) and thus a smaller delay is possible, disadvantage: higher CPU load due to SOF ISR handling every frame i.e. 1ms or 125us. This option is a great starting point to try the SOF ISR option but depending on your hardware setup (performance of the CPU) it might not work. If so, figure out why and use the next option. (The most critical point is the reading of the cycle counter value of f_m. It is read from within the SOF ISR - see: audiod_sof() -, hence, the ISR must has a high priority such that no software dependent "random" delay i.e. jitter is introduced).
-
-// Feedback value is determined by the user by use of SOF interrupt. The user may use tud_audio_sof_isr() which is called every SOF (of course only invoked when an alternate interface other than zero was set). The number of frames used to determine the feedback value for the currently active alternate setting can be get by tud_audio_get_fb_n_frames(). The feedback value must be set by use of tud_audio_n_fb_set().
 
 // This function is used to provide data rate feedback from an asynchronous sink. Feedback value will be sent at FB endpoint interval till it's changed.
 //
 // The feedback format is specified to be 16.16 for HS and 10.14 for FS devices (see Universal Serial Bus Specification Revision 2.0 5.12.4.2). By default,
-// the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set, then tinyusb
-// expects 16.16 format and handles the conversion to 10.14 on FS.
+// the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set or tud_audio_feedback_format_correction_cb()
+// return true, then tinyusb expects 16.16 format and handles the conversion to 10.14 on FS.
+//
+// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and it seems the
+// driver can work with either format.
 //
-// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the 
-// driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format.
-
 // Feedback value can be determined from within the SOF ISR of the audio driver. This should reduce jitter. If the feature is used, the user can not set the feedback value.
-
+//
 // Determine feedback value - The feedback method is described in 5.12.4.2 of the USB 2.0 spec
 // Boiled down, the feedback value Ff = n_samples / (micro)frame.
-// Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_m) frames need to be measured, where K = 10 for full speed and K = 13 for high speed, f_s is the sampling frequency e.g. 48 kHz and f_m is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
+// Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_m) frames need to be measured, where K = 10 for full speed and K = 13
+// for high speed, f_s is the sampling frequency e.g. 48 kHz and f_m is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
 // The update interval in the (4.10.2.1) Feedback Endpoint Descriptor must be less or equal to 2^(K - P), where P = min( ceil(log2(f_m / f_s)), K)
 // feedback = n_cycles / n_frames * f_s / f_m in 16.16 format, where n_cycles are the number of main clock cycles within fb_n_frames
-
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
-static inline bool tud_audio_fb_set(uint32_t feedback);
 
-// Update feedback value with passed cycles since last time this update function is called.
+// Update feedback value with passed MCLK cycles since last time this update function is called.
 // Typically called within tud_audio_sof_isr(). Required tud_audio_feedback_params_cb() is implemented
 // This function will also call tud_audio_feedback_set()
 // return feedback value in 16.16 for reference (0 for error)
+// Example :
+//   binterval=3 (4ms); FS = 48kHz; MCLK = 12.288MHz
+//   In 4 SOF MCLK counted 49152 cycles
 uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles);
 
 enum {
   AUDIO_FEEDBACK_METHOD_DISABLED,
   AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED,
   AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT,
-  AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2,
-
-  // impelemnt later
-  // AUDIO_FEEDBACK_METHOD_FIFO_COUNT
+  AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2, // For driver internal use only
+  AUDIO_FEEDBACK_METHOD_FIFO_COUNT
 };
 
 typedef struct {
@@ -512,52 +537,50 @@ typedef struct {
       uint32_t mclk_freq; // Main clock frequency in Hz i.e. master clock to which sample clock is based on
     }frequency;
 
-#if 0 // implement later
-    struct {
-      uint32_t threshold_bytes; // minimum number of bytes received to be considered as filled/ready
-    }fifo_count;
-#endif
   };
 }audio_feedback_params_t;
 
 // Invoked when needed to set feedback parameters
-TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param);
+void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param);
 
 // Callback in ISR context, invoked periodically according to feedback endpoint bInterval.
 // Could be used to compute and update feedback value, should be placed in RAM if possible
 // frame_number  : current SOF count
 // interval_shift: number of bit shift i.e log2(interval) from Feedback endpoint descriptor
-TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift);
+TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift);
 
+// (Full-Speed only) Callback to set feedback format correction is applied or not,
+// default to CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION if not implemented.
+bool tud_audio_feedback_format_correction_cb(uint8_t func_id);
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-TU_ATTR_WEAK bool tud_audio_int_ctr_done_cb(uint8_t rhport, uint16_t n_bytes_copied);
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+void tud_audio_int_done_cb(uint8_t rhport);
 #endif
 
 // Invoked when audio set interface request received
-TU_ATTR_WEAK bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request);
 
 // Invoked when audio set interface request received which closes an EP
-TU_ATTR_WEAK bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request);
 
 // Invoked when audio class specific set request received for an EP
-TU_ATTR_WEAK bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
+bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
 
 // Invoked when audio class specific set request received for an interface
-TU_ATTR_WEAK bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
+bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
 
 // Invoked when audio class specific set request received for an entity
-TU_ATTR_WEAK bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
 
 // Invoked when audio class specific get request received for an EP
-TU_ATTR_WEAK bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request);
 
 // Invoked when audio class specific get request received for an interface
-TU_ATTR_WEAK bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request);
 
 // Invoked when audio class specific get request received for an entity
-TU_ATTR_WEAK bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request);
 
 //--------------------------------------------------------------------+
 // Inline Functions
@@ -663,10 +686,10 @@ static inline tu_fifo_t* tud_audio_get_tx_support_ff(uint8_t ff_idx)
 
 #endif
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t len)
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+static inline bool tud_audio_int_write(const audio_interrupt_data_t * data)
 {
-  return tud_audio_int_ctr_n_write(0, buffer, len);
+  return tud_audio_int_n_write(0, data);
 }
 #endif
 
@@ -683,6 +706,7 @@ static inline bool tud_audio_fb_set(uint32_t feedback)
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     audiod_init           (void);
+bool     audiod_deinit         (void);
 void     audiod_reset          (uint8_t rhport);
 uint16_t audiod_open           (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     audiod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index f96bb3552..45cbf2d98 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -37,25 +37,29 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;
   uint8_t ep_ev;
   uint8_t ep_acl_in;
+  uint16_t ep_acl_in_pkt_sz;
   uint8_t ep_acl_out;
   uint8_t ep_voice[2];  // Not used yet
   uint8_t ep_voice_size[2][CFG_TUD_BTH_ISO_ALT_COUNT];
 
-  // Endpoint Transfer buffer
-  CFG_TUSB_MEM_ALIGN bt_hci_cmd_t hci_cmd;
-  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_BTH_DATA_EPSIZE];
-
+  // Previous amount of bytes sent when issuing ZLP
+  uint32_t prev_xferred_bytes;
 } btd_interface_t;
 
+typedef struct {
+  TUD_EPBUF_DEF(epout_buf, CFG_TUD_BTH_DATA_EPSIZE);
+  TUD_EPBUF_TYPE_DEF(bt_hci_cmd_t, hci_cmd);
+} btd_epbuf_t;
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION btd_interface_t _btd_itf;
+static btd_interface_t _btd_itf;
+CFG_TUD_MEM_SECTION static btd_epbuf_t _btd_epbuf;
 
 static bool bt_tx_data(uint8_t ep, void *data, uint16_t len)
 {
@@ -91,11 +95,14 @@ bool tud_bt_acl_data_send(void *event, uint16_t event_len)
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void btd_init(void)
-{
+void btd_init(void) {
   tu_memclr(&_btd_itf, sizeof(_btd_itf));
 }
 
+bool btd_deinit(void) {
+  return true;
+}
+
 void btd_reset(uint8_t rhport)
 {
   (void)rhport;
@@ -124,14 +131,28 @@ uint16_t btd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_
   TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0);
   _btd_itf.ep_ev = desc_ep->bEndpointAddress;
 
-  // Open endpoint pair
-  TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(desc_ep), 2, TUSB_XFER_BULK, &_btd_itf.ep_acl_out,
-                                &_btd_itf.ep_acl_in), 0);
+  desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep);
 
-  itf_desc = (tusb_desc_interface_t const *)tu_desc_next(tu_desc_next(tu_desc_next(desc_ep)));
+  // Open endpoint pair
+  TU_ASSERT(usbd_open_edpt_pair(rhport, (uint8_t const *)desc_ep, 2,
+                                TUSB_XFER_BULK, &_btd_itf.ep_acl_out,
+                                &_btd_itf.ep_acl_in),
+            0);
+
+  // Save acl in endpoint max packet size
+  tusb_desc_endpoint_t const *desc_ep_acl_in = desc_ep;
+  for (size_t p = 0; p < 2; p++) {
+    if (tu_edpt_dir(desc_ep_acl_in->bEndpointAddress) == TUSB_DIR_IN) {
+      _btd_itf.ep_acl_in_pkt_sz = tu_edpt_packet_size(desc_ep_acl_in);
+      break;
+    }
+    desc_ep_acl_in = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep_acl_in);
+  }
+
+  itf_desc = (tusb_desc_interface_t const *)tu_desc_next(tu_desc_next(desc_ep));
 
   // Prepare for incoming data from host
-  TU_ASSERT(usbd_edpt_xfer(rhport, _btd_itf.ep_acl_out, _btd_itf.epout_buf, CFG_TUD_BTH_DATA_EPSIZE), 0);
+  TU_ASSERT(usbd_edpt_xfer(rhport, _btd_itf.ep_acl_out, _btd_epbuf.epout_buf, CFG_TUD_BTH_DATA_EPSIZE), 0);
 
   drv_len = hci_itf_size;
 
@@ -204,7 +225,9 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c
         request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE)
     {
       // HCI command packet addressing for single function Primary Controllers
-      TU_VERIFY(request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0);
+      // also compatible with historical mode if enabled
+      TU_VERIFY((request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0) ||
+                (CFG_TUD_BTH_HISTORICAL_COMPATIBLE && request->bRequest == 0xe0));
     }
     else if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE)
     {
@@ -220,30 +243,30 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c
     }
     else return false;
 
-    return tud_control_xfer(rhport, request, &_btd_itf.hci_cmd, sizeof(_btd_itf.hci_cmd));
+    return tud_control_xfer(rhport, request, &_btd_epbuf.hci_cmd, sizeof(bt_hci_cmd_t));
   }
   else if ( stage == CONTROL_STAGE_DATA )
   {
     // Handle class request only
     TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
 
-    if (tud_bt_hci_cmd_cb) tud_bt_hci_cmd_cb(&_btd_itf.hci_cmd, tu_min16(request->wLength, sizeof(_btd_itf.hci_cmd)));
+    if (tud_bt_hci_cmd_cb) {
+      tud_bt_hci_cmd_cb(&_btd_epbuf.hci_cmd, tu_min16(request->wLength, sizeof(bt_hci_cmd_t)));
+      }
   }
 
   return true;
 }
 
-bool btd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
-  (void)result;
-
+bool btd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result,
+                 uint32_t xferred_bytes) {
   // received new data from host
   if (ep_addr == _btd_itf.ep_acl_out)
   {
-    if (tud_bt_acl_data_received_cb) tud_bt_acl_data_received_cb(_btd_itf.epout_buf, xferred_bytes);
+    if (tud_bt_acl_data_received_cb) tud_bt_acl_data_received_cb(_btd_epbuf.epout_buf, xferred_bytes);
 
     // prepare for next data
-    TU_ASSERT(usbd_edpt_xfer(rhport, _btd_itf.ep_acl_out, _btd_itf.epout_buf, CFG_TUD_BTH_DATA_EPSIZE));
+    TU_ASSERT(usbd_edpt_xfer(rhport, _btd_itf.ep_acl_out, _btd_epbuf.epout_buf, CFG_TUD_BTH_DATA_EPSIZE));
   }
   else if (ep_addr == _btd_itf.ep_ev)
   {
@@ -251,7 +274,20 @@ bool btd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t
   }
   else if (ep_addr == _btd_itf.ep_acl_in)
   {
-    if (tud_bt_acl_data_sent_cb) tud_bt_acl_data_sent_cb((uint16_t)xferred_bytes);
+    if ((result == XFER_RESULT_SUCCESS) && (xferred_bytes > 0) &&
+        ((xferred_bytes & (_btd_itf.ep_acl_in_pkt_sz - 1)) == 0)) {
+      // Save number of transferred bytes
+      _btd_itf.prev_xferred_bytes = xferred_bytes;
+
+      // Send zero-length packet
+      tud_bt_acl_data_send(NULL, 0);
+    } else if (tud_bt_acl_data_sent_cb) {
+      if (xferred_bytes == 0) {
+        xferred_bytes = _btd_itf.prev_xferred_bytes;
+        _btd_itf.prev_xferred_bytes = 0;
+      }
+      tud_bt_acl_data_sent_cb((uint16_t)xferred_bytes);
+    }
   }
 
   return true;
diff --git a/src/class/bth/bth_device.h b/src/class/bth/bth_device.h
index 1b90d0915..4f6350839 100755
--- a/src/class/bth/bth_device.h
+++ b/src/class/bth/bth_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenberg
@@ -36,10 +36,17 @@
 #ifndef CFG_TUD_BTH_EVENT_EPSIZE
 #define CFG_TUD_BTH_EVENT_EPSIZE     16
 #endif
+
 #ifndef CFG_TUD_BTH_DATA_EPSIZE
 #define CFG_TUD_BTH_DATA_EPSIZE      64
 #endif
 
+// Allow BTH class to work in historically compatibility mode where the bRequest is always 0xe0.
+// See Bluetooth Core v5.3, Vol. 4, Part B, Section 2.2
+#ifndef CFG_TUD_BTH_HISTORICAL_COMPATIBLE
+#define CFG_TUD_BTH_HISTORICAL_COMPATIBLE 0
+#endif
+
 typedef struct TU_ATTR_PACKED
 {
   uint16_t op_code;
@@ -97,6 +104,7 @@ bool tud_bt_acl_data_send(void *acl_data, uint16_t data_len);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     btd_init            (void);
+bool     btd_deinit          (void);
 void     btd_reset           (uint8_t rhport);
 uint16_t btd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     btd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const *request);
diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index e345139ea..5cbd658fe 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -41,16 +41,6 @@
 /** \defgroup ClassDriver_CDC_Common Common Definitions
  *  @{ */
 
-// TODO remove
-/// CDC Pipe ID, used to indicate which pipe the API is addressing to (Notification, Out, In)
-typedef enum
-{
-  CDC_PIPE_NOTIFICATION , ///< Notification pipe
-  CDC_PIPE_DATA_IN      , ///< Data in pipe
-  CDC_PIPE_DATA_OUT     , ///< Data out pipe
-  CDC_PIPE_ERROR        , ///< Invalid Pipe ID
-}cdc_pipeid_t;
-
 //--------------------------------------------------------------------+
 // CDC Communication Interface Class
 //--------------------------------------------------------------------+
@@ -146,8 +136,7 @@ typedef enum{
 //--------------------------------------------------------------------+
 
 /// Communication Interface Management Element Request Codes
-typedef enum
-{
+typedef enum {
   CDC_REQUEST_SEND_ENCAPSULATED_COMMAND                    = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface
   CDC_REQUEST_GET_ENCAPSULATED_RESPONSE                    = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface.
   CDC_REQUEST_SET_COMM_FEATURE                             = 0x02,
@@ -190,15 +179,38 @@ typedef enum
   CDC_REQUEST_GET_ATM_VC_STATISTICS                        = 0x53,
 
   CDC_REQUEST_MDLM_SEMANTIC_MODEL                          = 0x60,
-}cdc_management_request_t;
+} cdc_management_request_t;
+
+typedef enum {
+  CDC_CONTROL_LINE_STATE_DTR = 0x01,
+  CDC_CONTROL_LINE_STATE_RTS = 0x02,
+} cdc_control_line_state_t;
+
+typedef enum {
+  CDC_LINE_CODING_STOP_BITS_1   = 0, // 1   bit
+  CDC_LINE_CODING_STOP_BITS_1_5 = 1, // 1.5 bits
+  CDC_LINE_CODING_STOP_BITS_2   = 2, // 2   bits
+} cdc_line_coding_stopbits_t;
+
+// TODO Backward compatible for typos. Maybe removed in the future release
+#define CDC_LINE_CONDING_STOP_BITS_1   CDC_LINE_CODING_STOP_BITS_1
+#define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5
+#define CDC_LINE_CONDING_STOP_BITS_2   CDC_LINE_CODING_STOP_BITS_2
+
+typedef enum {
+  CDC_LINE_CODING_PARITY_NONE  = 0,
+  CDC_LINE_CODING_PARITY_ODD   = 1,
+  CDC_LINE_CODING_PARITY_EVEN  = 2,
+  CDC_LINE_CODING_PARITY_MARK  = 3,
+  CDC_LINE_CODING_PARITY_SPACE = 4,
+} cdc_line_coding_parity_t;
 
 //--------------------------------------------------------------------+
-// Management Elemenent Notification (Notification Endpoint)
+// Management Element Notification (Notification Endpoint)
 //--------------------------------------------------------------------+
 
 /// 6.3 Notification Codes
-typedef enum
-{
+typedef enum {
   CDC_NOTIF_NETWORK_CONNECTION               = 0x00, ///< This notification allows the device to notify the host about network connection status.
   CDC_NOTIF_RESPONSE_AVAILABLE               = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request.
   CDC_NOTIF_AUX_JACK_HOOK_STATE              = 0x08,
@@ -365,7 +377,9 @@ typedef struct TU_ATTR_PACKED
     uint32_t incoming_distinctive   : 1; ///< 0 : Reports only incoming ringing. 1 : Reports incoming distinctive ringing patterns.
     uint32_t dual_tone_multi_freq   : 1; ///< 0 : Cannot report dual tone multi-frequency (DTMF) digits input remotely over the telephone line. 1 : Can report DTMF digits input remotely over the telephone line.
     uint32_t line_state_change      : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification
-    uint32_t TU_RESERVED            : 26;
+    uint32_t TU_RESERVED0           : 2;
+    uint32_t TU_RESERVED1           : 16;
+    uint32_t TU_RESERVED2           : 8;
   } bmCapabilities;
 }cdc_desc_func_telephone_call_state_reporting_capabilities_t;
 
@@ -390,9 +404,10 @@ TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct");
 
 typedef struct TU_ATTR_PACKED
 {
-  uint16_t dte_is_present : 1; ///< Indicates to DCE if DTE is presentor not. This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR.
-  uint16_t half_duplex_carrier_control : 1;
-  uint16_t : 14;
+  uint16_t dtr : 1;
+  uint16_t rts : 1;
+  uint16_t : 6;
+  uint16_t : 8;
 } cdc_line_control_state_t;
 
 TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct");
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index fab6f0035..efb672201 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -33,16 +33,19 @@
 
 #include "cdc_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_CDC_LOG_LEVEL
+  #define CFG_TUD_CDC_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_CDC_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-enum
-{
-  BULK_PACKET_SIZE = (TUD_OPT_HIGH_SPEED ? 512 : 64)
-};
+#define BULK_PACKET_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;
   uint8_t ep_notif;
   uint8_t ep_in;
@@ -52,8 +55,8 @@ typedef struct
   uint8_t line_state;
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
-  char    wanted_char;
-  cdc_line_coding_t line_coding;
+  char wanted_char;
+  TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding;
 
   // FIFO
   tu_fifo_t rx_ff;
@@ -62,34 +65,40 @@ typedef struct
   uint8_t rx_ff_buf[CFG_TUD_CDC_RX_BUFSIZE];
   uint8_t tx_ff_buf[CFG_TUD_CDC_TX_BUFSIZE];
 
-#if CFG_FIFO_MUTEX
-  osal_mutex_def_t rx_ff_mutex;
-  osal_mutex_def_t tx_ff_mutex;
-#endif
-
-  // Endpoint Transfer buffer
-  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
-  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
-
-}cdcd_interface_t;
+  OSAL_MUTEX_DEF(rx_ff_mutex);
+  OSAL_MUTEX_DEF(tx_ff_mutex);
+} cdcd_interface_t;
 
 #define ITF_MEM_RESET_SIZE   offsetof(cdcd_interface_t, wanted_char)
 
+typedef struct {
+  TUD_EPBUF_DEF(epout, CFG_TUD_CDC_EP_BUFSIZE);
+  TUD_EPBUF_DEF(epin, CFG_TUD_CDC_EP_BUFSIZE);
+} cdcd_epbuf_t;
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
+static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
+CFG_TUD_MEM_SECTION static cdcd_epbuf_t _cdcd_epbuf[CFG_TUD_CDC];
+
+static tud_cdc_configure_fifo_t _cdcd_fifo_cfg;
+
+static bool _prep_out_transaction(uint8_t itf) {
+  const uint8_t rhport = 0;
+  cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
+  cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf];
+
+  // Skip if usb is not ready yet
+  TU_VERIFY(tud_ready() && p_cdc->ep_out);
 
-static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
-{
-  uint8_t const rhport = 0;
   uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff);
 
   // Prepare for incoming data but only allow what we can store in the ring buffer.
   // TODO Actually we can still carry out the transfer, keeping count of received bytes
   // and slowly move it to the FIFO when read().
   // This pre-check reduces endpoint claiming
-  TU_VERIFY(available >= sizeof(p_cdc->epout_buf));
+  TU_VERIFY(available >= CFG_TUD_CDC_EP_BUFSIZE);
 
   // claim endpoint
   TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out));
@@ -97,14 +106,11 @@ static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
   // fifo can be changed before endpoint is claimed
   available = tu_fifo_remaining(&p_cdc->rx_ff);
 
-  if ( available >= sizeof(p_cdc->epout_buf) )
-  {
-    return usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf));
-  }else
-  {
+  if (available >= CFG_TUD_CDC_EP_BUFSIZE) {
+    return usbd_edpt_xfer(rhport, p_cdc->ep_out, p_epbuf->epout, CFG_TUD_CDC_EP_BUFSIZE);
+  } else {
     // Release endpoint since we don't make any transfer
     usbd_edpt_release(rhport, p_cdc->ep_out);
-
     return false;
   }
 }
@@ -112,97 +118,101 @@ static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
-bool tud_cdc_n_connected(uint8_t itf)
-{
+
+bool tud_cdc_configure_fifo(const tud_cdc_configure_fifo_t* cfg) {
+  TU_VERIFY(cfg);
+  _cdcd_fifo_cfg = (*cfg);
+  return true;
+}
+
+bool tud_cdc_n_ready(uint8_t itf) {
+  return tud_ready() && _cdcd_itf[itf].ep_in != 0 && _cdcd_itf[itf].ep_out != 0;
+}
+
+bool tud_cdc_n_connected(uint8_t itf) {
   // DTR (bit 0) active  is considered as connected
   return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0);
 }
 
-uint8_t tud_cdc_n_get_line_state (uint8_t itf)
-{
+uint8_t tud_cdc_n_get_line_state(uint8_t itf) {
   return _cdcd_itf[itf].line_state;
 }
 
-void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding)
-{
+void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t* coding) {
   (*coding) = _cdcd_itf[itf].line_coding;
 }
 
-void tud_cdc_n_set_wanted_char (uint8_t itf, char wanted)
-{
+void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted) {
   _cdcd_itf[itf].wanted_char = wanted;
 }
 
-
 //--------------------------------------------------------------------+
 // READ API
 //--------------------------------------------------------------------+
-uint32_t tud_cdc_n_available(uint8_t itf)
-{
+uint32_t tud_cdc_n_available(uint8_t itf) {
   return tu_fifo_count(&_cdcd_itf[itf].rx_ff);
 }
 
-uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
-{
+uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize) {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) bufsize);
-  _prep_out_transaction(p_cdc);
+  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
+  _prep_out_transaction(itf);
   return num_read;
 }
 
-bool tud_cdc_n_peek(uint8_t itf, uint8_t* chr)
-{
+bool tud_cdc_n_peek(uint8_t itf, uint8_t* chr) {
   return tu_fifo_peek(&_cdcd_itf[itf].rx_ff, chr);
 }
 
-void tud_cdc_n_read_flush (uint8_t itf)
-{
+void tud_cdc_n_read_flush(uint8_t itf) {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
   tu_fifo_clear(&p_cdc->rx_ff);
-  _prep_out_transaction(p_cdc);
+  _prep_out_transaction(itf);
 }
 
 //--------------------------------------------------------------------+
 // WRITE API
 //--------------------------------------------------------------------+
-uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
-{
+uint32_t tud_cdc_n_write(uint8_t itf, const void* buffer, uint32_t bufsize) {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) bufsize);
+  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
 
   // flush if queue more than packet size
-  if ( tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE )
-  {
+  if (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE
+      #if CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE
+      || tu_fifo_full(&p_cdc->tx_ff) // check full if fifo size is less than packet size
+      #endif
+      ) {
     tud_cdc_n_write_flush(itf);
   }
 
   return ret;
 }
 
-uint32_t tud_cdc_n_write_flush (uint8_t itf)
-{
+uint32_t tud_cdc_n_write_flush(uint8_t itf) {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
+  cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf];
 
   // Skip if usb is not ready yet
-  TU_VERIFY( tud_ready(), 0 );
+  TU_VERIFY(tud_ready(), 0);
 
   // No data to send
-  if ( !tu_fifo_count(&p_cdc->tx_ff) ) return 0;
+  if (!tu_fifo_count(&p_cdc->tx_ff)) {
+    return 0;
+  }
 
-  uint8_t const rhport = 0;
+  const uint8_t rhport = 0;
 
   // Claim the endpoint
-  TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 );
+  TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_in), 0);
 
   // Pull data from FIFO
-  uint16_t const count = tu_fifo_read_n(&p_cdc->tx_ff, p_cdc->epin_buf, sizeof(p_cdc->epin_buf));
+  const uint16_t count = tu_fifo_read_n(&p_cdc->tx_ff, p_epbuf->epin, CFG_TUD_CDC_EP_BUFSIZE);
 
-  if ( count )
-  {
-    TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
+  if (count) {
+    TU_ASSERT(usbd_edpt_xfer(rhport, p_cdc->ep_in, p_epbuf->epin, count), 0);
     return count;
-  }else
-  {
+  } else {
     // Release endpoint since we don't make any transfer
     // Note: data is dropped if terminal is not connected
     usbd_edpt_release(rhport, p_cdc->ep_in);
@@ -210,33 +220,30 @@ uint32_t tud_cdc_n_write_flush (uint8_t itf)
   }
 }
 
-uint32_t tud_cdc_n_write_available (uint8_t itf)
-{
+uint32_t tud_cdc_n_write_available(uint8_t itf) {
   return tu_fifo_remaining(&_cdcd_itf[itf].tx_ff);
 }
 
-bool tud_cdc_n_write_clear (uint8_t itf)
-{
+bool tud_cdc_n_write_clear(uint8_t itf) {
   return tu_fifo_clear(&_cdcd_itf[itf].tx_ff);
 }
 
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void cdcd_init(void)
-{
+void cdcd_init(void) {
   tu_memclr(_cdcd_itf, sizeof(_cdcd_itf));
+  tu_memclr(&_cdcd_fifo_cfg, sizeof(_cdcd_fifo_cfg));
 
-  for(uint8_t i=0; i<CFG_TUD_CDC; i++)
-  {
+  for (uint8_t i = 0; i < CFG_TUD_CDC; i++) {
     cdcd_interface_t* p_cdc = &_cdcd_itf[i];
 
     p_cdc->wanted_char = (char) -1;
 
     // default line coding is : stop bit = 1, parity = none, data bits = 8
-    p_cdc->line_coding.bit_rate  = 115200;
+    p_cdc->line_coding.bit_rate = 115200;
     p_cdc->line_coding.stop_bits = 0;
-    p_cdc->line_coding.parity    = 0;
+    p_cdc->line_coding.parity = 0;
     p_cdc->line_coding.data_bits = 8;
 
     // Config RX fifo
@@ -247,87 +254,110 @@ void cdcd_init(void)
     // In this way, the most current data is prioritized.
     tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true);
 
-#if CFG_FIFO_MUTEX
-    tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, osal_mutex_create(&p_cdc->rx_ff_mutex));
-    tu_fifo_config_mutex(&p_cdc->tx_ff, osal_mutex_create(&p_cdc->tx_ff_mutex), NULL);
-#endif
+    #if OSAL_MUTEX_REQUIRED
+    osal_mutex_t mutex_rd = osal_mutex_create(&p_cdc->rx_ff_mutex);
+    osal_mutex_t mutex_wr = osal_mutex_create(&p_cdc->tx_ff_mutex);
+    TU_ASSERT(mutex_rd != NULL && mutex_wr != NULL, );
+
+    tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, mutex_rd);
+    tu_fifo_config_mutex(&p_cdc->tx_ff, mutex_wr, NULL);
+    #endif
   }
 }
 
-void cdcd_reset(uint8_t rhport)
-{
+bool cdcd_deinit(void) {
+  #if OSAL_MUTEX_REQUIRED
+  for(uint8_t i=0; i<CFG_TUD_CDC; i++) {
+    cdcd_interface_t* p_cdc = &_cdcd_itf[i];
+    osal_mutex_t mutex_rd = p_cdc->rx_ff.mutex_rd;
+    osal_mutex_t mutex_wr = p_cdc->tx_ff.mutex_wr;
+
+    if (mutex_rd) {
+      osal_mutex_delete(mutex_rd);
+      tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, NULL);
+    }
+
+    if (mutex_wr) {
+      osal_mutex_delete(mutex_wr);
+      tu_fifo_config_mutex(&p_cdc->tx_ff, NULL, NULL);
+    }
+  }
+  #endif
+
+  return true;
+}
+
+void cdcd_reset(uint8_t rhport) {
   (void) rhport;
 
-  for(uint8_t i=0; i<CFG_TUD_CDC; i++)
-  {
+  for (uint8_t i = 0; i < CFG_TUD_CDC; i++) {
     cdcd_interface_t* p_cdc = &_cdcd_itf[i];
 
     tu_memclr(p_cdc, ITF_MEM_RESET_SIZE);
-    tu_fifo_clear(&p_cdc->rx_ff);
-    tu_fifo_clear(&p_cdc->tx_ff);
+    if (!_cdcd_fifo_cfg.rx_persistent) {
+      tu_fifo_clear(&p_cdc->rx_ff);
+    }
+    if (!_cdcd_fifo_cfg.tx_persistent) {
+      tu_fifo_clear(&p_cdc->tx_ff);
+    }
     tu_fifo_set_overwritable(&p_cdc->tx_ff, true);
   }
 }
 
-uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
+uint16_t cdcd_open(uint8_t rhport, const tusb_desc_interface_t* itf_desc, uint16_t max_len) {
   // Only support ACM subclass
   TU_VERIFY( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
              CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass, 0);
 
   // Find available interface
-  cdcd_interface_t * p_cdc = NULL;
-  for(uint8_t cdc_id=0; cdc_id<CFG_TUD_CDC; cdc_id++)
-  {
-    if ( _cdcd_itf[cdc_id].ep_in == 0 )
-    {
-      p_cdc = &_cdcd_itf[cdc_id];
+  cdcd_interface_t* p_cdc;
+  uint8_t cdc_id;
+  for (cdc_id = 0; cdc_id < CFG_TUD_CDC; cdc_id++) {
+    p_cdc = &_cdcd_itf[cdc_id];
+    if (p_cdc->ep_in == 0) {
       break;
     }
   }
-  TU_ASSERT(p_cdc, 0);
+  TU_ASSERT(cdc_id < CFG_TUD_CDC, 0);
 
   //------------- Control Interface -------------//
   p_cdc->itf_num = itf_desc->bInterfaceNumber;
 
   uint16_t drv_len = sizeof(tusb_desc_interface_t);
-  uint8_t const * p_desc = tu_desc_next( itf_desc );
+  const uint8_t* p_desc = tu_desc_next(itf_desc);
 
   // Communication Functional Descriptors
-  while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
-  {
+  while (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len) {
     drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
+    p_desc = tu_desc_next(p_desc);
   }
 
-  if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
-  {
+  if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) {
     // notification endpoint
-    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+    const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc;
 
-    TU_ASSERT( usbd_edpt_open(rhport, desc_ep), 0 );
+    TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0);
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
+    p_desc = tu_desc_next(p_desc);
   }
 
   //------------- Data Interface (if any) -------------//
-  if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
-       (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
-  {
+  if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+      (TUSB_CLASS_CDC_DATA == ((const tusb_desc_interface_t*) p_desc)->bInterfaceClass)) {
     // next to endpoint descriptor
     drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
+    p_desc = tu_desc_next(p_desc);
 
     // Open endpoint pair
-    TU_ASSERT( usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &p_cdc->ep_out, &p_cdc->ep_in), 0 );
+    TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &p_cdc->ep_out, &p_cdc->ep_in), 0);
 
-    drv_len += 2*sizeof(tusb_desc_endpoint_t);
+    drv_len += 2 * sizeof(tusb_desc_endpoint_t);
   }
 
   // Prepare for incoming data
-  _prep_out_transaction(p_cdc);
+  _prep_out_transaction(cdc_id);
 
   return drv_len;
 }
@@ -335,51 +365,45 @@ uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
+bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request) {
   // Handle class request only
   TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
 
-  uint8_t itf = 0;
-  cdcd_interface_t* p_cdc = _cdcd_itf;
+  uint8_t itf;
+  cdcd_interface_t* p_cdc;
 
   // Identify which interface to use
-  for ( ; ; itf++, p_cdc++)
-  {
-    if (itf >= TU_ARRAY_SIZE(_cdcd_itf)) return false;
-
-    if ( p_cdc->itf_num == request->wIndex ) break;
+  for (itf = 0; itf < CFG_TUD_CDC; itf++) {
+    p_cdc = &_cdcd_itf[itf];
+    if (p_cdc->itf_num == request->wIndex) {
+      break;
+    }
   }
+  TU_VERIFY(itf < CFG_TUD_CDC);
 
-  switch ( request->bRequest )
-  {
+  switch (request->bRequest) {
     case CDC_REQUEST_SET_LINE_CODING:
-      if (stage == CONTROL_STAGE_SETUP)
-      {
-        TU_LOG2("  Set Line Coding\r\n");
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG_DRV("  Set Line Coding\r\n");
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
+      } else if (stage == CONTROL_STAGE_ACK) {
+        if (tud_cdc_line_coding_cb) {
+          tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
+        }
       }
-      else if ( stage == CONTROL_STAGE_ACK)
-      {
-        if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
-      }
-    break;
+      break;
 
     case CDC_REQUEST_GET_LINE_CODING:
-      if (stage == CONTROL_STAGE_SETUP)
-      {
-        TU_LOG2("  Get Line Coding\r\n");
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG_DRV("  Get Line Coding\r\n");
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
       }
-    break;
+      break;
 
     case CDC_REQUEST_SET_CONTROL_LINE_STATE:
-      if (stage == CONTROL_STAGE_SETUP)
-      {
+      if (stage == CONTROL_STAGE_SETUP) {
         tud_control_status(rhport, request);
-      }
-      else if (stage == CONTROL_STAGE_ACK)
-      {
+      } else if (stage == CONTROL_STAGE_ACK) {
         // CDC PSTN v1.2 section 6.3.12
         // Bit 0: Indicates if DTE is present or not.
         //        This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
@@ -389,89 +413,89 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         bool const rts = tu_bit_test(request->wValue, 1);
 
         p_cdc->line_state = (uint8_t) request->wValue;
-        
+
         // Disable fifo overwriting if DTR bit is set
         tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
 
-        TU_LOG2("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
+        TU_LOG_DRV("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
 
         // Invoke callback
-        if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
+        if (tud_cdc_line_state_cb) {
+          tud_cdc_line_state_cb(itf, dtr, rts);
+        }
       }
-    break;
-    case CDC_REQUEST_SEND_BREAK:
-      if (stage == CONTROL_STAGE_SETUP)
-      {
-        tud_control_status(rhport, request);
-      }
-      else if (stage == CONTROL_STAGE_ACK)
-      {
-        TU_LOG2("  Send Break\r\n");
-        if ( tud_cdc_send_break_cb ) tud_cdc_send_break_cb(itf, request->wValue);
-      }
-    break;
+      break;
 
-    default: return false; // stall unsupported request
+    case CDC_REQUEST_SEND_BREAK:
+      if (stage == CONTROL_STAGE_SETUP) {
+        tud_control_status(rhport, request);
+      } else if (stage == CONTROL_STAGE_ACK) {
+        TU_LOG_DRV("  Send Break\r\n");
+        if (tud_cdc_send_break_cb) {
+          tud_cdc_send_break_cb(itf, request->wValue);
+        }
+      }
+      break;
+
+    default:
+      return false; // stall unsupported request
   }
 
   return true;
 }
 
-bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) result;
 
   uint8_t itf;
   cdcd_interface_t* p_cdc;
 
   // Identify which interface to use
-  for (itf = 0; itf < CFG_TUD_CDC; itf++)
-  {
+  for (itf = 0; itf < CFG_TUD_CDC; itf++) {
     p_cdc = &_cdcd_itf[itf];
-    if ( ( ep_addr == p_cdc->ep_out ) || ( ep_addr == p_cdc->ep_in ) ) break;
+    if ((ep_addr == p_cdc->ep_out) || (ep_addr == p_cdc->ep_in)) {
+      break;
+    }
   }
   TU_ASSERT(itf < CFG_TUD_CDC);
+  cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf];
 
   // Received new data
-  if ( ep_addr == p_cdc->ep_out )
-  {
-    tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, (uint16_t) xferred_bytes);
-    
+  if (ep_addr == p_cdc->ep_out) {
+    tu_fifo_write_n(&p_cdc->rx_ff, p_epbuf->epout, (uint16_t) xferred_bytes);
+
     // Check for wanted char and invoke callback if needed
-    if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) )
-    {
-      for ( uint32_t i = 0; i < xferred_bytes; i++ )
-      {
-        if ( (p_cdc->wanted_char == p_cdc->epout_buf[i]) && !tu_fifo_empty(&p_cdc->rx_ff) )
-        {
+    if (tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1)) {
+      for (uint32_t i = 0; i < xferred_bytes; i++) {
+        if ((p_cdc->wanted_char == p_epbuf->epout[i]) && !tu_fifo_empty(&p_cdc->rx_ff)) {
           tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char);
         }
       }
     }
-    
+
     // invoke receive callback (if there is still data)
-    if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf);
-    
+    if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff)) {
+      tud_cdc_rx_cb(itf);
+    }
+
     // prepare for OUT transaction
-    _prep_out_transaction(p_cdc);
+    _prep_out_transaction(itf);
   }
-  
+
   // Data sent to host, we continue to fetch from tx fifo to send.
   // Note: This will cause incorrect baudrate set in line coding.
   //       Though maybe the baudrate is not really important !!!
-  if ( ep_addr == p_cdc->ep_in )
-  {
+  if (ep_addr == p_cdc->ep_in) {
     // invoke transmit callback to possibly refill tx fifo
-    if ( tud_cdc_tx_complete_cb ) tud_cdc_tx_complete_cb(itf);
+    if (tud_cdc_tx_complete_cb) {
+      tud_cdc_tx_complete_cb(itf);
+    }
 
-    if ( 0 == tud_cdc_n_write_flush(itf) )
-    {
+    if (0 == tud_cdc_n_write_flush(itf)) {
       // If there is no data left, a ZLP should be sent if
       // xferred_bytes is multiple of EP Packet size and not zero
-      if ( !tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE-1))) )
-      {
-        if ( usbd_edpt_claim(rhport, p_cdc->ep_in) )
-        {
+      if (!tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE - 1)))) {
+        if (usbd_edpt_claim(rhport, p_cdc->ep_in)) {
           usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0);
         }
       }
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index fbc7162a3..2d5ba2575 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,10 +24,9 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_CDC_DEVICE_H_
-#define _TUSB_CDC_DEVICE_H_
+#ifndef TUSB_CDC_DEVICE_H_
+#define TUSB_CDC_DEVICE_H_
 
-#include "common/tusb_common.h"
 #include "cdc.h"
 
 //--------------------------------------------------------------------+
@@ -46,84 +45,144 @@
  extern "C" {
 #endif
 
-/** \addtogroup CDC_Serial Serial
- *  @{
- *  \defgroup   CDC_Serial_Device Device
- *  @{ */
+//--------------------------------------------------------------------+
+// Driver Configuration
+//--------------------------------------------------------------------+
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t rx_persistent : 1; // keep rx fifo on bus reset or disconnect
+  uint8_t tx_persistent : 1; // keep tx fifo on bus reset or disconnect
+} tud_cdc_configure_fifo_t;
+
+// Configure CDC FIFOs behavior
+bool tud_cdc_configure_fifo(tud_cdc_configure_fifo_t const* cfg);
 
 //--------------------------------------------------------------------+
-// Application API (Multiple Ports)
-// CFG_TUD_CDC > 1
+// Application API (Multiple Ports) i.e. CFG_TUD_CDC > 1
 //--------------------------------------------------------------------+
 
+// Check if interface is ready
+bool tud_cdc_n_ready(uint8_t itf);
+
 // Check if terminal is connected to this port
-bool     tud_cdc_n_connected       (uint8_t itf);
+bool tud_cdc_n_connected(uint8_t itf);
 
 // Get current line state. Bit 0:  DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
-uint8_t  tud_cdc_n_get_line_state  (uint8_t itf);
+uint8_t tud_cdc_n_get_line_state(uint8_t itf);
 
 // Get current line encoding: bit rate, stop bits parity etc ..
-void     tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding);
+void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t* coding);
 
 // Set special character that will trigger tud_cdc_rx_wanted_cb() callback on receiving
-void     tud_cdc_n_set_wanted_char (uint8_t itf, char wanted);
+void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted);
 
 // Get the number of bytes available for reading
-uint32_t tud_cdc_n_available       (uint8_t itf);
+uint32_t tud_cdc_n_available(uint8_t itf);
 
 // Read received bytes
-uint32_t tud_cdc_n_read            (uint8_t itf, void* buffer, uint32_t bufsize);
+uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize);
 
 // Read a byte, return -1 if there is none
-static inline
-int32_t  tud_cdc_n_read_char       (uint8_t itf);
+TU_ATTR_ALWAYS_INLINE static inline int32_t tud_cdc_n_read_char(uint8_t itf) {
+  uint8_t ch;
+  return tud_cdc_n_read(itf, &ch, 1) ? (int32_t) ch : -1;
+}
 
 // Clear the received FIFO
-void     tud_cdc_n_read_flush      (uint8_t itf);
+void tud_cdc_n_read_flush(uint8_t itf);
 
-// Get a byte from FIFO at the specified position without removing it
-bool     tud_cdc_n_peek            (uint8_t itf, uint8_t* ui8);
+// Get a byte from FIFO without removing it
+bool tud_cdc_n_peek(uint8_t itf, uint8_t* ui8);
 
 // Write bytes to TX FIFO, data may remain in the FIFO for a while
-uint32_t tud_cdc_n_write           (uint8_t itf, void const* buffer, uint32_t bufsize);
+uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize);
 
 // Write a byte
-static inline
-uint32_t tud_cdc_n_write_char      (uint8_t itf, char ch);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_n_write_char(uint8_t itf, char ch) {
+  return tud_cdc_n_write(itf, &ch, 1);
+}
 
 // Write a null-terminated string
-static inline
-uint32_t tud_cdc_n_write_str       (uint8_t itf, char const* str);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_n_write_str(uint8_t itf, char const* str) {
+  return tud_cdc_n_write(itf, str, strlen(str));
+}
 
 // Force sending data if possible, return number of forced bytes
-uint32_t tud_cdc_n_write_flush     (uint8_t itf);
+uint32_t tud_cdc_n_write_flush(uint8_t itf);
 
 // Return the number of bytes (characters) available for writing to TX FIFO buffer in a single n_write operation.
-uint32_t tud_cdc_n_write_available (uint8_t itf);
+uint32_t tud_cdc_n_write_available(uint8_t itf);
 
 // Clear the transmit FIFO
-bool tud_cdc_n_write_clear (uint8_t itf);
+bool tud_cdc_n_write_clear(uint8_t itf);
 
 //--------------------------------------------------------------------+
 // Application API (Single Port)
 //--------------------------------------------------------------------+
-static inline bool     tud_cdc_connected       (void);
-static inline uint8_t  tud_cdc_get_line_state  (void);
-static inline void     tud_cdc_get_line_coding (cdc_line_coding_t* coding);
-static inline void     tud_cdc_set_wanted_char (char wanted);
 
-static inline uint32_t tud_cdc_available       (void);
-static inline int32_t  tud_cdc_read_char       (void);
-static inline uint32_t tud_cdc_read            (void* buffer, uint32_t bufsize);
-static inline void     tud_cdc_read_flush      (void);
-static inline bool     tud_cdc_peek            (uint8_t* ui8);
+TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_ready(void) {
+  return tud_cdc_n_ready(0);
+}
 
-static inline uint32_t tud_cdc_write_char      (char ch);
-static inline uint32_t tud_cdc_write           (void const* buffer, uint32_t bufsize);
-static inline uint32_t tud_cdc_write_str       (char const* str);
-static inline uint32_t tud_cdc_write_flush     (void);
-static inline uint32_t tud_cdc_write_available (void);
-static inline bool     tud_cdc_write_clear     (void);
+TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_connected(void) {
+  return tud_cdc_n_connected(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tud_cdc_get_line_state(void) {
+  return tud_cdc_n_get_line_state(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tud_cdc_get_line_coding(cdc_line_coding_t* coding) {
+  tud_cdc_n_get_line_coding(0, coding);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tud_cdc_set_wanted_char(char wanted) {
+  tud_cdc_n_set_wanted_char(0, wanted);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_available(void) {
+  return tud_cdc_n_available(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline int32_t tud_cdc_read_char(void) {
+  return tud_cdc_n_read_char(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_read(void* buffer, uint32_t bufsize) {
+  return tud_cdc_n_read(0, buffer, bufsize);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tud_cdc_read_flush(void) {
+  tud_cdc_n_read_flush(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_peek(uint8_t* ui8) {
+  return tud_cdc_n_peek(0, ui8);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write_char(char ch) {
+  return tud_cdc_n_write_char(0, ch);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write(void const* buffer, uint32_t bufsize) {
+  return tud_cdc_n_write(0, buffer, bufsize);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write_str(char const* str) {
+  return tud_cdc_n_write_str(0, str);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write_flush(void) {
+  return tud_cdc_n_write_flush(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write_available(void) {
+  return tud_cdc_n_write_available(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_write_clear(void) {
+  return tud_cdc_n_write_clear(0);
+}
 
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
@@ -135,7 +194,7 @@ TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf);
 // Invoked when received `wanted_char`
 TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char);
 
-// Invoked when space becomes available in TX buffer
+// Invoked when a TX is complete and therefore space becomes available in TX buffer
 TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf);
 
 // Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE
@@ -145,109 +204,16 @@ TU_ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts);
 TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p_line_coding);
 
 // Invoked when received send break
+// \param[in]  itf  interface for which send break was received.
+// \param[in]  duration_ms  the length of time, in milliseconds, of the break signal. If a value of FFFFh, then the
+//                          device will send a break until another SendBreak request is received with value 0000h.
 TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms);
 
-//--------------------------------------------------------------------+
-// Inline Functions
-//--------------------------------------------------------------------+
-static inline int32_t tud_cdc_n_read_char (uint8_t itf)
-{
-  uint8_t ch;
-  return tud_cdc_n_read(itf, &ch, 1) ? (int32_t) ch : -1;
-}
-
-static inline uint32_t tud_cdc_n_write_char(uint8_t itf, char ch)
-{
-  return tud_cdc_n_write(itf, &ch, 1);
-}
-
-static inline uint32_t tud_cdc_n_write_str (uint8_t itf, char const* str)
-{
-  return tud_cdc_n_write(itf, str, strlen(str));
-}
-
-static inline bool tud_cdc_connected (void)
-{
-  return tud_cdc_n_connected(0);
-}
-
-static inline uint8_t tud_cdc_get_line_state (void)
-{
-  return tud_cdc_n_get_line_state(0);
-}
-
-static inline void tud_cdc_get_line_coding (cdc_line_coding_t* coding)
-{
-  tud_cdc_n_get_line_coding(0, coding);
-}
-
-static inline void tud_cdc_set_wanted_char (char wanted)
-{
-  tud_cdc_n_set_wanted_char(0, wanted);
-}
-
-static inline uint32_t tud_cdc_available (void)
-{
-  return tud_cdc_n_available(0);
-}
-
-static inline int32_t tud_cdc_read_char (void)
-{
-  return tud_cdc_n_read_char(0);
-}
-
-static inline uint32_t tud_cdc_read (void* buffer, uint32_t bufsize)
-{
-  return tud_cdc_n_read(0, buffer, bufsize);
-}
-
-static inline void tud_cdc_read_flush (void)
-{
-  tud_cdc_n_read_flush(0);
-}
-
-static inline bool tud_cdc_peek (uint8_t* ui8)
-{
-  return tud_cdc_n_peek(0, ui8);
-}
-
-static inline uint32_t tud_cdc_write_char (char ch)
-{
-  return tud_cdc_n_write_char(0, ch);
-}
-
-static inline uint32_t tud_cdc_write (void const* buffer, uint32_t bufsize)
-{
-  return tud_cdc_n_write(0, buffer, bufsize);
-}
-
-static inline uint32_t tud_cdc_write_str (char const* str)
-{
-  return tud_cdc_n_write_str(0, str);
-}
-
-static inline uint32_t tud_cdc_write_flush (void)
-{
-  return tud_cdc_n_write_flush(0);
-}
-
-static inline uint32_t tud_cdc_write_available(void)
-{
-  return tud_cdc_n_write_available(0);
-}
-
-static inline bool tud_cdc_write_clear(void)
-{
-  return tud_cdc_n_write_clear(0);
-}
-
-/** @} */
-/** @} */
-
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+
 void     cdcd_init            (void);
+bool     cdcd_deinit          (void);
 void     cdcd_reset           (uint8_t rhport);
 uint16_t cdcd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     cdcd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ee824cb4e..e817ebc7e 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -22,6 +22,9 @@
  * THE SOFTWARE.
  *
  * This file is part of the TinyUSB stack.
+ *
+ * Contribution
+ * - Heiko Kuester: CH34x support
  */
 
 #include "tusb_option.h"
@@ -29,232 +32,1649 @@
 #if (CFG_TUH_ENABLED && CFG_TUH_CDC)
 
 #include "host/usbh.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 
 #include "cdc_host.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUH_CDC_LOG_LEVEL
+  #define CFG_TUH_CDC_LOG_LEVEL   CFG_TUH_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
+// Host CDC Interface
 //--------------------------------------------------------------------+
+
 typedef struct {
-  uint8_t itf_num;
-  uint8_t itf_protocol;
+  uint8_t daddr;
+  uint8_t bInterfaceNumber;
+  uint8_t bInterfaceSubClass;
+  uint8_t bInterfaceProtocol;
 
   uint8_t ep_notif;
-  uint8_t ep_in;
-  uint8_t ep_out;
-
+  uint8_t serial_drid; // Serial Driver ID
+  bool mounted;        // Enumeration is complete
   cdc_acm_capability_t acm_capability;
 
-} cdch_data_t;
+  TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
+  uint8_t line_state;                               // DTR (bit0), RTS (bit1)
+
+  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
+  cdc_line_coding_t requested_line_coding;
+  // 1 byte padding
+  #endif
+
+  tuh_xfer_cb_t user_control_cb;
+
+  struct {
+    tu_edpt_stream_t tx;
+    tu_edpt_stream_t rx;
+
+    uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
+    uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
+  } stream;
+} cdch_interface_t;
+
+typedef struct {
+  TUH_EPBUF_DEF(tx, CFG_TUH_CDC_TX_EPSIZE);
+  TUH_EPBUF_DEF(rx, CFG_TUH_CDC_TX_EPSIZE);
+} cdch_epbuf_t;
+
+static cdch_interface_t cdch_data[CFG_TUH_CDC];
+CFG_TUH_MEM_SECTION static cdch_epbuf_t cdch_epbuf[CFG_TUH_CDC];
+
+//--------------------------------------------------------------------+
+// Serial Driver
+//--------------------------------------------------------------------+
+
+//------------- ACM prototypes -------------//
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+static void acm_process_config(tuh_xfer_t* xfer);
+
+static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+//------------- FTDI prototypes -------------//
+#if CFG_TUH_CDC_FTDI
+#include "serial/ftdi_sio.h"
+
+static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST};
+
+static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
+static void ftdi_process_config(tuh_xfer_t* xfer);
+
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+#endif
+
+//------------- CP210X prototypes -------------//
+#if CFG_TUH_CDC_CP210X
+#include "serial/cp210x.h"
+
+static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST};
+
+static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+static void cp210x_process_config(tuh_xfer_t* xfer);
+
+static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+#endif
+
+//------------- CH34x prototypes -------------//
+#if CFG_TUH_CDC_CH34X
+#include "serial/ch34x.h"
+
+static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST};
+
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len);
+static void ch34x_process_config(tuh_xfer_t* xfer);
+
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+#endif
+
+//------------- Common -------------//
+enum {
+  SERIAL_DRIVER_ACM = 0,
+
+#if CFG_TUH_CDC_FTDI
+  SERIAL_DRIVER_FTDI,
+#endif
+
+#if CFG_TUH_CDC_CP210X
+  SERIAL_DRIVER_CP210X,
+#endif
+
+#if CFG_TUH_CDC_CH34X
+  SERIAL_DRIVER_CH34X,
+#endif
+
+  SERIAL_DRIVER_COUNT
+};
+
+typedef struct {
+  uint16_t const (*vid_pid_list)[2];
+  uint16_t const vid_pid_count;
+  bool (*const open)(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
+  void (*const process_set_config)(tuh_xfer_t* xfer);
+  bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_data_format)(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+} cdch_serial_driver_t;
+
+// Note driver list must be in the same order as SERIAL_DRIVER enum
+static const cdch_serial_driver_t serial_drivers[] = {
+  {
+      .vid_pid_list           = NULL,
+      .vid_pid_count          = 0,
+      .open                   = acm_open,
+      .process_set_config     = acm_process_config,
+      .set_control_line_state = acm_set_control_line_state,
+      .set_baudrate           = acm_set_baudrate,
+      .set_data_format        = acm_set_data_format,
+      .set_line_coding        = acm_set_line_coding
+  },
+
+  #if CFG_TUH_CDC_FTDI
+  {
+      .vid_pid_list           = ftdi_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(ftdi_vid_pid_list),
+      .open                   = ftdi_open,
+      .process_set_config     = ftdi_process_config,
+      .set_control_line_state = ftdi_sio_set_modem_ctrl,
+      .set_baudrate           = ftdi_sio_set_baudrate,
+      .set_data_format        = ftdi_set_data_format,
+      .set_line_coding        = ftdi_set_line_coding
+  },
+  #endif
+
+  #if CFG_TUH_CDC_CP210X
+  {
+      .vid_pid_list           = cp210x_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(cp210x_vid_pid_list),
+      .open                   = cp210x_open,
+      .process_set_config     = cp210x_process_config,
+      .set_control_line_state = cp210x_set_modem_ctrl,
+      .set_baudrate           = cp210x_set_baudrate,
+      .set_data_format        = cp210x_set_data_format,
+      .set_line_coding        = cp210x_set_line_coding
+  },
+  #endif
+
+  #if CFG_TUH_CDC_CH34X
+  {
+      .vid_pid_list           = ch34x_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(ch34x_vid_pid_list),
+      .open                   = ch34x_open,
+      .process_set_config     = ch34x_process_config,
+      .set_control_line_state = ch34x_set_modem_ctrl,
+      .set_baudrate           = ch34x_set_baudrate,
+      .set_data_format        = ch34x_set_data_format,
+      .set_line_coding        = ch34x_set_line_coding
+  },
+  #endif
+};
+
+TU_VERIFY_STATIC(TU_ARRAY_SIZE(serial_drivers) == SERIAL_DRIVER_COUNT, "Serial driver count mismatch");
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-static cdch_data_t cdch_data[CFG_TUH_DEVICE_MAX];
 
-static inline cdch_data_t* get_itf(uint8_t dev_addr)
-{
-  return &cdch_data[dev_addr-1];
+static inline cdch_interface_t* get_itf(uint8_t idx) {
+  TU_ASSERT(idx < CFG_TUH_CDC, NULL);
+  cdch_interface_t* p_cdc = &cdch_data[idx];
+
+  return (p_cdc->daddr != 0) ? p_cdc : NULL;
 }
 
-bool tuh_cdc_mounted(uint8_t dev_addr)
-{
-  cdch_data_t* cdc = get_itf(dev_addr);
-  return cdc->ep_in && cdc->ep_out;
+static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
+    cdch_interface_t* p_cdc = &cdch_data[i];
+    if ( (p_cdc->daddr == daddr) &&
+         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) {
+      return i;
+    }
+  }
+
+  return TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid)
-{
-  if ( !tuh_cdc_mounted(dev_addr) ) return false;
+static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
+    if (cdch_data[i].daddr == 0) {
+      cdch_interface_t* p_cdc = &cdch_data[i];
+      p_cdc->daddr              = daddr;
+      p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
+      p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
+      p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
+      p_cdc->line_state         = 0;
+      return p_cdc;
+    }
+  }
 
-  cdch_data_t const * p_cdc = get_itf(dev_addr);
+  return NULL;
+}
 
-  switch (pipeid)
-  {
-    case CDC_PIPE_NOTIFICATION:
-      return usbh_edpt_busy(dev_addr, p_cdc->ep_notif );
+static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep);
+static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num);
+static void cdch_internal_control_complete(tuh_xfer_t* xfer);
 
-    case CDC_PIPE_DATA_IN:
-      return usbh_edpt_busy(dev_addr, p_cdc->ep_in );
+//--------------------------------------------------------------------+
+// APPLICATION API
+//--------------------------------------------------------------------+
 
-    case CDC_PIPE_DATA_OUT:
-      return usbh_edpt_busy(dev_addr, p_cdc->ep_out );
+uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) {
+  for (uint8_t i = 0; i < CFG_TUH_CDC; i++) {
+    const cdch_interface_t* p_cdc = &cdch_data[i];
+    if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i;
+  }
 
-    default:
-      return false;
+  return TUSB_INDEX_INVALID_8;
+}
+
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && info);
+
+  info->daddr = p_cdc->daddr;
+
+  // re-construct descriptor
+  tusb_desc_interface_t* desc = &info->desc;
+  desc->bLength            = sizeof(tusb_desc_interface_t);
+  desc->bDescriptorType    = TUSB_DESC_INTERFACE;
+
+  desc->bInterfaceNumber   = p_cdc->bInterfaceNumber;
+  desc->bAlternateSetting  = 0;
+  desc->bNumEndpoints      = 2u + (p_cdc->ep_notif ? 1u : 0u);
+  desc->bInterfaceClass    = TUSB_CLASS_CDC;
+  desc->bInterfaceSubClass = p_cdc->bInterfaceSubClass;
+  desc->bInterfaceProtocol = p_cdc->bInterfaceProtocol;
+  desc->iInterface         = 0; // not used yet
+
+  return true;
+}
+
+bool tuh_cdc_mounted(uint8_t idx) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+  return p_cdc->mounted;
+}
+
+bool tuh_cdc_get_dtr(uint8_t idx) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false;
+}
+
+bool tuh_cdc_get_rts(uint8_t idx) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false;
+}
+
+bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  *line_coding = p_cdc->line_coding;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// Write
+//--------------------------------------------------------------------+
+
+uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_write(p_cdc->daddr, &p_cdc->stream.tx, buffer, bufsize);
+}
+
+uint32_t tuh_cdc_write_flush(uint8_t idx) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx);
+}
+
+bool tuh_cdc_write_clear(uint8_t idx) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_clear(&p_cdc->stream.tx);
+}
+
+uint32_t tuh_cdc_write_available(uint8_t idx) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_write_available(p_cdc->daddr, &p_cdc->stream.tx);
+}
+
+//--------------------------------------------------------------------+
+// Read
+//--------------------------------------------------------------------+
+
+uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_read(p_cdc->daddr, &p_cdc->stream.rx, buffer, bufsize);
+}
+
+uint32_t tuh_cdc_read_available(uint8_t idx) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_read_available(&p_cdc->stream.rx);
+}
+
+bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_peek(&p_cdc->stream.rx, ch);
+}
+
+bool tuh_cdc_read_clear (uint8_t idx) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  bool ret = tu_edpt_stream_clear(&p_cdc->stream.rx);
+  tu_edpt_stream_read_xfer(p_cdc->daddr, &p_cdc->stream.rx);
+  return ret;
+}
+
+//--------------------------------------------------------------------+
+// Control Endpoint API
+//--------------------------------------------------------------------+
+
+static void process_internal_control_complete(tuh_xfer_t* xfer, uint8_t itf_num) {
+  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
+  uint16_t const value = tu_le16toh(xfer->setup->wValue);
+
+  if (xfer->result == XFER_RESULT_SUCCESS) {
+    switch (p_cdc->serial_drid) {
+      case SERIAL_DRIVER_ACM:
+        switch (xfer->setup->bRequest) {
+          case CDC_REQUEST_SET_CONTROL_LINE_STATE:
+            p_cdc->line_state = (uint8_t) value;
+            break;
+
+          case CDC_REQUEST_SET_LINE_CODING: {
+            uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
+            memcpy(&p_cdc->line_coding, xfer->buffer, len);
+            break;
+          }
+
+          default: break;
+        }
+        break;
+
+      #if CFG_TUH_CDC_FTDI
+      case SERIAL_DRIVER_FTDI:
+        switch (xfer->setup->bRequest) {
+          case FTDI_SIO_MODEM_CTRL:
+            p_cdc->line_state = (uint8_t) value;
+            break;
+
+          case FTDI_SIO_SET_BAUD_RATE:
+            p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+            break;
+
+          default: break;
+        }
+        break;
+      #endif
+
+      #if CFG_TUH_CDC_CP210X
+      case SERIAL_DRIVER_CP210X:
+        switch(xfer->setup->bRequest) {
+          case CP210X_SET_MHS:
+            p_cdc->line_state = (uint8_t) value;
+            break;
+
+          case CP210X_SET_BAUDRATE: {
+            uint32_t baudrate;
+            memcpy(&baudrate, xfer->buffer, sizeof(uint32_t));
+            p_cdc->line_coding.bit_rate = tu_le32toh(baudrate);
+            break;
+          }
+
+          default: break;
+        }
+        break;
+      #endif
+
+      #if CFG_TUH_CDC_CH34X
+      case SERIAL_DRIVER_CH34X:
+        switch (xfer->setup->bRequest) {
+          case CH34X_REQ_WRITE_REG:
+            // register write request
+            switch (value) {
+              case CH34X_REG16_DIVISOR_PRESCALER:
+                // baudrate
+                p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+                break;
+
+              case CH32X_REG16_LCR2_LCR:
+                // data format
+                p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
+                p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
+                p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
+                break;
+
+              default: break;
+            }
+            break;
+
+          case CH34X_REQ_MODEM_CTRL: {
+            // set modem controls RTS/DTR request. Note: signals are inverted
+            uint16_t const modem_signal = ~value;
+            if (modem_signal & CH34X_BIT_RTS) {
+              p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
+            } else {
+              p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
+            }
+
+            if (modem_signal & CH34X_BIT_DTR) {
+              p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
+            } else {
+              p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
+            }
+            break;
+          }
+
+          default: break;
+        }
+        break;
+      #endif
+
+      default: break;
+    }
+  }
+
+  xfer->complete_cb = p_cdc->user_control_cb;
+  if (xfer->complete_cb) {
+    xfer->complete_cb(xfer);
+  }
+}
+
+// internal control complete to update state such as line state, encoding
+static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  process_internal_control_complete(xfer, itf_num);
+}
+
+bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
+
+  if (complete_cb) {
+    return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data);
+  } else {
+    // blocking
+    xfer_result_t result = XFER_RESULT_INVALID;
+    bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
+
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
+    p_cdc->line_state = (uint8_t) line_state;
+    return true;
+  }
+}
+
+bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
+
+  if (complete_cb) {
+    return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data);
+  } else {
+    // blocking
+    xfer_result_t result = XFER_RESULT_INVALID;
+    bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
+
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.bit_rate = baudrate;
+    return true;
+  }
+}
+
+bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
+
+  if (complete_cb) {
+    return driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, user_data);
+  } else {
+    // blocking
+    xfer_result_t result = XFER_RESULT_INVALID;
+    bool ret = driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
+
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.stop_bits = stop_bits;
+    p_cdc->line_coding.parity = parity;
+    p_cdc->line_coding.data_bits = data_bits;
+    return true;
+  }
+}
+
+bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
+
+  if ( complete_cb ) {
+    return driver->set_line_coding(p_cdc, line_coding, complete_cb, user_data);
+  } else {
+    // blocking
+    xfer_result_t result = XFER_RESULT_INVALID;
+    bool ret = driver->set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
+
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding = *line_coding;
+    return true;
   }
 }
 
 //--------------------------------------------------------------------+
-// APPLICATION API (parameter validation needed)
+// CLASS-USBH API
 //--------------------------------------------------------------------+
-bool tuh_cdc_serial_is_mounted(uint8_t dev_addr)
-{
-  // TODO consider all AT Command as serial candidate
-  return tuh_cdc_mounted(dev_addr)                                         &&
-      (cdch_data[dev_addr-1].itf_protocol <= CDC_COMM_PROTOCOL_ATCOMMAND_CDMA);
+
+bool cdch_init(void) {
+  TU_LOG_DRV("sizeof(cdch_interface_t) = %u\r\n", sizeof(cdch_interface_t));
+  tu_memclr(cdch_data, sizeof(cdch_data));
+  for (size_t i = 0; i < CFG_TUH_CDC; i++) {
+    cdch_interface_t* p_cdc = &cdch_data[i];
+    cdch_epbuf_t* epbuf = &cdch_epbuf[i];
+    tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false,
+                        p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
+                        epbuf->tx, CFG_TUH_CDC_TX_EPSIZE);
+
+    tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false,
+                        p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
+                        epbuf->rx, CFG_TUH_CDC_RX_EPSIZE);
+  }
+
+  return true;
 }
 
-bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify)
-{
-  (void) is_notify;
-  TU_VERIFY( tuh_cdc_mounted(dev_addr) );
-  TU_VERIFY( p_data != NULL && length);
-
-  uint8_t const ep_out = cdch_data[dev_addr-1].ep_out;
-  if ( usbh_edpt_busy(dev_addr, ep_out) ) return false;
-
-  return usbh_edpt_xfer(dev_addr, ep_out, (void*)(uintptr_t) p_data, (uint16_t) length);
+bool cdch_deinit(void) {
+  for (size_t i = 0; i < CFG_TUH_CDC; i++) {
+    cdch_interface_t* p_cdc = &cdch_data[i];
+    tu_edpt_stream_deinit(&p_cdc->stream.tx);
+    tu_edpt_stream_deinit(&p_cdc->stream.rx);
+  }
+  return true;
 }
 
-bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify)
-{
-  (void) is_notify;
-  TU_VERIFY( tuh_cdc_mounted(dev_addr) );
-  TU_VERIFY( p_buffer != NULL && length );
+void cdch_close(uint8_t daddr) {
+  for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
+    cdch_interface_t* p_cdc = &cdch_data[idx];
+    if (p_cdc->daddr == daddr) {
+      TU_LOG_DRV("  CDCh close addr = %u index = %u\r\n", daddr, idx);
 
-  uint8_t const ep_in = cdch_data[dev_addr-1].ep_in;
-  if ( usbh_edpt_busy(dev_addr, ep_in) ) return false;
+      // Invoke application callback
+      if (tuh_cdc_umount_cb) {
+        tuh_cdc_umount_cb(idx);
+      }
 
-  return usbh_edpt_xfer(dev_addr, ep_in, p_buffer, (uint16_t) length);
+      p_cdc->daddr = 0;
+      p_cdc->bInterfaceNumber = 0;
+      p_cdc->mounted = false;
+      tu_edpt_stream_close(&p_cdc->stream.tx);
+      tu_edpt_stream_close(&p_cdc->stream.rx);
+    }
+  }
 }
 
-bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb)
-{
-  cdch_data_t const * p_cdc = get_itf(dev_addr);
+bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) {
+  // TODO handle stall response, retry failed transfer ...
+  TU_ASSERT(event == XFER_RESULT_SUCCESS);
 
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
+  uint8_t const idx = get_idx_by_ep_addr(daddr, ep_addr);
+  cdch_interface_t * p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc);
+
+  if ( ep_addr == p_cdc->stream.tx.ep_addr ) {
+    // invoke tx complete callback to possibly refill tx fifo
+    if (tuh_cdc_tx_complete_cb) {
+      tuh_cdc_tx_complete_cb(idx);
+    }
+
+    if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) {
+      // If there is no data left, a ZLP should be sent if:
+      // - xferred_bytes is multiple of EP Packet size and not zero
+      tu_edpt_stream_write_zlp_if_needed(daddr, &p_cdc->stream.tx, xferred_bytes);
+    }
+  } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
+    #if CFG_TUH_CDC_FTDI
+    if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) {
+      // FTDI reserve 2 bytes for status
+      // uint8_t status[2] = {p_cdc->stream.rx.ep_buf[0], p_cdc->stream.rx.ep_buf[1]};
+      tu_edpt_stream_read_xfer_complete_offset(&p_cdc->stream.rx, xferred_bytes, 2);
+    }else
+    #endif
     {
+      tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
+    }
+
+    // invoke receive callback
+    if (tuh_cdc_rx_cb) {
+      tuh_cdc_rx_cb(idx);
+    }
+
+    // prepare for next transfer if needed
+    tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx);
+  }else if ( ep_addr == p_cdc->ep_notif ) {
+    // TODO handle notification endpoint
+  }else {
+    TU_ASSERT(false);
+  }
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// Enumeration
+//--------------------------------------------------------------------+
+
+static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const* desc_ep) {
+  for (size_t i = 0; i < 2; i++) {
+    TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
+              TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
+    TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep));
+
+    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+      tu_edpt_stream_open(&p_cdc->stream.rx, desc_ep);
+    } else {
+      tu_edpt_stream_open(&p_cdc->stream.tx, desc_ep);
+    }
+
+    desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(desc_ep);
+  }
+
+  return true;
+}
+
+bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+  (void) rhport;
+
+  // For CDC: only support ACM subclass
+  // Note: Protocol 0xFF can be RNDIS device
+  if (TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
+      CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) {
+    return acm_open(daddr, itf_desc, max_len);
+  } else if (SERIAL_DRIVER_COUNT > 1 &&
+             TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
+    uint16_t vid, pid;
+    TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
+
+    for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) {
+      cdch_serial_driver_t const* driver = &serial_drivers[dr];
+      for (size_t i = 0; i < driver->vid_pid_count; i++) {
+        if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) {
+          return driver->open(daddr, itf_desc, max_len);
+        }
+      }
+    }
+  }
+
+  return false;
+}
+
+static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) {
+  TU_LOG_DRV("CDCh Set Configure complete\r\n");
+  p_cdc->mounted = true;
+  if (tuh_cdc_mount_cb) {
+    tuh_cdc_mount_cb(idx);
+  }
+
+  // Prepare for incoming data
+  tu_edpt_stream_read_xfer(p_cdc->daddr, &p_cdc->stream.rx);
+
+  // notify usbh that driver enumeration is complete
+  usbh_driver_set_config_complete(p_cdc->daddr, itf_num);
+}
+
+bool cdch_set_config(uint8_t daddr, uint8_t itf_num) {
+  tusb_control_request_t request;
+  request.wIndex = tu_htole16((uint16_t) itf_num);
+
+  // fake transfer to kick-off process
+  tuh_xfer_t xfer;
+  xfer.daddr  = daddr;
+  xfer.result = XFER_RESULT_SUCCESS;
+  xfer.setup  = &request;
+  xfer.user_data = 0; // initial state
+
+  uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
+  cdch_interface_t * p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+
+  serial_drivers[p_cdc->serial_drid].process_set_config(&xfer);
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ACM
+//--------------------------------------------------------------------+
+
+enum {
+  CONFIG_ACM_SET_CONTROL_LINE_STATE = 0,
+  CONFIG_ACM_SET_LINE_CODING,
+  CONFIG_ACM_COMPLETE,
+};
+
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  uint8_t const* p_desc_end = ((uint8_t const*) itf_desc) + max_len;
+
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY(p_cdc);
+  p_cdc->serial_drid = SERIAL_DRIVER_ACM;
+
+  //------------- Control Interface -------------//
+  uint8_t const* p_desc = tu_desc_next(itf_desc);
+
+  // Communication Functional Descriptors
+  while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) {
+    if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) {
+      // save ACM bmCapabilities
+      p_cdc->acm_capability = ((cdc_desc_func_acm_t const*) p_desc)->bmCapabilities;
+    }
+
+    p_desc = tu_desc_next(p_desc);
+  }
+
+  // Open notification endpoint of control interface if any
+  if (itf_desc->bNumEndpoints == 1) {
+    TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc));
+    tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc;
+
+    TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
+    p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+    p_desc = tu_desc_next(p_desc);
+  }
+
+  //------------- Data Interface (if any) -------------//
+  if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+      (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) {
+    // next to endpoint descriptor
+    p_desc = tu_desc_next(p_desc);
+
+    // data endpoints expected to be in pairs
+    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const*) p_desc));
+  }
+
+  return true;
+}
+
+static void acm_process_config(tuh_xfer_t* xfer) {
+  uintptr_t const state = xfer->user_data;
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc,);
+
+  switch (state) {
+    case CONFIG_ACM_SET_CONTROL_LINE_STATE:
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+      if (p_cdc->acm_capability.support_line_request) {
+        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, CONFIG_ACM_SET_LINE_CODING),);
+        break;
+      }
+      #endif
+      TU_ATTR_FALLTHROUGH;
+
+    case CONFIG_ACM_SET_LINE_CODING:
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      if (p_cdc->acm_capability.support_line_request) {
+        cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE),);
+        break;
+      }
+      #endif
+      TU_ATTR_FALLTHROUGH;
+
+    case CONFIG_ACM_COMPLETE:
+      // itf_num+1 to account for data interface as well
+      set_config_complete(p_cdc, idx, itf_num + 1);
+      break;
+
+    default:
+      break;
+  }
+}
+
+static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_VERIFY(p_cdc->acm_capability.support_line_request);
+  TU_LOG_DRV("CDC ACM Set Control Line State\r\n");
+
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
       .type      = TUSB_REQ_TYPE_CLASS,
       .direction = TUSB_DIR_OUT
     },
     .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
-    .wValue   = tu_htole16((uint16_t) ((dtr ? 1u : 0u) | (rts ? 2u : 0u))),
-    .wIndex   = tu_htole16(p_cdc->itf_num),
+    .wValue   = tu_htole16(line_state),
+    .wIndex   = tu_htole16((uint16_t) p_cdc->bInterfaceNumber),
     .wLength  = 0
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = dev_addr,
+  p_cdc->user_control_cb = complete_cb;
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = NULL,
+    .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call
+    .user_data   = user_data
+  };
+
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
+}
+
+static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_DRV("CDC ACM Set Line Conding\r\n");
+
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = CDC_REQUEST_SET_LINE_CODING,
+    .wValue   = 0,
+    .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
+    .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
+  };
+
+  // use usbh enum buf to hold line coding since user line_coding variable does not live long enough
+  uint8_t* enum_buf = usbh_get_enum_buf();
+  memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t));
+
+  p_cdc->user_control_cb = complete_cb;
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = enum_buf,
+    .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call
+    .user_data   = user_data
+  };
+
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
+}
+
+static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_DRV("CDC ACM Set Data Format\r\n");
+
+  cdc_line_coding_t line_coding;
+  line_coding.bit_rate = p_cdc->line_coding.bit_rate;
+  line_coding.stop_bits = stop_bits;
+  line_coding.parity = parity;
+  line_coding.data_bits = data_bits;
+
+  return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data);
+}
+
+static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_VERIFY(p_cdc->acm_capability.support_line_request);
+  cdc_line_coding_t line_coding = p_cdc->line_coding;
+  line_coding.bit_rate = baudrate;
+  return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data);
+}
+
+//--------------------------------------------------------------------+
+// FTDI
+//--------------------------------------------------------------------+
+#if CFG_TUH_CDC_FTDI
+
+enum {
+  CONFIG_FTDI_RESET = 0,
+  CONFIG_FTDI_MODEM_CTRL,
+  CONFIG_FTDI_SET_BAUDRATE,
+  CONFIG_FTDI_SET_DATA,
+  CONFIG_FTDI_COMPLETE
+};
+
+static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) {
+  // FTDI Interface includes 1 vendor interface + 2 bulk endpoints
+  TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2);
+  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY(p_cdc);
+
+  TU_LOG_DRV("FTDI opened\r\n");
+  p_cdc->serial_drid = SERIAL_DRIVER_FTDI;
+
+  // endpoint pair
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  return open_ep_stream_pair(p_cdc, desc_ep);
+}
+
+// set request without data
+static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_VENDOR,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = command,
+    .wValue   = tu_htole16(value),
+    .wIndex   = 0,
+    .wLength  = 0
+  };
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
-    .user_data    = 0
+    .user_data   = user_data
   };
 
   return tuh_control_xfer(&xfer);
 }
 
-//--------------------------------------------------------------------+
-// USBH-CLASS DRIVER API
-//--------------------------------------------------------------------+
-void cdch_init(void)
-{
-  tu_memclr(cdch_data, sizeof(cdch_data));
+static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
-bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
-  (void) rhport;
-  (void) max_len;
+static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) stop_bits;
+  (void) parity;
+  (void) data_bits;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
 
-  // Only support ACM subclass
-  // Protocol 0xFF can be RNDIS device for windows XP
-  TU_VERIFY( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
-             CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass &&
-             0xFF                                     != itf_desc->bInterfaceProtocol);
+static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) line_coding;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
 
-  cdch_data_t * p_cdc = get_itf(dev_addr);
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
+                                 complete_cb ? cdch_internal_control_complete : NULL, user_data));
+  return true;
+}
 
-  p_cdc->itf_num      = itf_desc->bInterfaceNumber;
-  p_cdc->itf_protocol = itf_desc->bInterfaceProtocol;
+static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) {
+  const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 };
+  uint32_t divisor;
 
-  //------------- Communication Interface -------------//
-  uint16_t drv_len = tu_desc_len(itf_desc);
-  uint8_t const * p_desc = tu_desc_next(itf_desc);
+  /* divisor shifted 3 bits to the left */
+  uint32_t divisor3 = base / (2 * baud);
+  divisor = (divisor3 >> 3);
+  divisor |= (uint32_t) divfrac[divisor3 & 0x7] << 14;
 
-  // Communication Functional Descriptors
-  while( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
-  {
-    if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
-    {
-      // save ACM bmCapabilities
-      p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
+  /* Deal with special cases for highest baud rates. */
+  if (divisor == 1) { /* 1.0 */
+    divisor = 0;
+  }
+  else if (divisor == 0x4001) { /* 1.5 */
+    divisor = 1;
+  }
+
+  return divisor;
+}
+
+static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) {
+  return ftdi_232bm_baud_base_to_divisor(baud, 48000000u);
+}
+
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
+  TU_LOG_DRV("CDC FTDI Set BaudRate = %" PRIu32 ", divisor = 0x%04x\r\n", baudrate, divisor);
+
+  p_cdc->user_control_cb = complete_cb;
+  p_cdc->requested_line_coding.bit_rate = baudrate;
+  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor,
+                                 complete_cb ? cdch_internal_control_complete : NULL, user_data));
+
+  return true;
+}
+
+static void ftdi_process_config(tuh_xfer_t* xfer) {
+  uintptr_t const state = xfer->user_data;
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t * p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
+
+  switch(state) {
+    // Note may need to read FTDI eeprom
+    case CONFIG_FTDI_RESET:
+      TU_ASSERT(ftdi_sio_reset(p_cdc, ftdi_process_config, CONFIG_FTDI_MODEM_CTRL),);
+      break;
+
+    case CONFIG_FTDI_MODEM_CTRL:
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+      TU_ASSERT(ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+
+    case CONFIG_FTDI_SET_BAUDRATE: {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, ftdi_process_config, CONFIG_FTDI_SET_DATA),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
     }
 
-    drv_len += tu_desc_len(p_desc);
-    p_desc = tu_desc_next(p_desc);
-  }
+    case CONFIG_FTDI_SET_DATA: {
+      #if 0 // TODO set data format
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE),);
+      break;
+      #endif
+      #endif
 
-  if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
-  {
-    // notification endpoint
-    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-
-    TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) );
-    p_cdc->ep_notif = desc_ep->bEndpointAddress;
-
-    drv_len += tu_desc_len(p_desc);
-    p_desc = tu_desc_next(p_desc);
-  }
-
-  //------------- Data Interface (if any) -------------//
-  if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
-       (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
-  {
-    // next to endpoint descriptor
-    drv_len += tu_desc_len(p_desc);
-    p_desc = tu_desc_next(p_desc);
-
-    // data endpoints expected to be in pairs
-    for(uint32_t i=0; i<2; i++)
-    {
-      tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-      TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
-
-      TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep));
-
-      if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
-      {
-        p_cdc->ep_in = desc_ep->bEndpointAddress;
-      }else
-      {
-        p_cdc->ep_out = desc_ep->bEndpointAddress;
-      }
-
-      drv_len += tu_desc_len(p_desc);
-      p_desc = tu_desc_next( p_desc );
+      TU_ATTR_FALLTHROUGH;
     }
+
+    case CONFIG_FTDI_COMPLETE:
+      set_config_complete(p_cdc, idx, itf_num);
+      break;
+
+    default:
+      break;
   }
-
-  return true;
-}
-
-bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
-{
-  (void) dev_addr; (void) itf_num;
-  return true;
-}
-
-bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
-{
-  (void) ep_addr;
-  tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes );
-  return true;
-}
-
-void cdch_close(uint8_t dev_addr)
-{
-  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
-
-  cdch_data_t * p_cdc = get_itf(dev_addr);
-  tu_memclr(p_cdc, sizeof(cdch_data_t));
 }
 
 #endif
+
+//--------------------------------------------------------------------+
+// CP210x
+//--------------------------------------------------------------------+
+
+#if CFG_TUH_CDC_CP210X
+
+enum {
+  CONFIG_CP210X_IFC_ENABLE = 0,
+  CONFIG_CP210X_SET_BAUDRATE,
+  CONFIG_CP210X_SET_LINE_CTL,
+  CONFIG_CP210X_SET_DTR_RTS,
+  CONFIG_CP210X_COMPLETE
+};
+
+static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+  // CP210x Interface includes 1 vendor interface + 2 bulk endpoints
+  TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2);
+  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY(p_cdc);
+
+  TU_LOG_DRV("CP210x opened\r\n");
+  p_cdc->serial_drid = SERIAL_DRIVER_CP210X;
+
+  // endpoint pair
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  return open_ep_stream_pair(p_cdc, desc_ep);
+}
+
+static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_VENDOR,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = command,
+    .wValue   = tu_htole16(value),
+    .wIndex   = p_cdc->bInterfaceNumber,
+    .wLength  = tu_htole16(length)
+  };
+
+  // use usbh enum buf since application variable does not live long enough
+  uint8_t* enum_buf = NULL;
+
+  if (buffer && length > 0) {
+    enum_buf = usbh_get_enum_buf();
+    tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
+  }
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = enum_buf,
+    .complete_cb = complete_cb,
+    .user_data   = user_data
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
+static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data);
+}
+
+static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  // TODO implement later
+  (void) p_cdc;
+  (void) line_coding;
+  (void) complete_cb;
+  (void) user_data;
+  return false;
+}
+
+static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_DRV("CDC CP210x Set BaudRate = %" PRIu32 "\r\n", baudrate);
+  uint32_t baud_le = tu_htole32(baudrate);
+  p_cdc->user_control_cb = complete_cb;
+  return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4,
+                            complete_cb ? cdch_internal_control_complete : NULL, user_data);
+}
+
+static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) stop_bits;
+  (void) parity;
+  (void) data_bits;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
+
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_DRV("CDC CP210x Set Control Line State\r\n");
+  p_cdc->user_control_cb = complete_cb;
+  return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0,
+                            complete_cb ? cdch_internal_control_complete : NULL, user_data);
+}
+
+static void cp210x_process_config(tuh_xfer_t* xfer) {
+  uintptr_t const state   = xfer->user_data;
+  uint8_t const   itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const   idx     = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t *p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc,);
+
+  switch (state) {
+    case CONFIG_CP210X_IFC_ENABLE:
+      TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, cp210x_process_config, CONFIG_CP210X_SET_BAUDRATE),);
+      break;
+
+    case CONFIG_CP210X_SET_BAUDRATE: {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, cp210x_process_config, CONFIG_CP210X_SET_LINE_CTL),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+    }
+
+    case CONFIG_CP210X_SET_LINE_CTL: {
+      #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+    }
+
+    case CONFIG_CP210X_SET_DTR_RTS:
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+      TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+
+    case CONFIG_CP210X_COMPLETE:
+      set_config_complete(p_cdc, idx, itf_num);
+      break;
+
+    default: break;
+  }
+}
+
+#endif
+
+//--------------------------------------------------------------------+
+// CH34x (CH340 & CH341)
+//--------------------------------------------------------------------+
+
+#if CFG_TUH_CDC_CH34X
+
+static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits);
+static uint16_t ch34x_get_divisor_prescaler(uint32_t baval);
+
+//------------- control request -------------//
+
+static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value,
+                              uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request_setup = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_DEVICE,
+          .type      = TUSB_REQ_TYPE_VENDOR,
+          .direction = direction & 0x01u
+      },
+      .bRequest = request,
+      .wValue   = tu_htole16 (value),
+      .wIndex   = tu_htole16 (index),
+      .wLength  = tu_htole16 (length)
+  };
+
+  // use usbh enum buf since application variable does not live long enough
+  uint8_t* enum_buf = NULL;
+
+  if (buffer && length > 0) {
+    enum_buf = usbh_get_enum_buf();
+    if (direction == TUSB_DIR_OUT) {
+      tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
+    }
+  }
+
+  tuh_xfer_t xfer = {
+      .daddr       = p_cdc->daddr,
+      .ep_addr     = 0,
+      .setup       = &request_setup,
+      .buffer      = enum_buf,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
+static inline bool ch34x_control_out(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, NULL, 0, complete_cb, user_data);
+}
+
+static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                                    uint8_t* buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_set_request(p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize,
+                           complete_cb, user_data);
+}
+
+static inline bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data);
+}
+
+//static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg,
+//                                     uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+//{
+//  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data );
+//}
+
+static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
+  TU_VERIFY(div_ps);
+  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
+                            complete_cb, user_data));
+  return true;
+}
+
+//------------- Driver API -------------//
+
+// internal control complete to update state such as line state, encoding
+static void ch34x_control_complete(tuh_xfer_t* xfer) {
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  process_internal_control_complete(xfer, 0);
+}
+
+static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding.stop_bits = stop_bits;
+  p_cdc->requested_line_coding.parity = parity;
+  p_cdc->requested_line_coding.data_bits = data_bits;
+
+  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+  TU_VERIFY(lcr);
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
+}
+
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding.bit_rate = baudrate;
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, baudrate,
+                                     complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
+}
+
+static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) {
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  uint8_t const itf_num = 0;
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
+
+  if (xfer->result == XFER_RESULT_SUCCESS) {
+    // stage 1 success, continue to stage 2
+    p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+    TU_ASSERT(ch34x_set_data_format(p_cdc, p_cdc->requested_line_coding.stop_bits, p_cdc->requested_line_coding.parity,
+                                    p_cdc->requested_line_coding.data_bits, ch34x_control_complete, xfer->user_data), );
+  } else {
+    // stage 1 failed, notify user
+    xfer->complete_cb = p_cdc->user_control_cb;
+    if (xfer->complete_cb) {
+      xfer->complete_cb(xfer);
+    }
+  }
+}
+
+// 2 stages: set baudrate (stage1) + set data format (stage2)
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding = *line_coding;
+  p_cdc->user_control_cb = complete_cb;
+
+  if (complete_cb) {
+    // stage 1 set baudrate
+    TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate,
+                                       ch34x_set_line_coding_stage1_complete, user_data));
+  } else {
+    // sync call
+    xfer_result_t result;
+
+    // stage 1 set baudrate
+    TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate, NULL, (uintptr_t) &result));
+    TU_VERIFY(result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.bit_rate = line_coding->bit_rate;
+
+    // stage 2 set data format
+    TU_ASSERT(ch34x_set_data_format(p_cdc, line_coding->stop_bits, line_coding->parity, line_coding->data_bits,
+                                    NULL, (uintptr_t) &result));
+    TU_VERIFY(result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.stop_bits = line_coding->stop_bits;
+    p_cdc->line_coding.parity = line_coding->parity;
+    p_cdc->line_coding.data_bits = line_coding->data_bits;
+
+    // update transfer result, user_data is expected to point to xfer_result_t
+    if (user_data) {
+      *((xfer_result_t*) user_data) = result;
+    }
+  }
+
+  return true;
+}
+
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
+                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  uint8_t control = 0;
+  if (line_state & CDC_CONTROL_LINE_STATE_RTS) {
+    control |= CH34X_BIT_RTS;
+  }
+  if (line_state & CDC_CONTROL_LINE_STATE_DTR) {
+    control |= CH34X_BIT_DTR;
+  }
+
+  // CH34x signals are inverted
+  control = ~control;
+
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0,
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
+}
+
+//------------- Enumeration -------------//
+enum {
+  CONFIG_CH34X_READ_VERSION = 0,
+  CONFIG_CH34X_SERIAL_INIT,
+  CONFIG_CH34X_SPECIAL_REG_WRITE,
+  CONFIG_CH34X_FLOW_CONTROL,
+  CONFIG_CH34X_MODEM_CONTROL,
+  CONFIG_CH34X_COMPLETE
+};
+
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
+  TU_VERIFY (itf_desc->bNumEndpoints == 3);
+  TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY (p_cdc);
+
+  TU_LOG_DRV ("CH34x opened\r\n");
+  p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
+
+  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
+  desc_ep += 2;
+
+  // Interrupt endpoint: not used for now
+  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) &&
+            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer);
+  TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
+  p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+  return true;
+}
+
+static void ch34x_process_config(tuh_xfer_t* xfer) {
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  uint8_t const itf_num = 0;
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  uintptr_t const state = xfer->user_data;
+  uint8_t buffer[2]; // TODO remove
+  TU_ASSERT (p_cdc,);
+  TU_ASSERT (xfer->result == XFER_RESULT_SUCCESS,);
+
+  switch (state) {
+    case CONFIG_CH34X_READ_VERSION:
+      TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
+      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
+      break;
+
+    case CONFIG_CH34X_SERIAL_INIT: {
+      // handle version read data, set CH34x line coding (incl. baudrate)
+      uint8_t const version = xfer->buffer[0];
+      TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
+      // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
+      TU_ASSERT (version >= 0x30,);
+      // init CH34x with line coding
+      cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
+      uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
+      TU_ASSERT(div_ps, );
+      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      TU_ASSERT(lcr, );
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
+                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
+      break;
+    }
+
+    case CONFIG_CH34X_SPECIAL_REG_WRITE:
+      // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver
+      p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X);
+      TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
+      break;
+
+    case CONFIG_CH34X_FLOW_CONTROL:
+      // no hardware flow control
+      TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
+      break;
+
+    case CONFIG_CH34X_MODEM_CONTROL:
+      // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
+      TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
+      break;
+
+    case CONFIG_CH34X_COMPLETE:
+      set_config_complete(p_cdc, idx, itf_num);
+      break;
+
+    default:
+      TU_ASSERT (false,);
+      break;
+  }
+}
+
+//------------- CH34x helper  -------------//
+
+// calculate divisor and prescaler for baudrate, return it as 16-bit combined value
+static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
+  uint8_t a;
+  uint8_t b;
+  uint32_t c;
+
+  TU_VERIFY(baval != 0 && baval <= 2000000, 0);
+  switch (baval) {
+    case 921600:
+      a = 0xf3;
+      b = 7;
+      break;
+
+    case 307200:
+      a = 0xd9;
+      b = 7;
+      break;
+
+    default:
+      if (baval > 6000000 / 255) {
+        b = 3;
+        c = 6000000;
+      } else if (baval > 750000 / 255) {
+        b = 2;
+        c = 750000;
+      } else if (baval > 93750 / 255) {
+        b = 1;
+        c = 93750;
+      } else {
+        b = 0;
+        c = 11719;
+      }
+      a = (uint8_t) (c / baval);
+      if (a == 0 || a == 0xFF) {
+        return 0;
+      }
+      if ((c / a - baval) > (baval - c / (a + 1))) {
+        a++;
+      }
+      a = (uint8_t) (256 - a);
+      break;
+  }
+
+  // reg divisor = a, reg prescaler = b
+  // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE,
+  // otherwise the chip will buffer data.
+  return (uint16_t) ((uint16_t)a << 8 | 0x80 | b);
+}
+
+// calculate lcr value from data coding
+static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
+  uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
+  TU_VERIFY(data_bits >= 5 && data_bits <= 8, 0);
+  lcr |= (uint8_t) (data_bits - 5);
+
+  switch(parity) {
+    case CDC_LINE_CODING_PARITY_NONE:
+      break;
+
+    case CDC_LINE_CODING_PARITY_ODD:
+      lcr |= CH34X_LCR_ENABLE_PAR;
+      break;
+
+    case CDC_LINE_CODING_PARITY_EVEN:
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN;
+      break;
+
+    case CDC_LINE_CODING_PARITY_MARK:
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE;
+      break;
+
+    case CDC_LINE_CODING_PARITY_SPACE:
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
+      break;
+
+    default: break;
+  }
+
+  // 1.5 stop bits not supported
+  TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0);
+  if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+    lcr |= CH34X_LCR_STOP_BITS_2;
+  }
+
+  return lcr;
+}
+
+
+#endif // CFG_TUH_CDC_CH34X
+
+#endif
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 33dbd2efb..df975b2f0 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -34,94 +34,165 @@
 #endif
 
 //--------------------------------------------------------------------+
-// CDC APPLICATION PUBLIC API
+// Class Driver Configuration
 //--------------------------------------------------------------------+
-/** \ingroup ClassDriver_CDC Communication Device Class (CDC)
- * \addtogroup CDC_Serial Serial
- * @{
- * \defgroup   CDC_Serial_Host Host
- * @{ */
 
-bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb);
+// Set Line Control state on enumeration/mounted: DTR ( bit 0), RTS (bit 1)
+#ifndef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0
+#endif
 
-static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb)
-{
-  return tuh_cdc_set_control_line_state(dev_addr, true, true, complete_cb);
+// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
+//#ifndef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+//#endif
+
+// RX FIFO size
+#ifndef CFG_TUH_CDC_RX_BUFSIZE
+#define CFG_TUH_CDC_RX_BUFSIZE USBH_EPSIZE_BULK_MAX
+#endif
+
+// RX Endpoint size
+#ifndef CFG_TUH_CDC_RX_EPSIZE
+#define CFG_TUH_CDC_RX_EPSIZE  USBH_EPSIZE_BULK_MAX
+#endif
+
+// TX FIFO size
+#ifndef CFG_TUH_CDC_TX_BUFSIZE
+#define CFG_TUH_CDC_TX_BUFSIZE USBH_EPSIZE_BULK_MAX
+#endif
+
+// TX Endpoint size
+#ifndef CFG_TUH_CDC_TX_EPSIZE
+#define CFG_TUH_CDC_TX_EPSIZE  USBH_EPSIZE_BULK_MAX
+#endif
+
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
+
+// Get Interface index from device address + interface number
+// return TUSB_INDEX_INVALID_8 (0xFF) if not found
+uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num);
+
+// Get Interface information
+// return true if index is correct and interface is currently mounted
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info);
+
+// Check if a interface is mounted
+bool tuh_cdc_mounted(uint8_t idx);
+
+// Get current DTR status
+bool tuh_cdc_get_dtr(uint8_t idx);
+
+// Get current RTS status
+bool tuh_cdc_get_rts(uint8_t idx);
+
+// Check if interface is connected (DTR active)
+TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx) {
+  return tuh_cdc_get_dtr(idx);
 }
 
-static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb)
-{
-  return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb);
+// Get local (saved/cached) version of line coding.
+// This function should return correct values if tuh_cdc_set_line_coding() / tuh_cdc_get_line_coding()
+// are invoked previously or CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined.
+// NOTE: This function does not make any USB transfer request to device.
+bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding);
+
+//--------------------------------------------------------------------+
+// Write API
+//--------------------------------------------------------------------+
+
+// Get the number of bytes available for writing
+uint32_t tuh_cdc_write_available(uint8_t idx);
+
+// Write to cdc interface
+uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize);
+
+// Force sending data if possible, return number of forced bytes
+uint32_t tuh_cdc_write_flush(uint8_t idx);
+
+// Clear the transmit FIFO
+bool tuh_cdc_write_clear(uint8_t idx);
+
+//--------------------------------------------------------------------+
+// Read API
+//--------------------------------------------------------------------+
+
+// Get the number of bytes available for reading
+uint32_t tuh_cdc_read_available(uint8_t idx);
+
+// Read from cdc interface
+uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize);
+
+// Get a byte from RX FIFO without removing it
+bool tuh_cdc_peek(uint8_t idx, uint8_t* ch);
+
+// Clear the received FIFO
+bool tuh_cdc_read_clear (uint8_t idx);
+
+//--------------------------------------------------------------------+
+// Control Endpoint (Request) API
+// Each Function will make a USB control transfer request to/from device
+// - If complete_cb is provided, the function will return immediately and invoke
+// the callback when request is complete.
+// - If complete_cb is NULL, the function will block until request is complete.
+//   - In this case, user_data should be pointed to xfer_result_t to hold the transfer result.
+//   - The function will return true if transfer is successful, false otherwise.
+//--------------------------------------------------------------------+
+
+// Request to Set Control Line State: DTR (bit 0), RTS (bit 1)
+bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+// Request to set baudrate
+bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+// Request to set data format
+bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+// Request to Set Line Coding = baudrate + data format
+// Note: only implemented by ACM and CH34x, not supported by FTDI and CP210x yet
+bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+// Request to Get Line Coding (ACM only)
+// Should only use if tuh_cdc_set_line_coding() / tuh_cdc_get_line_coding() never got invoked and
+// CFG_TUH_CDC_LINE_CODING_ON_ENUM is not defined
+// bool tuh_cdc_get_line_coding(uint8_t idx, cdc_line_coding_t* coding);
+
+// Connect by set both DTR, RTS
+TU_ATTR_ALWAYS_INLINE static inline
+bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data);
 }
 
-/** \brief 			Check if device support CDC Serial interface or not
- * \param[in]		dev_addr	device address
- * \retval      true if device supports
- * \retval      false if device does not support or is not mounted
- */
-bool tuh_cdc_serial_is_mounted(uint8_t dev_addr);
-
-/** \brief      Check if the interface is currently busy or not
- * \param[in]   dev_addr device address
- * \param[in]   pipeid value from \ref cdc_pipeid_t to indicate target pipe.
- * \retval      true if the interface is busy, meaning the stack is still transferring/waiting data from/to device
- * \retval      false if the interface is not busy, meaning the stack successfully transferred data from/to device
- * \note        This function is used to check if previous transfer is complete (success or error), so that the next transfer
- *              can be scheduled. User needs to make sure the corresponding interface is mounted
- *              (by \ref tuh_cdc_serial_is_mounted) before calling this function.
- */
-bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid);
-
-/** \brief 			Perform USB OUT transfer to device
- * \param[in]		dev_addr	device address
- * \param[in]	  p_data    Buffer containing data. Must be accessible by USB controller (see \ref CFG_TUSB_MEM_SECTION)
- * \param[in]		length    Number of bytes to be transferred via USB bus
- * \retval      TUSB_ERROR_NONE on success
- * \retval      TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device
- * \retval      TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request)
- * \retval      TUSB_ERROR_INVALID_PARA if input parameters are not correct
- * \note        This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
- *              interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
- */
-bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify);
-
-/** \brief 			Perform USB IN transfer to get data from device
- * \param[in]		dev_addr	device address
- * \param[in]	  p_buffer  Buffer containing received data. Must be accessible by USB controller (see \ref CFG_TUSB_MEM_SECTION)
- * \param[in]		length    Number of bytes to be transferred via USB bus
- * \retval      TUSB_ERROR_NONE on success
- * \retval      TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device
- * \retval      TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request)
- * \retval      TUSB_ERROR_INVALID_PARA if input parameters are not correct
- * \note        This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
- *              interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
- */
-bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify);
+// Disconnect by clear both DTR, RTS
+TU_ATTR_ALWAYS_INLINE static inline
+bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data);
+}
 
 //--------------------------------------------------------------------+
 // CDC APPLICATION CALLBACKS
 //--------------------------------------------------------------------+
 
-/** \brief      Callback function that is invoked when an transferring event occurred
- * \param[in]		dev_addr	Address of device
- * \param[in]   event an value from \ref xfer_result_t
- * \param[in]   pipe_id value from \ref cdc_pipeid_t indicate the pipe
- * \param[in]   xferred_bytes Number of bytes transferred via USB bus
- * \note        event can be one of following
- *              - XFER_RESULT_SUCCESS : previously scheduled transfer completes successfully.
- *              - XFER_RESULT_FAILED   : previously scheduled transfer encountered a transaction error.
- *              - XFER_RESULT_STALLED : previously scheduled transfer is stalled by device.
- * \note
- */
-void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes);
+// Invoked when a device with CDC interface is mounted
+// idx is index of cdc interface in the internal pool.
+TU_ATTR_WEAK extern void tuh_cdc_mount_cb(uint8_t idx);
 
-/// @} // group CDC_Serial_Host
-/// @}
+// Invoked when a device with CDC interface is unmounted
+TU_ATTR_WEAK extern void tuh_cdc_umount_cb(uint8_t idx);
+
+// Invoked when received new data
+TU_ATTR_WEAK extern void tuh_cdc_rx_cb(uint8_t idx);
+
+// Invoked when a TX is complete and therefore space becomes available in TX buffer
+TU_ATTR_WEAK extern void tuh_cdc_tx_complete_cb(uint8_t idx);
 
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void cdch_init       (void);
+bool cdch_init       (void);
+bool cdch_deinit     (void);
 bool cdch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 bool cdch_set_config (uint8_t dev_addr, uint8_t itf_num);
 bool cdch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
diff --git a/src/class/cdc/cdc_rndis.h b/src/class/cdc/cdc_rndis.h
index e0f129fe3..ad153e0ac 100644
--- a/src/class/cdc/cdc_rndis.h
+++ b/src/class/cdc/cdc_rndis.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c
index 8f28f51ac..11a5355aa 100644
--- a/src/class/cdc/cdc_rndis_host.c
+++ b/src/class/cdc/cdc_rndis_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -50,8 +50,8 @@
 //--------------------------------------------------------------------+
 #define RNDIS_MSG_PAYLOAD_MAX   (1024*4)
 
-CFG_TUSB_MEM_SECTION static uint8_t msg_notification[CFG_TUH_DEVICE_MAX][8];
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX];
+CFG_TUH_MEM_SECTION static uint8_t msg_notification[CFG_TUH_DEVICE_MAX][8];
+CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX];
 
 static rndish_data_t rndish_data[CFG_TUH_DEVICE_MAX];
 
@@ -117,7 +117,7 @@ void rndish_init(void)
 
   //------------- Task creation -------------//
 
-  //------------- semaphore creation for notificaiton pipe -------------//
+  //------------- semaphore creation for notification pipe -------------//
   for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
   {
     rndish_data[i].sem_notification_hdl = osal_semaphore_create( OSAL_SEM_REF(rndish_data[i].semaphore_notification) );
diff --git a/src/class/cdc/cdc_rndis_host.h b/src/class/cdc/cdc_rndis_host.h
index 447cc4e97..bb431ec1f 100644
--- a/src/class/cdc/cdc_rndis_host.h
+++ b/src/class/cdc/cdc_rndis_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
new file mode 100644
index 000000000..c18066f57
--- /dev/null
+++ b/src/class/cdc/serial/ch34x.h
@@ -0,0 +1,84 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Heiko Kuester
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CH34X_H_
+#define _CH34X_H_
+
+// There is no official documentation for the CH34x (CH340, CH341) chips. Reference can be found
+// - https://github.com/WCHSoftGroup/ch341ser_linux
+// - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
+// - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c
+
+// set line_coding @ enumeration
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#else // this default is necessary to work properly
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+#endif
+
+// USB requests
+#define CH34X_REQ_READ_VERSION 0x5F // dec  95
+#define CH34X_REQ_WRITE_REG    0x9A // dec 154
+#define CH34X_REQ_READ_REG     0x95 // dec 149
+#define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
+#define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
+
+// registers
+#define CH34X_REG_BREAK        0x05
+#define CH34X_REG_PRESCALER    0x12
+#define CH34X_REG_DIVISOR      0x13
+#define CH34X_REG_LCR          0x18
+#define CH34X_REG_LCR2         0x25
+#define CH34X_REG_MCR_MSR      0x06
+#define CH34X_REG_MCR_MSR2     0x07
+#define CH34X_NBREAK_BITS      0x01
+
+#define CH341_REG_0x0F         0x0F // undocumented register
+#define CH341_REG_0x2C         0x2C // undocumented register
+#define CH341_REG_0x27         0x27 // hardware flow control (cts/rts)
+
+#define CH34X_REG16_DIVISOR_PRESCALER  TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+#define CH32X_REG16_LCR2_LCR           TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)
+
+// modem control bits
+#define CH34X_BIT_RTS ( 1 << 6 )
+#define CH34X_BIT_DTR ( 1 << 5 )
+
+// line control bits
+#define CH34X_LCR_ENABLE_RX    0x80
+#define CH34X_LCR_ENABLE_TX    0x40
+#define CH34X_LCR_MARK_SPACE   0x20
+#define CH34X_LCR_PAR_EVEN     0x10
+#define CH34X_LCR_ENABLE_PAR   0x08
+#define CH34X_LCR_PAR_MASK     0x38 // all parity bits
+#define CH34X_LCR_STOP_BITS_2  0x04
+#define CH34X_LCR_CS8          0x03
+#define CH34X_LCR_CS7          0x02
+#define CH34X_LCR_CS6          0x01
+#define CH34X_LCR_CS5          0x00
+#define CH34X_LCR_CS_MASK      0x03 // all CSx bits
+
+#endif /* _CH34X_H_ */
diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h
new file mode 100644
index 000000000..2c749f522
--- /dev/null
+++ b/src/class/cdc/serial/cp210x.h
@@ -0,0 +1,62 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TUSB_CP210X_H
+#define TUSB_CP210X_H
+
+// Protocol details can be found at AN571: CP210x Virtual COM Port Interface
+// https://www.silabs.com/documents/public/application-notes/AN571.pdf
+
+#define TU_CP210X_VID 0x10C4
+
+/* Config request codes */
+#define CP210X_IFC_ENABLE      0x00
+#define CP210X_SET_BAUDDIV     0x01
+#define CP210X_GET_BAUDDIV     0x02
+#define CP210X_SET_LINE_CTL    0x03 // Set parity, data bits, stop bits
+#define CP210X_GET_LINE_CTL    0x04
+#define CP210X_SET_BREAK       0x05
+#define CP210X_IMM_CHAR        0x06
+#define CP210X_SET_MHS         0x07 // Set DTR, RTS
+#define CP210X_GET_MDMSTS      0x08 // Get modem status (DTR, RTS, CTS, DSR, RI, DCD)
+#define CP210X_SET_XON         0x09
+#define CP210X_SET_XOFF        0x0A
+#define CP210X_SET_EVENTMASK   0x0B
+#define CP210X_GET_EVENTMASK   0x0C
+#define CP210X_SET_CHAR        0x0D
+#define CP210X_GET_CHARS       0x0E
+#define CP210X_GET_PROPS       0x0F
+#define CP210X_GET_COMM_STATUS 0x10
+#define CP210X_RESET           0x11
+#define CP210X_PURGE           0x12
+#define CP210X_SET_FLOW        0x13
+#define CP210X_GET_FLOW        0x14
+#define CP210X_EMBED_EVENTS    0x15
+#define CP210X_GET_EVENTSTATE  0x16
+#define CP210X_SET_CHARS       0x19
+#define CP210X_GET_BAUDRATE    0x1D
+#define CP210X_SET_BAUDRATE    0x1E
+#define CP210X_VENDOR_SPECIFIC 0xFF // GPIO, Recipient must be Device
+
+#endif //TUSB_CP210X_H
diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h
new file mode 100644
index 000000000..0825f0719
--- /dev/null
+++ b/src/class/cdc/serial/ftdi_sio.h
@@ -0,0 +1,246 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TUSB_FTDI_SIO_H
+#define TUSB_FTDI_SIO_H
+
+// VID for matching FTDI devices
+#define TU_FTDI_VID 0x0403
+
+// Commands
+#define FTDI_SIO_RESET             	0    /* Reset the port */
+#define FTDI_SIO_MODEM_CTRL        	1    /* Set the modem control register */
+#define FTDI_SIO_SET_FLOW_CTRL     	2    /* Set flow control register */
+#define FTDI_SIO_SET_BAUD_RATE     	3    /* Set baud rate */
+#define FTDI_SIO_SET_DATA          	4    /* Set the data characteristics of the port */
+#define FTDI_SIO_GET_MODEM_STATUS  	5    /* Retrieve current value of modem status register */
+#define FTDI_SIO_SET_EVENT_CHAR    	6    /* Set the event character */
+#define FTDI_SIO_SET_ERROR_CHAR    	7    /* Set the error character */
+#define FTDI_SIO_SET_LATENCY_TIMER 	9    /* Set the latency timer */
+#define FTDI_SIO_GET_LATENCY_TIMER 	0x0a /* Get the latency timer */
+#define FTDI_SIO_SET_BITMODE       	0x0b /* Set bitbang mode */
+#define FTDI_SIO_READ_PINS         	0x0c /* Read immediate value of pins */
+#define FTDI_SIO_READ_EEPROM       	0x90 /* Read EEPROM */
+
+/* FTDI_SIO_RESET */
+#define FTDI_SIO_RESET_SIO 0
+#define FTDI_SIO_RESET_PURGE_RX 1
+#define FTDI_SIO_RESET_PURGE_TX 2
+
+/*
+ * BmRequestType:  0100 0000B
+ * bRequest:       FTDI_SIO_RESET
+ * wValue:         Control Value
+ *                   0 = Reset SIO
+ *                   1 = Purge RX buffer
+ *                   2 = Purge TX buffer
+ * wIndex:         Port
+ * wLength:        0
+ * Data:           None
+ *
+ * The Reset SIO command has this effect:
+ *
+ *    Sets flow control set to 'none'
+ *    Event char = $0D
+ *    Event trigger = disabled
+ *    Purge RX buffer
+ *    Purge TX buffer
+ *    Clear DTR
+ *    Clear RTS
+ *    baud and data format not reset
+ *
+ * The Purge RX and TX buffer commands affect nothing except the buffers
+ *
+   */
+
+/* FTDI_SIO_MODEM_CTRL */
+/*
+ * BmRequestType:   0100 0000B
+ * bRequest:        FTDI_SIO_MODEM_CTRL
+ * wValue:          ControlValue (see below)
+ * wIndex:          Port
+ * wLength:         0
+ * Data:            None
+ *
+ * NOTE: If the device is in RTS/CTS flow control, the RTS set by this
+ * command will be IGNORED without an error being returned
+ * Also - you can not set DTR and RTS with one control message
+ */
+
+#define FTDI_SIO_SET_DTR_MASK 0x1
+#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1)
+#define FTDI_SIO_SET_DTR_LOW  ((FTDI_SIO_SET_DTR_MASK << 8) | 0)
+#define FTDI_SIO_SET_RTS_MASK 0x2
+#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2)
+#define FTDI_SIO_SET_RTS_LOW  ((FTDI_SIO_SET_RTS_MASK << 8) | 0)
+
+/*
+ * ControlValue
+ * B0    DTR state
+ *          0 = reset
+ *          1 = set
+ * B1    RTS state
+ *          0 = reset
+ *          1 = set
+ * B2..7 Reserved
+ * B8    DTR state enable
+ *          0 = ignore
+ *          1 = use DTR state
+ * B9    RTS state enable
+ *          0 = ignore
+ *          1 = use RTS state
+ * B10..15 Reserved
+ */
+
+/* FTDI_SIO_SET_FLOW_CTRL */
+#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0
+#define FTDI_SIO_RTS_CTS_HS (0x1 << 8)
+#define FTDI_SIO_DTR_DSR_HS (0x2 << 8)
+#define FTDI_SIO_XON_XOFF_HS (0x4 << 8)
+
+/*
+ *   BmRequestType:  0100 0000b
+ *   bRequest:       FTDI_SIO_SET_FLOW_CTRL
+ *   wValue:         Xoff/Xon
+ *   wIndex:         Protocol/Port - hIndex is protocol / lIndex is port
+ *   wLength:        0
+ *   Data:           None
+ *
+ * hIndex protocol is:
+ *   B0 Output handshaking using RTS/CTS
+ *       0 = disabled
+ *       1 = enabled
+ *   B1 Output handshaking using DTR/DSR
+ *       0 = disabled
+ *       1 = enabled
+ *   B2 Xon/Xoff handshaking
+ *       0 = disabled
+ *       1 = enabled
+ *
+ * A value of zero in the hIndex field disables handshaking
+ *
+ * If Xon/Xoff handshaking is specified, the hValue field should contain the
+ * XOFF character and the lValue field contains the XON character.
+ */
+
+/* FTDI_SIO_SET_BAUD_RATE */
+/*
+ * BmRequestType:  0100 0000B
+ * bRequest:       FTDI_SIO_SET_BAUDRATE
+ * wValue:         BaudDivisor value - see below
+ * wIndex:         Port
+ * wLength:        0
+ * Data:           None
+ * The BaudDivisor values are calculated as follows (too complicated):
+ */
+
+/* FTDI_SIO_SET_DATA */
+#define FTDI_SIO_SET_DATA_PARITY_NONE	(0x0 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_ODD	(0x1 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_EVEN	(0x2 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_MARK	(0x3 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_SPACE	(0x4 << 8)
+#define FTDI_SIO_SET_DATA_STOP_BITS_1	(0x0 << 11)
+#define FTDI_SIO_SET_DATA_STOP_BITS_15	(0x1 << 11)
+#define FTDI_SIO_SET_DATA_STOP_BITS_2	(0x2 << 11)
+#define FTDI_SIO_SET_BREAK		(0x1 << 14)
+
+/*
+ * BmRequestType:  0100 0000B
+ * bRequest:       FTDI_SIO_SET_DATA
+ * wValue:         Data characteristics (see below)
+ * wIndex:         Port
+ * wLength:        0
+ * Data:           No
+ *
+ * Data characteristics
+ *
+ *   B0..7   Number of data bits
+ *   B8..10  Parity
+ *           0 = None
+ *           1 = Odd
+ *           2 = Even
+ *           3 = Mark
+ *           4 = Space
+ *   B11..13 Stop Bits
+ *           0 = 1
+ *           1 = 1.5
+ *           2 = 2
+ *   B14
+ *           1 = TX ON (break)
+ *           0 = TX OFF (normal state)
+ *   B15 Reserved
+ *
+ */
+
+/*
+* DATA FORMAT
+*
+* IN Endpoint
+*
+* The device reserves the first two bytes of data on this endpoint to contain
+* the current values of the modem and line status registers. In the absence of
+* data, the device generates a message consisting of these two status bytes
+  * every 40 ms
+  *
+  * Byte 0: Modem Status
+*
+* Offset	Description
+* B0	Reserved - must be 1
+* B1	Reserved - must be 0
+* B2	Reserved - must be 0
+* B3	Reserved - must be 0
+* B4	Clear to Send (CTS)
+* B5	Data Set Ready (DSR)
+* B6	Ring Indicator (RI)
+* B7	Receive Line Signal Detect (RLSD)
+*
+* Byte 1: Line Status
+*
+* Offset	Description
+* B0	Data Ready (DR)
+* B1	Overrun Error (OE)
+* B2	Parity Error (PE)
+* B3	Framing Error (FE)
+* B4	Break Interrupt (BI)
+* B5	Transmitter Holding Register (THRE)
+* B6	Transmitter Empty (TEMT)
+* B7	Error in RCVR FIFO
+*
+*/
+#define FTDI_RS0_CTS	(1 << 4)
+#define FTDI_RS0_DSR	(1 << 5)
+#define FTDI_RS0_RI	(1 << 6)
+#define FTDI_RS0_RLSD	(1 << 7)
+
+#define FTDI_RS_DR	1
+#define FTDI_RS_OE	(1<<1)
+#define FTDI_RS_PE	(1<<2)
+#define FTDI_RS_FE	(1<<3)
+#define FTDI_RS_BI	(1<<4)
+#define FTDI_RS_THRE	(1<<5)
+#define FTDI_RS_TEMT	(1<<6)
+#define FTDI_RS_FIFO	(1<<7)
+
+#endif //TUSB_FTDI_SIO_H
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index aa5891ca9..d9e2d3f2f 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -37,11 +37,17 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_DFU_LOG_LEVEL
+  #define CFG_TUD_DFU_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_DFU_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
   uint8_t attrs;
   uint8_t alt;
 
@@ -51,69 +57,65 @@ typedef struct
   bool flashing_in_progress;
   uint16_t block;
   uint16_t length;
-
-  CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_XFER_BUFSIZE];
 } dfu_state_ctx_t;
 
 // Only a single dfu state is allowed
-CFG_TUSB_MEM_SECTION static dfu_state_ctx_t _dfu_ctx;
+static dfu_state_ctx_t _dfu_ctx;
 
-static void reset_state(void)
-{
+CFG_TUD_MEM_SECTION static struct {
+  TUD_EPBUF_DEF(transfer_buf, CFG_TUD_DFU_XFER_BUFSIZE);
+} _dfu_epbuf;
+
+static void reset_state(void) {
   _dfu_ctx.state = DFU_IDLE;
   _dfu_ctx.status = DFU_STATUS_OK;
   _dfu_ctx.flashing_in_progress = false;
 }
 
-static bool reply_getstatus(uint8_t rhport, tusb_control_request_t const * request, dfu_state_t state, dfu_status_t status, uint32_t timeout);
-static bool process_download_get_status(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
-static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+static bool reply_getstatus(uint8_t rhport, const tusb_control_request_t* request, dfu_state_t state, dfu_status_t status, uint32_t timeout);
+static bool process_download_get_status(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request);
+static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request);
 
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
 
-static tu_lookup_entry_t const _dfu_request_lookup[] =
-{
-  { .key = DFU_REQUEST_DETACH         , .data = "DETACH"    },
-  { .key = DFU_REQUEST_DNLOAD         , .data = "DNLOAD"    },
-  { .key = DFU_REQUEST_UPLOAD         , .data = "UPLOAD"    },
-  { .key = DFU_REQUEST_GETSTATUS      , .data = "GETSTATUS" },
-  { .key = DFU_REQUEST_CLRSTATUS      , .data = "CLRSTATUS" },
-  { .key = DFU_REQUEST_GETSTATE       , .data = "GETSTATE"  },
-  { .key = DFU_REQUEST_ABORT          , .data = "ABORT"     },
+tu_static tu_lookup_entry_t const _dfu_request_lookup[] = {
+  { .key = DFU_REQUEST_DETACH   , .data = "DETACH"    },
+  { .key = DFU_REQUEST_DNLOAD   , .data = "DNLOAD"    },
+  { .key = DFU_REQUEST_UPLOAD   , .data = "UPLOAD"    },
+  { .key = DFU_REQUEST_GETSTATUS, .data = "GETSTATUS" },
+  { .key = DFU_REQUEST_CLRSTATUS, .data = "CLRSTATUS" },
+  { .key = DFU_REQUEST_GETSTATE , .data = "GETSTATE"  },
+  { .key = DFU_REQUEST_ABORT    , .data = "ABORT"     },
 };
 
-static tu_lookup_table_t const _dfu_request_table =
-{
+tu_static tu_lookup_table_t const _dfu_request_table = {
   .count = TU_ARRAY_SIZE(_dfu_request_lookup),
   .items = _dfu_request_lookup
 };
 
-static tu_lookup_entry_t const _dfu_state_lookup[] =
-{
-  { .key = APP_IDLE                   , .data = "APP_IDLE"                },
-  { .key = APP_DETACH                 , .data = "APP_DETACH"              },
-  { .key = DFU_IDLE                   , .data = "IDLE"                },
-  { .key = DFU_DNLOAD_SYNC            , .data = "DNLOAD_SYNC"         },
-  { .key = DFU_DNBUSY                 , .data = "DNBUSY"              },
-  { .key = DFU_DNLOAD_IDLE            , .data = "DNLOAD_IDLE"         },
-  { .key = DFU_MANIFEST_SYNC          , .data = "MANIFEST_SYNC"       },
-  { .key = DFU_MANIFEST               , .data = "MANIFEST"            },
-  { .key = DFU_MANIFEST_WAIT_RESET    , .data = "MANIFEST_WAIT_RESET" },
-  { .key = DFU_UPLOAD_IDLE            , .data = "UPLOAD_IDLE"         },
-  { .key = DFU_ERROR                  , .data = "ERROR"               },
+tu_static tu_lookup_entry_t const _dfu_state_lookup[] = {
+  { .key = APP_IDLE               , .data = "APP_IDLE"            },
+  { .key = APP_DETACH             , .data = "APP_DETACH"          },
+  { .key = DFU_IDLE               , .data = "IDLE"                },
+  { .key = DFU_DNLOAD_SYNC        , .data = "DNLOAD_SYNC"         },
+  { .key = DFU_DNBUSY             , .data = "DNBUSY"              },
+  { .key = DFU_DNLOAD_IDLE        , .data = "DNLOAD_IDLE"         },
+  { .key = DFU_MANIFEST_SYNC      , .data = "MANIFEST_SYNC"       },
+  { .key = DFU_MANIFEST           , .data = "MANIFEST"            },
+  { .key = DFU_MANIFEST_WAIT_RESET, .data = "MANIFEST_WAIT_RESET" },
+  { .key = DFU_UPLOAD_IDLE        , .data = "UPLOAD_IDLE"         },
+  { .key = DFU_ERROR              , .data = "ERROR"               },
 };
 
-static tu_lookup_table_t const _dfu_state_table =
-{
+tu_static tu_lookup_table_t const _dfu_state_table = {
   .count = TU_ARRAY_SIZE(_dfu_state_lookup),
   .items = _dfu_state_lookup
 };
 
-static tu_lookup_entry_t const _dfu_status_lookup[] =
-{
+tu_static tu_lookup_entry_t const _dfu_status_lookup[] = {
   { .key = DFU_STATUS_OK               , .data = "OK"              },
   { .key = DFU_STATUS_ERR_TARGET       , .data = "errTARGET"       },
   { .key = DFU_STATUS_ERR_FILE         , .data = "errFILE"         },
@@ -132,8 +134,7 @@ static tu_lookup_entry_t const _dfu_status_lookup[] =
   { .key = DFU_STATUS_ERR_STALLEDPKT   , .data = "errSTALLEDPKT"   },
 };
 
-static tu_lookup_table_t const _dfu_status_table =
-{
+tu_static tu_lookup_table_t const _dfu_status_table = {
   .count = TU_ARRAY_SIZE(_dfu_status_lookup),
   .items = _dfu_status_lookup
 };
@@ -143,34 +144,32 @@ static tu_lookup_table_t const _dfu_status_table =
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void dfu_moded_reset(uint8_t rhport)
-{
+void dfu_moded_reset(uint8_t rhport) {
   (void) rhport;
-
   _dfu_ctx.attrs = 0;
   _dfu_ctx.alt = 0;
-
   reset_state();
 }
 
-void dfu_moded_init(void)
-{
+void dfu_moded_init(void) {
   dfu_moded_reset(0);
 }
 
-uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
+bool dfu_moded_deinit(void) {
+  return true;
+}
+
+uint16_t dfu_moded_open(uint8_t rhport, const tusb_desc_interface_t* itf_desc, uint16_t max_len) {
   (void) rhport;
 
   //------------- Interface (with Alt) descriptor -------------//
-  uint8_t const itf_num = itf_desc->bInterfaceNumber;
+  const uint8_t itf_num = itf_desc->bInterfaceNumber;
   uint8_t alt_count = 0;
 
   uint16_t drv_len = 0;
   TU_VERIFY(itf_desc->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS && itf_desc->bInterfaceProtocol == DFU_PROTOCOL_DFU, 0);
 
-  while(itf_desc->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS && itf_desc->bInterfaceProtocol == DFU_PROTOCOL_DFU)
-  {
+  while(itf_desc->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS && itf_desc->bInterfaceProtocol == DFU_PROTOCOL_DFU) {
     TU_ASSERT(max_len > drv_len, 0);
 
     // Alternate must have the same interface number
@@ -181,18 +180,18 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
     alt_count++;
 
     drv_len += tu_desc_len(itf_desc);
-    itf_desc = (tusb_desc_interface_t const *) tu_desc_next(itf_desc);
+    itf_desc = (const tusb_desc_interface_t*) tu_desc_next(itf_desc);
   }
 
   //------------- DFU Functional descriptor -------------//
-  tusb_desc_dfu_functional_t const *func_desc = (tusb_desc_dfu_functional_t const *) itf_desc;
+  const tusb_desc_dfu_functional_t*func_desc = (const tusb_desc_dfu_functional_t*) itf_desc;
   TU_ASSERT(tu_desc_type(func_desc) == TUSB_DESC_FUNCTIONAL, 0);
   drv_len += sizeof(tusb_desc_dfu_functional_t);
 
   _dfu_ctx.attrs = func_desc->bAttributes;
 
   // CFG_TUD_DFU_XFER_BUFSIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
-  uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16((uint8_t const*) func_desc + offsetof(tusb_desc_dfu_functional_t, wTransferSize)) );
+  const uint16_t transfer_size = tu_le16toh( tu_unaligned_read16((const uint8_t*) func_desc + offsetof(tusb_desc_dfu_functional_t, wTransferSize)) );
   TU_ASSERT(transfer_size <= CFG_TUD_DFU_XFER_BUFSIZE, drv_len);
 
   return drv_len;
@@ -201,99 +200,85 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
+bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request) {
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
+  TU_LOG_DRV("  DFU State  : %s, Status: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state), tu_lookup_find(&_dfu_status_table, _dfu_ctx.status));
 
-  TU_LOG2("  DFU State  : %s, Status: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state), tu_lookup_find(&_dfu_status_table, _dfu_ctx.status));
-
-  if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
-  {
+  if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) {
     // Standard request include GET/SET_INTERFACE
-    switch ( request->bRequest )
-    {
+    switch (request->bRequest) {
       case TUSB_REQ_SET_INTERFACE:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           // Switch Alt interface and reset state machine
-          _dfu_ctx.alt = (uint8_t) request->wValue;
+          _dfu_ctx.alt = (uint8_t)request->wValue;
           reset_state();
           return tud_control_status(rhport, request);
         }
-      break;
+        break;
 
       case TUSB_REQ_GET_INTERFACE:
-        if(stage == CONTROL_STAGE_SETUP)
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           return tud_control_xfer(rhport, request, &_dfu_ctx.alt, 1);
         }
-      break;
+        break;
 
       // unsupported request
       default: return false;
     }
-  }
-  else if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS )
-  {
-    TU_LOG2("  DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest));
+  } else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS) {
+    TU_LOG_DRV("  DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest));
 
     // Class request
-    switch ( request->bRequest )
-    {
+    switch (request->bRequest) {
       case DFU_REQUEST_DETACH:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           tud_control_status(rhport, request);
+        } else if (stage == CONTROL_STAGE_ACK) {
+          if (tud_dfu_detach_cb) {
+            tud_dfu_detach_cb();
+          }
         }
-        else if ( stage == CONTROL_STAGE_ACK )
-        {
-          if ( tud_dfu_detach_cb ) tud_dfu_detach_cb();
-        }
-      break;
+        break;
 
       case DFU_REQUEST_CLRSTATUS:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           reset_state();
           tud_control_status(rhport, request);
         }
-      break;
+        break;
 
       case DFU_REQUEST_GETSTATE:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           tud_control_xfer(rhport, request, &_dfu_ctx.state, 1);
         }
-      break;
+        break;
 
       case DFU_REQUEST_ABORT:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           reset_state();
           tud_control_status(rhport, request);
+        } else if (stage == CONTROL_STAGE_ACK) {
+          if (tud_dfu_abort_cb) {
+            tud_dfu_abort_cb(_dfu_ctx.alt);
+          }
         }
-        else if ( stage == CONTROL_STAGE_ACK )
-        {
-          if ( tud_dfu_abort_cb ) tud_dfu_abort_cb(_dfu_ctx.alt);
-        }
-      break;
+        break;
 
       case DFU_REQUEST_UPLOAD:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           TU_VERIFY(_dfu_ctx.attrs & DFU_ATTR_CAN_UPLOAD);
           TU_VERIFY(tud_dfu_upload_cb);
           TU_VERIFY(request->wLength <= CFG_TUD_DFU_XFER_BUFSIZE);
 
-          uint16_t const xfer_len = tud_dfu_upload_cb(_dfu_ctx.alt, request->wValue, _dfu_ctx.transfer_buf, request->wLength);
+          const uint16_t xfer_len = tud_dfu_upload_cb(_dfu_ctx.alt, request->wValue, _dfu_epbuf.transfer_buf,
+                                                      request->wLength);
 
-          return tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, xfer_len);
+          return tud_control_xfer(rhport, request, _dfu_epbuf.transfer_buf, xfer_len);
         }
-      break;
+        break;
 
       case DFU_REQUEST_DNLOAD:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           TU_VERIFY(_dfu_ctx.attrs & DFU_ATTR_CAN_DOWNLOAD);
           TU_VERIFY(_dfu_ctx.state == DFU_IDLE || _dfu_ctx.state == DFU_DNLOAD_IDLE);
           TU_VERIFY(request->wLength <= CFG_TUD_DFU_XFER_BUFSIZE);
@@ -302,104 +287,86 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
           _dfu_ctx.flashing_in_progress = true;
 
           // save block and length for flashing
-          _dfu_ctx.block  = request->wValue;
+          _dfu_ctx.block = request->wValue;
           _dfu_ctx.length = request->wLength;
 
-          if ( request->wLength )
-          {
+          if (request->wLength) {
             // Download with payload -> transition to DOWNLOAD SYNC
             _dfu_ctx.state = DFU_DNLOAD_SYNC;
-            return tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, request->wLength);
-          }
-          else
-          {
+            return tud_control_xfer(rhport, request, _dfu_epbuf.transfer_buf, request->wLength);
+          } else {
             // Download is complete -> transition to MANIFEST SYNC
             _dfu_ctx.state = DFU_MANIFEST_SYNC;
             return tud_control_status(rhport, request);
           }
         }
-      break;
+        break;
 
       case DFU_REQUEST_GETSTATUS:
-        switch ( _dfu_ctx.state )
-        {
+        switch (_dfu_ctx.state) {
           case DFU_DNLOAD_SYNC:
             return process_download_get_status(rhport, stage, request);
-          break;
+            break;
 
           case DFU_MANIFEST_SYNC:
             return process_manifest_get_status(rhport, stage, request);
-          break;
+            break;
 
           default:
-            if ( stage == CONTROL_STAGE_SETUP ) return reply_getstatus(rhport, request, _dfu_ctx.state, _dfu_ctx.status, 0);
-          break;
+            if (stage == CONTROL_STAGE_SETUP) {
+              return reply_getstatus(rhport, request, _dfu_ctx.state, _dfu_ctx.status, 0);
+            }
+            break;
         }
-      break;
+        break;
 
       default: return false; // stall unsupported request
     }
-  }else
-  {
+  } else {
     return false; // unsupported request
   }
 
   return true;
 }
 
-void tud_dfu_finish_flashing(uint8_t status)
-{
+void tud_dfu_finish_flashing(uint8_t status) {
   _dfu_ctx.flashing_in_progress = false;
 
-  if ( status == DFU_STATUS_OK )
-  {
-    if (_dfu_ctx.state == DFU_DNBUSY)
-    {
+  if (status == DFU_STATUS_OK) {
+    if (_dfu_ctx.state == DFU_DNBUSY) {
       _dfu_ctx.state = DFU_DNLOAD_SYNC;
-    }
-    else if (_dfu_ctx.state == DFU_MANIFEST)
-    {
+    } else if (_dfu_ctx.state == DFU_MANIFEST) {
       _dfu_ctx.state = (_dfu_ctx.attrs & DFU_ATTR_MANIFESTATION_TOLERANT)
-                               ? DFU_MANIFEST_SYNC : DFU_MANIFEST_WAIT_RESET;
+                         ? DFU_MANIFEST_SYNC
+                         : DFU_MANIFEST_WAIT_RESET;
     }
-  }
-  else
-  {
+  } else {
     // failed while flashing, move to dfuError
     _dfu_ctx.state = DFU_ERROR;
     _dfu_ctx.status = (dfu_status_t)status;
   }
 }
 
-static bool process_download_get_status(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
-  if ( stage == CONTROL_STAGE_SETUP )
-  {
+static bool process_download_get_status(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request) {
+  if (stage == CONTROL_STAGE_SETUP) {
     // only transition to next state on CONTROL_STAGE_ACK
     dfu_state_t next_state;
     uint32_t timeout;
 
-    if ( _dfu_ctx.flashing_in_progress )
-    {
+    if (_dfu_ctx.flashing_in_progress) {
       next_state = DFU_DNBUSY;
-      timeout = tud_dfu_get_timeout_cb(_dfu_ctx.alt, (uint8_t) next_state);
-    }
-    else
-    {
+      timeout = tud_dfu_get_timeout_cb(_dfu_ctx.alt, (uint8_t)next_state);
+    } else {
       next_state = DFU_DNLOAD_IDLE;
       timeout = 0;
     }
 
     return reply_getstatus(rhport, request, next_state, _dfu_ctx.status, timeout);
-  }
-  else if ( stage == CONTROL_STAGE_ACK )
-  {
-    if ( _dfu_ctx.flashing_in_progress )
-    {
+  } else if (stage == CONTROL_STAGE_ACK) {
+    if (_dfu_ctx.flashing_in_progress) {
       _dfu_ctx.state = DFU_DNBUSY;
-      tud_dfu_download_cb(_dfu_ctx.alt, _dfu_ctx.block, _dfu_ctx.transfer_buf, _dfu_ctx.length);
-    }else
-    {
+      tud_dfu_download_cb(_dfu_ctx.alt, _dfu_ctx.block, _dfu_epbuf.transfer_buf, _dfu_ctx.length);
+    } else {
       _dfu_ctx.state = DFU_DNLOAD_IDLE;
     }
   }
@@ -407,36 +374,26 @@ static bool process_download_get_status(uint8_t rhport, uint8_t stage, tusb_cont
   return true;
 }
 
-static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
-  if ( stage == CONTROL_STAGE_SETUP )
-  {
+static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request) {
+  if (stage == CONTROL_STAGE_SETUP) {
     // only transition to next state on CONTROL_STAGE_ACK
     dfu_state_t next_state;
     uint32_t timeout;
 
-    if ( _dfu_ctx.flashing_in_progress )
-    {
+    if (_dfu_ctx.flashing_in_progress) {
       next_state = DFU_MANIFEST;
       timeout = tud_dfu_get_timeout_cb(_dfu_ctx.alt, next_state);
-    }
-    else
-    {
+    } else {
       next_state = DFU_IDLE;
       timeout = 0;
     }
 
     return reply_getstatus(rhport, request, next_state, _dfu_ctx.status, timeout);
-  }
-  else if ( stage == CONTROL_STAGE_ACK )
-  {
-    if ( _dfu_ctx.flashing_in_progress )
-    {
+  } else if (stage == CONTROL_STAGE_ACK) {
+    if (_dfu_ctx.flashing_in_progress) {
       _dfu_ctx.state = DFU_MANIFEST;
       tud_dfu_manifest_cb(_dfu_ctx.alt);
-    }
-    else
-    {
+    } else {
       _dfu_ctx.state = DFU_IDLE;
     }
   }
@@ -444,15 +401,15 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_cont
   return true;
 }
 
-static bool reply_getstatus(uint8_t rhport, tusb_control_request_t const * request, dfu_state_t state, dfu_status_t status, uint32_t timeout)
-{
+static bool reply_getstatus(uint8_t rhport, const tusb_control_request_t* request, dfu_state_t state,
+                            dfu_status_t status, uint32_t timeout) {
   dfu_status_response_t resp;
-  resp.bStatus          = (uint8_t) status;
+  resp.bStatus = (uint8_t)status;
   resp.bwPollTimeout[0] = TU_U32_BYTE0(timeout);
   resp.bwPollTimeout[1] = TU_U32_BYTE1(timeout);
   resp.bwPollTimeout[2] = TU_U32_BYTE2(timeout);
-  resp.bState           = (uint8_t) state;
-  resp.iString          = 0;
+  resp.bState = (uint8_t)state;
+  resp.iString = 0;
 
   return tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_response_t));
 }
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index fecf8596f..00c22ea8b 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -86,6 +86,7 @@ TU_ATTR_WEAK void tud_dfu_abort_cb(uint8_t alt);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     dfu_moded_init(void);
+bool     dfu_moded_deinit(void);
 void     dfu_moded_reset(uint8_t rhport);
 uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c
index b9cd6096b..a63c23d9a 100644
--- a/src/class/dfu/dfu_rt_device.c
+++ b/src/class/dfu/dfu_rt_device.c
@@ -37,6 +37,13 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_DFU_RUNTIME_LOG_LEVEL
+  #define CFG_TUD_DFU_RUNTIME_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_DFU_RUNTIME_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
@@ -44,13 +51,15 @@
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void dfu_rtd_init(void)
-{
+void dfu_rtd_init(void) {
 }
 
-void dfu_rtd_reset(uint8_t rhport)
-{
-    (void) rhport;
+bool dfu_rtd_deinit(void) {
+  return true;
+}
+
+void dfu_rtd_reset(uint8_t rhport) {
+  (void) rhport;
 }
 
 uint16_t dfu_rtd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
@@ -99,7 +108,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
   {
     case DFU_REQUEST_DETACH:
     {
-      TU_LOG2("  DFU RT Request: DETACH\r\n");
+      TU_LOG_DRV("  DFU RT Request: DETACH\r\n");
       tud_control_status(rhport, request);
       tud_dfu_runtime_reboot_to_dfu_cb();
     }
@@ -107,17 +116,17 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
 
     case DFU_REQUEST_GETSTATUS:
     {
-      TU_LOG2("  DFU RT Request: GETSTATUS\r\n");
+      TU_LOG_DRV("  DFU RT Request: GETSTATUS\r\n");
       dfu_status_response_t resp;
       // Status = OK, Poll timeout is ignored during RT, State = APP_IDLE, IString = 0
-      memset(&resp, 0x00, sizeof(dfu_status_response_t));
+      TU_VERIFY(tu_memset_s(&resp, sizeof(resp), 0x00, sizeof(resp))==0);
       tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_response_t));
     }
     break;
 
     default:
     {
-      TU_LOG2("  DFU RT Unexpected Request: %d\r\n", request->bRequest);
+      TU_LOG_DRV("  DFU RT Unexpected Request: %d\r\n", request->bRequest);
       return false; // stall unsupported request
     }
   }
diff --git a/src/class/dfu/dfu_rt_device.h b/src/class/dfu/dfu_rt_device.h
index babaa8214..67eb26d95 100644
--- a/src/class/dfu/dfu_rt_device.h
+++ b/src/class/dfu/dfu_rt_device.h
@@ -43,6 +43,7 @@ void tud_dfu_runtime_reboot_to_dfu_cb(void);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     dfu_rtd_init(void);
+bool     dfu_rtd_deinit(void);
 void     dfu_rtd_reset(uint8_t rhport);
 uint16_t dfu_rtd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 44a464be1..c2434c20d 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -300,6 +300,19 @@ typedef struct TU_ATTR_PACKED
   int8_t  pan;     // using AC Pan
 } hid_mouse_report_t;
 
+
+// Absolute Mouse: same as the Standard (relative) Mouse Report but
+// with int16_t instead of int8_t for X and Y coordinates.
+typedef struct TU_ATTR_PACKED
+{
+    uint8_t buttons; /**< buttons mask for currently pressed buttons in the mouse. */
+    int16_t x;       /**< Current x position of the mouse. */
+    int16_t y;       /**< Current y position of the mouse. */
+    int8_t wheel;    /**< Current delta wheel movement on the mouse. */
+    int8_t pan;      // using AC Pan
+} hid_abs_mouse_report_t;
+
+
 /// Standard Mouse Buttons Bitmap
 typedef enum
 {
@@ -312,6 +325,29 @@ typedef enum
 
 /// @}
 
+//--------------------------------------------------------------------+
+// Digitizer Stylus Pen
+//--------------------------------------------------------------------+
+/** \addtogroup ClassDriver_HID_Stylus Stylus
+ *  @{ */
+
+// Standard Stylus Pen Report.
+typedef struct TU_ATTR_PACKED
+{
+  uint8_t attr;    /**< Attribute mask for describing current status of the stylus pen. */
+  uint16_t x;      /**< Current x position of the mouse. */
+  uint16_t y;      /**< Current y position of the mouse. */
+} hid_stylus_report_t;
+
+// Standard Stylus Pen Attributes Bitmap.
+typedef enum
+{
+  STYLUS_ATTR_TIP_SWITCH = TU_BIT(0), ///< Tip switch
+  STYLUS_ATTR_IN_RANGE   = TU_BIT(1), ///< In-range bit.
+} hid_stylus_attr_bm_t;
+
+/// @}
+
 //--------------------------------------------------------------------+
 // Keyboard
 //--------------------------------------------------------------------+
@@ -353,177 +389,224 @@ typedef enum
 //--------------------------------------------------------------------+
 // HID KEYCODE
 //--------------------------------------------------------------------+
-#define HID_KEY_NONE                      0x00
-#define HID_KEY_A                         0x04
-#define HID_KEY_B                         0x05
-#define HID_KEY_C                         0x06
-#define HID_KEY_D                         0x07
-#define HID_KEY_E                         0x08
-#define HID_KEY_F                         0x09
-#define HID_KEY_G                         0x0A
-#define HID_KEY_H                         0x0B
-#define HID_KEY_I                         0x0C
-#define HID_KEY_J                         0x0D
-#define HID_KEY_K                         0x0E
-#define HID_KEY_L                         0x0F
-#define HID_KEY_M                         0x10
-#define HID_KEY_N                         0x11
-#define HID_KEY_O                         0x12
-#define HID_KEY_P                         0x13
-#define HID_KEY_Q                         0x14
-#define HID_KEY_R                         0x15
-#define HID_KEY_S                         0x16
-#define HID_KEY_T                         0x17
-#define HID_KEY_U                         0x18
-#define HID_KEY_V                         0x19
-#define HID_KEY_W                         0x1A
-#define HID_KEY_X                         0x1B
-#define HID_KEY_Y                         0x1C
-#define HID_KEY_Z                         0x1D
-#define HID_KEY_1                         0x1E
-#define HID_KEY_2                         0x1F
-#define HID_KEY_3                         0x20
-#define HID_KEY_4                         0x21
-#define HID_KEY_5                         0x22
-#define HID_KEY_6                         0x23
-#define HID_KEY_7                         0x24
-#define HID_KEY_8                         0x25
-#define HID_KEY_9                         0x26
-#define HID_KEY_0                         0x27
-#define HID_KEY_ENTER                     0x28
-#define HID_KEY_ESCAPE                    0x29
-#define HID_KEY_BACKSPACE                 0x2A
-#define HID_KEY_TAB                       0x2B
-#define HID_KEY_SPACE                     0x2C
-#define HID_KEY_MINUS                     0x2D
-#define HID_KEY_EQUAL                     0x2E
-#define HID_KEY_BRACKET_LEFT              0x2F
-#define HID_KEY_BRACKET_RIGHT             0x30
-#define HID_KEY_BACKSLASH                 0x31
-#define HID_KEY_EUROPE_1                  0x32
-#define HID_KEY_SEMICOLON                 0x33
-#define HID_KEY_APOSTROPHE                0x34
-#define HID_KEY_GRAVE                     0x35
-#define HID_KEY_COMMA                     0x36
-#define HID_KEY_PERIOD                    0x37
-#define HID_KEY_SLASH                     0x38
-#define HID_KEY_CAPS_LOCK                 0x39
-#define HID_KEY_F1                        0x3A
-#define HID_KEY_F2                        0x3B
-#define HID_KEY_F3                        0x3C
-#define HID_KEY_F4                        0x3D
-#define HID_KEY_F5                        0x3E
-#define HID_KEY_F6                        0x3F
-#define HID_KEY_F7                        0x40
-#define HID_KEY_F8                        0x41
-#define HID_KEY_F9                        0x42
-#define HID_KEY_F10                       0x43
-#define HID_KEY_F11                       0x44
-#define HID_KEY_F12                       0x45
-#define HID_KEY_PRINT_SCREEN              0x46
-#define HID_KEY_SCROLL_LOCK               0x47
-#define HID_KEY_PAUSE                     0x48
-#define HID_KEY_INSERT                    0x49
-#define HID_KEY_HOME                      0x4A
-#define HID_KEY_PAGE_UP                   0x4B
-#define HID_KEY_DELETE                    0x4C
-#define HID_KEY_END                       0x4D
-#define HID_KEY_PAGE_DOWN                 0x4E
-#define HID_KEY_ARROW_RIGHT               0x4F
-#define HID_KEY_ARROW_LEFT                0x50
-#define HID_KEY_ARROW_DOWN                0x51
-#define HID_KEY_ARROW_UP                  0x52
-#define HID_KEY_NUM_LOCK                  0x53
-#define HID_KEY_KEYPAD_DIVIDE             0x54
-#define HID_KEY_KEYPAD_MULTIPLY           0x55
-#define HID_KEY_KEYPAD_SUBTRACT           0x56
-#define HID_KEY_KEYPAD_ADD                0x57
-#define HID_KEY_KEYPAD_ENTER              0x58
-#define HID_KEY_KEYPAD_1                  0x59
-#define HID_KEY_KEYPAD_2                  0x5A
-#define HID_KEY_KEYPAD_3                  0x5B
-#define HID_KEY_KEYPAD_4                  0x5C
-#define HID_KEY_KEYPAD_5                  0x5D
-#define HID_KEY_KEYPAD_6                  0x5E
-#define HID_KEY_KEYPAD_7                  0x5F
-#define HID_KEY_KEYPAD_8                  0x60
-#define HID_KEY_KEYPAD_9                  0x61
-#define HID_KEY_KEYPAD_0                  0x62
-#define HID_KEY_KEYPAD_DECIMAL            0x63
-#define HID_KEY_EUROPE_2                  0x64
-#define HID_KEY_APPLICATION               0x65
-#define HID_KEY_POWER                     0x66
-#define HID_KEY_KEYPAD_EQUAL              0x67
-#define HID_KEY_F13                       0x68
-#define HID_KEY_F14                       0x69
-#define HID_KEY_F15                       0x6A
-#define HID_KEY_F16                       0x6B
-#define HID_KEY_F17                       0x6C
-#define HID_KEY_F18                       0x6D
-#define HID_KEY_F19                       0x6E
-#define HID_KEY_F20                       0x6F
-#define HID_KEY_F21                       0x70
-#define HID_KEY_F22                       0x71
-#define HID_KEY_F23                       0x72
-#define HID_KEY_F24                       0x73
-#define HID_KEY_EXECUTE                   0x74
-#define HID_KEY_HELP                      0x75
-#define HID_KEY_MENU                      0x76
-#define HID_KEY_SELECT                    0x77
-#define HID_KEY_STOP                      0x78
-#define HID_KEY_AGAIN                     0x79
-#define HID_KEY_UNDO                      0x7A
-#define HID_KEY_CUT                       0x7B
-#define HID_KEY_COPY                      0x7C
-#define HID_KEY_PASTE                     0x7D
-#define HID_KEY_FIND                      0x7E
-#define HID_KEY_MUTE                      0x7F
-#define HID_KEY_VOLUME_UP                 0x80
-#define HID_KEY_VOLUME_DOWN               0x81
-#define HID_KEY_LOCKING_CAPS_LOCK         0x82
-#define HID_KEY_LOCKING_NUM_LOCK          0x83
-#define HID_KEY_LOCKING_SCROLL_LOCK       0x84
-#define HID_KEY_KEYPAD_COMMA              0x85
-#define HID_KEY_KEYPAD_EQUAL_SIGN         0x86
-#define HID_KEY_KANJI1                    0x87
-#define HID_KEY_KANJI2                    0x88
-#define HID_KEY_KANJI3                    0x89
-#define HID_KEY_KANJI4                    0x8A
-#define HID_KEY_KANJI5                    0x8B
-#define HID_KEY_KANJI6                    0x8C
-#define HID_KEY_KANJI7                    0x8D
-#define HID_KEY_KANJI8                    0x8E
-#define HID_KEY_KANJI9                    0x8F
-#define HID_KEY_LANG1                     0x90
-#define HID_KEY_LANG2                     0x91
-#define HID_KEY_LANG3                     0x92
-#define HID_KEY_LANG4                     0x93
-#define HID_KEY_LANG5                     0x94
-#define HID_KEY_LANG6                     0x95
-#define HID_KEY_LANG7                     0x96
-#define HID_KEY_LANG8                     0x97
-#define HID_KEY_LANG9                     0x98
-#define HID_KEY_ALTERNATE_ERASE           0x99
-#define HID_KEY_SYSREQ_ATTENTION          0x9A
-#define HID_KEY_CANCEL                    0x9B
-#define HID_KEY_CLEAR                     0x9C
-#define HID_KEY_PRIOR                     0x9D
-#define HID_KEY_RETURN                    0x9E
-#define HID_KEY_SEPARATOR                 0x9F
-#define HID_KEY_OUT                       0xA0
-#define HID_KEY_OPER                      0xA1
-#define HID_KEY_CLEAR_AGAIN               0xA2
-#define HID_KEY_CRSEL_PROPS               0xA3
-#define HID_KEY_EXSEL                     0xA4
-// RESERVED					                      0xA5-DF
-#define HID_KEY_CONTROL_LEFT              0xE0
-#define HID_KEY_SHIFT_LEFT                0xE1
-#define HID_KEY_ALT_LEFT                  0xE2
-#define HID_KEY_GUI_LEFT                  0xE3
-#define HID_KEY_CONTROL_RIGHT             0xE4
-#define HID_KEY_SHIFT_RIGHT               0xE5
-#define HID_KEY_ALT_RIGHT                 0xE6
-#define HID_KEY_GUI_RIGHT                 0xE7
+#define HID_KEY_NONE                        0x00
+#define HID_KEY_A                           0x04
+#define HID_KEY_B                           0x05
+#define HID_KEY_C                           0x06
+#define HID_KEY_D                           0x07
+#define HID_KEY_E                           0x08
+#define HID_KEY_F                           0x09
+#define HID_KEY_G                           0x0A
+#define HID_KEY_H                           0x0B
+#define HID_KEY_I                           0x0C
+#define HID_KEY_J                           0x0D
+#define HID_KEY_K                           0x0E
+#define HID_KEY_L                           0x0F
+#define HID_KEY_M                           0x10
+#define HID_KEY_N                           0x11
+#define HID_KEY_O                           0x12
+#define HID_KEY_P                           0x13
+#define HID_KEY_Q                           0x14
+#define HID_KEY_R                           0x15
+#define HID_KEY_S                           0x16
+#define HID_KEY_T                           0x17
+#define HID_KEY_U                           0x18
+#define HID_KEY_V                           0x19
+#define HID_KEY_W                           0x1A
+#define HID_KEY_X                           0x1B
+#define HID_KEY_Y                           0x1C
+#define HID_KEY_Z                           0x1D
+#define HID_KEY_1                           0x1E
+#define HID_KEY_2                           0x1F
+#define HID_KEY_3                           0x20
+#define HID_KEY_4                           0x21
+#define HID_KEY_5                           0x22
+#define HID_KEY_6                           0x23
+#define HID_KEY_7                           0x24
+#define HID_KEY_8                           0x25
+#define HID_KEY_9                           0x26
+#define HID_KEY_0                           0x27
+#define HID_KEY_ENTER                       0x28
+#define HID_KEY_ESCAPE                      0x29
+#define HID_KEY_BACKSPACE                   0x2A
+#define HID_KEY_TAB                         0x2B
+#define HID_KEY_SPACE                       0x2C
+#define HID_KEY_MINUS                       0x2D
+#define HID_KEY_EQUAL                       0x2E
+#define HID_KEY_BRACKET_LEFT                0x2F
+#define HID_KEY_BRACKET_RIGHT               0x30
+#define HID_KEY_BACKSLASH                   0x31
+#define HID_KEY_EUROPE_1                    0x32
+#define HID_KEY_SEMICOLON                   0x33
+#define HID_KEY_APOSTROPHE                  0x34
+#define HID_KEY_GRAVE                       0x35
+#define HID_KEY_COMMA                       0x36
+#define HID_KEY_PERIOD                      0x37
+#define HID_KEY_SLASH                       0x38
+#define HID_KEY_CAPS_LOCK                   0x39
+#define HID_KEY_F1                          0x3A
+#define HID_KEY_F2                          0x3B
+#define HID_KEY_F3                          0x3C
+#define HID_KEY_F4                          0x3D
+#define HID_KEY_F5                          0x3E
+#define HID_KEY_F6                          0x3F
+#define HID_KEY_F7                          0x40
+#define HID_KEY_F8                          0x41
+#define HID_KEY_F9                          0x42
+#define HID_KEY_F10                         0x43
+#define HID_KEY_F11                         0x44
+#define HID_KEY_F12                         0x45
+#define HID_KEY_PRINT_SCREEN                0x46
+#define HID_KEY_SCROLL_LOCK                 0x47
+#define HID_KEY_PAUSE                       0x48
+#define HID_KEY_INSERT                      0x49
+#define HID_KEY_HOME                        0x4A
+#define HID_KEY_PAGE_UP                     0x4B
+#define HID_KEY_DELETE                      0x4C
+#define HID_KEY_END                         0x4D
+#define HID_KEY_PAGE_DOWN                   0x4E
+#define HID_KEY_ARROW_RIGHT                 0x4F
+#define HID_KEY_ARROW_LEFT                  0x50
+#define HID_KEY_ARROW_DOWN                  0x51
+#define HID_KEY_ARROW_UP                    0x52
+#define HID_KEY_NUM_LOCK                    0x53
+#define HID_KEY_KEYPAD_DIVIDE               0x54
+#define HID_KEY_KEYPAD_MULTIPLY             0x55
+#define HID_KEY_KEYPAD_SUBTRACT             0x56
+#define HID_KEY_KEYPAD_ADD                  0x57
+#define HID_KEY_KEYPAD_ENTER                0x58
+#define HID_KEY_KEYPAD_1                    0x59
+#define HID_KEY_KEYPAD_2                    0x5A
+#define HID_KEY_KEYPAD_3                    0x5B
+#define HID_KEY_KEYPAD_4                    0x5C
+#define HID_KEY_KEYPAD_5                    0x5D
+#define HID_KEY_KEYPAD_6                    0x5E
+#define HID_KEY_KEYPAD_7                    0x5F
+#define HID_KEY_KEYPAD_8                    0x60
+#define HID_KEY_KEYPAD_9                    0x61
+#define HID_KEY_KEYPAD_0                    0x62
+#define HID_KEY_KEYPAD_DECIMAL              0x63
+#define HID_KEY_EUROPE_2                    0x64
+#define HID_KEY_APPLICATION                 0x65
+#define HID_KEY_POWER                       0x66
+#define HID_KEY_KEYPAD_EQUAL                0x67
+#define HID_KEY_F13                         0x68
+#define HID_KEY_F14                         0x69
+#define HID_KEY_F15                         0x6A
+#define HID_KEY_F16                         0x6B
+#define HID_KEY_F17                         0x6C
+#define HID_KEY_F18                         0x6D
+#define HID_KEY_F19                         0x6E
+#define HID_KEY_F20                         0x6F
+#define HID_KEY_F21                         0x70
+#define HID_KEY_F22                         0x71
+#define HID_KEY_F23                         0x72
+#define HID_KEY_F24                         0x73
+#define HID_KEY_EXECUTE                     0x74
+#define HID_KEY_HELP                        0x75
+#define HID_KEY_MENU                        0x76
+#define HID_KEY_SELECT                      0x77
+#define HID_KEY_STOP                        0x78
+#define HID_KEY_AGAIN                       0x79
+#define HID_KEY_UNDO                        0x7A
+#define HID_KEY_CUT                         0x7B
+#define HID_KEY_COPY                        0x7C
+#define HID_KEY_PASTE                       0x7D
+#define HID_KEY_FIND                        0x7E
+#define HID_KEY_MUTE                        0x7F
+#define HID_KEY_VOLUME_UP                   0x80
+#define HID_KEY_VOLUME_DOWN                 0x81
+#define HID_KEY_LOCKING_CAPS_LOCK           0x82
+#define HID_KEY_LOCKING_NUM_LOCK            0x83
+#define HID_KEY_LOCKING_SCROLL_LOCK         0x84
+#define HID_KEY_KEYPAD_COMMA                0x85
+#define HID_KEY_KEYPAD_EQUAL_SIGN           0x86
+#define HID_KEY_KANJI1                      0x87
+#define HID_KEY_KANJI2                      0x88
+#define HID_KEY_KANJI3                      0x89
+#define HID_KEY_KANJI4                      0x8A
+#define HID_KEY_KANJI5                      0x8B
+#define HID_KEY_KANJI6                      0x8C
+#define HID_KEY_KANJI7                      0x8D
+#define HID_KEY_KANJI8                      0x8E
+#define HID_KEY_KANJI9                      0x8F
+#define HID_KEY_LANG1                       0x90
+#define HID_KEY_LANG2                       0x91
+#define HID_KEY_LANG3                       0x92
+#define HID_KEY_LANG4                       0x93
+#define HID_KEY_LANG5                       0x94
+#define HID_KEY_LANG6                       0x95
+#define HID_KEY_LANG7                       0x96
+#define HID_KEY_LANG8                       0x97
+#define HID_KEY_LANG9                       0x98
+#define HID_KEY_ALTERNATE_ERASE             0x99
+#define HID_KEY_SYSREQ_ATTENTION            0x9A
+#define HID_KEY_CANCEL                      0x9B
+#define HID_KEY_CLEAR                       0x9C
+#define HID_KEY_PRIOR                       0x9D
+#define HID_KEY_RETURN                      0x9E
+#define HID_KEY_SEPARATOR                   0x9F
+#define HID_KEY_OUT                         0xA0
+#define HID_KEY_OPER                        0xA1
+#define HID_KEY_CLEAR_AGAIN                 0xA2
+#define HID_KEY_CRSEL_PROPS                 0xA3
+#define HID_KEY_EXSEL                       0xA4
+// RESERVED					                        0xA5-AF
+#define HID_KEY_KEYPAD_00                   0xB0
+#define HID_KEY_KEYPAD_000                  0xB1
+#define HID_KEY_THOUSANDS_SEPARATOR         0xB2
+#define HID_KEY_DECIMAL_SEPARATOR           0xB3
+#define HID_KEY_CURRENCY_UNIT               0xB4
+#define HID_KEY_CURRENCY_SUBUNIT            0xB5
+#define HID_KEY_KEYPAD_LEFT_PARENTHESIS     0xB6
+#define HID_KEY_KEYPAD_RIGHT_PARENTHESIS    0xB7
+#define HID_KEY_KEYPAD_LEFT_BRACE           0xB8
+#define HID_KEY_KEYPAD_RIGHT_BRACE          0xB9
+#define HID_KEY_KEYPAD_TAB                  0xBA
+#define HID_KEY_KEYPAD_BACKSPACE            0xBB
+#define HID_KEY_KEYPAD_A                    0xBC
+#define HID_KEY_KEYPAD_B                    0xBD
+#define HID_KEY_KEYPAD_C                    0xBE
+#define HID_KEY_KEYPAD_D                    0xBF
+#define HID_KEY_KEYPAD_E                    0xC0
+#define HID_KEY_KEYPAD_F                    0xC1
+#define HID_KEY_KEYPAD_XOR                  0xC2
+#define HID_KEY_KEYPAD_CARET                0xC3
+#define HID_KEY_KEYPAD_PERCENT              0xC4
+#define HID_KEY_KEYPAD_LESS_THAN            0xC5
+#define HID_KEY_KEYPAD_GREATER_THAN         0xC6
+#define HID_KEY_KEYPAD_AMPERSAND            0xC7
+#define HID_KEY_KEYPAD_DOUBLE_AMPERSAND     0xC8
+#define HID_KEY_KEYPAD_VERTICAL_BAR         0xC9
+#define HID_KEY_KEYPAD_DOUBLE_VERTICAL_BAR  0xCA
+#define HID_KEY_KEYPAD_COLON                0xCB
+#define HID_KEY_KEYPAD_HASH                 0xCC
+#define HID_KEY_KEYPAD_SPACE                0xCD
+#define HID_KEY_KEYPAD_AT                   0xCE
+#define HID_KEY_KEYPAD_EXCLAMATION          0xCF
+#define HID_KEY_KEYPAD_MEMORY_STORE         0xD0
+#define HID_KEY_KEYPAD_MEMORY_RECALL        0xD1
+#define HID_KEY_KEYPAD_MEMORY_CLEAR         0xD2
+#define HID_KEY_KEYPAD_MEMORY_ADD           0xD3
+#define HID_KEY_KEYPAD_MEMORY_SUBTRACT      0xD4
+#define HID_KEY_KEYPAD_MEMORY_MULTIPLY      0xD5
+#define HID_KEY_KEYPAD_MEMORY_DIVIDE        0xD6
+#define HID_KEY_KEYPAD_PLUS_MINUS           0xD7
+#define HID_KEY_KEYPAD_CLEAR                0xD8
+#define HID_KEY_KEYPAD_CLEAR_ENTRY          0xD9
+#define HID_KEY_KEYPAD_BINARY               0xDA
+#define HID_KEY_KEYPAD_OCTAL                0xDB
+#define HID_KEY_KEYPAD_DECIMAL_2            0xDC
+#define HID_KEY_KEYPAD_HEXADECIMAL          0xDD
+// RESERVED					                        0xDE-DF
+#define HID_KEY_CONTROL_LEFT                0xE0
+#define HID_KEY_SHIFT_LEFT                  0xE1
+#define HID_KEY_ALT_LEFT                    0xE2
+#define HID_KEY_GUI_LEFT                    0xE3
+#define HID_KEY_CONTROL_RIGHT               0xE4
+#define HID_KEY_SHIFT_RIGHT                 0xE5
+#define HID_KEY_ALT_RIGHT                   0xE6
+#define HID_KEY_GUI_RIGHT                   0xE7
 
 
 //--------------------------------------------------------------------+
@@ -680,35 +763,58 @@ enum {
 
 //--------------------------------------------------------------------+
 // Usage Table
+/* Usage Types Data
+    Sel  Selector               Array
+    SV   Static Value           Constant, Variable, Absolute
+    SF   Static Flag            Constant, Variable, Absolute
+    DV   Dynamic Value          Constant, Variable, Absolute
+    DF   Dynamic Flag           Constant, Variable, Absolute
+*/
+/* Usage Types Collection
+    NAry  Named Array             Logical
+    CA    Collection Application  Application
+    CL    Collection Logical      Logical
+    CP    Collection Physical     Physical
+    US    Usage Switch            Logical
+    UM    Usage Modifier          Logical
+*/
 //--------------------------------------------------------------------+
 
 /// HID Usage Table - Table 1: Usage Page Summary
 enum {
-  HID_USAGE_PAGE_DESKTOP         = 0x01,
-  HID_USAGE_PAGE_SIMULATE        = 0x02,
-  HID_USAGE_PAGE_VIRTUAL_REALITY = 0x03,
-  HID_USAGE_PAGE_SPORT           = 0x04,
-  HID_USAGE_PAGE_GAME            = 0x05,
-  HID_USAGE_PAGE_GENERIC_DEVICE  = 0x06,
-  HID_USAGE_PAGE_KEYBOARD        = 0x07,
-  HID_USAGE_PAGE_LED             = 0x08,
-  HID_USAGE_PAGE_BUTTON          = 0x09,
-  HID_USAGE_PAGE_ORDINAL         = 0x0a,
-  HID_USAGE_PAGE_TELEPHONY       = 0x0b,
-  HID_USAGE_PAGE_CONSUMER        = 0x0c,
-  HID_USAGE_PAGE_DIGITIZER       = 0x0d,
-  HID_USAGE_PAGE_PID             = 0x0f,
-  HID_USAGE_PAGE_UNICODE         = 0x10,
-  HID_USAGE_PAGE_ALPHA_DISPLAY   = 0x14,
-  HID_USAGE_PAGE_MEDICAL         = 0x40,
-  HID_USAGE_PAGE_MONITOR         = 0x80, //0x80 - 0x83
-  HID_USAGE_PAGE_POWER           = 0x84, // 0x084 - 0x87
-  HID_USAGE_PAGE_BARCODE_SCANNER = 0x8c,
-  HID_USAGE_PAGE_SCALE           = 0x8d,
-  HID_USAGE_PAGE_MSR             = 0x8e,
-  HID_USAGE_PAGE_CAMERA          = 0x90,
-  HID_USAGE_PAGE_ARCADE          = 0x91,
-  HID_USAGE_PAGE_VENDOR          = 0xFF00 // 0xFF00 - 0xFFFF
+  HID_USAGE_PAGE_DESKTOP                   = 0x01,
+  HID_USAGE_PAGE_SIMULATE                  = 0x02,
+  HID_USAGE_PAGE_VIRTUAL_REALITY           = 0x03,
+  HID_USAGE_PAGE_SPORT                     = 0x04,
+  HID_USAGE_PAGE_GAME                      = 0x05,
+  HID_USAGE_PAGE_GENERIC_DEVICE            = 0x06,
+  HID_USAGE_PAGE_KEYBOARD                  = 0x07,
+  HID_USAGE_PAGE_LED                       = 0x08,
+  HID_USAGE_PAGE_BUTTON                    = 0x09,
+  HID_USAGE_PAGE_ORDINAL                   = 0x0a,
+  HID_USAGE_PAGE_TELEPHONY                 = 0x0b,
+  HID_USAGE_PAGE_CONSUMER                  = 0x0c,
+  HID_USAGE_PAGE_DIGITIZER                 = 0x0d,
+  HID_USAGE_PAGE_PID                       = 0x0f,
+  HID_USAGE_PAGE_UNICODE                   = 0x10,
+  HID_USAGE_PAGE_SOC                       = 0x11,
+  HID_USAGE_PAGE_EYE_AND_HEAD_TRACKERS     = 0x12,
+  // 0x13 is reserved
+  HID_USAGE_PAGE_AUXILIARY_DISPLAY         = 0x14,
+  // 0x15 - 0x1f is reserved
+  HID_USAGE_PAGE_SENSORS                   = 0x20,
+  // 0x21 - 0x3f is reserved
+  HID_USAGE_PAGE_MEDICAL_INSTRUMENT        = 0x40,
+  HID_USAGE_PAGE_LIGHTING_AND_ILLUMINATION = 0x59,
+  HID_USAGE_PAGE_MONITOR                   = 0x80, // 0x80 - 0x83
+  HID_USAGE_PAGE_POWER                     = 0x84, // 0x084 - 0x87
+  HID_USAGE_PAGE_BARCODE_SCANNER           = 0x8c,
+  HID_USAGE_PAGE_SCALE                     = 0x8d,
+  HID_USAGE_PAGE_MSR                       = 0x8e,
+  HID_USAGE_PAGE_CAMERA                    = 0x90,
+  HID_USAGE_PAGE_ARCADE                    = 0x91,
+  HID_USAGE_PAGE_FIDO                      = 0xF1D0, // FIDO alliance HID usage page
+  HID_USAGE_PAGE_VENDOR                    = 0xFF00  // 0xFF00 - 0xFFFF
 };
 
 /// HID Usage Table - Table 6: Generic Desktop Page
@@ -784,11 +890,9 @@ enum {
   HID_USAGE_DESKTOP_SYSTEM_DISPLAY_LCD_AUTOSCALE          = 0xB7
 };
 
-
 /// HID Usage Table: Consumer Page (0x0C)
 /// Only contains controls that supported by Windows (whole list is too long)
-enum
-{
+enum {
   // Generic Control
   HID_USAGE_CONSUMER_CONTROL                           = 0x0001,
 
@@ -844,6 +948,281 @@ enum
   HID_USAGE_CONSUMER_AC_PAN                            = 0x0238,
 };
 
+/// HID Usage Table: Digitizer Page (0x0D)
+enum {
+  HID_USAGE_DIGITIZER_UNDEFINED                           = 0x00,
+  HID_USAGE_DIGITIZER_DIGITIZER                           = 0x01, // CA
+  HID_USAGE_DIGITIZER_PEN                                 = 0x02, // CA
+  HID_USAGE_DIGITIZER_LIGHT_PEN                           = 0x03, // CA
+  HID_USAGE_DIGITIZER_TOUCH_SCREEN                        = 0x04, // CA
+  HID_USAGE_DIGITIZER_TOUCH_PAD                           = 0x05, // CA
+  HID_USAGE_DIGITIZER_WHITEBOARD                          = 0x06, // CA
+  HID_USAGE_DIGITIZER_COORDINATE_MEASURING_MACHINE        = 0x07, // CA
+  HID_USAGE_DIGITIZER_3D_DIGITIZER                        = 0x08, // CA
+  HID_USAGE_DIGITIZER_STEREO_PLOTTER                      = 0x09, // CA
+  HID_USAGE_DIGITIZER_ARTICULATED_ARM                     = 0x0A, // CA
+  HID_USAGE_DIGITIZER_ARMATURE                            = 0x0B, // CA
+  HID_USAGE_DIGITIZER_MULTIPLE_POINT_DIGITIZER            = 0x0C, // CA
+  HID_USAGE_DIGITIZER_FREE_SPACE_WAND                     = 0x0D, // CA
+  HID_USAGE_DIGITIZER_DEVICE_CONFIGURATION                = 0x0E, // CA
+  HID_USAGE_DIGITIZER_CAPACITIVE_HEAT_MAP_DIGITIZER       = 0x0F, // CA
+  // Reserved (0x10 - 0x1F)
+  HID_USAGE_DIGITIZER_STYLUS                              = 0x20, // CA/CL
+  HID_USAGE_DIGITIZER_PUCK                                = 0x21, // CL
+  HID_USAGE_DIGITIZER_FINGER                              = 0x22, // CL
+  HID_USAGE_DIGITIZER_DEVICE_SETTINGS                     = 0x23, // CL
+  HID_USAGE_DIGITIZER_CHARACTER_GESTURE                   = 0x24, // CL
+  // Reserved (0x25 - 0x2F)
+  HID_USAGE_DIGITIZER_TIP_PRESSURE                        = 0x30, // DV
+  HID_USAGE_DIGITIZER_BARREL_PRESSURE                     = 0x31, // DV
+  HID_USAGE_DIGITIZER_IN_RANGE                            = 0x32, // MC
+  HID_USAGE_DIGITIZER_TOUCH                               = 0x33, // MC
+  HID_USAGE_DIGITIZER_UNTOUCH                             = 0x34, // OSC
+  HID_USAGE_DIGITIZER_TAP                                 = 0x35, // OSC
+  HID_USAGE_DIGITIZER_QUALITY                             = 0x36, // DV
+  HID_USAGE_DIGITIZER_DATA_VALID                          = 0x37, // MC
+  HID_USAGE_DIGITIZER_TRANSDUCER_INDEX                    = 0x38, // DV
+  HID_USAGE_DIGITIZER_TABLET_FUNCTION_KEYS                = 0x39, // CL
+  HID_USAGE_DIGITIZER_PROGRAM_CHANGE_KEYS                 = 0x3A, // CL
+  HID_USAGE_DIGITIZER_BATTERY_STRENGTH                    = 0x3B, // DV
+  HID_USAGE_DIGITIZER_INVERT                              = 0x3C, // MC
+  HID_USAGE_DIGITIZER_X_TILT                              = 0x3D, // DV
+  HID_USAGE_DIGITIZER_Y_TILT                              = 0x3E, // DV
+  HID_USAGE_DIGITIZER_AZIMUTH                             = 0x3F, // DV
+  HID_USAGE_DIGITIZER_ALTITUDE                            = 0x40, // DV
+  HID_USAGE_DIGITIZER_TWIST                               = 0x41, // DV
+  HID_USAGE_DIGITIZER_TIP_SWITCH                          = 0x42, // MC
+  HID_USAGE_DIGITIZER_SECONDARY_TIP_SWITCH                = 0x43, // MC
+  HID_USAGE_DIGITIZER_BARREL_SWITCH                       = 0x44, // MC
+  HID_USAGE_DIGITIZER_ERASER                              = 0x45, // MC
+  HID_USAGE_DIGITIZER_TABLET_PICK                         = 0x46, // MC
+  HID_USAGE_DIGITIZER_TOUCH_VALID                         = 0x47, // MC
+  HID_USAGE_DIGITIZER_WIDTH                               = 0x48, // DV
+  HID_USAGE_DIGITIZER_HEIGHT                              = 0x49, // DV
+  // Reserved (0x4A - 0x50)
+  HID_USAGE_DIGITIZER_CONTACT_IDENTIFIER                  = 0x51, // DV
+  HID_USAGE_DIGITIZER_DEVICE_MODE                         = 0x52, // DV
+  HID_USAGE_DIGITIZER_DEVICE_IDENTIFIER                   = 0x53, // DV/SV
+  HID_USAGE_DIGITIZER_CONTACT_COUNT                       = 0x54, // DV
+  HID_USAGE_DIGITIZER_CONTACT_COUNT_MAXIMUM               = 0x55, // SV
+  HID_USAGE_DIGITIZER_SCAN_TIME                           = 0x56, // DV
+  HID_USAGE_DIGITIZER_SURFACE_SWITCH                      = 0x57, // DF
+  HID_USAGE_DIGITIZER_BUTTON_SWITCH                       = 0x58, // DF
+  HID_USAGE_DIGITIZER_PAD_TYPE                            = 0x59, // SF
+  HID_USAGE_DIGITIZER_TRANSDUCER_SERIAL_NUMBER            = 0x5B, // SV
+  HID_USAGE_DIGITIZER_PREFERRED_COLOR                     = 0x5C, // DV
+  HID_USAGE_DIGITIZER_PREFERRED_COLOR_LOCKED              = 0x5D, // MC
+  HID_USAGE_DIGITIZER_PREFERRED_LINE_WIDTH                = 0x5E, // DV
+  HID_USAGE_DIGITIZER_PREFERRED_LINE_WIDTH_LOCKED         = 0x5F, // MC
+  HID_USAGE_DIGITIZER_LATENCY_MODE                        = 0x60, // DF
+  HID_USAGE_DIGITIZER_GESTURE_CHARACTER_QUALITY           = 0x61, // DV
+  HID_USAGE_DIGITIZER_CHARACTER_GESTURE_DATA_LENGTH       = 0x62, // DV
+  HID_USAGE_DIGITIZER_CHARACTER_GESTURE_DATA              = 0x63, // DV
+  HID_USAGE_DIGITIZER_GESTURE_CHARACTER_ENCODING          = 0x64, // NAry
+  HID_USAGE_DIGITIZER_UTF8_CHARACTER_GESTURE_ENCODING     = 0x65, // Sel
+  HID_USAGE_DIGITIZER_UTF16_LE_CHARACTER_GESTURE_ENCODING = 0x66, // Sel
+  HID_USAGE_DIGITIZER_UTF16_BE_CHARACTER_GESTURE_ENCODING = 0x67, // Sel
+  HID_USAGE_DIGITIZER_UTF32_LE_CHARACTER_GESTURE_ENCODING = 0x68, // Sel
+  HID_USAGE_DIGITIZER_UTF32_BE_CHARACTER_GESTURE_ENCODING = 0x69, // Sel
+  HID_USAGE_DIGITIZER_CAPACITIVE_HEAT_MAP_VENDOR_ID       = 0x6A, // SV
+  HID_USAGE_DIGITIZER_CAPACITIVE_HEAT_MAP_VERSION         = 0x6B, // SV
+  HID_USAGE_DIGITIZER_CAPACITIVE_HEAT_MAP_FRAME_DATA      = 0x6C, // DV
+  HID_USAGE_DIGITIZER_GESTURE_CHARACTER_ENABLE            = 0x6D, // DF
+  HID_USAGE_DIGITIZER_TRANSDUCER_SERIAL_NUMBER_PART2      = 0x6E, // SV
+  HID_USAGE_DIGITIZER_NO_PREFERRED_COLOR                  = 0x6F, // DF
+  HID_USAGE_DIGITIZER_PREFERRED_LINE_STYLE                = 0x70, // NAry
+  HID_USAGE_DIGITIZER_PREFERRED_LINE_STYLE_LOCKED         = 0x71, // MC
+  HID_USAGE_DIGITIZER_INK                                 = 0x72, // Sel
+  HID_USAGE_DIGITIZER_PENCIL                              = 0x73, // Sel
+  HID_USAGE_DIGITIZER_HIGHLIGHTER                         = 0x74, // Sel
+  HID_USAGE_DIGITIZER_CHISEL_MARKER                       = 0x75, // Sel
+  HID_USAGE_DIGITIZER_BRUSH                               = 0x76, // Sel
+  HID_USAGE_DIGITIZER_NO_PREFERENCE                       = 0x77, // Sel
+  // Reserved (0x78 - 0x7F)
+  HID_USAGE_DIGITIZER_DIGITIZER_DIAGNOSTIC                = 0x80, // CL
+  HID_USAGE_DIGITIZER_DIGITIZER_ERROR                     = 0x81, // NAry
+  HID_USAGE_DIGITIZER_ERR_NORMAL_STATUS                   = 0x82, // Sel
+  HID_USAGE_DIGITIZER_ERR_TRANSDUCERS_EXCEEDED            = 0x83, // Sel
+  HID_USAGE_DIGITIZER_ERR_FULL_TRANS_FEATURES_UNAVAILABLE = 0x84, // Sel
+  HID_USAGE_DIGITIZER_ERR_CHARGE_LOW                      = 0x85, // Sel
+  // Reserved (0x86 - 0x8F)
+  HID_USAGE_DIGITIZER_TRANSDUCER_SOFTWARE_INFO            = 0x90, // CL
+  HID_USAGE_DIGITIZER_TRANSDUCER_VENDOR_ID                = 0x91, // SV
+  HID_USAGE_DIGITIZER_TRANSDUCER_PRODUCT_ID               = 0x92, // SV
+  HID_USAGE_DIGITIZER_DEVICE_SUPPORTED_PROTOCOLS          = 0x93, // NAry/CL
+  HID_USAGE_DIGITIZER_TRANSDUCER_SUPPORTED_PROTOCOLS      = 0x94, // NAry/CL
+  HID_USAGE_DIGITIZER_NO_PROTOCOL                         = 0x95, // Sel
+  HID_USAGE_DIGITIZER_WACOM_AES_PROTOCOL                  = 0x96, // Sel
+  HID_USAGE_DIGITIZER_USI_PROTOCOL                        = 0x97, // Sel
+  HID_USAGE_DIGITIZER_MICROSOFT_PEN_PROTOCOL              = 0x98, // Sel
+  // Reserved (0x99 - 0x9F)
+  HID_USAGE_DIGITIZER_SUPPORTED_REPORT_RATES              = 0xA0, // SV/CL
+  HID_USAGE_DIGITIZER_REPORT_RATE                         = 0xA1, // DV
+  HID_USAGE_DIGITIZER_TRANSDUCER_CONNECTED                = 0xA2, // SF
+  HID_USAGE_DIGITIZER_SWITCH_DISABLED                     = 0xA3, // Sel
+  HID_USAGE_DIGITIZER_SWITCH_UNIMPLEMENTED                = 0xA4, // Sel
+  HID_USAGE_DIGITIZER_TRANSDUCER_SWITCHES                 = 0xA5, // CL
+  HID_USAGE_DIGITIZER_TRANSDUCER_INDEX_SELECTOR           = 0xA6, // DV
+  // Reserved (0xA7 - 0xAF)
+  HID_USAGE_DIGITIZER_BUTTON_PRESS_THRESHOLD              = 0xB0, // DV
+
+  // Reserved (0xB1 - 0xFFFF)
+};
+
+/// HID Usage Table: Physical Input Device Page (0x0F)
+enum {
+  HID_USAGE_PID_UNDEFINED                                = 0x00,
+  HID_USAGE_PID_PHYSICAL_INPUT_DEVICE                    = 0x01,
+  HID_USAGE_PID_NORMAL                                   = 0x20,
+  HID_USAGE_PID_SET_EFFECT_REPORT                        = 0x21,
+  HID_USAGE_PID_EFFECT_PARAMETER_BLOCK_INDEX             = 0x22,
+  HID_USAGE_PID_PARAMETER_BLOCK_OFFSET                   = 0x23,
+  HID_USAGE_PID_ROM_FLAG                                 = 0x24,
+  HID_USAGE_PID_EFFECT_TYPE                              = 0x25,
+  HID_USAGE_PID_ET_CONSTANTFORCE                         = 0x26,
+  HID_USAGE_PID_ET_RAMP                                  = 0x27,
+  HID_USAGE_PID_ET_CUSTOMFORCE                           = 0x28,
+  HID_USAGE_PID_ET_SQUARE                                = 0x30,
+  HID_USAGE_PID_ET_SINE                                  = 0x31,
+  HID_USAGE_PID_ET_TRIANGLE                              = 0x32,
+  HID_USAGE_PID_ET_SAWTOOTH_UP                           = 0x33,
+  HID_USAGE_PID_ET_SAWTOOTH_DOWN                         = 0x34,
+  HID_USAGE_PID_ET_SPRING                                = 0x40,
+  HID_USAGE_PID_ET_DAMPER                                = 0x41,
+  HID_USAGE_PID_ET_INERTIA                               = 0x42,
+  HID_USAGE_PID_ET_FRICTION                              = 0x43,
+  HID_USAGE_PID_DURATION                                 = 0x50,
+  HID_USAGE_PID_SAMPLE_PERIOD                            = 0x51,
+  HID_USAGE_PID_GAIN                                     = 0x52,
+  HID_USAGE_PID_TRIGGER_BUTTON                           = 0x53,
+  HID_USAGE_PID_TRIGGER_REPEAT_INTERVAL                  = 0x54,
+  HID_USAGE_PID_AXES_ENABLE                              = 0x55,
+  HID_USAGE_PID_DIRECTION_ENABLE                         = 0x56,
+  HID_USAGE_PID_DIRECTION                                = 0x57,
+  HID_USAGE_PID_TYPE_SPECIFIC_BLOCK_OFFSET               = 0x58,
+  HID_USAGE_PID_BLOCK_TYPE                               = 0x59,
+  HID_USAGE_PID_SET_ENVELOPE_REPORT                      = 0x5a,
+  HID_USAGE_PID_ATTACK_LEVEL                             = 0x5b,
+  HID_USAGE_PID_ATTACK_TIME                              = 0x5c,
+  HID_USAGE_PID_FADE_LEVEL                               = 0x5d,
+  HID_USAGE_PID_FADE_TIME                                = 0x5e,
+  HID_USAGE_PID_SET_CONDITION_REPORT                     = 0x5f,
+  HID_USAGE_PID_CENTERPOINT_OFFSET                       = 0x60,
+  HID_USAGE_PID_POSITIVE_COEFFICIENT                     = 0x61,
+  HID_USAGE_PID_NEGATIVE_COEFFICIENT                     = 0x62,
+  HID_USAGE_PID_POSITIVE_SATURATION                      = 0x63,
+  HID_USAGE_PID_NEGATIVE_SATURATION                      = 0x64,
+  HID_USAGE_PID_DEAD_BAND                                = 0x65,
+  HID_USAGE_PID_DOWNLOAD_FORCE_SAMPLE                    = 0x66,
+  HID_USAGE_PID_ISOCH_CUSTOMFORCE_ENABLE                 = 0x67,
+  HID_USAGE_PID_CUSTOMFORCE_DATA_REPORT                  = 0x68,
+  HID_USAGE_PID_CUSTOMFORCE_DATA                         = 0x69,
+  HID_USAGE_PID_CUSTOMFORCE_VENDOR_DEFINED_DATA          = 0x6a,
+  HID_USAGE_PID_SET_CUSTOMFORCE_REPORT                   = 0x6b,
+  HID_USAGE_PID_CUSTOMFORCE_DATA_OFFSET                  = 0x6c,
+  HID_USAGE_PID_SAMPLE_COUNT                             = 0x6d,
+  HID_USAGE_PID_SET_PERIODIC_REPORT                      = 0x6e,
+  HID_USAGE_PID_OFFSET                                   = 0x6f,
+  HID_USAGE_PID_MAGNITUDE                                = 0x70,
+  HID_USAGE_PID_PHASE                                    = 0x71,
+  HID_USAGE_PID_PERIOD                                   = 0x72,
+  HID_USAGE_PID_SET_CONSTANTFORCE_REPORT                 = 0x73,
+  HID_USAGE_PID_SET_RAMPFORCE_REPORT                     = 0x74,
+  HID_USAGE_PID_RAMP_START                               = 0x75,
+  HID_USAGE_PID_RAMP_END                                 = 0x76,
+  HID_USAGE_PID_EFFECT_OPERATION_REPORT                  = 0x77,
+  HID_USAGE_PID_EFFECT_OPERATION                         = 0x78,
+  HID_USAGE_PID_OP_EFFECT_START                          = 0x79,
+  HID_USAGE_PID_OP_EFFECT_START_SOLO                     = 0x7a,
+  HID_USAGE_PID_OP_EFFECT_STOP                           = 0x7b,
+  HID_USAGE_PID_LOOP_COUNT                               = 0x7c,
+  HID_USAGE_PID_DEVICE_GAIN_REPORT                       = 0x7d,
+  HID_USAGE_PID_DEVICE_GAIN                              = 0x7e,
+  HID_USAGE_PID_PARAMETER_BLOCK_POOLS_REPORT             = 0x7f,
+  HID_USAGE_PID_RAM_POOL_SIZE                            = 0x80,
+  HID_USAGE_PID_ROM_POOL_SIZE                            = 0x81,
+  HID_USAGE_PID_ROM_EFFECT_BLOCK_COUNT                   = 0x82,
+  HID_USAGE_PID_SIMULTANEOUS_EFFECTS_MAX                 = 0x83,
+  HID_USAGE_PID_POOL_ALIGNMENT                           = 0x84,
+  HID_USAGE_PID_PARAMETER_BLOCK_MOVE_REPORT              = 0x85,
+  HID_USAGE_PID_MOVE_SOURCE                              = 0x86,
+  HID_USAGE_PID_MOVE_DESTINATION                         = 0x87,
+  HID_USAGE_PID_MOVE_LENGTH                              = 0x88,
+  HID_USAGE_PID_EFFECT_PARAMETER_BLOCK_LOAD_REPORT       = 0x89,
+  HID_USAGE_PID_EFFECT_PARAMETER_BLOCK_LOAD_STATUS       = 0x8b,
+  HID_USAGE_PID_BLOCK_LOAD_SUCCESS                       = 0x8c,
+  HID_USAGE_PID_BLOCK_LOAD_FULL                          = 0x8d,
+  HID_USAGE_PID_BLOCK_LOAD_ERROR                         = 0x8e,
+  HID_USAGE_PID_BLOCK_HANDLE                             = 0x8f,
+  HID_USAGE_PID_EFFECT_PARAMETER_BLOCK_FREE_REPORT       = 0x90,
+  HID_USAGE_PID_TYPE_SPECIFIC_BLOCK_HANDLE               = 0x91,
+  HID_USAGE_PID_PID_STATE_REPORT                         = 0x92,
+  HID_USAGE_PID_EFFECT_PLAYING                           = 0x94,
+  HID_USAGE_PID_PID_DEVICE_CONTROL_REPORT                = 0x95,
+  HID_USAGE_PID_PID_DEVICE_CONTROL                       = 0x96,
+  HID_USAGE_PID_DC_ENABLE_ACTUATORS                      = 0x97,
+  HID_USAGE_PID_DC_DISABLE_ACTUATORS                     = 0x98,
+  HID_USAGE_PID_DC_STOP_ALL_EFFECTS                      = 0x99,
+  HID_USAGE_PID_DC_RESET                                 = 0x9a,
+  HID_USAGE_PID_DC_PAUSE                                 = 0x9b,
+  HID_USAGE_PID_DC_CONTINUE                              = 0x9c,
+  HID_USAGE_PID_DEVICE_PAUSED                            = 0x9f,
+  HID_USAGE_PID_ACTUATORS_ENABLED                        = 0xa0,
+  HID_USAGE_PID_SAFETY_SWITCH                            = 0xa4,
+  HID_USAGE_PID_ACTUATOR_OVERRIDE_SWITCH                 = 0xa5,
+  HID_USAGE_PID_ACTUATOR_POWER                           = 0xa6,
+  HID_USAGE_PID_START_DELAY                              = 0xa7,
+  HID_USAGE_PID_PARAMETER_BLOCK_SIZE                     = 0xa8,
+  HID_USAGE_PID_DEVICEMANAGED_POOL                       = 0xa9,
+  HID_USAGE_PID_SHARED_PARAMETER_BLOCKS                  = 0xaa,
+  HID_USAGE_PID_CREATE_NEW_EFFECT_PARAMETER_BLOCK_REPORT = 0xab,
+  HID_USAGE_PID_RAM_POOL_AVAILABLE                       = 0xac,
+};
+
+/// HID Usage Table - Lighting And Illumination Page (0x59)
+enum {
+  HID_USAGE_LIGHTING_LAMP_ARRAY                          = 0x01,
+  HID_USAGE_LIGHTING_LAMP_ARRAY_ATTRIBUTES_REPORT        = 0x02,
+  HID_USAGE_LIGHTING_LAMP_COUNT                          = 0x03,
+  HID_USAGE_LIGHTING_BOUNDING_BOX_WIDTH_IN_MICROMETERS   = 0x04,
+  HID_USAGE_LIGHTING_BOUNDING_BOX_HEIGHT_IN_MICROMETERS  = 0x05,
+  HID_USAGE_LIGHTING_BOUNDING_BOX_DEPTH_IN_MICROMETERS   = 0x06,
+  HID_USAGE_LIGHTING_LAMP_ARRAY_KIND                     = 0x07,
+  HID_USAGE_LIGHTING_MIN_UPDATE_INTERVAL_IN_MICROSECONDS = 0x08,
+  HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_REQUEST_REPORT      = 0x20,
+  HID_USAGE_LIGHTING_LAMP_ID                             = 0x21,
+  HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_RESPONSE_REPORT     = 0x22,
+  HID_USAGE_LIGHTING_POSITION_X_IN_MICROMETERS           = 0x23,
+  HID_USAGE_LIGHTING_POSITION_Y_IN_MICROMETERS           = 0x24,
+  HID_USAGE_LIGHTING_POSITION_Z_IN_MICROMETERS           = 0x25,
+  HID_USAGE_LIGHTING_LAMP_PURPOSES                       = 0x26,
+  HID_USAGE_LIGHTING_UPDATE_LATENCY_IN_MICROSECONDS      = 0x27,
+  HID_USAGE_LIGHTING_RED_LEVEL_COUNT                     = 0x28,
+  HID_USAGE_LIGHTING_GREEN_LEVEL_COUNT                   = 0x29,
+  HID_USAGE_LIGHTING_BLUE_LEVEL_COUNT                    = 0x2A,
+  HID_USAGE_LIGHTING_INTENSITY_LEVEL_COUNT               = 0x2B,
+  HID_USAGE_LIGHTING_IS_PROGRAMMABLE                     = 0x2C,
+  HID_USAGE_LIGHTING_INPUT_BINDING                       = 0x2D,
+  HID_USAGE_LIGHTING_LAMP_MULTI_UPDATE_REPORT            = 0x50,
+  HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL                  = 0x51,
+  HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL                = 0x52,
+  HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL                 = 0x53,
+  HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL            = 0x54,
+  HID_USAGE_LIGHTING_LAMP_UPDATE_FLAGS                   = 0x55,
+  HID_USAGE_LIGHTING_LAMP_RANGE_UPDATE_REPORT            = 0x60,
+  HID_USAGE_LIGHTING_LAMP_ID_START                       = 0x61,
+  HID_USAGE_LIGHTING_LAMP_ID_END                         = 0x62,
+  HID_USAGE_LIGHTING_LAMP_ARRAY_CONTROL_REPORT           = 0x70,
+  HID_USAGE_LIGHTING_AUTONOMOUS_MODE                     = 0x71,
+};
+
+/// HID Usage Table: FIDO Alliance Page (0xF1D0)
+enum {
+  HID_USAGE_FIDO_U2FHID   = 0x01, // U2FHID usage for top-level collection
+  HID_USAGE_FIDO_DATA_IN  = 0x20, // Raw IN data report
+  HID_USAGE_FIDO_DATA_OUT = 0x21  // Raw OUT data report
+};
+
 /*--------------------------------------------------------------------
  * ASCII to KEYCODE Conversion
  *  Expand to array of [128][2] (shift, keycode)
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 8077e4deb..b4f24902b 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -39,96 +39,114 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;
   uint8_t ep_in;
-  uint8_t ep_out;        // optional Out endpoint
-  uint8_t itf_protocol;  // Boot mouse or keyboard
+  uint8_t ep_out;       // optional Out endpoint
+  uint8_t itf_protocol; // Boot mouse or keyboard
 
+  uint16_t report_desc_len;
   uint8_t protocol_mode; // Boot (0) or Report protocol (1)
   uint8_t idle_rate;     // up to application to handle idle rate
-  uint16_t report_desc_len;
-
-  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE];
-  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE];
 
   // TODO save hid descriptor since host can specifically request this after enumeration
   // Note: HID descriptor may be not available from application after enumeration
-  tusb_hid_descriptor_hid_t const * hid_descriptor;
+  const tusb_hid_descriptor_hid_t*hid_descriptor;
 } hidd_interface_t;
 
-CFG_TUSB_MEM_SECTION static hidd_interface_t _hidd_itf[CFG_TUD_HID];
+typedef struct {
+  TUD_EPBUF_DEF(ctrl , CFG_TUD_HID_EP_BUFSIZE);
+  TUD_EPBUF_DEF(epin , CFG_TUD_HID_EP_BUFSIZE);
+  TUD_EPBUF_DEF(epout, CFG_TUD_HID_EP_BUFSIZE);
+} hidd_epbuf_t;
+
+static hidd_interface_t _hidd_itf[CFG_TUD_HID];
+CFG_TUD_MEM_SECTION static hidd_epbuf_t _hidd_epbuf[CFG_TUD_HID];
 
 /*------------- Helpers -------------*/
-static inline uint8_t get_index_by_itfnum(uint8_t itf_num)
-{
-	for (uint8_t i=0; i < CFG_TUD_HID; i++ )
-	{
-		if ( itf_num == _hidd_itf[i].itf_num ) return i;
-	}
+TU_ATTR_ALWAYS_INLINE static inline uint8_t get_index_by_itfnum(uint8_t itf_num) {
+  for (uint8_t i = 0; i < CFG_TUD_HID; i++) {
+    if (itf_num == _hidd_itf[i].itf_num) {
+      return i;
+    }
+  }
+  return 0xFF;
+}
 
-	return 0xFF;
+//--------------------------------------------------------------------+
+// Weak stubs: invoked if no strong implementation is available
+//--------------------------------------------------------------------+
+TU_ATTR_WEAK void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol) {
+  (void) instance;
+  (void) protocol;
+}
+
+TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate) {
+  (void) instance;
+  (void) idle_rate;
+  return true;
+}
+
+TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len) {
+  (void) instance;
+  (void) report;
+  (void) len;
+}
+
+// Invoked when a transfer wasn't successful
+TU_ATTR_WEAK void tud_hid_report_failed_cb(uint8_t instance, hid_report_type_t report_type, uint8_t const* report, uint16_t xferred_bytes) {
+  (void) instance;
+  (void) report_type;
+  (void) report;
+  (void) xferred_bytes;
 }
 
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
-bool tud_hid_n_ready(uint8_t instance)
-{
+bool tud_hid_n_ready(uint8_t instance) {
   uint8_t const rhport = 0;
   uint8_t const ep_in = _hidd_itf[instance].ep_in;
   return tud_ready() && (ep_in != 0) && !usbd_edpt_busy(rhport, ep_in);
 }
 
-bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, uint16_t len)
-{
-  uint8_t const rhport = 0;
-  hidd_interface_t * p_hid = &_hidd_itf[instance];
+bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const *report, uint16_t len) {
+  TU_VERIFY(instance < CFG_TUD_HID);
+  const uint8_t rhport = 0;
+  hidd_interface_t *p_hid = &_hidd_itf[instance];
+  hidd_epbuf_t *p_epbuf = &_hidd_epbuf[instance];
 
   // claim endpoint
-  TU_VERIFY( usbd_edpt_claim(rhport, p_hid->ep_in) );
+  TU_VERIFY(usbd_edpt_claim(rhport, p_hid->ep_in));
 
   // prepare data
-  if (report_id)
-  {
-    len = tu_min16(len, CFG_TUD_HID_EP_BUFSIZE-1);
-
-    p_hid->epin_buf[0] = report_id;
-    memcpy(p_hid->epin_buf+1, report, len);
+  if (report_id) {
+    p_epbuf->epin[0] = report_id;
+    TU_VERIFY(0 == tu_memcpy_s(p_epbuf->epin + 1, CFG_TUD_HID_EP_BUFSIZE - 1, report, len));
     len++;
-  }else
-  {
-    // If report id = 0, skip ID field
-    len = tu_min16(len, CFG_TUD_HID_EP_BUFSIZE);
-    memcpy(p_hid->epin_buf, report, len);
+  } else {
+    TU_VERIFY(0 == tu_memcpy_s(p_epbuf->epin, CFG_TUD_HID_EP_BUFSIZE, report, len));
   }
 
-  return usbd_edpt_xfer(rhport, p_hid->ep_in, p_hid->epin_buf, len);
+  return usbd_edpt_xfer(rhport, p_hid->ep_in, p_epbuf->epin, len);
 }
 
-uint8_t tud_hid_n_interface_protocol(uint8_t instance)
-{
+uint8_t tud_hid_n_interface_protocol(uint8_t instance) {
   return _hidd_itf[instance].itf_protocol;
 }
 
-uint8_t tud_hid_n_get_protocol(uint8_t instance)
-{
+uint8_t tud_hid_n_get_protocol(uint8_t instance) {
   return _hidd_itf[instance].protocol_mode;
 }
 
-bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modifier, uint8_t keycode[6])
-{
+bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modifier, const uint8_t keycode[6]) {
   hid_keyboard_report_t report;
-
   report.modifier = modifier;
   report.reserved = 0;
 
-  if ( keycode )
-  {
-    memcpy(report.keycode, keycode, 6);
-  }else
-  {
+  if (keycode) {
+    memcpy(report.keycode, keycode, sizeof(report.keycode));
+  } else {
     tu_memclr(report.keycode, 6);
   }
 
@@ -136,33 +154,51 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi
 }
 
 bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id,
-                            uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal)
-{
-  hid_mouse_report_t report =
-  {
+                            uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal) {
+  hid_mouse_report_t report = {
     .buttons = buttons,
-    .x       = x,
-    .y       = y,
-    .wheel   = vertical,
-    .pan     = horizontal
+    .x = x,
+    .y = y,
+    .wheel = vertical,
+    .pan = horizontal
   };
 
   return tud_hid_n_report(instance, report_id, &report, sizeof(report));
 }
 
-bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
-                              int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons)
-{
-  hid_gamepad_report_t report =
-  {
-    .x       = x,
-    .y       = y,
-    .z       = z,
-    .rz      = rz,
-    .rx      = rx,
-    .ry      = ry,
-    .hat     = hat,
+bool tud_hid_n_abs_mouse_report(uint8_t instance, uint8_t report_id,
+                                uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal) {
+  hid_abs_mouse_report_t report = {
     .buttons = buttons,
+    .x = x,
+    .y = y,
+    .wheel = vertical,
+    .pan = horizontal
+  };
+  return tud_hid_n_report(instance, report_id, &report, sizeof(report));
+}
+
+bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
+                              int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) {
+  hid_gamepad_report_t report = {
+      .x = x,
+      .y = y,
+      .z = z,
+      .rz = rz,
+      .rx = rx,
+      .ry = ry,
+      .hat = hat,
+      .buttons = buttons,
+  };
+
+  return tud_hid_n_report(instance, report_id, &report, sizeof(report));
+}
+
+bool tud_hid_n_stylus_report(uint8_t instance, uint8_t report_id, uint8_t attrs, uint16_t x, uint16_t y) {
+  hid_stylus_report_t report = {
+    .attr = attrs,
+    .x = x,
+    .y = y,
   };
 
   return tud_hid_n_report(instance, report_id, &report, sizeof(report));
@@ -171,19 +207,20 @@ bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
 //--------------------------------------------------------------------+
 // USBD-CLASS API
 //--------------------------------------------------------------------+
-void hidd_init(void)
-{
+void hidd_init(void) {
   hidd_reset(0);
 }
 
-void hidd_reset(uint8_t rhport)
-{
-  (void) rhport;
+bool hidd_deinit(void) {
+  return true;
+}
+
+void hidd_reset(uint8_t rhport) {
+  (void)rhport;
   tu_memclr(_hidd_itf, sizeof(_hidd_itf));
 }
 
-uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len)
-{
+uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const *desc_itf, uint16_t max_len) {
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass, 0);
 
   // len = interface + hid + n*endpoints
@@ -192,45 +229,41 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1
   TU_ASSERT(max_len >= drv_len, 0);
 
   // Find available interface
-  hidd_interface_t * p_hid = NULL;
+  hidd_interface_t *p_hid;
   uint8_t hid_id;
-  for(hid_id=0; hid_id<CFG_TUD_HID; hid_id++)
-  {
-    if ( _hidd_itf[hid_id].ep_in == 0 )
-    {
-      p_hid = &_hidd_itf[hid_id];
+  for (hid_id = 0; hid_id < CFG_TUD_HID; hid_id++) {
+    p_hid = &_hidd_itf[hid_id];
+    if (p_hid->ep_in == 0) {
       break;
     }
   }
-  TU_ASSERT(p_hid, 0);
+  TU_ASSERT(hid_id < CFG_TUD_HID, 0);
+  hidd_epbuf_t *p_epbuf = &_hidd_epbuf[hid_id];
 
-  uint8_t const *p_desc = (uint8_t const *) desc_itf;
+  uint8_t const *p_desc = (uint8_t const *)desc_itf;
 
   //------------- HID descriptor -------------//
   p_desc = tu_desc_next(p_desc);
   TU_ASSERT(HID_DESC_TYPE_HID == tu_desc_type(p_desc), 0);
-  p_hid->hid_descriptor = (tusb_hid_descriptor_hid_t const *) p_desc;
+  p_hid->hid_descriptor = (tusb_hid_descriptor_hid_t const *)p_desc;
 
   //------------- Endpoint Descriptor -------------//
   p_desc = tu_desc_next(p_desc);
   TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_INTERRUPT, &p_hid->ep_out, &p_hid->ep_in), 0);
 
-  if ( desc_itf->bInterfaceSubClass == HID_SUBCLASS_BOOT ) p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
+  if (desc_itf->bInterfaceSubClass == HID_SUBCLASS_BOOT) {
+    p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
+  }
 
   p_hid->protocol_mode = HID_PROTOCOL_REPORT; // Per Specs: default is report mode
-  p_hid->itf_num       = desc_itf->bInterfaceNumber;
+  p_hid->itf_num = desc_itf->bInterfaceNumber;
 
   // Use offsetof to avoid pointer to the odd/misaligned address
-  p_hid->report_desc_len = tu_unaligned_read16((uint8_t const*) p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength));
+  p_hid->report_desc_len = tu_unaligned_read16((uint8_t const *)p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength));
 
   // Prepare for output endpoint
-  if (p_hid->ep_out)
-  {
-    if ( !usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)) )
-    {
-      TU_LOG_FAILED();
-      TU_BREAKPOINT();
-    }
+  if (p_hid->ep_out) {
+    TU_ASSERT(usbd_edpt_xfer(rhport, p_hid->ep_out, p_epbuf->epout, CFG_TUD_HID_EP_BUFSIZE), drv_len);
   }
 
   return drv_len;
@@ -239,178 +272,148 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
+bool hidd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) {
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
 
-  uint8_t const hid_itf = get_index_by_itfnum((uint8_t) request->wIndex);
+  uint8_t const hid_itf = get_index_by_itfnum((uint8_t)request->wIndex);
   TU_VERIFY(hid_itf < CFG_TUD_HID);
+  hidd_interface_t *p_hid = &_hidd_itf[hid_itf];
+  hidd_epbuf_t *p_epbuf = &_hidd_epbuf[hid_itf];
 
-  hidd_interface_t* p_hid = &_hidd_itf[hid_itf];
-
-  if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD)
-  {
+  if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) {
     //------------- STD Request -------------//
-    if ( stage == CONTROL_STAGE_SETUP )
-    {
-      uint8_t const desc_type  = tu_u16_high(request->wValue);
-      //uint8_t const desc_index = tu_u16_low (request->wValue);
+    if (stage == CONTROL_STAGE_SETUP) {
+      uint8_t const desc_type = tu_u16_high(request->wValue);
+      // uint8_t const desc_index = tu_u16_low (request->wValue);
 
-      if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID)
-      {
+      if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID) {
         TU_VERIFY(p_hid->hid_descriptor);
-        TU_VERIFY(tud_control_xfer(rhport, request, (void*)(uintptr_t) p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
-      }
-      else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT)
-      {
-        uint8_t const * desc_report = tud_hid_descriptor_report_cb(hid_itf);
-        tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_report, p_hid->report_desc_len);
-      }
-      else
-      {
+        TU_VERIFY(tud_control_xfer(rhport, request, (void *)(uintptr_t)p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
+      } else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT) {
+        uint8_t const *desc_report = tud_hid_descriptor_report_cb(hid_itf);
+        tud_control_xfer(rhport, request, (void *)(uintptr_t)desc_report, p_hid->report_desc_len);
+      } else {
         return false; // stall unsupported request
       }
     }
-  }
-  else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS)
-  {
+  } else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS) {
     //------------- Class Specific Request -------------//
-    switch( request->bRequest )
-    {
+    switch (request->bRequest) {
       case HID_REQ_CONTROL_GET_REPORT:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           uint8_t const report_type = tu_u16_high(request->wValue);
-          uint8_t const report_id   = tu_u16_low(request->wValue);
+          uint8_t const report_id = tu_u16_low(request->wValue);
 
-          uint8_t* report_buf = p_hid->epin_buf;
+          uint8_t* report_buf = p_epbuf->ctrl;
           uint16_t req_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
-
           uint16_t xferlen = 0;
 
           // If host request a specific Report ID, add ID to as 1 byte of response
-          if ( (report_id != HID_REPORT_TYPE_INVALID) && (req_len > 1) )
-          {
+          if ((report_id != HID_REPORT_TYPE_INVALID) && (req_len > 1)) {
             *report_buf++ = report_id;
             req_len--;
-
             xferlen++;
           }
 
           xferlen += tud_hid_get_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, report_buf, req_len);
-          TU_ASSERT( xferlen > 0 );
+          TU_ASSERT(xferlen > 0);
 
-          tud_control_xfer(rhport, request, p_hid->epin_buf, xferlen);
+          tud_control_xfer(rhport, request, p_epbuf->ctrl, xferlen);
         }
-      break;
+        break;
 
-      case  HID_REQ_CONTROL_SET_REPORT:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
-          TU_VERIFY(request->wLength <= sizeof(p_hid->epout_buf));
-          tud_control_xfer(rhport, request, p_hid->epout_buf, request->wLength);
-        }
-        else if ( stage == CONTROL_STAGE_ACK )
-        {
+      case HID_REQ_CONTROL_SET_REPORT:
+        if (stage == CONTROL_STAGE_SETUP) {
+          TU_VERIFY(request->wLength <= CFG_TUD_HID_EP_BUFSIZE);
+          tud_control_xfer(rhport, request, p_epbuf->ctrl, request->wLength);
+        } else if (stage == CONTROL_STAGE_ACK) {
           uint8_t const report_type = tu_u16_high(request->wValue);
-          uint8_t const report_id   = tu_u16_low(request->wValue);
+          uint8_t const report_id = tu_u16_low(request->wValue);
 
-          uint8_t const* report_buf = p_hid->epout_buf;
+          uint8_t const* report_buf = p_epbuf->ctrl;
           uint16_t report_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
 
           // If host request a specific Report ID, extract report ID in buffer before invoking callback
-          if ( (report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == report_buf[0]) )
-          {
+          if ((report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == report_buf[0])) {
             report_buf++;
             report_len--;
           }
 
           tud_hid_set_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, report_buf, report_len);
         }
-      break;
+        break;
 
       case HID_REQ_CONTROL_SET_IDLE:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           p_hid->idle_rate = tu_u16_high(request->wValue);
-          if ( tud_hid_set_idle_cb )
-          {
-            // stall request if callback return false
-            TU_VERIFY( tud_hid_set_idle_cb( hid_itf, p_hid->idle_rate) );
-          }
-
+          TU_VERIFY(tud_hid_set_idle_cb(hid_itf, p_hid->idle_rate)); // stall if false
           tud_control_status(rhport, request);
         }
-      break;
+        break;
 
       case HID_REQ_CONTROL_GET_IDLE:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           // TODO idle rate of report
           tud_control_xfer(rhport, request, &p_hid->idle_rate, 1);
         }
-      break;
+        break;
 
       case HID_REQ_CONTROL_GET_PROTOCOL:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           tud_control_xfer(rhport, request, &p_hid->protocol_mode, 1);
         }
-      break;
+        break;
 
       case HID_REQ_CONTROL_SET_PROTOCOL:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
+        if (stage == CONTROL_STAGE_SETUP) {
           tud_control_status(rhport, request);
-        }
-        else if ( stage == CONTROL_STAGE_ACK )
-        {
+        } else if (stage == CONTROL_STAGE_ACK) {
           p_hid->protocol_mode = (uint8_t) request->wValue;
-          if (tud_hid_set_protocol_cb)
-          {
-            tud_hid_set_protocol_cb(hid_itf, p_hid->protocol_mode);
-          }
+          tud_hid_set_protocol_cb(hid_itf, p_hid->protocol_mode);
         }
-      break;
+        break;
 
-      default: return false; // stall unsupported request
+      default:
+        return false; // stall unsupported request
     }
-  }else
-  {
+  } else {
     return false; // stall unsupported request
   }
 
   return true;
 }
 
-bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
-  (void) result;
-
-  uint8_t instance = 0;
-  hidd_interface_t * p_hid = _hidd_itf;
+bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
+  uint8_t instance;
+  hidd_interface_t *p_hid;
 
   // Identify which interface to use
-  for (instance = 0; instance < CFG_TUD_HID; instance++)
-  {
+  for (instance = 0; instance < CFG_TUD_HID; instance++) {
     p_hid = &_hidd_itf[instance];
-    if ( (ep_addr == p_hid->ep_out) || (ep_addr == p_hid->ep_in) ) break;
-  }
-  TU_ASSERT(instance < CFG_TUD_HID);
-
-  // Sent report successfully
-  if (ep_addr == p_hid->ep_in)
-  {
-    if (tud_hid_report_complete_cb)
-    {
-      tud_hid_report_complete_cb(instance, p_hid->epin_buf, (/*uint16_t*/ uint8_t) xferred_bytes);
+    if ((ep_addr == p_hid->ep_out) || (ep_addr == p_hid->ep_in)) {
+      break;
     }
   }
-  // Received report
-  else if (ep_addr == p_hid->ep_out)
-  {
-    tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_INVALID, p_hid->epout_buf, (uint16_t) xferred_bytes);
-    TU_ASSERT(usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)));
+  TU_ASSERT(instance < CFG_TUD_HID);
+  hidd_epbuf_t *p_epbuf = &_hidd_epbuf[instance];
+
+  if (ep_addr == p_hid->ep_in) {
+    // Input report
+    if (XFER_RESULT_SUCCESS == result) {
+      tud_hid_report_complete_cb(instance, p_epbuf->epin, (uint16_t) xferred_bytes);
+    } else {
+      tud_hid_report_failed_cb(instance, HID_REPORT_TYPE_INPUT, p_epbuf->epin, (uint16_t) xferred_bytes);
+    }
+  } else {
+    // Output report
+    if (XFER_RESULT_SUCCESS == result) {
+      tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_OUTPUT, p_epbuf->epout, (uint16_t)xferred_bytes);
+    } else {
+      tud_hid_report_failed_cb(instance, HID_REPORT_TYPE_OUTPUT, p_epbuf->epout, (uint16_t) xferred_bytes);
+    }
+
+    // prepare for new transfer
+    TU_ASSERT(usbd_edpt_xfer(rhport, p_hid->ep_out, p_epbuf->epout, CFG_TUD_HID_EP_BUFSIZE));
   }
 
   return true;
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 3143b1024..fc1dbcbd8 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_HID_DEVICE_H_
-#define _TUSB_HID_DEVICE_H_
+#ifndef TUSB_HID_DEVICE_H_
+#define TUSB_HID_DEVICE_H_
 
 #include "hid.h"
 
@@ -48,8 +48,7 @@
 #endif
 
 //--------------------------------------------------------------------+
-// Application API (Multiple Instances)
-// CFG_TUD_HID > 1
+// Application API (Multiple Instances) i.e. CFG_TUD_HID > 1
 //--------------------------------------------------------------------+
 
 // Check if the interface is ready to use
@@ -66,29 +65,64 @@ bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, u
 
 // KEYBOARD: convenient helper to send keyboard report if application
 // use template layout report as defined by hid_keyboard_report_t
-bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modifier, uint8_t keycode[6]);
+bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modifier, const uint8_t keycode[6]);
 
 // MOUSE: convenient helper to send mouse report if application
 // use template layout report as defined by hid_mouse_report_t
 bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal);
 
+// ABSOLUTE MOUSE: convenient helper to send absolute mouse report if application
+// use template layout report as defined by hid_abs_mouse_report_t
+bool tud_hid_n_abs_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal);
+
 // Gamepad: convenient helper to send gamepad report if application
 // use template layout report TUD_HID_REPORT_DESC_GAMEPAD
 bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons);
 
+// STYLUS PEN: convenient helper to send absolute stylus pen report if application
+bool tud_hid_n_stylus_report(uint8_t instance, uint8_t report_id, uint8_t attrs, uint16_t x, uint16_t y);
+
 //--------------------------------------------------------------------+
 // Application API (Single Port)
 //--------------------------------------------------------------------+
-static inline bool    tud_hid_ready(void);
-static inline uint8_t tud_hid_interface_protocol(void);
-static inline uint8_t tud_hid_get_protocol(void);
-static inline bool    tud_hid_report(uint8_t report_id, void const* report, uint16_t len);
-static inline bool    tud_hid_keyboard_report(uint8_t report_id, uint8_t modifier, uint8_t keycode[6]);
-static inline bool    tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal);
-static inline bool    tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons);
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_ready(void) {
+  return tud_hid_n_ready(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tud_hid_interface_protocol(void) {
+  return tud_hid_n_interface_protocol(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tud_hid_get_protocol(void) {
+  return tud_hid_n_get_protocol(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_report(uint8_t report_id, void const* report, uint16_t len) {
+  return tud_hid_n_report(0, report_id, report, len);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_keyboard_report(uint8_t report_id, uint8_t modifier, const uint8_t keycode[6]) {
+  return tud_hid_n_keyboard_report(0, report_id, modifier, keycode);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal) {
+  return tud_hid_n_mouse_report(0, report_id, buttons, x, y, vertical, horizontal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_abs_mouse_report(uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal) {
+  return tud_hid_n_abs_mouse_report(0, report_id, buttons, x, y, vertical, horizontal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) {
+  return tud_hid_n_gamepad_report(0, report_id, x, y, z, rz, rx, ry, hat, buttons);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_stylus_report(uint8_t report_id, uint8_t attrs, uint16_t x, uint16_t y) {
+  return tud_hid_n_stylus_report(0, report_id, attrs, x, y);
+}
 
 //--------------------------------------------------------------------+
-// Callbacks (Weak is optional)
+// Application Callbacks
 //--------------------------------------------------------------------+
 
 // Invoked when received GET HID REPORT DESCRIPTOR request
@@ -101,61 +135,25 @@ uint8_t const * tud_hid_descriptor_report_cb(uint8_t instance);
 uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen);
 
 // Invoked when received SET_REPORT control request or
-// received data on OUT endpoint ( Report ID = 0, Type = 0 )
+// received data on OUT endpoint (Report ID = 0, Type = OUTPUT)
 void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize);
 
 // Invoked when received SET_PROTOCOL request
 // protocol is either HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
-TU_ATTR_WEAK void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol);
+void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol);
 
 // Invoked when received SET_IDLE request. return false will stall the request
-// - Idle Rate = 0 : only send report if there is changes, i.e skip duplication
+// - Idle Rate = 0 : only send report if there is changes, i.e. skip duplication
 // - Idle Rate > 0 : skip duplication, but send at least 1 report every idle rate (in unit of 4 ms).
-TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
+bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
 
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len );
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len);
 
-
-//--------------------------------------------------------------------+
-// Inline Functions
-//--------------------------------------------------------------------+
-static inline bool tud_hid_ready(void)
-{
-  return tud_hid_n_ready(0);
-}
-
-static inline uint8_t tud_hid_interface_protocol(void)
-{
-  return tud_hid_n_interface_protocol(0);
-}
-
-static inline uint8_t tud_hid_get_protocol(void)
-{
-  return tud_hid_n_get_protocol(0);
-}
-
-static inline bool tud_hid_report(uint8_t report_id, void const* report, uint16_t len)
-{
-  return tud_hid_n_report(0, report_id, report, len);
-}
-
-static inline bool tud_hid_keyboard_report(uint8_t report_id, uint8_t modifier, uint8_t keycode[6])
-{
-  return tud_hid_n_keyboard_report(0, report_id, modifier, keycode);
-}
-
-static inline bool tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal)
-{
-  return tud_hid_n_mouse_report(0, report_id, buttons, x, y, vertical, horizontal);
-}
-
-static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons)
-{
-  return tud_hid_n_gamepad_report(0, report_id, x, y, z, rz, rx, ry, hat, buttons);
-}
+// Invoked when a transfer wasn't successful
+void tud_hid_report_failed_cb(uint8_t instance, hid_report_type_t report_type, uint8_t const* report, uint16_t xferred_bytes);
 
 /* --------------------------------------------------------------------+
  * HID Report Descriptor Template
@@ -182,7 +180,7 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
   HID_COLLECTION ( HID_COLLECTION_APPLICATION )                    ,\
     /* Report ID if any */\
     __VA_ARGS__ \
-    /* 8 bits Modifier Keys (Shfit, Control, Alt) */ \
+    /* 8 bits Modifier Keys (Shift, Control, Alt) */ \
     HID_USAGE_PAGE ( HID_USAGE_PAGE_KEYBOARD )                     ,\
       HID_USAGE_MIN    ( 224                                    )  ,\
       HID_USAGE_MAX    ( 231                                    )  ,\
@@ -266,6 +264,90 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     HID_COLLECTION_END                                            , \
   HID_COLLECTION_END \
 
+// Stylus Pen Report Descriptor Template
+#define TUD_HID_REPORT_DESC_STYLUS_PEN(...) \
+  HID_USAGE_PAGE ( HID_USAGE_PAGE_DIGITIZER )                     , \
+  HID_USAGE      ( HID_USAGE_DIGITIZER_TOUCH_SCREEN )             , \
+  HID_COLLECTION ( HID_COLLECTION_APPLICATION  )                  , \
+    /* Report ID if any */\
+    __VA_ARGS__ \
+    HID_USAGE    ( HID_USAGE_DIGITIZER_STYLUS )                   , \
+    HID_COLLECTION ( HID_COLLECTION_PHYSICAL   )                  , \
+      HID_USAGE_PAGE  ( HID_USAGE_DIGITIZER_TIP_SWITCH )          , \
+      HID_USAGE_PAGE  ( HID_USAGE_DIGITIZER_IN_RANGE )            , \
+        HID_LOGICAL_MIN ( 0                                      ), \
+        HID_LOGICAL_MAX ( 1                                      ), \
+        HID_REPORT_SIZE ( 1                                      ), \
+        HID_REPORT_COUNT( 2                                      ), \
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ), \
+        HID_REPORT_SIZE ( 1                                      ), \
+        HID_REPORT_COUNT( 6                                      ), \
+        HID_INPUT       ( HID_CONSTANT | HID_ARRAY | HID_ABSOLUTE), \
+      HID_USAGE_PAGE    ( HID_USAGE_PAGE_DESKTOP                 ), \
+        HID_PHYSICAL_MAX_N( 0x7fff, 2                            ), \
+        HID_LOGICAL_MAX_N ( 0x7fff, 2                            ), \
+        HID_REPORT_SIZE ( 16                                     ), \
+        HID_REPORT_COUNT( 1                                      ), \
+        HID_UNIT_EXPONENT( 0x0f                                  ), \
+        HID_UNIT        ( HID_VARIABLE | HID_NONLINEAR           ), \
+        HID_PHYSICAL_MIN( 0                                      ), \
+        HID_PHYSICAL_MAX( 0                                      ), \
+        HID_USAGE       ( HID_USAGE_DESKTOP_X                    ), \
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ), \
+        HID_USAGE       ( HID_USAGE_DESKTOP_Y                    ), \
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ), \
+    HID_COLLECTION_END                                          , \
+  HID_COLLECTION_END \
+
+// Absolute Mouse Report Descriptor Template
+#define TUD_HID_REPORT_DESC_ABSMOUSE(...) \
+  HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP      )                   ,\
+  HID_USAGE      ( HID_USAGE_DESKTOP_MOUSE     )                   ,\
+  HID_COLLECTION ( HID_COLLECTION_APPLICATION  )                   ,\
+    /* Report ID if any */\
+    __VA_ARGS__ \
+    HID_USAGE      ( HID_USAGE_DESKTOP_POINTER )                   ,\
+    HID_COLLECTION ( HID_COLLECTION_PHYSICAL   )                   ,\
+      HID_USAGE_PAGE  ( HID_USAGE_PAGE_BUTTON  )                   ,\
+        HID_USAGE_MIN   ( 1                                      ) ,\
+        HID_USAGE_MAX   ( 5                                      ) ,\
+        HID_LOGICAL_MIN ( 0                                      ) ,\
+        HID_LOGICAL_MAX ( 1                                      ) ,\
+        /* Left, Right, Middle, Backward, Forward buttons */ \
+        HID_REPORT_COUNT( 5                                      ) ,\
+        HID_REPORT_SIZE ( 1                                      ) ,\
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+        /* 3 bit padding */ \
+        HID_REPORT_COUNT( 1                                      ) ,\
+        HID_REPORT_SIZE ( 3                                      ) ,\
+        HID_INPUT       ( HID_CONSTANT                           ) ,\
+      HID_USAGE_PAGE  ( HID_USAGE_PAGE_DESKTOP )                   ,\
+        /* X, Y absolute position [0, 32767] */ \
+        HID_USAGE       ( HID_USAGE_DESKTOP_X                    ) ,\
+        HID_USAGE       ( HID_USAGE_DESKTOP_Y                    ) ,\
+        HID_LOGICAL_MIN  ( 0x00                                ) ,\
+        HID_LOGICAL_MAX_N( 0x7FFF, 2                           ) ,\
+        HID_REPORT_SIZE  ( 16                                  ) ,\
+        HID_REPORT_COUNT ( 2                                   ) ,\
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+        /* Vertical wheel scroll [-127, 127] */ \
+        HID_USAGE       ( HID_USAGE_DESKTOP_WHEEL                )  ,\
+        HID_LOGICAL_MIN ( 0x81                                   )  ,\
+        HID_LOGICAL_MAX ( 0x7f                                   )  ,\
+        HID_REPORT_COUNT( 1                                      )  ,\
+        HID_REPORT_SIZE ( 8                                      )  ,\
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_RELATIVE )  ,\
+      HID_USAGE_PAGE  ( HID_USAGE_PAGE_CONSUMER ), \
+       /* Horizontal wheel scroll [-127, 127] */ \
+        HID_USAGE_N     ( HID_USAGE_CONSUMER_AC_PAN, 2           ), \
+        HID_LOGICAL_MIN ( 0x81                                   ), \
+        HID_LOGICAL_MAX ( 0x7f                                   ), \
+        HID_REPORT_COUNT( 1                                      ), \
+        HID_REPORT_SIZE ( 8                                      ), \
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_RELATIVE ), \
+    HID_COLLECTION_END                                            , \
+  HID_COLLECTION_END \
+
 // Consumer Control Report Descriptor Template
 #define TUD_HID_REPORT_DESC_CONSUMER(...) \
   HID_USAGE_PAGE ( HID_USAGE_PAGE_CONSUMER    )              ,\
@@ -352,6 +434,31 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     HID_INPUT          ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
 
+// FIDO U2F Authenticator Descriptor Template
+// - 1st parameter is report size, which is 64 bytes maximum in U2F
+// - 2nd parameter is HID_REPORT_ID(n) (optional)
+#define TUD_HID_REPORT_DESC_FIDO_U2F(report_size, ...) \
+  HID_USAGE_PAGE_N ( HID_USAGE_PAGE_FIDO, 2                    ) ,\
+  HID_USAGE      ( HID_USAGE_FIDO_U2FHID                       ) ,\
+  HID_COLLECTION ( HID_COLLECTION_APPLICATION                  ) ,\
+    /* Report ID if any */ \
+    __VA_ARGS__ \
+    /* Usage Data In */ \
+    HID_USAGE         ( HID_USAGE_FIDO_DATA_IN                 ) ,\
+    HID_LOGICAL_MIN   ( 0                                      ) ,\
+    HID_LOGICAL_MAX_N ( 0xff, 2                                ) ,\
+    HID_REPORT_SIZE   ( 8                                      ) ,\
+    HID_REPORT_COUNT  ( report_size                            ) ,\
+    HID_INPUT         ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+    /* Usage Data Out */ \
+    HID_USAGE         ( HID_USAGE_FIDO_DATA_OUT                ) ,\
+    HID_LOGICAL_MIN   ( 0                                      ) ,\
+    HID_LOGICAL_MAX_N ( 0xff, 2                                ) ,\
+    HID_REPORT_SIZE   ( 8                                      ) ,\
+    HID_REPORT_COUNT  ( report_size                            ) ,\
+    HID_OUTPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+  HID_COLLECTION_END \
+
 // HID Generic Input & Output
 // - 1st parameter is report size (mandatory)
 // - 2nd parameter is report id HID_REPORT_ID(n) (optional)
@@ -377,10 +484,183 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
       HID_OUTPUT      ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE  ),\
     HID_COLLECTION_END \
 
+// HID Lighting and Illumination Report Descriptor Template
+// - 1st parameter is report id (required)
+//   Creates 6 report ids for lighting HID usages in the following order:
+//     report_id+0: HID_USAGE_LIGHTING_LAMP_ARRAY_ATTRIBUTES_REPORT
+//     report_id+1: HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_REQUEST_REPORT
+//     report_id+2: HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_RESPONSE_REPORT
+//     report_id+3: HID_USAGE_LIGHTING_LAMP_MULTI_UPDATE_REPORT
+//     report_id+4: HID_USAGE_LIGHTING_LAMP_RANGE_UPDATE_REPORT
+//     report_id+5: HID_USAGE_LIGHTING_LAMP_ARRAY_CONTROL_REPORT
+#define TUD_HID_REPORT_DESC_LIGHTING(report_id) \
+  HID_USAGE_PAGE ( HID_USAGE_PAGE_LIGHTING_AND_ILLUMINATION ),\
+  HID_USAGE      ( HID_USAGE_LIGHTING_LAMP_ARRAY            ),\
+  HID_COLLECTION ( HID_COLLECTION_APPLICATION               ),\
+    /* Lamp Array Attributes Report */ \
+    HID_REPORT_ID (report_id                                    ) \
+    HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ARRAY_ATTRIBUTES_REPORT ),\
+    HID_COLLECTION ( HID_COLLECTION_LOGICAL                     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_COUNT                          ),\
+      HID_LOGICAL_MIN   ( 0                                                      ),\
+      HID_LOGICAL_MAX_N ( 65535, 3                                               ),\
+      HID_REPORT_SIZE   ( 16                                                     ),\
+      HID_REPORT_COUNT  ( 1                                                      ),\
+      HID_FEATURE       ( HID_CONSTANT | HID_VARIABLE | HID_ABSOLUTE             ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BOUNDING_BOX_WIDTH_IN_MICROMETERS   ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BOUNDING_BOX_HEIGHT_IN_MICROMETERS  ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BOUNDING_BOX_DEPTH_IN_MICROMETERS   ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_ARRAY_KIND                     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_MIN_UPDATE_INTERVAL_IN_MICROSECONDS ),\
+      HID_LOGICAL_MIN   ( 0                                                      ),\
+      HID_LOGICAL_MAX_N ( 2147483647, 3                                          ),\
+      HID_REPORT_SIZE   ( 32                                                     ),\
+      HID_REPORT_COUNT  ( 5                                                      ),\
+      HID_FEATURE       ( HID_CONSTANT | HID_VARIABLE | HID_ABSOLUTE             ),\
+    HID_COLLECTION_END ,\
+    /* Lamp Attributes Request Report */ \
+    HID_REPORT_ID       ( report_id + 1                                     ) \
+    HID_USAGE           ( HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_REQUEST_REPORT ),\
+    HID_COLLECTION      ( HID_COLLECTION_LOGICAL                            ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_ID             ),\
+      HID_LOGICAL_MIN   ( 0                                      ),\
+      HID_LOGICAL_MAX_N ( 65535, 3                               ),\
+      HID_REPORT_SIZE   ( 16                                     ),\
+      HID_REPORT_COUNT  ( 1                                      ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+    HID_COLLECTION_END ,\
+    /* Lamp Attributes Response Report */ \
+    HID_REPORT_ID       ( report_id + 2                                      ) \
+    HID_USAGE           ( HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_RESPONSE_REPORT ),\
+    HID_COLLECTION      ( HID_COLLECTION_LOGICAL                             ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_ID                        ),\
+      HID_LOGICAL_MIN   ( 0                                                 ),\
+      HID_LOGICAL_MAX_N ( 65535, 3                                          ),\
+      HID_REPORT_SIZE   ( 16                                                ),\
+      HID_REPORT_COUNT  ( 1                                                 ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE            ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_POSITION_X_IN_MICROMETERS      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_POSITION_Y_IN_MICROMETERS      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_POSITION_Z_IN_MICROMETERS      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_UPDATE_LATENCY_IN_MICROSECONDS ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_PURPOSES                  ),\
+      HID_LOGICAL_MIN   ( 0                                                 ),\
+      HID_LOGICAL_MAX_N ( 2147483647, 3                                     ),\
+      HID_REPORT_SIZE   ( 32                                                ),\
+      HID_REPORT_COUNT  ( 5                                                 ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE            ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_LEVEL_COUNT                ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_LEVEL_COUNT              ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_LEVEL_COUNT               ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_LEVEL_COUNT          ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_IS_PROGRAMMABLE                ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INPUT_BINDING                  ),\
+      HID_LOGICAL_MIN   ( 0                                                 ),\
+      HID_LOGICAL_MAX_N ( 255, 2                                            ),\
+      HID_REPORT_SIZE   ( 8                                                 ),\
+      HID_REPORT_COUNT  ( 6                                                 ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE            ),\
+    HID_COLLECTION_END ,\
+    /* Lamp Multi-Update Report */ \
+    HID_REPORT_ID       ( report_id + 3                               ) \
+    HID_USAGE           ( HID_USAGE_LIGHTING_LAMP_MULTI_UPDATE_REPORT ),\
+    HID_COLLECTION      ( HID_COLLECTION_LOGICAL                      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_COUNT               ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_UPDATE_FLAGS        ),\
+      HID_LOGICAL_MIN   ( 0                                           ),\
+      HID_LOGICAL_MAX   ( 8                                           ),\
+      HID_REPORT_SIZE   ( 8                                           ),\
+      HID_REPORT_COUNT  ( 2                                           ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_ID                  ),\
+      HID_LOGICAL_MIN   ( 0                                           ),\
+      HID_LOGICAL_MAX_N ( 65535, 3                                    ),\
+      HID_REPORT_SIZE   ( 16                                          ),\
+      HID_REPORT_COUNT  ( 8                                           ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL       ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL       ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL       ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL       ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL       ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL       ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL       ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL       ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+      HID_LOGICAL_MIN   ( 0                                           ),\
+      HID_LOGICAL_MAX_N ( 255, 2                                      ),\
+      HID_REPORT_SIZE   ( 8                                           ),\
+      HID_REPORT_COUNT  ( 32                                          ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE      ),\
+    HID_COLLECTION_END ,\
+    /* Lamp Range Update Report */ \
+    HID_REPORT_ID       ( report_id + 4 ) \
+    HID_USAGE           ( HID_USAGE_LIGHTING_LAMP_RANGE_UPDATE_REPORT ),\
+    HID_COLLECTION      ( HID_COLLECTION_LOGICAL                      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_UPDATE_FLAGS        ),\
+      HID_LOGICAL_MIN   ( 0                                           ),\
+      HID_LOGICAL_MAX   ( 8                                           ),\
+      HID_REPORT_SIZE   ( 8                                           ),\
+      HID_REPORT_COUNT  ( 1                                           ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_ID_START            ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_LAMP_ID_END              ),\
+      HID_LOGICAL_MIN   ( 0                                           ),\
+      HID_LOGICAL_MAX_N ( 65535, 3                                    ),\
+      HID_REPORT_SIZE   ( 16                                          ),\
+      HID_REPORT_COUNT  ( 2                                           ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL       ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL     ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL      ),\
+      HID_USAGE         ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+      HID_LOGICAL_MIN   ( 0                                           ),\
+      HID_LOGICAL_MAX_N ( 255, 2                                      ),\
+      HID_REPORT_SIZE   ( 8                                           ),\
+      HID_REPORT_COUNT  ( 4                                           ),\
+      HID_FEATURE       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE      ),\
+    HID_COLLECTION_END ,\
+    /* Lamp Array Control Report */ \
+    HID_REPORT_ID      ( report_id + 5                                ) \
+    HID_USAGE          ( HID_USAGE_LIGHTING_LAMP_ARRAY_CONTROL_REPORT ),\
+    HID_COLLECTION     ( HID_COLLECTION_LOGICAL                       ),\
+      HID_USAGE        ( HID_USAGE_LIGHTING_AUTONOMOUS_MODE     ),\
+      HID_LOGICAL_MIN  ( 0                                      ),\
+      HID_LOGICAL_MAX  ( 1                                      ),\
+      HID_REPORT_SIZE  ( 8                                      ),\
+      HID_REPORT_COUNT ( 1                                      ),\
+      HID_FEATURE      ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+    HID_COLLECTION_END ,\
+  HID_COLLECTION_END \
+
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     hidd_init            (void);
+bool     hidd_deinit          (void);
 void     hidd_reset           (uint8_t rhport);
 uint16_t hidd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
@@ -390,4 +670,4 @@ bool     hidd_xfer_cb         (uint8_t rhport, uint8_t ep_addr, xfer_result_t ev
  }
 #endif
 
-#endif /* _TUSB_HID_DEVICE_H_ */
+#endif
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index ca745464c..a3cc7d6d7 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -29,362 +29,501 @@
 #if (CFG_TUH_ENABLED && CFG_TUH_HID)
 
 #include "host/usbh.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 
 #include "hid_host.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUH_HID_LOG_LEVEL
+  #define CFG_TUH_HID_LOG_LEVEL   CFG_TUH_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_HID_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-
-typedef struct
-{
+typedef struct {
+  uint8_t daddr;
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t ep_out;
 
+  bool mounted;           // Enumeration is complete
   uint8_t itf_protocol;   // None, Keyboard, Mouse
   uint8_t protocol_mode;  // Boot (0) or Report protocol (1)
 
-  uint8_t  report_desc_type;
+  uint8_t report_desc_type;
   uint16_t report_desc_len;
 
   uint16_t epin_size;
   uint16_t epout_size;
-
-  uint8_t epin_buf[CFG_TUH_HID_EPIN_BUFSIZE];
-  uint8_t epout_buf[CFG_TUH_HID_EPOUT_BUFSIZE];
 } hidh_interface_t;
 
-typedef struct
-{
-  uint8_t inst_count;
-  hidh_interface_t instances[CFG_TUH_HID];
-} hidh_device_t;
+typedef struct {
+  TUH_EPBUF_DEF(epin, CFG_TUH_HID_EPIN_BUFSIZE);
+  TUH_EPBUF_DEF(epout, CFG_TUH_HID_EPOUT_BUFSIZE);
+} hidh_epbuf_t;
 
-static hidh_device_t _hidh_dev[CFG_TUH_DEVICE_MAX];
+static hidh_interface_t _hidh_itf[CFG_TUH_HID];
+CFG_TUH_MEM_SECTION static hidh_epbuf_t _hidh_epbuf[CFG_TUH_HID];
 
-//------------- Internal prototypes -------------//
+static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT;
 
-// Get HID device & interface
-TU_ATTR_ALWAYS_INLINE static inline hidh_device_t* get_dev(uint8_t dev_addr);
-TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_instance(uint8_t dev_addr, uint8_t instance);
-static uint8_t get_instance_id_by_itfnum(uint8_t dev_addr, uint8_t itf);
-static uint8_t get_instance_id_by_epaddr(uint8_t dev_addr, uint8_t ep_addr);
+//--------------------------------------------------------------------+
+// Helper
+//--------------------------------------------------------------------+
+TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_hid_itf(uint8_t daddr, uint8_t idx) {
+  TU_ASSERT(daddr > 0 && idx < CFG_TUH_HID, NULL);
+  hidh_interface_t* p_hid = &_hidh_itf[idx];
+  return (p_hid->daddr == daddr) ? p_hid : NULL;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline hidh_epbuf_t* get_hid_epbuf(uint8_t idx) {
+  return &_hidh_epbuf[idx];
+}
+
+// Get instance ID by endpoint address
+static uint8_t get_idx_by_epaddr(uint8_t daddr, uint8_t ep_addr) {
+  for (uint8_t idx = 0; idx < CFG_TUH_HID; idx++) {
+    hidh_interface_t const* p_hid = &_hidh_itf[idx];
+    if (p_hid->daddr == daddr &&
+        (p_hid->ep_in == ep_addr || p_hid->ep_out == ep_addr)) {
+      return idx;
+    }
+  }
+  return TUSB_INDEX_INVALID_8;
+}
+
+static hidh_interface_t* find_new_itf(void) {
+  for (uint8_t i = 0; i < CFG_TUH_HID; i++) {
+    if (_hidh_itf[i].daddr == 0) return &_hidh_itf[i];
+  }
+  return NULL;
+}
 
 //--------------------------------------------------------------------+
 // Interface API
 //--------------------------------------------------------------------+
-
-uint8_t tuh_hid_instance_count(uint8_t dev_addr)
-{
-  return get_dev(dev_addr)->inst_count;
+uint8_t tuh_hid_itf_get_count(uint8_t daddr) {
+  uint8_t count = 0;
+  for (uint8_t i = 0; i < CFG_TUH_HID; i++) {
+    if (_hidh_itf[i].daddr == daddr) count++;
+  }
+  return count;
 }
 
-bool tuh_hid_mounted(uint8_t dev_addr, uint8_t instance)
-{
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  return (hid_itf->ep_in != 0) || (hid_itf->ep_out != 0);
+uint8_t tuh_hid_itf_get_total_count(void) {
+  uint8_t count = 0;
+  for (uint8_t i = 0; i < CFG_TUH_HID; i++) {
+    if (_hidh_itf[i].daddr != 0) count++;
+  }
+  return count;
 }
 
-uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance)
-{
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  return hid_itf->itf_protocol;
+bool tuh_hid_mounted(uint8_t daddr, uint8_t idx) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
+  return p_hid->mounted;
+}
+
+bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid && info);
+
+  info->daddr = daddr;
+
+  // re-construct descriptor
+  tusb_desc_interface_t* desc = &info->desc;
+  desc->bLength = sizeof(tusb_desc_interface_t);
+  desc->bDescriptorType = TUSB_DESC_INTERFACE;
+
+  desc->bInterfaceNumber = p_hid->itf_num;
+  desc->bAlternateSetting = 0;
+  desc->bNumEndpoints = (uint8_t) ((p_hid->ep_in ? 1u : 0u) + (p_hid->ep_out ? 1u : 0u));
+  desc->bInterfaceClass = TUSB_CLASS_HID;
+  desc->bInterfaceSubClass = (p_hid->itf_protocol ? HID_SUBCLASS_BOOT : HID_SUBCLASS_NONE);
+  desc->bInterfaceProtocol = p_hid->itf_protocol;
+  desc->iInterface = 0; // not used yet
+
+  return true;
+}
+
+uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num) {
+  for (uint8_t idx = 0; idx < CFG_TUH_HID; idx++) {
+    hidh_interface_t const* p_hid = &_hidh_itf[idx];
+    if (p_hid->daddr == daddr && p_hid->itf_num == itf_num) return idx;
+  }
+
+  return TUSB_INDEX_INVALID_8;
+}
+
+uint8_t tuh_hid_interface_protocol(uint8_t daddr, uint8_t idx) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  return p_hid ? p_hid->itf_protocol : 0;
 }
 
 //--------------------------------------------------------------------+
 // Control Endpoint API
 //--------------------------------------------------------------------+
-
-uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
-{
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  return hid_itf->protocol_mode;
+uint8_t tuh_hid_get_protocol(uint8_t daddr, uint8_t idx) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  return p_hid ? p_hid->protocol_mode : 0;
 }
 
-static void set_protocol_complete(tuh_xfer_t* xfer)
-{
-  uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t const daddr       = xfer->daddr;
-  uint8_t const instance    = get_instance_id_by_itfnum(daddr, itf_num);
-  hidh_interface_t* hid_itf = get_instance(daddr, instance);
+static void set_protocol_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const daddr = xfer->daddr;
+  uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num);
 
-  if (XFER_RESULT_SUCCESS == xfer->result)
-  {
-    hid_itf->protocol_mode = (uint8_t) tu_le16toh(xfer->setup->wValue);
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid,);
+
+  if (XFER_RESULT_SUCCESS == xfer->result) {
+    p_hid->protocol_mode = (uint8_t) tu_le16toh(xfer->setup->wValue);
   }
 
-  if (tuh_hid_set_protocol_complete_cb)
-  {
-    tuh_hid_set_protocol_complete_cb(daddr, instance, hid_itf->protocol_mode);
+  if (tuh_hid_set_protocol_complete_cb) {
+    tuh_hid_set_protocol_complete_cb(daddr, idx, p_hid->protocol_mode);
   }
 }
 
-
-static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  TU_LOG2("HID Set Protocol = %d\r\n", protocol);
-
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
-    .wValue   = protocol,
-    .wIndex   = itf_num,
-    .wLength  = 0
-  };
-
-  tuh_xfer_t xfer =
-  {
-    .daddr       = dev_addr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
-  };
-
-  TU_ASSERT( tuh_control_xfer(&xfer) );
-  return true;
+void tuh_hid_set_default_protocol(uint8_t protocol) {
+  _hidh_default_protocol = protocol;
 }
 
-bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
-{
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  TU_VERIFY(hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE);
+static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_DRV("HID Set Protocol = %d\r\n", protocol);
 
-  return _hidh_set_protocol(dev_addr, hid_itf->itf_num, protocol, set_protocol_complete, 0);
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
+      .wValue   = protocol,
+      .wIndex   = itf_num,
+      .wLength  = 0
+  };
+
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
+  };
+
+  return tuh_control_xfer(&xfer);
 }
 
-static void set_report_complete(tuh_xfer_t* xfer)
-{
-  TU_LOG2("HID Set Report complete\r\n");
+bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid && p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE);
 
-  if (tuh_hid_set_report_complete_cb)
-  {
-    uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-    uint8_t const instance    = get_instance_id_by_itfnum(xfer->daddr, itf_num);
+  return _hidh_set_protocol(daddr, p_hid->itf_num, protocol, set_protocol_complete, 0);
+}
+
+static void get_report_complete(tuh_xfer_t* xfer) {
+  TU_LOG_DRV("HID Get Report complete\r\n");
+
+  if (tuh_hid_get_report_complete_cb) {
+    uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+    uint8_t const idx = tuh_hid_itf_get_index(xfer->daddr, itf_num);
 
     uint8_t const report_type = tu_u16_high(xfer->setup->wValue);
-    uint8_t const report_id   = tu_u16_low(xfer->setup->wValue);
+    uint8_t const report_id = tu_u16_low(xfer->setup->wValue);
 
-    tuh_hid_set_report_complete_cb(xfer->daddr, instance, report_id, report_type,
+    tuh_hid_get_report_complete_cb(xfer->daddr, idx, report_id, report_type,
                                    (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
   }
 }
 
-bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, void* report, uint16_t len)
-{
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  TU_LOG2("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
+bool tuh_hid_get_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
+  TU_LOG_DRV("HID Get Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
 
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = HID_REQ_CONTROL_SET_REPORT,
-    .wValue   = tu_u16(report_type, report_id),
-    .wIndex   = hid_itf->itf_num,
-    .wLength  = len
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_IN
+      },
+      .bRequest = HID_REQ_CONTROL_GET_REPORT,
+      .wValue   = tu_htole16(tu_u16(report_type, report_id)),
+      .wIndex   = tu_htole16((uint16_t) p_hid->itf_num),
+      .wLength  = len
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = dev_addr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = report,
-    .complete_cb = set_report_complete,
-    .user_data   = 0
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = report,
+      .complete_cb = get_report_complete,
+      .user_data   = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(&xfer) );
-  return true;
+  return tuh_control_xfer(&xfer);
 }
 
-static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static void set_report_complete(tuh_xfer_t* xfer) {
+  TU_LOG_DRV("HID Set Report complete\r\n");
+
+  if (tuh_hid_set_report_complete_cb) {
+    uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+    uint8_t const idx = tuh_hid_itf_get_index(xfer->daddr, itf_num);
+
+    uint8_t const report_type = tu_u16_high(xfer->setup->wValue);
+    uint8_t const report_id = tu_u16_low(xfer->setup->wValue);
+
+    tuh_hid_set_report_complete_cb(xfer->daddr, idx, report_id, report_type,
+                                   (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
+  }
+}
+
+bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
+  TU_LOG_DRV("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
+
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_REPORT,
+      .wValue   = tu_htole16(tu_u16(report_type, report_id)),
+      .wIndex   = tu_htole16((uint16_t) p_hid->itf_num),
+      .wLength  = len
+  };
+
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = report,
+      .complete_cb = set_report_complete,
+      .user_data   = 0
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
+static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate,
+                           tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   // SET IDLE request, device can stall if not support this request
-  TU_LOG2("HID Set Idle \r\n");
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = HID_REQ_CONTROL_SET_IDLE,
-    .wValue   = idle_rate,
-    .wIndex   = itf_num,
-    .wLength  = 0
+  TU_LOG_DRV("HID Set Idle \r\n");
+
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_IDLE,
+      .wValue   = tu_htole16(idle_rate),
+      .wIndex   = tu_htole16((uint16_t) itf_num),
+      .wLength  = 0
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = dev_addr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
   };
 
-  TU_ASSERT( tuh_control_xfer(&xfer) );
-
-  return true;
+  return tuh_control_xfer(&xfer);
 }
 
 //--------------------------------------------------------------------+
 // Interrupt Endpoint API
 //--------------------------------------------------------------------+
 
-bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance)
-{
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+// Check if HID interface is ready to receive report
+bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx) {
+  hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx);
+  TU_VERIFY(p_hid);
+  return !usbh_edpt_busy(dev_addr, p_hid->ep_in);
+}
+
+bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
+  hidh_epbuf_t* epbuf = get_hid_epbuf(idx);
 
   // claim endpoint
-  TU_VERIFY( usbh_edpt_claim(dev_addr, hid_itf->ep_in) );
+  TU_VERIFY(usbh_edpt_claim(daddr, p_hid->ep_in));
 
-  if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_in, hid_itf->epin_buf, hid_itf->epin_size) )
-  {
-    usbh_edpt_claim(dev_addr, hid_itf->ep_in);
+  if (!usbh_edpt_xfer(daddr, p_hid->ep_in, epbuf->epin, p_hid->epin_size)) {
+    usbh_edpt_release(daddr, p_hid->ep_in);
+    return false;
+  }
+
+  return true;
+}
+bool tuh_hid_receive_abort(uint8_t dev_addr, uint8_t idx) {
+  hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx);
+  TU_VERIFY(p_hid);
+  return tuh_edpt_abort_xfer(dev_addr, p_hid->ep_in);
+}
+
+bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx) {
+  hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx);
+  TU_VERIFY(p_hid);
+  return !usbh_edpt_busy(dev_addr, p_hid->ep_out);
+}
+
+bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len) {
+  TU_LOG_DRV("HID Send Report %d\r\n", report_id);
+
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
+  hidh_epbuf_t* epbuf = get_hid_epbuf(idx);
+
+  if (p_hid->ep_out == 0) {
+    // This HID does not have an out endpoint (other than control)
+    return false;
+  } else if (len > CFG_TUH_HID_EPOUT_BUFSIZE ||
+             (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1))) {
+    // ep_out buffer is not large enough to hold contents
+    return false;
+  }
+
+  // claim endpoint
+  TU_VERIFY(usbh_edpt_claim(daddr, p_hid->ep_out));
+
+  if (report_id == 0) {
+    // No report ID in transmission
+    memcpy(&epbuf->epout[0], report, len);
+  } else {
+    epbuf->epout[0] = report_id;
+    memcpy(&epbuf->epout[1], report, len);
+    ++len; // 1 more byte for report_id
+  }
+
+  TU_LOG3_MEM(epbuf->epout, len, 2);
+
+  if (!usbh_edpt_xfer(daddr, p_hid->ep_out, epbuf->epout, len)) {
+    usbh_edpt_release(daddr, p_hid->ep_out);
     return false;
   }
 
   return true;
 }
 
-//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t instance)
-//{
-//  TU_VERIFY(tuh_n_hid_n_mounted(dev_addr, instance));
-//
-//  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-//  return !usbh_edpt_busy(dev_addr, hid_itf->ep_in);
-//}
-
-//void tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len);
-
 //--------------------------------------------------------------------+
 // USBH API
 //--------------------------------------------------------------------+
-void hidh_init(void)
-{
-  tu_memclr(_hidh_dev, sizeof(_hidh_dev));
+bool hidh_init(void) {
+  TU_LOG_DRV("sizeof(hidh_interface_t) = %u\r\n", sizeof(hidh_interface_t));
+  tu_memclr(_hidh_itf, sizeof(_hidh_itf));
+  return true;
 }
 
-bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool hidh_deinit(void) {
+  return true;
+}
+
+bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) result;
 
   uint8_t const dir = tu_edpt_dir(ep_addr);
-  uint8_t const instance = get_instance_id_by_epaddr(dev_addr, ep_addr);
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  uint8_t const idx = get_idx_by_epaddr(daddr, ep_addr);
 
-  if ( dir == TUSB_DIR_IN )
-  {
-    TU_LOG2("  Get Report callback (%u, %u)\r\n", dev_addr, instance);
-    TU_LOG3_MEM(hid_itf->epin_buf, xferred_bytes, 2);
-    tuh_hid_report_received_cb(dev_addr, instance, hid_itf->epin_buf, (uint16_t) xferred_bytes);
-  }else
-  {
-    if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(dev_addr, instance, hid_itf->epout_buf, (uint16_t) xferred_bytes);
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
+  hidh_epbuf_t* epbuf = get_hid_epbuf(idx);
+
+  if (dir == TUSB_DIR_IN) {
+    TU_LOG_DRV("  Get Report callback (%u, %u)\r\n", daddr, idx);
+    TU_LOG3_MEM(epbuf->epin, xferred_bytes, 2);
+    tuh_hid_report_received_cb(daddr, idx, epbuf->epin, (uint16_t) xferred_bytes);
+  } else {
+    if (tuh_hid_report_sent_cb) {
+      tuh_hid_report_sent_cb(daddr, idx, epbuf->epout, (uint16_t) xferred_bytes);
+    }
   }
 
   return true;
 }
 
-void hidh_close(uint8_t dev_addr)
-{
-  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
-
-  hidh_device_t* hid_dev = get_dev(dev_addr);
-
-  if (tuh_hid_umount_cb)
-  {
-    for (uint8_t inst = 0; inst < hid_dev->inst_count; inst++ ) tuh_hid_umount_cb(dev_addr, inst);
+void hidh_close(uint8_t daddr) {
+  for (uint8_t i = 0; i < CFG_TUH_HID; i++) {
+    hidh_interface_t* p_hid = &_hidh_itf[i];
+    if (p_hid->daddr == daddr) {
+      TU_LOG_DRV("  HIDh close addr = %u index = %u\r\n", daddr, i);
+      if (tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i);
+      tu_memclr(p_hid, sizeof(hidh_interface_t));
+    }
   }
-
-  tu_memclr(hid_dev, sizeof(hidh_device_t));
 }
 
 //--------------------------------------------------------------------+
 // Enumeration
 //--------------------------------------------------------------------+
 
-bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
-{
+bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const* desc_itf, uint16_t max_len) {
   (void) rhport;
   (void) max_len;
 
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass);
-
-  TU_LOG2("[%u] HID opening Interface %u\r\n", dev_addr, desc_itf->bInterfaceNumber);
+  TU_LOG_DRV("[%u] HID opening Interface %u\r\n", daddr, desc_itf->bInterfaceNumber);
 
   // len = interface + hid + n*endpoints
   uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
                                        desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(max_len >= drv_len);
-
-  uint8_t const *p_desc = (uint8_t const *) desc_itf;
+  uint8_t const* p_desc = (uint8_t const*) desc_itf;
 
   //------------- HID descriptor -------------//
   p_desc = tu_desc_next(p_desc);
-  tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc;
+  tusb_hid_descriptor_hid_t const* desc_hid = (tusb_hid_descriptor_hid_t const*) p_desc;
   TU_ASSERT(HID_DESC_TYPE_HID == desc_hid->bDescriptorType);
 
-  // not enough interface, try to increase CFG_TUH_HID
-  // TODO multiple devices
-  hidh_device_t* hid_dev = get_dev(dev_addr);
-  TU_ASSERT(hid_dev->inst_count < CFG_TUH_HID, 0);
-
-  hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count);  
+  hidh_interface_t* p_hid = find_new_itf();
+  TU_ASSERT(p_hid); // not enough interface, try to increase CFG_TUH_HID
+  p_hid->daddr = daddr;
 
   //------------- Endpoint Descriptors -------------//
   p_desc = tu_desc_next(p_desc);
-  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc;
 
-  for(int i = 0; i < desc_itf->bNumEndpoints; i++)
-  {
+  for (int i = 0; i < desc_itf->bNumEndpoints; i++) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
-    TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) );
+    TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
 
-    if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
-    {
-      hid_itf->ep_in     = desc_ep->bEndpointAddress;
-      hid_itf->epin_size = tu_edpt_packet_size(desc_ep);
-    }
-    else
-    {
-      hid_itf->ep_out     = desc_ep->bEndpointAddress;
-      hid_itf->epout_size = tu_edpt_packet_size(desc_ep);
+    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+      p_hid->ep_in = desc_ep->bEndpointAddress;
+      p_hid->epin_size = tu_edpt_packet_size(desc_ep);
+    } else {
+      p_hid->ep_out = desc_ep->bEndpointAddress;
+      p_hid->epout_size = tu_edpt_packet_size(desc_ep);
     }
 
     p_desc = tu_desc_next(p_desc);
-    desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+    desc_ep = (tusb_desc_endpoint_t const*) p_desc;
   }
 
-  hid_dev->inst_count++;
-
-  hid_itf->itf_num   = desc_itf->bInterfaceNumber;
+  p_hid->itf_num = desc_itf->bInterfaceNumber;
 
   // Assume bNumDescriptors = 1
-  hid_itf->report_desc_type = desc_hid->bReportType;
-  hid_itf->report_desc_len  = tu_unaligned_read16(&desc_hid->wReportLength);
+  p_hid->report_desc_type = desc_hid->bReportType;
+  p_hid->report_desc_len = tu_unaligned_read16(&desc_hid->wReportLength);
 
   // Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config
-  hid_itf->protocol_mode = HID_PROTOCOL_BOOT;
-  if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass ) hid_itf->itf_protocol = desc_itf->bInterfaceProtocol;
+  p_hid->protocol_mode = _hidh_default_protocol;
+  if (HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass) {
+    p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
+  }
 
   return true;
 }
@@ -400,18 +539,17 @@ enum {
   CONFIG_COMPLETE
 };
 
-static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
+static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len);
 static void process_set_config(tuh_xfer_t* xfer);
 
-bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
-{
+bool hidh_set_config(uint8_t daddr, uint8_t itf_num) {
   tusb_control_request_t request;
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
   tuh_xfer_t xfer;
-  xfer.daddr     = dev_addr;
-  xfer.result    = XFER_RESULT_SUCCESS;
-  xfer.setup     = &request;
+  xfer.daddr = daddr;
+  xfer.result = XFER_RESULT_SUCCESS;
+  xfer.setup = &request;
   xfer.user_data = CONFG_SET_IDLE;
 
   // fake request to kick-off the set config process
@@ -420,94 +558,93 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static void process_set_config(tuh_xfer_t* xfer)
-{
-  // Stall is a valid response for SET_IDLE, therefore we could ignore its result
-  if ( xfer->setup->bRequest != HID_REQ_CONTROL_SET_IDLE )
-  {
-    TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
+static void process_set_config(tuh_xfer_t* xfer) {
+  // Stall is a valid response for SET_IDLE, sometime SET_PROTOCOL as well
+  // therefore we could ignore its result
+  if (!(xfer->setup->bRequest == HID_REQ_CONTROL_SET_IDLE ||
+        xfer->setup->bRequest == HID_REQ_CONTROL_SET_PROTOCOL)) {
+    TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS,);
   }
 
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t const daddr   = xfer->daddr;
+  uint8_t const daddr = xfer->daddr;
 
-  uint8_t const instance    = get_instance_id_by_itfnum(daddr, itf_num);
-  hidh_interface_t* hid_itf = get_instance(daddr, instance);
+  uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num);
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid,);
 
-  switch(state)
-  {
-    case CONFG_SET_IDLE:
-    {
+  switch (state) {
+    case CONFG_SET_IDLE: {
       // Idle rate = 0 mean only report when there is changes
       const uint16_t idle_rate = 0;
-      const uintptr_t next_state = (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC;
+      const uintptr_t next_state = (p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE)
+                                   ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC;
       _hidh_set_idle(daddr, itf_num, idle_rate, process_set_config, next_state);
+      break;
     }
-    break;
 
     case CONFIG_SET_PROTOCOL:
-      _hidh_set_protocol(daddr, hid_itf->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC);
-    break;
+      _hidh_set_protocol(daddr, p_hid->itf_num, _hidh_default_protocol, process_set_config, CONFIG_GET_REPORT_DESC);
+      break;
 
     case CONFIG_GET_REPORT_DESC:
       // Get Report Descriptor if possible
       // using usbh enumeration buffer since report descriptor can be very long
-      if( hid_itf->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE )
-      {
-        TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", hid_itf->report_desc_len);
+      if (p_hid->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE) {
+        TU_LOG_DRV("HID Skip Report Descriptor since it is too large %u bytes\r\n", p_hid->report_desc_len);
 
         // Driver is mounted without report descriptor
-        config_driver_mount_complete(daddr, instance, NULL, 0);
-      }else
-      {
-        tuh_descriptor_get_hid_report(daddr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, process_set_config, CONFIG_COMPLETE);
+        config_driver_mount_complete(daddr, idx, NULL, 0);
+      } else {
+        tuh_descriptor_get_hid_report(daddr, itf_num, p_hid->report_desc_type, 0,
+                                      usbh_get_enum_buf(), p_hid->report_desc_len,
+                                      process_set_config, CONFIG_COMPLETE);
       }
       break;
 
-    case CONFIG_COMPLETE:
-    {
+    case CONFIG_COMPLETE: {
       uint8_t const* desc_report = usbh_get_enum_buf();
-      uint16_t const desc_len    = tu_le16toh(xfer->setup->wLength);
+      uint16_t const desc_len = tu_le16toh(xfer->setup->wLength);
 
-      config_driver_mount_complete(daddr, instance, desc_report, desc_len);
+      config_driver_mount_complete(daddr, idx, desc_report, desc_len);
+      break;
     }
-    break;
 
-    default: break;
+    default:
+      break;
   }
 }
 
-static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
-{
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid,);
+  p_hid->mounted = true;
 
   // enumeration is complete
-  tuh_hid_mount_cb(dev_addr, instance, desc_report, desc_len);
+  if (tuh_hid_mount_cb) tuh_hid_mount_cb(daddr, idx, desc_report, desc_len);
 
   // notify usbh that driver enumeration is complete
-  usbh_driver_set_config_complete(dev_addr, hid_itf->itf_num);
+  usbh_driver_set_config_complete(daddr, p_hid->itf_num);
 }
 
 //--------------------------------------------------------------------+
 // Report Descriptor Parser
 //--------------------------------------------------------------------+
 
-uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len)
-{
+uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, uint8_t arr_count,
+                                        uint8_t const* desc_report, uint16_t desc_len) {
   // Report Item 6.2.2.2 USB HID 1.11
-  union TU_ATTR_PACKED
-  {
+  union TU_ATTR_PACKED {
     uint8_t byte;
-    struct TU_ATTR_PACKED
-    {
-        uint8_t size : 2;
-        uint8_t type : 2;
-        uint8_t tag  : 4;
+    struct TU_ATTR_PACKED {
+      uint8_t size : 2;
+      uint8_t type : 2;
+      uint8_t tag : 4;
     };
   } header;
 
-  tu_memclr(report_info_arr, arr_count*sizeof(tuh_hid_report_info_t));
+  tu_memclr(report_info_arr, arr_count * sizeof(tuh_hid_report_info_t));
 
   uint8_t report_num = 0;
   tuh_hid_report_info_t* info = report_info_arr;
@@ -517,160 +654,111 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr,
 //  uint8_t ri_report_size = 0;
 
   uint8_t ri_collection_depth = 0;
-
-  while(desc_len && report_num < arr_count)
-  {
+  while (desc_len && report_num < arr_count) {
     header.byte = *desc_report++;
     desc_len--;
 
-    uint8_t const tag  = header.tag;
+    uint8_t const tag = header.tag;
     uint8_t const type = header.type;
     uint8_t const size = header.size;
 
     uint8_t const data8 = desc_report[0];
 
     TU_LOG(3, "tag = %d, type = %d, size = %d, data = ", tag, type, size);
-    for(uint32_t i=0; i<size; i++) TU_LOG(3, "%02X ", desc_report[i]);
+    for (uint32_t i = 0; i < size; i++) {
+      TU_LOG(3, "%02X ", desc_report[i]);
+    }
     TU_LOG(3, "\r\n");
 
-    switch(type)
-    {
+    switch (type) {
       case RI_TYPE_MAIN:
-        switch (tag)
-        {
+        switch (tag) {
           case RI_MAIN_INPUT: break;
           case RI_MAIN_OUTPUT: break;
           case RI_MAIN_FEATURE: break;
-
           case RI_MAIN_COLLECTION:
             ri_collection_depth++;
-          break;
+            break;
 
           case RI_MAIN_COLLECTION_END:
             ri_collection_depth--;
-            if (ri_collection_depth == 0)
-            {
+            if (ri_collection_depth == 0) {
               info++;
               report_num++;
             }
-          break;
+            break;
 
-          default: break;
+          default:break;
         }
-      break;
+        break;
 
       case RI_TYPE_GLOBAL:
-        switch(tag)
-        {
+        switch (tag) {
           case RI_GLOBAL_USAGE_PAGE:
             // only take in account the "usage page" before REPORT ID
-            if ( ri_collection_depth == 0 ) memcpy(&info->usage_page, desc_report, size);
-          break;
+            if (ri_collection_depth == 0) memcpy(&info->usage_page, desc_report, size);
+            break;
 
-          case RI_GLOBAL_LOGICAL_MIN   : break;
-          case RI_GLOBAL_LOGICAL_MAX   : break;
-          case RI_GLOBAL_PHYSICAL_MIN  : break;
-          case RI_GLOBAL_PHYSICAL_MAX  : break;
+          case RI_GLOBAL_LOGICAL_MIN: break;
+          case RI_GLOBAL_LOGICAL_MAX: break;
+          case RI_GLOBAL_PHYSICAL_MIN: break;
+          case RI_GLOBAL_PHYSICAL_MAX: break;
 
           case RI_GLOBAL_REPORT_ID:
             info->report_id = data8;
-          break;
+            break;
 
           case RI_GLOBAL_REPORT_SIZE:
 //            ri_report_size = data8;
-          break;
+            break;
 
           case RI_GLOBAL_REPORT_COUNT:
 //            ri_report_count = data8;
-          break;
+            break;
 
-          case RI_GLOBAL_UNIT_EXPONENT : break;
-          case RI_GLOBAL_UNIT          : break;
-          case RI_GLOBAL_PUSH          : break;
-          case RI_GLOBAL_POP           : break;
+          case RI_GLOBAL_UNIT_EXPONENT: break;
+          case RI_GLOBAL_UNIT: break;
+          case RI_GLOBAL_PUSH: break;
+          case RI_GLOBAL_POP: break;
 
           default: break;
         }
-      break;
+        break;
 
       case RI_TYPE_LOCAL:
-        switch(tag)
-        {
+        switch (tag) {
           case RI_LOCAL_USAGE:
             // only take in account the "usage" before starting REPORT ID
-            if ( ri_collection_depth == 0 ) info->usage = data8;
-          break;
+            if (ri_collection_depth == 0) info->usage = data8;
+            break;
 
-          case RI_LOCAL_USAGE_MIN        : break;
-          case RI_LOCAL_USAGE_MAX        : break;
-          case RI_LOCAL_DESIGNATOR_INDEX : break;
-          case RI_LOCAL_DESIGNATOR_MIN   : break;
-          case RI_LOCAL_DESIGNATOR_MAX   : break;
-          case RI_LOCAL_STRING_INDEX     : break;
-          case RI_LOCAL_STRING_MIN       : break;
-          case RI_LOCAL_STRING_MAX       : break;
-          case RI_LOCAL_DELIMITER        : break;
+          case RI_LOCAL_USAGE_MIN: break;
+          case RI_LOCAL_USAGE_MAX: break;
+          case RI_LOCAL_DESIGNATOR_INDEX: break;
+          case RI_LOCAL_DESIGNATOR_MIN: break;
+          case RI_LOCAL_DESIGNATOR_MAX: break;
+          case RI_LOCAL_STRING_INDEX: break;
+          case RI_LOCAL_STRING_MIN: break;
+          case RI_LOCAL_STRING_MAX: break;
+          case RI_LOCAL_DELIMITER: break;
           default: break;
         }
-      break;
+        break;
 
-      // error
+        // error
       default: break;
     }
 
     desc_report += size;
-    desc_len    -= size;
+    desc_len -= size;
   }
 
-  for ( uint8_t i = 0; i < report_num; i++ )
-  {
-    info = report_info_arr+i;
-    TU_LOG2("%u: id = %u, usage_page = %u, usage = %u\r\n", i, info->report_id, info->usage_page, info->usage);
+  for (uint8_t i = 0; i < report_num; i++) {
+    info = report_info_arr + i;
+    TU_LOG_DRV("%u: id = %u, usage_page = %u, usage = %u\r\n", i, info->report_id, info->usage_page, info->usage);
   }
 
   return report_num;
 }
 
-//--------------------------------------------------------------------+
-// Helper
-//--------------------------------------------------------------------+
-
-// Get Device by address
-TU_ATTR_ALWAYS_INLINE static inline hidh_device_t* get_dev(uint8_t dev_addr)
-{
-  return &_hidh_dev[dev_addr-1];
-}
-
-// Get Interface by instance number
-TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_instance(uint8_t dev_addr, uint8_t instance)
-{
-  return &_hidh_dev[dev_addr-1].instances[instance];
-}
-
-// Get instance ID by interface number
-static uint8_t get_instance_id_by_itfnum(uint8_t dev_addr, uint8_t itf)
-{
-  for ( uint8_t inst = 0; inst < CFG_TUH_HID; inst++ )
-  {
-    hidh_interface_t *hid = get_instance(dev_addr, inst);
-
-    if ( (hid->itf_num == itf) && (hid->ep_in || hid->ep_out) ) return inst;
-  }
-
-  return 0xff;
-}
-
-// Get instance ID by endpoint address
-static uint8_t get_instance_id_by_epaddr(uint8_t dev_addr, uint8_t ep_addr)
-{
-  for ( uint8_t inst = 0; inst < CFG_TUH_HID; inst++ )
-  {
-    hidh_interface_t *hid = get_instance(dev_addr, inst);
-
-    if ( (ep_addr == hid->ep_in) || ( ep_addr == hid->ep_out) ) return inst;
-  }
-
-  return 0xff;
-}
-
 #endif
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index fe09b03b2..9681c704b 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -30,7 +30,7 @@
 #include "hid.h"
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 //--------------------------------------------------------------------+
@@ -47,10 +47,9 @@
 #endif
 
 
-typedef struct
-{
-  uint8_t  report_id;
-  uint8_t  usage;
+typedef struct {
+  uint8_t report_id;
+  uint8_t usage;
   uint16_t usage_page;
 
   // TODO still use the endpoint size for now
@@ -62,18 +61,32 @@ typedef struct
 // Interface API
 //--------------------------------------------------------------------+
 
-// Get the number of HID instances
-uint8_t tuh_hid_instance_count(uint8_t dev_addr);
+// Get the total number of mounted HID interfaces of a device
+uint8_t tuh_hid_itf_get_count(uint8_t dev_addr);
 
-// Check if HID instance is mounted
-bool tuh_hid_mounted(uint8_t dev_addr, uint8_t instance);
+// Get all mounted interfaces across devices
+uint8_t tuh_hid_itf_get_total_count(void);
+
+// backward compatible rename
+#define tuh_hid_instance_count    tuh_hid_itf_get_count
+
+// Get Interface information
+bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* itf_info);
+
+// Get Interface index from device address + interface number
+// return TUSB_INDEX_INVALID_8 (0xFF) if not found
+uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num);
 
 // Get interface supported protocol (bInterfaceProtocol) check out hid_interface_protocol_enum_t for possible values
-uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance);
+uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t idx);
+
+// Check if HID interface is mounted
+bool tuh_hid_mounted(uint8_t dev_addr, uint8_t idx);
 
 // Parse report descriptor into array of report_info struct and return number of reports.
 // For complicated report, application should write its own parser.
-uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len) TU_ATTR_UNUSED;
+TU_ATTR_UNUSED uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count,
+                                                       uint8_t const* desc_report, uint16_t desc_len);
 
 //--------------------------------------------------------------------+
 // Control Endpoint API
@@ -82,31 +95,46 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr,
 // Get current protocol: HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
 // Note: Device will be initialized in Boot protocol for simplicity.
 //       Application can use set_protocol() to switch back to Report protocol.
-uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance);
+uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t idx);
+
+// Device by default is enumerated in Boot protocol for simplicity. Application
+// can use this to modify the default protocol for next enumeration.
+void tuh_hid_set_default_protocol(uint8_t protocol);
 
 // Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
 // This function is only supported by Boot interface (tuh_n_hid_interface_protocol() != NONE)
-bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol);
+bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t idx, uint8_t protocol);
+
+// Get Report using control endpoint
+// report_type is either Input, Output or Feature, (value from hid_report_type_t)
+bool tuh_hid_get_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len);
 
 // Set Report using control endpoint
-// report_type is either Intput, Output or Feature, (value from hid_report_type_t)
-bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, void* report, uint16_t len);
+// report_type is either Input, Output or Feature, (value from hid_report_type_t)
+bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type,
+                        void* report, uint16_t len);
 
 //--------------------------------------------------------------------+
 // Interrupt Endpoint API
 //--------------------------------------------------------------------+
 
-// Check if the interface is ready to use
-//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t instance);
+// Check if HID interface is ready to receive report
+bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx);
 
 // Try to receive next report on Interrupt Endpoint. Immediately return
 // - true If succeeded, tuh_hid_report_received_cb() callback will be invoked when report is available
 // - false if failed to queue the transfer e.g endpoint is busy
-bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance);
+bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t idx);
+
+// Abort receiving report on Interrupt Endpoint
+bool tuh_hid_receive_abort(uint8_t dev_addr, uint8_t idx);
+
+// Check if HID interface is ready to send report
+bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx);
 
 // Send report using interrupt endpoint
 // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent.
-//void tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len);
+bool tuh_hid_send_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len);
 
 //--------------------------------------------------------------------+
 // Callbacks (Weak is optional)
@@ -117,33 +145,38 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance);
 // can be used to parse common/simple enough descriptor.
 // Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
 // therefore report_desc = NULL, desc_len = 0
-void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report_desc, uint16_t desc_len);
+TU_ATTR_WEAK void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report_desc, uint16_t desc_len);
 
 // Invoked when device with hid interface is un-mounted
-TU_ATTR_WEAK void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance);
+TU_ATTR_WEAK void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t idx);
 
 // Invoked when received report from device via interrupt endpoint
 // Note: if there is report ID (composite), it is 1st byte of report
-void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len);
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report, uint16_t len);
 
 // Invoked when sent report to device successfully via interrupt endpoint
-TU_ATTR_WEAK void tuh_hid_report_sent_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len);
+TU_ATTR_WEAK void tuh_hid_report_sent_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report, uint16_t len);
+
+// Invoked when Get Report to device via either control endpoint
+// len = 0 indicate there is error in the transfer e.g stalled response
+TU_ATTR_WEAK void tuh_hid_get_report_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, uint16_t len);
 
 // Invoked when Sent Report to device via either control endpoint
 // len = 0 indicate there is error in the transfer e.g stalled response
-TU_ATTR_WEAK void tuh_hid_set_report_complete_cb(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, uint16_t len);
+TU_ATTR_WEAK void tuh_hid_set_report_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, uint16_t len);
 
 // Invoked when Set Protocol request is complete
-TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t instance, uint8_t protocol);
+TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t protocol);
 
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void hidh_init       (void);
-bool hidh_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
-bool hidh_set_config (uint8_t dev_addr, uint8_t itf_num);
-bool hidh_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-void hidh_close      (uint8_t dev_addr);
+bool hidh_init(void);
+bool hidh_deinit(void);
+bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len);
+bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num);
+bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+void hidh_close(uint8_t dev_addr);
 
 #ifdef __cplusplus
 }
diff --git a/src/class/midi/midi.h b/src/class/midi/midi.h
index ea2cfec75..68a784c60 100644
--- a/src/class/midi/midi.h
+++ b/src/class/midi/midi.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -71,8 +71,8 @@ typedef enum
   MIDI_CIN_SYSEX_END_1BYTE   = 5, // SysEx ends with 1 data, or 1 byte system common message
   MIDI_CIN_SYSEX_END_2BYTE   = 6, // SysEx ends with 2 data
   MIDI_CIN_SYSEX_END_3BYTE   = 7, // SysEx ends with 3 data
-  MIDI_CIN_NOTE_ON           = 9,
   MIDI_CIN_NOTE_OFF          = 8,
+  MIDI_CIN_NOTE_ON           = 9,
   MIDI_CIN_POLY_KEYPRESS     = 10,
   MIDI_CIN_CONTROL_CHANGE    = 11,
   MIDI_CIN_PROGRAM_CHANGE    = 12,
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index c6c99db29..4ae8ea8fa 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -40,15 +40,13 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-typedef struct
-{
+typedef struct {
   uint8_t buffer[4];
   uint8_t index;
   uint8_t total;
-}midid_stream_t;
+} midid_stream_t;
 
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t ep_out;
@@ -70,36 +68,36 @@ typedef struct
   osal_mutex_def_t rx_ff_mutex;
   osal_mutex_def_t tx_ff_mutex;
   #endif
-
-  // Endpoint Transfer buffer
-  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_MIDI_EP_BUFSIZE];
-  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_MIDI_EP_BUFSIZE];
-
 } midid_interface_t;
 
 #define ITF_MEM_RESET_SIZE   offsetof(midid_interface_t, rx_ff)
 
+// Endpoint Transfer buffer
+CFG_TUD_MEM_SECTION static struct {
+  TUD_EPBUF_DEF(epin, CFG_TUD_MIDI_EP_BUFSIZE);
+  TUD_EPBUF_DEF(epout, CFG_TUD_MIDI_EP_BUFSIZE);
+} _midid_epbuf[CFG_TUD_MIDI];
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION midid_interface_t _midid_itf[CFG_TUD_MIDI];
+static midid_interface_t _midid_itf[CFG_TUD_MIDI];
 
-bool tud_midi_n_mounted (uint8_t itf)
-{
+bool tud_midi_n_mounted (uint8_t itf) {
   midid_interface_t* midi = &_midid_itf[itf];
   return midi->ep_in && midi->ep_out;
 }
 
-static void _prep_out_transaction (midid_interface_t* p_midi)
-{
-  uint8_t const rhport = 0;
+static void _prep_out_transaction(uint8_t idx) {
+  const uint8_t rhport = 0;
+  midid_interface_t* p_midi = &_midid_itf[idx];
   uint16_t available = tu_fifo_remaining(&p_midi->rx_ff);
 
   // Prepare for incoming data but only allow what we can store in the ring buffer.
   // TODO Actually we can still carry out the transfer, keeping count of received bytes
   // and slowly move it to the FIFO when read().
   // This pre-check reduces endpoint claiming
-  TU_VERIFY(available >= sizeof(p_midi->epout_buf), );
+  TU_VERIFY(available >= CFG_TUD_MIDI_EP_BUFSIZE, );
 
   // claim endpoint
   TU_VERIFY(usbd_edpt_claim(rhport, p_midi->ep_out), );
@@ -107,8 +105,8 @@ static void _prep_out_transaction (midid_interface_t* p_midi)
   // fifo can be changed before endpoint is claimed
   available = tu_fifo_remaining(&p_midi->rx_ff);
 
-  if ( available >= sizeof(p_midi->epout_buf) )  {
-    usbd_edpt_xfer(rhport, p_midi->ep_out, p_midi->epout_buf, sizeof(p_midi->epout_buf));
+  if ( available >= CFG_TUD_MIDI_EP_BUFSIZE )  {
+    usbd_edpt_xfer(rhport, p_midi->ep_out, _midid_epbuf[idx].epout, CFG_TUD_MIDI_EP_BUFSIZE);
   }else
   {
     // Release endpoint since we don't make any transfer
@@ -124,7 +122,7 @@ uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num)
   (void) cable_num;
 
   midid_interface_t* midi = &_midid_itf[itf];
-  midid_stream_t const* stream = &midi->stream_read;
+  const midid_stream_t* stream = &midi->stream_read;
 
   // when using with packet API stream total & index are both zero
   return tu_fifo_count(&midi->rx_ff) + (uint8_t) (stream->total - stream->index);
@@ -182,7 +180,7 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, ui
     uint8_t const count = (uint8_t) tu_min32(stream->total - stream->index, bufsize);
 
     // Skip the header (1st byte) in the buffer
-    memcpy(buf8, stream->buffer + 1 + stream->index, count);
+    TU_VERIFY(0 == tu_memcpy_s(buf8, bufsize, stream->buffer + 1 + stream->index, count));
 
     total_read += count;
     stream->index += count;
@@ -205,8 +203,8 @@ bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4])
   midid_interface_t* midi = &_midid_itf[itf];
   TU_VERIFY(midi->ep_out);
 
-  uint32_t const num_read = tu_fifo_read_n(&midi->rx_ff, packet, 4);
-  _prep_out_transaction(midi);
+  const uint32_t num_read = tu_fifo_read_n(&midi->rx_ff, packet, 4);
+  _prep_out_transaction(itf);
   return (num_read == 4);
 }
 
@@ -214,31 +212,31 @@ bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4])
 // WRITE API
 //--------------------------------------------------------------------+
 
-static uint32_t write_flush(midid_interface_t* midi)
-{
-  // No data to send
-  if ( !tu_fifo_count(&midi->tx_ff) ) return 0;
+static uint32_t write_flush(uint8_t idx) {
+  midid_interface_t* midi = &_midid_itf[idx];
 
-  uint8_t const rhport = 0;
+  if (!tu_fifo_count(&midi->tx_ff)) {
+    return 0; // No data to send
+  }
+
+  const uint8_t rhport = 0;
 
   // skip if previous transfer not complete
   TU_VERIFY( usbd_edpt_claim(rhport, midi->ep_in), 0 );
 
-  uint16_t count = tu_fifo_read_n(&midi->tx_ff, midi->epin_buf, CFG_TUD_MIDI_EP_BUFSIZE);
+  uint16_t count = tu_fifo_read_n(&midi->tx_ff, _midid_epbuf[idx].epin, CFG_TUD_MIDI_EP_BUFSIZE);
 
-  if (count)
-  {
-    TU_ASSERT( usbd_edpt_xfer(rhport, midi->ep_in, midi->epin_buf, count), 0 );
+  if (count) {
+    TU_ASSERT( usbd_edpt_xfer(rhport, midi->ep_in, _midid_epbuf[idx].epin, count), 0 );
     return count;
-  }else
-  {
+  }else {
     // Release endpoint since we don't make any transfer
     usbd_edpt_release(rhport, midi->ep_in);
     return 0;
   }
 }
 
-uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize)
+uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, const uint8_t* buffer, uint32_t bufsize)
 {
   midid_interface_t* midi = &_midid_itf[itf];
   TU_VERIFY(midi->ep_in, 0);
@@ -248,24 +246,23 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
   uint32_t i = 0;
   while ( (i < bufsize) && (tu_fifo_remaining(&midi->tx_ff) >= 4) )
   {
-    uint8_t const data = buffer[i];
+    const uint8_t data = buffer[i];
     i++;
 
     if ( stream->index == 0 )
     {
       //------------- New event packet -------------//
-
-      uint8_t const msg = data >> 4;
+      const uint8_t msg = data >> 4;
 
       stream->index = 2;
       stream->buffer[1] = data;
 
       // Check to see if we're still in a SysEx transmit.
-      if ( stream->buffer[0] == MIDI_CIN_SYSEX_START )
+      if ( ((stream->buffer[0]) & 0xF) == MIDI_CIN_SYSEX_START )
       {
         if ( data == MIDI_STATUS_SYSEX_END )
         {
-          stream->buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
+          stream->buffer[0] = (uint8_t) ((cable_num << 4) | MIDI_CIN_SYSEX_END_1BYTE);
           stream->total = 2;
         }
         else
@@ -308,6 +305,7 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
           stream->buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
           stream->total = 2;
         }
+        stream->buffer[0] |= (uint8_t)(cable_num << 4);
       }
       else
       {
@@ -328,9 +326,9 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
       stream->index++;
 
       // See if this byte ends a SysEx.
-      if ( stream->buffer[0] == MIDI_CIN_SYSEX_START && data == MIDI_STATUS_SYSEX_END )
+      if ( (stream->buffer[0] & 0xF) == MIDI_CIN_SYSEX_START && data == MIDI_STATUS_SYSEX_END )
       {
-        stream->buffer[0] = MIDI_CIN_SYSEX_START + (stream->index - 1);
+        stream->buffer[0] = (uint8_t) ((cable_num << 4) | (MIDI_CIN_SYSEX_START + (stream->index - 1)));
         stream->total = stream->index;
       }
     }
@@ -339,9 +337,11 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
     if ( stream->index == stream->total )
     {
       // zeroes unused bytes
-      for(uint8_t idx = stream->total; idx < 4; idx++) stream->buffer[idx] = 0;
+      for (uint8_t idx = stream->total; idx < 4; idx++) {
+        stream->buffer[idx] = 0;
+      }
 
-      uint16_t const count = tu_fifo_write_n(&midi->tx_ff, stream->buffer, 4);
+      const uint16_t count = tu_fifo_write_n(&midi->tx_ff, stream->buffer, 4);
 
       // complete current event packet, reset stream
       stream->index = stream->total = 0;
@@ -351,20 +351,21 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
     }
   }
 
-  write_flush(midi);
+  write_flush(itf);
 
   return i;
 }
 
-bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4])
-{
+bool tud_midi_n_packet_write (uint8_t itf, const uint8_t packet[4]) {
   midid_interface_t* midi = &_midid_itf[itf];
   TU_VERIFY(midi->ep_in);
 
-  if (tu_fifo_remaining(&midi->tx_ff) < 4) return false;
+  if (tu_fifo_remaining(&midi->tx_ff) < 4) {
+    return false;
+  }
 
   tu_fifo_write_n(&midi->tx_ff, packet, 4);
-  write_flush(midi);
+  write_flush(itf);
 
   return true;
 }
@@ -372,12 +373,10 @@ bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4])
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void midid_init(void)
-{
+void midid_init(void) {
   tu_memclr(_midid_itf, sizeof(_midid_itf));
 
-  for(uint8_t i=0; i<CFG_TUD_MIDI; i++)
-  {
+  for (uint8_t i = 0; i < CFG_TUD_MIDI; i++) {
     midid_interface_t* midi = &_midid_itf[i];
 
     // config fifo
@@ -385,12 +384,38 @@ void midid_init(void)
     tu_fifo_config(&midi->tx_ff, midi->tx_ff_buf, CFG_TUD_MIDI_TX_BUFSIZE, 1, false); // OBVS.
 
     #if CFG_FIFO_MUTEX
-    tu_fifo_config_mutex(&midi->rx_ff, NULL, osal_mutex_create(&midi->rx_ff_mutex));
-    tu_fifo_config_mutex(&midi->tx_ff, osal_mutex_create(&midi->tx_ff_mutex), NULL);
+    osal_mutex_t mutex_rd = osal_mutex_create(&midi->rx_ff_mutex);
+    osal_mutex_t mutex_wr = osal_mutex_create(&midi->tx_ff_mutex);
+    TU_ASSERT(mutex_wr != NULL && mutex_wr != NULL, );
+
+    tu_fifo_config_mutex(&midi->rx_ff, NULL, mutex_rd);
+    tu_fifo_config_mutex(&midi->tx_ff, mutex_wr, NULL);
     #endif
   }
 }
 
+bool midid_deinit(void) {
+  #if CFG_FIFO_MUTEX
+  for(uint8_t i=0; i<CFG_TUD_MIDI; i++) {
+    midid_interface_t* midi = &_midid_itf[i];
+    osal_mutex_t mutex_rd = midi->rx_ff.mutex_rd;
+    osal_mutex_t mutex_wr = midi->tx_ff.mutex_wr;
+
+    if (mutex_rd) {
+      osal_mutex_delete(mutex_rd);
+      tu_fifo_config_mutex(&midi->rx_ff, NULL, NULL);
+    }
+
+    if (mutex_wr) {
+      osal_mutex_delete(mutex_wr);
+      tu_fifo_config_mutex(&midi->tx_ff, NULL, NULL);
+    }
+  }
+  #endif
+
+  return true;
+}
+
 void midid_reset(uint8_t rhport)
 {
   (void) rhport;
@@ -404,32 +429,28 @@ void midid_reset(uint8_t rhport)
   }
 }
 
-uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len)
-{
+uint16_t midid_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint16_t max_len) {
   uint16_t drv_len = 0;
   uint8_t const * p_desc = (uint8_t const *)desc_itf;
-  // 1st Interface is Audio Control v1
+
+  // 1st Interface is Audio Control v1 (optional)
   if (TUSB_CLASS_AUDIO               == desc_itf->bInterfaceClass    &&
-            AUDIO_SUBCLASS_CONTROL         == desc_itf->bInterfaceSubClass &&
-            AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol)
-  {
+      AUDIO_SUBCLASS_CONTROL         == desc_itf->bInterfaceSubClass &&
+      AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) {
     drv_len = tu_desc_len(desc_itf);
     p_desc = tu_desc_next(desc_itf);
     // Skip Class Specific descriptors
-    while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
-    {
-        drv_len += tu_desc_len(p_desc);
-        p_desc   = tu_desc_next(p_desc);
+    while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) {
+      drv_len += tu_desc_len(p_desc);
+      p_desc   = tu_desc_next(p_desc);
     }
-  }
-  else
-  {
-    TU_LOG1("Warning: MIDI Device has no Audio Control Interface");
+  } else {
+    TU_LOG2("Warning: MIDI Device has no Audio Control Interface");
   }
 
   // 2nd Interface is MIDI Streaming
   TU_VERIFY(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0);
-  tusb_desc_interface_t const * desc_midi = (tusb_desc_interface_t const *) p_desc;
+  const tusb_desc_interface_t* desc_midi = (const tusb_desc_interface_t*) p_desc;
 
   TU_VERIFY(TUSB_CLASS_AUDIO               == desc_midi->bInterfaceClass    &&
             AUDIO_SUBCLASS_MIDI_STREAMING  == desc_midi->bInterfaceSubClass &&
@@ -437,11 +458,10 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint
 
   // Find available interface
   midid_interface_t * p_midi = NULL;
-  for(uint8_t i=0; i<CFG_TUD_MIDI; i++)
-  {
-    if ( _midid_itf[i].ep_in == 0 && _midid_itf[i].ep_out == 0 )
-    {
-      p_midi = &_midid_itf[i];
+  uint8_t idx;
+  for(idx=0; idx<CFG_TUD_MIDI; idx++) {
+    if ( _midid_itf[idx].ep_in == 0 && _midid_itf[idx].ep_out == 0 ) {
+      p_midi = &_midid_itf[idx];
       break;
     }
   }
@@ -460,8 +480,8 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint
   {
     if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
     {
-      TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0);
-      uint8_t ep_addr = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+      TU_ASSERT(usbd_edpt_open(rhport, (const tusb_desc_endpoint_t*) p_desc), 0);
+      uint8_t ep_addr = ((const tusb_desc_endpoint_t*) p_desc)->bEndpointAddress;
 
       if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN)
       {
@@ -482,7 +502,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint
   }
 
   // Prepare for incoming data
-  _prep_out_transaction(p_midi);
+  _prep_out_transaction(idx);
 
   return drv_len;
 }
@@ -490,14 +510,9 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool midid_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
-  (void) rhport;
-  (void) stage;
-  (void) request;
-
-  // driver doesn't support any request yet
-  return false;
+bool midid_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request) {
+  (void) rhport; (void) stage; (void) request;
+  return false; // driver doesn't support any request yet
 }
 
 bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
@@ -505,40 +520,37 @@ bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32
   (void) result;
   (void) rhport;
 
-  uint8_t itf;
+  uint8_t idx;
   midid_interface_t* p_midi;
 
   // Identify which interface to use
-  for (itf = 0; itf < CFG_TUD_MIDI; itf++)
-  {
-    p_midi = &_midid_itf[itf];
-    if ( ( ep_addr == p_midi->ep_out ) || ( ep_addr == p_midi->ep_in ) ) break;
+  for (idx = 0; idx < CFG_TUD_MIDI; idx++) {
+    p_midi = &_midid_itf[idx];
+    if ((ep_addr == p_midi->ep_out) || (ep_addr == p_midi->ep_in)) {
+      break;
+    }
   }
-  TU_ASSERT(itf < CFG_TUD_MIDI);
+  TU_ASSERT(idx < CFG_TUD_MIDI);
 
   // receive new data
-  if ( ep_addr == p_midi->ep_out )
-  {
-    tu_fifo_write_n(&p_midi->rx_ff, p_midi->epout_buf, (uint16_t) xferred_bytes);
+  if (ep_addr == p_midi->ep_out) {
+    tu_fifo_write_n(&p_midi->rx_ff, _midid_epbuf[idx].epout, (uint16_t)xferred_bytes);
 
     // invoke receive callback if available
-    if (tud_midi_rx_cb) tud_midi_rx_cb(itf);
+    if (tud_midi_rx_cb) {
+      tud_midi_rx_cb(idx);
+    }
 
     // prepare for next
     // TODO for now ep_out is not used by public API therefore there is no race condition,
     // and does not need to claim like ep_in
-    _prep_out_transaction(p_midi);
-  }
-  else if ( ep_addr == p_midi->ep_in )
-  {
-    if (0 == write_flush(p_midi))
-    {
+    _prep_out_transaction(idx);
+  } else if (ep_addr == p_midi->ep_in) {
+    if (0 == write_flush(idx)) {
       // If there is no data left, a ZLP should be sent if
       // xferred_bytes is multiple of EP size and not zero
-      if ( !tu_fifo_count(&p_midi->tx_ff) && xferred_bytes && (0 == (xferred_bytes % CFG_TUD_MIDI_EP_BUFSIZE)) )
-      {
-        if ( usbd_edpt_claim(rhport, p_midi->ep_in) )
-        {
+      if (!tu_fifo_count(&p_midi->tx_ff) && xferred_bytes && (0 == (xferred_bytes % CFG_TUD_MIDI_EP_BUFSIZE))) {
+        if (usbd_edpt_claim(rhport, p_midi->ep_in)) {
           usbd_edpt_xfer(rhport, p_midi->ep_in, NULL, 0);
         }
       }
diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h
index 211edc8d1..3e89cc0a3 100644
--- a/src/class/midi/midi_device.h
+++ b/src/class/midi/midi_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -158,6 +158,7 @@ static inline bool tud_midi_packet_write (uint8_t const packet[4])
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     midid_init            (void);
+bool     midid_deinit          (void);
 void     midid_reset           (uint8_t rhport);
 uint16_t midid_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     midid_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/msc/msc.h b/src/class/msc/msc.h
index 84b6e4d79..bbfd35a43 100644
--- a/src/class/msc/msc.h
+++ b/src/class/msc/msc.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -53,7 +53,7 @@ enum {
 };
 
 /// \brief MassStorage Protocol.
-/// \details CBI only approved to use with full-speed floopy disk & should not used with highspeed or device other than floopy
+/// \details CBI only approved to use with full-speed floppy disk & should not used with highspeed or device other than floppy
 typedef enum
 {
   MSC_PROTOCOL_CBI              = 0 ,  ///< Control/Bulk/Interrupt protocol (with command completion interrupt)
@@ -97,7 +97,7 @@ typedef struct TU_ATTR_PACKED
 {
   uint32_t signature    ; ///< Signature that helps identify this data packet as a CSW. The signature field shall contain the value 53425355h (little endian), indicating CSW.
   uint32_t tag          ; ///< The device shall set this field to the value received in the dCBWTag of the associated CBW.
-  uint32_t data_residue ; ///< For Data-Out the device shall report in the dCSWDataResiduethe difference between the amount of data expected as stated in the dCBWDataTransferLength, and the actual amount of data processed by the device. For Data-In the device shall report in the dCSWDataResiduethe difference between the amount of data expected as stated in the dCBWDataTransferLengthand the actual amount of relevant data sent by the device
+  uint32_t data_residue ; ///< For Data-Out the device shall report in the dCSWDataResidue the difference between the amount of data expected as stated in the dCBWDataTransferLength, and the actual amount of data processed by the device. For Data-In the device shall report in the dCSWDataResiduethe difference between the amount of data expected as stated in the dCBWDataTransferLengthand the actual amount of relevant data sent by the device
   uint8_t  status       ; ///< indicates the success or failure of the command. Values from \ref msc_csw_status_t
 }msc_csw_t;
 
@@ -120,14 +120,14 @@ typedef enum
   SCSI_CMD_REQUEST_SENSE                = 0x03, ///< The SCSI Request Sense command is part of the SCSI computer protocol standard. This command is used to obtain sense data -- status/error information -- from a target device.
   SCSI_CMD_READ_FORMAT_CAPACITY         = 0x23, ///< The command allows the Host to request a list of the possible format capacities for an installed writable media. This command also has the capability to report the writable capacity for a media when it is installed
   SCSI_CMD_READ_10                      = 0x28, ///< The READ (10) command requests that the device server read the specified logical block(s) and transfer them to the data-in buffer.
-  SCSI_CMD_WRITE_10                     = 0x2A, ///< The WRITE (10) command requests thatthe device server transfer the specified logical block(s) from the data-out buffer and write them.
+  SCSI_CMD_WRITE_10                     = 0x2A, ///< The WRITE (10) command requests that the device server transfer the specified logical block(s) from the data-out buffer and write them.
 }scsi_cmd_type_t;
 
 /// SCSI Sense Key
 typedef enum
 {
   SCSI_SENSE_NONE            = 0x00, ///< no specific Sense Key. This would be the case for a successful command
-  SCSI_SENSE_RECOVERED_ERROR = 0x01, ///< ndicates the last command completed successfully with some recovery action performed by the disc drive.
+  SCSI_SENSE_RECOVERED_ERROR = 0x01, ///< Indicates the last command completed successfully with some recovery action performed by the disc drive.
   SCSI_SENSE_NOT_READY       = 0x02, ///< Indicates the logical unit addressed cannot be accessed.
   SCSI_SENSE_MEDIUM_ERROR    = 0x03, ///< Indicates the command terminated with a non-recovered error condition.
   SCSI_SENSE_HARDWARE_ERROR  = 0x04, ///< Indicates the disc drive detected a nonrecoverable hardware failure while performing the command or during a self test.
@@ -138,7 +138,7 @@ typedef enum
   SCSI_SENSE_ABORTED_COMMAND = 0x0b, ///< Indicates the disc drive aborted the command.
   SCSI_SENSE_EQUAL           = 0x0c, ///< Indicates a SEARCH DATA command has satisfied an equal comparison.
   SCSI_SENSE_VOLUME_OVERFLOW = 0x0d, ///< Indicates a buffered peripheral device has reached the end of medium partition and data remains in the buffer that has not been written to the medium.
-  SCSI_SENSE_MISCOMPARE      = 0x0e  ///< ndicates that the source data did not match the data read from the medium.
+  SCSI_SENSE_MISCOMPARE      = 0x0e  ///< Indicates that the source data did not match the data read from the medium.
 }scsi_sense_key_type_t;
 
 //--------------------------------------------------------------------+
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 00b0a1d06..6670045aa 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -34,15 +34,17 @@
 
 #include "msc_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_MSC_LOG_LEVEL
+  #define CFG_TUD_MSC_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_MSC_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-
-// Can be selectively disabled to reduce logging when troubleshooting other driver
-#define MSC_DEBUG   2
-
-enum
-{
+enum {
   MSC_STAGE_CMD  = 0,
   MSC_STAGE_DATA,
   MSC_STAGE_STATUS,
@@ -50,11 +52,9 @@ enum
   MSC_STAGE_NEED_RESET,
 };
 
-typedef struct
-{
-  // TODO optimize alignment
-  CFG_TUSB_MEM_ALIGN msc_cbw_t cbw;
-  CFG_TUSB_MEM_ALIGN msc_csw_t csw;
+typedef struct {
+  TU_ATTR_ALIGNED(4) msc_cbw_t cbw;
+  TU_ATTR_ALIGNED(4) msc_csw_t csw;
 
   uint8_t  itf_num;
   uint8_t  ep_in;
@@ -62,6 +62,7 @@ typedef struct
 
   // Bulk Only Transfer (BOT) Protocol
   uint8_t  stage;
+
   uint32_t total_len;   // byte to be transferred, can be smaller than total_bytes in cbw
   uint32_t xferred_len; // numbered of bytes transferred so far in the Data Stage
 
@@ -71,8 +72,11 @@ typedef struct
   uint8_t add_sense_qualifier;
 }mscd_interface_t;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static mscd_interface_t _mscd_itf;
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE];
+static mscd_interface_t _mscd_itf;
+
+CFG_TUD_MEM_SECTION static struct {
+  TUD_EPBUF_DEF(buf, CFG_TUD_MSC_EP_BUFSIZE);
+} _mscd_epbuf;
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -83,28 +87,24 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
 static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
 static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes);
 
-TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) {
   return tu_bit_test(dir, 7);
 }
 
-static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc)
-{
+static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) {
   // Data residue is always = host expect - actual transferred
   p_msc->csw.data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len;
-
   p_msc->stage = MSC_STAGE_STATUS_SENT;
-  return usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t));
+  memcpy(_mscd_epbuf.buf, &p_msc->csw, sizeof(msc_csw_t));
+  return usbd_edpt_xfer(rhport, p_msc->ep_in , _mscd_epbuf.buf, sizeof(msc_csw_t));
 }
 
-static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc)
-{
+static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) {
   p_msc->stage = MSC_STAGE_CMD;
-  return usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t));
+  return usbd_edpt_xfer(rhport, p_msc->ep_out,  _mscd_epbuf.buf, sizeof(msc_cbw_t));
 }
 
-static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status)
-{
+static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status) {
   msc_cbw_t const * p_cbw = &p_msc->cbw;
   msc_csw_t       * p_csw = &p_msc->csw;
 
@@ -113,83 +113,63 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status
   p_msc->stage        = MSC_STAGE_STATUS;
 
   // failed but sense key is not set: default to Illegal Request
-  if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+  if (p_msc->sense_key == 0) {
+    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+  }
 
   // If there is data stage and not yet complete, stall it
-  if ( p_cbw->total_bytes && p_csw->data_residue )
-  {
-    if ( is_data_in(p_cbw->dir) )
-    {
+  if (p_cbw->total_bytes && p_csw->data_residue) {
+    if (is_data_in(p_cbw->dir)) {
       usbd_edpt_stall(rhport, p_msc->ep_in);
-    }
-    else
-    {
+    } else {
       usbd_edpt_stall(rhport, p_msc->ep_out);
     }
   }
 }
 
-static inline uint32_t rdwr10_get_lba(uint8_t const command[])
-{
+static inline uint32_t rdwr10_get_lba(uint8_t const command[]) {
   // use offsetof to avoid pointer to the odd/unaligned address
-  uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba));
-
-  // lba is in Big Endian
-  return tu_ntohl(lba);
+  const uint32_t lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba));
+  return tu_ntohl(lba); // lba is in Big Endian
 }
 
-static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw)
-{
+static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw) {
   uint16_t const block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count));
   return tu_ntohs(block_count);
 }
 
-static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw)
-{
+static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) {
   // first extract block count in the command
   uint16_t const block_count = rdwr10_get_blockcount(cbw);
-
-  // invalid block count
-  if (block_count == 0) return 0;
-
+  if (block_count == 0) {
+    return 0; // invalid block count
+  }
   return (uint16_t) (cbw->total_bytes / block_count);
 }
 
-uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
-{
+static uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) {
   uint8_t status = MSC_CSW_STATUS_PASSED;
   uint16_t const block_count = rdwr10_get_blockcount(cbw);
 
-  if ( cbw->total_bytes == 0 )
-  {
-    if ( block_count )
-    {
-      TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n");
+  if (cbw->total_bytes == 0) {
+    if (block_count) {
+      TU_LOG_DRV("  SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
-    }else
-    {
+    } else {
       // no data transfer, only exist in complaint test suite
     }
-  }else
-  {
-    if ( SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir) )
-    {
-      TU_LOG(MSC_DEBUG, "  SCSI case 10 (Ho <> Di)\r\n");
+  } else {
+    if (SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir)) {
+      TU_LOG_DRV("  SCSI case 10 (Ho <> Di)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
-    }
-    else if ( SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir) )
-    {
-      TU_LOG(MSC_DEBUG, "  SCSI case 8 (Hi <> Do)\r\n");
+    } else if (SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir)) {
+      TU_LOG_DRV("  SCSI case 8 (Hi <> Do)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
-    }
-    else if ( 0 == block_count )
-    {
-      TU_LOG(MSC_DEBUG, "  SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n");
-      status =  MSC_CSW_STATUS_FAILED;
-    }
-    else if ( cbw->total_bytes / block_count == 0 )
-    {
-      TU_LOG(MSC_DEBUG, " Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n");
+    } else if (0 == block_count) {
+      TU_LOG_DRV("  SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n");
+      status = MSC_CSW_STATUS_FAILED;
+    } else if (cbw->total_bytes / block_count == 0) {
+      TU_LOG_DRV(" Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }
   }
@@ -200,10 +180,9 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUD_MSC_LOG_LEVEL
 
-TU_ATTR_UNUSED static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
-{
+TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = {
   { .key = SCSI_CMD_TEST_UNIT_READY              , .data = "Test Unit Ready" },
   { .key = SCSI_CMD_INQUIRY                      , .data = "Inquiry" },
   { .key = SCSI_CMD_MODE_SELECT_6                , .data = "Mode_Select 6" },
@@ -217,8 +196,7 @@ TU_ATTR_UNUSED static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
   { .key = SCSI_CMD_WRITE_10                     , .data = "Write10" }
 };
 
-TU_ATTR_UNUSED static tu_lookup_table_t const _msc_scsi_cmd_table =
-{
+TU_ATTR_UNUSED tu_static tu_lookup_table_t const _msc_scsi_cmd_table = {
   .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup),
   .items = _msc_scsi_cmd_lookup
 };
@@ -228,19 +206,15 @@ TU_ATTR_UNUSED static tu_lookup_table_t const _msc_scsi_cmd_table =
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
-bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, uint8_t add_sense_qualifier)
-{
+bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, uint8_t add_sense_qualifier) {
   (void) lun;
-
   _mscd_itf.sense_key           = sense_key;
   _mscd_itf.add_sense_code      = add_sense_code;
   _mscd_itf.add_sense_qualifier = add_sense_qualifier;
-
   return true;
 }
 
-static inline void set_sense_medium_not_present(uint8_t lun)
-{
+static inline void set_sense_medium_not_present(uint8_t lun) {
   // default sense is NOT READY, MEDIUM NOT PRESENT
   tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3A, 0x00);
 }
@@ -248,48 +222,43 @@ static inline void set_sense_medium_not_present(uint8_t lun)
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void mscd_init(void)
-{
+void mscd_init(void) {
   tu_memclr(&_mscd_itf, sizeof(mscd_interface_t));
 }
 
-void mscd_reset(uint8_t rhport)
-{
+bool mscd_deinit(void) {
+  return true; // nothing to do
+}
+
+void mscd_reset(uint8_t rhport) {
   (void) rhport;
   tu_memclr(&_mscd_itf, sizeof(mscd_interface_t));
 }
 
-uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
+uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) {
   // only support SCSI's BOT protocol
   TU_VERIFY(TUSB_CLASS_MSC    == itf_desc->bInterfaceClass &&
             MSC_SUBCLASS_SCSI == itf_desc->bInterfaceSubClass &&
             MSC_PROTOCOL_BOT  == itf_desc->bInterfaceProtocol, 0);
-
-  // msc driver length is fixed
   uint16_t const drv_len = sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
-
-  // Max length must be at least 1 interface + 2 endpoints
-  TU_ASSERT(max_len >= drv_len, 0);
+  TU_ASSERT(max_len >= drv_len, 0); // Max length must be at least 1 interface + 2 endpoints
 
   mscd_interface_t * p_msc = &_mscd_itf;
   p_msc->itf_num = itf_desc->bInterfaceNumber;
 
   // Open endpoint pair
-  TU_ASSERT( usbd_open_edpt_pair(rhport, tu_desc_next(itf_desc), 2, TUSB_XFER_BULK, &p_msc->ep_out, &p_msc->ep_in), 0 );
+  TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(itf_desc), 2, TUSB_XFER_BULK, &p_msc->ep_out, &p_msc->ep_in), 0);
 
   // Prepare for Command Block Wrapper
-  TU_ASSERT( prepare_cbw(rhport, p_msc), drv_len);
+  TU_ASSERT(prepare_cbw(rhport, p_msc), drv_len);
 
   return drv_len;
 }
 
-static void proc_bot_reset(mscd_interface_t* p_msc)
-{
+static void proc_bot_reset(mscd_interface_t* p_msc) {
   p_msc->stage       = MSC_STAGE_CMD;
   p_msc->total_len   = 0;
   p_msc->xferred_len = 0;
-
   p_msc->sense_key           = 0;
   p_msc->add_sense_code      = 0;
   p_msc->add_sense_qualifier = 0;
@@ -298,10 +267,10 @@ static void proc_bot_reset(mscd_interface_t* p_msc)
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
-  // nothing to do with DATA & ACK stage
-  if (stage != CONTROL_STAGE_SETUP) return true;
+bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) {
+  if (stage != CONTROL_STAGE_SETUP) {
+    return true; // nothing to do with DATA & ACK stage
+  }
 
   mscd_interface_t* p_msc = &_mscd_itf;
 
@@ -309,35 +278,25 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
   if ( TUSB_REQ_TYPE_STANDARD     == request->bmRequestType_bit.type      &&
        TUSB_REQ_RCPT_ENDPOINT     == request->bmRequestType_bit.recipient &&
        TUSB_REQ_CLEAR_FEATURE     == request->bRequest                    &&
-       TUSB_REQ_FEATURE_EDPT_HALT == request->wValue )
-  {
+       TUSB_REQ_FEATURE_EDPT_HALT == request->wValue ) {
     uint8_t const ep_addr = tu_u16_low(request->wIndex);
 
-    if ( p_msc->stage == MSC_STAGE_NEED_RESET )
-    {
+    if (p_msc->stage == MSC_STAGE_NEED_RESET) {
       // reset recovery is required to recover from this stage
       // Clear Stall request cannot resolve this -> continue to stall endpoint
       usbd_edpt_stall(rhport, ep_addr);
-    }
-    else
-    {
-      if ( ep_addr == p_msc->ep_in )
-      {
-        if ( p_msc->stage == MSC_STAGE_STATUS )
-        {
+    } else {
+      if (ep_addr == p_msc->ep_in) {
+        if (p_msc->stage == MSC_STAGE_STATUS) {
           // resume sending SCSI status if we are in this stage previously before stalled
-          TU_ASSERT( send_csw(rhport, p_msc) );
+          TU_ASSERT(send_csw(rhport, p_msc));
         }
-      }
-      else if ( ep_addr == p_msc->ep_out )
-      {
-        if ( p_msc->stage == MSC_STAGE_CMD )
-        {
+      } else if (ep_addr == p_msc->ep_out) {
+        if (p_msc->stage == MSC_STAGE_CMD) {
           // part of reset recovery (probably due to invalid CBW) -> prepare for new command
           // Note: skip if already queued previously
-          if ( usbd_edpt_ready(rhport, p_msc->ep_out) )
-          {
-            TU_ASSERT( prepare_cbw(rhport, p_msc) );
+          if (usbd_edpt_ready(rhport, p_msc->ep_out)) {
+            TU_ASSERT(prepare_cbw(rhport, p_msc));
           }
         }
       }
@@ -349,33 +308,27 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
   // From this point only handle class request only
   TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
 
-  switch ( request->bRequest )
-  {
+  switch ( request->bRequest ) {
     case MSC_REQ_RESET:
-      TU_LOG(MSC_DEBUG, "  MSC BOT Reset\r\n");
+      TU_LOG_DRV("  MSC BOT Reset\r\n");
       TU_VERIFY(request->wValue == 0 && request->wLength == 0);
-
-      // driver state reset
-      proc_bot_reset(p_msc);
-
+      proc_bot_reset(p_msc); // driver state reset
       tud_control_status(rhport, request);
     break;
 
-    case MSC_REQ_GET_MAX_LUN:
-    {
-      TU_LOG(MSC_DEBUG, "  MSC Get Max Lun\r\n");
+    case MSC_REQ_GET_MAX_LUN: {
+      TU_LOG_DRV("  MSC Get Max Lun\r\n");
       TU_VERIFY(request->wValue == 0 && request->wLength == 1);
 
       uint8_t maxlun = 1;
-      if (tud_msc_get_maxlun_cb) maxlun = tud_msc_get_maxlun_cb();
+      if (tud_msc_get_maxlun_cb) {
+        maxlun = tud_msc_get_maxlun_cb();
+      }
       TU_VERIFY(maxlun);
-
-      // MAX LUN is minus 1 by specs
-      maxlun--;
-
+      maxlun--; // MAX LUN is minus 1 by specs
       tud_control_xfer(rhport, request, &maxlun, 1);
+      break;
     }
-    break;
 
     default: return false; // stall unsupported request
   }
@@ -383,37 +336,36 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
   return true;
 }
 
-bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
-{
+bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) {
   (void) event;
 
   mscd_interface_t* p_msc = &_mscd_itf;
-  msc_cbw_t const * p_cbw = &p_msc->cbw;
-  msc_csw_t       * p_csw = &p_msc->csw;
+  msc_cbw_t * p_cbw = &p_msc->cbw;
+  msc_csw_t * p_csw = &p_msc->csw;
 
-  switch (p_msc->stage)
-  {
+  switch (p_msc->stage) {
     case MSC_STAGE_CMD:
       //------------- new CBW received -------------//
       // Complete IN while waiting for CMD is usually Status of previous SCSI op, ignore it
-      if(ep_addr != p_msc->ep_out) return true;
+      if (ep_addr != p_msc->ep_out) {
+        return true;
+      }
 
-      if ( !(xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE) )
-      {
-        TU_LOG(MSC_DEBUG, "  SCSI CBW is not valid\r\n");
+      const uint32_t signature = tu_le32toh(tu_unaligned_read32(_mscd_epbuf.buf));
 
+      if (!(xferred_bytes == sizeof(msc_cbw_t) && signature == MSC_CBW_SIGNATURE)) {
         // BOT 6.6.1 If CBW is not valid stall both endpoints until reset recovery
+        TU_LOG_DRV("  SCSI CBW is not valid\r\n");
         p_msc->stage = MSC_STAGE_NEED_RESET;
-
-        // invalid CBW stall both endpoints
         usbd_edpt_stall(rhport, p_msc->ep_in);
         usbd_edpt_stall(rhport, p_msc->ep_out);
-
         return false;
       }
 
-      TU_LOG(MSC_DEBUG, "  SCSI Command [Lun%u]: %s\r\n", p_cbw->lun, tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
-      //TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2);
+      memcpy(p_cbw, _mscd_epbuf.buf, sizeof(msc_cbw_t));
+
+      TU_LOG_DRV("  SCSI Command [Lun%u]: %s\r\n", p_cbw->lun, tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
+      // TU_LOG_MEM(CFG_TUD_MSC_LOG_LEVEL, p_cbw, xferred_bytes, 2);
 
       p_csw->signature    = MSC_CSW_SIGNATURE;
       p_csw->tag          = p_cbw->tag;
@@ -426,87 +378,65 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       p_msc->xferred_len = 0;
 
       // Read10 or Write10
-      if ( (SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0]) )
-      {
+      if ((SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0])) {
         uint8_t const status = rdwr10_validate_cmd(p_cbw);
 
-        if ( status != MSC_CSW_STATUS_PASSED)
-        {
+        if (status != MSC_CSW_STATUS_PASSED) {
           fail_scsi_op(rhport, p_msc, status);
-        }else if ( p_cbw->total_bytes )
-        {
-          if (SCSI_CMD_READ_10 == p_cbw->command[0])
-          {
+        } else if (p_cbw->total_bytes) {
+          if (SCSI_CMD_READ_10 == p_cbw->command[0]) {
             proc_read10_cmd(rhport, p_msc);
-          }else
-          {
+          } else {
             proc_write10_cmd(rhport, p_msc);
           }
-        }else
-        {
+        } else {
           // no data transfer, only exist in complaint test suite
           p_msc->stage = MSC_STAGE_STATUS;
         }
-      }
-      else
-      {
+      } else {
         // For other SCSI commands
         // 1. OUT : queue transfer (invoke app callback after done)
         // 2. IN & Zero: Process if is built-in, else Invoke app callback. Skip DATA if zero length
-        if ( (p_cbw->total_bytes > 0 ) && !is_data_in(p_cbw->dir) )
-        {
-          if (p_cbw->total_bytes > sizeof(_mscd_buf))
-          {
-            TU_LOG(MSC_DEBUG, "  SCSI reject non READ10/WRITE10 with large data\r\n");
+        if ((p_cbw->total_bytes > 0) && !is_data_in(p_cbw->dir)) {
+          if (p_cbw->total_bytes > CFG_TUD_MSC_EP_BUFSIZE) {
+            TU_LOG_DRV("  SCSI reject non READ10/WRITE10 with large data\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-          }else
-          {
+          } else {
             // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first
             // but it is OK to just receive data then responded with failed status
-            TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, (uint16_t) p_msc->total_len) );
+            TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_epbuf.buf, (uint16_t) p_msc->total_len));
           }
-        }else
-        {
+        } else {
           // First process if it is a built-in commands
-          int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, _mscd_buf, sizeof(_mscd_buf));
+          int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, _mscd_epbuf.buf, CFG_TUD_MSC_EP_BUFSIZE);
 
           // Invoke user callback if not built-in
-          if ( (resplen < 0) && (p_msc->sense_key == 0) )
-          {
-            resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len);
+          if ((resplen < 0) && (p_msc->sense_key == 0)) {
+            resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_epbuf.buf, (uint16_t)p_msc->total_len);
           }
 
-          if ( resplen < 0 )
-          {
+          if (resplen < 0) {
             // unsupported command
-            TU_LOG(MSC_DEBUG, "  SCSI unsupported or failed command\r\n");
+            TU_LOG_DRV("  SCSI unsupported or failed command\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-          }
-          else if (resplen == 0)
-          {
-            if (p_cbw->total_bytes)
-            {
+          } else if (resplen == 0) {
+            if (p_cbw->total_bytes) {
               // 6.7 The 13 Cases: case 4 (Hi > Dn)
-              // TU_LOG(MSC_DEBUG, "  SCSI case 4 (Hi > Dn): %lu\r\n", p_cbw->total_bytes);
+              // TU_LOG_DRV("  SCSI case 4 (Hi > Dn): %lu\r\n", p_cbw->total_bytes);
               fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-            }else
-            {
+            } else {
               // case 1 Hn = Dn: all good
               p_msc->stage = MSC_STAGE_STATUS;
             }
-          }
-          else
-          {
-            if ( p_cbw->total_bytes == 0 )
-            {
+          } else {
+            if (p_cbw->total_bytes == 0) {
               // 6.7 The 13 Cases: case 2 (Hn < Di)
-              // TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di): %lu\r\n", p_cbw->total_bytes);
+              // TU_LOG_DRV("  SCSI case 2 (Hn < Di): %lu\r\n", p_cbw->total_bytes);
               fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-            }else
-            {
+            } else {
               // cannot return more than host expect
-              p_msc->total_len = tu_min32((uint32_t) resplen, p_cbw->total_bytes);
-              TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) p_msc->total_len) );
+              p_msc->total_len = tu_min32((uint32_t)resplen, p_cbw->total_bytes);
+              TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_epbuf.buf, (uint16_t) p_msc->total_len));
             }
           }
         }
@@ -514,53 +444,41 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     break;
 
     case MSC_STAGE_DATA:
-      TU_LOG(MSC_DEBUG, "  SCSI Data [Lun%u]\r\n", p_cbw->lun);
-      //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2);
+      TU_LOG_DRV("  SCSI Data [Lun%u]\r\n", p_cbw->lun);
+      TU_ASSERT(xferred_bytes <= CFG_TUD_MSC_EP_BUFSIZE); // sanity check to avoid buffer overflow
+      // TU_LOG_MEM(CFG_TUD_MSC_LOG_LEVEL, _mscd_epbuf.buf, xferred_bytes, 2);
 
-      if (SCSI_CMD_READ_10 == p_cbw->command[0])
-      {
+      if (SCSI_CMD_READ_10 == p_cbw->command[0]) {
         p_msc->xferred_len += xferred_bytes;
 
-        if ( p_msc->xferred_len >= p_msc->total_len )
-        {
+        if ( p_msc->xferred_len >= p_msc->total_len ) {
           // Data Stage is complete
           p_msc->stage = MSC_STAGE_STATUS;
-        }else
-        {
+        }else {
           proc_read10_cmd(rhport, p_msc);
         }
-      }
-      else if (SCSI_CMD_WRITE_10 == p_cbw->command[0])
-      {
+      } else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) {
         proc_write10_new_data(rhport, p_msc, xferred_bytes);
-      }
-      else
-      {
+      } else {
         p_msc->xferred_len += xferred_bytes;
 
         // OUT transfer, invoke callback if needed
-        if ( !is_data_in(p_cbw->dir) )
-        {
-          int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len);
+        if ( !is_data_in(p_cbw->dir) ) {
+          int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_epbuf.buf, (uint16_t) p_msc->total_len);
 
-          if ( cb_result < 0 )
-          {
+          if ( cb_result < 0 ) {
             // unsupported command
-            TU_LOG(MSC_DEBUG, "  SCSI unsupported command\r\n");
+            TU_LOG_DRV("  SCSI unsupported command\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-          }else
-          {
+          }else {
             // TODO haven't implement this scenario any further yet
           }
         }
 
-        if ( p_msc->xferred_len >= p_msc->total_len )
-        {
+        if ( p_msc->xferred_len >= p_msc->total_len ) {
           // Data Stage is complete
           p_msc->stage = MSC_STAGE_STATUS;
-        }
-        else
-        {
+        } else {
           // This scenario with command that take more than one transfer is already rejected at Command stage
           TU_BREAKPOINT();
         }
@@ -573,53 +491,52 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
 
     case MSC_STAGE_STATUS_SENT:
       // Wait for the Status phase to complete
-      if( (ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t)) )
-      {
-        TU_LOG(MSC_DEBUG, "  SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status);
-        // TU_LOG_MEM(MSC_DEBUG, p_csw, xferred_bytes, 2);
+      if ((ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t))) {
+        TU_LOG_DRV("  SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status);
+        // TU_LOG_MEM(CFG_TUD_MSC_LOG_LEVEL, p_csw, xferred_bytes, 2);
 
         // Invoke complete callback if defined
         // Note: There is racing issue with samd51 + qspi flash testing with arduino
         // if complete_cb() is invoked after queuing the status.
-        switch(p_cbw->command[0])
-        {
+        switch (p_cbw->command[0]) {
           case SCSI_CMD_READ_10:
-            if ( tud_msc_read10_complete_cb ) tud_msc_read10_complete_cb(p_cbw->lun);
-          break;
+            if (tud_msc_read10_complete_cb) {
+              tud_msc_read10_complete_cb(p_cbw->lun);
+            }
+            break;
 
           case SCSI_CMD_WRITE_10:
-            if ( tud_msc_write10_complete_cb ) tud_msc_write10_complete_cb(p_cbw->lun);
-          break;
+            if (tud_msc_write10_complete_cb) {
+              tud_msc_write10_complete_cb(p_cbw->lun);
+            }
+            break;
 
           default:
-            if ( tud_msc_scsi_complete_cb ) tud_msc_scsi_complete_cb(p_cbw->lun, p_cbw->command);
-          break;
+            if (tud_msc_scsi_complete_cb) {
+              tud_msc_scsi_complete_cb(p_cbw->lun, p_cbw->command);
+            }
+            break;
         }
 
-        TU_ASSERT( prepare_cbw(rhport, p_msc) );
-      }else
-      {
+        TU_ASSERT(prepare_cbw(rhport, p_msc));
+      } else {
         // Any xfer ended here is consider unknown error, ignore it
         TU_LOG1("  Warning expect SCSI Status but received unknown data\r\n");
       }
-    break;
+      break;
 
-    default : break;
+    default: break;
   }
 
-  if ( p_msc->stage == MSC_STAGE_STATUS )
-  {
+  if (p_msc->stage == MSC_STAGE_STATUS) {
     // skip status if epin is currently stalled, will do it when received Clear Stall request
-    if ( !usbd_edpt_stalled(rhport,  p_msc->ep_in) )
-    {
-      if ( (p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir) )
-      {
+    if (!usbd_edpt_stalled(rhport, p_msc->ep_in)) {
+      if ((p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir)) {
         // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status
-        // TU_LOG(MSC_DEBUG, "  SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len);
+        // TU_LOG_DRV("  SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len);
         usbd_edpt_stall(rhport, p_msc->ep_in);
-      }else
-      {
-        TU_ASSERT( send_csw(rhport, p_msc) );
+      } else {
+        TU_ASSERT(send_csw(rhport, p_msc));
       }
     }
 
@@ -627,8 +544,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD.
     // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and
     // hope everything will work
-    if ( usbd_edpt_stalled(rhport, p_msc->ep_in) )
-    {
+    if ( usbd_edpt_stalled(rhport, p_msc->ep_in) ) {
       usbd_edpt_clear_stall(rhport, p_msc->ep_in);
       send_csw(rhport, p_msc);
     }
@@ -644,82 +560,97 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
 
 // return response's length (copied to buffer). Negative if it is not an built-in command or indicate Failed status (CSW)
 // In case of a failed status, sense key must be set for reason of failure
-static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_t* buffer, uint32_t bufsize)
-{
-  (void) bufsize; // TODO refractor later
+static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_t* buffer, uint32_t bufsize) {
+  (void)bufsize; // TODO refractor later
   int32_t resplen;
 
   mscd_interface_t* p_msc = &_mscd_itf;
 
-  switch ( scsi_cmd[0] )
-  {
+  switch (scsi_cmd[0]) {
     case SCSI_CMD_TEST_UNIT_READY:
       resplen = 0;
-      if ( !tud_msc_test_unit_ready_cb(lun) )
-      {
+      if (!tud_msc_test_unit_ready_cb(lun)) {
         // Failed status response
-        resplen = - 1;
+        resplen = -1;
 
         // set default sense if not set by callback
-        if ( p_msc->sense_key == 0 ) set_sense_medium_not_present(lun);
+        if (p_msc->sense_key == 0) {
+          set_sense_medium_not_present(lun);
+        }
       }
-    break;
+      break;
 
     case SCSI_CMD_START_STOP_UNIT:
       resplen = 0;
 
-      if (tud_msc_start_stop_cb)
-      {
-        scsi_start_stop_unit_t const * start_stop = (scsi_start_stop_unit_t const *) scsi_cmd;
-        if ( !tud_msc_start_stop_cb(lun, start_stop->power_condition, start_stop->start, start_stop->load_eject) )
-        {
+      if (tud_msc_start_stop_cb) {
+        scsi_start_stop_unit_t const* start_stop = (scsi_start_stop_unit_t const*)scsi_cmd;
+        if (!tud_msc_start_stop_cb(lun, start_stop->power_condition, start_stop->start, start_stop->load_eject)) {
           // Failed status response
-          resplen = - 1;
+          resplen = -1;
 
           // set default sense if not set by callback
-          if ( p_msc->sense_key == 0 ) set_sense_medium_not_present(lun);
+          if (p_msc->sense_key == 0) {
+            set_sense_medium_not_present(lun);
+          }
         }
       }
-    break;
+      break;
 
-    case SCSI_CMD_READ_CAPACITY_10:
-    {
+    case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
+      resplen = 0;
+
+      if (tud_msc_prevent_allow_medium_removal_cb) {
+        scsi_prevent_allow_medium_removal_t const* prevent_allow = (scsi_prevent_allow_medium_removal_t const*)scsi_cmd;
+        if (!tud_msc_prevent_allow_medium_removal_cb(lun, prevent_allow->prohibit_removal, prevent_allow->control)) {
+          // Failed status response
+          resplen = -1;
+
+          // set default sense if not set by callback
+          if (p_msc->sense_key == 0) {
+            set_sense_medium_not_present(lun);
+          }
+        }
+      }
+      break;
+
+
+    case SCSI_CMD_READ_CAPACITY_10: {
       uint32_t block_count;
       uint32_t block_size;
       uint16_t block_size_u16;
 
       tud_msc_capacity_cb(lun, &block_count, &block_size_u16);
-      block_size = (uint32_t) block_size_u16;
+      block_size = (uint32_t)block_size_u16;
 
       // Invalid block size/count from callback, possibly unit is not ready
       // stall this request, set sense key to NOT READY
-      if (block_count == 0 || block_size == 0)
-      {
+      if (block_count == 0 || block_size == 0) {
         resplen = -1;
 
         // set default sense if not set by callback
-        if ( p_msc->sense_key == 0 ) set_sense_medium_not_present(lun);
-      }else
-      {
+        if (p_msc->sense_key == 0) {
+          set_sense_medium_not_present(lun);
+        }
+      } else {
         scsi_read_capacity10_resp_t read_capa10;
 
-        read_capa10.last_lba   = tu_htonl(block_count-1);
+        read_capa10.last_lba = tu_htonl(block_count-1);
         read_capa10.block_size = tu_htonl(block_size);
 
         resplen = sizeof(read_capa10);
-        memcpy(buffer, &read_capa10, (size_t) resplen);
+        TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &read_capa10, (size_t) resplen));
       }
     }
     break;
 
-    case SCSI_CMD_READ_FORMAT_CAPACITY:
-    {
+    case SCSI_CMD_READ_FORMAT_CAPACITY: {
       scsi_read_format_capacity_data_t read_fmt_capa =
       {
-          .list_length     = 8,
-          .block_num       = 0,
-          .descriptor_type = 2, // formatted media
-          .block_size_u16  = 0
+        .list_length = 8,
+        .block_num = 0,
+        .descriptor_type = 2, // formatted media
+        .block_size_u16 = 0
       };
 
       uint32_t block_count;
@@ -729,31 +660,30 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
 
       // Invalid block size/count from callback, possibly unit is not ready
       // stall this request, set sense key to NOT READY
-      if (block_count == 0 || block_size == 0)
-      {
+      if (block_count == 0 || block_size == 0) {
         resplen = -1;
 
         // set default sense if not set by callback
-        if ( p_msc->sense_key == 0 ) set_sense_medium_not_present(lun);
-      }else
-      {
+        if (p_msc->sense_key == 0) {
+          set_sense_medium_not_present(lun);
+        }
+      } else {
         read_fmt_capa.block_num = tu_htonl(block_count);
         read_fmt_capa.block_size_u16 = tu_htons(block_size);
 
         resplen = sizeof(read_fmt_capa);
-        memcpy(buffer, &read_fmt_capa, (size_t) resplen);
+        TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &read_fmt_capa, (size_t) resplen));
       }
     }
     break;
 
-    case SCSI_CMD_INQUIRY:
-    {
+    case SCSI_CMD_INQUIRY: {
       scsi_inquiry_resp_t inquiry_rsp =
       {
-          .is_removable         = 1,
-          .version              = 2,
-          .response_data_format = 2,
-          .additional_length    = sizeof(scsi_inquiry_resp_t) - 5,
+        .is_removable = 1,
+        .version = 2,
+        .response_data_format = 2,
+        .additional_length = sizeof(scsi_inquiry_resp_t) - 5,
       };
 
       // vendor_id, product_id, product_rev is space padded string
@@ -764,54 +694,50 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       tud_msc_inquiry_cb(lun, inquiry_rsp.vendor_id, inquiry_rsp.product_id, inquiry_rsp.product_rev);
 
       resplen = sizeof(inquiry_rsp);
-      memcpy(buffer, &inquiry_rsp, (size_t) resplen);
+      TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &inquiry_rsp, (size_t) resplen));
     }
     break;
 
-    case SCSI_CMD_MODE_SENSE_6:
-    {
+    case SCSI_CMD_MODE_SENSE_6: {
       scsi_mode_sense6_resp_t mode_resp =
       {
-          .data_len             = 3,
-          .medium_type          = 0,
-          .write_protected      = false,
-          .reserved             = 0,
-          .block_descriptor_len = 0  // no block descriptor are included
+        .data_len = 3,
+        .medium_type = 0,
+        .write_protected = false,
+        .reserved = 0,
+        .block_descriptor_len = 0 // no block descriptor are included
       };
 
       bool writable = true;
-      if ( tud_msc_is_writable_cb )
-      {
+      if (tud_msc_is_writable_cb) {
         writable = tud_msc_is_writable_cb(lun);
       }
 
       mode_resp.write_protected = !writable;
 
       resplen = sizeof(mode_resp);
-      memcpy(buffer, &mode_resp, (size_t) resplen);
+      TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &mode_resp, (size_t) resplen));
     }
     break;
 
-    case SCSI_CMD_REQUEST_SENSE:
-    {
+    case SCSI_CMD_REQUEST_SENSE: {
       scsi_sense_fixed_resp_t sense_rsp =
       {
-          .response_code = 0x70, // current, fixed format
-          .valid         = 1
+        .response_code = 0x70, // current, fixed format
+        .valid = 1
       };
 
-      sense_rsp.add_sense_len       = sizeof(scsi_sense_fixed_resp_t) - 8;
-      sense_rsp.sense_key           = (uint8_t) (p_msc->sense_key & 0x0F);
-      sense_rsp.add_sense_code      = p_msc->add_sense_code;
+      sense_rsp.add_sense_len = sizeof(scsi_sense_fixed_resp_t) - 8;
+      sense_rsp.sense_key = (uint8_t)(p_msc->sense_key & 0x0F);
+      sense_rsp.add_sense_code = p_msc->add_sense_code;
       sense_rsp.add_sense_qualifier = p_msc->add_sense_qualifier;
 
       resplen = sizeof(sense_rsp);
-      memcpy(buffer, &sense_rsp, (size_t) resplen);
+      TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &sense_rsp, (size_t) resplen));
 
       // request sense callback could overwrite the sense data
-      if (tud_msc_request_sense_cb)
-      {
-        resplen = tud_msc_request_sense_cb(lun, buffer, (uint16_t) bufsize);
+      if (tud_msc_request_sense_cb) {
+        resplen = tud_msc_request_sense_cb(lun, buffer, (uint16_t)bufsize);
       }
 
       // Clear sense data after copy
@@ -819,15 +745,15 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
     }
     break;
 
-    default: resplen = -1; break;
+    default: resplen = -1;
+      break;
   }
 
   return resplen;
 }
 
-static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
-{
-  msc_cbw_t const * p_cbw = &p_msc->cbw;
+static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) {
+  msc_cbw_t const* p_cbw = &p_msc->cbw;
 
   // block size already verified not zero
   uint16_t const block_sz = rdwr10_get_blocksize(p_cbw);
@@ -836,45 +762,37 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz);
 
   // remaining bytes capped at class buffer
-  int32_t nbytes = (int32_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len);
+  int32_t nbytes = (int32_t)tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes - p_msc->xferred_len);
 
   // Application can consume smaller bytes
   uint32_t const offset = p_msc->xferred_len % block_sz;
-  nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_buf, (uint32_t) nbytes);
+  nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, (uint32_t)nbytes);
 
-  if ( nbytes < 0 )
-  {
+  if (nbytes < 0) {
     // negative means error -> endpoint is stalled & status in CSW set to failed
-    TU_LOG(MSC_DEBUG, "  tud_msc_read10_cb() return -1\r\n");
+    TU_LOG_DRV("  tud_msc_read10_cb() return -1\r\n");
 
     // set sense
     set_sense_medium_not_present(p_cbw->lun);
 
     fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-  }
-  else if ( nbytes == 0 )
-  {
+  } else if (nbytes == 0) {
     // zero means not ready -> simulate an transfer complete so that this driver callback will fired again
     dcd_event_xfer_complete(rhport, p_msc->ep_in, 0, XFER_RESULT_SUCCESS, false);
-  }
-  else
-  {
-    TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) nbytes), );
+  } else {
+    TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_epbuf.buf, (uint16_t) nbytes),);
   }
 }
 
-static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
-{
-  msc_cbw_t const * p_cbw = &p_msc->cbw;
+static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) {
+  msc_cbw_t const* p_cbw = &p_msc->cbw;
   bool writable = true;
 
-  if ( tud_msc_is_writable_cb )
-  {
+  if (tud_msc_is_writable_cb) {
     writable = tud_msc_is_writable_cb(p_cbw->lun);
   }
 
-  if ( !writable )
-  {
+  if (!writable) {
     // Not writable, complete this SCSI op with error
     // Sense = Write protected
     tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00);
@@ -883,16 +801,15 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   }
 
   // remaining bytes capped at class buffer
-  uint16_t nbytes = (uint16_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len);
+  uint16_t nbytes = (uint16_t)tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes - p_msc->xferred_len);
 
   // Write10 callback will be called later when usb transfer complete
-  TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, nbytes), );
+  TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_epbuf.buf, nbytes),);
 }
 
 // process new data arrived from WRITE10
-static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes)
-{
-  msc_cbw_t const * p_cbw = &p_msc->cbw;
+static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes) {
+  msc_cbw_t const* p_cbw = &p_msc->cbw;
 
   // block size already verified not zero
   uint16_t const block_sz = rdwr10_get_blocksize(p_cbw);
@@ -902,46 +819,36 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
 
   // Invoke callback to consume new data
   uint32_t const offset = p_msc->xferred_len % block_sz;
-  int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_buf, xferred_bytes);
+  int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, xferred_bytes);
 
-  if ( nbytes < 0 )
-  {
+  if (nbytes < 0) {
     // negative means error -> failed this scsi op
-    TU_LOG(MSC_DEBUG, "  tud_msc_write10_cb() return -1\r\n");
+    TU_LOG_DRV("  tud_msc_write10_cb() return -1\r\n");
 
     // update actual byte before failed
     p_msc->xferred_len += xferred_bytes;
 
-    // Set sense
     set_sense_medium_not_present(p_cbw->lun);
-
     fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-  }else
-  {
-    // Application consume less than what we got (including zero)
-    if ( (uint32_t) nbytes < xferred_bytes )
-    {
-      uint32_t const left_over = xferred_bytes - (uint32_t) nbytes;
-      if ( nbytes > 0 )
-      {
-        p_msc->xferred_len += (uint16_t) nbytes;
-        memmove(_mscd_buf, _mscd_buf+nbytes, left_over);
+  } else {
+    if ((uint32_t)nbytes < xferred_bytes) {
+      // Application consume less than what we got (including zero)
+      const uint32_t left_over = xferred_bytes - (uint32_t)nbytes;
+      if (nbytes > 0) {
+        p_msc->xferred_len += (uint16_t)nbytes;
+        memmove(_mscd_epbuf.buf, _mscd_epbuf.buf + nbytes, left_over);
       }
 
-      // simulate an transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter
+      // simulate a transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter
       dcd_event_xfer_complete(rhport, p_msc->ep_out, left_over, XFER_RESULT_SUCCESS, false);
-    }
-    else
-    {
+    } else {
       // Application consume all bytes in our buffer
       p_msc->xferred_len += xferred_bytes;
 
-      if ( p_msc->xferred_len >= p_msc->total_len )
-      {
+      if (p_msc->xferred_len >= p_msc->total_len) {
         // Data Stage is complete
         p_msc->stage = MSC_STAGE_STATUS;
-      }else
-      {
+      } else {
         // prepare to receive more data from host
         proc_write10_cmd(rhport, p_msc);
       }
diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h
index 5839b168d..29acd280a 100644
--- a/src/class/msc/msc_device.h
+++ b/src/class/msc/msc_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -131,6 +131,9 @@ TU_ATTR_WEAK uint8_t tud_msc_get_maxlun_cb(void);
 // - Start = 1 : active mode, if load_eject = 1 : load disk storage
 TU_ATTR_WEAK bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject);
 
+//Invoked when we receive the Prevent / Allow Medium Removal command
+TU_ATTR_WEAK bool tud_msc_prevent_allow_medium_removal_cb(uint8_t lun, uint8_t prohibit_removal, uint8_t control);
+
 // Invoked when received REQUEST_SENSE
 TU_ATTR_WEAK int32_t tud_msc_request_sense_cb(uint8_t lun, void* buffer, uint16_t bufsize);
 
@@ -150,6 +153,7 @@ TU_ATTR_WEAK bool tud_msc_is_writable_cb(uint8_t lun);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     mscd_init            (void);
+bool     mscd_deinit          (void);
 void     mscd_reset           (uint8_t rhport);
 uint16_t mscd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     mscd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * p_request);
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 934f79ff7..ef0635bbe 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -29,124 +29,129 @@
 #if CFG_TUH_ENABLED && CFG_TUH_MSC
 
 #include "host/usbh.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 
 #include "msc_host.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUH_MSC_LOG_LEVEL
+  #define CFG_TUH_MSC_LOG_LEVEL   CFG_TUH_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_MSC_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-enum
-{
+enum {
   MSC_STAGE_IDLE = 0,
   MSC_STAGE_CMD,
   MSC_STAGE_DATA,
   MSC_STAGE_STATUS,
 };
 
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t ep_out;
-
   uint8_t max_lun;
 
   volatile bool configured; // Receive SET_CONFIGURE
   volatile bool mounted;    // Enumeration is complete
 
+  // SCSI command data
+  uint8_t stage;
+  void* buffer;
+  tuh_msc_complete_cb_t complete_cb;
+  uintptr_t complete_arg;
+
   struct {
     uint32_t block_size;
     uint32_t block_count;
   } capacity[CFG_TUH_MSC_MAXLUN];
+} msch_interface_t;
 
-  //------------- SCSI -------------//
-  uint8_t stage;
-  void*   buffer;
-  tuh_msc_complete_cb_t complete_cb;
+typedef struct {
+  TUH_EPBUF_TYPE_DEF(msc_cbw_t, cbw);
+  TUH_EPBUF_TYPE_DEF(msc_csw_t, csw);
+} msch_epbuf_t;
 
-  msc_cbw_t cbw;
-  msc_csw_t csw;
-}msch_interface_t;
+static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
+CFG_TUH_MEM_SECTION static msch_epbuf_t _msch_epbuf[CFG_TUH_DEVICE_MAX];
 
-CFG_TUSB_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
+TU_ATTR_ALWAYS_INLINE static inline msch_interface_t* get_itf(uint8_t daddr) {
+  return &_msch_itf[daddr - 1];
+}
 
-// buffer used to read scsi information when mounted
-// largest response data currently is inquiry TODO Inquiry is not part of enum anymore
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4)
-static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)];
-
-TU_ATTR_ALWAYS_INLINE
-static inline msch_interface_t* get_itf(uint8_t dev_addr)
-{
-  return &_msch_itf[dev_addr-1];
+TU_ATTR_ALWAYS_INLINE static inline msch_epbuf_t* get_epbuf(uint8_t daddr) {
+  return &_msch_epbuf[daddr - 1];
 }
 
 //--------------------------------------------------------------------+
 // PUBLIC API
 //--------------------------------------------------------------------+
-uint8_t tuh_msc_get_maxlun(uint8_t dev_addr)
-{
+uint8_t tuh_msc_get_maxlun(uint8_t dev_addr) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->max_lun;
 }
 
-uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun)
-{
+uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->capacity[lun].block_count;
 }
 
-uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun)
-{
+uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->capacity[lun].block_size;
 }
 
-bool tuh_msc_mounted(uint8_t dev_addr)
-{
+bool tuh_msc_mounted(uint8_t dev_addr) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->mounted;
 }
 
-bool tuh_msc_ready(uint8_t dev_addr)
-{
+bool tuh_msc_ready(uint8_t dev_addr) {
   msch_interface_t* p_msc = get_itf(dev_addr);
-  return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in);
+  return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in) && !usbh_edpt_busy(dev_addr, p_msc->ep_out);
 }
 
 //--------------------------------------------------------------------+
 // PUBLIC API: SCSI COMMAND
 //--------------------------------------------------------------------+
-static inline void cbw_init(msc_cbw_t *cbw, uint8_t lun)
-{
+static inline void cbw_init(msc_cbw_t* cbw, uint8_t lun) {
   tu_memclr(cbw, sizeof(msc_cbw_t));
   cbw->signature = MSC_CBW_SIGNATURE;
   cbw->tag       = 0x54555342; // TUSB
   cbw->lun       = lun;
 }
 
-bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb)
-{
-  msch_interface_t* p_msc = get_itf(dev_addr);
+bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data,
+                          tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
+  msch_interface_t* p_msc = get_itf(daddr);
   TU_VERIFY(p_msc->configured);
 
-  // TODO claim endpoint
+  // claim endpoint
+  TU_VERIFY(usbh_edpt_claim(daddr, p_msc->ep_out));
+  msch_epbuf_t* epbuf = get_epbuf(daddr);
 
-  p_msc->cbw = *cbw;
-  p_msc->stage = MSC_STAGE_CMD;
+  epbuf->cbw = *cbw;
   p_msc->buffer = data;
   p_msc->complete_cb = complete_cb;
+  p_msc->complete_arg = arg;
+  p_msc->stage = MSC_STAGE_CMD;
 
-  TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)));
+  if (!usbh_edpt_xfer(daddr, p_msc->ep_out, (uint8_t*) &epbuf->cbw, sizeof(msc_cbw_t))) {
+    usbh_edpt_release(daddr, p_msc->ep_out);
+    return false;
+  }
 
   return true;
 }
 
-bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb)
-{
-   msch_interface_t* p_msc = get_itf(dev_addr);
-   TU_VERIFY(p_msc->configured);
+bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response,
+                           tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
+  msch_interface_t* p_msc = get_itf(dev_addr);
+  TU_VERIFY(p_msc->configured);
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
@@ -156,11 +161,11 @@ bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_r
   cbw.cmd_len    = sizeof(scsi_read_capacity10_t);
   cbw.command[0] = SCSI_CMD_READ_CAPACITY_10;
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb)
-{
+bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response,
+                     tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
 
@@ -171,18 +176,16 @@ bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* respons
   cbw.dir         = TUSB_DIR_IN_MASK;
   cbw.cmd_len     = sizeof(scsi_inquiry_t);
 
-  scsi_inquiry_t const cmd_inquiry =
-  {
-    .cmd_code     = SCSI_CMD_INQUIRY,
-    .alloc_length = sizeof(scsi_inquiry_resp_t)
+  scsi_inquiry_t const cmd_inquiry = {
+      .cmd_code     = SCSI_CMD_INQUIRY,
+      .alloc_length = sizeof(scsi_inquiry_resp_t)
   };
   memcpy(cbw.command, &cmd_inquiry, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb)
-{
+bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->configured);
 
@@ -190,16 +193,16 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
   cbw_init(&cbw, lun);
 
   cbw.total_bytes = 0;
-  cbw.dir         = TUSB_DIR_OUT;
-  cbw.cmd_len     = sizeof(scsi_test_unit_ready_t);
-  cbw.command[0]  = SCSI_CMD_TEST_UNIT_READY;
-  cbw.command[1]  = lun; // according to wiki TODO need verification
+  cbw.dir        = TUSB_DIR_OUT;
+  cbw.cmd_len    = sizeof(scsi_test_unit_ready_t);
+  cbw.command[0] = SCSI_CMD_TEST_UNIT_READY;
+  cbw.command[1] = lun; // according to wiki TODO need verification
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb, arg);
 }
 
-bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb)
-{
+bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void* response,
+                           tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
 
@@ -207,73 +210,64 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_ms
   cbw.dir         = TUSB_DIR_IN_MASK;
   cbw.cmd_len     = sizeof(scsi_request_sense_t);
 
-  scsi_request_sense_t const cmd_request_sense =
-  {
-    .cmd_code     = SCSI_CMD_REQUEST_SENSE,
-    .alloc_length = 18
+  scsi_request_sense_t const cmd_request_sense = {
+      .cmd_code     = SCSI_CMD_REQUEST_SENSE,
+      .alloc_length = 18
   };
-
   memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, resposne, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb)
-{
+bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void* buffer, uint32_t lba, uint16_t block_count,
+                    tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
- 
-  cbw.total_bytes = block_count*p_msc->capacity[lun].block_size;
-  cbw.dir         = TUSB_DIR_IN_MASK;
-  cbw.cmd_len     = sizeof(scsi_read10_t);
- 
-  scsi_read10_t const cmd_read10 =
-  {
-    .cmd_code    = SCSI_CMD_READ_10,
-    .lba         = tu_htonl(lba),
-    .block_count = tu_htons(block_count)
+
+  cbw.total_bytes = block_count * p_msc->capacity[lun].block_size;
+  cbw.dir = TUSB_DIR_IN_MASK;
+  cbw.cmd_len = sizeof(scsi_read10_t);
+
+  scsi_read10_t const cmd_read10 = {
+      .cmd_code    = SCSI_CMD_READ_10,
+      .lba         = tu_htonl(lba),
+      .block_count = tu_htons(block_count)
   };
- 
   memcpy(cbw.command, &cmd_read10, cbw.cmd_len);
- 
-  return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb);
+
+  return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg);
 }
- 
-bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb)
-{
+
+bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const* buffer, uint32_t lba, uint16_t block_count,
+                     tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
 
-  cbw.total_bytes = block_count*p_msc->capacity[lun].block_size;
+  cbw.total_bytes = block_count * p_msc->capacity[lun].block_size;
   cbw.dir         = TUSB_DIR_OUT;
   cbw.cmd_len     = sizeof(scsi_write10_t);
 
-  scsi_write10_t const cmd_write10 =
-  {
-    .cmd_code    = SCSI_CMD_WRITE_10,
-    .lba         = tu_htonl(lba),
-    .block_count = tu_htons(block_count)
+  scsi_write10_t const cmd_write10 = {
+      .cmd_code    = SCSI_CMD_WRITE_10,
+      .lba         = tu_htonl(lba),
+      .block_count = tu_htons(block_count)
   };
-
   memcpy(cbw.command, &cmd_write10, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, (void*) (uintptr_t) buffer, complete_cb, arg);
 }
 
 #if 0
 // MSC interface Reset (not used now)
-bool tuh_msc_reset(uint8_t dev_addr)
-{
-  tusb_control_request_t const new_request =
-  {
-    .bmRequestType_bit =
-    {
+bool tuh_msc_reset(uint8_t dev_addr) {
+  tusb_control_request_t const new_request = {
+    .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
       .type      = TUSB_REQ_TYPE_CLASS,
       .direction = TUSB_DIR_OUT
@@ -290,65 +284,78 @@ bool tuh_msc_reset(uint8_t dev_addr)
 //--------------------------------------------------------------------+
 // CLASS-USBH API
 //--------------------------------------------------------------------+
-void msch_init(void)
-{
+bool msch_init(void) {
+  TU_LOG_DRV("sizeof(msch_interface_t) = %u\r\n", sizeof(msch_interface_t));
+  TU_LOG_DRV("sizeof(msch_epbuf_t) = %u\r\n", sizeof(msch_epbuf_t));
   tu_memclr(_msch_itf, sizeof(_msch_itf));
+  return true;
 }
 
-void msch_close(uint8_t dev_addr)
-{
-  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
+bool msch_deinit(void) {
+  return true;
+}
 
+void msch_close(uint8_t dev_addr) {
+  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX,);
   msch_interface_t* p_msc = get_itf(dev_addr);
+  TU_VERIFY(p_msc->configured,);
+
+  TU_LOG_DRV("  MSCh close addr = %d\r\n", dev_addr);
 
   // invoke Application Callback
-  if (p_msc->mounted && tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
+  if (p_msc->mounted) {
+    if (tuh_msc_umount_cb) {
+      tuh_msc_umount_cb(dev_addr);
+    }
+  }
 
   tu_memclr(p_msc, sizeof(msch_interface_t));
 }
 
-bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
-{
+bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) {
   msch_interface_t* p_msc = get_itf(dev_addr);
-  msc_cbw_t const * cbw = &p_msc->cbw;
-  msc_csw_t       * csw = &p_msc->csw;
+  msch_epbuf_t* epbuf = get_epbuf(dev_addr);
+  msc_cbw_t const * cbw = &epbuf->cbw;
+  msc_csw_t       * csw = &epbuf->csw;
 
-  switch (p_msc->stage)
-  {
+  switch (p_msc->stage) {
     case MSC_STAGE_CMD:
       // Must be Command Block
-      TU_ASSERT(ep_addr == p_msc->ep_out &&  event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
-
-      if ( cbw->total_bytes && p_msc->buffer )
-      {
+      TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
+      if (cbw->total_bytes && p_msc->buffer) {
         // Data stage if any
         p_msc->stage = MSC_STAGE_DATA;
-
         uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out;
         TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, (uint16_t) cbw->total_bytes));
-      }else
-      {
-        // Status stage
-        p_msc->stage = MSC_STAGE_STATUS;
-        TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
+        break;
       }
-    break;
+
+      TU_ATTR_FALLTHROUGH; // fallthrough to status stage
 
     case MSC_STAGE_DATA:
       // Status stage
       p_msc->stage = MSC_STAGE_STATUS;
-      TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
-    break;
+      TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) csw, (uint16_t) sizeof(msc_csw_t)));
+      break;
 
     case MSC_STAGE_STATUS:
       // SCSI op is complete
       p_msc->stage = MSC_STAGE_IDLE;
 
-      if (p_msc->complete_cb) p_msc->complete_cb(dev_addr, cbw, csw);
-    break;
+      if (p_msc->complete_cb) {
+        tuh_msc_complete_data_t const cb_data = {
+            .cbw = cbw,
+            .csw = csw,
+            .scsi_data = p_msc->buffer,
+            .user_arg = p_msc->complete_arg
+        };
+        p_msc->complete_cb(dev_addr, &cb_data);
+      }
+      break;
 
-    // unknown state
-    default: break;
+      // unknown state
+    default:
+      break;
   }
 
   return true;
@@ -357,39 +364,35 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 //--------------------------------------------------------------------+
 // MSC Enumeration
 //--------------------------------------------------------------------+
+static void config_get_maxlun_complete(tuh_xfer_t* xfer);
+static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
+static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
+static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 
-static void config_get_maxlun_complete (tuh_xfer_t* xfer);
-static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
-static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
-static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
-
-bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
-{
+bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len) {
   (void) rhport;
   TU_VERIFY (MSC_SUBCLASS_SCSI == desc_itf->bInterfaceSubClass &&
-             MSC_PROTOCOL_BOT  == desc_itf->bInterfaceProtocol);
+             MSC_PROTOCOL_BOT == desc_itf->bInterfaceProtocol);
 
   // msc driver length is fixed
-  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
+  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) +
+                                       desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(drv_len <= max_len);
 
   msch_interface_t* p_msc = get_itf(dev_addr);
-  tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(desc_itf);
+  tusb_desc_endpoint_t const* ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(desc_itf);
 
-  for(uint32_t i=0; i<2; i++)
-  {
+  for (uint32_t i = 0; i < 2; i++) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
     TU_ASSERT(tuh_edpt_open(dev_addr, ep_desc));
 
-    if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
-    {
+    if (TUSB_DIR_IN == tu_edpt_dir(ep_desc->bEndpointAddress)) {
       p_msc->ep_in = ep_desc->bEndpointAddress;
-    }else
-    {
+    } else {
       p_msc->ep_out = ep_desc->bEndpointAddress;
     }
 
-    ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(ep_desc);
+    ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(ep_desc);
   }
 
   p_msc->itf_num = desc_itf->bInterfaceNumber;
@@ -397,98 +400,106 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   return true;
 }
 
-bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
-{
-  msch_interface_t* p_msc = get_itf(dev_addr);
+bool msch_set_config(uint8_t daddr, uint8_t itf_num) {
+  msch_interface_t* p_msc = get_itf(daddr);
   TU_ASSERT(p_msc->itf_num == itf_num);
-
   p_msc->configured = true;
 
   //------------- Get Max Lun -------------//
-  TU_LOG2("MSC Get Max Lun\r\n");
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = MSC_REQ_GET_MAX_LUN,
-    .wValue   = 0,
-    .wIndex   = itf_num,
-    .wLength  = 1
+  TU_LOG_DRV("MSC Get Max Lun\r\n");
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_IN
+      },
+      .bRequest = MSC_REQ_GET_MAX_LUN,
+      .wValue   = 0,
+      .wIndex   = itf_num,
+      .wLength  = 1
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = dev_addr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = &p_msc->max_lun,
-    .complete_cb = config_get_maxlun_complete,
-    .user_data    = 0
+  uint8_t* enum_buf = usbh_get_enum_buf();
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = enum_buf,
+      .complete_cb = config_get_maxlun_complete,
+      .user_data    = 0
   };
   TU_ASSERT(tuh_control_xfer(&xfer));
 
   return true;
 }
 
-static void config_get_maxlun_complete (tuh_xfer_t* xfer)
-{
+static void config_get_maxlun_complete(tuh_xfer_t* xfer) {
   uint8_t const daddr = xfer->daddr;
   msch_interface_t* p_msc = get_itf(daddr);
 
-  // STALL means zero
-  p_msc->max_lun = (XFER_RESULT_SUCCESS == xfer->result) ? _msch_buffer[0] : 0;
-  p_msc->max_lun++; // MAX LUN is minus 1 by specs
+  // MAXLUN's response is minus 1 by specs, STALL means 1
+  if (XFER_RESULT_SUCCESS == xfer->result) {
+    uint8_t* enum_buf = usbh_get_enum_buf();
+    p_msc->max_lun = enum_buf[0] + 1;
+  } else {
+    p_msc->max_lun = 1;
+  }
+
+  TU_LOG_DRV("  Max LUN = %u\r\n", p_msc->max_lun);
 
   // TODO multiple LUN support
-  TU_LOG2("SCSI Test Unit Ready\r\n");
+  TU_LOG_DRV("SCSI Test Unit Ready\r\n");
   uint8_t const lun = 0;
-  tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete);
+  tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0);
 }
 
-static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
-{
-  if (csw->status == 0)
-  {
+static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
+  uint8_t* enum_buf = usbh_get_enum_buf();
+
+  if (csw->status == 0) {
     // Unit is ready, read its capacity
-    TU_LOG2("SCSI Read Capacity\r\n");
-    tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete);
-  }else
-  {
+    TU_LOG_DRV("SCSI Read Capacity\r\n");
+    tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) (uintptr_t) enum_buf,
+                          config_read_capacity_complete, 0);
+  } else {
     // Note: During enumeration, some device fails Test Unit Ready and require a few retries
     // with Request Sense to start working !!
     // TODO limit number of retries
-    TU_LOG2("SCSI Request Sense\r\n");
-    TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete));
+    TU_LOG_DRV("SCSI Request Sense\r\n");
+    TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, enum_buf, config_request_sense_complete, 0));
   }
 
   return true;
 }
 
-static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
-{
+static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
+
   TU_ASSERT(csw->status == 0);
-  TU_ASSERT(tuh_msc_test_unit_ready(dev_addr, cbw->lun, config_test_unit_ready_complete));
+  TU_ASSERT(tuh_msc_test_unit_ready(dev_addr, cbw->lun, config_test_unit_ready_complete, 0));
   return true;
 }
 
-static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
-{
+static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
   TU_ASSERT(csw->status == 0);
-
   msch_interface_t* p_msc = get_itf(dev_addr);
+  uint8_t* enum_buf = usbh_get_enum_buf();
 
   // Capacity response field: Block size and Last LBA are both Big-Endian
-  scsi_read_capacity10_resp_t* resp = (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer);
+  scsi_read_capacity10_resp_t* resp = (scsi_read_capacity10_resp_t*) (uintptr_t) enum_buf;
   p_msc->capacity[cbw->lun].block_count = tu_ntohl(resp->last_lba) + 1;
   p_msc->capacity[cbw->lun].block_size  = tu_ntohl(resp->block_size);
 
   // Mark enumeration is complete
   p_msc->mounted = true;
-  if (tuh_msc_mount_cb) tuh_msc_mount_cb(dev_addr);
+  if (tuh_msc_mount_cb) {
+    tuh_msc_mount_cb(dev_addr);
+  }
 
   // notify usbh that driver enumeration is complete
   usbh_driver_set_config_complete(dev_addr, p_msc->itf_num);
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 8d95980f9..09d777066 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_MSC_HOST_H_
-#define _TUSB_MSC_HOST_H_
+#ifndef TUSB_MSC_HOST_H_
+#define TUSB_MSC_HOST_H_
 
 #include "msc.h"
 
@@ -41,7 +41,14 @@
 #define CFG_TUH_MSC_MAXLUN  4
 #endif
 
-typedef bool (*tuh_msc_complete_cb_t)(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
+typedef struct {
+  msc_cbw_t const* cbw; // SCSI command
+  msc_csw_t const* csw; // SCSI status
+  void* scsi_data;      // SCSI Data
+  uintptr_t user_arg;   // user argument
+}tuh_msc_complete_data_t;
+
+typedef bool (*tuh_msc_complete_cb_t)(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 
 //--------------------------------------------------------------------+
 // Application API
@@ -66,33 +73,38 @@ uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun);
 // Perform a full SCSI command (cbw, data, csw) in non-blocking manner.
 // Complete callback is invoked when SCSI op is complete.
 // return true if success, false if there is already pending operation.
-bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb);
+// NOTE: buffer must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
+bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Inquiry command
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb);
+// NOTE: response must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
+bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Test Unit Ready command
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Request Sense 10 command
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb);
+// NOTE: response must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
+bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Read 10 command. Read n blocks starting from LBA to buffer
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb);
+// NOTE: buffer must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
+bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Write 10 command. Write n blocks starting from LBA to device
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb);
+// NOTE: buffer must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
+bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Read Capacity 10 command
 // Complete callback is invoked when SCSI op is complete.
 // Note: during enumeration, host stack already carried out this request. Application can retrieve capacity by
 // simply call tuh_msc_get_block_count() and tuh_msc_get_block_size()
-bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 //------------- Application Callback -------------//
 
@@ -106,9 +118,10 @@ TU_ATTR_WEAK void tuh_msc_umount_cb(uint8_t dev_addr);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 
-void msch_init       (void);
+bool msch_init       (void);
+bool msch_deinit     (void);
 bool msch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
-bool msch_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool msch_set_config (uint8_t daddr, uint8_t itf_num);
 void msch_close      (uint8_t dev_addr);
 bool msch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
 
@@ -116,4 +129,4 @@ bool msch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, ui
  }
 #endif
 
-#endif /* _TUSB_MSC_HOST_H_ */
+#endif
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index 5f316762f..a54e6d662 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Peter Lawrence
@@ -35,13 +35,18 @@
 #include "net_device.h"
 #include "rndis_protocol.h"
 
-void rndis_class_set_handler(uint8_t *data, int size); /* found in ./misc/networking/rndis_reports.c */
+extern void rndis_class_set_handler(uint8_t *data, int size); /* found in ./misc/networking/rndis_reports.c */
+
+#define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t)
+#define CFG_TUD_NET_PACKET_SUFFIX_LEN 0
+
+#define NETD_PACKET_SIZE  (CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN)
+#define NETD_CONTROL_SIZE 120
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;      // Index number of Management Interface, +1 for Data Interface
   uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active
 
@@ -51,98 +56,67 @@ typedef struct
 
   bool ecm_mode;
 
-  // Endpoint descriptor use to open/close when receving SetInterface
+  // Endpoint descriptor use to open/close when receiving SetInterface
   // TODO since configuration descriptor may not be long-lived memory, we should
   // keep a copy of endpoint attribute instead
   uint8_t const * ecm_desc_epdata;
-
 } netd_interface_t;
 
-#define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t)
-#define CFG_TUD_NET_PACKET_SUFFIX_LEN 0
-
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
-
-struct ecm_notify_struct
-{
+typedef struct ecm_notify_struct {
   tusb_control_request_t header;
   uint32_t downlink, uplink;
-};
+} ecm_notify_t;
 
-static const struct ecm_notify_struct ecm_notify_nc =
-{
-  .header = {
-    .bmRequestType = 0xA1,
-    .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */,
-    .wValue = 1 /* Connected */,
-    .wLength = 0,
-  },
-};
+typedef struct {
+  TUD_EPBUF_DEF(rx, NETD_PACKET_SIZE);
+  TUD_EPBUF_DEF(tx, NETD_PACKET_SIZE);
 
-static const struct ecm_notify_struct ecm_notify_csc =
-{
-  .header = {
-    .bmRequestType = 0xA1,
-    .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */,
-    .wLength = 8,
-  },
-  .downlink = 9728000,
-  .uplink = 9728000,
-};
-
-// TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static union
-{
-  uint8_t rndis_buf[120];
-  struct ecm_notify_struct ecm_buf;
-} notify;
+  TUD_EPBUF_DEF(notify, sizeof(ecm_notify_t));
+  TUD_EPBUF_DEF(ctrl, NETD_CONTROL_SIZE);
+} netd_epbuf_t;
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-// TODO remove CFG_TUSB_MEM_SECTION
-CFG_TUSB_MEM_SECTION static netd_interface_t _netd_itf;
-
+static netd_interface_t _netd_itf;
+CFG_TUD_MEM_SECTION static netd_epbuf_t _netd_epbuf;
 static bool can_xmit;
 
-void tud_network_recv_renew(void)
-{
-  usbd_edpt_xfer(0, _netd_itf.ep_out, received, sizeof(received));
+void tud_network_recv_renew(void) {
+  usbd_edpt_xfer(0, _netd_itf.ep_out, _netd_epbuf.rx, NETD_PACKET_SIZE);
 }
 
-static void do_in_xfer(uint8_t *buf, uint16_t len)
-{
+static void do_in_xfer(uint8_t *buf, uint16_t len) {
   can_xmit = false;
   usbd_edpt_xfer(0, _netd_itf.ep_in, buf, len);
 }
 
-void netd_report(uint8_t *buf, uint16_t len)
-{
-  uint8_t const rhport = 0;
+void netd_report(uint8_t *buf, uint16_t len) {
+  const uint8_t rhport = 0;
+  len = tu_min16(len, sizeof(ecm_notify_t));
 
-  // skip if previous report not yet acknowledged by host
-  if ( usbd_edpt_busy(rhport, _netd_itf.ep_notif) ) return;
-  usbd_edpt_xfer(rhport, _netd_itf.ep_notif, buf, len);
+  TU_VERIFY(usbd_edpt_claim(rhport, _netd_itf.ep_notif), );
+  memcpy(_netd_epbuf.notify, buf, len);
+  usbd_edpt_xfer(rhport, _netd_itf.ep_notif, _netd_epbuf.notify, len);
 }
 
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void netd_init(void)
-{
+void netd_init(void) {
   tu_memclr(&_netd_itf, sizeof(_netd_itf));
 }
 
-void netd_reset(uint8_t rhport)
-{
-  (void) rhport;
+bool netd_deinit(void) {
+  return true;
+}
 
+void netd_reset(uint8_t rhport) {
+  (void) rhport;
   netd_init();
 }
 
-uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
+uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) {
   bool const is_rndis = (TUD_RNDIS_ITF_CLASS    == itf_desc->bInterfaceClass    &&
                          TUD_RNDIS_ITF_SUBCLASS == itf_desc->bInterfaceSubClass &&
                          TUD_RNDIS_ITF_PROTOCOL == itf_desc->bInterfaceProtocol);
@@ -166,21 +140,19 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
   uint8_t const * p_desc = tu_desc_next( itf_desc );
 
   // Communication Functional Descriptors
-  while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
-  {
+  while (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len) {
     drv_len += tu_desc_len(p_desc);
     p_desc   = tu_desc_next(p_desc);
   }
 
   // notification endpoint (if any)
-  if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
-  {
-    TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 );
+  if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) {
+    TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0);
 
-    _netd_itf.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+    _netd_itf.ep_notif = ((tusb_desc_endpoint_t const*)p_desc)->bEndpointAddress;
 
     drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
+    p_desc = tu_desc_next(p_desc);
   }
 
   //------------- Data Interface -------------//
@@ -190,27 +162,24 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
   //   - 1 : IN & OUT endpoints for active networking
   TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0);
 
-  do
-  {
+  do {
     tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc;
     TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0);
 
     drv_len += tu_desc_len(p_desc);
     p_desc   = tu_desc_next(p_desc);
-  }while( _netd_itf.ecm_mode && (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len) );
+  } while (_netd_itf.ecm_mode && (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len));
 
   // Pair of endpoints
   TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0);
 
-  if ( _netd_itf.ecm_mode )
-  {
+  if (_netd_itf.ecm_mode) {
     // ECM by default is in-active, save the endpoint attribute
     // to open later when received setInterface
     _netd_itf.ecm_desc_epdata = p_desc;
-  }else
-  {
+  } else {
     // Open endpoint pair for RNDIS
-    TU_ASSERT( usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in), 0 );
+    TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in), 0);
 
     tud_network_init_cb();
 
@@ -226,38 +195,50 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
   return drv_len;
 }
 
-static void ecm_report(bool nc)
-{
-  notify.ecm_buf = (nc) ? ecm_notify_nc : ecm_notify_csc;
-  notify.ecm_buf.header.wIndex = _netd_itf.itf_num;
-  netd_report((uint8_t *)&notify.ecm_buf, (nc) ? sizeof(notify.ecm_buf.header) : sizeof(notify.ecm_buf));
+static void ecm_report(bool nc) {
+  const ecm_notify_t ecm_notify_nc = {
+    .header = {
+      .bmRequestType = 0xA1,
+      .bRequest = 0, /* NETWORK_CONNECTION aka NetworkConnection */
+      .wValue = 1,   /* Connected */
+      .wLength = 0,
+    },
+  };
+
+  const ecm_notify_t ecm_notify_csc = {
+    .header = {
+      .bmRequestType = 0xA1,
+      .bRequest = 0x2A, /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */
+      .wLength = 8,
+    },
+    .downlink = 9728000,
+    .uplink = 9728000,
+  };
+
+  ecm_notify_t notify = (nc) ? ecm_notify_nc : ecm_notify_csc;
+  notify.header.wIndex = _netd_itf.itf_num;
+  netd_report((uint8_t *)&notify, (nc) ? sizeof(notify.header) : sizeof(notify));
 }
 
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
-  if ( stage == CONTROL_STAGE_SETUP )
-  {
-    switch ( request->bmRequestType_bit.type )
-    {
+bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) {
+  if (stage == CONTROL_STAGE_SETUP) {
+    switch (request->bmRequestType_bit.type) {
       case TUSB_REQ_TYPE_STANDARD:
-        switch ( request->bRequest )
-        {
-          case TUSB_REQ_GET_INTERFACE:
-          {
-            uint8_t const req_itfnum = (uint8_t) request->wIndex;
+        switch (request->bRequest) {
+          case TUSB_REQ_GET_INTERFACE: {
+            uint8_t const req_itfnum = (uint8_t)request->wIndex;
             TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum);
 
             tud_control_xfer(rhport, request, &_netd_itf.itf_data_alt, 1);
           }
           break;
 
-          case TUSB_REQ_SET_INTERFACE:
-          {
-            uint8_t const req_itfnum = (uint8_t) request->wIndex;
-            uint8_t const req_alt    = (uint8_t) request->wValue;
+          case TUSB_REQ_SET_INTERFACE: {
+            uint8_t const req_itfnum = (uint8_t)request->wIndex;
+            uint8_t const req_alt = (uint8_t)request->wValue;
 
             // Only valid for Data Interface with Alternate is either 0 or 1
             TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum && req_alt < 2);
@@ -267,14 +248,14 @@ bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
 
             _netd_itf.itf_data_alt = req_alt;
 
-            if ( _netd_itf.itf_data_alt )
-            {
+            if (_netd_itf.itf_data_alt) {
               // TODO since we don't actually close endpoint
               // hack here to not re-open it
-              if ( _netd_itf.ep_in == 0 && _netd_itf.ep_out == 0 )
-              {
+              if (_netd_itf.ep_in == 0 && _netd_itf.ep_out == 0) {
                 TU_ASSERT(_netd_itf.ecm_desc_epdata);
-                TU_ASSERT( usbd_open_edpt_pair(rhport, _netd_itf.ecm_desc_epdata, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in) );
+                TU_ASSERT(
+                  usbd_open_edpt_pair(rhport, _netd_itf.ecm_desc_epdata, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &
+                    _netd_itf.ep_in));
 
                 // TODO should be merge with RNDIS's after endpoint opened
                 // Also should have opposite callback for application to disable network !!
@@ -282,8 +263,7 @@ bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
                 can_xmit = true; // we are ready to transmit a packet
                 tud_network_recv_renew(); // prepare for incoming packets
               }
-            }else
-            {
+            } else {
               // TODO close the endpoint pair
               // For now pretend that we did, this should have no harm since host won't try to
               // communicate with the endpoints again
@@ -297,50 +277,39 @@ bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
           // unsupported request
           default: return false;
         }
-      break;
+        break;
 
       case TUSB_REQ_TYPE_CLASS:
-        TU_VERIFY (_netd_itf.itf_num == request->wIndex);
+        TU_VERIFY(_netd_itf.itf_num == request->wIndex);
 
-        if (_netd_itf.ecm_mode)
-        {
+        if (_netd_itf.ecm_mode) {
           /* the only required CDC-ECM Management Element Request is SetEthernetPacketFilter */
-          if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest)
-          {
+          if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest) {
             tud_control_xfer(rhport, request, NULL, 0);
             ecm_report(true);
           }
-        }
-        else
-        {
-          if (request->bmRequestType_bit.direction == TUSB_DIR_IN)
-          {
-            rndis_generic_msg_t *rndis_msg = (rndis_generic_msg_t *) ((void*) notify.rndis_buf);
+        } else {
+          if (request->bmRequestType_bit.direction == TUSB_DIR_IN) {
+            rndis_generic_msg_t* rndis_msg = (rndis_generic_msg_t*)((void*)_netd_epbuf.ctrl);
             uint32_t msglen = tu_le32toh(rndis_msg->MessageLength);
-            TU_ASSERT(msglen <= sizeof(notify.rndis_buf));
-            tud_control_xfer(rhport, request, notify.rndis_buf, (uint16_t) msglen);
-          }
-          else
-          {
-            tud_control_xfer(rhport, request, notify.rndis_buf, (uint16_t) sizeof(notify.rndis_buf));
+            TU_ASSERT(msglen <= NETD_CONTROL_SIZE);
+            tud_control_xfer(rhport, request, _netd_epbuf.ctrl, (uint16_t)msglen);
+          } else {
+            tud_control_xfer(rhport, request, _netd_epbuf.ctrl, NETD_CONTROL_SIZE);
           }
         }
-      break;
+        break;
 
       // unsupported request
       default: return false;
     }
-  }
-  else if ( stage == CONTROL_STAGE_DATA )
-  {
+  } else if (stage == CONTROL_STAGE_DATA) {
     // Handle RNDIS class control OUT only
     if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS &&
-        request->bmRequestType_bit.direction == TUSB_DIR_OUT   &&
-        _netd_itf.itf_num == request->wIndex)
-    {
-      if ( !_netd_itf.ecm_mode )
-      {
-        rndis_class_set_handler(notify.rndis_buf, request->wLength);
+        request->bmRequestType_bit.direction == TUSB_DIR_OUT &&
+        _netd_itf.itf_num == request->wIndex) {
+      if (!_netd_itf.ecm_mode) {
+        rndis_class_set_handler(_netd_epbuf.ctrl, request->wLength);
       }
     }
   }
@@ -348,92 +317,77 @@ bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
   return true;
 }
 
-static void handle_incoming_packet(uint32_t len)
-{
-  uint8_t *pnt = received;
+static void handle_incoming_packet(uint32_t len) {
+  uint8_t* pnt = _netd_epbuf.rx;
   uint32_t size = 0;
 
-  if (_netd_itf.ecm_mode)
-  {
+  if (_netd_itf.ecm_mode) {
     size = len;
-  }
-  else
-  {
-    rndis_data_packet_t *r = (rndis_data_packet_t *) ((void*) pnt);
-    if (len >= sizeof(rndis_data_packet_t))
-      if ( (r->MessageType == REMOTE_NDIS_PACKET_MSG) && (r->MessageLength <= len))
-        if ( (r->DataOffset + offsetof(rndis_data_packet_t, DataOffset) + r->DataLength) <= len)
-        {
-          pnt = &received[r->DataOffset + offsetof(rndis_data_packet_t, DataOffset)];
+  } else {
+    rndis_data_packet_t* r = (rndis_data_packet_t*)((void*)pnt);
+    if (len >= sizeof(rndis_data_packet_t)) {
+      if ((r->MessageType == REMOTE_NDIS_PACKET_MSG) && (r->MessageLength <= len)) {
+        if ((r->DataOffset + offsetof(rndis_data_packet_t, DataOffset) + r->DataLength) <= len) {
+          pnt = &_netd_epbuf.rx[r->DataOffset + offsetof(rndis_data_packet_t, DataOffset)];
           size = r->DataLength;
         }
+      }
+    }
   }
 
-  if (!tud_network_recv_cb(pnt, (uint16_t) size))
-  {
+  if (!tud_network_recv_cb(pnt, (uint16_t)size)) {
     /* if a buffer was never handled by user code, we must renew on the user's behalf */
     tud_network_recv_renew();
   }
 }
 
-bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
-  (void) rhport;
-  (void) result;
+bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
+  (void)rhport;
+  (void)result;
 
   /* new packet received */
-  if ( ep_addr == _netd_itf.ep_out )
-  {
+  if (ep_addr == _netd_itf.ep_out) {
     handle_incoming_packet(xferred_bytes);
   }
 
   /* data transmission finished */
-  if ( ep_addr == _netd_itf.ep_in )
-  {
+  if (ep_addr == _netd_itf.ep_in) {
     /* TinyUSB requires the class driver to implement ZLP (since ZLP usage is class-specific) */
 
-    if ( xferred_bytes && (0 == (xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE)) )
-    {
+    if (xferred_bytes && (0 == (xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE))) {
       do_in_xfer(NULL, 0); /* a ZLP is needed */
-    }
-    else
-    {
+    } else {
       /* we're finally finished */
       can_xmit = true;
     }
   }
 
-  if ( _netd_itf.ecm_mode && (ep_addr == _netd_itf.ep_notif) )
-  {
-    if (sizeof(notify.ecm_buf.header) == xferred_bytes) ecm_report(false);
+  if (_netd_itf.ecm_mode && (ep_addr == _netd_itf.ep_notif)) {
+    if (sizeof(tusb_control_request_t) == xferred_bytes) {
+      ecm_report(false);
+    }
   }
 
   return true;
 }
 
-bool tud_network_can_xmit(uint16_t size)
-{
+bool tud_network_can_xmit(uint16_t size) {
   (void)size;
-
   return can_xmit;
 }
 
-void tud_network_xmit(void *ref, uint16_t arg)
-{
-  uint8_t *data;
-  uint16_t len;
-
-  if (!can_xmit)
+void tud_network_xmit(void *ref, uint16_t arg) {
+  if (!can_xmit) {
     return;
+  }
 
-  len = (_netd_itf.ecm_mode) ? 0 : CFG_TUD_NET_PACKET_PREFIX_LEN;
-  data = transmitted + len;
+  uint16_t len = (_netd_itf.ecm_mode) ? 0 : CFG_TUD_NET_PACKET_PREFIX_LEN;
+  uint8_t* data = _netd_epbuf.tx + len;
 
   len += tud_network_xmit_cb(data, ref, arg);
 
-  if (!_netd_itf.ecm_mode)
-  {
-    rndis_data_packet_t *hdr = (rndis_data_packet_t *) ((void*) transmitted);
+  if (!_netd_itf.ecm_mode) {
+    rndis_data_packet_t *hdr = (rndis_data_packet_t *) ((void*) _netd_epbuf.tx);
     memset(hdr, 0, sizeof(rndis_data_packet_t));
     hdr->MessageType = REMOTE_NDIS_PACKET_MSG;
     hdr->MessageLength = len;
@@ -441,7 +395,7 @@ void tud_network_xmit(void *ref, uint16_t arg)
     hdr->DataLength = len - sizeof(rndis_data_packet_t);
   }
 
-  do_in_xfer(transmitted, len);
+  do_in_xfer(_netd_epbuf.tx, len);
 }
 
 #endif
diff --git a/src/class/net/ncm.h b/src/class/net/ncm.h
index 96ba11fbc..0245a87f2 100644
--- a/src/class/net/ncm.h
+++ b/src/class/net/ncm.h
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ * Copyright (c) 2024, Hardy Griech
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,22 +25,58 @@
  * This file is part of the TinyUSB stack.
  */
 
-
 #ifndef _TUSB_NCM_H_
 #define _TUSB_NCM_H_
 
 #include "common/tusb_common.h"
 
-#ifdef __cplusplus
- extern "C" {
+// NTB buffers size for reception side, must be >> MTU to avoid TCP retransmission (driver issue ?)
+// Linux use 2048 as minimal size
+#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
+  #define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200
 #endif
 
-// Table 4.3 Data Class Interface Protocol Codes
-typedef enum
-{
-  NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK = 0x01
-} ncm_data_interface_protocol_code_t;
+// NTB buffers size for reception side, must be > MTU
+// Linux use 2048 as minimal size
+#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
+  #define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200
+#endif
 
+// Number of NTB buffers for reception side
+// Depending on the configuration, this parameter could be increased with the cost of additional RAM requirements
+// On Full-Speed (RP2040) :
+//    1  - good performance
+//    2  - up to 30% more performance with iperf with small packets
+//    >2 - no performance gain
+// On High-Speed (STM32F7) :
+//    No performance gain
+#ifndef CFG_TUD_NCM_OUT_NTB_N
+  #define CFG_TUD_NCM_OUT_NTB_N 1
+#endif
+
+// Number of NTB buffers for transmission side
+// Depending on the configuration, this parameter could be increased with the cost of additional RAM requirements
+// On Full-Speed (RP2040) :
+//    1 - good performance but SystemView shows lost events (on load test)
+//    2 - up to 50% more performance with iperf with small packets, "tud_network_can_xmit: request blocked"
+//        happens from time to time with SystemView
+//    3 - "tud_network_can_xmit: request blocked" never happens
+//    >3 - no performance gain
+// On High-Speed (STM32F7) :
+//    No performance gain
+#ifndef CFG_TUD_NCM_IN_NTB_N
+  #define CFG_TUD_NCM_IN_NTB_N 1
+#endif
+
+// How many datagrams it is allowed to put into an NTB for transmission side
+#ifndef CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB
+  #define CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB 8
+#endif
+
+// This tells the host how many datagrams it is allowed to put into an NTB
+#ifndef CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB
+  #define CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB 6
+#endif
 
 // Table 6.2 Class-Specific Request Codes for Network Control Model subclass
 typedef enum
@@ -62,8 +99,66 @@ typedef enum
   NCM_SET_CRC_MODE                                 = 0x8A,
 } ncm_request_code_t;
 
-#ifdef __cplusplus
- }
-#endif
+#define NTH16_SIGNATURE 0x484D434E
+#define NDP16_SIGNATURE_NCM0 0x304D434E
+#define NDP16_SIGNATURE_NCM1 0x314D434E
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t wLength;
+  uint16_t bmNtbFormatsSupported;
+  uint32_t dwNtbInMaxSize;
+  uint16_t wNdbInDivisor;
+  uint16_t wNdbInPayloadRemainder;
+  uint16_t wNdbInAlignment;
+  uint16_t wReserved;
+  uint32_t dwNtbOutMaxSize;
+  uint16_t wNdbOutDivisor;
+  uint16_t wNdbOutPayloadRemainder;
+  uint16_t wNdbOutAlignment;
+  uint16_t wNtbOutMaxDatagrams;
+} ntb_parameters_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t dwSignature;
+  uint16_t wHeaderLength;
+  uint16_t wSequence;
+  uint16_t wBlockLength;
+  uint16_t wNdpIndex;
+} nth16_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t wDatagramIndex;
+  uint16_t wDatagramLength;
+} ndp16_datagram_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t dwSignature;
+  uint16_t wLength;
+  uint16_t wNextNdpIndex;
+  //ndp16_datagram_t datagram[];
+} ndp16_t;
+
+typedef union TU_ATTR_PACKED {
+  struct {
+    nth16_t nth;
+    ndp16_t ndp;
+    ndp16_datagram_t ndp_datagram[CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB + 1];
+  };
+  uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
+} xmit_ntb_t;
+
+typedef union TU_ATTR_PACKED {
+  struct {
+    nth16_t nth;
+    // only the header is at a guaranteed position
+  };
+  uint8_t data[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+} recv_ntb_t;
+
+typedef struct {
+  tusb_control_request_t header;
+  uint32_t downlink;
+  uint32_t uplink;
+} ncm_notify_t;
 
 #endif
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 00892b49c..f9fda0698 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -1,9 +1,10 @@
 /*
  * The MIT License (MIT)
  *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2024 Hardy Griech
  * Copyright (c) 2020 Jacob Berg Potter
  * Copyright (c) 2020 Peter Lawrence
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -26,486 +27,918 @@
  * This file is part of the TinyUSB stack.
  */
 
+/**
+ * Small Glossary (from the spec)
+ * --------------
+ * Datagram - A collection of bytes forming a single item of information, passed as a unit from source to destination.
+ * NCM      - Network Control Model
+ * NDP      - NCM Datagram Pointer: NTB structure that delineates Datagrams (typically Ethernet frames) within an NTB
+ * NTB      - NCM Transfer Block: a data structure for efficient USB encapsulation of one or more datagrams
+ *            Each NTB is designed to be a single USB transfer
+ * NTH      - NTB Header: a data structure at the front of each NTB, which provides the information needed to validate
+ *            the NTB and begin decoding
+ *
+ * Some explanations
+ * -----------------
+ * - rhport        is the USB port of the device, in most cases "0"
+ * - itf_data_alt  if != 0 -> data xmit/recv are allowed (see spec)
+ * - ep_in         IN endpoints take data from the device intended to go in to the host (the device transmits)
+ * - ep_out        OUT endpoints send data out of the host to the device (the device receives)
+ */
+
 #include "tusb_option.h"
 
-#if ( CFG_TUD_ENABLED && CFG_TUD_NCM )
+#if (CFG_TUD_ENABLED && CFG_TUD_NCM)
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
+
+#include "ncm.h"
 #include "net_device.h"
 
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_NCM_LOG_LEVEL
+  #define CFG_TUD_NCM_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
 
-#define NTH16_SIGNATURE      0x484D434E
-#define NDP16_SIGNATURE_NCM0 0x304D434E
-#define NDP16_SIGNATURE_NCM1 0x314D434E
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_NCM_LOG_LEVEL, __VA_ARGS__)
 
-typedef struct TU_ATTR_PACKED
-{
-  uint16_t wLength;
-  uint16_t bmNtbFormatsSupported;
-  uint32_t dwNtbInMaxSize;
-  uint16_t wNdbInDivisor;
-  uint16_t wNdbInPayloadRemainder;
-  uint16_t wNdbInAlignment;
-  uint16_t wReserved;
-  uint32_t dwNtbOutMaxSize;
-  uint16_t wNdbOutDivisor;
-  uint16_t wNdbOutPayloadRemainder;
-  uint16_t wNdbOutAlignment;
-  uint16_t wNtbOutMaxDatagrams;
-} ntb_parameters_t;
+// Alignment must be 4
+#define TUD_NCM_ALIGNMENT   4
+// calculate alignment of xmit datagrams within an NTB
+#define XMIT_ALIGN_OFFSET(x) ((TUD_NCM_ALIGNMENT - ((x) & (TUD_NCM_ALIGNMENT - 1))) & (TUD_NCM_ALIGNMENT - 1))
 
-typedef struct TU_ATTR_PACKED
-{
-  uint32_t dwSignature;
-  uint16_t wHeaderLength;
-  uint16_t wSequence;
-  uint16_t wBlockLength;
-  uint16_t wNdpIndex;
-} nth16_t;
+//-----------------------------------------------------------------------------
+//
+// Module global things
+//
+#define XMIT_NTB_N CFG_TUD_NCM_IN_NTB_N
+#define RECV_NTB_N CFG_TUD_NCM_OUT_NTB_N
 
-typedef struct TU_ATTR_PACKED
-{
-  uint16_t wDatagramIndex;
-  uint16_t wDatagramLength;
-} ndp16_datagram_t;
+typedef struct {
+  // general
+  uint8_t ep_in;        // endpoint for outgoing datagrams (naming is a little bit confusing)
+  uint8_t ep_out;       // endpoint for incoming datagrams (naming is a little bit confusing)
+  uint8_t ep_notif;     // endpoint for notifications
+  uint8_t itf_num;      // interface number
+  uint8_t itf_data_alt; // ==0 -> no endpoints, i.e. no network traffic, ==1 -> normal operation with two endpoints (spec, chapter 5.3)
+  uint8_t rhport;       // storage of \a rhport because some callbacks are done without it
 
-typedef struct TU_ATTR_PACKED
-{
-  uint32_t dwSignature;
-  uint16_t wLength;
-  uint16_t wNextNdpIndex;
-  ndp16_datagram_t datagram[];
-} ndp16_t;
+  // recv handling
+  recv_ntb_t *recv_free_ntb[RECV_NTB_N];                // free list of recv NTBs
+  recv_ntb_t *recv_ready_ntb[RECV_NTB_N];               // NTBs waiting for transmission to glue logic
+  recv_ntb_t *recv_tinyusb_ntb;                         // buffer for the running transfer TinyUSB -> driver
+  recv_ntb_t *recv_glue_ntb;                            // buffer for the running transfer driver -> glue logic
+  uint16_t recv_glue_ntb_datagram_ndx;                  // index into \a recv_glue_ntb_datagram
 
-typedef union TU_ATTR_PACKED {
-  struct {
-    nth16_t nth;
-    ndp16_t ndp;
-  };
-  uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
-} transmit_ntb_t;
-
-struct ecm_notify_struct
-{
-  tusb_control_request_t header;
-  uint32_t downlink, uplink;
-};
-
-typedef struct
-{
-  uint8_t itf_num;      // Index number of Management Interface, +1 for Data Interface
-  uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active
-
-  uint8_t ep_notif;
-  uint8_t ep_in;
-  uint8_t ep_out;
-
-  const ndp16_t *ndp;
-  uint8_t num_datagrams, current_datagram_index;
+  // xmit handling
+  xmit_ntb_t *xmit_free_ntb[XMIT_NTB_N];                // free list of xmit NTBs
+  xmit_ntb_t *xmit_ready_ntb[XMIT_NTB_N];               // NTBs waiting for transmission to TinyUSB
+  xmit_ntb_t *xmit_tinyusb_ntb;                         // buffer for the running transfer driver -> TinyUSB
+  xmit_ntb_t *xmit_glue_ntb;                            // buffer for the running transfer glue logic -> driver
+  uint16_t xmit_sequence;                               // NTB sequence counter
+  uint16_t xmit_glue_ntb_datagram_ndx;                  // index into \a xmit_glue_ntb_datagram
 
+  // notification handling
   enum {
-    REPORT_SPEED,
-    REPORT_CONNECTED,
-    REPORT_DONE
-  } report_state;
-  bool report_pending;
-
-  uint8_t  current_ntb;           // Index in transmit_ntb[] that is currently being filled with datagrams
-  uint8_t  datagram_count;        // Number of datagrams in transmit_ntb[current_ntb]
-  uint16_t next_datagram_offset;  // Offset in transmit_ntb[current_ntb].data to place the next datagram
-  uint16_t ntb_in_size;           // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE
-  uint8_t  max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
-
-  uint16_t nth_sequence;          // Sequence number counter for transmitted NTBs
-
-  bool transferring;
+    NOTIFICATION_SPEED,
+    NOTIFICATION_CONNECTED,
+    NOTIFICATION_DONE
+  } notification_xmit_state;                            // state of notification transmission
+  bool notification_xmit_is_running;                    // notification is currently transmitted
 
+  // misc
+  bool tud_network_recv_renew_active;                   // tud_network_recv_renew() is active (avoid recursive invocations)
+  bool tud_network_recv_renew_process_again;            // tud_network_recv_renew() should process again
 } ncm_interface_t;
 
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
+typedef struct {
+  struct {
+    TUD_EPBUF_TYPE_DEF(recv_ntb_t, ntb);
+  } recv[RECV_NTB_N];
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parameters = {
-    .wLength                 = sizeof(ntb_parameters_t),
-    .bmNtbFormatsSupported   = 0x01,
-    .dwNtbInMaxSize          = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
-    .wNdbInDivisor           = 4,
-    .wNdbInPayloadRemainder  = 0,
-    .wNdbInAlignment         = CFG_TUD_NCM_ALIGNMENT,
-    .wReserved               = 0,
-    .dwNtbOutMaxSize         = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
-    .wNdbOutDivisor          = 4,
-    .wNdbOutPayloadRemainder = 0,
-    .wNdbOutAlignment        = CFG_TUD_NCM_ALIGNMENT,
-    .wNtbOutMaxDatagrams     = 0
-};
+  struct {
+    TUD_EPBUF_TYPE_DEF(xmit_ntb_t, ntb);
+  } xmit[XMIT_NTB_N];
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static transmit_ntb_t transmit_ntb[2];
-
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+  TUD_EPBUF_TYPE_DEF(ncm_notify_t, epnotif);
+} ncm_epbuf_t;
 
 static ncm_interface_t ncm_interface;
+CFG_TUD_MEM_SECTION static ncm_epbuf_t ncm_epbuf;
 
-/*
- * Set up the NTB state in ncm_interface to be ready to add datagrams.
+/**
+ * This is the NTB parameter structure
+ *
+ * \attention
+ *     We are lucky, that byte order is correct
  */
-static void ncm_prepare_for_tx(void) {
-  ncm_interface.datagram_count = 0;
-  // datagrams start after all the headers
-  ncm_interface.next_datagram_offset = sizeof(nth16_t) + sizeof(ndp16_t)
-      + ((CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + 1) * sizeof(ndp16_datagram_t));
-}
+TU_ATTR_ALIGNED(4) static const ntb_parameters_t ntb_parameters = {
+  .wLength                  = sizeof(ntb_parameters_t),
+  .bmNtbFormatsSupported    = 0x01,// 16-bit NTB supported
+  .dwNtbInMaxSize           = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
+  .wNdbInDivisor            = 1,
+  .wNdbInPayloadRemainder   = 0,
+  .wNdbInAlignment          = TUD_NCM_ALIGNMENT,
+  .wReserved                = 0,
+  .dwNtbOutMaxSize          = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
+  .wNdbOutDivisor           = 1,
+  .wNdbOutPayloadRemainder  = 0,
+  .wNdbOutAlignment         = TUD_NCM_ALIGNMENT,
+  .wNtbOutMaxDatagrams      = CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB,
+};
 
-/*
- * If not already transmitting, start sending the current NTB to the host and swap buffers
- * to start filling the other one with datagrams.
+// Some confusing remarks about wNtbOutMaxDatagrams...
+//      ==1 -> SystemView packets/s goes up to 2000 and events are lost during startup
+//      ==0 -> SystemView runs fine, iperf shows in wireshark a lot of error
+//      ==6 -> SystemView runs fine, iperf also
+//      >6  -> iperf starts to show errors
+//      -> 6 seems to be the best value.  Why?  Don't know, perhaps only on my system?
+//
+//      iperf:    for MSS in 100 200 400 800 1200 1450 1500; do iperf -c 192.168.14.1 -e -i 1 -M $MSS -l 8192 -P 1; sleep 2; done
+//      sysview:  SYSTICKS_PER_SEC=35000, IDLE_US=1000, PRINT_MOD=1000
+//
+
+//-----------------------------------------------------------------------------
+//
+// everything about notifications
+//
+
+/**
+ * Transmit next notification to the host (if appropriate).
+ * Notifications are transferred to the host once during connection setup.
  */
-static void ncm_start_tx(void) {
-  if (ncm_interface.transferring) {
+static void notification_xmit(uint8_t rhport, bool force_next) {
+  TU_LOG_DRV("notification_xmit(%d, %d) - %d %d\n", force_next, rhport, ncm_interface.notification_xmit_state, ncm_interface.notification_xmit_is_running);
+
+  if (!force_next && ncm_interface.notification_xmit_is_running) {
     return;
   }
 
-  transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
-  size_t ntb_length = ncm_interface.next_datagram_offset;
-
-  // Fill in NTB header
-  ntb->nth.dwSignature = NTH16_SIGNATURE;
-  ntb->nth.wHeaderLength = sizeof(nth16_t);
-  ntb->nth.wSequence = ncm_interface.nth_sequence++;
-  ntb->nth.wBlockLength = ntb_length;
-  ntb->nth.wNdpIndex = sizeof(nth16_t);
-
-  // Fill in NDP16 header and terminator
-  ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0;
-  ntb->ndp.wLength = sizeof(ndp16_t) + (ncm_interface.datagram_count + 1) * sizeof(ndp16_datagram_t);
-  ntb->ndp.wNextNdpIndex = 0;
-  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = 0;
-  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = 0;
-
-  // Kick off an endpoint transfer
-  usbd_edpt_xfer(0, ncm_interface.ep_in, ntb->data, ntb_length);
-  ncm_interface.transferring = true;
-
-  // Swap to the other NTB and clear it out
-  ncm_interface.current_ntb = 1 - ncm_interface.current_ntb;
-  ncm_prepare_for_tx();
-}
-
-static struct ecm_notify_struct ncm_notify_connected =
-{
-    .header = {
+  if (ncm_interface.notification_xmit_state == NOTIFICATION_SPEED) {
+    TU_LOG_DRV("  NOTIFICATION_SPEED\n");
+    ncm_notify_t notify_speed_change = {
+      .header = {
         .bmRequestType_bit = {
           .recipient = TUSB_REQ_RCPT_INTERFACE,
-          .type      = TUSB_REQ_TYPE_CLASS,
-          .direction = TUSB_DIR_IN
-        },
-        .bRequest      = CDC_NOTIF_NETWORK_CONNECTION,
-        .wValue        = 1 /* Connected */,
-        .wLength       = 0,
-    },
-};
-
-static struct ecm_notify_struct ncm_notify_speed_change =
-{
-    .header = {
-        .bmRequestType_bit = {
-          .recipient = TUSB_REQ_RCPT_INTERFACE,
-          .type      = TUSB_REQ_TYPE_CLASS,
+          .type = TUSB_REQ_TYPE_CLASS,
           .direction = TUSB_DIR_IN
         },
         .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE,
-        .wLength = 8,
-    },
-    .downlink = 10000000,
-    .uplink = 10000000,
-};
+        .wValue = 0,
+        .wIndex = ncm_interface.itf_num,
+        .wLength = 8
+      }
+    };
+    if (tud_speed_get() == TUSB_SPEED_HIGH) {
+      notify_speed_change.downlink = 480000000;
+      notify_speed_change.uplink = 480000000;
+    } else {
+      notify_speed_change.downlink = 12000000;
+      notify_speed_change.uplink = 12000000;
+    }
 
-void tud_network_recv_renew(void)
-{
-  if (!ncm_interface.num_datagrams)
-  {
-    usbd_edpt_xfer(0, ncm_interface.ep_out, receive_ntb, sizeof(receive_ntb));
+    uint16_t notif_len = sizeof(notify_speed_change.header) + notify_speed_change.header.wLength;
+    ncm_epbuf.epnotif = notify_speed_change;
+    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t*) &ncm_epbuf.epnotif, notif_len);
+
+    ncm_interface.notification_xmit_state = NOTIFICATION_CONNECTED;
+    ncm_interface.notification_xmit_is_running = true;
+  } else if (ncm_interface.notification_xmit_state == NOTIFICATION_CONNECTED) {
+    TU_LOG_DRV("  NOTIFICATION_CONNECTED\n");
+    ncm_notify_t notify_connected = {
+      .header = {
+        .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_IN
+        },
+        .bRequest = CDC_NOTIF_NETWORK_CONNECTION,
+        .wValue = 1 /* Connected */,
+        .wIndex = ncm_interface.itf_num,
+        .wLength = 0,
+      },
+    };
+
+    uint16_t notif_len = sizeof(notify_connected.header) + notify_connected.header.wLength;
+    ncm_epbuf.epnotif = notify_connected;
+    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_epbuf.epnotif, notif_len);
+
+    ncm_interface.notification_xmit_state = NOTIFICATION_DONE;
+    ncm_interface.notification_xmit_is_running = true;
+  } else {
+    TU_LOG_DRV("  NOTIFICATION_FINISHED\n");
+  }
+} // notification_xmit
+
+//-----------------------------------------------------------------------------
+//
+// everything about packet transmission (driver -> TinyUSB)
+//
+
+/**
+ * Put NTB into the transmitter free list.
+ */
+static void xmit_put_ntb_into_free_list(xmit_ntb_t *free_ntb) {
+  TU_LOG_DRV("xmit_put_ntb_into_free_list() - %p\n", ncm_interface.xmit_tinyusb_ntb);
+
+  if (free_ntb == NULL) { // can happen due to ZLPs
     return;
   }
 
-  const ndp16_t *ndp = ncm_interface.ndp;
-  const int i = ncm_interface.current_datagram_index;
-  ncm_interface.current_datagram_index++;
-  ncm_interface.num_datagrams--;
+  for (int i = 0; i < XMIT_NTB_N; ++i) {
+    if (ncm_interface.xmit_free_ntb[i] == NULL) {
+      ncm_interface.xmit_free_ntb[i] = free_ntb;
+      return;
+    }
+  }
+  TU_LOG_DRV("(EE) xmit_put_ntb_into_free_list - no entry in free list\n");// this should not happen
+} // xmit_put_ntb_into_free_list
 
-  tud_network_recv_cb(receive_ntb + ndp->datagram[i].wDatagramIndex, ndp->datagram[i].wDatagramLength);
+/**
+ * Get an NTB from the free list
+ */
+static xmit_ntb_t *xmit_get_free_ntb(void) {
+  TU_LOG_DRV("xmit_get_free_ntb()\n");
+
+  for (int i = 0; i < XMIT_NTB_N; ++i) {
+    if (ncm_interface.xmit_free_ntb[i] != NULL) {
+      xmit_ntb_t *free = ncm_interface.xmit_free_ntb[i];
+      ncm_interface.xmit_free_ntb[i] = NULL;
+      return free;
+    }
+  }
+  return NULL;
+} // xmit_get_free_ntb
+
+/**
+ * Put a filled NTB into the ready list
+ */
+static void xmit_put_ntb_into_ready_list(xmit_ntb_t *ready_ntb) {
+  TU_LOG_DRV("xmit_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
+
+  for (int i = 0; i < XMIT_NTB_N; ++i) {
+    if (ncm_interface.xmit_ready_ntb[i] == NULL) {
+      ncm_interface.xmit_ready_ntb[i] = ready_ntb;
+      return;
+    }
+  }
+  TU_LOG_DRV("(EE) xmit_put_ntb_into_ready_list: ready list full\n");// this should not happen
+} // xmit_put_ntb_into_ready_list
+
+/**
+ * Get the next NTB from the ready list (and remove it from the list).
+ * If the ready list is empty, return NULL.
+ */
+static xmit_ntb_t *xmit_get_next_ready_ntb(void) {
+  xmit_ntb_t *r = NULL;
+
+  r = ncm_interface.xmit_ready_ntb[0];
+  memmove(ncm_interface.xmit_ready_ntb + 0, ncm_interface.xmit_ready_ntb + 1, sizeof(ncm_interface.xmit_ready_ntb) - sizeof(ncm_interface.xmit_ready_ntb[0]));
+  ncm_interface.xmit_ready_ntb[XMIT_NTB_N - 1] = NULL;
+
+  TU_LOG_DRV("recv_get_next_ready_ntb: %p\n", r);
+  return r;
+} // xmit_get_next_ready_ntb
+
+/**
+ * Transmit a ZLP if required
+ *
+ * \note
+ *    Insertion of the ZLPs is a little bit different then described in the spec.
+ *    But the below implementation actually works.  Don't know if this is a spec
+ *    or TinyUSB issue.
+ *
+ * \pre
+ *    This must be called from netd_xfer_cb() so that ep_in is ready
+ */
+static bool xmit_insert_required_zlp(uint8_t rhport, uint32_t xferred_bytes) {
+  TU_LOG_DRV("xmit_insert_required_zlp(%d,%ld)\n", rhport, xferred_bytes);
+
+  if (xferred_bytes == 0 || xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE != 0) {
+    return false;
+  }
+
+  TU_ASSERT(ncm_interface.itf_data_alt == 1, false);
+  TU_ASSERT(!usbd_edpt_busy(rhport, ncm_interface.ep_in), false);
+
+  TU_LOG_DRV("xmit_insert_required_zlp! (%u)\n", (unsigned) xferred_bytes);
+
+  // start transmission of the ZLP
+  usbd_edpt_xfer(rhport, ncm_interface.ep_in, NULL, 0);
+
+  return true;
+} // xmit_insert_required_zlp
+
+/**
+ * Start transmission if it there is a waiting packet and if can be done from interface side.
+ */
+static void xmit_start_if_possible(uint8_t rhport) {
+  TU_LOG_DRV("xmit_start_if_possible()\n");
+
+  if (ncm_interface.xmit_tinyusb_ntb != NULL) {
+    TU_LOG_DRV("  !xmit_start_if_possible 1\n");
+    return;
+  }
+  if (ncm_interface.itf_data_alt != 1) {
+    TU_LOG_DRV("(EE) !xmit_start_if_possible 2\n");
+    return;
+  }
+  if (usbd_edpt_busy(rhport, ncm_interface.ep_in)) {
+    TU_LOG_DRV("  !xmit_start_if_possible 3\n");
+    return;
+  }
+
+  ncm_interface.xmit_tinyusb_ntb = xmit_get_next_ready_ntb();
+  if (ncm_interface.xmit_tinyusb_ntb == NULL) {
+    if (ncm_interface.xmit_glue_ntb == NULL || ncm_interface.xmit_glue_ntb_datagram_ndx == 0) {
+      // -> really nothing is waiting
+      return;
+    }
+    ncm_interface.xmit_tinyusb_ntb = ncm_interface.xmit_glue_ntb;
+    ncm_interface.xmit_glue_ntb = NULL;
+  }
+
+  #if CFG_TUD_NCM_LOG_LEVEL >= 3
+  {
+    uint16_t len = ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength;
+    TU_LOG_BUF(3, ncm_interface.xmit_tinyusb_ntb->data[i], len);
+  }
+  #endif
+
+  if (ncm_interface.xmit_glue_ntb_datagram_ndx != 1) {
+    TU_LOG_DRV(">> %d %d\n", ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength, ncm_interface.xmit_glue_ntb_datagram_ndx);
+  }
+
+  // Kick off an endpoint transfer
+  usbd_edpt_xfer(0, ncm_interface.ep_in, ncm_interface.xmit_tinyusb_ntb->data, ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength);
+} // xmit_start_if_possible
+
+/**
+ * check if a new datagram fits into the current NTB
+ */
+static bool xmit_requested_datagram_fits_into_current_ntb(uint16_t datagram_size) {
+  TU_LOG_DRV("xmit_requested_datagram_fits_into_current_ntb(%d) - %p %p\n", datagram_size, ncm_interface.xmit_tinyusb_ntb, ncm_interface.xmit_glue_ntb);
+
+  if (ncm_interface.xmit_glue_ntb == NULL) {
+    return false;
+  }
+  if (ncm_interface.xmit_glue_ntb_datagram_ndx >= CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB) {
+    return false;
+  }
+  if (ncm_interface.xmit_glue_ntb->nth.wBlockLength + datagram_size + XMIT_ALIGN_OFFSET(datagram_size) > CFG_TUD_NCM_IN_NTB_MAX_SIZE) {
+    return false;
+  }
+  return true;
+} // xmit_requested_datagram_fits_into_current_ntb
+
+/**
+ * Setup an NTB for the glue logic
+ */
+static bool xmit_setup_next_glue_ntb(void) {
+  TU_LOG_DRV("xmit_setup_next_glue_ntb - %p\n", ncm_interface.xmit_glue_ntb);
+
+  if (ncm_interface.xmit_glue_ntb != NULL) {
+    // put NTB into waiting list (the new datagram did not fit in)
+    xmit_put_ntb_into_ready_list(ncm_interface.xmit_glue_ntb);
+  }
+
+  ncm_interface.xmit_glue_ntb = xmit_get_free_ntb();// get next buffer (if any)
+  if (ncm_interface.xmit_glue_ntb == NULL) {
+    TU_LOG_DRV("  xmit_setup_next_glue_ntb - nothing free\n");// should happen rarely
+    return false;
+  }
+
+  ncm_interface.xmit_glue_ntb_datagram_ndx = 0;
+
+  xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
+
+  // Fill in NTB header
+  ntb->nth.dwSignature = NTH16_SIGNATURE;
+  ntb->nth.wHeaderLength = sizeof(ntb->nth);
+  ntb->nth.wSequence = ncm_interface.xmit_sequence++;
+  ntb->nth.wBlockLength = sizeof(ntb->nth) + sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
+  ntb->nth.wNdpIndex = sizeof(ntb->nth);
+
+  // Fill in NDP16 header and terminator
+  ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0;
+  ntb->ndp.wLength = sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
+  ntb->ndp.wNextNdpIndex = 0;
+
+  memset(ntb->ndp_datagram, 0, sizeof(ntb->ndp_datagram));
+  return true;
+} // xmit_setup_next_glue_ntb
+
+//-----------------------------------------------------------------------------
+//
+// all the recv_*() stuff (TinyUSB -> driver -> glue logic)
+//
+
+/**
+ * Return pointer to an available receive buffer or NULL.
+ * Returned buffer (if any) has the size \a CFG_TUD_NCM_OUT_NTB_MAX_SIZE.
+ */
+static recv_ntb_t *recv_get_free_ntb(void) {
+  TU_LOG_DRV("recv_get_free_ntb()\n");
+
+  for (int i = 0; i < RECV_NTB_N; ++i) {
+    if (ncm_interface.recv_free_ntb[i] != NULL) {
+      recv_ntb_t *free = ncm_interface.recv_free_ntb[i];
+      ncm_interface.recv_free_ntb[i] = NULL;
+      return free;
+    }
+  }
+  return NULL;
+} // recv_get_free_ntb
+
+/**
+ * Get the next NTB from the ready list (and remove it from the list).
+ * If the ready list is empty, return NULL.
+ */
+static recv_ntb_t *recv_get_next_ready_ntb(void) {
+  recv_ntb_t *r = NULL;
+
+  r = ncm_interface.recv_ready_ntb[0];
+  memmove(ncm_interface.recv_ready_ntb + 0, ncm_interface.recv_ready_ntb + 1, sizeof(ncm_interface.recv_ready_ntb) - sizeof(ncm_interface.recv_ready_ntb[0]));
+  ncm_interface.recv_ready_ntb[RECV_NTB_N - 1] = NULL;
+
+  TU_LOG_DRV("recv_get_next_ready_ntb: %p\n", r);
+  return r;
+} // recv_get_next_ready_ntb
+
+/**
+ * Put NTB into the receiver free list.
+ */
+static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb) {
+  TU_LOG_DRV("recv_put_ntb_into_free_list(%p)\n", free_ntb);
+
+  for (int i = 0; i < RECV_NTB_N; ++i) {
+    if (ncm_interface.recv_free_ntb[i] == NULL) {
+      ncm_interface.recv_free_ntb[i] = free_ntb;
+      return;
+    }
+  }
+  TU_LOG_DRV("(EE) recv_put_ntb_into_free_list - no entry in free list\n");// this should not happen
+} // recv_put_ntb_into_free_list
+
+/**
+ * \a ready_ntb holds a validated NTB,
+ * put this buffer into the waiting list.
+ */
+static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb) {
+  TU_LOG_DRV("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
+
+  for (int i = 0; i < RECV_NTB_N; ++i) {
+    if (ncm_interface.recv_ready_ntb[i] == NULL) {
+      ncm_interface.recv_ready_ntb[i] = ready_ntb;
+      return;
+    }
+  }
+  TU_LOG_DRV("(EE) recv_put_ntb_into_ready_list: ready list full\n");// this should not happen
+} // recv_put_ntb_into_ready_list
+
+/**
+ * If possible, start a new reception TinyUSB -> driver.
+ */
+static void recv_try_to_start_new_reception(uint8_t rhport) {
+  TU_LOG_DRV("recv_try_to_start_new_reception(%d)\n", rhport);
+
+  if (ncm_interface.itf_data_alt != 1) {
+    return;
+  }
+  if (ncm_interface.recv_tinyusb_ntb != NULL) {
+    return;
+  }
+  if (usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
+    return;
+  }
+
+  ncm_interface.recv_tinyusb_ntb = recv_get_free_ntb();
+  if (ncm_interface.recv_tinyusb_ntb == NULL) {
+    return;
+  }
+
+  // initiate transfer
+  TU_LOG_DRV("  start reception\n");
+  bool r = usbd_edpt_xfer(rhport, ncm_interface.ep_out, ncm_interface.recv_tinyusb_ntb->data, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+  if (!r) {
+    recv_put_ntb_into_free_list(ncm_interface.recv_tinyusb_ntb);
+    ncm_interface.recv_tinyusb_ntb = NULL;
+  }
+} // recv_try_to_start_new_reception
+
+/**
+ * Validate incoming datagram.
+ * \return true if valid
+ *
+ * \note
+ *    \a ndp16->wNextNdpIndex != 0 is not supported
+ */
+static bool recv_validate_datagram(const recv_ntb_t *ntb, uint32_t len) {
+  const nth16_t *nth16 = &(ntb->nth);
+
+  TU_LOG_DRV("recv_validate_datagram(%p, %d)\n", ntb, (int) len);
+
+  // check header
+  if (nth16->wHeaderLength != sizeof(nth16_t)) {
+    TU_LOG_DRV("(EE) ill nth16 length: %d\n", nth16->wHeaderLength);
+    return false;
+  }
+  if (nth16->dwSignature != NTH16_SIGNATURE) {
+    TU_LOG_DRV("(EE) ill signature: 0x%08x\n", (unsigned) nth16->dwSignature);
+    return false;
+  }
+  if (len < sizeof(nth16_t) + sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t)) {
+    TU_LOG_DRV("(EE) ill min len: %lu\n", len);
+    return false;
+  }
+  if (nth16->wBlockLength > len) {
+    TU_LOG_DRV("(EE) ill block length: %d > %lu\n", nth16->wBlockLength, len);
+    return false;
+  }
+  if (nth16->wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+    TU_LOG_DRV("(EE) ill block length2: %d > %d\n", nth16->wBlockLength, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+    return false;
+  }
+  if (nth16->wNdpIndex < sizeof(nth16) || nth16->wNdpIndex > len - (sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t))) {
+    TU_LOG_DRV("(EE) ill position of first ndp: %d (%lu)\n", nth16->wNdpIndex, len);
+    return false;
+  }
+
+  // check (first) NDP(16)
+  const ndp16_t *ndp16 = (const ndp16_t *) (ntb->data + nth16->wNdpIndex);
+
+  if (ndp16->wLength < sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t)) {
+    TU_LOG_DRV("(EE) ill ndp16 length: %d\n", ndp16->wLength);
+    return false;
+  }
+  if (ndp16->dwSignature != NDP16_SIGNATURE_NCM0 && ndp16->dwSignature != NDP16_SIGNATURE_NCM1) {
+    TU_LOG_DRV("(EE) ill signature: 0x%08x\n", (unsigned) ndp16->dwSignature);
+    return false;
+  }
+  if (ndp16->wNextNdpIndex != 0) {
+    TU_LOG_DRV("(EE) cannot handle wNextNdpIndex!=0 (%d)\n", ndp16->wNextNdpIndex);
+    return false;
+  }
+
+  const ndp16_datagram_t *ndp16_datagram = (const ndp16_datagram_t *) (ntb->data + nth16->wNdpIndex + sizeof(ndp16_t));
+  int ndx = 0;
+  uint16_t max_ndx = (uint16_t) ((ndp16->wLength - sizeof(ndp16_t)) / sizeof(ndp16_datagram_t));
+
+  if (max_ndx > 2) { // number of datagrams in NTB > 1
+    TU_LOG_DRV("<< %d (%d)\n", max_ndx - 1, ntb->nth.wBlockLength);
+  }
+  if (ndp16_datagram[max_ndx - 1].wDatagramIndex != 0 || ndp16_datagram[max_ndx - 1].wDatagramLength != 0) {
+    TU_LOG_DRV("  max_ndx != 0\n");
+    return false;
+  }
+  while (ndp16_datagram[ndx].wDatagramIndex != 0 && ndp16_datagram[ndx].wDatagramLength != 0) {
+    TU_LOG_DRV("  << %d %d\n", ndp16_datagram[ndx].wDatagramIndex, ndp16_datagram[ndx].wDatagramLength);
+    if (ndp16_datagram[ndx].wDatagramIndex > len) {
+      TU_LOG_DRV("(EE) ill start of datagram[%d]: %d (%lu)\n", ndx, ndp16_datagram[ndx].wDatagramIndex, len);
+      return false;
+    }
+    if (ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength > len) {
+      TU_LOG_DRV("(EE) ill end of datagram[%d]: %d (%lu)\n", ndx, ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength, len);
+      return false;
+    }
+    ++ndx;
+  }
+
+  #if CFG_TUD_NCM_LOG_LEVEL >= 3
+  TU_LOG_BUF(3, ntb->data[i], len);
+  #endif
+
+  // -> ntb contains a valid packet structure
+  //    ok... I did not check for garbage within the datagram indices...
+  return true;
+} // recv_validate_datagram
+
+/**
+ * Transfer the next (pending) datagram to the glue logic and return receive buffer if empty.
+ */
+static void recv_transfer_datagram_to_glue_logic(void) {
+  TU_LOG_DRV("recv_transfer_datagram_to_glue_logic()\n");
+
+  if (ncm_interface.recv_glue_ntb == NULL) {
+    ncm_interface.recv_glue_ntb = recv_get_next_ready_ntb();
+    TU_LOG_DRV("  new buffer for glue logic: %p\n", ncm_interface.recv_glue_ntb);
+    ncm_interface.recv_glue_ntb_datagram_ndx = 0;
+  }
+
+  if (ncm_interface.recv_glue_ntb != NULL) {
+    const ndp16_datagram_t *ndp16_datagram = (ndp16_datagram_t *) (ncm_interface.recv_glue_ntb->data + ncm_interface.recv_glue_ntb->nth.wNdpIndex + sizeof(ndp16_t));
+
+    if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex == 0) {
+      TU_LOG_DRV("(EE) SOMETHING WENT WRONG 1\n");
+    } else if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength == 0) {
+      TU_LOG_DRV("(EE) SOMETHING WENT WRONG 2\n");
+    } else {
+      uint16_t datagramIndex = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex;
+      uint16_t datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength;
+
+      TU_LOG_DRV("  recv[%d] - %d %d\n", ncm_interface.recv_glue_ntb_datagram_ndx, datagramIndex, datagramLength);
+      if (tud_network_recv_cb(ncm_interface.recv_glue_ntb->data + datagramIndex, datagramLength)) {
+        // send datagram successfully to glue logic
+        TU_LOG_DRV("    OK\n");
+        datagramIndex = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramIndex;
+        datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramLength;
+
+        if (datagramIndex != 0 && datagramLength != 0) {
+          // -> next datagram
+          ++ncm_interface.recv_glue_ntb_datagram_ndx;
+        } else {
+          // end of datagrams reached
+          recv_put_ntb_into_free_list(ncm_interface.recv_glue_ntb);
+          ncm_interface.recv_glue_ntb = NULL;
+        }
+      }
+    }
+  }
+} // recv_transfer_datagram_to_glue_logic
+
+//-----------------------------------------------------------------------------
+//
+// all the tud_network_*() stuff (glue logic -> driver)
+//
+
+/**
+ * Check if the glue logic is allowed to call tud_network_xmit().
+ * This function also fetches a next buffer if required, so that tud_network_xmit() is ready for copy
+ * and transmission operation.
+ */
+bool tud_network_can_xmit(uint16_t size) {
+  TU_LOG_DRV("tud_network_can_xmit(%d)\n", size);
+
+  TU_ASSERT(size <= CFG_TUD_NCM_IN_NTB_MAX_SIZE - (sizeof(nth16_t) + sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t)), false);
+
+  if (xmit_requested_datagram_fits_into_current_ntb(size) || xmit_setup_next_glue_ntb()) {
+    // -> everything is fine
+    return true;
+  }
+  xmit_start_if_possible(ncm_interface.rhport);
+  TU_LOG_DRV("(II) tud_network_can_xmit: request blocked\n");// could happen if all xmit buffers are full (but should happen rarely)
+  return false;
+} // tud_network_can_xmit
+
+/**
+ * Put a datagram into a waiting NTB.
+ * If currently no transmission is started, then initiate transmission.
+ */
+void tud_network_xmit(void *ref, uint16_t arg) {
+  TU_LOG_DRV("tud_network_xmit(%p, %d)\n", ref, arg);
+
+  if (ncm_interface.xmit_glue_ntb == NULL) {
+    TU_LOG_DRV("(EE) tud_network_xmit: no buffer\n");// must not happen (really)
+    return;
+  }
+
+  xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
+
+  // copy new datagram to the end of the current NTB
+  uint16_t size = tud_network_xmit_cb(ntb->data + ntb->nth.wBlockLength, ref, arg);
+
+  // correct NTB internals
+  ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramIndex = ntb->nth.wBlockLength;
+  ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramLength = size;
+  ncm_interface.xmit_glue_ntb_datagram_ndx += 1;
+
+  ntb->nth.wBlockLength += (uint16_t) (size + XMIT_ALIGN_OFFSET(size));
+
+  if (ntb->nth.wBlockLength > CFG_TUD_NCM_IN_NTB_MAX_SIZE) {
+    TU_LOG_DRV("(EE) tud_network_xmit: buffer overflow\n"); // must not happen (really)
+    return;
+  }
+
+  xmit_start_if_possible(ncm_interface.rhport);
+} // tud_network_xmit
+
+/**
+ * Keep the receive logic busy and transfer pending packets to the glue logic.
+ * Avoid recursive calls due to wrong expectations of the net glue logic,
+ * see https://github.com/hathach/tinyusb/issues/2711
+ */
+void tud_network_recv_renew(void) {
+  TU_LOG_DRV("tud_network_recv_renew()\n");
+
+  ncm_interface.tud_network_recv_renew_process_again = true;
+
+  if (ncm_interface.tud_network_recv_renew_active) {
+    TU_LOG_DRV("Re-entrant into tud_network_recv_renew, will process later\n");
+    return;
+  }
+
+  while (ncm_interface.tud_network_recv_renew_process_again) {
+    ncm_interface.tud_network_recv_renew_process_again = false;
+
+    // If the current function is called within recv_transfer_datagram_to_glue_logic,
+    // tud_network_recv_renew_process_again will become true, and the loop will run again
+    // Otherwise the loop will not run again
+    ncm_interface.tud_network_recv_renew_active = true;
+    recv_transfer_datagram_to_glue_logic();
+    ncm_interface.tud_network_recv_renew_active = false;
+  }
+  recv_try_to_start_new_reception(ncm_interface.rhport);
+} // tud_network_recv_renew
+
+/**
+ * Same as tud_network_recv_renew() but knows \a rhport
+ */
+static void tud_network_recv_renew_r(uint8_t rhport) {
+  TU_LOG_DRV("tud_network_recv_renew_r(%d)\n", rhport);
+
+  ncm_interface.rhport = rhport;
+  tud_network_recv_renew();
+} // tud_network_recv_renew
+
+//-----------------------------------------------------------------------------
+//
+// all the netd_*() stuff (interface TinyUSB -> driver)
+//
+/**
+ * Initialize the driver data structures.
+ * Might be called several times.
+ */
+void netd_init(void) {
+  TU_LOG_DRV("netd_init()\n");
+
+  memset(&ncm_interface, 0, sizeof(ncm_interface));
+
+  for (int i = 0; i < XMIT_NTB_N; ++i) {
+    ncm_interface.xmit_free_ntb[i] = &ncm_epbuf.xmit[i].ntb;
+  }
+  for (int i = 0; i < RECV_NTB_N; ++i) {
+    ncm_interface.recv_free_ntb[i] = &ncm_epbuf.recv[i].ntb;
+  }
+} // netd_init
+
+/**
+ * Deinit driver
+ */
+bool netd_deinit(void) {
+  return true;
 }
 
-//--------------------------------------------------------------------+
-// USBD Driver API
-//--------------------------------------------------------------------+
-
-void netd_init(void)
-{
-  tu_memclr(&ncm_interface, sizeof(ncm_interface));
-  ncm_interface.ntb_in_size = CFG_TUD_NCM_IN_NTB_MAX_SIZE;
-  ncm_interface.max_datagrams_per_ntb = CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB;
-  ncm_prepare_for_tx();
-}
-
-void netd_reset(uint8_t rhport)
-{
+/**
+ * Resets the port.
+ * In this driver this is the same as netd_init()
+ */
+void netd_reset(uint8_t rhport) {
   (void) rhport;
 
   netd_init();
-}
+} // netd_reset
 
-uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
-  // confirm interface hasn't already been allocated
-  TU_ASSERT(0 == ncm_interface.ep_notif, 0);
+/**
+ * Open the USB interface.
+ * - parse the USB descriptor \a TUD_CDC_NCM_DESCRIPTOR for itfnum and endpoints
+ * - a specific order of elements in the descriptor is tested.
+ *
+ * \note
+ *   Actually all of the information could be read directly from \a itf_desc, because the
+ *   structure and the values are well known.  But we do it this way.
+ *
+ * \post
+ * - \a itf_num set
+ * - \a ep_notif, \a ep_in and \a ep_out are set
+ * - USB interface is open
+ */
+uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+  TU_ASSERT(ncm_interface.ep_notif == 0, 0);// assure that the interface is only opened once
 
-  //------------- Management Interface -------------//
-  ncm_interface.itf_num = itf_desc->bInterfaceNumber;
+  ncm_interface.itf_num = itf_desc->bInterfaceNumber;// management interface
 
+  // skip the two first entries and the following TUSB_DESC_CS_INTERFACE entries
   uint16_t drv_len = sizeof(tusb_desc_interface_t);
-  uint8_t const * p_desc = tu_desc_next( itf_desc );
-
-  // Communication Functional Descriptors
-  while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
-  {
+  uint8_t const *p_desc = tu_desc_next(itf_desc);
+  while (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && drv_len <= max_len) {
     drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
+    p_desc = tu_desc_next(p_desc);
   }
 
-  // notification endpoint (if any)
-  if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
-  {
-    TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 );
+  // get notification endpoint
+  TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
+  TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0);
+  ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+  drv_len += tu_desc_len(p_desc);
+  p_desc = tu_desc_next(p_desc);
 
-    ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+  // skip the following TUSB_DESC_INTERFACE entries (which must be TUSB_CLASS_CDC_DATA)
+  while (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && drv_len <= max_len) {
+    tusb_desc_interface_t const *data_itf_desc = (tusb_desc_interface_t const *) p_desc;
+    TU_ASSERT(data_itf_desc->bInterfaceClass == TUSB_CLASS_CDC_DATA, 0);
 
     drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
+    p_desc = tu_desc_next(p_desc);
   }
 
-  //------------- Data Interface -------------//
-  // - CDC-NCM data interface has 2 alternate settings
-  //   - 0 : zero endpoints for inactive (default)
-  //   - 1 : IN & OUT endpoints for transfer of NTBs
-  TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0);
-
-  do
-  {
-    tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc;
-    TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0);
-
-    drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
-  } while((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len));
-
-  // Pair of endpoints
-  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0);
-
-  TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) );
-
-  drv_len += 2*sizeof(tusb_desc_endpoint_t);
+  // a TUSB_DESC_ENDPOINT (actually two) must follow, open these endpoints
+  TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
+  TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in));
+  drv_len += 2 * sizeof(tusb_desc_endpoint_t);
 
   return drv_len;
-}
+} // netd_open
 
-static void ncm_report(void)
-{
-  uint8_t const rhport = 0;
-  if (ncm_interface.report_state == REPORT_SPEED) {
-    ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
-    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
-    ncm_interface.report_state = REPORT_CONNECTED;
-    ncm_interface.report_pending = true;
-  } else if (ncm_interface.report_state == REPORT_CONNECTED) {
-    ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
-    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected));
-    ncm_interface.report_state = REPORT_DONE;
-    ncm_interface.report_pending = true;
+/**
+ * Handle TinyUSB requests to process transfer events.
+ */
+bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
+  (void) result;
+
+  if (ep_addr == ncm_interface.ep_out) {
+    // new NTB received
+    // - make the NTB valid
+    // - if ready transfer datagrams to the glue logic for further processing
+    // - if there is a free receive buffer, initiate reception
+    if (!recv_validate_datagram(ncm_interface.recv_tinyusb_ntb, xferred_bytes)) {
+      // verification failed: ignore NTB and return it to free
+      TU_LOG_DRV("Invalid datatagram. Ignoring NTB\n");
+      recv_put_ntb_into_free_list(ncm_interface.recv_tinyusb_ntb);
+    } else {
+      // packet ok -> put it into ready list
+      recv_put_ntb_into_ready_list(ncm_interface.recv_tinyusb_ntb);
+    }
+    ncm_interface.recv_tinyusb_ntb = NULL;
+    tud_network_recv_renew_r(rhport);
+  } else if (ep_addr == ncm_interface.ep_in) {
+    // transmission of an NTB finished
+    // - free the transmitted NTB buffer
+    // - insert ZLPs when necessary
+    // - if there is another transmit NTB waiting, try to start transmission
+    xmit_put_ntb_into_free_list(ncm_interface.xmit_tinyusb_ntb);
+    ncm_interface.xmit_tinyusb_ntb = NULL;
+    if (!xmit_insert_required_zlp(rhport, xferred_bytes)) {
+      xmit_start_if_possible(rhport);
+    }
+  } else if (ep_addr == ncm_interface.ep_notif) {
+    // next transfer on notification channel
+    notification_xmit(rhport, true);
   }
-}
 
-TU_ATTR_WEAK void tud_network_link_state_cb(bool state)
-{
-  (void)state;
-}
+  return true;
+} // netd_xfer_cb
 
-// Handle class control request
-// return false to stall control endpoint (e.g unsupported request)
-bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
-  if ( stage != CONTROL_STAGE_SETUP ) return true;
+/**
+ * Respond to TinyUSB control requests.
+ * At startup transmission of notification packets are done here.
+ */
+bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) {
+  if (stage != CONTROL_STAGE_SETUP) {
+    return true;
+  }
 
-  switch ( request->bmRequestType_bit.type )
-  {
+  switch (request->bmRequestType_bit.type) {
     case TUSB_REQ_TYPE_STANDARD:
-      switch ( request->bRequest )
-      {
-        case TUSB_REQ_GET_INTERFACE:
-        {
-          uint8_t const req_itfnum = (uint8_t) request->wIndex;
-          TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum);
+
+      switch (request->bRequest) {
+        case TUSB_REQ_GET_INTERFACE: {
+          TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex, false);
 
           tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
-        }
-          break;
+        } break;
 
-        case TUSB_REQ_SET_INTERFACE:
-        {
-          uint8_t const req_itfnum = (uint8_t) request->wIndex;
-          uint8_t const req_alt    = (uint8_t) request->wValue;
+        case TUSB_REQ_SET_INTERFACE: {
+          TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex && request->wValue < 2, false);
 
-          // Only valid for Data Interface with Alternate is either 0 or 1
-          TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum && req_alt < 2);
+          ncm_interface.itf_data_alt = (uint8_t) request->wValue;
 
-          if (req_alt != ncm_interface.itf_data_alt) {
-            ncm_interface.itf_data_alt = req_alt;
-
-            if (ncm_interface.itf_data_alt) {
-              if (!usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
-                tud_network_recv_renew(); // prepare for incoming datagrams
-              }
-              if (!ncm_interface.report_pending) {
-                ncm_report();
-              }
-            }
-
-            tud_network_link_state_cb(ncm_interface.itf_data_alt);
+          if (ncm_interface.itf_data_alt == 1) {
+            tud_network_recv_renew_r(rhport);
+            notification_xmit(rhport, false);
           }
-
           tud_control_status(rhport, request);
-        }
-          break;
+        } break;
 
-          // unsupported request
-        default: return false;
+        // unsupported request
+        default:
+          return false;
       }
       break;
 
     case TUSB_REQ_TYPE_CLASS:
-      TU_VERIFY (ncm_interface.itf_num == request->wIndex);
+      TU_VERIFY(ncm_interface.itf_num == request->wIndex, false);
+      switch (request->bRequest) {
+        case NCM_GET_NTB_PARAMETERS: {
+          // transfer NTB parameters to host.
+          tud_control_xfer(rhport, request, (void *) (uintptr_t) &ntb_parameters, sizeof(ntb_parameters));
+        } break;
 
-      if (NCM_GET_NTB_PARAMETERS == request->bRequest)
-      {
-        tud_control_xfer(rhport, request, (void*)&ntb_parameters, sizeof(ntb_parameters));
+          // unsupported request
+        default:
+          return false;
       }
-
       break;
-
       // unsupported request
-    default: return false;
+    default:
+      return false;
   }
 
   return true;
-}
+} // netd_control_xfer_cb
 
-static void handle_incoming_datagram(uint32_t len)
-{
-  uint32_t size = len;
-
-  if (len == 0) {
-    return;
-  }
-
-  TU_ASSERT(size >= sizeof(nth16_t), );
-
-  const nth16_t *hdr = (const nth16_t *)receive_ntb;
-  TU_ASSERT(hdr->dwSignature == NTH16_SIGNATURE, );
-  TU_ASSERT(hdr->wNdpIndex >= sizeof(nth16_t) && (hdr->wNdpIndex + sizeof(ndp16_t)) <= len, );
-
-  const ndp16_t *ndp = (const ndp16_t *)(receive_ntb + hdr->wNdpIndex);
-  TU_ASSERT(ndp->dwSignature == NDP16_SIGNATURE_NCM0 || ndp->dwSignature == NDP16_SIGNATURE_NCM1, );
-  TU_ASSERT(hdr->wNdpIndex + ndp->wLength <= len, );
-
-  int num_datagrams = (ndp->wLength - 12) / 4;
-  ncm_interface.current_datagram_index = 0;
-  ncm_interface.num_datagrams = 0;
-  ncm_interface.ndp = ndp;
-  for (int i = 0; i < num_datagrams && ndp->datagram[i].wDatagramIndex && ndp->datagram[i].wDatagramLength; i++)
-  {
-    ncm_interface.num_datagrams++;
-  }
-  
-  tud_network_recv_renew();
-}
-
-bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
-  (void) rhport;
-  (void) result;
-
-  /* new datagram receive_ntb */
-  if (ep_addr == ncm_interface.ep_out )
-  {
-    handle_incoming_datagram(xferred_bytes);
-  }
-
-  /* data transmission finished */
-  if (ep_addr == ncm_interface.ep_in )
-  {
-    if (ncm_interface.transferring) {
-      ncm_interface.transferring = false;
-    }
-
-    // If there are datagrams queued up that we tried to send while this NTB was being emitted, send them now
-    if (ncm_interface.datagram_count && ncm_interface.itf_data_alt == 1) {
-      ncm_start_tx();
-    }
-  }
-
-  if (ep_addr == ncm_interface.ep_notif )
-  {
-    ncm_interface.report_pending = false;
-    ncm_report();
-  }
-
-  return true;
-}
-
-// poll network driver for its ability to accept another packet to transmit
-bool tud_network_can_xmit(uint16_t size)
-{
-  TU_VERIFY(ncm_interface.itf_data_alt == 1);
-
-  if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) {
-    TU_LOG2("NTB full [by count]\r\n");
-    return false;
-  }
-
-  size_t next_datagram_offset = ncm_interface.next_datagram_offset;
-  if (next_datagram_offset + size > ncm_interface.ntb_in_size) {
-    TU_LOG2("ntb full [by size]\r\n");
-    return false;
-  }
-
-  return true;
-}
-
-void tud_network_xmit(void *ref, uint16_t arg)
-{
-  transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
-  size_t next_datagram_offset = ncm_interface.next_datagram_offset;
-
-  uint16_t size = tud_network_xmit_cb(ntb->data + next_datagram_offset, ref, arg);
-
-  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = ncm_interface.next_datagram_offset;
-  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = size;
-
-  ncm_interface.datagram_count++;
-  next_datagram_offset += size;
-
-  // round up so the next datagram is aligned correctly
-  next_datagram_offset += (CFG_TUD_NCM_ALIGNMENT - 1);
-  next_datagram_offset -= (next_datagram_offset % CFG_TUD_NCM_ALIGNMENT);
-
-  ncm_interface.next_datagram_offset = next_datagram_offset;
-
-  ncm_start_tx();
-}
-
-#endif
+#endif // ( CFG_TUD_ENABLED && CFG_TUD_NCM )
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index 6e294465b..4c9a92f2d 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Peter Lawrence
@@ -28,14 +28,13 @@
 #ifndef _TUSB_NET_DEVICE_H_
 #define _TUSB_NET_DEVICE_H_
 
+#include <stdint.h>
 #include "class/cdc/cdc.h"
 
 #if CFG_TUD_ECM_RNDIS && CFG_TUD_NCM
 #error "Cannot enable both ECM_RNDIS and NCM network drivers"
 #endif
 
-#include "ncm.h"
-
 /* declared here, NOT in usb_descriptors.c, so that the driver can intelligently ZLP as needed */
 #define CFG_TUD_NET_ENDPOINT_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
@@ -44,21 +43,13 @@
 #define CFG_TUD_NET_MTU           1514
 #endif
 
-#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
-#define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200
-#endif
 
-#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
-#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200
-#endif
+// Table 4.3 Data Class Interface Protocol Codes
+typedef enum
+{
+  NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK = 0x01
+} ncm_data_interface_protocol_code_t;
 
-#ifndef CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
-#define CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB 8
-#endif
-
-#ifndef CFG_TUD_NCM_ALIGNMENT
-#define CFG_TUD_NCM_ALIGNMENT 4
-#endif
 
 #ifdef __cplusplus
  extern "C" {
@@ -94,17 +85,13 @@ void tud_network_init_cb(void);
 
 // client must provide this: 48-bit MAC address
 // TODO removed later since it is not part of tinyusb stack
-extern const uint8_t tud_network_mac_address[6];
-
-//------------- NCM -------------//
-
-// callback to client providing optional indication of internal state of network driver
-void tud_network_link_state_cb(bool state);
+extern uint8_t tud_network_mac_address[6];
 
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+
 void     netd_init            (void);
+bool     netd_deinit          (void);
 void     netd_reset           (uint8_t rhport);
 uint16_t netd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h
index e7016ae24..327de087c 100644
--- a/src/class/usbtmc/usbtmc.h
+++ b/src/class/usbtmc/usbtmc.h
@@ -158,7 +158,7 @@ enum {
   USBTMC_BULK_IN_ERR_DATA_TOO_SHORT = 4u,
   USBTMC_BULK_IN_ERR_DATA_TOO_LONG = 5u,
 };
-// bult-in halt errors
+// built-in halt errors
 enum {
   USBTMC_BULK_IN_ERR = 1u, ///< receives a USBTMC command message that expects a response while a
                            /// Bulk-IN transfer is in progress
@@ -183,6 +183,23 @@ typedef enum {
 
 } usmtmc_request_type_enum;
 
+typedef enum {
+  // The last and first valid bNotify1 for use by the USBTMC class specification.
+  USBTMC_bNOTIFY1_USBTMC_FIRST          = 0x00,
+  USBTMC_bNOTIFY1_USBTMC_LAST           = 0x3F,
+
+  // The last and first valid bNotify1 for use by vendors.
+  USBTMC_bNOTIFY1_VENDOR_SPECIFIC_FIRST = 0x40,
+  USBTMC_bNOTIFY1_VENDOR_SPECIFIC_LAST  = 0x7F,
+
+  // The last and first valid bNotify1 for use by USBTMC subclass specifications.
+  USBTMC_bNOTIFY1_SUBCLASS_FIRST        = 0x80,
+  USBTMC_bNOTIFY1_SUBCLASS_LAST         = 0xFF,
+
+  // From the USB488 Subclass Specification, Section 3.4.
+  USB488_bNOTIFY1_SRQ                   = 0x81,
+} usbtmc_int_in_payload_format;
+
 typedef enum {
   USBTMC_STATUS_SUCCESS = 0x01,
   USBTMC_STATUS_PENDING = 0x02,
@@ -262,14 +279,14 @@ typedef struct TU_ATTR_PACKED
 
   struct TU_ATTR_PACKED
   {
-    unsigned int listenOnly :1;
-    unsigned int talkOnly :1;
-    unsigned int supportsIndicatorPulse :1;
+    uint8_t listenOnly :1;
+    uint8_t talkOnly :1;
+    uint8_t supportsIndicatorPulse :1;
   } bmIntfcCapabilities;
 
   struct TU_ATTR_PACKED
   {
-    unsigned int canEndBulkInOnTermChar :1;
+    uint8_t canEndBulkInOnTermChar :1;
   } bmDevCapabilities;
 
   uint8_t _reserved2[6];
@@ -277,17 +294,17 @@ typedef struct TU_ATTR_PACKED
 
   struct TU_ATTR_PACKED
   {
-    unsigned int is488_2 :1;
-    unsigned int supportsREN_GTL_LLO :1;
-    unsigned int supportsTrigger :1;
+    uint8_t supportsTrigger :1;
+    uint8_t supportsREN_GTL_LLO :1;
+    uint8_t is488_2 :1;
   } bmIntfcCapabilities488;
 
   struct TU_ATTR_PACKED
   {
-    unsigned int SCPI :1;
-    unsigned int SR1 :1;
-    unsigned int RL1 :1;
-    unsigned int DT1 :1;
+    uint8_t DT1 :1;
+    uint8_t RL1 :1;
+    uint8_t SR1 :1;
+    uint8_t SCPI :1;
   } bmDevCapabilities488;
   uint8_t _reserved3[8];
 } usbtmc_response_capabilities_488_t;
@@ -303,6 +320,14 @@ typedef struct TU_ATTR_PACKED
 
 TU_VERIFY_STATIC(sizeof(usbtmc_read_stb_rsp_488_t) == 3u, "struct wrong length");
 
+typedef struct TU_ATTR_PACKED
+{
+  uint8_t bNotify1; // Must be USB488_bNOTIFY1_SRQ
+  uint8_t StatusByte;
+} usbtmc_srq_interrupt_488_t;
+
+TU_VERIFY_STATIC(sizeof(usbtmc_srq_interrupt_488_t) == 2u, "struct wrong length");
+
 typedef struct TU_ATTR_PACKED
 {
   struct TU_ATTR_PACKED
@@ -316,4 +341,3 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC(sizeof(usbtmc_read_stb_interrupt_488_t) == 2u, "struct wrong length");
 
 #endif
-
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index af4a92732..abde9679f 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -78,14 +78,19 @@
 
 #ifdef xDEBUG
 #include "uart_util.h"
-static char logMsg[150];
+tu_static char logMsg[150];
 #endif
 
 // Buffer size must be an exact multiple of the max packet size for both
 // bulk  (up to 64 bytes for FS, 512 bytes for HS). In addation, this driver
-// imposes a minimum buffer size of 32 bytes. 
+// imposes a minimum buffer size of 32 bytes.
 #define USBTMCD_BUFFER_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
+// Interrupt endpoint buffer size, default to 2 bytes as USB488 specification.
+#ifndef CFG_TUD_USBTMC_INT_EP_SIZE
+#define CFG_TUD_USBTMC_INT_EP_SIZE 2
+#endif
+
 /*
  * The state machine does not allow simultaneous reading and writing. This is
  * consistent with USBTMC.
@@ -124,14 +129,8 @@ typedef struct
   uint8_t ep_bulk_in;
   uint8_t ep_bulk_out;
   uint8_t ep_int_in;
-  // IN buffer is only used for first packet, not the remainder
-  // in order to deal with prepending header
-  CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_in_buf[USBTMCD_BUFFER_SIZE];
   uint32_t ep_bulk_in_wMaxPacketSize;
-  // OUT buffer receives one packet at a time
-  CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_out_buf[USBTMCD_BUFFER_SIZE];
   uint32_t ep_bulk_out_wMaxPacketSize;
-
   uint32_t transfer_size_remaining; // also used for requested length for bulk IN.
   uint32_t transfer_size_sent;      // To keep track of data bytes that have been queued in FIFO (not header bytes)
 
@@ -143,28 +142,45 @@ typedef struct
   usbtmc_capabilities_specific_t const * capabilities;
 } usbtmc_interface_state_t;
 
-CFG_TUSB_MEM_SECTION static usbtmc_interface_state_t usbtmc_state =
-{
-    .itf_id = 0xFF,
+typedef struct {
+  // IN buffer is only used for first packet, not the remainder in order to deal with prepending header
+  TUD_EPBUF_DEF(epin, USBTMCD_BUFFER_SIZE);
+
+  // OUT buffer receives one packet at a time
+  TUD_EPBUF_DEF(epout, USBTMCD_BUFFER_SIZE);
+
+  // Buffer int msg
+  TUD_EPBUF_DEF(epnotif, CFG_TUD_USBTMC_INT_EP_SIZE);
+} usbtmc_epbuf_t;
+
+static usbtmc_interface_state_t usbtmc_state = {
+  .itf_id = 0xFF,
 };
 
+CFG_TUD_MEM_SECTION static usbtmc_epbuf_t usbtmc_epbuf;
+
 // We need all headers to fit in a single packet in this implementation, 32 bytes will fit all standard USBTMC headers
 TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small");
 
 static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len);
 static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen);
 
-static uint8_t termChar;
-static uint8_t termCharRequested = false;
+#ifndef NDEBUG
+tu_static uint8_t termChar;
+#endif
 
-osal_mutex_def_t usbtmcLockBuffer;
-static osal_mutex_t usbtmcLock;
+tu_static uint8_t termCharRequested = false;
+
+#if OSAL_MUTEX_REQUIRED
+static OSAL_MUTEX_DEF(usbtmcLockBuffer);
+#endif
+osal_mutex_t usbtmcLock;
 
 // Our own private lock, mostly for the state variable.
-#define criticalEnter() do {osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0)
-#define criticalLeave() do {osal_mutex_unlock(usbtmcLock); } while (0)
+#define criticalEnter() do { (void) osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0)
+#define criticalLeave() do { (void) osal_mutex_unlock(usbtmcLock); } while (0)
 
-bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState)
+static bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState)
 {
   bool ret = true;
   criticalEnter();
@@ -193,7 +209,7 @@ bool tud_usbtmc_transmit_dev_msg_data(
     bool endOfMessage,
     bool usingTermChar)
 {
-  const unsigned int txBufLen = sizeof(usbtmc_state.ep_bulk_in_buf);
+  const unsigned int txBufLen = USBTMCD_BUFFER_SIZE;
 
 #ifndef NDEBUG
   TU_ASSERT(len > 0u);
@@ -208,7 +224,7 @@ bool tud_usbtmc_transmit_dev_msg_data(
 #endif
 
   TU_VERIFY(usbtmc_state.state == STATE_TX_REQUESTED);
-  usbtmc_msg_dev_dep_msg_in_header_t *hdr = (usbtmc_msg_dev_dep_msg_in_header_t*)usbtmc_state.ep_bulk_in_buf;
+  usbtmc_msg_dev_dep_msg_in_header_t *hdr = (usbtmc_msg_dev_dep_msg_in_header_t*)usbtmc_epbuf.epin;
   tu_varclr(hdr);
   hdr->header.MsgID = USBTMC_MSGID_DEV_DEP_MSG_IN;
   hdr->header.bTag = usbtmc_state.lastBulkInTag;
@@ -223,7 +239,7 @@ bool tud_usbtmc_transmit_dev_msg_data(
                             len : (txBufLen - headerLen);
   const size_t packetLen = headerLen + dataLen;
 
-  memcpy((uint8_t*)(usbtmc_state.ep_bulk_in_buf) + headerLen, data, dataLen);
+  memcpy((uint8_t*)(usbtmc_epbuf.epin) + headerLen, data, dataLen);
   usbtmc_state.transfer_size_remaining = len - dataLen;
   usbtmc_state.transfer_size_sent = dataLen;
   usbtmc_state.devInBuffer = (uint8_t const*) data + (dataLen);
@@ -231,7 +247,20 @@ bool tud_usbtmc_transmit_dev_msg_data(
   bool stateChanged =
       atomicChangeState(STATE_TX_REQUESTED, (packetLen >= txBufLen) ? STATE_TX_INITIATED : STATE_TX_SHORTED);
   TU_VERIFY(stateChanged);
-  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf, (uint16_t)packetLen));
+  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, (uint16_t)packetLen));
+  return true;
+}
+
+bool tud_usbtmc_transmit_notification_data(const void * data, size_t len)
+{
+#ifndef NDEBUG
+  TU_ASSERT(len > 0);
+  TU_ASSERT(usbtmc_state.ep_int_in != 0);
+#endif
+  TU_VERIFY(usbd_edpt_busy(usbtmc_state.rhport, usbtmc_state.ep_int_in));
+
+  TU_VERIFY(tu_memcpy_s(usbtmc_epbuf.epnotif, CFG_TUD_USBTMC_INT_EP_SIZE, data, len) == 0);
+  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, usbtmc_epbuf.epnotif, (uint16_t)len));
   return true;
 }
 
@@ -255,6 +284,13 @@ void usbtmcd_init_cb(void)
   usbtmcLock = osal_mutex_create(&usbtmcLockBuffer);
 }
 
+bool usbtmcd_deinit(void) {
+  #if OSAL_MUTEX_REQUIRED
+  osal_mutex_delete(usbtmcLock);
+  #endif
+  return true;
+}
+
 uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
 {
   (void)rhport;
@@ -348,7 +384,7 @@ uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 // processing a command (such as a clear). Returns true if it was
 // in the NAK state and successfully transitioned to the ACK wait
 // state.
-bool tud_usbtmc_start_bus_read()
+bool tud_usbtmc_start_bus_read(void)
 {
   usbtmcd_state_enum oldState = usbtmc_state.state;
   switch(oldState)
@@ -362,9 +398,9 @@ bool tud_usbtmc_start_bus_read()
   case STATE_RCV:
     break;
   default:
-    TU_VERIFY(false);
+    return false;
   }
-  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, 64));
+  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_epbuf.epout, (uint16_t)usbtmc_state.ep_bulk_out_wMaxPacketSize));
   return true;
 }
 
@@ -440,7 +476,10 @@ static bool handle_devMsgIn(void *data, size_t len)
   usbtmc_state.transfer_size_sent = 0u;
 
   termCharRequested = msg->bmTransferAttributes.TermCharEnabled;
+
+#ifndef NDEBUG
   termChar = msg->TermChar;
+#endif
 
   if(termCharRequested)
     TU_VERIFY(usbtmc_state.capabilities->bmDevCapabilities.canEndBulkInOnTermChar);
@@ -464,53 +503,53 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
     switch(usbtmc_state.state)
     {
     case STATE_IDLE:
-      TU_VERIFY(xferred_bytes >= sizeof(usbtmc_msg_generic_t));
-      msg = (usbtmc_msg_generic_t*)(usbtmc_state.ep_bulk_out_buf);
-      uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse);
-      TU_VERIFY(msg->header.bTag == invInvTag);
-      TU_VERIFY(msg->header.bTag != 0x00);
+      {
+        TU_VERIFY(xferred_bytes >= sizeof(usbtmc_msg_generic_t));
+        msg = (usbtmc_msg_generic_t*)(usbtmc_epbuf.epout);
+        uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse);
+        TU_VERIFY(msg->header.bTag == invInvTag);
+        TU_VERIFY(msg->header.bTag != 0x00);
 
-      switch(msg->header.MsgID) {
-      case USBTMC_MSGID_DEV_DEP_MSG_OUT:
-        if(!handle_devMsgOutStart(rhport, msg, xferred_bytes))
-        {
-          usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
-          TU_VERIFY(false);
-        }
-        break;
+        switch(msg->header.MsgID) {
+        case USBTMC_MSGID_DEV_DEP_MSG_OUT:
+          if(!handle_devMsgOutStart(rhport, msg, xferred_bytes))
+          {
+            usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
+            return false;
+          }
+          break;
 
-      case USBTMC_MSGID_DEV_DEP_MSG_IN:
-        TU_VERIFY(handle_devMsgIn(msg, xferred_bytes));
-        break;
+        case USBTMC_MSGID_DEV_DEP_MSG_IN:
+          TU_VERIFY(handle_devMsgIn(msg, xferred_bytes));
+          break;
 
 #if (CFG_TUD_USBTMC_ENABLE_488)
-      case USBTMC_MSGID_USB488_TRIGGER:
-        // Spec says we halt the EP if we didn't declare we support it.
-        TU_VERIFY(usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger);
-        TU_VERIFY(tud_usbtmc_msg_trigger_cb(msg));
+        case USBTMC_MSGID_USB488_TRIGGER:
+          // Spec says we halt the EP if we didn't declare we support it.
+          TU_VERIFY(usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger);
+          TU_VERIFY(tud_usbtmc_msg_trigger_cb(msg));
 
-        break;
+          break;
 #endif
-      case USBTMC_MSGID_VENDOR_SPECIFIC_MSG_OUT:
-      case USBTMC_MSGID_VENDOR_SPECIFIC_IN:
-      default:
+        case USBTMC_MSGID_VENDOR_SPECIFIC_MSG_OUT:
+        case USBTMC_MSGID_VENDOR_SPECIFIC_IN:
+        default:
+          usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
+          return false;
+        }
+        return true;
+      }
+    case STATE_RCV:
+      if(!handle_devMsgOut(rhport, usbtmc_epbuf.epout, xferred_bytes, xferred_bytes))
+      {
         usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
-        TU_VERIFY(false);
         return false;
       }
       return true;
 
-    case STATE_RCV:
-      if(!handle_devMsgOut(rhport, usbtmc_state.ep_bulk_out_buf, xferred_bytes, xferred_bytes))
-      {
-        usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
-        TU_VERIFY(false);
-      }
-      return true;
-
     case STATE_ABORTING_BULK_OUT:
-      TU_VERIFY(false);
-      return false; // Should be stalled by now, shouldn't have received a packet.
+      // Should be stalled by now, shouldn't have received a packet.
+      return false;
 
     case STATE_TX_REQUESTED:
     case STATE_TX_INITIATED:
@@ -518,7 +557,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
     case STATE_ABORTING_BULK_IN_SHORTED:
     case STATE_ABORTING_BULK_IN_ABORTED:
     default:
-      TU_VERIFY(false);
+      return false;
     }
   }
   else if(ep_addr == usbtmc_state.ep_bulk_in)
@@ -530,23 +569,23 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
       break;
 
     case STATE_TX_INITIATED:
-      if(usbtmc_state.transfer_size_remaining >= sizeof(usbtmc_state.ep_bulk_in_buf))
+      if(usbtmc_state.transfer_size_remaining >= USBTMCD_BUFFER_SIZE)
       {
-        // FIXME! This removes const below!
-        TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in,
-            (void*)(uintptr_t) usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf)));
-        usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf);
-        usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf);
-        usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf);
+        // Copy buffer to ensure alignment correctness
+        memcpy(usbtmc_epbuf.epin, usbtmc_state.devInBuffer, USBTMCD_BUFFER_SIZE);
+        TU_VERIFY(usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, USBTMCD_BUFFER_SIZE));
+        usbtmc_state.devInBuffer += USBTMCD_BUFFER_SIZE;
+        usbtmc_state.transfer_size_remaining -= USBTMCD_BUFFER_SIZE;
+        usbtmc_state.transfer_size_sent += USBTMCD_BUFFER_SIZE;
       }
       else // last packet
       {
         size_t packetLen = usbtmc_state.transfer_size_remaining;
-        memcpy(usbtmc_state.ep_bulk_in_buf, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining);
+        memcpy(usbtmc_epbuf.epin, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining);
           usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining);
         usbtmc_state.transfer_size_remaining = 0;
         usbtmc_state.devInBuffer = NULL;
-        TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf, (uint16_t)packetLen) );
+        TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, (uint16_t)packetLen) );
         if(((packetLen % usbtmc_state.ep_bulk_in_wMaxPacketSize) != 0) || (packetLen == 0 ))
         {
           usbtmc_state.state = STATE_TX_SHORTED;
@@ -556,7 +595,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
 
     case STATE_ABORTING_BULK_IN:
       // need to send short packet  (ZLP?)
-      TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf,(uint16_t)0u));
+      TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin,(uint16_t)0u));
       usbtmc_state.state = STATE_ABORTING_BULK_IN_SHORTED;
       return true;
 
@@ -567,11 +606,12 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
 
     default:
       TU_ASSERT(false);
-      return false;
     }
   }
   else if (ep_addr == usbtmc_state.ep_int_in) {
-    // Good?
+    if (tud_usbtmc_notification_complete_cb) {
+      TU_VERIFY(tud_usbtmc_notification_complete_cb());
+    }
     return true;
   }
   return false;
@@ -598,8 +638,8 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
     uint32_t ep_addr = (request->wIndex);
 
     // At this point, a transfer MAY be in progress. Based on USB spec, when clearing bulk EP HALT,
-    // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if 
-    // the EP is not halted. The only USBD API interface to do this is to stall and then unstall the EP.
+    // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if
+    // the EP is not halted. The only USBD API interface to do this is to stall and then un-stall the EP.
     if(ep_addr == usbtmc_state.ep_bulk_out)
     {
       criticalEnter();
@@ -707,7 +747,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
       if(usbtmc_state.transfer_size_sent  == 0)
       {
         // Send short packet, nothing is in the buffer yet
-        TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf,(uint16_t)0u));
+        TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin,(uint16_t)0u));
         usbtmc_state.state = STATE_ABORTING_BULK_IN_SHORTED;
       }
       TU_VERIFY(tud_usbtmc_initiate_abort_bulk_in_cb(&(rsp.USBTMC_status)));
@@ -871,16 +911,13 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
   case USB488_bREQUEST_LOCAL_LOCKOUT:
     {
       TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface
-      TU_VERIFY(false);
       return false;
     }
 #endif
 
   default:
-    TU_VERIFY(false);
     return false;
   }
-  TU_VERIFY(false);
 }
 
 #endif /* CFG_TUD_TSMC */
diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h
index 144b3315d..b85ef12b5 100644
--- a/src/class/usbtmc/usbtmc_device.h
+++ b/src/class/usbtmc/usbtmc_device.h
@@ -36,7 +36,7 @@
 #endif
 
 /***********************************************
- *  Functions to be implemeted by the class implementation
+ *  Functions to be implemented by the class implementation
  */
 
 // In order to proceed, app must call call tud_usbtmc_start_bus_read(rhport) during or soon after:
@@ -73,6 +73,10 @@ bool tud_usbtmc_check_abort_bulk_in_cb(usbtmc_check_abort_bulk_rsp_t *rsp);
 bool tud_usbtmc_check_abort_bulk_out_cb(usbtmc_check_abort_bulk_rsp_t *rsp);
 bool tud_usbtmc_check_clear_cb(usbtmc_get_clear_status_rsp_t *rsp);
 
+// The interrupt-IN endpoint buffer was transmitted to the host. Use
+// tud_usbtmc_transmit_notification_data to send another notification.
+TU_ATTR_WEAK bool tud_usbtmc_notification_complete_cb(void);
+
 // Indicator pulse should be 0.5 to 1.0 seconds long
 TU_ATTR_WEAK bool tud_usbtmc_indicator_pulse_cb(tusb_control_request_t const * msg, uint8_t *tmcResult);
 
@@ -82,31 +86,33 @@ TU_ATTR_WEAK bool tud_usbtmc_msg_trigger_cb(usbtmc_msg_generic_t* msg);
 //TU_ATTR_WEAK bool tud_usbtmc_app_go_to_local_cb();
 #endif
 
-/*******************************************
- * Called from app
- *
- * We keep a reference to the buffer, so it MUST not change until the app is
- * notified that the transfer is complete.
- ******************************************/
-
+// Called from app
+//
+// We keep a reference to the buffer, so it MUST not change until the app is
+// notified that the transfer is complete.
 bool tud_usbtmc_transmit_dev_msg_data(
     const void * data, size_t len,
     bool endOfMessage, bool usingTermChar);
 
+// Buffers a notification to be sent to the host. The data starts
+// with the bNotify1 field, see the USBTMC Specification, Table 13.
+//
+// If the previous notification data has not yet been sent, this
+// returns false.
+//
+// Requires an interrupt endpoint in the interface.
+bool tud_usbtmc_transmit_notification_data(const void * data, size_t len);
+
 bool tud_usbtmc_start_bus_read(void);
 
 
 /* "callbacks" from USB device core */
 
+void     usbtmcd_init_cb(void);
+bool     usbtmcd_deinit(void);
 uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 void     usbtmcd_reset_cb(uint8_t rhport);
 bool     usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 bool     usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
-void     usbtmcd_init_cb(void);
-
-/************************************************************
- * USBTMC Descriptor Templates
- *************************************************************/
-
 
 #endif /* CLASS_USBTMC_USBTMC_DEVICE_H_ */
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 3b81a108f..6f9b4853f 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -36,172 +36,173 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;
-  uint8_t ep_in;
-  uint8_t ep_out;
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
-  tu_fifo_t rx_ff;
-  tu_fifo_t tx_ff;
+  struct {
+    tu_edpt_stream_t stream;
+    #if CFG_TUD_VENDOR_TX_BUFSIZE > 0
+    uint8_t ff_buf[CFG_TUD_VENDOR_TX_BUFSIZE];
+    #endif
+  } tx;
 
-  uint8_t rx_ff_buf[CFG_TUD_VENDOR_RX_BUFSIZE];
-  uint8_t tx_ff_buf[CFG_TUD_VENDOR_TX_BUFSIZE];
+  struct {
+    tu_edpt_stream_t stream;
+    #if CFG_TUD_VENDOR_RX_BUFSIZE > 0
+    uint8_t ff_buf[CFG_TUD_VENDOR_RX_BUFSIZE];
+    #endif
+  } rx;
 
-#if CFG_FIFO_MUTEX
-  osal_mutex_def_t rx_ff_mutex;
-  osal_mutex_def_t tx_ff_mutex;
-#endif
-
-  // Endpoint Transfer buffer
-  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_VENDOR_EPSIZE];
-  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE];
 } vendord_interface_t;
 
-CFG_TUSB_MEM_SECTION static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
+#define ITF_MEM_RESET_SIZE   (offsetof(vendord_interface_t, itf_num) + sizeof(((vendord_interface_t *)0)->itf_num))
 
-#define ITF_MEM_RESET_SIZE   offsetof(vendord_interface_t, rx_ff)
+static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
 
+typedef struct {
+  TUD_EPBUF_DEF(epout, CFG_TUD_VENDOR_EPSIZE);
+  TUD_EPBUF_DEF(epin, CFG_TUD_VENDOR_EPSIZE);
+} vendord_epbuf_t;
 
-bool tud_vendor_n_mounted (uint8_t itf)
-{
-  return _vendord_itf[itf].ep_in && _vendord_itf[itf].ep_out;
-}
+CFG_TUD_MEM_SECTION static vendord_epbuf_t _vendord_epbuf[CFG_TUD_VENDOR];
 
-uint32_t tud_vendor_n_available (uint8_t itf)
-{
-  return tu_fifo_count(&_vendord_itf[itf].rx_ff);
-}
+//--------------------------------------------------------------------
+// Application API
+//--------------------------------------------------------------------
 
-bool tud_vendor_n_peek(uint8_t itf, uint8_t* u8)
-{
-  return tu_fifo_peek(&_vendord_itf[itf].rx_ff, u8);
+bool tud_vendor_n_mounted(uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_VENDOR);
+  vendord_interface_t* p_itf = &_vendord_itf[itf];
+  return p_itf->rx.stream.ep_addr || p_itf->tx.stream.ep_addr;
 }
 
 //--------------------------------------------------------------------+
 // Read API
 //--------------------------------------------------------------------+
-static void _prep_out_transaction (vendord_interface_t* p_itf)
-{
-  uint8_t const rhport = 0;
+uint32_t tud_vendor_n_available(uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
+  vendord_interface_t* p_itf = &_vendord_itf[itf];
 
-  // skip if previous transfer not complete
-  if ( usbd_edpt_busy(rhport, p_itf->ep_out) ) return;
-
-  // Prepare for incoming data but only allow what we can store in the ring buffer.
-  uint16_t max_read = tu_fifo_remaining(&p_itf->rx_ff);
-  if ( max_read >= CFG_TUD_VENDOR_EPSIZE )
-  {
-    usbd_edpt_xfer(rhport, p_itf->ep_out, p_itf->epout_buf, CFG_TUD_VENDOR_EPSIZE);
-  }
+  return tu_edpt_stream_read_available(&p_itf->rx.stream);
 }
 
-uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize)
-{
+bool tud_vendor_n_peek(uint8_t itf, uint8_t* u8) {
+  TU_VERIFY(itf < CFG_TUD_VENDOR);
   vendord_interface_t* p_itf = &_vendord_itf[itf];
-  uint32_t num_read = tu_fifo_read_n(&p_itf->rx_ff, buffer, (uint16_t) bufsize);
-  _prep_out_transaction(p_itf);
-  return num_read;
+
+  return tu_edpt_stream_peek(&p_itf->rx.stream, u8);
 }
 
-void tud_vendor_n_read_flush (uint8_t itf)
-{
+uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize) {
+  TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
   vendord_interface_t* p_itf = &_vendord_itf[itf];
-  tu_fifo_clear(&p_itf->rx_ff);
-  _prep_out_transaction(p_itf);
+  const uint8_t rhport = 0;
+
+  return tu_edpt_stream_read(rhport, &p_itf->rx.stream, buffer, bufsize);
+}
+
+void tud_vendor_n_read_flush (uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_VENDOR, );
+  vendord_interface_t* p_itf = &_vendord_itf[itf];
+  const uint8_t rhport = 0;
+
+  tu_edpt_stream_clear(&p_itf->rx.stream);
+  tu_edpt_stream_read_xfer(rhport, &p_itf->rx.stream);
 }
 
 //--------------------------------------------------------------------+
 // Write API
 //--------------------------------------------------------------------+
-static uint16_t maybe_transmit(vendord_interface_t* p_itf)
-{
-  uint8_t const rhport = 0;
-
-  // skip if previous transfer not complete
-  TU_VERIFY( !usbd_edpt_busy(rhport, p_itf->ep_in) );
-
-  uint16_t count = tu_fifo_read_n(&p_itf->tx_ff, p_itf->epin_buf, CFG_TUD_VENDOR_EPSIZE);
-  if (count > 0)
-  {
-    TU_ASSERT( usbd_edpt_xfer(rhport, p_itf->ep_in, p_itf->epin_buf, count) );
-  }
-  return count;
-}
-
-uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize)
-{
+uint32_t tud_vendor_n_write (uint8_t itf, const void* buffer, uint32_t bufsize) {
+  TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
   vendord_interface_t* p_itf = &_vendord_itf[itf];
-  uint16_t ret = tu_fifo_write_n(&p_itf->tx_ff, buffer, (uint16_t) bufsize);
-  if (tu_fifo_count(&p_itf->tx_ff) >= CFG_TUD_VENDOR_EPSIZE) {
-    maybe_transmit(p_itf);
-  }
-  return ret;
+  const uint8_t rhport = 0;
+
+  return tu_edpt_stream_write(rhport, &p_itf->tx.stream, buffer, (uint16_t) bufsize);
 }
 
-uint32_t tud_vendor_n_flush (uint8_t itf)
-{
+uint32_t tud_vendor_n_write_flush (uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
   vendord_interface_t* p_itf = &_vendord_itf[itf];
-  uint32_t ret = maybe_transmit(p_itf);
+  const uint8_t rhport = 0;
 
-  return ret;
+  return tu_edpt_stream_write_xfer(rhport, &p_itf->tx.stream);
 }
 
-uint32_t tud_vendor_n_write_available (uint8_t itf)
-{
-  return tu_fifo_remaining(&_vendord_itf[itf].tx_ff);
+uint32_t tud_vendor_n_write_available (uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
+  vendord_interface_t* p_itf = &_vendord_itf[itf];
+  const uint8_t rhport = 0;
+
+  return tu_edpt_stream_write_available(rhport, &p_itf->tx.stream);
 }
 
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void vendord_init(void)
-{
+void vendord_init(void) {
   tu_memclr(_vendord_itf, sizeof(_vendord_itf));
 
-  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++)
-  {
+  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++) {
     vendord_interface_t* p_itf = &_vendord_itf[i];
+    vendord_epbuf_t* p_epbuf = &_vendord_epbuf[i];
 
-    // config fifo
-    tu_fifo_config(&p_itf->rx_ff, p_itf->rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, 1, false);
-    tu_fifo_config(&p_itf->tx_ff, p_itf->tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, 1, false);
+    uint8_t* rx_ff_buf =
+                        #if CFG_TUD_VENDOR_RX_BUFSIZE > 0
+                          p_itf->rx.ff_buf;
+                        #else
+                          NULL;
+                        #endif
 
-#if CFG_FIFO_MUTEX
-    tu_fifo_config_mutex(&p_itf->rx_ff, NULL, osal_mutex_create(&p_itf->rx_ff_mutex));
-    tu_fifo_config_mutex(&p_itf->tx_ff, osal_mutex_create(&p_itf->tx_ff_mutex), NULL);
-#endif
+    tu_edpt_stream_init(&p_itf->rx.stream, false, false, false,
+                        rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE,
+                        p_epbuf->epout, CFG_TUD_VENDOR_EPSIZE);
+
+    uint8_t* tx_ff_buf =
+                        #if CFG_TUD_VENDOR_TX_BUFSIZE > 0
+                          p_itf->tx.ff_buf;
+                        #else
+                          NULL;
+                        #endif
+
+    tu_edpt_stream_init(&p_itf->tx.stream, false, true, false,
+                        tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE,
+                        p_epbuf->epin, CFG_TUD_VENDOR_EPSIZE);
   }
 }
 
-void vendord_reset(uint8_t rhport)
-{
+bool vendord_deinit(void) {
+  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++) {
+    vendord_interface_t* p_itf = &_vendord_itf[i];
+    tu_edpt_stream_deinit(&p_itf->rx.stream);
+    tu_edpt_stream_deinit(&p_itf->tx.stream);
+  }
+  return true;
+}
+
+void vendord_reset(uint8_t rhport) {
   (void) rhport;
 
-  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++)
-  {
+  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++) {
     vendord_interface_t* p_itf = &_vendord_itf[i];
-
     tu_memclr(p_itf, ITF_MEM_RESET_SIZE);
-    tu_fifo_clear(&p_itf->rx_ff);
-    tu_fifo_clear(&p_itf->tx_ff);
+    tu_edpt_stream_clear(&p_itf->rx.stream);
+    tu_edpt_stream_clear(&p_itf->tx.stream);
+    tu_edpt_stream_close(&p_itf->rx.stream);
+    tu_edpt_stream_close(&p_itf->tx.stream);
   }
 }
 
-uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len)
-{
+uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint16_t max_len) {
   TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0);
-
-  uint8_t const * p_desc = tu_desc_next(desc_itf);
-  uint8_t const * desc_end = p_desc + max_len;
+  const uint8_t* p_desc = tu_desc_next(desc_itf);
+  const uint8_t* desc_end = p_desc + max_len;
 
   // Find available interface
   vendord_interface_t* p_vendor = NULL;
-  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++)
-  {
-    if ( _vendord_itf[i].ep_in == 0 && _vendord_itf[i].ep_out == 0 )
-    {
+  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++) {
+    if (!tud_vendor_n_mounted(i)) {
       p_vendor = &_vendord_itf[i];
       break;
     }
@@ -209,61 +210,72 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui
   TU_VERIFY(p_vendor, 0);
 
   p_vendor->itf_num = desc_itf->bInterfaceNumber;
-  if (desc_itf->bNumEndpoints)
-  {
+  uint8_t found_ep = 0;
+  while (found_ep < desc_itf->bNumEndpoints) {
     // skip non-endpoint descriptors
-    while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (p_desc < desc_end) )
-    {
+    while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (p_desc < desc_end) ) {
       p_desc = tu_desc_next(p_desc);
     }
-
-    // Open endpoint pair with usbd helper
-    TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0);
-
-    p_desc += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
-
-    // Prepare for incoming data
-    if ( p_vendor->ep_out )
-    {
-      TU_ASSERT(usbd_edpt_xfer(rhport, p_vendor->ep_out, p_vendor->epout_buf, sizeof(p_vendor->epout_buf)), 0);
+    if (p_desc >= desc_end) {
+      break;
     }
 
-    if ( p_vendor->ep_in ) maybe_transmit(p_vendor);
+    const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc;
+    TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
+    found_ep++;
+
+    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+      tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep);
+      tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf));
+    } else {
+      tu_edpt_stream_open(&p_vendor->rx.stream, desc_ep);
+      TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream) > 0, 0); // prepare for incoming data
+    }
+
+    p_desc = tu_desc_next(p_desc);
   }
 
   return (uint16_t) ((uintptr_t) p_desc - (uintptr_t) desc_itf);
 }
 
-bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
-  (void) rhport;
+bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) result;
 
-  uint8_t itf = 0;
-  vendord_interface_t* p_itf = _vendord_itf;
+  uint8_t itf;
+  vendord_interface_t* p_vendor;
 
-  for ( ; ; itf++, p_itf++)
-  {
-    if (itf >= TU_ARRAY_SIZE(_vendord_itf)) return false;
-
-    if ( ( ep_addr == p_itf->ep_out ) || ( ep_addr == p_itf->ep_in ) ) break;
+  for (itf = 0; itf < CFG_TUD_VENDOR; itf++) {
+    p_vendor = &_vendord_itf[itf];
+    if ((ep_addr == p_vendor->rx.stream.ep_addr) || (ep_addr == p_vendor->tx.stream.ep_addr)) {
+      break;
+    }
   }
+  TU_VERIFY(itf < CFG_TUD_VENDOR);
+  vendord_epbuf_t* p_epbuf = &_vendord_epbuf[itf];
 
-  if ( ep_addr == p_itf->ep_out )
-  {
-    // Receive new data
-    tu_fifo_write_n(&p_itf->rx_ff, p_itf->epout_buf, (uint16_t) xferred_bytes);
+  if ( ep_addr == p_vendor->rx.stream.ep_addr ) {
+    // Received new data: put into stream's fifo
+    tu_edpt_stream_read_xfer_complete(&p_vendor->rx.stream, xferred_bytes);
 
     // Invoked callback if any
-    if (tud_vendor_rx_cb) tud_vendor_rx_cb(itf);
+    if (tud_vendor_rx_cb) {
+      tud_vendor_rx_cb(itf, p_epbuf->epout, (uint16_t) xferred_bytes);
+    }
 
-    _prep_out_transaction(p_itf);
-  }
-  else if ( ep_addr == p_itf->ep_in )
-  {
-    if (tud_vendor_tx_cb) tud_vendor_tx_cb(itf, (uint16_t) xferred_bytes);
-    // Send complete, try to send more if possible
-    maybe_transmit(p_itf);
+    tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream);
+  } else if ( ep_addr == p_vendor->tx.stream.ep_addr ) {
+    // Send complete
+    if (tud_vendor_tx_cb) {
+      tud_vendor_tx_cb(itf, (uint16_t) xferred_bytes);
+    }
+
+    #if CFG_TUD_VENDOR_TX_BUFSIZE > 0
+    // try to send more if possible
+    if ( 0 == tu_edpt_stream_write_xfer(rhport, &p_vendor->tx.stream) ) {
+      // If there is no data left, a ZLP should be sent if xferred_bytes is multiple of EP Packet size and not zero
+      tu_edpt_stream_write_zlp_if_needed(rhport, &p_vendor->tx.stream, xferred_bytes);
+    }
+    #endif
   }
 
   return true;
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index 4a873e5fc..149ae2d56 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -33,46 +33,93 @@
 #define CFG_TUD_VENDOR_EPSIZE     64
 #endif
 
+// RX FIFO can be disabled by setting this value to 0
+#ifndef CFG_TUD_VENDOR_RX_BUFSIZE
+#define CFG_TUD_VENDOR_RX_BUFSIZE    64
+#endif
+
+// TX FIFO can be disabled by setting this value to 0
+#ifndef CFG_TUD_VENDOR_TX_BUFSIZE
+#define CFG_TUD_VENDOR_TX_BUFSIZE    64
+#endif
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
 //--------------------------------------------------------------------+
-// Application API (Multiple Interfaces)
+// Application API (Multiple Interfaces) i.e CFG_TUD_VENDOR > 1
 //--------------------------------------------------------------------+
 bool     tud_vendor_n_mounted         (uint8_t itf);
-
 uint32_t tud_vendor_n_available       (uint8_t itf);
 uint32_t tud_vendor_n_read            (uint8_t itf, void* buffer, uint32_t bufsize);
 bool     tud_vendor_n_peek            (uint8_t itf, uint8_t* ui8);
 void     tud_vendor_n_read_flush      (uint8_t itf);
 
 uint32_t tud_vendor_n_write           (uint8_t itf, void const* buffer, uint32_t bufsize);
+uint32_t tud_vendor_n_write_flush     (uint8_t itf);
 uint32_t tud_vendor_n_write_available (uint8_t itf);
 
-static inline
-uint32_t tud_vendor_n_write_str       (uint8_t itf, char const* str);
-uint32_t tud_vendor_n_flush           (uint8_t itf);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str);
+
+// backward compatible
+#define tud_vendor_n_flush(itf) tud_vendor_n_write_flush(itf)
 
 //--------------------------------------------------------------------+
-// Application API (Single Port)
+// Application API (Single Port) i.e CFG_TUD_VENDOR = 1
 //--------------------------------------------------------------------+
-static inline bool     tud_vendor_mounted         (void);
-static inline uint32_t tud_vendor_available       (void);
-static inline uint32_t tud_vendor_read            (void* buffer, uint32_t bufsize);
-static inline bool     tud_vendor_peek            (uint8_t* ui8);
-static inline void     tud_vendor_read_flush      (void);
-static inline uint32_t tud_vendor_write           (void const* buffer, uint32_t bufsize);
-static inline uint32_t tud_vendor_write_str       (char const* str);
-static inline uint32_t tud_vendor_write_available (void);
-static inline uint32_t tud_vendor_flush           (void);
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_n_write_str(uint8_t itf, char const* str) {
+ return tud_vendor_n_write(itf, str, strlen(str));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_vendor_mounted(void) {
+ return tud_vendor_n_mounted(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_available(void) {
+ return tud_vendor_n_available(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_read(void* buffer, uint32_t bufsize) {
+ return tud_vendor_n_read(0, buffer, bufsize);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_vendor_peek(uint8_t* ui8) {
+ return tud_vendor_n_peek(0, ui8);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tud_vendor_read_flush(void) {
+ tud_vendor_n_read_flush(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write(void const* buffer, uint32_t bufsize) {
+ return tud_vendor_n_write(0, buffer, bufsize);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_str(char const* str) {
+ return tud_vendor_n_write_str(0, str);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_flush(void) {
+ return tud_vendor_n_write_flush(0);
+}
+
+#if CFG_TUD_VENDOR_TX_BUFSIZE > 0
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_available(void) {
+ return tud_vendor_n_write_available(0);
+}
+#endif
+
+// backward compatible
+#define tud_vendor_flush() tud_vendor_write_flush()
 
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
 //--------------------------------------------------------------------+
 
 // Invoked when received new data
-TU_ATTR_WEAK void tud_vendor_rx_cb(uint8_t itf);
+TU_ATTR_WEAK void tud_vendor_rx_cb(uint8_t itf, uint8_t const* buffer, uint16_t bufsize);
 // Invoked when last rx transfer finished
 TU_ATTR_WEAK void tud_vendor_tx_cb(uint8_t itf, uint32_t sent_bytes);
 
@@ -80,60 +127,12 @@ TU_ATTR_WEAK void tud_vendor_tx_cb(uint8_t itf, uint32_t sent_bytes);
 // Inline Functions
 //--------------------------------------------------------------------+
 
-static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str)
-{
-  return tud_vendor_n_write(itf, str, strlen(str));
-}
-
-static inline bool tud_vendor_mounted (void)
-{
-  return tud_vendor_n_mounted(0);
-}
-
-static inline uint32_t tud_vendor_available (void)
-{
-  return tud_vendor_n_available(0);
-}
-
-static inline uint32_t tud_vendor_read (void* buffer, uint32_t bufsize)
-{
-  return tud_vendor_n_read(0, buffer, bufsize);
-}
-
-static inline bool tud_vendor_peek (uint8_t* ui8)
-{
-  return tud_vendor_n_peek(0, ui8);
-}
-
-static inline void tud_vendor_read_flush(void)
-{
-    tud_vendor_n_read_flush(0);
-}
-
-static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize)
-{
-  return tud_vendor_n_write(0, buffer, bufsize);
-}
-
-static inline uint32_t tud_vendor_write_str (char const* str)
-{
-  return tud_vendor_n_write_str(0, str);
-}
-
-static inline uint32_t tud_vendor_write_available (void)
-{
-  return tud_vendor_n_write_available(0);
-}
-
-static inline uint32_t tud_vendor_flush (void)
-{
-  return tud_vendor_n_flush(0);
-}
 
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     vendord_init(void);
+bool     vendord_deinit(void);
 void     vendord_reset(uint8_t rhport);
 uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
diff --git a/src/class/vendor/vendor_host.c b/src/class/vendor/vendor_host.c
index dbea1228d..e66c5007f 100644
--- a/src/class/vendor/vendor_host.c
+++ b/src/class/vendor/vendor_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/vendor/vendor_host.h b/src/class/vendor/vendor_host.h
index 65223fbca..acfebe7a4 100644
--- a/src/class/vendor/vendor_host.h
+++ b/src/class/vendor/vendor_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/video/video.h b/src/class/video/video.h
index e8227ea60..f348e187b 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -29,6 +29,10 @@
 
 #include "common/tusb_common.h"
 
+enum {
+  VIDEO_BCD_1_50 = 0x0150,
+};
+
 // Table 3-19 Color Matching Descriptor
 typedef enum {
   VIDEO_COLOR_PRIMARIES_UNDEFINED = 0x00,
@@ -156,22 +160,23 @@ typedef enum {
 /* A.9.1 VideoControl Interface Control Selectors */
 typedef enum {
   VIDEO_VC_CTL_UNDEFINED = 0x00,
-  VIDEO_VC_CTL_VIDEO_POWER_MODE,
-  VIDEO_VC_CTL_REQUEST_ERROR_CODE,
+  VIDEO_VC_CTL_VIDEO_POWER_MODE,   // 0x01
+  VIDEO_VC_CTL_REQUEST_ERROR_CODE, // 0x02
 } video_interface_control_selector_t;
 
 /* A.9.8 VideoStreaming Interface Control Selectors */
 typedef enum {
   VIDEO_VS_CTL_UNDEFINED = 0x00,
-  VIDEO_VS_CTL_PROBE,
-  VIDEO_VS_CTL_COMMIT,
-  VIDEO_VS_CTL_STILL_PROBE,
-  VIDEO_VS_CTL_STILL_COMMIT,
-  VIDEO_VS_CTL_STILL_IMAGE_TRIGGER,
-  VIDEO_VS_CTL_STREAM_ERROR_CODE,
-  VIDEO_VS_CTL_GENERATE_KEY_FRAME,
-  VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT,
-  VIDEO_VS_CTL_SYNCH_DELAY_CONTROL,
+  VIDEO_VS_CTL_PROBE,                // 0x01
+  VIDEO_VS_CTL_COMMIT,               // 0x02
+  VIDEO_VS_CTL_STILL_PROBE,          // 0x03
+  VIDEO_VS_CTL_STILL_COMMIT,         // 0x04
+  VIDEO_VS_CTL_STILL_IMAGE_TRIGGER,  // 0x05
+  VIDEO_VS_CTL_STREAM_ERROR_CODE,    // 0x06
+  VIDEO_VS_CTL_GENERATE_KEY_FRAME,   // 0x07
+  VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT, // 0x08
+  VIDEO_VS_CTL_SYNCH_DELAY_CONTROL,  // 0x09
+
 } video_interface_streaming_selector_t;
 
 /* B. Terminal Types */
@@ -198,55 +203,98 @@ typedef enum {
 } video_terminal_type_t;
 
 //--------------------------------------------------------------------+
-// Descriptors
+// Video Control (VC) Descriptors
 //--------------------------------------------------------------------+
 
 /* 2.3.4.2 */
+#define tusb_desc_video_control_header_nitf_t(_nitf) \
+  struct TU_ATTR_PACKED { \
+    uint8_t  bLength; \
+    uint8_t  bDescriptorType; \
+    uint8_t  bDescriptorSubType; \
+    uint16_t bcdUVC; \
+    uint16_t wTotalLength; \
+    uint32_t dwClockFrequency; /* deprecated */ \
+    uint8_t  bInCollection; \
+    uint8_t  baInterfaceNr[_nitf]; \
+  }
+
+typedef tusb_desc_video_control_header_nitf_t()  tusb_desc_video_control_header_t;
+typedef tusb_desc_video_control_header_nitf_t(1) tusb_desc_video_control_header_1itf_t;
+typedef tusb_desc_video_control_header_nitf_t(2) tusb_desc_video_control_header_2itf_t;
+typedef tusb_desc_video_control_header_nitf_t(3) tusb_desc_video_control_header_3itf_t;
+typedef tusb_desc_video_control_header_nitf_t(4) tusb_desc_video_control_header_4itf_t;
+
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
   uint8_t  bDescriptorSubType;
-  uint16_t bcdUVC;
-  uint16_t wTotalLength;
-  uint32_t dwClockFrequency;
-  uint8_t  bInCollection;
-  uint8_t  baInterfaceNr[];
-} tusb_desc_cs_video_ctl_itf_hdr_t;
+  uint8_t  bTerminalID;
+  uint16_t wTerminalType;
+  uint8_t  bAssocTerminal;
+  uint8_t  iTerminal;
+} tusb_desc_video_control_input_terminal_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_input_terminal_t) == 8, "size is not correct");
 
-/* 2.4.3.3 */
 typedef struct TU_ATTR_PACKED {
-  uint8_t bHeaderLength;
-  union {
-    uint8_t bmHeaderInfo;
-    struct {
-      uint8_t FrameID:              1;
-      uint8_t EndOfFrame:           1;
-      uint8_t PresentationTime:     1;
-      uint8_t SourceClockReference: 1;
-      uint8_t PayloadSpecific:      1;
-      uint8_t StillImage:           1;
-      uint8_t Error:                1;
-      uint8_t EndOfHeader:          1;
-    };
-  };
-} tusb_video_payload_header_t;
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bTerminalID;
+  uint16_t wTerminalType;
+  uint8_t  bAssocTerminal;
+  uint8_t  bSourceID;
+  uint8_t  iTerminal;
+} tusb_desc_video_control_output_terminal_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_output_terminal_t) == 9, "size is not correct");
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bTerminalID;
+  uint16_t wTerminalType;
+  uint8_t  bAssocTerminal;
+  uint8_t  iTerminal;
+
+  uint16_t wObjectiveFocalLengthMin;
+  uint16_t wObjectiveFocalLengthMax;
+  uint16_t wOcularFocalLength;
+  uint8_t  bControlSize;
+  uint8_t  bmControls[3];
+} tusb_desc_video_control_camera_terminal_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_camera_terminal_t) == 18, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Video Streaming (VS) Descriptors
+//--------------------------------------------------------------------+
 
 /* 3.9.2.1 */
-typedef struct TU_ATTR_PACKED {
-  uint8_t  bLength;
-  uint8_t  bDescriptorType;
-  uint8_t  bDescriptorSubType;
-  uint8_t  bNumFormats;
-  uint16_t wTotalLength;
-  uint8_t  bEndpointAddress;
-  uint8_t  bmInfo;
-  uint8_t  bTerminalLink;
-  uint8_t  bStillCaptureMethod;
-  uint8_t  bTriggerSupport;
-  uint8_t  bTriggerUsage;
-  uint8_t  bControlSize;
-  uint8_t  bmaControls[];
-} tusb_desc_cs_video_stm_itf_in_hdr_t;
+#define tusb_desc_video_streaming_input_header_nbyte_t(_nb) \
+  struct TU_ATTR_PACKED { \
+    uint8_t  bLength; \
+    uint8_t  bDescriptorType; \
+    uint8_t  bDescriptorSubType; \
+    uint8_t  bNumFormats; /* Number of video payload Format descriptors for this interface */ \
+    uint16_t wTotalLength; \
+    uint8_t  bEndpointAddress; \
+    uint8_t  bmInfo; /* Bit 0: dynamic format change supported */ \
+    uint8_t  bTerminalLink; \
+    uint8_t  bStillCaptureMethod; \
+    uint8_t  bTriggerSupport; /* Hardware trigger supported */ \
+    uint8_t  bTriggerUsage; \
+    uint8_t  bControlSize; /* sizeof of each control item */ \
+    uint8_t  bmaControls[_nb]; \
+  }
+
+typedef tusb_desc_video_streaming_input_header_nbyte_t() tusb_desc_video_streaming_input_header_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(1) tusb_desc_video_streaming_input_header_1byte_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(2) tusb_desc_video_streaming_input_header_2byte_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(3) tusb_desc_video_streaming_input_header_3byte_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(4) tusb_desc_video_streaming_input_header_4byte_t;
 
 /* 3.9.2.2 */
 typedef struct TU_ATTR_PACKED {
@@ -259,7 +307,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bTerminalLink;
   uint8_t  bControlSize;
   uint8_t  bmaControls[];
-} tusb_desc_cs_video_stm_itf_out_hdr_t;
+} tusb_desc_video_streaming_output_header_t;
 
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
@@ -285,14 +333,33 @@ typedef struct TU_ATTR_PACKED {
       uint8_t  bmaControls[];
     } output;
   };
-} tusb_desc_cs_video_stm_itf_hdr_t;
+} tusb_desc_video_streaming_inout_header_t;
 
+// 3.9.2.6 Color Matching Descriptor
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bColorPrimaries;
+  uint8_t  bTransferCharacteristics;
+  uint8_t  bMatrixCoefficients;
+} tusb_desc_video_streaming_color_matching_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_streaming_color_matching_t) == 6, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Format and Frame Descriptor
+// Note: bFormatIndex & bFrameIndex are 1-based index
+//--------------------------------------------------------------------+
+
+//------------- Uncompressed -------------//
+// Uncompressed payload specs: 3.1.1 format descriptor
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
   uint8_t bDescriptorSubType;
   uint8_t bFormatIndex;
-  uint8_t bNumFrameDescriptors;
+  uint8_t bNumFrameDescriptors; // Number of frame descriptors for this format
   uint8_t guidFormat[16];
   uint8_t bBitsPerPixel;
   uint8_t bDefaultFrameIndex;
@@ -300,22 +367,69 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bAspectRatioY;
   uint8_t bmInterlaceFlags;
   uint8_t bCopyProtect;
-} tusb_desc_cs_video_fmt_uncompressed_t;
+} tusb_desc_video_format_uncompressed_t;
 
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_uncompressed_t) == 27, "size is not correct");
+
+// Uncompressed payload specs: 3.1.2 frame descriptor
+#define tusb_desc_video_frame_uncompressed_nint_t(_nint) \
+  struct TU_ATTR_PACKED { \
+    uint8_t  bLength; \
+    uint8_t  bDescriptorType; \
+    uint8_t  bDescriptorSubType; \
+    uint8_t  bFrameIndex; \
+    uint8_t  bmCapabilities; \
+    uint16_t wWidth; \
+    uint16_t wHeight; \
+    uint32_t dwMinBitRate; \
+    uint32_t dwMaxBitRate; \
+    uint32_t dwMaxVideoFrameBufferSize; /* deprecated in 1.5 */ \
+    uint32_t dwDefaultFrameInterval; /* 100ns unit */\
+    uint8_t  bFrameIntervalType; \
+    uint32_t dwFrameInterval[_nint]; \
+  }
+
+typedef tusb_desc_video_frame_uncompressed_nint_t() tusb_desc_video_frame_uncompressed_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(1) tusb_desc_video_frame_uncompressed_1int_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(2) tusb_desc_video_frame_uncompressed_2int_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(3) tusb_desc_video_frame_uncompressed_3int_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(4) tusb_desc_video_frame_uncompressed_4int_t;
+
+// continuous = 3 intervals: min, max, step
+typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_uncompressed_continuous_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_frame_uncompressed_continuous_t) == 38, "size is not correct");
+
+//------------- MJPEG -------------//
+// MJPEG payload specs: 3.1.1 format descriptor
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
   uint8_t bDescriptorSubType;
   uint8_t bFormatIndex;
   uint8_t bNumFrameDescriptors;
-  uint8_t bmFlags;
+  uint8_t bmFlags; // Bit 0: fixed size samples (1 = yes)
   uint8_t bDefaultFrameIndex;
   uint8_t bAspectRatioX;
   uint8_t bAspectRatioY;
   uint8_t bmInterlaceFlags;
   uint8_t bCopyProtect;
-} tusb_desc_cs_video_fmt_mjpeg_t;
+} tusb_desc_video_format_mjpeg_t;
 
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_mjpeg_t) == 11, "size is not correct");
+
+// MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed)
+typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t;
+typedef tusb_desc_video_frame_uncompressed_1int_t tusb_desc_video_frame_mjpeg_1int_t;
+typedef tusb_desc_video_frame_uncompressed_2int_t tusb_desc_video_frame_mjpeg_2int_t;
+typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_mjpeg_3int_t;
+typedef tusb_desc_video_frame_uncompressed_4int_t tusb_desc_video_frame_mjpeg_4int_t;
+
+// continuous = 3 intervals: min, max, step
+typedef tusb_desc_video_frame_mjpeg_3int_t tusb_desc_video_frame_mjpeg_continuous_t;
+
+//------------- DV -------------//
+// DV payload specs: 3.1.1
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
@@ -323,8 +437,9 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bFormatIndex;
   uint32_t dwMaxVideoFrameBufferSize; /* deprecated */
   uint8_t  bFormatType;
-} tusb_desc_cs_video_fmt_dv_t;
+} tusb_desc_video_format_dv_t;
 
+// Frame Based payload specs: 3.1.1
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
@@ -339,25 +454,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bmInterlaceFlags;
   uint8_t bCopyProtect;
   uint8_t bVaribaleSize;
-} tusb_desc_cs_video_fmt_frame_based_t;
-
-typedef struct TU_ATTR_PACKED {
-  uint8_t  bLength;
-  uint8_t  bDescriptorType;
-  uint8_t  bDescriptorSubType;
-  uint8_t  bFrameIndex;
-  uint8_t  bmCapabilities;
-  uint16_t wWidth;
-  uint16_t wHeight;
-  uint32_t dwMinBitRate;
-  uint32_t dwMaxBitRate;
-  uint32_t dwMaxVideoFrameBufferSize; /* deprecated */
-  uint32_t dwDefaultFrameInterval;
-  uint8_t  bFrameIntervalType;
-  uint32_t dwFrameInterval[];
-} tusb_desc_cs_video_frm_uncompressed_t;
-
-typedef tusb_desc_cs_video_frm_uncompressed_t tusb_desc_cs_video_frm_mjpeg_t;
+} tusb_desc_video_format_framebased_t;
 
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
@@ -373,12 +470,30 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bFrameIntervalType;
   uint32_t dwBytesPerLine;
   uint32_t dwFrameInterval[];
-} tusb_desc_cs_video_frm_frame_based_t;
+} tusb_desc_video_frame_framebased_t;
 
 //--------------------------------------------------------------------+
 // Requests
 //--------------------------------------------------------------------+
 
+/* 2.4.3.3 */
+typedef struct TU_ATTR_PACKED {
+  uint8_t bHeaderLength;
+  union {
+    uint8_t bmHeaderInfo;
+    struct {
+      uint8_t FrameID:              1;
+      uint8_t EndOfFrame:           1;
+      uint8_t PresentationTime:     1;
+      uint8_t SourceClockReference: 1;
+      uint8_t PayloadSpecific:      1;
+      uint8_t StillImage:           1;
+      uint8_t Error:                1;
+      uint8_t EndOfHeader:          1;
+    };
+  };
+} tusb_video_payload_header_t;
+
 /* 4.3.1.1 */
 typedef struct TU_ATTR_PACKED {
   union {
@@ -425,32 +540,36 @@ typedef struct TU_ATTR_PACKED {
 
 TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not correct");
 
-#define TUD_VIDEO_DESC_IAD_LEN                    8
-#define TUD_VIDEO_DESC_STD_VC_LEN                 9
-#define TUD_VIDEO_DESC_CS_VC_LEN                  12
-#define TUD_VIDEO_DESC_INPUT_TERM_LEN             8
-#define TUD_VIDEO_DESC_OUTPUT_TERM_LEN            9
-#define TUD_VIDEO_DESC_CAMERA_TERM_LEN            18
-#define TUD_VIDEO_DESC_STD_VS_LEN                 9
-#define TUD_VIDEO_DESC_CS_VS_IN_LEN               13
-#define TUD_VIDEO_DESC_CS_VS_OUT_LEN              9
-#define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN      27
-#define TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN        11
-#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN 38
-#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN 26
-#define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN   38
-#define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC_LEN   26
-#define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN   6
+#define TUD_VIDEO_DESC_IAD_LEN                          8
+#define TUD_VIDEO_DESC_STD_VC_LEN                       9
+#define TUD_VIDEO_DESC_CS_VC_LEN                        12
+#define TUD_VIDEO_DESC_INPUT_TERM_LEN                   8
+#define TUD_VIDEO_DESC_OUTPUT_TERM_LEN                  9
+#define TUD_VIDEO_DESC_CAMERA_TERM_LEN                  18
+#define TUD_VIDEO_DESC_STD_VS_LEN                       9
+#define TUD_VIDEO_DESC_CS_VS_IN_LEN                     13
+#define TUD_VIDEO_DESC_CS_VS_OUT_LEN                    9
+#define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN            27
+#define TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN              11
+#define TUD_VIDEO_DESC_CS_VS_FMT_FRAME_BASED_LEN        28
+#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN       38
+#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN       26
+#define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN         38
+#define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC_LEN         26
+#define TUD_VIDEO_DESC_CS_VS_FRM_FRAME_BASED_CONT_LEN   38
+#define TUD_VIDEO_DESC_CS_VS_FRM_FRAME_BASED_DISC_LEN   26
+#define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN         6
 
 /* 2.2 compression formats */
 #define TUD_VIDEO_GUID_YUY2   0x59,0x55,0x59,0x32,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
 #define TUD_VIDEO_GUID_NV12   0x4E,0x56,0x31,0x32,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
 #define TUD_VIDEO_GUID_M420   0x4D,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
 #define TUD_VIDEO_GUID_I420   0x49,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
+#define TUD_VIDEO_GUID_H264   0x48,0x32,0x36,0x34,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
 
-#define TUD_VIDEO_DESC_IAD(_firstitfs, _nitfs, _stridx) \
+#define TUD_VIDEO_DESC_IAD(_firstitf, _nitfs, _stridx) \
   TUD_VIDEO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, \
-  _firstitfs, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \
+  _firstitf, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \
   VIDEO_ITF_PROTOCOL_UNDEFINED, _stridx
 
 #define TUD_VIDEO_DESC_STD_VC(_itfnum, _nEPs, _stridx) \
@@ -537,10 +656,29 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 /* Motion-JPEG 3.1.1 Table 3-2 and 3-4 */
 #define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \
   TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \
-  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_MJPEG, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_MJPEG, \
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
+/* Motion-Frame-Based 3.1.1 Table 3-1 */
+#define TUD_VIDEO_DESC_CS_VS_FMT_FRAME_BASED(_fmtidx, _numfrmdesc, _guid, _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp, _variablesize) \
+  TUD_VIDEO_DESC_CS_VS_FMT_FRAME_BASED_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED, \
+  _fmtidx, _numfrmdesc, TUD_VIDEO_GUID(_guid), _bitsperpix, _frmidx, _asrx,  _asry, _interlace, _cp, _variablesize
+
+/* Motion-Frame-Based 3.1.1 Table 3-2 and 3-3 */
+#define TUD_VIDEO_DESC_CS_VS_FRM_FRAME_BASED_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _frminterval, _bytesperline, _minfrminterval, _maxfrminterval, _frmintervalstep) \
+  TUD_VIDEO_DESC_CS_VS_FRM_FRAME_BASED_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_FRAME_BASED, \
+  _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
+  U32_TO_U8S_LE(_frminterval), 0, U32_TO_U8S_LE(_bytesperline), \
+  U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep)
+
+/* Motion-Frame-Based 3.1.1 Table 3-2 and 3-4 */
+#define TUD_VIDEO_DESC_CS_VS_FRM_FRAME_BASED_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _frminterval, _bytesperline, ...) \
+  TUD_VIDEO_DESC_CS_VS_FRM_FRAME_BASED_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_FRAME_BASED, \
+  _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
+U32_TO_U8S_LE(_frminterval), U32_TO_U8S_LE(_bytesperline), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
+
 /* 3.9.2.6 */
 #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \
   TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN, \
@@ -549,7 +687,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 
 /* 3.10.1.1 */
 #define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) \
-  7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\
+  7, TUSB_DESC_ENDPOINT, _ep, (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS),\
   U16_TO_U8S_LE(_epsize), _ep_interval
 
 /* 3.10.1.2 */
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index a6d2724c1..3124d5596 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji KITAYAMA
@@ -34,22 +34,33 @@
 
 #include "video_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_VIDEO_LOG_LEVEL
+  #define CFG_TUD_VIDEO_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_VIDEO_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
+#define VS_STATE_PROBING      0     /* Configuration in progress */
+#define VS_STATE_COMMITTED    1     /* Ready for streaming or Streaming via bulk endpoint */
+#define VS_STATE_STREAMING    2     /* Streaming via isochronous endpoint */
+
 typedef struct {
   tusb_desc_interface_t            std;
-  tusb_desc_cs_video_ctl_itf_hdr_t ctl;
+  tusb_desc_video_control_header_t ctl;
 } tusb_desc_vc_itf_t;
 
 typedef struct {
   tusb_desc_interface_t            std;
-  tusb_desc_cs_video_stm_itf_hdr_t stm;
+  tusb_desc_video_streaming_inout_header_t stm;
 } tusb_desc_vs_itf_t;
 
 typedef union {
-  tusb_desc_cs_video_ctl_itf_hdr_t ctl;
-  tusb_desc_cs_video_stm_itf_hdr_t stm;
+  tusb_desc_video_control_header_t ctl;
+  tusb_desc_video_streaming_inout_header_t stm;
 } tusb_desc_video_itf_hdr_t;
 
 typedef struct TU_ATTR_PACKED {
@@ -67,9 +78,9 @@ typedef union {
     uint8_t bFormatIndex;
     uint8_t bNumFrameDescriptors;
   };
-  tusb_desc_cs_video_fmt_uncompressed_t uncompressed;
-  tusb_desc_cs_video_fmt_mjpeg_t        mjpeg;
-  tusb_desc_cs_video_fmt_frame_based_t  frame_based;
+  tusb_desc_video_format_uncompressed_t uncompressed;
+  tusb_desc_video_format_mjpeg_t        mjpeg;
+  tusb_desc_video_format_framebased_t  frame_based;
 } tusb_desc_cs_video_fmt_t;
 
 typedef union {
@@ -82,9 +93,9 @@ typedef union {
     uint16_t wWidth;
     uint16_t wHeight;
   };
-  tusb_desc_cs_video_frm_uncompressed_t uncompressed;
-  tusb_desc_cs_video_frm_mjpeg_t        mjpeg;
-  tusb_desc_cs_video_frm_frame_based_t  frame_based;
+  tusb_desc_video_frame_uncompressed_t uncompressed;
+  tusb_desc_video_frame_mjpeg_t        mjpeg;
+  tusb_desc_video_frame_framebased_t  frame_based;
 } tusb_desc_cs_video_frm_t;
 
 /* video streaming interface */
@@ -102,42 +113,95 @@ typedef struct TU_ATTR_PACKED {
   uint32_t offset;   /* offset for the next payload transfer */
   uint32_t max_payload_transfer_size;
   uint8_t  error_code;/* error code */
-  /*------------- From this point, data is not cleared by bus reset -------------*/
-  CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE]; /* EP transfer buffer for streaming */
+  uint8_t  state;    /* 0:probing 1:committed 2:streaming */
+
+  video_probe_and_commit_control_t probe_commit_payload; /* Probe and Commit control */
 } videod_streaming_interface_t;
 
+typedef struct {
+  TUD_EPBUF_DEF(buf, CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE);
+} videod_streaming_epbuf_t;
+
 /* video control interface */
 typedef struct TU_ATTR_PACKED {
-  void const *beg;  /* The head of the first video control interface descriptor */
-  uint16_t    len;  /* Byte length of the descriptors */
-  uint16_t    cur;  /* offset for current video control interface */
-  uint8_t     stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */
-  uint8_t error_code;  /* error code */
-  uint8_t power_mode;
-
-  /*------------- From this point, data is not cleared by bus reset -------------*/
-  // CFG_TUSB_MEM_ALIGN uint8_t ctl_buf[64]; /* EP transfer buffer for interrupt transfer */
-
+  const uint8_t*beg;                     /* The head of the first video control interface descriptor */
+  uint16_t len;                          /* Byte length of the descriptors */
+  uint16_t cur;                          /* offset for current video control interface */
+  uint8_t  stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */
+  uint8_t  error_code;                   /* error code */
+  uint8_t  power_mode;
 } videod_interface_t;
 
-#define ITF_STM_MEM_RESET_SIZE   offsetof(videod_streaming_interface_t, ep_buf)
-
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
-CFG_TUSB_MEM_SECTION static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
+static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
+
+static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
+CFG_TUD_MEM_SECTION static videod_streaming_epbuf_t _videod_streaming_epbuf[CFG_TUD_VIDEO_STREAMING];
 
 static uint8_t const _cap_get     = 0x1u; /* support for GET */
 static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
 
+//--------------------------------------------------------------------+
+// Debug
+//--------------------------------------------------------------------+
+#if CFG_TUSB_DEBUG >= CFG_TUD_VIDEO_LOG_LEVEL
+
+static tu_lookup_entry_t const tu_lookup_video_request[] = {
+    {.key = VIDEO_REQUEST_UNDEFINED, .data = "Undefined"},
+    {.key = VIDEO_REQUEST_SET_CUR, .data = "SetCur"},
+    {.key = VIDEO_REQUEST_SET_CUR_ALL, .data = "SetCurAll"},
+    {.key = VIDEO_REQUEST_GET_CUR, .data = "GetCur"},
+    {.key = VIDEO_REQUEST_GET_MIN, .data = "GetMin"},
+    {.key = VIDEO_REQUEST_GET_MAX, .data = "GetMax"},
+    {.key = VIDEO_REQUEST_GET_RES, .data = "GetRes"},
+    {.key = VIDEO_REQUEST_GET_LEN, .data = "GetLen"},
+    {.key = VIDEO_REQUEST_GET_INFO, .data = "GetInfo"},
+    {.key = VIDEO_REQUEST_GET_DEF, .data = "GetDef"},
+    {.key = VIDEO_REQUEST_GET_CUR_ALL, .data = "GetCurAll"},
+    {.key = VIDEO_REQUEST_GET_MIN_ALL, .data = "GetMinAll"},
+    {.key = VIDEO_REQUEST_GET_MAX_ALL, .data = "GetMaxAll"},
+    {.key = VIDEO_REQUEST_GET_RES_ALL, .data = "GetResAll"},
+    {.key = VIDEO_REQUEST_GET_DEF_ALL, .data = "GetDefAll"},
+};
+
+static tu_lookup_table_t const tu_table_video_request = {
+    .count = TU_ARRAY_SIZE(tu_lookup_video_request),
+    .items = tu_lookup_video_request
+};
+
+static char const* const tu_str_video_vc_control_selector[] = {
+    "Undefined",
+    "Video Power Mode",
+    "Request Error Code",
+};
+
+static char const* const tu_str_video_vs_control_selector[] = {
+    "Undefined",
+    "Probe",
+    "Commit",
+    "Still Probe",
+    "Still Commit",
+    "Still Image Trigger",
+    "Stream Error Code",
+    "Generate Key Frame",
+    "Update Frame Segment",
+    "Sync Delay",
+};
+
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 /** Get interface number from the interface descriptor
  *
  * @param[in] desc    interface descriptor
  *
  * @return bInterfaceNumber */
-static inline uint8_t _desc_itfnum(void const *desc)
-{
+static inline uint8_t _desc_itfnum(void const *desc) {
   return ((uint8_t const*)desc)[2];
 }
 
@@ -146,8 +210,7 @@ static inline uint8_t _desc_itfnum(void const *desc)
  * @param[in] desc    endpoint descriptor
  *
  * @return bEndpointAddress */
-static inline uint8_t _desc_ep_addr(void const *desc)
-{
+static inline uint8_t _desc_ep_addr(void const *desc) {
   return ((uint8_t const*)desc)[2];
 }
 
@@ -157,8 +220,7 @@ static inline uint8_t _desc_ep_addr(void const *desc)
  * @param[in] stm_idx    index number of streaming interface
  *
  * @return instance */
-static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
-{
+static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) {
   videod_interface_t *ctl = &_videod_itf[ctl_idx];
   if (!ctl->beg) return NULL;
   videod_streaming_interface_t *stm = &_videod_streaming_itf[ctl->stm[stm_idx]];
@@ -166,15 +228,13 @@ static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_id
   return stm;
 }
 
-static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self)
-{
+static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) {
   return (tusb_desc_vc_itf_t const *)(self->beg + self->cur);
 }
 
-static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self)
-{
+static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self) {
   if (!self->desc.cur) return NULL;
-  void const *desc = _videod_itf[self->index_vc].beg;
+  uint8_t const *desc = _videod_itf[self->index_vc].beg;
   return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur);
 }
 
@@ -186,8 +246,7 @@ static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type)
-{
+static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type) {
   void const *cur = beg;
   while ((cur < end) && (desc_type != tu_desc_type(cur))) {
     cur = tu_desc_next(cur);
@@ -195,6 +254,24 @@ static void const* _find_desc(void const *beg, void const *end, uint_fast8_t des
   return cur;
 }
 
+/** Find the first descriptor of two given types
+ *
+ * @param[in] beg        The head of descriptor byte array.
+ * @param[in] end        The tail of descriptor byte array.
+ * @param[in] desc_type_0 The first target descriptor type.
+ * @param[in] desc_type_1 The second target descriptor type.
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* _find_desc_2_type(void const *beg, void const *end, uint_fast8_t desc_type_0, uint_fast8_t desc_type_1)
+{
+  void const *cur = beg;
+  while ((cur < end) && (desc_type_0 != tu_desc_type(cur)) && (desc_type_1 != tu_desc_type(cur))) {
+    cur = tu_desc_next(cur);
+  }
+  return cur;
+}
+
 /** Find the first descriptor specified by the arguments
  *
  * @param[in] beg        The head of descriptor byte array.
@@ -208,8 +285,7 @@ static void const* _find_desc(void const *beg, void const *end, uint_fast8_t des
 static void const* _find_desc_3(void const *beg, void const *end,
                                 uint_fast8_t desc_type,
                                 uint_fast8_t element_0,
-                                uint_fast8_t element_1)
-{
+                                uint_fast8_t element_1) {
   for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) {
     uint8_t const *p = (uint8_t const *)cur;
     if ((p[2] == element_0) && (p[3] == element_1)) {
@@ -221,19 +297,22 @@ static void const* _find_desc_3(void const *beg, void const *end,
 }
 
 /** Return the next interface descriptor which has another interface number.
+ *  If there are multiple VC interfaces, there will be an IAD descriptor before
+ *  the next interface descriptor. Check both the IAD descriptor and the interface
+ *  descriptor.
+ *  3.1 Descriptor Layout Overview
  *
  * @param[in] beg     The head of descriptor byte array.
  * @param[in] end     The tail of descriptor byte array.
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _next_desc_itf(void const *beg, void const *end)
-{
+static void const* _next_desc_itf(void const *beg, void const *end) {
   void const *cur = beg;
   uint_fast8_t itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber;
   while ((cur < end) &&
          (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) {
-    cur = _find_desc(tu_desc_next(cur), end, TUSB_DESC_INTERFACE);
+    cur = _find_desc_2_type(tu_desc_next(cur), end, TUSB_DESC_INTERFACE, TUSB_DESC_INTERFACE_ASSOCIATION);
   }
   return cur;
 }
@@ -247,9 +326,9 @@ static void const* _next_desc_itf(void const *beg, void const *end)
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static inline void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum)
+static inline uint8_t const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum)
 {
-  return _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum);
+  return (uint8_t const*) _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum);
 }
 
 /** Find the first endpoint descriptor belonging to the current interface descriptor.
@@ -275,7 +354,7 @@ static void const* _find_desc_ep(void const *beg, void const *end)
 static inline void const* _end_of_control_descriptor(void const *desc)
 {
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)desc;
-  return desc + vc->std.bLength + vc->ctl.wTotalLength;
+  return ((uint8_t const*) desc) + vc->std.bLength + tu_le16toh(vc->ctl.wTotalLength);
 }
 
 /** Find the first entity descriptor with the entity ID
@@ -305,7 +384,7 @@ static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid)
 static inline void const* _end_of_streaming_descriptor(void const *desc)
 {
   tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)desc;
-  return desc + vs->std.bLength + vs->stm.wTotalLength;
+  return ((uint8_t const*) desc) + vs->std.bLength + tu_le16toh(vs->stm.wTotalLength);
 }
 
 /** Find the first format descriptor with the specified format number. */
@@ -317,7 +396,7 @@ static inline void const *_find_desc_format(void const *beg, void const *end, ui
     if ((fmt == VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED ||
          fmt == VIDEO_CS_ITF_VS_FORMAT_MJPEG ||
          fmt == VIDEO_CS_ITF_VS_FORMAT_DV ||
-         fmt == VIDEO_CS_ITF_VS_FRAME_FRAME_BASED) &&
+         fmt == VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED) &&
         fmtnum == p[3]) {
       return cur;
     }
@@ -379,8 +458,13 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
     case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
       param->wCompQuality = 1; /* 1 to 10000 */
       break;
-  case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
+
+    case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
       break;
+
+    case VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED:
+      break;
+
     default: return false;
   }
 
@@ -401,9 +485,15 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
       case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
         frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->uncompressed.bBitsPerPixel / 8;
         break;
+
       case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
         frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */
         break;
+
+      case VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED:
+        frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */
+        break;
+
       default: break;
     }
     param->dwMaxVideoFrameSize = frame_size;
@@ -422,8 +512,9 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   uint_fast32_t interval_ms = interval / 10000;
   TU_ASSERT(interval_ms);
   uint_fast32_t payload_size = (frame_size + interval_ms - 1) / interval_ms + 2;
-  if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size)
+  if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) {
     payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE;
+  }
   param->dwMaxPayloadTransferSize = payload_size;
   return true;
 }
@@ -443,10 +534,12 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
         if (_get_desc_vs(stm))
           param->bFormatIndex = _get_desc_vs(stm)->stm.bNumFormats;
         break;
+
       case VIDEO_REQUEST_GET_MIN:
       case VIDEO_REQUEST_GET_DEF:
         param->bFormatIndex = 1;
         break;
+
       default: return false;
     }
     /* Set the parameters determined by the format  */
@@ -475,18 +568,26 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
       case VIDEO_REQUEST_GET_MAX:
         frmnum = fmt->bNumFrameDescriptors;
         break;
+
       case VIDEO_REQUEST_GET_MIN:
         frmnum = 1;
         break;
+
       case VIDEO_REQUEST_GET_DEF:
         switch (fmt->bDescriptorSubType) {
-        case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
-          frmnum = fmt->uncompressed.bDefaultFrameIndex;
-          break;
-        case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
-          frmnum = fmt->mjpeg.bDefaultFrameIndex;
-          break;
-        default: return false;
+          case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
+            frmnum = fmt->uncompressed.bDefaultFrameIndex;
+            break;
+
+          case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
+            frmnum = fmt->mjpeg.bDefaultFrameIndex;
+            break;
+
+          case VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED:
+            frmnum = fmt->frame_based.bDefaultFrameIndex;
+            break;
+
+          default: return false;
         }
         break;
       default: return false;
@@ -499,9 +600,15 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
       case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
         frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->uncompressed.bBitsPerPixel / 8;
         break;
+
       case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
         frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */
         break;
+
+      case VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED:
+        frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */
+        break;
+
       default: return false;
     }
     param->dwMaxVideoFrameSize = frame_size;
@@ -517,41 +624,43 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
 
     uint_fast32_t interval, interval_ms;
     switch (request) {
-      case VIDEO_REQUEST_GET_MAX:
-        {
-          uint_fast32_t min_interval, max_interval;
-          uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
-          max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
-          min_interval = frm->uncompressed.dwFrameInterval[0];
-          interval = max_interval;
-          interval_ms = min_interval / 10000;
-        }
+      case VIDEO_REQUEST_GET_MAX: {
+        uint_fast32_t min_interval, max_interval;
+        uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
+        max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
+        min_interval = frm->uncompressed.dwFrameInterval[0];
+        interval = max_interval;
+        interval_ms = min_interval / 10000;
         break;
-      case VIDEO_REQUEST_GET_MIN:
-        {
-          uint_fast32_t min_interval, max_interval;
-          uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
-          max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
-          min_interval = frm->uncompressed.dwFrameInterval[0];
-          interval = min_interval;
-          interval_ms = max_interval / 10000;
-        }
+      }
+
+      case VIDEO_REQUEST_GET_MIN: {
+        uint_fast32_t min_interval, max_interval;
+        uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
+        max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
+        min_interval = frm->uncompressed.dwFrameInterval[0];
+        interval = min_interval;
+        interval_ms = max_interval / 10000;
         break;
+      }
+
       case VIDEO_REQUEST_GET_DEF:
         interval = frm->uncompressed.dwDefaultFrameInterval;
         interval_ms = interval / 10000;
         break;
-      case VIDEO_REQUEST_GET_RES:
-        {
-          uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
-          if (num_intervals) {
-            interval = 0;
-          } else {
-            interval = frm->uncompressed.dwFrameInterval[2];
-            interval_ms = interval / 10000;
-          }
+
+      case VIDEO_REQUEST_GET_RES: {
+        uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
+        if (num_intervals) {
+          interval = 0;
+          interval_ms = 0;
+        } else {
+          interval = frm->uncompressed.dwFrameInterval[2];
+          interval_ms = interval / 10000;
         }
         break;
+      }
+
       default: return false;
     }
     param->dwFrameInterval = interval;
@@ -565,8 +674,9 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
       } else {
         payload_size = (frame_size + interval_ms - 1) / interval_ms + 2;
       }
-      if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size)
+      if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) {
         payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE;
+      }
       param->dwMaxPayloadTransferSize = payload_size;
     }
     return true;
@@ -581,8 +691,10 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
 static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
 {
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
+
   /* The next descriptor after the class-specific VC interface header descriptor. */
-  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength;
+  void const *cur = (uint8_t const*)vc + vc->std.bLength + vc->ctl.bLength;
+
   /* The end of the video control interface descriptor. */
   void const *end = _end_of_control_descriptor(vc);
   if (vc->std.bNumEndpoints) {
@@ -602,24 +714,26 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
-  TU_LOG2("    open VC %d\n", altnum);
-  void const *beg = self->beg;
-  void const *end = beg + self->len;
+  TU_LOG_DRV("    open VC %d\r\n", altnum);
+  uint8_t const *beg = self->beg;
+  uint8_t const *end = beg + self->len;
+
   /* The first descriptor is a video control interface descriptor. */
-  void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
-  TU_LOG2("    cur %d\n", cur - beg);
+  uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
+  TU_LOG_DRV("    cur %" PRId32 "\r\n", (int32_t) (cur - beg));
   TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
-  TU_LOG2("    bInCollection %d\n", vc->ctl.bInCollection);
+  TU_LOG_DRV("    bInCollection %d\r\n", vc->ctl.bInCollection);
   /* Support for up to 2 streaming interfaces only. */
   TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING);
 
   /* Update to point the end of the video control interface descriptor. */
-  end  = _end_of_control_descriptor(cur);
+  end = _end_of_control_descriptor(cur);
+
   /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
   cur += vc->std.bLength + vc->ctl.bLength;
-  TU_LOG2("    bNumEndpoints %d\n", vc->std.bNumEndpoints);
+  TU_LOG_DRV("    bNumEndpoints %d\r\n", vc->std.bNumEndpoints);
   /* Open the notification endpoint if it exist. */
   if (vc->std.bNumEndpoints) {
     /* Support for 1 endpoint only. */
@@ -631,10 +745,19 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
     /* Open the notification endpoint */
     TU_ASSERT(usbd_edpt_open(rhport, notif));
   }
-  self->cur = (uint16_t) ((void const*)vc - beg);
+  self->cur = (uint16_t) ((uint8_t const*)vc - beg);
   return true;
 }
 
+static bool _init_vs_configuration(videod_streaming_interface_t *stm) {
+  /* initialize streaming settings */
+  stm->state = VS_STATE_PROBING;
+  stm->max_payload_transfer_size = 0;
+  video_probe_and_commit_control_t *param = &stm->probe_commit_payload;
+  tu_memclr(param, sizeof(*param));
+  return _update_streaming_parameters(stm, param);
+}
+
 /** Set the alternate setting to own video streaming interface.
  *
  * @param[in,out] stm      Streaming interface context.
@@ -642,85 +765,84 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
 static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum)
 {
   uint_fast8_t i;
-  TU_LOG2("    reopen VS %d\n", altnum);
-  void const *desc = _videod_itf[stm->index_vc].beg;
+  TU_LOG_DRV("    reopen VS %d\r\n", altnum);
+  uint8_t const *desc = _videod_itf[stm->index_vc].beg;
 
+#ifndef TUP_DCD_EDPT_ISO_ALLOC
   /* Close endpoints of previous settings. */
   for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) {
     uint_fast16_t ofs_ep = stm->desc.ep[i];
     if (!ofs_ep) break;
-    uint8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
-    usbd_edpt_close(rhport, ep_adr);
-    stm->desc.ep[i] = 0;
-    TU_LOG2("    close EP%02x\n", ep_adr);
+    tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)(desc + ofs_ep);
+    /* Only ISO endpoints needs to be closed */
+    if(ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
+      stm->desc.ep[i] = 0;
+      usbd_edpt_close(rhport, ep->bEndpointAddress);
+      TU_LOG_DRV("    close EP%02x\r\n", ep->bEndpointAddress);
+    }
   }
+#endif
+
   /* clear transfer management information */
   stm->buffer  = NULL;
   stm->bufsize = 0;
   stm->offset  = 0;
 
   /* Find a alternate interface */
-  void const *beg = desc + stm->desc.beg;
-  void const *end = desc + stm->desc.end;
-  void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
+  uint8_t const *beg = desc + stm->desc.beg;
+  uint8_t const *end = desc + stm->desc.end;
+  uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
   TU_VERIFY(cur < end);
+
   uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints;
   TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep));
-  stm->desc.cur = (uint16_t) (cur - desc); /* Save the offset of the new settings */
-  if (!altnum) {
-    /* initialize streaming settings */
-    stm->max_payload_transfer_size = 0;
-    video_probe_and_commit_control_t *param =
-      (video_probe_and_commit_control_t *)&stm->ep_buf;
-    tu_memclr(param, sizeof(*param));
-    TU_LOG2("    done 0\n");
-    return _update_streaming_parameters(stm, param);
+  stm->desc.cur = (uint16_t)(cur - desc); /* Save the offset of the new settings */
+  if (!altnum && (VS_STATE_COMMITTED != stm->state)) {
+    TU_VERIFY(_init_vs_configuration(stm));
   }
-  /* Open endpoints of the new settings. */
+  /* Open bulk or isochronous endpoints of the new settings. */
   for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) {
     cur = _find_desc_ep(cur, end);
     TU_ASSERT(cur < end);
     tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur;
-    if (!stm->max_payload_transfer_size) {
-      video_probe_and_commit_control_t const *param = (video_probe_and_commit_control_t const*)&stm->ep_buf;
-      uint_fast32_t max_size = param->dwMaxPayloadTransferSize;
-      if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) &&
-          (tu_edpt_packet_size(ep) < max_size))
-      {
-        /* FS must be less than or equal to max packet size */
-        return false;
-      }
-      /* Set the negotiated value */
-      stm->max_payload_transfer_size = max_size;
+    uint_fast32_t max_size = stm->max_payload_transfer_size;
+    if (altnum && (TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer)) {
+      /* FS must be less than or equal to max packet size */
+      TU_VERIFY (tu_edpt_packet_size(ep) >= max_size);
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+      usbd_edpt_iso_activate(rhport, ep);
+#else
+      TU_ASSERT(usbd_edpt_open(rhport, ep));
+#endif
+    } else {
+      TU_VERIFY(TUSB_XFER_BULK == ep->bmAttributes.xfer);
+      TU_ASSERT(usbd_edpt_open(rhport, ep));
     }
-    TU_ASSERT(usbd_edpt_open(rhport, ep));
     stm->desc.ep[i] = (uint16_t) (cur - desc);
-    TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
+    TU_LOG_DRV("    open EP%02x\r\n", _desc_ep_addr(cur));
   }
-  /* initialize payload header */
-  tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
-  hdr->bHeaderLength = sizeof(*hdr);
-  hdr->bmHeaderInfo  = 0;
-
-  TU_LOG2("    done\n");
+  if (altnum) {
+    stm->state = VS_STATE_STREAMING;
+  }
+  TU_LOG_DRV("    done\r\n");
   return true;
 }
 
 /** Prepare the next packet payload. */
-static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm)
-{
+static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm, uint8_t* ep_buf) {
   uint_fast16_t remaining = stm->bufsize - stm->offset;
-  uint_fast16_t hdr_len   = stm->ep_buf[0];
+  uint_fast16_t hdr_len   = ep_buf[0];
   uint_fast16_t pkt_len   = stm->max_payload_transfer_size;
   if (hdr_len + remaining < pkt_len) {
     pkt_len = hdr_len + remaining;
   }
+  TU_ASSERT(pkt_len >= hdr_len);
   uint_fast16_t data_len = pkt_len - hdr_len;
-  memcpy(&stm->ep_buf[hdr_len], stm->buffer + stm->offset, data_len);
+  memcpy(&ep_buf[hdr_len], stm->buffer + stm->offset, data_len);
   stm->offset += data_len;
   remaining -= data_len;
   if (!remaining) {
-    tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
+    tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*) ep_buf;
     hdr->EndOfFrame = 1;
   }
   return hdr_len + data_len;
@@ -731,6 +853,7 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage,
                                     tusb_control_request_t const *request,
                                     uint_fast8_t ctl_idx)
 {
+  TU_LOG_DRV("\r\n");
   switch (request->bRequest) {
     case TUSB_REQ_GET_INTERFACE:
       if (stage == CONTROL_STAGE_SETUP)
@@ -768,7 +891,10 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage,
   videod_interface_t *self = &_videod_itf[ctl_idx];
 
   /* 4.2.1 Interface Control Request */
-  switch (TU_U16_HIGH(request->wValue)) {
+  uint8_t const ctrl_sel = TU_U16_HIGH(request->wValue);
+  TU_LOG_DRV("%s_Control(%s)\r\n",  tu_str_video_vc_control_selector[ctrl_sel], tu_lookup_find(&tu_table_video_request, request->bRequest));
+
+  switch (ctrl_sel) {
     case VIDEO_VC_CTL_VIDEO_POWER_MODE:
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
@@ -832,19 +958,19 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage,
                                 tusb_control_request_t const *request,
                                 uint_fast8_t ctl_idx)
 {
-  uint_fast8_t entity_id;
   switch (request->bmRequestType_bit.type) {
     case TUSB_REQ_TYPE_STANDARD:
       return handle_video_ctl_std_req(rhport, stage, request, ctl_idx);
 
-    case TUSB_REQ_TYPE_CLASS:
-      entity_id = TU_U16_HIGH(request->wIndex);
+    case TUSB_REQ_TYPE_CLASS: {
+      uint_fast8_t entity_id = TU_U16_HIGH(request->wIndex);
       if (!entity_id) {
         return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx);
       } else {
         TU_VERIFY(_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id), VIDEO_ERROR_INVALID_REQUEST);
         return VIDEO_ERROR_NONE;
       }
+    }
 
     default:
       return VIDEO_ERROR_INVALID_REQUEST;
@@ -855,6 +981,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
                                     tusb_control_request_t const *request,
                                     uint_fast8_t stm_idx)
 {
+  TU_LOG_DRV("\r\n");
   videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx];
   switch (request->bRequest) {
     case TUSB_REQ_GET_INTERFACE:
@@ -870,8 +997,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
       return VIDEO_ERROR_NONE;
 
     case TUSB_REQ_SET_INTERFACE:
-      if (stage == CONTROL_STAGE_SETUP)
-      {
+      if (stage == CONTROL_STAGE_SETUP) {
         TU_VERIFY(_open_vs_itf(rhport, self, request->wValue), VIDEO_ERROR_UNKNOWN);
         tud_control_status(rhport, request);
       }
@@ -885,26 +1011,27 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
 
 static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
                                    tusb_control_request_t const *request,
-                                   uint_fast8_t stm_idx)
-{
+                                   uint_fast8_t stm_idx) {
   (void)rhport;
-  videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx];
+  videod_streaming_interface_t *stm = &_videod_streaming_itf[stm_idx];
+  videod_streaming_epbuf_t *stm_epbuf = &_videod_streaming_epbuf[stm_idx];
+
+  uint8_t const ctrl_sel = TU_U16_HIGH(request->wValue);
+  TU_LOG_DRV("%s_Control(%s)\r\n", tu_str_video_vs_control_selector[ctrl_sel], tu_lookup_find(&tu_table_video_request, request->bRequest));
 
   /* 4.2.1 Interface Control Request */
-  switch (TU_U16_HIGH(request->wValue)) {
+  switch (ctrl_sel) {
     case VIDEO_VS_CTL_STREAM_ERROR_CODE:
       switch (request->bRequest) {
         case VIDEO_REQUEST_GET_CUR:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             /* TODO */
-            TU_VERIFY(tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &stm->error_code, sizeof(uint8_t)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_INFO:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
@@ -914,23 +1041,25 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
       break;
 
     case VIDEO_VS_CTL_PROBE:
+      if (stm->state != VS_STATE_PROBING) {
+        stm->state = VS_STATE_PROBING;
+      }
+
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
-            TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)),
+            TU_VERIFY(tud_control_xfer(rhport, request, &stm->probe_commit_payload, sizeof(video_probe_and_commit_control_t)),
                       VIDEO_ERROR_UNKNOWN);
           } else if (stage == CONTROL_STAGE_DATA) {
-            TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf),
+            TU_VERIFY(_update_streaming_parameters(stm, &stm->probe_commit_payload),
                       VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
           }
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_CUR:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &stm->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
@@ -938,19 +1067,16 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
         case VIDEO_REQUEST_GET_MAX:
         case VIDEO_REQUEST_GET_RES:
         case VIDEO_REQUEST_GET_DEF:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-            video_probe_and_commit_control_t tmp;
-            tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
-            TU_VERIFY(_negotiate_streaming_parameters(self, request->bRequest, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            video_probe_and_commit_control_t tmp = stm->probe_commit_payload;
+            TU_VERIFY(_negotiate_streaming_parameters(stm, request->bRequest, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
             TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(tmp)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_LEN:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN);
             uint16_t len = sizeof(video_probe_and_commit_control_t);
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN);
@@ -958,8 +1084,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_INFO:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
           }
@@ -973,27 +1098,38 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
-            TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &stm->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           } else if (stage == CONTROL_STAGE_DATA) {
-            TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            video_probe_and_commit_control_t *param = &stm->probe_commit_payload;
+            TU_VERIFY(_update_streaming_parameters(stm, param), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            /* Set the negotiated value */
+            stm->max_payload_transfer_size = param->dwMaxPayloadTransferSize;
+            int ret = VIDEO_ERROR_NONE;
             if (tud_video_commit_cb) {
-              return tud_video_commit_cb(self->index_vc, self->index_vs, (video_probe_and_commit_control_t*)self->ep_buf);
+              ret = tud_video_commit_cb(stm->index_vc, stm->index_vs, param);
+            }
+            if (VIDEO_ERROR_NONE == ret) {
+              stm->state   = VS_STATE_COMMITTED;
+              stm->buffer  = NULL;
+              stm->bufsize = 0;
+              stm->offset  = 0;
+              /* initialize payload header */
+              tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm_epbuf->buf;
+              hdr->bHeaderLength = sizeof(*hdr);
+              hdr->bmHeaderInfo  = 0;
             }
           }
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_CUR:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &stm->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_LEN:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN);
             uint16_t len = sizeof(video_probe_and_commit_control_t);
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN);
@@ -1001,8 +1137,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_INFO:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
           }
@@ -1043,7 +1178,6 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage,
 
     default: return VIDEO_ERROR_INVALID_REQUEST;
   }
-  return VIDEO_ERROR_UNKNOWN;
 }
 
 //--------------------------------------------------------------------+
@@ -1064,19 +1198,33 @@ bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
   TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING);
   videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
   if (!stm || !stm->desc.ep[0]) return false;
+  if (stm->state == VS_STATE_PROBING) return false;
+
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+  uint8_t const *desc = _videod_itf[stm->index_vc].beg;
+  uint_fast16_t ofs_ep = stm->desc.ep[0];
+  tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)(desc + ofs_ep);
+  if (ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
+    if (stm->state == VS_STATE_COMMITTED) return false;
+  }
+#endif
+
   return true;
 }
 
-bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *buffer, size_t bufsize)
-{
+bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *buffer, size_t bufsize) {
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
   TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING);
+
   if (!buffer || !bufsize) return false;
   videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
+  videod_streaming_epbuf_t *stm_epbuf = &_videod_streaming_epbuf[ctl_idx];
+
   if (!stm || !stm->desc.ep[0] || stm->buffer) return false;
+  if (stm->state == VS_STATE_PROBING) return false;
 
   /* Find EP address */
-  void const *desc = _videod_itf[stm->index_vc].beg;
+  uint8_t const *desc = _videod_itf[stm->index_vc].beg;
   uint8_t ep_addr = 0;
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
     uint_fast16_t ofs_ep = stm->desc.ep[i];
@@ -1088,34 +1236,36 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
 
   TU_VERIFY( usbd_edpt_claim(0, ep_addr) );
   /* update the packet header */
-  tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
+  tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm_epbuf->buf;
   hdr->FrameID   ^= 1;
   hdr->EndOfFrame = 0;
   /* update the packet data */
   stm->buffer     = (uint8_t*)buffer;
   stm->bufsize    = bufsize;
-  uint_fast16_t pkt_len = _prepare_in_payload(stm);
-  TU_ASSERT( usbd_edpt_xfer(0, ep_addr, stm->ep_buf, (uint16_t) pkt_len), 0);
+  uint_fast16_t pkt_len = _prepare_in_payload(stm, stm_epbuf->buf);
+  TU_ASSERT( usbd_edpt_xfer(0, ep_addr, stm_epbuf->buf, (uint16_t) pkt_len), 0);
   return true;
 }
 
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void videod_init(void)
-{
+void videod_init(void) {
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) {
     videod_interface_t* ctl = &_videod_itf[i];
     tu_memclr(ctl, sizeof(*ctl));
   }
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
     videod_streaming_interface_t *stm = &_videod_streaming_itf[i];
-    tu_memclr(stm, ITF_STM_MEM_RESET_SIZE);
+    tu_memclr(stm, sizeof(videod_streaming_interface_t));
   }
 }
 
-void videod_reset(uint8_t rhport)
-{
+bool videod_deinit(void) {
+  return true;
+}
+
+void videod_reset(uint8_t rhport) {
   (void) rhport;
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) {
     videod_interface_t* ctl = &_videod_itf[i];
@@ -1123,12 +1273,11 @@ void videod_reset(uint8_t rhport)
   }
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
     videod_streaming_interface_t *stm = &_videod_streaming_itf[i];
-    tu_memclr(stm, ITF_STM_MEM_RESET_SIZE);
+    tu_memclr(stm, sizeof(videod_streaming_interface_t));
   }
 }
 
-uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
+uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) {
   TU_VERIFY((TUSB_CLASS_VIDEO       == itf_desc->bInterfaceClass) &&
             (VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass) &&
             (VIDEO_ITF_PROTOCOL_15  == itf_desc->bInterfaceProtocol), 0);
@@ -1143,13 +1292,15 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   }
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO, 0);
 
-  void const *end = (void const*)itf_desc + max_len;
-  self->beg = itf_desc;
+  uint8_t const *end = (uint8_t const*)itf_desc + max_len;
+  self->beg = (uint8_t const*) itf_desc;
   self->len = max_len;
+
   /*------------- Video Control Interface -------------*/
   TU_VERIFY(_open_vc_itf(rhport, self, 0), 0);
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   uint_fast8_t bInCollection   = vc->ctl.bInCollection;
+
   /* Find the end of the video interface descriptor */
   void const *cur = _next_desc_itf(itf_desc, end);
   for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) {
@@ -1167,6 +1318,34 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
     stm->desc.beg = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
     cur = _next_desc_itf(cur, end);
     stm->desc.end = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
+    stm->state = VS_STATE_PROBING;
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+    /* Allocate ISO endpoints */
+    uint16_t ep_size = 0;
+    uint8_t ep_addr = 0;
+    uint8_t const *p_desc = (uint8_t const*)itf_desc + stm->desc.beg;
+    uint8_t const *p_desc_end = (uint8_t const*)itf_desc + stm->desc.end;
+    while (p_desc < p_desc_end) {
+      if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) {
+        tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+        if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
+              ep_addr = desc_ep->bEndpointAddress;
+              ep_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_size);
+        }
+      }
+      p_desc = tu_desc_next(p_desc);
+    }
+    if(ep_addr > 0 && ep_size > 0) usbd_edpt_iso_alloc(rhport, ep_addr, ep_size);
+#endif
+    if (0 == stm_idx && 1 == bInCollection) {
+      /* If there is only one streaming interface and no alternate settings,
+       * host may not issue set_interface so open the streaming interface here. */
+      uint8_t const *sbeg = (uint8_t const*)itf_desc + stm->desc.beg;
+      uint8_t const *send = (uint8_t const*)itf_desc + stm->desc.end;
+      if (send == _find_desc_itf(sbeg, send, _desc_itfnum(sbeg), 1)) {
+        TU_VERIFY(_open_vs_itf(rhport, stm, 0), 0);
+      }
+    }
   }
   self->len = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
   return (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
@@ -1175,12 +1354,10 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
+bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) {
   int err;
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
   uint_fast8_t itfnum = tu_u16_low(request->wIndex);
-
   /* Identify which control interface to use */
   uint_fast8_t itf;
   for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
@@ -1190,6 +1367,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   }
 
   if (itf < CFG_TUD_VIDEO) {
+    TU_LOG_DRV("  VC[%d]: ", itf);
     err = handle_video_ctl_req(rhport, stage, request, itf);
     _videod_itf[itf].error_code = (uint8_t)err;
     if (err) return false;
@@ -1200,11 +1378,12 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) {
     videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
     if (!stm->desc.beg) continue;
-    void const *desc = _videod_itf[stm->index_vc].beg;
+    uint8_t const *desc = _videod_itf[stm->index_vc].beg;
     if (itfnum == _desc_itfnum(desc + stm->desc.beg)) break;
   }
 
   if (itf < CFG_TUD_VIDEO_STREAMING) {
+    TU_LOG_DRV("  VS[%d]: ", itf);
     err = handle_video_stm_req(rhport, stage, request, itf);
     _videod_streaming_itf[itf].error_code = (uint8_t)err;
     if (err) return false;
@@ -1213,8 +1392,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   return false;
 }
 
-bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void)result; (void)xferred_bytes;
 
   /* find streaming handle */
@@ -1226,16 +1404,17 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     uint_fast16_t const ep_ofs = stm->desc.ep[0];
     if (!ep_ofs) continue;
     ctl = &_videod_itf[stm->index_vc];
-    void const *desc = ctl->beg;
+    uint8_t const *desc = ctl->beg;
     if (ep_addr == _desc_ep_addr(desc + ep_ofs)) break;
   }
-
   TU_ASSERT(itf < CFG_TUD_VIDEO_STREAMING);
+  videod_streaming_epbuf_t *stm_epbuf = &_videod_streaming_epbuf[itf];
+
   if (stm->offset < stm->bufsize) {
     /* Claim the endpoint */
     TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0);
-    uint_fast16_t pkt_len = _prepare_in_payload(stm);
-    TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, (uint16_t) pkt_len), 0);
+    uint_fast16_t pkt_len = _prepare_in_payload(stm, stm_epbuf->buf);
+    TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm_epbuf->buf, (uint16_t) pkt_len), 0);
   } else {
     stm->buffer  = NULL;
     stm->bufsize = 0;
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index ee2fcb9d5..648a221d5 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -40,6 +40,8 @@ extern "C" {
 // CFG_TUD_VIDEO > 1
 //--------------------------------------------------------------------+
 
+bool tud_video_n_connected(uint_fast8_t ctl_idx);
+
 /** Return true if streaming
  *
  * @param[in] ctl_idx    Destination control interface index
@@ -85,6 +87,7 @@ TU_ATTR_WEAK int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+
 void     videod_init           (void);
+bool     videod_deinit         (void);
 void     videod_reset          (uint8_t rhport);
 uint16_t videod_open           (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index b1ee40a1a..74cac965d 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -37,6 +37,7 @@
 #define TU_ARRAY_SIZE(_arr)   ( sizeof(_arr) / sizeof(_arr[0]) )
 #define TU_MIN(_x, _y)        ( ( (_x) < (_y) ) ? (_x) : (_y) )
 #define TU_MAX(_x, _y)        ( ( (_x) > (_y) ) ? (_x) : (_y) )
+#define TU_DIV_CEIL(n, d)     (((n) + (d) - 1) / (d))
 
 #define TU_U16(_high, _low)   ((uint16_t) (((_high) << 8) | (_low)))
 #define TU_U16_HIGH(_u16)     ((uint8_t) (((_u16) >> 8) & 0x00ff))
@@ -53,6 +54,8 @@
 #define U32_TO_U8S_LE(_u32)   TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32)
 
 #define TU_BIT(n)             (1UL << (n))
+
+// Generate a mask with bit from high (31) to low (0) set, e.g TU_GENMASK(3, 0) = 0b1111
 #define TU_GENMASK(h, l)      ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) )
 
 //--------------------------------------------------------------------+
@@ -62,6 +65,7 @@
 // Standard Headers
 #include <stdbool.h>
 #include <stdint.h>
+#include <inttypes.h>
 #include <stddef.h>
 #include <string.h>
 #include <stdio.h>
@@ -73,7 +77,20 @@
 #include "tusb_types.h"
 #include "tusb_debug.h"
 
-#include "tusb_timeout.h" // TODO remove
+//--------------------------------------------------------------------+
+// Optional API implemented by application if needed
+// TODO move to a more obvious place/file
+//--------------------------------------------------------------------+
+
+// flush data cache
+TU_ATTR_WEAK extern void tusb_app_dcache_flush(uintptr_t addr, uint32_t data_size);
+
+// invalidate data cache
+TU_ATTR_WEAK extern void tusb_app_dcache_invalidate(uintptr_t addr, uint32_t data_size);
+
+// Optional physical <-> virtual address translation
+TU_ATTR_WEAK extern void* tusb_app_virt_to_phys(void *virt_addr);
+TU_ATTR_WEAK extern void* tusb_app_phys_to_virt(void *phys_addr);
 
 //--------------------------------------------------------------------+
 // Internal Inline Functions
@@ -83,15 +100,38 @@
 #define tu_memclr(buffer, size)  memset((buffer), 0, (size))
 #define tu_varclr(_var)          tu_memclr(_var, sizeof(*(_var)))
 
-//------------- Bytes -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0)
-{
-  return ( ((uint32_t) b3) << 24) | ( ((uint32_t) b2) << 16) | ( ((uint32_t) b1) << 8) | b0;
+// This is a backport of memset_s from c11
+TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count) {
+  // TODO may check if desst and src is not NULL
+  if ( count > destsz ) {
+    return -1;
+  }
+  memset(dest, ch, count);
+  return 0;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low)
-{
-  return (uint16_t) ((((uint16_t) high) << 8) | low);
+// This is a backport of memcpy_s from c11
+TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, const void *src, size_t count) {
+  // TODO may check if desst and src is not NULL
+  if ( count > destsz ) {
+    return -1;
+  }
+  memcpy(dest, src, count);
+  return 0;
+}
+
+
+//------------- Bytes -------------//
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) {
+  return (((uint32_t)b3) << 24) | (((uint32_t)b2) << 16) | (((uint32_t)b1) << 8) | b0;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32_from_u16(uint16_t high, uint16_t low) {
+  return (((uint32_t)high) << 16) | low;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) {
+  return (uint16_t)((((uint16_t)high) << 8) | low);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t ui32) { return TU_U32_BYTE3(ui32); }
@@ -121,18 +161,23 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_max16 (uint16_t x, uint16_t y) {
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_max32 (uint32_t x, uint32_t y) { return (x > y) ? x : y; }
 
 //------------- Align -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment) {
   return value & ((uint32_t) ~(alignment-1));
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4  (uint32_t value) { return (value & 0xFFFFFFFCUL); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align8  (uint32_t value) { return (value & 0xFFFFFFF8UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); }
 
+TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned32(uint32_t value) { return (value & 0x1FUL) == 0; }
+TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned64(uint64_t value) { return (value & 0x3FUL) == 0; }
+
 //------------- Mathematics -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return TU_DIV_CEIL(v, d); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_round_up(uint32_t v, uint32_t f) { return tu_div_ceil(v, f) * f; }
 
 // log2 of a value is its MSB's position
 // TODO use clz TODO remove
@@ -222,11 +267,21 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_
 #else
 
 // MCU that could access unaligned memory natively
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32  (const void* mem) { return *((uint32_t const *) mem); }
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16  (const void* mem) { return *((uint16_t const *) mem); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) {
+  return *((uint32_t const *) mem);
+}
 
-TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; }
-TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) {
+  return *((uint16_t const *) mem);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) {
+  *((uint32_t *) mem) = value;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) {
+  *((uint16_t *) mem) = value;
+}
 
 #endif
 
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 2c30daf6f..9b33a6f61 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -56,11 +56,18 @@
 #elif defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
   #define TU_VERIFY_STATIC   _Static_assert
 #elif defined(__CCRX__)
-  #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(Line, __LINE__)[(const_expr) ? 1 : 0];
+  #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(_verify_static_, _TU_COUNTER_)[(const_expr) ? 1 : 0];
 #else
   #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) }
 #endif
 
+/* --------------------- Fuzzing types -------------------------------------- */
+#ifdef _FUZZ
+  #define tu_static static __thread
+#else
+  #define tu_static static
+#endif
+
 // for declaration of reserved field, make use of _TU_COUNTER_
 #define TU_RESERVED           TU_XSTRCAT(reserved, _TU_COUNTER_)
 
@@ -76,9 +83,9 @@
  * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma)
  *------------------------------------------------------------------*/
 #if !defined(__CCRX__)
-#define TU_ARGS_NUM(...)   _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N())
+#define TU_ARGS_NUM(...)   _TU_NARG(_0, ##__VA_ARGS__, _RSEQ_N())
 #else
-#define TU_ARGS_NUM(...)   _TU_NARG(_0, __VA_ARGS__,_RSEQ_N())
+#define TU_ARGS_NUM(...)   _TU_NARG(_0, __VA_ARGS__, _RSEQ_N())
 #endif
 
 #define _TU_NARG(...)      _GET_NTH_ARG(__VA_ARGS__)
@@ -111,6 +118,14 @@
 #define _TU_ARGS_APPLY_7(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7)      _X(_a1) _s _TU_ARGS_APPLY_6(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7)
 #define _TU_ARGS_APPLY_8(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7, _a8) _X(_a1) _s _TU_ARGS_APPLY_7(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7, _a8)
 
+//--------------------------------------------------------------------+
+// Macro for function default arguments
+//--------------------------------------------------------------------+
+#define TU_GET_3RD_ARG(arg1, arg2, arg3, ...)        arg3
+
+// function expand with number of arguments
+#define TU_FUNC_OPTIONAL_ARG(func, ...)   TU_XSTRCAT(func##_arg, TU_ARGS_NUM(__VA_ARGS__))(__VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // Compiler porting with Attribute and Endian
 //--------------------------------------------------------------------+
@@ -121,7 +136,10 @@
   #define TU_ATTR_SECTION(sec_name)     __attribute__ ((section(#sec_name)))
   #define TU_ATTR_PACKED                __attribute__ ((packed))
   #define TU_ATTR_WEAK                  __attribute__ ((weak))
-  #define TU_ATTR_ALWAYS_INLINE         __attribute__ ((always_inline))
+  // #define TU_ATTR_WEAK_ALIAS(f)         __attribute__ ((weak, alias(#f)))
+  #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug
+    #define TU_ATTR_ALWAYS_INLINE       __attribute__ ((always_inline))
+  #endif
   #define TU_ATTR_DEPRECATED(mess)      __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
@@ -131,10 +149,14 @@
   #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
   #define TU_ATTR_BIT_FIELD_ORDER_END
 
-  #if __has_attribute(__fallthrough__)
-    #define TU_ATTR_FALLTHROUGH         __attribute__((fallthrough))
-  #else
+  #if __GNUC__ < 5
     #define TU_ATTR_FALLTHROUGH         do {} while (0)  /* fallthrough */
+  #else
+    #if __has_attribute(__fallthrough__)
+      #define TU_ATTR_FALLTHROUGH         __attribute__((fallthrough))
+    #else
+      #define TU_ATTR_FALLTHROUGH         do {} while (0)  /* fallthrough */
+    #endif
   #endif
 
   // Endian conversion use well-known host to network (big endian) naming
@@ -144,8 +166,17 @@
     #define TU_BYTE_ORDER TU_BIG_ENDIAN
   #endif
 
-  #define TU_BSWAP16(u16) (__builtin_bswap16(u16))
-  #define TU_BSWAP32(u32) (__builtin_bswap32(u32))
+  // Unfortunately XC16 doesn't provide builtins for 32bit endian conversion
+  #if defined(__XC16)
+    #define TU_BSWAP16(u16) (__builtin_swap(u16))
+    #define TU_BSWAP32(u32) ((((u32) & 0xff000000) >> 24) |  \
+                            (((u32) & 0x00ff0000) >> 8)  |  \
+                            (((u32) & 0x0000ff00) << 8)  |  \
+                            (((u32) & 0x000000ff) << 24))
+  #else
+    #define TU_BSWAP16(u16) (__builtin_bswap16(u16))
+    #define TU_BSWAP32(u32) (__builtin_bswap32(u32))
+  #endif
 
 	#ifndef __ARMCC_VERSION
   // List of obsolete callback function that is renamed and should not be defined.
@@ -158,6 +189,7 @@
   #define TU_ATTR_SECTION(sec_name)     __attribute__ ((section(#sec_name)))
   #define TU_ATTR_PACKED                __attribute__ ((packed))
   #define TU_ATTR_WEAK                  __attribute__ ((weak))
+  // #define TU_ATTR_WEAK_ALIAS(f)         __attribute__ ((weak, alias(#f)))
   #define TU_ATTR_ALWAYS_INLINE         __attribute__ ((always_inline))
   #define TU_ATTR_DEPRECATED(mess)      __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
@@ -185,11 +217,14 @@
   #define TU_ATTR_SECTION(sec_name)     __attribute__ ((section(#sec_name)))
   #define TU_ATTR_PACKED                __attribute__ ((packed))
   #define TU_ATTR_WEAK                  __attribute__ ((weak))
-  #define TU_ATTR_ALWAYS_INLINE         __attribute__ ((always_inline))
+  // #define TU_ATTR_WEAK_ALIAS(f)         __attribute__ ((weak, alias(#f)))
+  #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug
+    #define TU_ATTR_ALWAYS_INLINE         __attribute__ ((always_inline))
+  #endif
   #define TU_ATTR_DEPRECATED(mess)      __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
-  #define TU_ATTR_FALLTHROUGH           __attribute__((fallthrough))
+  #define TU_ATTR_FALLTHROUGH           do {} while (0)  /* fallthrough */
 
   #define TU_ATTR_PACKED_BEGIN
   #define TU_ATTR_PACKED_END
@@ -211,6 +246,7 @@
   #define TU_ATTR_SECTION(sec_name)
   #define TU_ATTR_PACKED
   #define TU_ATTR_WEAK
+  // #define TU_ATTR_WEAK_ALIAS(f)
   #define TU_ATTR_ALWAYS_INLINE
   #define TU_ATTR_DEPRECATED(mess)
   #define TU_ATTR_UNUSED
@@ -232,7 +268,7 @@
   #define TU_BSWAP16(u16) ((unsigned short)_builtin_revw((unsigned long)u16))
   #define TU_BSWAP32(u32) (_builtin_revl(u32))
 
-#else 
+#else
   #error "Compiler attribute porting is required"
 #endif
 
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index ac5bee6ec..2e9f1d9cd 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -43,9 +43,10 @@
 #if CFG_TUSB_DEBUG
 
 // Enum to String for debugging purposes
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
 extern char const* const tu_str_speed[];
 extern char const* const tu_str_std_request[];
+extern char const* const tu_str_xfer_result[];
 #endif
 
 void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
@@ -57,16 +58,15 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
   #define tu_printf    printf
 #endif
 
-static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
-{
+static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
   for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
+  tu_printf("\r\n");
 }
 
 // Log with Level
 #define TU_LOG(n, ...)        TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
 #define TU_LOG_MEM(n, ...)    TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
-#define TU_LOG_ARR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _ARR)(__VA_ARGS__)
-#define TU_LOG_VAR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__)
+#define TU_LOG_BUF(n, ...)    TU_XSTRCAT3(TU_LOG, n, _BUF)(__VA_ARGS__)
 #define TU_LOG_INT(n, ...)    TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
 #define TU_LOG_HEX(n, ...)    TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
 #define TU_LOG_LOCATION()     tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
@@ -75,17 +75,15 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 // Log Level 1: Error
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
-#define TU_LOG1_ARR(_x, _n)   tu_print_arr((uint8_t const*)(_x), _n)
-#define TU_LOG1_VAR(_x)       tu_print_arr((uint8_t const*)(_x), sizeof(*(_x)))
+#define TU_LOG1_BUF(_x, _n)   tu_print_buf((uint8_t const*)(_x), _n)
 #define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
-#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
+#define TU_LOG1_HEX(_x)       tu_printf(#_x " = 0x%lX\r\n", (unsigned long) (_x) )
 
 // Log Level 2: Warn
 #if CFG_TUSB_DEBUG >= 2
   #define TU_LOG2             TU_LOG1
   #define TU_LOG2_MEM         TU_LOG1_MEM
-  #define TU_LOG2_ARR         TU_LOG1_ARR
-  #define TU_LOG2_VAR         TU_LOG1_VAR
+  #define TU_LOG2_BUF         TU_LOG1_BUF
   #define TU_LOG2_INT         TU_LOG1_INT
   #define TU_LOG2_HEX         TU_LOG1_HEX
 #endif
@@ -94,30 +92,25 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 #if CFG_TUSB_DEBUG >= 3
   #define TU_LOG3             TU_LOG1
   #define TU_LOG3_MEM         TU_LOG1_MEM
-  #define TU_LOG3_ARR         TU_LOG1_ARR
-  #define TU_LOG3_VAR         TU_LOG1_VAR
+  #define TU_LOG3_BUF         TU_LOG1_BUF
   #define TU_LOG3_INT         TU_LOG1_INT
   #define TU_LOG3_HEX         TU_LOG1_HEX
 #endif
 
-typedef struct
-{
+typedef struct {
   uint32_t key;
   const char* data;
 } tu_lookup_entry_t;
 
-typedef struct
-{
+typedef struct {
   uint16_t count;
   tu_lookup_entry_t const* items;
 } tu_lookup_table_t;
 
-static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
-{
-  static char not_found[11];
+static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) {
+  tu_static char not_found[11];
 
-  for(uint16_t i=0; i<p_table->count; i++)
-  {
+  for(uint16_t i=0; i<p_table->count; i++) {
     if (p_table->items[i].key == key) return p_table->items[i].data;
   }
 
@@ -132,7 +125,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG
   #define TU_LOG(n, ...)
   #define TU_LOG_MEM(n, ...)
-  #define TU_LOG_VAR(n, ...)
+  #define TU_LOG_BUF(n, ...)
   #define TU_LOG_INT(n, ...)
   #define TU_LOG_HEX(n, ...)
   #define TU_LOG_LOCATION()
@@ -143,14 +136,14 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 
 #define TU_LOG0(...)
 #define TU_LOG0_MEM(...)
-#define TU_LOG0_VAR(...)
+#define TU_LOG0_BUF(...)
 #define TU_LOG0_INT(...)
 #define TU_LOG0_HEX(...)
 
 #ifndef TU_LOG1
   #define TU_LOG1(...)
   #define TU_LOG1_MEM(...)
-  #define TU_LOG1_VAR(...)
+  #define TU_LOG1_BUF(...)
   #define TU_LOG1_INT(...)
   #define TU_LOG1_HEX(...)
 #endif
@@ -158,7 +151,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG2
   #define TU_LOG2(...)
   #define TU_LOG2_MEM(...)
-  #define TU_LOG2_VAR(...)
+  #define TU_LOG2_BUF(...)
   #define TU_LOG2_INT(...)
   #define TU_LOG2_HEX(...)
 #endif
@@ -166,7 +159,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG3
   #define TU_LOG3(...)
   #define TU_LOG3_MEM(...)
-  #define TU_LOG3_VAR(...)
+  #define TU_LOG3_BUF(...)
   #define TU_LOG3_INT(...)
   #define TU_LOG3_HEX(...)
 #endif
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 895b9208b..5f2dcabad 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -28,21 +28,22 @@
 #include "osal/osal.h"
 #include "tusb_fifo.h"
 
-// Supress IAR warning
+#define TU_FIFO_DBG   0
+
+// Suppress IAR warning
 // Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement
 #if defined(__ICCARM__)
 #pragma diag_suppress = Pa082
 #endif
 
-// implement mutex lock and unlock
-#if CFG_FIFO_MUTEX
+#if OSAL_MUTEX_REQUIRED
 
-static inline void _ff_lock(tu_fifo_mutex_t mutex)
+TU_ATTR_ALWAYS_INLINE static inline void _ff_lock(osal_mutex_t mutex)
 {
   if (mutex) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 }
 
-static inline void _ff_unlock(tu_fifo_mutex_t mutex)
+TU_ATTR_ALWAYS_INLINE static inline void _ff_unlock(osal_mutex_t mutex)
 {
   if (mutex) osal_mutex_unlock(mutex);
 }
@@ -61,28 +62,27 @@ static inline void _ff_unlock(tu_fifo_mutex_t mutex)
 typedef enum
 {
   TU_FIFO_COPY_INC,            ///< Copy from/to an increasing source/destination address - default mode
+#ifdef TUP_MEM_CONST_ADDR
   TU_FIFO_COPY_CST_FULL_WORDS, ///< Copy from/to a constant source/destination address - required for e.g. STM32 to write into USB hardware FIFO
+#endif
 } tu_fifo_copy_mode_t;
 
 bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable)
 {
-  if (depth > 0x8000) return false;               // Maximum depth is 2^15 items
+  // Limit index space to 2*depth - this allows for a fast "modulo" calculation
+  // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable
+  // only if overflow happens once (important for unsupervised DMA applications)
+  if (depth > 0x8000) return false;
 
   _ff_lock(f->mutex_wr);
   _ff_lock(f->mutex_rd);
 
-  f->buffer = (uint8_t*) buffer;
-  f->depth  = depth;
-  f->item_size = item_size;
+  f->buffer       = (uint8_t*) buffer;
+  f->depth        = depth;
+  f->item_size    = (uint16_t) (item_size & 0x7FFF);
   f->overwritable = overwritable;
-
-  // Limit index space to 2*depth - this allows for a fast "modulo" calculation
-  // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable
-  // only if overflow happens once (important for unsupervised DMA applications)
-  f->max_pointer_idx = (uint16_t) (2*depth - 1);
-  f->non_used_index_space = UINT16_MAX - f->max_pointer_idx;
-
-  f->rd_idx = f->wr_idx = 0;
+  f->rd_idx       = 0;
+  f->wr_idx       = 0;
 
   _ff_unlock(f->mutex_wr);
   _ff_unlock(f->mutex_rd);
@@ -90,25 +90,23 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
   return true;
 }
 
-// Static functions are intended to work on local variables
-static inline uint16_t _ff_mod(uint16_t idx, uint16_t depth)
-{
-  while ( idx >= depth) idx -= depth;
-  return idx;
-}
+//--------------------------------------------------------------------+
+// Pull & Push
+//--------------------------------------------------------------------+
 
+#ifdef TUP_MEM_CONST_ADDR
 // Intended to be used to read from hardware USB FIFO in e.g. STM32 where all data is read from a constant address
-// Code adapted from dcd_synopsis.c
+// Code adapted from dcd_synopsys.c
 // TODO generalize with configurable 1 byte or 4 byte each read
 static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t len)
 {
-  volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf;
+  volatile const uint32_t * reg_rx = (volatile const uint32_t *) app_buf;
 
   // Reading full available 32 bit words from const app address
   uint16_t full_words = len >> 2;
   while(full_words--)
   {
-    tu_unaligned_write32(ff_buf, *rx_fifo);
+    tu_unaligned_write32(ff_buf, *reg_rx);
     ff_buf += 4;
   }
 
@@ -116,7 +114,7 @@ static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t
   uint8_t const bytes_rem = len & 0x03;
   if ( bytes_rem )
   {
-    uint32_t tmp32 = *rx_fifo;
+    uint32_t tmp32 = *reg_rx;
     memcpy(ff_buf, &tmp32, bytes_rem);
   }
 }
@@ -125,49 +123,50 @@ static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t
 // where all data is written to a constant address in full word copies
 static void _ff_pull_const_addr(void * app_buf, const uint8_t * ff_buf, uint16_t len)
 {
-  volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf;
+  volatile uint32_t * reg_tx = (volatile uint32_t *) app_buf;
 
-  // Pushing full available 32 bit words to const app address
+  // Write full available 32 bit words to const address
   uint16_t full_words = len >> 2;
   while(full_words--)
   {
-    *tx_fifo = tu_unaligned_read32(ff_buf);
+    *reg_tx = tu_unaligned_read32(ff_buf);
     ff_buf += 4;
   }
 
-  // Write the remaining 1-3 bytes into const app address
+  // Write the remaining 1-3 bytes into const address
   uint8_t const bytes_rem = len & 0x03;
   if ( bytes_rem )
   {
     uint32_t tmp32 = 0;
     memcpy(&tmp32, ff_buf, bytes_rem);
 
-    *tx_fifo = tmp32;
+    *reg_tx = tmp32;
   }
 }
+#endif
 
-// send one item to FIFO WITHOUT updating write pointer
+// send one item to fifo WITHOUT updating write pointer
 static inline void _ff_push(tu_fifo_t* f, void const * app_buf, uint16_t rel)
 {
   memcpy(f->buffer + (rel * f->item_size), app_buf, f->item_size);
 }
 
-// send n items to FIFO WITHOUT updating write pointer
-static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode)
+// send n items to fifo WITHOUT updating write pointer
+static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t wr_ptr, tu_fifo_copy_mode_t copy_mode)
 {
-  uint16_t const nLin = f->depth - rel;
-  uint16_t const nWrap = n - nLin;
+  uint16_t const lin_count = f->depth - wr_ptr;
+  uint16_t const wrap_count = n - lin_count;
 
-  uint16_t nLin_bytes = nLin * f->item_size;
-  uint16_t nWrap_bytes = nWrap * f->item_size;
+  uint16_t lin_bytes = lin_count * f->item_size;
+  uint16_t wrap_bytes = wrap_count * f->item_size;
 
   // current buffer of fifo
-  uint8_t* ff_buf = f->buffer + (rel * f->item_size);
+  uint8_t* ff_buf = f->buffer + (wr_ptr * f->item_size);
 
   switch (copy_mode)
   {
     case TU_FIFO_COPY_INC:
-      if(n <= nLin)
+      if(n <= lin_count)
       {
         // Linear only
         memcpy(ff_buf, app_buf, n*f->item_size);
@@ -177,16 +176,17 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         // Wrap around
 
         // Write data to linear part of buffer
-        memcpy(ff_buf, app_buf, nLin_bytes);
+        memcpy(ff_buf, app_buf, lin_bytes);
 
         // Write data wrapped around
-        memcpy(f->buffer, ((uint8_t const*) app_buf) + nLin_bytes, nWrap_bytes);
+        // TU_ASSERT(nWrap_bytes <= f->depth, );
+        memcpy(f->buffer, ((uint8_t const*) app_buf) + lin_bytes, wrap_bytes);
       }
       break;
-
+#ifdef TUP_MEM_CONST_ADDR
     case TU_FIFO_COPY_CST_FULL_WORDS:
       // Intended for hardware buffers from which it can be read word by word only
-      if(n <= nLin)
+      if(n <= lin_count)
       {
         // Linear only
         _ff_push_const_addr(ff_buf, app_buf, n*f->item_size);
@@ -196,17 +196,18 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         // Wrap around case
 
         // Write full words to linear part of buffer
-        uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC;
+        uint16_t nLin_4n_bytes = lin_bytes & 0xFFFC;
         _ff_push_const_addr(ff_buf, app_buf, nLin_4n_bytes);
         ff_buf += nLin_4n_bytes;
 
         // There could be odd 1-3 bytes before the wrap-around boundary
-        volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf;
-        uint8_t rem = nLin_bytes & 0x03;
+        uint8_t rem = lin_bytes & 0x03;
         if (rem > 0)
         {
-          uint8_t remrem = (uint8_t) tu_min16(nWrap_bytes, 4-rem);
-          nWrap_bytes -= remrem;
+          volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf;
+
+          uint8_t remrem = (uint8_t) tu_min16(wrap_bytes, 4-rem);
+          wrap_bytes -= remrem;
 
           uint32_t tmp32 = *rx_fifo;
           uint8_t * src_u8 = ((uint8_t *) &tmp32);
@@ -224,34 +225,36 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         }
 
         // Write data wrapped part
-        if (nWrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, nWrap_bytes);
+        if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes);
       }
       break;
+#endif
+    default: break;
   }
 }
 
-// get one item from FIFO WITHOUT updating read pointer
+// get one item from fifo WITHOUT updating read pointer
 static inline void _ff_pull(tu_fifo_t* f, void * app_buf, uint16_t rel)
 {
   memcpy(app_buf, f->buffer + (rel * f->item_size), f->item_size);
 }
 
-// get n items from FIFO WITHOUT updating read pointer
-static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode)
+// get n items from fifo WITHOUT updating read pointer
+static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rd_ptr, tu_fifo_copy_mode_t copy_mode)
 {
-  uint16_t const nLin = f->depth - rel;
-  uint16_t const nWrap = n - nLin; // only used if wrapped
+  uint16_t const lin_count = f->depth - rd_ptr;
+  uint16_t const wrap_count = n - lin_count; // only used if wrapped
 
-  uint16_t nLin_bytes = nLin * f->item_size;
-  uint16_t nWrap_bytes = nWrap * f->item_size;
+  uint16_t lin_bytes = lin_count * f->item_size;
+  uint16_t wrap_bytes = wrap_count * f->item_size;
 
   // current buffer of fifo
-  uint8_t* ff_buf = f->buffer + (rel * f->item_size);
+  uint8_t* ff_buf = f->buffer + (rd_ptr * f->item_size);
 
   switch (copy_mode)
   {
     case TU_FIFO_COPY_INC:
-      if ( n <= nLin )
+      if ( n <= lin_count )
       {
         // Linear only
         memcpy(app_buf, ff_buf, n*f->item_size);
@@ -261,15 +264,15 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
         // Wrap around
 
         // Read data from linear part of buffer
-        memcpy(app_buf, ff_buf, nLin_bytes);
+        memcpy(app_buf, ff_buf, lin_bytes);
 
         // Read data wrapped part
-        memcpy((uint8_t*) app_buf + nLin_bytes, f->buffer, nWrap_bytes);
+        memcpy((uint8_t*) app_buf + lin_bytes, f->buffer, wrap_bytes);
       }
     break;
-
+#ifdef TUP_MEM_CONST_ADDR
     case TU_FIFO_COPY_CST_FULL_WORDS:
-      if ( n <= nLin )
+      if ( n <= lin_count )
       {
         // Linear only
         _ff_pull_const_addr(app_buf, ff_buf, n*f->item_size);
@@ -279,17 +282,18 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
         // Wrap around case
 
         // Read full words from linear part of buffer
-        uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC;
-        _ff_pull_const_addr(app_buf, ff_buf, nLin_4n_bytes);
-        ff_buf += nLin_4n_bytes;
+        uint16_t lin_4n_bytes = lin_bytes & 0xFFFC;
+        _ff_pull_const_addr(app_buf, ff_buf, lin_4n_bytes);
+        ff_buf += lin_4n_bytes;
 
         // There could be odd 1-3 bytes before the wrap-around boundary
-        volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf;
-        uint8_t rem = nLin_bytes & 0x03;
+        uint8_t rem = lin_bytes & 0x03;
         if (rem > 0)
         {
-          uint8_t remrem = (uint8_t) tu_min16(nWrap_bytes, 4-rem);
-          nWrap_bytes -= remrem;
+          volatile uint32_t * reg_tx = (volatile uint32_t *) app_buf;
+
+          uint8_t remrem = (uint8_t) tu_min16(wrap_bytes, 4-rem);
+          wrap_bytes -= remrem;
 
           uint32_t tmp32=0;
           uint8_t * dst_u8 = (uint8_t *)&tmp32;
@@ -301,7 +305,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
           ff_buf = f->buffer;
           while(remrem--) *dst_u8++ = *ff_buf++;
 
-          *tx_fifo = tmp32;
+          *reg_tx = tmp32;
         }
         else
         {
@@ -309,186 +313,240 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
         }
 
         // Read data wrapped part
-        if (nWrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, nWrap_bytes);
+        if (wrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, wrap_bytes);
       }
     break;
-
+#endif
     default: break;
   }
 }
 
-// Advance an absolute pointer
-static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
-{
-  // We limit the index space of p such that a correct wrap around happens
-  // Check for a wrap around or if we are in unused index space - This has to be checked first!!
-  // We are exploiting the wrap around to the correct index
-  if ((p > (uint16_t)(p + offset)) || ((uint16_t)(p + offset) > f->max_pointer_idx))
-  {
-    p = (uint16_t) ((p + offset) + f->non_used_index_space);
-  }
-  else
-  {
-    p += offset;
-  }
-  return p;
-}
+//--------------------------------------------------------------------+
+// Helper
+//--------------------------------------------------------------------+
 
-// Backward an absolute pointer
-static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
+// return only the index difference and as such can be used to determine an overflow i.e overflowable count
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t _ff_count(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
 {
-  // We limit the index space of p such that a correct wrap around happens
-  // Check for a wrap around or if we are in unused index space - This has to be checked first!!
-  // We are exploiting the wrap around to the correct index
-  if ((p < (uint16_t)(p - offset)) || ((uint16_t)(p - offset) > f->max_pointer_idx))
-  {
-    p = (uint16_t) ((p - offset) - f->non_used_index_space);
-  }
-  else
-  {
-    p -= offset;
-  }
-  return p;
-}
-
-// get relative from absolute pointer
-static uint16_t get_relative_pointer(tu_fifo_t* f, uint16_t p)
-{
-  return _ff_mod(p, f->depth);
-}
-
-// Works on local copies of w and r - return only the difference and as such can be used to determine an overflow
-static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
-{
-  uint16_t cnt = wAbs-rAbs;
-
   // In case we have non-power of two depth we need a further modification
-  if (rAbs > wAbs) cnt -= f->non_used_index_space;
-
-  return cnt;
+  if (wr_idx >= rd_idx)
+  {
+    return (uint16_t) (wr_idx - rd_idx);
+  } else
+  {
+    return (uint16_t) (2*depth - (rd_idx - wr_idx));
+  }
 }
 
-// Works on local copies of w and r
-static inline bool _tu_fifo_empty(uint16_t wAbs, uint16_t rAbs)
+// return remaining slot in fifo
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
 {
-  return wAbs == rAbs;
+  uint16_t const count = _ff_count(depth, wr_idx, rd_idx);
+  return (depth > count) ? (depth - count) : 0;
 }
 
-// Works on local copies of w and r
-static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
+//--------------------------------------------------------------------+
+// Index Helper
+//--------------------------------------------------------------------+
+
+// Advance an absolute index
+// "absolute" index is only in the range of [0..2*depth)
+static uint16_t advance_index(uint16_t depth, uint16_t idx, uint16_t offset)
 {
-  return (_tu_fifo_count(f, wAbs, rAbs) == f->depth);
+  // We limit the index space of p such that a correct wrap around happens
+  // Check for a wrap around or if we are in unused index space - This has to be checked first!!
+  // We are exploiting the wrap around to the correct index
+  uint16_t new_idx = (uint16_t) (idx + offset);
+  if ( (idx > new_idx) || (new_idx >= 2*depth) )
+  {
+    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1));
+    new_idx = (uint16_t) (new_idx + non_used_index_space);
+  }
+
+  return new_idx;
 }
 
-// Works on local copies of w and r
-// BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS"
-// Only one overflow is allowed for this function to work e.g. if depth = 100, you must not
-// write more than 2*depth-1 items in one rush without updating write pointer. Otherwise
-// write pointer wraps and you pointer states are messed up. This can only happen if you
-// use DMAs, write functions do not allow such an error.
-static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
+#if 0 // not used but
+// Backward an absolute index
+static uint16_t backward_index(uint16_t depth, uint16_t idx, uint16_t offset)
 {
-  return (_tu_fifo_count(f, wAbs, rAbs) > f->depth);
+  // We limit the index space of p such that a correct wrap around happens
+  // Check for a wrap around or if we are in unused index space - This has to be checked first!!
+  // We are exploiting the wrap around to the correct index
+  uint16_t new_idx = (uint16_t) (idx - offset);
+  if ( (idx < new_idx) || (new_idx >= 2*depth) )
+  {
+    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1));
+    new_idx = (uint16_t) (new_idx - non_used_index_space);
+  }
+
+  return new_idx;
+}
+#endif
+
+// index to pointer, simply an modulo with minus.
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t idx2ptr(uint16_t depth, uint16_t idx)
+{
+  // Only run at most 3 times since index is limit in the range of [0..2*depth)
+  while ( idx >= depth ) idx -= depth;
+  return idx;
 }
 
 // Works on local copies of w
-// For more details see _tu_fifo_overflow()!
-static inline void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs)
+// When an overwritable fifo is overflowed, rd_idx will be re-index so that it forms
+// an full fifo i.e _ff_count() = depth
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t _ff_correct_read_index(tu_fifo_t* f, uint16_t wr_idx)
 {
-  f->rd_idx = backward_pointer(f, wAbs, f->depth);
+  uint16_t rd_idx;
+  if ( wr_idx >= f->depth )
+  {
+    rd_idx = wr_idx - f->depth;
+  }else
+  {
+    rd_idx = wr_idx + f->depth;
+  }
+
+  f->rd_idx = rd_idx;
+
+  return rd_idx;
 }
 
 // Works on local copies of w and r
 // Must be protected by mutexes since in case of an overflow read pointer gets modified
-static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wAbs, uint16_t rAbs)
+static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16_t rd_idx)
 {
-  uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs);
+  uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
+
+  // nothing to peek
+  if ( cnt == 0 ) return false;
 
   // Check overflow and correct if required
-  if (cnt > f->depth)
+  if ( cnt > f->depth )
   {
-    _tu_fifo_correct_read_pointer(f, wAbs);
+    rd_idx = _ff_correct_read_index(f, wr_idx);
     cnt = f->depth;
   }
 
-  // Skip beginning of buffer
-  if (cnt == 0) return false;
-
-  uint16_t rRel = get_relative_pointer(f, rAbs);
+  uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
   // Peek data
-  _ff_pull(f, p_buffer, rRel);
+  _ff_pull(f, p_buffer, rd_ptr);
 
   return true;
 }
 
 // Works on local copies of w and r
 // Must be protected by mutexes since in case of an overflow read pointer gets modified
-static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wAbs, uint16_t rAbs, tu_fifo_copy_mode_t copy_mode)
+static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wr_idx, uint16_t rd_idx, tu_fifo_copy_mode_t copy_mode)
 {
-  uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs);
+  uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
+
+  // nothing to peek
+  if ( cnt == 0 ) return 0;
 
   // Check overflow and correct if required
-  if (cnt > f->depth)
+  if ( cnt > f->depth )
   {
-    _tu_fifo_correct_read_pointer(f, wAbs);
-    rAbs = f->rd_idx;
+    rd_idx = _ff_correct_read_index(f, wr_idx);
     cnt = f->depth;
   }
 
-  // Skip beginning of buffer
-  if (cnt == 0) return 0;
-
   // Check if we can read something at and after offset - if too less is available we read what remains
-  if (cnt < n) n = cnt;
+  if ( cnt < n ) n = cnt;
 
-  uint16_t rRel = get_relative_pointer(f, rAbs);
+  uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
   // Peek data
-  _ff_pull_n(f, p_buffer, n, rRel, copy_mode);
+  _ff_pull_n(f, p_buffer, n, rd_ptr, copy_mode);
 
   return n;
 }
 
-// Works on local copies of w and r
-static inline uint16_t _tu_fifo_remaining(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
-{
-  return f->depth - _tu_fifo_count(f, wAbs, rAbs);
-}
-
 static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu_fifo_copy_mode_t copy_mode)
 {
   if ( n == 0 ) return 0;
 
   _ff_lock(f->mutex_wr);
 
-  uint16_t w = f->wr_idx, r = f->rd_idx;
+  uint16_t wr_idx = f->wr_idx;
+  uint16_t rd_idx = f->rd_idx;
+
   uint8_t const* buf8 = (uint8_t const*) data;
 
-  if (!f->overwritable)
-  {
-    // Not overwritable limit up to full
-    n = tu_min16(n, _tu_fifo_remaining(f, w, r));
-  }
-  else if (n >= f->depth)
-  {
-    // Only copy last part
-    buf8 = buf8 + (n - f->depth) * f->item_size;
-    n = f->depth;
+  TU_LOG(TU_FIFO_DBG, "rd = %3u, wr = %3u, count = %3u, remain = %3u, n = %3u:  ",
+                       rd_idx, wr_idx, _ff_count(f->depth, wr_idx, rd_idx), _ff_remaining(f->depth, wr_idx, rd_idx), n);
 
-    // We start writing at the read pointer's position since we fill the complete
-    // buffer and we do not want to modify the read pointer within a write function!
-    // This would end up in a race condition with read functions!
-    w = r;
+  if ( !f->overwritable )
+  {
+    // limit up to full
+    uint16_t const remain = _ff_remaining(f->depth, wr_idx, rd_idx);
+    n = tu_min16(n, remain);
+  }
+  else
+  {
+    // In over-writable mode, fifo_write() is allowed even when fifo is full. In such case,
+    // oldest data in fifo i.e at read pointer data will be overwritten
+    // Note: we can modify read buffer contents but we must not modify the read index itself within a write function!
+    // Since it would end up in a race condition with read functions!
+    if ( n >= f->depth )
+    {
+      // Only copy last part
+      if ( copy_mode == TU_FIFO_COPY_INC )
+      {
+        buf8 += (n - f->depth) * f->item_size;
+      }else
+      {
+        // TODO should read from hw fifo to discard data, however reading an odd number could
+        // accidentally discard data.
+      }
+
+      n = f->depth;
+
+      // We start writing at the read pointer's position since we fill the whole buffer
+      wr_idx = rd_idx;
+    }
+    else
+    {
+      uint16_t const overflowable_count = _ff_count(f->depth, wr_idx, rd_idx);
+      if (overflowable_count + n >= 2*f->depth)
+      {
+        // Double overflowed
+        // Index is bigger than the allowed range [0,2*depth)
+        // re-position write index to have a full fifo after pushed
+        wr_idx = advance_index(f->depth, rd_idx, f->depth - n);
+
+        // TODO we should also shift out n bytes from read index since we avoid changing rd index !!
+        // However memmove() is expensive due to actual copying + wrapping consideration.
+        // Also race condition could happen anyway if read() is invoke while moving result in corrupted memory
+        // currently deliberately not implemented --> result in incorrect data read back
+      }else
+      {
+        // normal + single overflowed:
+        // Index is in the range of [0,2*depth) and thus detect and recoverable. Recovering is handled in read()
+        // Therefore we just increase write index
+        // we will correct (re-position) read index later on in fifo_read() function
+      }
+    }
   }
 
-  uint16_t wRel = get_relative_pointer(f, w);
+  if (n)
+  {
+    uint16_t wr_ptr = idx2ptr(f->depth, wr_idx);
 
-  // Write data
-  _ff_push_n(f, buf8, n, wRel, copy_mode);
+    TU_LOG(TU_FIFO_DBG, "actual_n = %u, wr_ptr = %u", n, wr_ptr);
 
-  // Advance pointer
-  f->wr_idx = advance_pointer(f, w, n);
+    // Write data
+    _ff_push_n(f, buf8, n, wr_ptr, copy_mode);
+
+    // Advance index
+    f->wr_idx = advance_index(f->depth, wr_idx, n);
+
+    TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\r\n", f->wr_idx);
+  }
 
   _ff_unlock(f->mutex_wr);
 
@@ -504,12 +562,16 @@ static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo
   n = _tu_fifo_peek_n(f, buffer, n, f->wr_idx, f->rd_idx, copy_mode);
 
   // Advance read pointer
-  f->rd_idx = advance_pointer(f, f->rd_idx, n);
+  f->rd_idx = advance_index(f->depth, f->rd_idx, n);
 
   _ff_unlock(f->mutex_rd);
   return n;
 }
 
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
+
 /******************************************************************************/
 /*!
     @brief Get number of items in FIFO.
@@ -527,7 +589,7 @@ static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo
 /******************************************************************************/
 uint16_t tu_fifo_count(tu_fifo_t* f)
 {
-  return tu_min16(_tu_fifo_count(f, f->wr_idx, f->rd_idx), f->depth);
+  return tu_min16(_ff_count(f->depth, f->wr_idx, f->rd_idx), f->depth);
 }
 
 /******************************************************************************/
@@ -545,7 +607,7 @@ uint16_t tu_fifo_count(tu_fifo_t* f)
 /******************************************************************************/
 bool tu_fifo_empty(tu_fifo_t* f)
 {
-  return _tu_fifo_empty(f->wr_idx, f->rd_idx);
+  return f->wr_idx == f->rd_idx;
 }
 
 /******************************************************************************/
@@ -563,7 +625,7 @@ bool tu_fifo_empty(tu_fifo_t* f)
 /******************************************************************************/
 bool tu_fifo_full(tu_fifo_t* f)
 {
-  return _tu_fifo_full(f, f->wr_idx, f->rd_idx);
+  return _ff_count(f->depth, f->wr_idx, f->rd_idx) >= f->depth;
 }
 
 /******************************************************************************/
@@ -581,7 +643,7 @@ bool tu_fifo_full(tu_fifo_t* f)
 /******************************************************************************/
 uint16_t tu_fifo_remaining(tu_fifo_t* f)
 {
-  return _tu_fifo_remaining(f, f->wr_idx, f->rd_idx);
+  return _ff_remaining(f->depth, f->wr_idx, f->rd_idx);
 }
 
 /******************************************************************************/
@@ -607,14 +669,14 @@ uint16_t tu_fifo_remaining(tu_fifo_t* f)
 /******************************************************************************/
 bool tu_fifo_overflowed(tu_fifo_t* f)
 {
-  return _tu_fifo_overflowed(f, f->wr_idx, f->rd_idx);
+  return _ff_count(f->depth, f->wr_idx, f->rd_idx) > f->depth;
 }
 
 // Only use in case tu_fifo_overflow() returned true!
 void tu_fifo_correct_read_pointer(tu_fifo_t* f)
 {
   _ff_lock(f->mutex_rd);
-  _tu_fifo_correct_read_pointer(f, f->wr_idx);
+  _ff_correct_read_index(f, f->wr_idx);
   _ff_unlock(f->mutex_rd);
 }
 
@@ -643,7 +705,7 @@ bool tu_fifo_read(tu_fifo_t* f, void * buffer)
   bool ret = _tu_fifo_peek(f, buffer, f->wr_idx, f->rd_idx);
 
   // Advance pointer
-  f->rd_idx = advance_pointer(f, f->rd_idx, ret);
+  f->rd_idx = advance_index(f->depth, f->rd_idx, ret);
 
   _ff_unlock(f->mutex_rd);
   return ret;
@@ -670,10 +732,29 @@ uint16_t tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n)
   return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_INC);
 }
 
+#ifdef TUP_MEM_CONST_ADDR
+/******************************************************************************/
+/*!
+    @brief This function will read n elements from the array index specified by
+    the read pointer and increment the read index.
+    This function checks for an overflow and corrects read pointer if required.
+    The dest address will not be incremented which is useful for writing to registers.
+
+    @param[in]  f
+                Pointer to the FIFO buffer to manipulate
+    @param[in]  buffer
+                The pointer to data location
+    @param[in]  n
+                Number of element that buffer can afford
+
+    @returns number of items read from the FIFO
+ */
+/******************************************************************************/
 uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t* f, void * buffer, uint16_t n)
 {
   return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_CST_FULL_WORDS);
 }
+#endif
 
 /******************************************************************************/
 /*!
@@ -682,8 +763,6 @@ uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t* f, void * buffer, uint1
 
     @param[in]  f
                 Pointer to the FIFO buffer to manipulate
-    @param[in]  offset
-                Position to read from in the FIFO buffer with respect to read pointer
     @param[in]  p_buffer
                 Pointer to the place holder for data read from the buffer
 
@@ -742,20 +821,20 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data)
   _ff_lock(f->mutex_wr);
 
   bool ret;
-  uint16_t const w = f->wr_idx;
+  uint16_t const wr_idx = f->wr_idx;
 
-  if ( _tu_fifo_full(f, w, f->rd_idx) && !f->overwritable )
+  if ( tu_fifo_full(f) && !f->overwritable )
   {
     ret = false;
   }else
   {
-    uint16_t wRel = get_relative_pointer(f, w);
+    uint16_t wr_ptr = idx2ptr(f->depth, wr_idx);
 
     // Write data
-    _ff_push(f, data, wRel);
+    _ff_push(f, data, wr_ptr);
 
     // Advance pointer
-    f->wr_idx = advance_pointer(f, w, 1);
+    f->wr_idx = advance_index(f->depth, wr_idx, 1);
 
     ret = true;
   }
@@ -784,6 +863,7 @@ uint16_t tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n)
   return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_INC);
 }
 
+#ifdef TUP_MEM_CONST_ADDR
 /******************************************************************************/
 /*!
     @brief This function will write n elements into the array index specified by
@@ -803,6 +883,7 @@ uint16_t tu_fifo_write_n_const_addr_full_words(tu_fifo_t* f, const void * data,
 {
   return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_CST_FULL_WORDS);
 }
+#endif
 
 /******************************************************************************/
 /*!
@@ -817,9 +898,8 @@ bool tu_fifo_clear(tu_fifo_t *f)
   _ff_lock(f->mutex_wr);
   _ff_lock(f->mutex_rd);
 
-  f->rd_idx = f->wr_idx = 0;
-  f->max_pointer_idx = (uint16_t) (2*f->depth-1);
-  f->non_used_index_space = UINT16_MAX - f->max_pointer_idx;
+  f->rd_idx = 0;
+  f->wr_idx = 0;
 
   _ff_unlock(f->mutex_wr);
   _ff_unlock(f->mutex_rd);
@@ -857,7 +937,7 @@ bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable)
     As long as the DMA is the only process writing into the FIFO this is safe
     to use.
 
-    USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE!
+    USE WITH CARE - WE DO NOT CONDUCT SAFETY CHECKS HERE!
 
     @param[in]  f
                 Pointer to the FIFO buffer to manipulate
@@ -867,7 +947,7 @@ bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable)
 /******************************************************************************/
 void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n)
 {
-  f->wr_idx = advance_pointer(f, f->wr_idx, n);
+  f->wr_idx = advance_index(f->depth, f->wr_idx, n);
 }
 
 /******************************************************************************/
@@ -878,7 +958,7 @@ void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n)
     FIFO. As long as the DMA is the only process reading from the FIFO this is
     safe to use.
 
-    USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE!
+    USE WITH CARE - WE DO NOT CONDUCT SAFETY CHECKS HERE!
 
     @param[in]  f
                 Pointer to the FIFO buffer to manipulate
@@ -888,7 +968,7 @@ void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n)
 /******************************************************************************/
 void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n)
 {
-  f->rd_idx = advance_pointer(f, f->rd_idx, n);
+  f->rd_idx = advance_index(f->depth, f->rd_idx, n);
 }
 
 /******************************************************************************/
@@ -909,17 +989,18 @@ void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n)
 void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
 {
   // Operate on temporary values in case they change in between
-  uint16_t w = f->wr_idx, r = f->rd_idx;
+  uint16_t wr_idx = f->wr_idx;
+  uint16_t rd_idx = f->rd_idx;
 
-  uint16_t cnt = _tu_fifo_count(f, w, r);
+  uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
 
   // Check overflow and correct if required - may happen in case a DMA wrote too fast
   if (cnt > f->depth)
   {
     _ff_lock(f->mutex_rd);
-    _tu_fifo_correct_read_pointer(f, w);
+    rd_idx = _ff_correct_read_index(f, wr_idx);
     _ff_unlock(f->mutex_rd);
-    r = f->rd_idx;
+
     cnt = f->depth;
   }
 
@@ -934,22 +1015,25 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
   }
 
   // Get relative pointers
-  w = get_relative_pointer(f, w);
-  r = get_relative_pointer(f, r);
+  uint16_t wr_ptr = idx2ptr(f->depth, wr_idx);
+  uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
   // Copy pointer to buffer to start reading from
-  info->ptr_lin = &f->buffer[r];
+  info->ptr_lin = &f->buffer[rd_ptr];
 
   // Check if there is a wrap around necessary
-  if (w > r) {
+  if (wr_ptr > rd_ptr)
+  {
     // Non wrapping case
     info->len_lin  = cnt;
+
     info->len_wrap = 0;
     info->ptr_wrap = NULL;
   }
   else
   {
-    info->len_lin  = f->depth - r;         // Also the case if FIFO was full
+    info->len_lin  = f->depth - rd_ptr;   // Also the case if FIFO was full
+
     info->len_wrap = cnt - info->len_lin;
     info->ptr_wrap = f->buffer;
   }
@@ -972,36 +1056,37 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
 /******************************************************************************/
 void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
 {
-  uint16_t w = f->wr_idx, r = f->rd_idx;
-  uint16_t free = _tu_fifo_remaining(f, w, r);
+  uint16_t wr_idx = f->wr_idx;
+  uint16_t rd_idx = f->rd_idx;
+  uint16_t remain = _ff_remaining(f->depth, wr_idx, rd_idx);
 
-  if (free == 0)
+  if (remain == 0)
   {
-    info->len_lin = 0;
+    info->len_lin  = 0;
     info->len_wrap = 0;
-    info->ptr_lin = NULL;
+    info->ptr_lin  = NULL;
     info->ptr_wrap = NULL;
     return;
   }
 
   // Get relative pointers
-  w = get_relative_pointer(f, w);
-  r = get_relative_pointer(f, r);
+  uint16_t wr_ptr = idx2ptr(f->depth, wr_idx);
+  uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
   // Copy pointer to buffer to start writing to
-  info->ptr_lin = &f->buffer[w];
+  info->ptr_lin = &f->buffer[wr_ptr];
 
-  if (w < r)
+  if (wr_ptr < rd_ptr)
   {
     // Non wrapping case
-    info->len_lin = r-w;
+    info->len_lin  = rd_ptr-wr_ptr;
     info->len_wrap = 0;
     info->ptr_wrap = NULL;
   }
   else
   {
-    info->len_lin = f->depth - w;
-    info->len_wrap = free - info->len_lin; // Remaining length - n already was limited to free or FIFO depth
-    info->ptr_wrap = f->buffer;            // Always start of buffer
+    info->len_lin  = f->depth - wr_ptr;
+    info->len_wrap = remain - info->len_lin; // Remaining length - n already was limited to remain or FIFO depth
+    info->ptr_wrap = f->buffer;              // Always start of buffer
   }
 }
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 18db289a1..879acda4f 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -32,7 +32,7 @@
 extern "C" {
 #endif
 
-// Due to the use of unmasked pointers, this FIFO does not suffer from loosing
+// Due to the use of unmasked pointers, this FIFO does not suffer from losing
 // one item slice. Furthermore, write and read operations are completely
 // decoupled as write and read functions do not modify a common state. Henceforth,
 // writing or reading from the FIFO within an ISR is safe as long as no other
@@ -42,79 +42,129 @@ extern "C" {
 // within a certain number (see tu_fifo_overflow()).
 
 #include "common/tusb_common.h"
+#include "osal/osal.h"
 
 // mutex is only needed for RTOS
 // for OS None, we don't get preempted
-#define CFG_FIFO_MUTEX      (CFG_TUSB_OS != OPT_OS_NONE)
+#define CFG_FIFO_MUTEX      OSAL_MUTEX_REQUIRED
 
-#if CFG_FIFO_MUTEX
-#include "osal/osal.h"
-#define tu_fifo_mutex_t  osal_mutex_t
-#endif
+/* Write/Read index is always in the range of:
+ *      0 .. 2*depth-1
+ * The extra window allow us to determine the fifo state of empty or full with only 2 indices
+ * Following are examples with depth = 3
+ *
+ * - empty: W = R
+ *                |
+ *    -------------------------
+ *    | 0 | RW| 2 | 3 | 4 | 5 |
+ *
+ * - full 1: W > R
+ *                |
+ *    -------------------------
+ *    | 0 | R | 2 | 3 | W | 5 |
+ *
+ * - full 2: W < R
+ *                |
+ *    -------------------------
+ *    | 0 | 1 | W | 3 | 4 | R |
+ *
+ * - Number of items in the fifo can be determined in either cases:
+ *    - case W >= R: Count = W - R
+ *    - case W <  R: Count = 2*depth - (R - W)
+ *
+ * In non-overwritable mode, computed Count (in above 2 cases) is at most equal to depth.
+ * However, in over-writable mode, write index can be repeatedly increased and count can be
+ * temporarily larger than depth (overflowed condition) e.g
+ *
+ *  - Overflowed 1: write(3), write(1)
+ *    In this case we will adjust Read index when read()/peek() is called so that count = depth.
+ *                  |
+ *      -------------------------
+ *      | R | 1 | 2 | 3 | W | 5 |
+ *
+ *  - Double Overflowed i.e index is out of allowed range [0,2*depth)
+ *    This occurs when we continue to write after 1st overflowed to 2nd overflowed. e.g:
+ *      write(3), write(1), write(2)
+ *    This must be prevented since it will cause unrecoverable state, in above example
+ *    if not handled the fifo will be empty instead of continue-to-be full. Since we must not modify
+ *    read index in write() function, which cause race condition. We will re-position write index so that
+ *    after data is written it is a full fifo i.e W = depth - R
+ *
+ *      re-position W = 1 before write(2)
+ *      Note: we should also move data from mem[3] to read index as well, but deliberately skipped here
+ *      since it is an expensive operation !!!
+ *                  |
+ *      -------------------------
+ *      | R | W | 2 | 3 | 4 | 5 |
+ *
+ *      perform write(2), result is still a full fifo.
+ *
+ *                  |
+ *      -------------------------
+ *      | R | 1 | 2 | W | 4 | 5 |
+ */
+typedef struct {
+  uint8_t* buffer          ; // buffer pointer
+  uint16_t depth           ; // max items
 
-typedef struct
-{
-  uint8_t* buffer               ; ///< buffer pointer
-  uint16_t depth                ; ///< max items
-  uint16_t item_size            ; ///< size of each item
-  bool overwritable             ;
+  struct TU_ATTR_PACKED {
+    uint16_t item_size : 15; // size of each item
+    bool overwritable  : 1 ; // ovwerwritable when full
+  };
 
-  uint16_t non_used_index_space ; ///< required for non-power-of-two buffer length
-  uint16_t max_pointer_idx      ; ///< maximum absolute pointer index
+  volatile uint16_t wr_idx ; // write index
+  volatile uint16_t rd_idx ; // read index
 
-  volatile uint16_t wr_idx      ; ///< write pointer
-  volatile uint16_t rd_idx      ; ///< read pointer
-
-#if CFG_FIFO_MUTEX
-  tu_fifo_mutex_t mutex_wr;
-  tu_fifo_mutex_t mutex_rd;
+#if OSAL_MUTEX_REQUIRED
+  osal_mutex_t mutex_wr;
+  osal_mutex_t mutex_rd;
 #endif
 
 } tu_fifo_t;
 
-typedef struct
-{
+typedef struct {
   uint16_t len_lin  ; ///< linear length in item size
   uint16_t len_wrap ; ///< wrapped length in item size
   void * ptr_lin    ; ///< linear part start pointer
   void * ptr_wrap   ; ///< wrapped part start pointer
 } tu_fifo_buffer_info_t;
 
-#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \
-{                                                           \
+#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable){\
   .buffer               = _buffer,                          \
   .depth                = _depth,                           \
   .item_size            = sizeof(_type),                    \
   .overwritable         = _overwritable,                    \
-  .non_used_index_space = UINT16_MAX - (2*(_depth)-1),      \
-  .max_pointer_idx      = 2*(_depth)-1,                     \
 }
 
 #define TU_FIFO_DEF(_name, _depth, _type, _overwritable)                      \
     uint8_t _name##_buf[_depth*sizeof(_type)];                                \
     tu_fifo_t _name = TU_FIFO_INIT(_name##_buf, _depth, _type, _overwritable)
 
-
 bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable);
 bool tu_fifo_clear(tu_fifo_t *f);
 bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable);
 
-#if CFG_FIFO_MUTEX
+#if OSAL_MUTEX_REQUIRED
 TU_ATTR_ALWAYS_INLINE static inline
-void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t write_mutex_hdl, tu_fifo_mutex_t read_mutex_hdl)
-{
-  f->mutex_wr = write_mutex_hdl;
-  f->mutex_rd = read_mutex_hdl;
+void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex) {
+  f->mutex_wr = wr_mutex;
+  f->mutex_rd = rd_mutex;
 }
+#else
+#define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex)
 #endif
 
-bool     tu_fifo_write                  (tu_fifo_t* f, void const * p_data);
-uint16_t tu_fifo_write_n                (tu_fifo_t* f, void const * p_data, uint16_t n);
+bool     tu_fifo_write                  (tu_fifo_t* f, void const * data);
+uint16_t tu_fifo_write_n                (tu_fifo_t* f, void const * data, uint16_t n);
+#ifdef TUP_MEM_CONST_ADDR
 uint16_t tu_fifo_write_n_const_addr_full_words    (tu_fifo_t* f, const void * data, uint16_t n);
+#endif
 
-bool     tu_fifo_read                   (tu_fifo_t* f, void * p_buffer);
-uint16_t tu_fifo_read_n                 (tu_fifo_t* f, void * p_buffer, uint16_t n);
+bool     tu_fifo_read                   (tu_fifo_t* f, void * buffer);
+uint16_t tu_fifo_read_n                 (tu_fifo_t* f, void * buffer, uint16_t n);
+#ifdef TUP_MEM_CONST_ADDR
 uint16_t tu_fifo_read_n_const_addr_full_words     (tu_fifo_t* f, void * buffer, uint16_t n);
+#endif
 
 bool     tu_fifo_peek                   (tu_fifo_t* f, void * p_buffer);
 uint16_t tu_fifo_peek_n                 (tu_fifo_t* f, void * p_buffer, uint16_t n);
@@ -127,13 +177,12 @@ bool     tu_fifo_overflowed             (tu_fifo_t* f);
 void     tu_fifo_correct_read_pointer   (tu_fifo_t* f);
 
 TU_ATTR_ALWAYS_INLINE static inline
-uint16_t tu_fifo_depth(tu_fifo_t* f)
-{
+uint16_t tu_fifo_depth(tu_fifo_t* f) {
   return f->depth;
 }
 
 // Pointer modifications intended to be used in combinations with DMAs.
-// USE WITH CARE - NO SAFTY CHECKS CONDUCTED HERE! NOT MUTEX PROTECTED!
+// USE WITH CARE - NO SAFETY CHECKS CONDUCTED HERE! NOT MUTEX PROTECTED!
 void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n);
 void tu_fifo_advance_read_pointer (tu_fifo_t *f, uint16_t n);
 
@@ -143,7 +192,6 @@ void tu_fifo_advance_read_pointer (tu_fifo_t *f, uint16_t n);
 void tu_fifo_get_read_info (tu_fifo_t *f, tu_fifo_buffer_info_t *info);
 void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
 
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 86c68baf8..a0175d664 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -28,16 +28,22 @@
 #define TUSB_MCU_H_
 
 //--------------------------------------------------------------------+
-// Port Specific
-// TUP stand for TinyUSB Port (can be renamed)
+// Port/Platform Specific
+// TUP stand for TinyUSB Port/Platform (can be renamed)
 //--------------------------------------------------------------------+
 
 //------------- Unaligned Memory Access -------------//
 
-// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
-#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
-  #define TUP_ARCH_STRICT_ALIGN   0
+#ifdef __ARM_ARCH
+  // ARM Architecture set __ARM_FEATURE_UNALIGNED to 1 for mcu supports unaligned access
+  #if defined(__ARM_FEATURE_UNALIGNED) && __ARM_FEATURE_UNALIGNED == 1
+    #define TUP_ARCH_STRICT_ALIGN   0
+  #else
+    #define TUP_ARCH_STRICT_ALIGN   1
+  #endif
 #else
+  // TODO default to strict align for others
+  // Should investigate other architecture such as risv, xtensa, mips for optimal setting
   #define TUP_ARCH_STRICT_ALIGN   1
 #endif
 
@@ -48,87 +54,139 @@
  * - RHPORT_HIGHSPEED: support highspeed with on-chip PHY
  */
 
-//------------- NXP -------------//
+//--------------------------------------------------------------------+
+// NXP
+//--------------------------------------------------------------------+
 #if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
+  #define TUP_USBIP_IP3511
   #define TUP_DCD_ENDPOINT_MAX    5
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   #define TUP_DCD_ENDPOINT_MAX    16
   #define TUP_USBIP_OHCI
+  #define TUP_OHCI_RHPORTS        2
+
+#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
+   #define TUP_USBIP_IP3511
+   #define TUP_DCD_ENDPOINT_MAX   5
+
+#elif TU_CHECK_MCU(OPT_MCU_LPC54)
+  // TODO USB0 has 5, USB1 has 6
+  #define TUP_USBIP_IP3511
+  #define TUP_DCD_ENDPOINT_MAX    6
+
+#elif TU_CHECK_MCU(OPT_MCU_LPC55)
+  // TODO USB0 has 5, USB1 has 6
+  #define TUP_USBIP_IP3511
+  #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
-  // TODO USB0 has 6, USB1 has 4
+  // USB0 has 6 with HS PHY, USB1 has 4 only FS
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
 
   #define TUP_DCD_ENDPOINT_MAX    6
-  #define TUP_RHPORT_HIGHSPEED    1 // Port0 HS, Port1 FS
+  #define TUP_RHPORT_HIGHSPEED    1
 
-#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
-   #define TUP_DCD_ENDPOINT_MAX   5
+#elif TU_CHECK_MCU(OPT_MCU_MCXN9)
+  // USB0 is chipidea FS
+  #define TUP_USBIP_CHIPIDEA_FS
+  #define TUP_USBIP_CHIPIDEA_FS_MCX
 
-#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
-  // TODO USB0 has 5, USB1 has 6
-  #define TUP_DCD_ENDPOINT_MAX    6
-
-#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
-  // TODO USB0 has 5, USB1 has 6
-  #define TUP_DCD_ENDPOINT_MAX    6
-
-#elif TU_CHECK_MCU(OPT_MCU_MIMXRT)
+  // USB1 is chipidea HS
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
 
   #define TUP_DCD_ENDPOINT_MAX    8
-  #define TUP_RHPORT_HIGHSPEED    1 // Port0 HS, Port1 HS
+  #define TUP_RHPORT_HIGHSPEED    1
 
-#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
+#elif TU_CHECK_MCU(OPT_MCU_MCXA15)
+  // USB0 is chipidea FS
+  #define TUP_USBIP_CHIPIDEA_FS
+  #define TUP_USBIP_CHIPIDEA_FS_MCX
+
+  #define TUP_DCD_ENDPOINT_MAX    16
+
+#elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX)
+  #include "fsl_device_registers.h"
+
+  #define TUP_USBIP_CHIPIDEA_HS
+  #define TUP_USBIP_EHCI
+
+  #define TUP_DCD_ENDPOINT_MAX    8
+  #define TUP_RHPORT_HIGHSPEED    1
+
+  #if __CORTEX_M == 7
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  1
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
+  #endif
+
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
+  #define TUP_USBIP_CHIPIDEA_FS
+  #define TUP_USBIP_CHIPIDEA_FS_KINETIS
   #define TUP_DCD_ENDPOINT_MAX    16
 
 #elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
   #define TUP_DCD_ENDPOINT_MAX    16
 
-//------------- Nordic -------------//
+//--------------------------------------------------------------------+
+// Nordic
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // 8 CBI + 1 ISO
   #define TUP_DCD_ENDPOINT_MAX    9
 
-//------------- Microchip -------------//
+//--------------------------------------------------------------------+
+// Microchip
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
       TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_SAMG)
   #define TUP_DCD_ENDPOINT_MAX    6
-  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+  #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
 
 #elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
   #define TUP_DCD_ENDPOINT_MAX    10
   #define TUP_RHPORT_HIGHSPEED    1
-  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+  #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
 
 #elif TU_CHECK_MCU(OPT_MCU_PIC32MZ)
   #define TUP_DCD_ENDPOINT_MAX    8
-  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+  #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
 
 #elif TU_CHECK_MCU(OPT_MCU_PIC32MX, OPT_MCU_PIC32MM, OPT_MCU_PIC32MK) || \
       TU_CHECK_MCU(OPT_MCU_PIC24, OPT_MCU_DSPIC33)
   #define TUP_DCD_ENDPOINT_MAX    16
-  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+  #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
 
-//------------- ST -------------//
+//--------------------------------------------------------------------+
+// ST
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_STM32F0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F1)
+  // - F102, F103 use fsdev
+  // - F105, F107 use dwc2
   #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
       defined (STM32F107xB) || defined (STM32F107xC)
     #define TUP_USBIP_DWC2
     #define TUP_USBIP_DWC2_STM32
+    #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0
 
     #define TUP_DCD_ENDPOINT_MAX  4
-  #else
+  #elif defined(STM32F102x6) || defined(STM32F102xB) || \
+        defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+    #define TUP_USBIP_FSDEV
+    #define TUP_USBIP_FSDEV_STM32
     #define TUP_DCD_ENDPOINT_MAX  8
+  #else
+    #error "Unsupported STM32F1 mcu"
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F2)
@@ -139,6 +197,8 @@
   #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F3)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F4)
@@ -166,13 +226,39 @@
 
   #define TUP_DCD_ENDPOINT_MAX    9
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define TUP_DCD_ENDPOINT_MAX    8
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
+  // Device controller
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+
+  // TypeC controller
+  #define TUP_USBIP_TYPEC_STM32
+  #define TUP_DCD_ENDPOINT_MAX    8
+  #define TUP_TYPEC_RHPORTS_NUM 1
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32G0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define TUP_DCD_ENDPOINT_MAX    8
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32C0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L4)
+  // - L4x2, L4x3 use fsdev
+  // - L4x4, L4x6, L4x7, L4x9 use dwc2
   #if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
       defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
       defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
@@ -182,36 +268,88 @@
     #define TUP_USBIP_DWC2_STM32
 
     #define TUP_DCD_ENDPOINT_MAX  6
-  #else
+  #elif defined(STM32L412xx) || defined(STM32L422xx) || defined(STM32L432xx) || defined(STM32L433xx) || \
+        defined(STM32L442xx) || defined(STM32L443xx) || defined(STM32L452xx) || defined(STM32L462xx)
+    #define TUP_USBIP_FSDEV
+    #define TUP_USBIP_FSDEV_STM32
     #define TUP_DCD_ENDPOINT_MAX  8
+  #else
+    #error "Unsupported STM32L4 mcu"
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32WB)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32U5)
+  #if defined (STM32U535xx) || defined (STM32U545xx)
+    #define TUP_USBIP_FSDEV
+    #define TUP_USBIP_FSDEV_STM32
+    #define TUP_DCD_ENDPOINT_MAX    8
+
+  #else
+    #define TUP_USBIP_DWC2
+    #define TUP_USBIP_DWC2_STM32
+
+    // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
+    #if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \
+        defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
+      #define TUP_DCD_ENDPOINT_MAX  9
+      #define TUP_RHPORT_HIGHSPEED  1
+    #else
+      #define TUP_DCD_ENDPOINT_MAX  6
+    #endif
+  #endif
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define TUP_DCD_ENDPOINT_MAX    8
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32U0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define TUP_DCD_ENDPOINT_MAX    8
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
-  #define TUP_DCD_ENDPOINT_MAX    6
 
-//------------- Sony -------------//
+  // FS has 6, HS has 9
+  #define TUP_DCD_ENDPOINT_MAX    9
+
+  // MCU with on-chip HS Phy
+  #define TUP_RHPORT_HIGHSPEED    1
+
+//--------------------------------------------------------------------+
+// Sony
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_CXD56)
   #define TUP_DCD_ENDPOINT_MAX    7
   #define TUP_RHPORT_HIGHSPEED    1
-  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+  #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
 
-//------------- TI -------------//
+//--------------------------------------------------------------------+
+// TI
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+  #define TUP_USBIP_MUSB
+  #define TUP_USBIP_MUSB_TI
   #define TUP_DCD_ENDPOINT_MAX    8
 
-//------------- ValentyUSB -------------//
+//--------------------------------------------------------------------+
+// ValentyUSB (Litex)
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI)
   #define TUP_DCD_ENDPOINT_MAX    16
 
-//------------- Nuvoton -------------//
+//--------------------------------------------------------------------+
+// Nuvoton
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_NUC121, OPT_MCU_NUC126)
   #define TUP_DCD_ENDPOINT_MAX    8
 
@@ -222,66 +360,205 @@
   #define TUP_DCD_ENDPOINT_MAX    12
   #define TUP_RHPORT_HIGHSPEED    1
 
-//------------- Espressif -------------//
+//--------------------------------------------------------------------+
+// Espressif
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #define TUP_USBIP_DWC2
-  #define TUP_DCD_ENDPOINT_MAX    6
+  #define TUP_USBIP_DWC2_ESP32
+  #define TUP_DCD_ENDPOINT_MAX    7 // only 5 TX FIFO for endpoint IN
+  #define CFG_TUSB_OS_INC_PATH_DEFAULT   freertos/
 
-//------------- Dialog -------------//
+  // Disable slave if DMA is enabled
+  #define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT  !CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT  !CFG_TUH_DWC2_DMA_ENABLE
+
+#elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
+  #define TUP_USBIP_DWC2
+  #define TUP_USBIP_DWC2_ESP32
+  #define TUP_RHPORT_HIGHSPEED    1  // port0 FS, port1 HS
+  #define TUP_DCD_ENDPOINT_MAX    16 // FS 7 ep, HS 16 ep
+
+  #define CFG_TUSB_OS_INC_PATH_DEFAULT   freertos/
+
+  // Disable slave if DMA is enabled
+  #define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT  !CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT  !CFG_TUH_DWC2_DMA_ENABLE
+
+  // Enable dcache if DMA is enabled
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUH_DWC2_DMA_ENABLE
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT  64
+
+#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
+  #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421))
+  #error "MCUs are only supported with CFG_TUH_MAX3421 enabled"
+  #endif
+
+  #define TUP_DCD_ENDPOINT_MAX    0
+  #define CFG_TUSB_OS_INC_PATH_DEFAULT   freertos/
+
+//--------------------------------------------------------------------+
+// Dialog
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_DA1469X)
   #define TUP_DCD_ENDPOINT_MAX    4
 
-//------------- Raspberry Pi -------------//
+//--------------------------------------------------------------------+
+// Raspberry Pi
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_RP2040)
+  #define TUP_DCD_EDPT_ISO_ALLOC
   #define TUP_DCD_ENDPOINT_MAX    16
 
   #define TU_ATTR_FAST_FUNC       __attribute__((section(".time_critical.tinyusb")))
 
-//------------- Silabs -------------//
+//--------------------------------------------------------------------+
+// Silabs
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    7
 
-//------------- Renesas -------------//
-#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+//--------------------------------------------------------------------+
+// Renesas
+//--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX)
+  #define TUP_USBIP_RUSB2
   #define TUP_DCD_ENDPOINT_MAX    10
 
-//------------- GigaDevice -------------//
+//--------------------------------------------------------------------+
+// GigaDevice
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    4
 
-//------------- Broadcom -------------//
+//--------------------------------------------------------------------+
+// Broadcom
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
 
-//------------- Broadcom -------------//
+//--------------------------------------------------------------------+
+// Infineon
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_XMC4000)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    8
 
-//------------- BridgeTek -------------//
+//--------------------------------------------------------------------+
+// BridgeTek
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_FT90X)
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
+  #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
 
 #elif TU_CHECK_MCU(OPT_MCU_FT93X)
   #define TUP_DCD_ENDPOINT_MAX    16
   #define TUP_RHPORT_HIGHSPEED    1
+  #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
 
-//------------ Allwinner -------------//
+//--------------------------------------------------------------------+
+// Allwinner
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_F1C100S)
   #define TUP_DCD_ENDPOINT_MAX    4
 
+//--------------------------------------------------------------------+
+// WCH
+//--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_CH32F20X)
+  #define TUP_USBIP_WCH_USBHS
+  #define TUP_USBIP_WCH_USBFS
+
+  #if !defined(CFG_TUD_WCH_USBIP_USBFS)
+  #define CFG_TUD_WCH_USBIP_USBFS 0
+  #endif
+
+  #if !defined(CFG_TUD_WCH_USBIP_USBHS)
+  #define CFG_TUD_WCH_USBIP_USBHS (CFG_TUD_WCH_USBIP_USBFS ? 0 : 1)
+  #endif
+
+  #define TUP_RHPORT_HIGHSPEED    CFG_TUD_WCH_USBIP_USBHS
+  #define TUP_DCD_ENDPOINT_MAX    (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8)
+
+#elif TU_CHECK_MCU(OPT_MCU_CH32V103)
+  #define TUP_USBIP_WCH_USBFS
+
+  #if !defined(CFG_TUD_WCH_USBIP_USBFS)
+  #define CFG_TUD_WCH_USBIP_USBFS 1
+  #endif
+
+  #define TUP_DCD_ENDPOINT_MAX    8
+
+#elif TU_CHECK_MCU(OPT_MCU_CH32V20X)
+  // v20x support both FSDEV (USBD) and USBFS, default to FSDEV
+  #define TUP_USBIP_WCH_USBFS
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_CH32
+
+  #if !defined(CFG_TUD_WCH_USBIP_USBFS)
+  #define CFG_TUD_WCH_USBIP_USBFS 0
+  #endif
+
+  #if !defined(CFG_TUD_WCH_USBIP_FSDEV)
+  #define CFG_TUD_WCH_USBIP_FSDEV  (CFG_TUD_WCH_USBIP_USBFS ? 0 : 1)
+  #endif
+
+  #define TUP_DCD_ENDPOINT_MAX    8
+
+#elif TU_CHECK_MCU(OPT_MCU_CH32V307)
+  // v307 support both FS and HS, default to HS
+  #define TUP_USBIP_WCH_USBHS
+  #define TUP_USBIP_WCH_USBFS
+
+  #if !defined(CFG_TUD_WCH_USBIP_USBFS)
+  #define CFG_TUD_WCH_USBIP_USBFS 0
+  #endif
+
+  #if !defined(CFG_TUD_WCH_USBIP_USBHS)
+  #define CFG_TUD_WCH_USBIP_USBHS (CFG_TUD_WCH_USBIP_USBFS ? 0 : 1)
+  #endif
+
+  #define TUP_RHPORT_HIGHSPEED    CFG_TUD_WCH_USBIP_USBHS
+  #define TUP_DCD_ENDPOINT_MAX    (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8)
+
+//--------------------------------------------------------------------+
+// Analog Devices
+//--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX32690, OPT_MCU_MAX78002)
+  #define TUP_USBIP_MUSB
+  #define TUP_USBIP_MUSB_ADI
+  #define TUP_DCD_ENDPOINT_MAX    12
+  #define TUP_RHPORT_HIGHSPEED    1
+  #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
+
 #endif
 
+//--------------------------------------------------------------------+
+// External USB controller
+//--------------------------------------------------------------------+
+
+#if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+  #ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL
+    #define CFG_TUH_MAX3421_ENDPOINT_TOTAL  (8 + 4*(CFG_TUH_DEVICE_MAX-1))
+  #endif
+#endif
+
+
 //--------------------------------------------------------------------+
 // Default Values
 //--------------------------------------------------------------------+
 
-#ifndef TUP_DCD_ENDPOINT_MAX
+#ifndef TUP_MCU_MULTIPLE_CORE
+#define TUP_MCU_MULTIPLE_CORE 0
+#endif
+
+#if !defined(TUP_DCD_ENDPOINT_MAX) && defined(CFG_TUD_ENABLED) && CFG_TUD_ENABLED
   #warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define TUP_DCD_ENDPOINT_MAX    8
 #endif
@@ -296,4 +573,13 @@
   #define TU_ATTR_FAST_FUNC
 #endif
 
+// USBIP that support ISO alloc & activate API
+#if defined(TUP_USBIP_DWC2) || defined(TUP_USBIP_FSDEV) || defined(TUP_USBIP_MUSB)
+  #define TUP_DCD_EDPT_ISO_ALLOC
+#endif
+
+#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA_ENABLE == 0
+  #define TUP_MEM_CONST_ADDR
+#endif
+
 #endif
diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index b34506f65..c71775abb 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -24,23 +24,46 @@
  * This file is part of the TinyUSB stack.
  */
 
+#ifndef TUSB_PRIVATE_H_
+#define TUSB_PRIVATE_H_
 
-#ifndef _TUSB_PRIVATE_H_
-#define _TUSB_PRIVATE_H_
+// Internal Helper used by Host and Device Stack
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-typedef struct TU_ATTR_PACKED
-{
+#define TUP_USBIP_CONTROLLER_NUM 2
+extern tusb_role_t _tusb_rhport_role[TUP_USBIP_CONTROLLER_NUM];
+
+//--------------------------------------------------------------------+
+// Endpoint
+//--------------------------------------------------------------------+
+
+typedef struct TU_ATTR_PACKED {
   volatile uint8_t busy    : 1;
   volatile uint8_t stalled : 1;
   volatile uint8_t claimed : 1;
 }tu_edpt_state_t;
 
+typedef struct {
+  struct TU_ATTR_PACKED  {
+    uint8_t is_host   : 1; // 1: host, 0: device
+    uint8_t is_mps512 : 1; // 1: 512, 0: 64 since stream is used for Bulk only
+  };
+  uint8_t ep_addr;
+  uint16_t ep_bufsize;
+
+  uint8_t* ep_buf; // TODO xfer_fifo can skip this buffer
+  tu_fifo_t ff;
+
+  // mutex: read if rx, otherwise write
+  OSAL_MUTEX_DEF(ff_mutexdef);
+
+}tu_edpt_stream_t;
+
 //--------------------------------------------------------------------+
-// Internal Helper used by Host and Device Stack
+// Endpoint
 //--------------------------------------------------------------------+
 
 // Check if endpoint descriptor is valid per USB specs
@@ -58,8 +81,92 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
 // Release an endpoint with provided mutex
 bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
 
+//--------------------------------------------------------------------+
+// Endpoint Stream
+//--------------------------------------------------------------------+
+
+// Init an endpoint stream
+bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
+                         void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize);
+
+// Deinit an endpoint stream
+bool tu_edpt_stream_deinit(tu_edpt_stream_t* s);
+
+// Open an stream for an endpoint
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_edpt_stream_open(tu_edpt_stream_t* s, tusb_desc_endpoint_t const *desc_ep) {
+  tu_fifo_clear(&s->ff);
+  s->ep_addr = desc_ep->bEndpointAddress;
+  s->is_mps512 = (tu_edpt_packet_size(desc_ep) == 512) ? 1 : 0;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_edpt_stream_close(tu_edpt_stream_t* s) {
+  s->ep_addr = 0;
+}
+
+// Clear fifo
+TU_ATTR_ALWAYS_INLINE static inline
+bool tu_edpt_stream_clear(tu_edpt_stream_t* s) {
+  return tu_fifo_clear(&s->ff);
+}
+
+//--------------------------------------------------------------------+
+// Stream Write
+//--------------------------------------------------------------------+
+
+// Write to stream
+uint32_t tu_edpt_stream_write(uint8_t hwid, tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize);
+
+// Start an usb transfer if endpoint is not busy
+uint32_t tu_edpt_stream_write_xfer(uint8_t hwid, tu_edpt_stream_t* s);
+
+// Start an zero-length packet if needed
+bool tu_edpt_stream_write_zlp_if_needed(uint8_t hwid, tu_edpt_stream_t* s, uint32_t last_xferred_bytes);
+
+// Get the number of bytes available for writing to FIFO
+// Note: if no fifo, return endpoint size if not busy, 0 otherwise
+uint32_t tu_edpt_stream_write_available(uint8_t hwid, tu_edpt_stream_t* s);
+
+//--------------------------------------------------------------------+
+// Stream Read
+//--------------------------------------------------------------------+
+
+// Read from stream
+uint32_t tu_edpt_stream_read(uint8_t hwid, tu_edpt_stream_t* s, void* buffer, uint32_t bufsize);
+
+// Start an usb transfer if endpoint is not busy
+uint32_t tu_edpt_stream_read_xfer(uint8_t hwid, tu_edpt_stream_t* s);
+
+// Must be called in the transfer complete callback
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes) {
+  if (tu_fifo_depth(&s->ff)) {
+    tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes);
+  }
+}
+
+// Same as tu_edpt_stream_read_xfer_complete but skip the first n bytes
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_edpt_stream_read_xfer_complete_offset(tu_edpt_stream_t* s, uint32_t xferred_bytes, uint32_t skip_offset) {
+  if (tu_fifo_depth(&s->ff) && (skip_offset < xferred_bytes)) {
+    tu_fifo_write_n(&s->ff, s->ep_buf + skip_offset, (uint16_t) (xferred_bytes - skip_offset));
+  }
+}
+
+// Get the number of bytes available for reading
+TU_ATTR_ALWAYS_INLINE static inline
+uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s) {
+  return (uint32_t) tu_fifo_count(&s->ff);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline
+bool tu_edpt_stream_peek(tu_edpt_stream_t* s, uint8_t* ch) {
+  return tu_fifo_peek(&s->ff, ch);
+}
+
 #ifdef __cplusplus
  }
 #endif
 
-#endif /* _TUSB_PRIVATE_H_ */
+#endif
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index e11f08dd1..9e4d9380c 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -24,12 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-/** \ingroup group_usb_definitions
- *  \defgroup USBDef_Type USB Types
- *  @{ */
-
-#ifndef _TUSB_TYPES_H_
-#define _TUSB_TYPES_H_
+#ifndef TUSB_TYPES_H_
+#define TUSB_TYPES_H_
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -39,39 +35,87 @@
  extern "C" {
 #endif
 
+//------------- Device DCache declaration -------------//
+#define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \
+  (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size))
+
+// Declare an endpoint buffer with uint8_t[size]
+#define TUD_EPBUF_DEF(_name, _size) \
+  union { \
+    CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
+    uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
+  }
+
+// Declare an endpoint buffer with a type
+#define TUD_EPBUF_TYPE_DEF(_type, _name) \
+  union { \
+    CFG_TUD_MEM_ALIGN _type _name; \
+    uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
+  }
+
+//------------- Host DCache declaration -------------//
+#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \
+  (TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size))
+
+// Declare an endpoint buffer with uint8_t[size]
+#define TUH_EPBUF_DEF(_name, _size) \
+  union { \
+    CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
+    uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
+  }
+
+// Declare an endpoint buffer with a type
+#define TUH_EPBUF_TYPE_DEF(_type, _name) \
+  union { \
+    CFG_TUH_MEM_ALIGN _type _name; \
+    uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
+  }
+
+
 /*------------------------------------------------------------------*/
 /* CONSTANTS
  *------------------------------------------------------------------*/
 
+typedef enum {
+  TUSB_ROLE_INVALID = 0,
+  TUSB_ROLE_DEVICE  = 0x1,
+  TUSB_ROLE_HOST    = 0x2,
+} tusb_role_t;
+
 /// defined base on EHCI specs value for Endpoint Speed
-typedef enum
-{
+typedef enum {
   TUSB_SPEED_FULL = 0,
   TUSB_SPEED_LOW  = 1,
   TUSB_SPEED_HIGH = 2,
+  TUSB_SPEED_AUTO = 0xaa,
   TUSB_SPEED_INVALID = 0xff,
-}tusb_speed_t;
+} tusb_speed_t;
 
 /// defined base on USB Specs Endpoint's bmAttributes
-typedef enum
-{
-  TUSB_XFER_CONTROL = 0 ,
-  TUSB_XFER_ISOCHRONOUS ,
-  TUSB_XFER_BULK        ,
-  TUSB_XFER_INTERRUPT
-}tusb_xfer_type_t;
+typedef enum {
+  TUSB_XFER_CONTROL     = 0,
+  TUSB_XFER_ISOCHRONOUS = 1,
+  TUSB_XFER_BULK        = 2,
+  TUSB_XFER_INTERRUPT   = 3
+} tusb_xfer_type_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_DIR_OUT = 0,
   TUSB_DIR_IN  = 1,
 
   TUSB_DIR_IN_MASK = 0x80
-}tusb_dir_t;
+} tusb_dir_t;
 
-/// Isochronous End Point Attributes
-typedef enum
-{
+enum {
+  TUSB_EPSIZE_BULK_FS = 64,
+  TUSB_EPSIZE_BULK_HS = 512,
+
+  TUSB_EPSIZE_ISO_FS_MAX = 1023,
+  TUSB_EPSIZE_ISO_HS_MAX = 1024,
+};
+
+/// Isochronous Endpoint Attributes
+typedef enum {
   TUSB_ISO_EP_ATT_NO_SYNC         = 0x00,
   TUSB_ISO_EP_ATT_ASYNCHRONOUS    = 0x04,
   TUSB_ISO_EP_ATT_ADAPTIVE        = 0x08,
@@ -79,11 +123,10 @@ typedef enum
   TUSB_ISO_EP_ATT_DATA            = 0x00, ///< Data End Point
   TUSB_ISO_EP_ATT_EXPLICIT_FB     = 0x10, ///< Feedback End Point
   TUSB_ISO_EP_ATT_IMPLICIT_FB     = 0x20, ///< Data endpoint that also serves as an implicit feedback
-}tusb_iso_ep_attribute_t;
+} tusb_iso_ep_attribute_t;
 
 /// USB Descriptor Types
-typedef enum
-{
+typedef enum {
   TUSB_DESC_DEVICE                = 0x01,
   TUSB_DESC_CONFIGURATION         = 0x02,
   TUSB_DESC_STRING                = 0x03,
@@ -110,10 +153,9 @@ typedef enum
 
   TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION     = 0x30,
   TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31
-}tusb_desc_type_t;
+} tusb_desc_type_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_GET_STATUS        = 0  ,
   TUSB_REQ_CLEAR_FEATURE     = 1  ,
   TUSB_REQ_RESERVED          = 2  ,
@@ -127,25 +169,22 @@ typedef enum
   TUSB_REQ_GET_INTERFACE     = 10 ,
   TUSB_REQ_SET_INTERFACE     = 11 ,
   TUSB_REQ_SYNCH_FRAME       = 12
-}tusb_request_code_t;
+} tusb_request_code_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_FEATURE_EDPT_HALT     = 0,
   TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1,
   TUSB_REQ_FEATURE_TEST_MODE     = 2
-}tusb_request_feature_selector_t;
+} tusb_request_feature_selector_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_TYPE_STANDARD = 0,
   TUSB_REQ_TYPE_CLASS,
   TUSB_REQ_TYPE_VENDOR,
   TUSB_REQ_TYPE_INVALID
 } tusb_request_type_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_RCPT_DEVICE =0,
   TUSB_REQ_RCPT_INTERFACE,
   TUSB_REQ_RCPT_ENDPOINT,
@@ -153,8 +192,7 @@ typedef enum
 } tusb_request_recipient_t;
 
 // https://www.usb.org/defined-class-codes
-typedef enum
-{
+typedef enum {
   TUSB_CLASS_UNSPECIFIED          = 0    ,
   TUSB_CLASS_AUDIO                = 1    ,
   TUSB_CLASS_CDC                  = 2    ,
@@ -178,26 +216,23 @@ typedef enum
   TUSB_CLASS_MISC                 = 0xEF ,
   TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE ,
   TUSB_CLASS_VENDOR_SPECIFIC      = 0xFF
-}tusb_class_code_t;
+} tusb_class_code_t;
 
 typedef enum
 {
   MISC_SUBCLASS_COMMON = 2
 }misc_subclass_type_t;
 
-typedef enum
-{
+typedef enum {
   MISC_PROTOCOL_IAD = 1
-}misc_protocol_type_t;
+} misc_protocol_type_t;
 
-typedef enum
-{
+typedef enum {
   APP_SUBCLASS_USBTMC = 0x03,
   APP_SUBCLASS_DFU_RUNTIME = 0x01
 } app_subclass_type_t;
 
-typedef enum
-{
+typedef enum {
   DEVICE_CAPABILITY_WIRELESS_USB               = 0x01,
   DEVICE_CAPABILITY_USB20_EXTENSION            = 0x02,
   DEVICE_CAPABILITY_SUPERSPEED_USB             = 0x03,
@@ -214,38 +249,46 @@ typedef enum
   DEVICE_CAPABILITY_AUTHENTICATION             = 0x0E,
   DEVICE_CAPABILITY_BILLBOARD_EX               = 0x0F,
   DEVICE_CAPABILITY_CONFIGURATION_SUMMARY      = 0x10
-}device_capability_type_t;
+} device_capability_type_t;
 
 enum {
-  TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5),
-  TUSB_DESC_CONFIG_ATT_SELF_POWERED  = TU_BIT(6),
+  TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = 1u << 5,
+  TUSB_DESC_CONFIG_ATT_SELF_POWERED  = 1u << 6,
 };
 
 #define TUSB_DESC_CONFIG_POWER_MA(x)  ((x)/2)
 
-typedef enum
-{
-  XFER_RESULT_SUCCESS,
+// USB 2.0 Spec Table 9-7: Test Mode Selectors
+typedef enum {
+  TUSB_FEATURE_TEST_J = 1,
+  TUSB_FEATURE_TEST_K = 2,
+  TUSB_FEATURE_TEST_SE0_NAK = 3,
+  TUSB_FEATURE_TEST_PACKET = 4,
+  TUSB_FEATURE_TEST_FORCE_ENABLE = 5,
+} tusb_feature_test_mode_t;
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+typedef enum {
+  XFER_RESULT_SUCCESS = 0,
   XFER_RESULT_FAILED,
   XFER_RESULT_STALLED,
   XFER_RESULT_TIMEOUT,
   XFER_RESULT_INVALID
-}xfer_result_t;
+} xfer_result_t;
 
-enum // TODO remove
-{
+// TODO remove
+enum {
   DESC_OFFSET_LEN  = 0,
   DESC_OFFSET_TYPE = 1
 };
 
-enum
-{
+enum {
   INTERFACE_INVALID_NUMBER = 0xff
 };
 
-
-typedef enum
-{
+typedef enum {
   MS_OS_20_SET_HEADER_DESCRIPTOR       = 0x00,
   MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01,
   MS_OS_20_SUBSET_HEADER_FUNCTION      = 0x02,
@@ -257,14 +300,25 @@ typedef enum
   MS_OS_20_FEATURE_VENDOR_REVISION     = 0x08
 } microsoft_os_20_type_t;
 
-enum
-{
-  CONTROL_STAGE_IDLE,
+enum {
+  CONTROL_STAGE_IDLE = 0,
   CONTROL_STAGE_SETUP,
   CONTROL_STAGE_DATA,
   CONTROL_STAGE_ACK
 };
 
+enum {
+  TUSB_INDEX_INVALID_8 = 0xFFu
+};
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+typedef struct {
+  tusb_role_t role;
+  tusb_speed_t speed;
+} tusb_rhport_init_t;
+
 //--------------------------------------------------------------------+
 // USB Descriptors
 //--------------------------------------------------------------------+
@@ -274,15 +328,14 @@ TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
 /// USB Device Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes.
   uint8_t  bDescriptorType    ; ///< DEVICE Descriptor Type.
-  uint16_t bcdUSB             ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant.
+  uint16_t bcdUSB             ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H).
 
-  uint8_t  bDeviceClass       ; ///< Class code (assigned by the USB-IF). \li If this field is reset to zero, each interface within a configuration specifies its own class information and the various interfaces operate independently. \li If this field is set to a value between 1 and FEH, the device supports different class specifications on different interfaces and the interfaces may not operate independently. This value identifies the class definition used for the aggregate interfaces. \li If this field is set to FFH, the device class is vendor-specific.
-  uint8_t  bDeviceSubClass    ; ///< Subclass code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass field. \li If the bDeviceClass field is reset to zero, this field must also be reset to zero. \li If the bDeviceClass field is not set to FFH, all values are reserved for assignment by the USB-IF.
-  uint8_t  bDeviceProtocol    ; ///< Protocol code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass and the bDeviceSubClass fields. If a device supports class-specific protocols on a device basis as opposed to an interface basis, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use class-specific protocols on a device basis. However, it may use classspecific protocols on an interface basis. \li If this field is set to FFH, the device uses a vendor-specific protocol on a device basis.
+  uint8_t  bDeviceClass       ; ///< Class code (assigned by the USB-IF).
+  uint8_t  bDeviceSubClass    ; ///< Subclass code (assigned by the USB-IF).
+  uint8_t  bDeviceProtocol    ; ///< Protocol code (assigned by the USB-IF).
   uint8_t  bMaxPacketSize0    ; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64.
 
   uint16_t idVendor           ; ///< Vendor ID (assigned by the USB-IF).
@@ -298,8 +351,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct");
 
 // USB Binary Device Object Store (BOS) Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType ; ///< CONFIGURATION Descriptor Type
   uint16_t wTotalLength    ; ///< Total length of data returned for this descriptor
@@ -309,8 +361,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_bos_t) == 5, "size is not correct");
 
 /// USB Configuration Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength             ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType     ; ///< CONFIGURATION Descriptor Type
   uint16_t wTotalLength        ; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration.
@@ -325,8 +376,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_configuration_t) == 9, "size is not correct");
 
 /// USB Interface Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType    ; ///< INTERFACE Descriptor Type
 
@@ -342,8 +392,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_interface_t) == 9, "size is not correct");
 
 /// USB Endpoint Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength          ; // Size of this descriptor in bytes
   uint8_t  bDescriptorType  ; // ENDPOINT Descriptor Type
 
@@ -363,8 +412,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_endpoint_t) == 7, "size is not correct");
 
 /// USB Other Speed Configuration Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength             ; ///< Size of descriptor
   uint8_t  bDescriptorType     ; ///< Other_speed_Configuration Type
   uint16_t wTotalLength        ; ///< Total length of data returned
@@ -377,8 +425,7 @@ typedef struct TU_ATTR_PACKED
 } tusb_desc_other_speed_t;
 
 /// USB Device Qualifier Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of descriptor
   uint8_t  bDescriptorType    ; ///< Device Qualifier Type
   uint16_t bcdUSB             ; ///< USB specification version number (e.g., 0200H for V2.00)
@@ -395,8 +442,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_device_qualifier_t) == 10, "size is not correct");
 
 /// USB Interface Association Descriptor (IAD ECN)
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t bLength           ; ///< Size of descriptor
   uint8_t bDescriptorType   ; ///< Other_speed_Configuration Type
 
@@ -410,17 +456,17 @@ typedef struct TU_ATTR_PACKED
   uint8_t iFunction         ; ///< Index of the string descriptor describing the interface association.
 } tusb_desc_interface_assoc_t;
 
+TU_VERIFY_STATIC( sizeof(tusb_desc_interface_assoc_t) == 8, "size is not correct");
+
 // USB String Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType ; ///< Descriptor Type
   uint16_t unicode_string[];
 } tusb_desc_string_t;
 
 // USB Binary Device Object Store (BOS)
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType ;
   uint8_t bDevCapabilityType;
@@ -429,9 +475,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t CapabilityData[];
 } tusb_desc_bos_platform_t;
 
-// USB WebuSB URL Descriptor
-typedef struct TU_ATTR_PACKED
-{
+// USB WebUSB URL Descriptor
+typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
   uint8_t bScheme;
@@ -439,8 +484,7 @@ typedef struct TU_ATTR_PACKED
 } tusb_desc_webusb_url_t;
 
 // DFU Functional Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
 
@@ -461,10 +505,11 @@ typedef struct TU_ATTR_PACKED
   uint16_t bcdDFUVersion;
 } tusb_desc_dfu_functional_t;
 
-/*------------------------------------------------------------------*/
-/* Types
- *------------------------------------------------------------------*/
-typedef struct TU_ATTR_PACKED{
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+typedef struct TU_ATTR_PACKED {
   union {
     struct TU_ATTR_PACKED {
       uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
@@ -483,7 +528,6 @@ typedef struct TU_ATTR_PACKED{
 
 TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 
-
 TU_ATTR_PACKED_END  // End of all packed definitions
 TU_ATTR_BIT_FIELD_ORDER_END
 
@@ -492,37 +536,26 @@ TU_ATTR_BIT_FIELD_ORDER_END
 //--------------------------------------------------------------------+
 
 // Get direction from Endpoint address
-TU_ATTR_ALWAYS_INLINE static inline tusb_dir_t tu_edpt_dir(uint8_t addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline tusb_dir_t tu_edpt_dir(uint8_t addr) {
   return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
 }
 
 // Get Endpoint number from address
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr) {
   return (uint8_t)(addr & (~TUSB_DIR_IN_MASK));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) {
   return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep)
-{
-  return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0);
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) {
+  return tu_le16toh(desc_ep->wMaxPacketSize) & 0x7FF;
 }
 
 #if CFG_TUSB_DEBUG
-TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir)
-{
-  static const char *str[] = {"out", "in"};
-  return str[dir];
-}
-
-TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t)
-{
-  static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
+TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) {
+  tu_static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
   return str[t];
 }
 #endif
@@ -530,26 +563,34 @@ TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_
 //--------------------------------------------------------------------+
 // Descriptor helper
 //--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc)
-{
+
+// return next descriptor
+TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc) {
   uint8_t const* desc8 = (uint8_t const*) desc;
   return desc8 + desc8[DESC_OFFSET_LEN];
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc)
-{
+// get descriptor type
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc) {
   return ((uint8_t const*) desc)[DESC_OFFSET_TYPE];
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc)
-{
+// get descriptor length
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc) {
   return ((uint8_t const*) desc)[DESC_OFFSET_LEN];
 }
 
+// find descriptor that match byte1 (type)
+uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1);
+
+// find descriptor that match byte1 (type) and byte2
+uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2);
+
+// find descriptor that match byte1 (type) and byte2
+uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3);
+
 #ifdef __cplusplus
  }
 #endif
 
-#endif /* _TUSB_TYPES_H_ */
-
-/** @} */
+#endif // TUSB_TYPES_H_
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index a52a6d269..6d02d3572 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -56,12 +56,8 @@
  *   #define TU_VERIFY(cond)                  if(cond) return false;
  *   #define TU_VERIFY(cond,ret)              if(cond) return ret;
  *
- *   #define TU_VERIFY_HDLR(cond,handler)     if(cond) {handler; return false;}
- *   #define TU_VERIFY_HDLR(cond,ret,handler) if(cond) {handler; return ret;}
- *
- *   #define TU_ASSERT(cond)                  if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return false;}
- *   #define TU_ASSERT(cond,ret)              if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
- *
+ *   #define TU_ASSERT(cond)                  if(cond) {TU_MESS_FAILED(); TU_BREAKPOINT(), return false;}
+ *   #define TU_ASSERT(cond,ret)              if(cond) {TU_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
  *------------------------------------------------------------------*/
 
 #ifdef __cplusplus
@@ -74,20 +70,20 @@
 
 #if CFG_TUSB_DEBUG
   #include <stdio.h>
-  #define _MESS_FAILED()    tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
+  #define TU_MESS_FAILED()    tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
 #else
-  #define _MESS_FAILED() do {} while (0)
+  #define TU_MESS_FAILED() do {} while (0)
 #endif
 
-// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)
-  #define TU_BREAKPOINT() do                                                                                \
-  {                                                                                                         \
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
+    defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+  #define TU_BREAKPOINT() do {                                                                              \
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
     if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */            \
   } while(0)
 
-#elif defined(__riscv)
+#elif defined(__riscv) && !TUSB_MCU_VENDOR_ESPRESSIF
   #define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0)
 
 #elif defined(_mips)
@@ -97,40 +93,20 @@
   #define TU_BREAKPOINT() do {} while (0)
 #endif
 
-/*------------------------------------------------------------------*/
-/* Macro Generator
- *------------------------------------------------------------------*/
-
-// Helper to implement optional parameter for TU_VERIFY Macro family
-#define _GET_3RD_ARG(arg1, arg2, arg3, ...)        arg3
-#define _GET_4TH_ARG(arg1, arg2, arg3, arg4, ...)  arg4
-
-/*------------- Generator for TU_VERIFY and TU_VERIFY_HDLR -------------*/
-#define TU_VERIFY_DEFINE(_cond, _handler, _ret)  do            \
-{                                                              \
-  if ( !(_cond) ) { _handler; return _ret;  }                  \
-} while(0)
-
 /*------------------------------------------------------------------*/
 /* TU_VERIFY
  * - TU_VERIFY_1ARGS : return false if failed
  * - TU_VERIFY_2ARGS : return provided value if failed
  *------------------------------------------------------------------*/
-#define TU_VERIFY_1ARGS(_cond)                         TU_VERIFY_DEFINE(_cond, , false)
-#define TU_VERIFY_2ARGS(_cond, _ret)                   TU_VERIFY_DEFINE(_cond, , _ret)
+#define TU_VERIFY_DEFINE(_cond, _ret)    \
+  do {                                   \
+    if ( !(_cond) ) { return _ret; }     \
+  } while(0)
 
-#define TU_VERIFY(...)                   _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, UNUSED)(__VA_ARGS__)
+#define TU_VERIFY_1ARGS(_cond)         TU_VERIFY_DEFINE(_cond, false)
+#define TU_VERIFY_2ARGS(_cond, _ret)   TU_VERIFY_DEFINE(_cond, _ret)
 
-
-/*------------------------------------------------------------------*/
-/* TU_VERIFY WITH HANDLER
- * - TU_VERIFY_HDLR_2ARGS : execute handler, return false if failed
- * - TU_VERIFY_HDLR_3ARGS : execute handler, return provided error if failed
- *------------------------------------------------------------------*/
-#define TU_VERIFY_HDLR_2ARGS(_cond, _handler)           TU_VERIFY_DEFINE(_cond, _handler, false)
-#define TU_VERIFY_HDLR_3ARGS(_cond, _handler, _ret)     TU_VERIFY_DEFINE(_cond, _handler, _ret)
-
-#define TU_VERIFY_HDLR(...)              _GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_HDLR_3ARGS, TU_VERIFY_HDLR_2ARGS,UNUSED)(__VA_ARGS__)
+#define TU_VERIFY(...)                 TU_GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, _dummy)(__VA_ARGS__)
 
 /*------------------------------------------------------------------*/
 /* ASSERT
@@ -138,19 +114,20 @@
  * - 1 arg : return false if failed
  * - 2 arg : return error if failed
  *------------------------------------------------------------------*/
-#define ASSERT_1ARGS(_cond)            TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), false)
-#define ASSERT_2ARGS(_cond, _ret)      TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), _ret)
+#define TU_ASSERT_DEFINE(_cond, _ret)                                 \
+  do {                                                                \
+    if ( !(_cond) ) { TU_MESS_FAILED(); TU_BREAKPOINT(); return _ret; } \
+  } while(0)
+
+#define TU_ASSERT_1ARGS(_cond)         TU_ASSERT_DEFINE(_cond, false)
+#define TU_ASSERT_2ARGS(_cond, _ret)   TU_ASSERT_DEFINE(_cond, _ret)
 
 #ifndef TU_ASSERT
-#define TU_ASSERT(...)             _GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__)
+#define TU_ASSERT(...)                 TU_GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_2ARGS, TU_ASSERT_1ARGS, _dummy)(__VA_ARGS__)
 #endif
 
-/*------------------------------------------------------------------*/
-/* ASSERT HDLR
- *------------------------------------------------------------------*/
-
 #ifdef __cplusplus
  }
 #endif
 
-#endif /* TUSB_VERIFY_H_ */
+#endif
diff --git a/src/device/dcd.h b/src/device/dcd.h
index c1780f656..789552d47 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_DCD_H_
-#define _TUSB_DCD_H_
+#ifndef TUSB_DCD_H_
+#define TUSB_DCD_H_
 
 #include "common/tusb_common.h"
 #include "osal/osal.h"
@@ -35,43 +35,28 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Configuration
-//--------------------------------------------------------------------+
-
-#ifndef CFG_TUD_ENDPPOINT_MAX
-  #define CFG_TUD_ENDPPOINT_MAX   TUP_DCD_ENDPOINT_MAX
-#endif
-
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
 
-typedef enum
-{
-  DCD_EVENT_INVALID = 0,
-  DCD_EVENT_BUS_RESET,
-  DCD_EVENT_UNPLUGGED,
-  DCD_EVENT_SOF,
-  DCD_EVENT_SUSPEND, // TODO LPM Sleep L1 support
-  DCD_EVENT_RESUME,
-
-  DCD_EVENT_SETUP_RECEIVED,
-  DCD_EVENT_XFER_COMPLETE,
-
-  // Not an DCD event, just a convenient way to defer ISR function
-  USBD_EVENT_FUNC_CALL,
-
+typedef enum {
+  DCD_EVENT_INVALID = 0,    // 0
+  DCD_EVENT_BUS_RESET,      // 1
+  DCD_EVENT_UNPLUGGED,      // 2
+  DCD_EVENT_SOF,            // 3
+  DCD_EVENT_SUSPEND,        // 4 TODO LPM Sleep L1 support
+  DCD_EVENT_RESUME,         // 5
+  DCD_EVENT_SETUP_RECEIVED, // 6
+  DCD_EVENT_XFER_COMPLETE,  // 7
+  USBD_EVENT_FUNC_CALL,     // 8 Not an DCD event, just a convenient way to defer ISR function
   DCD_EVENT_COUNT
 } dcd_eventid_t;
 
-typedef struct TU_ATTR_ALIGNED(4)
-{
+typedef struct TU_ATTR_ALIGNED(4) {
   uint8_t rhport;
   uint8_t event_id;
 
-  union
-  {
+  union {
     // BUS RESET
     struct {
       tusb_speed_t speed;
@@ -102,12 +87,31 @@ typedef struct TU_ATTR_ALIGNED(4)
 
 //TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct");
 
+//--------------------------------------------------------------------+
+// Memory API
+//--------------------------------------------------------------------+
+
+// clean/flush data cache: write cache -> memory.
+// Required before an DMA TX transfer to make sure data is in memory
+bool dcd_dcache_clean(const void* addr, uint32_t data_size);
+
+// invalidate data cache: mark cache as invalid, next read will read from memory
+// Required BOTH before and after an DMA RX transfer
+bool dcd_dcache_invalidate(const void* addr, uint32_t data_size);
+
+// clean and invalidate data cache
+// Required before an DMA transfer where memory is both read/write by DMA
+bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
+
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
 
 // Initialize controller to device mode
-void dcd_init       (uint8_t rhport);
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
+
+// Deinitialize controller, unset device mode.
+bool dcd_deinit(uint8_t rhport);
 
 // Interrupt Handler
 void dcd_int_handler(uint8_t rhport);
@@ -125,21 +129,25 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr);
 void dcd_remote_wakeup(uint8_t rhport);
 
 // Connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(uint8_t rhport) TU_ATTR_WEAK;
+void dcd_connect(uint8_t rhport);
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK;
+void dcd_disconnect(uint8_t rhport);
 
 // Enable/Disable Start-of-frame interrupt. Default is disabled
 void dcd_sof_enable(uint8_t rhport, bool en);
 
+#if CFG_TUD_TEST_MODE
+// Put device into a test mode (needs power cycle to quit)
+void dcd_enter_test_mode(uint8_t rhport, tusb_feature_test_mode_t test_selector);
+#endif
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
 
 // Invoked when a control transfer's status stage is complete.
 // May help DCD to prepare for next control transfer, this API is optional.
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK;
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request);
 
 // Configure endpoint's registers according to descriptor
 bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
@@ -149,10 +157,6 @@ bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * desc
 // required for multiple configuration support.
 void dcd_edpt_close_all       (uint8_t rhport);
 
-// Close an endpoint.
-// Since it is weak, caller must TU_ASSERT this function's existence before calling it.
-void dcd_edpt_close           (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK;
-
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
 bool dcd_edpt_xfer            (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
 
@@ -167,6 +171,20 @@ void dcd_edpt_stall           (uint8_t rhport, uint8_t ep_addr);
 // This API never calls with control endpoints, since it is auto cleared when receiving setup packet
 void dcd_edpt_clear_stall     (uint8_t rhport, uint8_t ep_addr);
 
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+// Allocate packet buffer used by ISO endpoints
+// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
+
+// Configure and enable an ISO endpoint according to descriptor
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
+
+#else
+// Close an endpoint.
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr);
+
+#endif
+
 //--------------------------------------------------------------------+
 // Event API (implemented by stack)
 //--------------------------------------------------------------------+
@@ -175,44 +193,46 @@ void dcd_edpt_clear_stall     (uint8_t rhport, uint8_t ep_addr);
 extern void dcd_event_handler(dcd_event_t const * event, bool in_isr);
 
 // helper to send bus signal event
-TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr)
-{
-  dcd_event_t event = { .rhport = rhport, .event_id = eid };
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr) {
+  dcd_event_t event;
+  event.rhport = rhport;
+  event.event_id = eid;
   dcd_event_handler(&event, in_isr);
 }
 
 // helper to send bus reset event
-TU_ATTR_ALWAYS_INLINE static inline  void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr)
-{
-  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET };
+TU_ATTR_ALWAYS_INLINE static inline  void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr) {
+  dcd_event_t event;
+  event.rhport = rhport;
+  event.event_id = DCD_EVENT_BUS_RESET;
   event.bus_reset.speed = speed;
   dcd_event_handler(&event, in_isr);
 }
 
 // helper to send setup received
-TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr)
-{
-  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
-  memcpy(&event.setup_received, setup, 8);
-
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr) {
+  dcd_event_t event;
+  event.rhport = rhport;
+  event.event_id = DCD_EVENT_SETUP_RECEIVED;
+  memcpy(&event.setup_received, setup, sizeof(tusb_control_request_t));
   dcd_event_handler(&event, in_isr);
 }
 
 // helper to send transfer complete event
-TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr)
-{
-  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE };
-
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr) {
+  dcd_event_t event;
+  event.rhport = rhport;
+  event.event_id = DCD_EVENT_XFER_COMPLETE;
   event.xfer_complete.ep_addr = ep_addr;
   event.xfer_complete.len     = xferred_bytes;
   event.xfer_complete.result  = result;
-
   dcd_event_handler(&event, in_isr);
 }
 
-static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr)
-{
-  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SOF };
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr) {
+  dcd_event_t event;
+  event.rhport = rhport;
+  event.event_id = DCD_EVENT_SOF;
   event.sof.frame_count = frame_count;
   dcd_event_handler(&event, in_isr);
 }
@@ -221,4 +241,4 @@ static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_i
  }
 #endif
 
-#endif /* _TUSB_DCD_H_ */
+#endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 1cede1289..20f803563 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -38,14 +38,80 @@
 //--------------------------------------------------------------------+
 // USBD Configuration
 //--------------------------------------------------------------------+
-
-// Debug level of USBD
-#define USBD_DBG   2
-
 #ifndef CFG_TUD_TASK_QUEUE_SZ
   #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
 
+//--------------------------------------------------------------------+
+// Weak stubs: invoked if no strong implementation is available
+//--------------------------------------------------------------------+
+TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
+  (void) rhport; (void) eventid; (void) in_isr;
+}
+
+TU_ATTR_WEAK void tud_sof_cb(uint32_t frame_count) {
+  (void) frame_count;
+}
+
+TU_ATTR_WEAK uint8_t const* tud_descriptor_bos_cb(void) {
+  return NULL;
+}
+
+TU_ATTR_WEAK uint8_t const* tud_descriptor_device_qualifier_cb(void) {
+  return NULL;
+}
+
+TU_ATTR_WEAK uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void) index;
+  return NULL;
+}
+
+TU_ATTR_WEAK void tud_mount_cb(void) {
+}
+
+TU_ATTR_WEAK void tud_umount_cb(void) {
+}
+
+TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en) {
+  (void) remote_wakeup_en;
+}
+
+TU_ATTR_WEAK void tud_resume_cb(void) {
+}
+
+TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) {
+  (void) rhport; (void) stage; (void) request;
+  return false;
+}
+
+TU_ATTR_WEAK bool dcd_deinit(uint8_t rhport) {
+  (void) rhport;
+  return false;
+}
+
+TU_ATTR_WEAK void dcd_connect(uint8_t rhport) {
+  (void) rhport;
+}
+
+TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) {
+  (void) rhport;
+}
+
+TU_ATTR_WEAK bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
+  (void) addr; (void) data_size;
+  return true;
+}
+
+TU_ATTR_WEAK bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
+  (void) addr; (void) data_size;
+  return true;
+}
+
+TU_ATTR_WEAK bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
+  (void) addr; (void) data_size;
+  return true;
+}
+
 //--------------------------------------------------------------------+
 // Device Data
 //--------------------------------------------------------------------+
@@ -53,10 +119,8 @@
 // Invalid driver ID in itf2drv[] ep2drv[][] mapping
 enum { DRVID_INVALID = 0xFFu };
 
-typedef struct
-{
-  struct TU_ATTR_PACKED
-  {
+typedef struct {
+  struct TU_ATTR_PACKED {
     volatile uint8_t connected    : 1;
     volatile uint8_t addressed    : 1;
     volatile uint8_t suspended    : 1;
@@ -65,9 +129,9 @@ typedef struct
     uint8_t remote_wakeup_support : 1; // configuration descriptor's attribute
     uint8_t self_powered          : 1; // configuration descriptor's attribute
   };
-
   volatile uint8_t cfg_num; // current active configuration (0x00 is not configured)
   uint8_t speed;
+  volatile uint8_t sof_consumer;
 
   uint8_t itf2drv[CFG_TUD_INTERFACE_MAX];   // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ), can use only 4-bit each
@@ -76,208 +140,224 @@ typedef struct
 
 }usbd_device_t;
 
-static usbd_device_t _usbd_dev;
+tu_static usbd_device_t _usbd_dev;
+static volatile uint8_t _usbd_queued_setup;
 
 //--------------------------------------------------------------------+
 // Class Driver
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= 2
-  #define DRIVER_NAME(_name)    .name = _name,
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
+  #define DRIVER_NAME(_name)  _name
 #else
-  #define DRIVER_NAME(_name)
+  #define DRIVER_NAME(_name)  NULL
 #endif
 
 // Built-in class drivers
-static usbd_class_driver_t const _usbd_driver[] =
-{
-  #if CFG_TUD_CDC
-  {
-    DRIVER_NAME("CDC")
-    .init             = cdcd_init,
-    .reset            = cdcd_reset,
-    .open             = cdcd_open,
-    .control_xfer_cb  = cdcd_control_xfer_cb,
-    .xfer_cb          = cdcd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
+tu_static usbd_class_driver_t const _usbd_driver[] = {
+    #if CFG_TUD_CDC
+    {
+        .name             = DRIVER_NAME("CDC"),
+        .init             = cdcd_init,
+        .deinit           = cdcd_deinit,
+        .reset            = cdcd_reset,
+        .open             = cdcd_open,
+        .control_xfer_cb  = cdcd_control_xfer_cb,
+        .xfer_cb          = cdcd_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
 
-  #if CFG_TUD_MSC
-  {
-    DRIVER_NAME("MSC")
-    .init             = mscd_init,
-    .reset            = mscd_reset,
-    .open             = mscd_open,
-    .control_xfer_cb  = mscd_control_xfer_cb,
-    .xfer_cb          = mscd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
+    #if CFG_TUD_MSC
+    {
+        .name             = DRIVER_NAME("MSC"),
+        .init             = mscd_init,
+        .deinit           = NULL,
+        .reset            = mscd_reset,
+        .open             = mscd_open,
+        .control_xfer_cb  = mscd_control_xfer_cb,
+        .xfer_cb          = mscd_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
 
-  #if CFG_TUD_HID
-  {
-    DRIVER_NAME("HID")
-    .init             = hidd_init,
-    .reset            = hidd_reset,
-    .open             = hidd_open,
-    .control_xfer_cb  = hidd_control_xfer_cb,
-    .xfer_cb          = hidd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
+    #if CFG_TUD_HID
+    {
+        .name             = DRIVER_NAME("HID"),
+        .init             = hidd_init,
+        .deinit           = hidd_deinit,
+        .reset            = hidd_reset,
+        .open             = hidd_open,
+        .control_xfer_cb  = hidd_control_xfer_cb,
+        .xfer_cb          = hidd_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
 
-  #if CFG_TUD_AUDIO
-  {
-    DRIVER_NAME("AUDIO")
-    .init             = audiod_init,
-    .reset            = audiod_reset,
-    .open             = audiod_open,
-    .control_xfer_cb  = audiod_control_xfer_cb,
-    .xfer_cb          = audiod_xfer_cb,
-    .sof              = audiod_sof_isr
-  },
-  #endif
+    #if CFG_TUD_AUDIO
+    {
+        .name             = DRIVER_NAME("AUDIO"),
+        .init             = audiod_init,
+        .deinit           = audiod_deinit,
+        .reset            = audiod_reset,
+        .open             = audiod_open,
+        .control_xfer_cb  = audiod_control_xfer_cb,
+        .xfer_cb          = audiod_xfer_cb,
+        .sof              = audiod_sof_isr
+    },
+    #endif
 
-  #if CFG_TUD_VIDEO
-  {
-    DRIVER_NAME("VIDEO")
-    .init             = videod_init,
-    .reset            = videod_reset,
-    .open             = videod_open,
-    .control_xfer_cb  = videod_control_xfer_cb,
-    .xfer_cb          = videod_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
+    #if CFG_TUD_VIDEO
+    {
+        .name             = DRIVER_NAME("VIDEO"),
+        .init             = videod_init,
+        .deinit           = videod_deinit,
+        .reset            = videod_reset,
+        .open             = videod_open,
+        .control_xfer_cb  = videod_control_xfer_cb,
+        .xfer_cb          = videod_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
 
-  #if CFG_TUD_MIDI
-  {
-    DRIVER_NAME("MIDI")
-    .init             = midid_init,
-    .open             = midid_open,
-    .reset            = midid_reset,
-    .control_xfer_cb  = midid_control_xfer_cb,
-    .xfer_cb          = midid_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
+    #if CFG_TUD_MIDI
+    {
+        .name             = DRIVER_NAME("MIDI"),
+        .init             = midid_init,
+        .deinit           = midid_deinit,
+        .open             = midid_open,
+        .reset            = midid_reset,
+        .control_xfer_cb  = midid_control_xfer_cb,
+        .xfer_cb          = midid_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
 
-  #if CFG_TUD_VENDOR
-  {
-    DRIVER_NAME("VENDOR")
-    .init             = vendord_init,
-    .reset            = vendord_reset,
-    .open             = vendord_open,
-    .control_xfer_cb  = tud_vendor_control_xfer_cb,
-    .xfer_cb          = vendord_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
+    #if CFG_TUD_VENDOR
+    {
+        .name             = DRIVER_NAME("VENDOR"),
+        .init             = vendord_init,
+        .deinit           = vendord_deinit,
+        .reset            = vendord_reset,
+        .open             = vendord_open,
+        .control_xfer_cb  = tud_vendor_control_xfer_cb,
+        .xfer_cb          = vendord_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
 
-  #if CFG_TUD_USBTMC
-  {
-    DRIVER_NAME("TMC")
-    .init             = usbtmcd_init_cb,
-    .reset            = usbtmcd_reset_cb,
-    .open             = usbtmcd_open_cb,
-    .control_xfer_cb  = usbtmcd_control_xfer_cb,
-    .xfer_cb          = usbtmcd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
+    #if CFG_TUD_USBTMC
+    {
+        .name             = DRIVER_NAME("TMC"),
+        .init             = usbtmcd_init_cb,
+        .deinit           = usbtmcd_deinit,
+        .reset            = usbtmcd_reset_cb,
+        .open             = usbtmcd_open_cb,
+        .control_xfer_cb  = usbtmcd_control_xfer_cb,
+        .xfer_cb          = usbtmcd_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
 
-  #if CFG_TUD_DFU_RUNTIME
-  {
-    DRIVER_NAME("DFU-RUNTIME")
-    .init             = dfu_rtd_init,
-    .reset            = dfu_rtd_reset,
-    .open             = dfu_rtd_open,
-    .control_xfer_cb  = dfu_rtd_control_xfer_cb,
-    .xfer_cb          = NULL,
-    .sof              = NULL
-  },
-  #endif
+    #if CFG_TUD_DFU_RUNTIME
+    {
+        .name             = DRIVER_NAME("DFU-RUNTIME"),
+        .init             = dfu_rtd_init,
+        .deinit           = dfu_rtd_deinit,
+        .reset            = dfu_rtd_reset,
+        .open             = dfu_rtd_open,
+        .control_xfer_cb  = dfu_rtd_control_xfer_cb,
+        .xfer_cb          = NULL,
+        .sof              = NULL
+    },
+    #endif
 
-  #if CFG_TUD_DFU
-  {
-    DRIVER_NAME("DFU")
-    .init             = dfu_moded_init,
-    .reset            = dfu_moded_reset,
-    .open             = dfu_moded_open,
-    .control_xfer_cb  = dfu_moded_control_xfer_cb,
-    .xfer_cb          = NULL,
-    .sof              = NULL
-  },
-  #endif
+    #if CFG_TUD_DFU
+    {
+        .name             = DRIVER_NAME("DFU"),
+        .init             = dfu_moded_init,
+        .deinit           = dfu_moded_deinit,
+        .reset            = dfu_moded_reset,
+        .open             = dfu_moded_open,
+        .control_xfer_cb  = dfu_moded_control_xfer_cb,
+        .xfer_cb          = NULL,
+        .sof              = NULL
+    },
+    #endif
 
-  #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
-  {
-    DRIVER_NAME("NET")
-    .init             = netd_init,
-    .reset            = netd_reset,
-    .open             = netd_open,
-    .control_xfer_cb  = netd_control_xfer_cb,
-    .xfer_cb          = netd_xfer_cb,
-    .sof                  = NULL,
-  },
-  #endif
+    #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
+    {
+        .name             = DRIVER_NAME("NET"),
+        .init             = netd_init,
+        .deinit           = netd_deinit,
+        .reset            = netd_reset,
+        .open             = netd_open,
+        .control_xfer_cb  = netd_control_xfer_cb,
+        .xfer_cb          = netd_xfer_cb,
+        .sof                  = NULL,
+    },
+    #endif
 
-  #if CFG_TUD_BTH
-  {
-    DRIVER_NAME("BTH")
-    .init             = btd_init,
-    .reset            = btd_reset,
-    .open             = btd_open,
-    .control_xfer_cb  = btd_control_xfer_cb,
-    .xfer_cb          = btd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
+    #if CFG_TUD_BTH
+    {
+        .name             = DRIVER_NAME("BTH"),
+        .init             = btd_init,
+        .deinit           = btd_deinit,
+        .reset            = btd_reset,
+        .open             = btd_open,
+        .control_xfer_cb  = btd_control_xfer_cb,
+        .xfer_cb          = btd_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
 };
 
 enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
 
 // Additional class drivers implemented by application
-static usbd_class_driver_t const * _app_driver = NULL;
-static uint8_t _app_driver_count = 0;
+tu_static usbd_class_driver_t const * _app_driver = NULL;
+tu_static uint8_t _app_driver_count = 0;
+
+#define TOTAL_DRIVER_COUNT    (_app_driver_count + BUILTIN_DRIVER_COUNT)
 
 // virtually joins built-in and application drivers together.
 // Application is positioned first to allow overwriting built-in ones.
-static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
-{
-  // Application drivers
-  if ( usbd_app_driver_get_cb )
-  {
-    if ( drvid < _app_driver_count ) return &_app_driver[drvid];
-    drvid -= _app_driver_count;
+TU_ATTR_ALWAYS_INLINE static inline usbd_class_driver_t const * get_driver(uint8_t drvid) {
+  usbd_class_driver_t const * driver = NULL;
+  if ( drvid < _app_driver_count ) {
+    // Application drivers
+    driver = &_app_driver[drvid];
+  } else if ( drvid < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0 ){
+    driver = &_usbd_driver[drvid - _app_driver_count];
   }
-
-  // Built-in drivers
-  if (drvid < BUILTIN_DRIVER_COUNT) return &_usbd_driver[drvid];
-
-  return NULL;
+  return driver;
 }
 
-#define TOTAL_DRIVER_COUNT    (_app_driver_count + BUILTIN_DRIVER_COUNT)
 
 //--------------------------------------------------------------------+
 // DCD Event
 //--------------------------------------------------------------------+
 
 enum { RHPORT_INVALID = 0xFFu };
-static uint8_t _usbd_rhport = RHPORT_INVALID;
+tu_static uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
 OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
-static osal_queue_t _usbd_q;
+tu_static osal_queue_t _usbd_q;
 
-// Mutex for claiming endpoint, only needed when using with preempted RTOS
-#if CFG_TUSB_OS != OPT_OS_NONE
-static osal_mutex_def_t _ubsd_mutexdef;
-static osal_mutex_t _usbd_mutex;
+// Mutex for claiming endpoint
+#if OSAL_MUTEX_REQUIRED
+  tu_static osal_mutex_def_t _ubsd_mutexdef;
+  tu_static osal_mutex_t _usbd_mutex;
+#else
+  #define _usbd_mutex   NULL
 #endif
 
+TU_ATTR_ALWAYS_INLINE static inline bool queue_event(dcd_event_t const * event, bool in_isr) {
+  TU_ASSERT(osal_queue_send(_usbd_q, event, in_isr));
+  tud_event_hook_cb(event->rhport, event->event_id, in_isr);
+  return true;
+}
 
 //--------------------------------------------------------------------+
 // Prototypes
@@ -286,6 +366,16 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
 static bool process_set_config(uint8_t rhport, uint8_t cfg_num);
 static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const * p_request);
 
+#if CFG_TUD_TEST_MODE
+static bool process_test_mode_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) {
+  TU_VERIFY(CONTROL_STAGE_ACK == stage);
+  uint8_t const selector = tu_u16_high(request->wIndex);
+  TU_LOG_USBD("    Enter Test Mode (test selector index: %d)\r\n", selector);
+  dcd_enter_test_mode(rhport, (tusb_feature_test_mode_t) selector);
+  return true;
+}
+#endif
+
 // from usbd_control.c
 void usbd_control_reset(void);
 void usbd_control_set_request(tusb_control_request_t const *request);
@@ -296,29 +386,25 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event,
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= 2
-static char const* const _usbd_event_str[DCD_EVENT_COUNT] =
-{
-  "Invalid"        ,
-  "Bus Reset"      ,
-  "Unplugged"      ,
-  "SOF"            ,
-  "Suspend"        ,
-  "Resume"         ,
-  "Setup Received" ,
-  "Xfer Complete"  ,
-  "Func Call"
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
+tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] = {
+    "Invalid",
+    "Bus Reset",
+    "Unplugged",
+    "SOF",
+    "Suspend",
+    "Resume",
+    "Setup Received",
+    "Xfer Complete",
+    "Func Call"
 };
 
 // for usbd_control to print the name of control complete driver
-void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
-{
-  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
-  {
-    usbd_class_driver_t const * driver = get_driver(i);
-    if ( driver && driver->control_xfer_cb == callback )
-    {
-      TU_LOG(USBD_DBG, "  %s control complete\r\n", driver->name);
+void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) {
+  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+    usbd_class_driver_t const* driver = get_driver(i);
+    if (driver && driver->control_xfer_cb == callback) {
+      TU_LOG_USBD("%s control complete\r\n", driver->name);
       return;
     }
   }
@@ -329,67 +415,67 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
-tusb_speed_t tud_speed_get(void)
-{
+tusb_speed_t tud_speed_get(void) {
   return (tusb_speed_t) _usbd_dev.speed;
 }
 
-bool tud_connected(void)
-{
+bool tud_connected(void) {
   return _usbd_dev.connected;
 }
 
-bool tud_mounted(void)
-{
+bool tud_mounted(void) {
   return _usbd_dev.cfg_num ? true : false;
 }
 
-bool tud_suspended(void)
-{
+bool tud_suspended(void) {
   return _usbd_dev.suspended;
 }
 
-bool tud_remote_wakeup(void)
-{
+bool tud_remote_wakeup(void) {
   // only wake up host if this feature is supported and enabled and we are suspended
-  TU_VERIFY (_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en );
+  TU_VERIFY (_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en);
   dcd_remote_wakeup(_usbd_rhport);
   return true;
 }
 
-bool tud_disconnect(void)
-{
-  TU_VERIFY(dcd_disconnect);
+bool tud_disconnect(void) {
   dcd_disconnect(_usbd_rhport);
   return true;
 }
 
-bool tud_connect(void)
-{
-  TU_VERIFY(dcd_connect);
+bool tud_connect(void) {
   dcd_connect(_usbd_rhport);
   return true;
 }
 
+void tud_sof_cb_enable(bool en) {
+  usbd_sof_enable(_usbd_rhport, SOF_CONSUMER_USER, en);
+}
+
 //--------------------------------------------------------------------+
 // USBD Task
 //--------------------------------------------------------------------+
-bool tud_inited(void)
-{
+bool tud_inited(void) {
   return _usbd_rhport != RHPORT_INVALID;
 }
 
-bool tud_init (uint8_t rhport)
-{
-  // skip if already initialized
-  if ( tud_inited() ) return true;
+bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  if (tud_inited()) {
+    return true; // skip if already initialized
+  }
+  TU_ASSERT(rh_init);
 
-  TU_LOG(USBD_DBG, "USBD init on controller %u\r\n", rhport);
-  TU_LOG_INT(USBD_DBG, sizeof(usbd_device_t));
+  TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rhport,
+    rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t));
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t));
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t));
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_edpt_stream_t));
 
   tu_varclr(&_usbd_dev);
+  _usbd_queued_setup = 0;
 
-#if CFG_TUSB_OS != OPT_OS_NONE
+#if OSAL_MUTEX_REQUIRED
   // Init device mutex
   _usbd_mutex = osal_mutex_create(&_ubsd_mutexdef);
   TU_ASSERT(_usbd_mutex);
@@ -400,54 +486,83 @@ bool tud_init (uint8_t rhport)
   TU_ASSERT(_usbd_q);
 
   // Get application driver if available
-  if ( usbd_app_driver_get_cb )
-  {
+  if (usbd_app_driver_get_cb) {
     _app_driver = usbd_app_driver_get_cb(&_app_driver_count);
   }
 
   // Init class drivers
-  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
-  {
-    usbd_class_driver_t const * driver = get_driver(i);
-    TU_ASSERT(driver);
-    TU_LOG(USBD_DBG, "%s init\r\n", driver->name);
+  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+    usbd_class_driver_t const* driver = get_driver(i);
+    TU_ASSERT(driver && driver->init);
+    TU_LOG_USBD("%s init\r\n", driver->name);
     driver->init();
   }
 
   _usbd_rhport = rhport;
 
   // Init device controller driver
-  dcd_init(rhport);
+  TU_ASSERT(dcd_init(rhport, rh_init));
   dcd_int_enable(rhport);
 
   return true;
 }
 
-static void configuration_reset(uint8_t rhport)
-{
-  for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
-  {
-    usbd_class_driver_t const * driver = get_driver(i);
-    TU_ASSERT(driver, );
+bool tud_deinit(uint8_t rhport) {
+  if (!tud_inited()) {
+    return true; // skip if not initialized
+  }
+
+  TU_LOG_USBD("USBD deinit on controller %u\r\n", rhport);
+
+  // Deinit device controller driver
+  dcd_int_disable(rhport);
+  dcd_disconnect(rhport);
+  dcd_deinit(rhport);
+
+  // Deinit class drivers
+  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+    usbd_class_driver_t const* driver = get_driver(i);
+    if(driver && driver->deinit) {
+      TU_LOG_USBD("%s deinit\r\n", driver->name);
+      driver->deinit();
+    }
+  }
+
+  // Deinit device queue & task
+  osal_queue_delete(_usbd_q);
+  _usbd_q = NULL;
+
+#if OSAL_MUTEX_REQUIRED
+  // TODO make sure there is no task waiting on this mutex
+  osal_mutex_delete(_usbd_mutex);
+  _usbd_mutex = NULL;
+#endif
+
+  _usbd_rhport = RHPORT_INVALID;
+
+  return true;
+}
+
+static void configuration_reset(uint8_t rhport) {
+  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+    usbd_class_driver_t const* driver = get_driver(i);
+    TU_ASSERT(driver,);
     driver->reset(rhport);
   }
 
   tu_varclr(&_usbd_dev);
   memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping
-  memset(_usbd_dev.ep2drv , DRVID_INVALID, sizeof(_usbd_dev.ep2drv )); // invalid mapping
+  memset(_usbd_dev.ep2drv, DRVID_INVALID, sizeof(_usbd_dev.ep2drv)); // invalid mapping
 }
 
-static void usbd_reset(uint8_t rhport)
-{
+static void usbd_reset(uint8_t rhport) {
   configuration_reset(rhport);
   usbd_control_reset();
 }
 
-bool tud_task_event_ready(void)
-{
+bool tud_task_event_ready(void) {
   // Skip if stack is not initialized
-  if ( !tusb_inited() ) return false;
-
+  if (!tud_inited()) return false;
   return !osal_queue_empty(_usbd_q);
 }
 
@@ -455,139 +570,133 @@ bool tud_task_event_ready(void)
  * This top level thread manages all device controller event and delegates events to class-specific drivers.
  * This should be called periodically within the mainloop or rtos thread.
  *
-   @code
-    int main(void)
-    {
+    int main(void) {
       application_init();
-      tusb_init();
+      tusb_init(0, TUSB_ROLE_DEVICE);
 
-      while(1) // the mainloop
-      {
+      while(1) { // the mainloop
         application_code();
         tud_task(); // tinyusb device task
       }
     }
-    @endcode
  */
-void tud_task_ext(uint32_t timeout_ms, bool in_isr)
-{
+void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
   (void) in_isr; // not implemented yet
 
   // Skip if stack is not initialized
-  if ( !tusb_inited() ) return;
+  if (!tud_inited()) return;
 
   // Loop until there is no more events in the queue
-  while (1)
-  {
+  while (1) {
     dcd_event_t event;
-    if ( !osal_queue_receive(_usbd_q, &event, timeout_ms) ) return;
+    if (!osal_queue_receive(_usbd_q, &event, timeout_ms)) return;
 
-#if CFG_TUSB_DEBUG >= 2
-    if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG(USBD_DBG, "\r\n"); // extra line for setup
-    TU_LOG(USBD_DBG, "USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
+    if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG_USBD("\r\n"); // extra line for setup
+    TU_LOG_USBD("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
 #endif
 
-    switch ( event.event_id )
-    {
+    switch (event.event_id) {
       case DCD_EVENT_BUS_RESET:
-        TU_LOG(USBD_DBG, ": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
+        TU_LOG_USBD(": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
         usbd_reset(event.rhport);
         _usbd_dev.speed = event.bus_reset.speed;
-      break;
+        break;
 
       case DCD_EVENT_UNPLUGGED:
-        TU_LOG(USBD_DBG, "\r\n");
+        TU_LOG_USBD("\r\n");
         usbd_reset(event.rhport);
-
-        // invoke callback
-        if (tud_umount_cb) tud_umount_cb();
-      break;
+        tud_umount_cb();
+        break;
 
       case DCD_EVENT_SETUP_RECEIVED:
-        TU_LOG_VAR(USBD_DBG, &event.setup_received);
-        TU_LOG(USBD_DBG, "\r\n");
+        TU_ASSERT(_usbd_queued_setup > 0,);
+        _usbd_queued_setup--;
+        TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
+        if (_usbd_queued_setup) {
+          TU_LOG_USBD("  Skipped since there is other SETUP in queue\r\n");
+          break;
+        }
 
         // Mark as connected after receiving 1st setup packet.
         // But it is easier to set it every time instead of wasting time to check then set
         _usbd_dev.connected = 1;
 
         // mark both in & out control as free
-        _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = false;
+        _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = 0;
         _usbd_dev.ep_status[0][TUSB_DIR_OUT].claimed = 0;
-        _usbd_dev.ep_status[0][TUSB_DIR_IN ].busy = false;
-        _usbd_dev.ep_status[0][TUSB_DIR_IN ].claimed = 0;
+        _usbd_dev.ep_status[0][TUSB_DIR_IN].busy = 0;
+        _usbd_dev.ep_status[0][TUSB_DIR_IN].claimed = 0;
 
         // Process control request
-        if ( !process_control_request(event.rhport, &event.setup_received) )
-        {
-          TU_LOG(USBD_DBG, "  Stall EP0\r\n");
+        if (!process_control_request(event.rhport, &event.setup_received)) {
+          TU_LOG_USBD("  Stall EP0\r\n");
           // Failed -> stall both control endpoint IN and OUT
           dcd_edpt_stall(event.rhport, 0);
           dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK);
         }
-      break;
+        break;
 
-      case DCD_EVENT_XFER_COMPLETE:
-      {
+      case DCD_EVENT_XFER_COMPLETE: {
         // Invoke the class callback associated with the endpoint address
         uint8_t const ep_addr = event.xfer_complete.ep_addr;
-        uint8_t const epnum   = tu_edpt_number(ep_addr);
-        uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
+        uint8_t const epnum = tu_edpt_number(ep_addr);
+        uint8_t const ep_dir = tu_edpt_dir(ep_addr);
 
-        TU_LOG(USBD_DBG, "on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+        TU_LOG_USBD("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
 
-        _usbd_dev.ep_status[epnum][ep_dir].busy = false;
+        _usbd_dev.ep_status[epnum][ep_dir].busy = 0;
         _usbd_dev.ep_status[epnum][ep_dir].claimed = 0;
 
-        if ( 0 == epnum )
-        {
-          usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len);
-        }
-        else
-        {
-          usbd_class_driver_t const * driver = get_driver( _usbd_dev.ep2drv[epnum][ep_dir] );
-          TU_ASSERT(driver, );
+        if (0 == epnum) {
+          usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result,
+                               event.xfer_complete.len);
+        } else {
+          usbd_class_driver_t const* driver = get_driver(_usbd_dev.ep2drv[epnum][ep_dir]);
+          TU_ASSERT(driver,);
 
-          TU_LOG(USBD_DBG, "  %s xfer callback\r\n", driver->name);
-          driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len);
+          TU_LOG_USBD("  %s xfer callback\r\n", driver->name);
+          driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
         }
+        break;
       }
-      break;
 
       case DCD_EVENT_SUSPEND:
         // NOTE: When plugging/unplugging device, the D+/D- state are unstable and
         // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ), which result in a series of event
         // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected
-        if ( _usbd_dev.connected )
-        {
-          TU_LOG(USBD_DBG, ": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
-          if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
-        }else
-        {
-          TU_LOG(USBD_DBG, " Skipped\r\n");
+        if (_usbd_dev.connected) {
+          TU_LOG_USBD(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
+          tud_suspend_cb(_usbd_dev.remote_wakeup_en);
+        } else {
+          TU_LOG_USBD(" Skipped\r\n");
         }
-      break;
+        break;
 
       case DCD_EVENT_RESUME:
-        if ( _usbd_dev.connected )
-        {
-          TU_LOG(USBD_DBG, "\r\n");
-          if (tud_resume_cb) tud_resume_cb();
-        }else
-        {
-          TU_LOG(USBD_DBG, " Skipped\r\n");
+        if (_usbd_dev.connected) {
+          TU_LOG_USBD("\r\n");
+          tud_resume_cb();
+        } else {
+          TU_LOG_USBD(" Skipped\r\n");
+        }
+        break;
+
+      case USBD_EVENT_FUNC_CALL:
+        TU_LOG_USBD("\r\n");
+        if (event.func_call.func) event.func_call.func(event.func_call.param);
+        break;
+
+      case DCD_EVENT_SOF:
+        if (tu_bit_test(_usbd_dev.sof_consumer, SOF_CONSUMER_USER)) {
+          TU_LOG_USBD("\r\n");
+          tud_sof_cb(event.sof.frame_count);
         }
       break;
 
-      case USBD_EVENT_FUNC_CALL:
-        TU_LOG(USBD_DBG, "\r\n");
-        if ( event.func_call.func ) event.func_call.func(event.func_call.param);
-      break;
-
-      case DCD_EVENT_SOF:
       default:
         TU_BREAKPOINT();
-      break;
+        break;
     }
 
 #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
@@ -602,44 +711,35 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
 //--------------------------------------------------------------------+
 
 // Helper to invoke class driver control request handler
-static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request)
-{
+static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request) {
   usbd_control_set_complete_callback(driver->control_xfer_cb);
-  TU_LOG(USBD_DBG, "  %s control request\r\n", driver->name);
+  TU_LOG_USBD("  %s control request\r\n", driver->name);
   return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request);
 }
 
 // This handles the actual request and its response.
-// return false will cause its caller to stall control endpoint
-static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request)
-{
+// Returns false if unable to complete the request, causing caller to stall control endpoints.
+static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request) {
   usbd_control_set_complete_callback(NULL);
-
   TU_ASSERT(p_request->bmRequestType_bit.type < TUSB_REQ_TYPE_INVALID);
 
   // Vendor request
-  if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR )
-  {
-    TU_VERIFY(tud_vendor_control_xfer_cb);
-
+  if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR ) {
     usbd_control_set_complete_callback(tud_vendor_control_xfer_cb);
     return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request);
   }
 
-#if CFG_TUSB_DEBUG >= 2
-  if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME)
-  {
-    TU_LOG(USBD_DBG, "  %s", tu_str_std_request[p_request->bRequest]);
-    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG(USBD_DBG, "\r\n");
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
+  if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME) {
+    TU_LOG_USBD("  %s", tu_str_std_request[p_request->bRequest]);
+    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG_USBD("\r\n");
   }
 #endif
 
-  switch ( p_request->bmRequestType_bit.recipient )
-  {
+  switch ( p_request->bmRequestType_bit.recipient ) {
     //------------- Device Requests e.g in enumeration -------------//
     case TUSB_REQ_RCPT_DEVICE:
-      if ( TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type )
-      {
+      if ( TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type ) {
         uint8_t const itf = tu_u16_low(p_request->wIndex);
         TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv));
 
@@ -650,15 +750,13 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
         return invoke_class_control(rhport, driver, p_request);
       }
 
-      if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type )
-      {
-        // Non standard request is not supported
+      if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type ) {
+        // Non-standard request is not supported
         TU_BREAKPOINT();
         return false;
       }
 
-      switch ( p_request->bRequest )
-      {
+      switch ( p_request->bRequest ) {
         case TUSB_REQ_SET_ADDRESS:
           // Depending on mcu, status phase could be sent either before or after changing device address,
           // or even require stack to not response with status at all
@@ -669,24 +767,23 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           _usbd_dev.addressed = 1;
         break;
 
-        case TUSB_REQ_GET_CONFIGURATION:
-        {
+        case TUSB_REQ_GET_CONFIGURATION: {
           uint8_t cfg_num = _usbd_dev.cfg_num;
           tud_control_xfer(rhport, p_request, &cfg_num, 1);
         }
         break;
 
-        case TUSB_REQ_SET_CONFIGURATION:
-        {
+        case TUSB_REQ_SET_CONFIGURATION: {
           uint8_t const cfg_num = (uint8_t) p_request->wValue;
 
           // Only process if new configure is different
-          if (_usbd_dev.cfg_num != cfg_num)
-          {
-            if ( _usbd_dev.cfg_num )
-            {
+          if (_usbd_dev.cfg_num != cfg_num) {
+            if ( _usbd_dev.cfg_num ) {
               // already configured: need to clear all endpoints and driver first
-              TU_LOG(USBD_DBG, "  Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
+              TU_LOG_USBD("  Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
+
+              // disable SOF
+              dcd_sof_enable(rhport, false);
 
               // close all non-control endpoints, cancel all pending transfers if any
               dcd_edpt_close_all(rhport);
@@ -698,11 +795,23 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
               _usbd_dev.speed = speed; // restore speed
             }
 
-            // switch to new configuration if not zero
-            if ( cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) );
+            _usbd_dev.cfg_num = cfg_num;
+
+            // Handle the new configuration and execute the corresponding callback
+            if ( cfg_num ) {
+              // switch to new configuration if not zero
+              if (!process_set_config(rhport, cfg_num)) {
+                TU_MESS_FAILED();
+                TU_BREAKPOINT();
+                _usbd_dev.cfg_num = 0;
+                return false;
+              }
+              tud_mount_cb();
+            } else {
+              tud_umount_cb();
+            }
           }
 
-          _usbd_dev.cfg_num = cfg_num;
           tud_control_status(rhport, p_request);
         }
         break;
@@ -712,36 +821,52 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
         break;
 
         case TUSB_REQ_SET_FEATURE:
-          // Only support remote wakeup for device feature
-          TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
+          switch(p_request->wValue) {
+            case TUSB_REQ_FEATURE_REMOTE_WAKEUP:
+              TU_LOG_USBD("    Enable Remote Wakeup\r\n");
+              // Host may enable remote wake up before suspending especially HID device
+              _usbd_dev.remote_wakeup_en = true;
+              tud_control_status(rhport, p_request);
+            break;
 
-          TU_LOG(USBD_DBG, "    Enable Remote Wakeup\r\n");
+            #if CFG_TUD_TEST_MODE
+            case TUSB_REQ_FEATURE_TEST_MODE: {
+              // Only handle the test mode if supported and valid
+              TU_VERIFY(0 == tu_u16_low(p_request->wIndex));
 
-          // Host may enable remote wake up before suspending especially HID device
-          _usbd_dev.remote_wakeup_en = true;
-          tud_control_status(rhport, p_request);
+              uint8_t const selector = tu_u16_high(p_request->wIndex);
+              TU_VERIFY(TUSB_FEATURE_TEST_J <= selector && selector <= TUSB_FEATURE_TEST_FORCE_ENABLE);
+
+              usbd_control_set_complete_callback(process_test_mode_cb);
+              tud_control_status(rhport, p_request);
+              break;
+            }
+            #endif /* CFG_TUD_TEST_MODE */
+
+            // Stall unsupported feature selector
+            default: return false;
+          }
         break;
 
         case TUSB_REQ_CLEAR_FEATURE:
           // Only support remote wakeup for device feature
           TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
 
-          TU_LOG(USBD_DBG, "    Disable Remote Wakeup\r\n");
+          TU_LOG_USBD("    Disable Remote Wakeup\r\n");
 
           // Host may disable remote wake up after resuming
           _usbd_dev.remote_wakeup_en = false;
           tud_control_status(rhport, p_request);
         break;
 
-        case TUSB_REQ_GET_STATUS:
-        {
+        case TUSB_REQ_GET_STATUS: {
           // Device status bit mask
           // - Bit 0: Self Powered
           // - Bit 1: Remote Wakeup enabled
           uint16_t status = (uint16_t) ((_usbd_dev.self_powered ? 1u : 0u) | (_usbd_dev.remote_wakeup_en ? 2u : 0u));
           tud_control_xfer(rhport, p_request, &status, 2);
+          break;
         }
-        break;
 
         // Unknown/Unsupported request
         default: TU_BREAKPOINT(); return false;
@@ -749,8 +874,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
     break;
 
     //------------- Class/Interface Specific Request -------------//
-    case TUSB_REQ_RCPT_INTERFACE:
-    {
+    case TUSB_REQ_RCPT_INTERFACE: {
       uint8_t const itf = tu_u16_low(p_request->wIndex);
       TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv));
 
@@ -759,25 +883,21 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
 
       // all requests to Interface (STD or Class) is forwarded to class driver.
       // notable requests are: GET HID REPORT DESCRIPTOR, SET_INTERFACE, GET_INTERFACE
-      if ( !invoke_class_control(rhport, driver, p_request) )
-      {
+      if ( !invoke_class_control(rhport, driver, p_request) ) {
         // For GET_INTERFACE and SET_INTERFACE, it is mandatory to respond even if the class
         // driver doesn't use alternate settings or implement this
         TU_VERIFY(TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type);
 
-        switch(p_request->bRequest)
-        {
+        switch(p_request->bRequest) {
           case TUSB_REQ_GET_INTERFACE:
           case TUSB_REQ_SET_INTERFACE:
             // Clear complete callback if driver set since it can also stall the request.
             usbd_control_set_complete_callback(NULL);
 
-            if (TUSB_REQ_GET_INTERFACE == p_request->bRequest)
-            {
+            if (TUSB_REQ_GET_INTERFACE == p_request->bRequest) {
               uint8_t alternate = 0;
               tud_control_xfer(rhport, p_request, &alternate, 1);
-            }else
-            {
+            }else {
               tud_control_status(rhport, p_request);
             }
           break;
@@ -785,54 +905,42 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           default: return false;
         }
       }
+      break;
     }
-    break;
 
     //------------- Endpoint Request -------------//
-    case TUSB_REQ_RCPT_ENDPOINT:
-    {
+    case TUSB_REQ_RCPT_ENDPOINT: {
       uint8_t const ep_addr = tu_u16_low(p_request->wIndex);
       uint8_t const ep_num  = tu_edpt_number(ep_addr);
       uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
       TU_ASSERT(ep_num < TU_ARRAY_SIZE(_usbd_dev.ep2drv) );
-
       usbd_class_driver_t const * driver = get_driver(_usbd_dev.ep2drv[ep_num][ep_dir]);
 
-      if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type )
-      {
+      if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type ) {
         // Forward class request to its driver
         TU_VERIFY(driver);
         return invoke_class_control(rhport, driver, p_request);
-      }
-      else
-      {
+      } else {
         // Handle STD request to endpoint
-        switch ( p_request->bRequest )
-        {
-          case TUSB_REQ_GET_STATUS:
-          {
+        switch ( p_request->bRequest ) {
+          case TUSB_REQ_GET_STATUS: {
             uint16_t status = usbd_edpt_stalled(rhport, ep_addr) ? 0x0001 : 0x0000;
             tud_control_xfer(rhport, p_request, &status, 2);
           }
           break;
 
           case TUSB_REQ_CLEAR_FEATURE:
-          case TUSB_REQ_SET_FEATURE:
-          {
-            if ( TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue )
-            {
-              if ( TUSB_REQ_CLEAR_FEATURE ==  p_request->bRequest )
-              {
+          case TUSB_REQ_SET_FEATURE: {
+            if ( TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue ) {
+              if ( TUSB_REQ_CLEAR_FEATURE ==  p_request->bRequest ) {
                 usbd_edpt_clear_stall(rhport, ep_addr);
-              }else
-              {
+              }else {
                 usbd_edpt_stall(rhport, ep_addr);
               }
             }
 
-            if (driver)
-            {
+            if (driver) {
               // Some classes such as USBTMC needs to clear/re-init its buffer when receiving CLEAR_FEATURE request
               // We will also forward std request targeted endpoint to class drivers as well
 
@@ -848,14 +956,18 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           break;
 
           // Unknown/Unsupported request
-          default: TU_BREAKPOINT(); return false;
+          default:
+            TU_BREAKPOINT();
+            return false;
         }
       }
     }
     break;
 
     // Unknown recipient
-    default: TU_BREAKPOINT(); return false;
+    default:
+      TU_BREAKPOINT();
+      return false;
   }
 
   return true;
@@ -909,7 +1021,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
       if ( (sizeof(tusb_desc_interface_t) <= drv_len)  && (drv_len <= remaining_len) )
       {
         // Open successfully
-        TU_LOG(USBD_DBG, "  %s opened\r\n", driver->name);
+        TU_LOG_USBD("  %s opened\r\n", driver->name);
 
         // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or
         // BTH (even CDC) with class in device descriptor (single interface)
@@ -960,9 +1072,6 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
     TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT);
   }
 
-  // invoke callback
-  if (tud_mount_cb) tud_mount_cb();
-
   return true;
 }
 
@@ -974,39 +1083,34 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
   switch(desc_type)
   {
-    case TUSB_DESC_DEVICE:
-    {
-      TU_LOG(USBD_DBG, " Device\r\n");
+    case TUSB_DESC_DEVICE: {
+      TU_LOG_USBD(" Device\r\n");
 
       void* desc_device = (void*) (uintptr_t) tud_descriptor_device_cb();
+      TU_ASSERT(desc_device);
 
       // Only response with exactly 1 Packet if: not addressed and host requested more data than device descriptor has.
       // This only happens with the very first get device descriptor and EP0 size = 8 or 16.
       if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed &&
-          ((tusb_control_request_t const*) p_request)->wLength > sizeof(tusb_desc_device_t))
-      {
+          ((tusb_control_request_t const*) p_request)->wLength > sizeof(tusb_desc_device_t)) {
         // Hack here: we modify the request length to prevent usbd_control response with zlp
         // since we are responding with 1 packet & less data than wLength.
         tusb_control_request_t mod_request = *p_request;
         mod_request.wLength = CFG_TUD_ENDPOINT0_SIZE;
 
         return tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE);
-      }else
-      {
+      }else {
         return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t));
       }
     }
     // break; // unreachable
 
-    case TUSB_DESC_BOS:
-    {
-      TU_LOG(USBD_DBG, " BOS\r\n");
+    case TUSB_DESC_BOS: {
+      TU_LOG_USBD(" BOS\r\n");
 
       // requested by host if USB > 2.0 ( i.e 2.1 or 3.x )
-      if (!tud_descriptor_bos_cb) return false;
-
       uintptr_t desc_bos = (uintptr_t) tud_descriptor_bos_cb();
-      TU_ASSERT(desc_bos);
+      TU_VERIFY(desc_bos);
 
       // Use offsetof to avoid pointer to the odd/misaligned address
       uint16_t const total_len = tu_le16toh( tu_unaligned_read16((const void*) (desc_bos + offsetof(tusb_desc_bos_t, wTotalLength))) );
@@ -1016,24 +1120,20 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
     // break; // unreachable
 
     case TUSB_DESC_CONFIGURATION:
-    case TUSB_DESC_OTHER_SPEED_CONFIG:
-    {
+    case TUSB_DESC_OTHER_SPEED_CONFIG: {
       uintptr_t desc_config;
 
-      if ( desc_type == TUSB_DESC_CONFIGURATION )
-      {
-        TU_LOG(USBD_DBG, " Configuration[%u]\r\n", desc_index);
+      if ( desc_type == TUSB_DESC_CONFIGURATION ) {
+        TU_LOG_USBD(" Configuration[%u]\r\n", desc_index);
         desc_config = (uintptr_t) tud_descriptor_configuration_cb(desc_index);
-      }else
-      {
+        TU_ASSERT(desc_config);
+      }else {
         // Host only request this after getting Device Qualifier descriptor
-        TU_LOG(USBD_DBG, " Other Speed Configuration\r\n");
-        TU_VERIFY( tud_descriptor_other_speed_configuration_cb );
+        TU_LOG_USBD(" Other Speed Configuration\r\n");
         desc_config = (uintptr_t) tud_descriptor_other_speed_configuration_cb(desc_index);
+        TU_VERIFY(desc_config);
       }
 
-      TU_ASSERT(desc_config);
-
       // Use offsetof to avoid pointer to the odd/misaligned address
       uint16_t const total_len = tu_le16toh( tu_unaligned_read16((const void*) (desc_config + offsetof(tusb_desc_configuration_t, wTotalLength))) );
 
@@ -1043,7 +1143,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_STRING:
     {
-      TU_LOG(USBD_DBG, " String[%u]\r\n", desc_index);
+      TU_LOG_USBD(" String[%u]\r\n", desc_index);
 
       // String Descriptor always uses the desc set from user
       uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, tu_le16toh(p_request->wIndex));
@@ -1054,16 +1154,10 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
     }
     // break; // unreachable
 
-    case TUSB_DESC_DEVICE_QUALIFIER:
-    {
-      TU_LOG(USBD_DBG, " Device Qualifier\r\n");
-
-      TU_VERIFY( tud_descriptor_device_qualifier_cb );
-
+    case TUSB_DESC_DEVICE_QUALIFIER: {
+      TU_LOG_USBD(" Device Qualifier\r\n");
       uint8_t const* desc_qualifier = tud_descriptor_device_qualifier_cb();
       TU_VERIFY(desc_qualifier);
-
-      // first byte of descriptor is its size
       return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_qualifier, tu_desc_len(desc_qualifier));
     }
     // break; // unreachable
@@ -1075,66 +1169,72 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 //--------------------------------------------------------------------+
 // DCD Event Handler
 //--------------------------------------------------------------------+
-TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
-{
-  switch (event->event_id)
-  {
+TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr) {
+  bool send = false;
+  switch (event->event_id) {
     case DCD_EVENT_UNPLUGGED:
-      _usbd_dev.connected  = 0;
-      _usbd_dev.addressed  = 0;
-      _usbd_dev.cfg_num    = 0;
-      _usbd_dev.suspended  = 0;
-      osal_queue_send(_usbd_q, event, in_isr);
-    break;
+      _usbd_dev.connected = 0;
+      _usbd_dev.addressed = 0;
+      _usbd_dev.cfg_num = 0;
+      _usbd_dev.suspended = 0;
+      send = true;
+      break;
 
     case DCD_EVENT_SUSPEND:
       // NOTE: When plugging/unplugging device, the D+/D- state are unstable and
       // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ).
       // In addition, some MCUs such as SAMD or boards that haven no VBUS detection cannot distinguish
       // suspended vs disconnected. We will skip handling SUSPEND/RESUME event if not currently connected
-      if ( _usbd_dev.connected )
-      {
+      if (_usbd_dev.connected) {
         _usbd_dev.suspended = 1;
-        osal_queue_send(_usbd_q, event, in_isr);
+        send = true;
       }
-    break;
+      break;
 
     case DCD_EVENT_RESUME:
       // skip event if not connected (especially required for SAMD)
-      if ( _usbd_dev.connected )
-      {
+      if (_usbd_dev.connected) {
         _usbd_dev.suspended = 0;
-        osal_queue_send(_usbd_q, event, in_isr);
+        send = true;
       }
-    break;
+      break;
 
     case DCD_EVENT_SOF:
       // SOF driver handler in ISR context
-      for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
-      {
-        usbd_class_driver_t const * driver = get_driver(i);
-        if (driver && driver->sof)
-        {
+      for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+        usbd_class_driver_t const* driver = get_driver(i);
+        if (driver && driver->sof) {
           driver->sof(event->rhport, event->sof.frame_count);
         }
       }
 
       // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup
       // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational
-      if ( _usbd_dev.suspended )
-      {
+      if (_usbd_dev.suspended) {
         _usbd_dev.suspended = 0;
 
-        dcd_event_t const event_resume = { .rhport = event->rhport, .event_id = DCD_EVENT_RESUME };
-        osal_queue_send(_usbd_q, &event_resume, in_isr);
+        dcd_event_t const event_resume = {.rhport = event->rhport, .event_id = DCD_EVENT_RESUME};
+        queue_event(&event_resume, in_isr);
       }
 
-      // skip osal queue for SOF in usbd task
-    break;
+      if (tu_bit_test(_usbd_dev.sof_consumer, SOF_CONSUMER_USER)) {
+        dcd_event_t const event_sof = {.rhport = event->rhport, .event_id = DCD_EVENT_SOF, .sof.frame_count = event->sof.frame_count};
+        queue_event(&event_sof, in_isr);
+      }
+      break;
+
+    case DCD_EVENT_SETUP_RECEIVED:
+      _usbd_queued_setup++;
+      send = true;
+      break;
 
     default:
-      osal_queue_send(_usbd_q, event, in_isr);
-    break;
+      send = true;
+      break;
+  }
+
+  if (send) {
+    queue_event(event, in_isr);
   }
 }
 
@@ -1178,26 +1278,22 @@ bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count
 }
 
 // Helper to defer an isr function
-void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr)
-{
-  dcd_event_t event =
-  {
+void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr) {
+  dcd_event_t event = {
       .rhport   = 0,
       .event_id = USBD_EVENT_FUNC_CALL,
   };
-
   event.func_call.func  = func;
   event.func_call.param = param;
 
-  dcd_event_handler(&event, in_isr);
+  queue_event(&event, in_isr);
 }
 
 //--------------------------------------------------------------------+
 // USBD Endpoint API
 //--------------------------------------------------------------------+
 
-bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
-{
+bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) {
   rhport = _usbd_rhport;
 
   TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX);
@@ -1206,67 +1302,59 @@ bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
   return dcd_edpt_open(rhport, desc_ep);
 }
 
-bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   // TODO add this check later, also make sure we don't starve an out endpoint while suspending
   // TU_VERIFY(tud_ready());
 
-  uint8_t const epnum       = tu_edpt_number(ep_addr);
-  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir];
 
-#if TUSB_OPT_MUTEX
   return tu_edpt_claim(ep_state, _usbd_mutex);
-#else
-  return tu_edpt_claim(ep_state, NULL);
-#endif
 }
 
-bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
-  uint8_t const epnum       = tu_edpt_number(ep_addr);
-  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir];
 
-#if TUSB_OPT_MUTEX
   return tu_edpt_release(ep_state, _usbd_mutex);
-#else
-  return tu_edpt_release(ep_state, NULL);
-#endif
 }
 
-bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   // TODO skip ready() check for now since enumeration also use this API
   // TU_VERIFY(tud_ready());
 
-  TU_LOG(USBD_DBG, "  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
+  TU_LOG_USBD("  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
+#if CFG_TUD_LOG_LEVEL >= 3
+  if(dir == TUSB_DIR_IN) {
+    TU_LOG_MEM(CFG_TUD_LOG_LEVEL, buffer, total_bytes, 2);
+  }
+#endif
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
 
   // Set busy first since the actual transfer can be complete before dcd_edpt_xfer()
   // could return and USBD task can preempt and clear the busy
-  _usbd_dev.ep_status[epnum][dir].busy = true;
+  _usbd_dev.ep_status[epnum][dir].busy = 1;
 
-  if ( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) )
-  {
+  if (dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes)) {
     return true;
-  }else
-  {
+  } else {
     // DCD error, mark endpoint as ready to allow next transfer
-    _usbd_dev.ep_status[epnum][dir].busy = false;
+    _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
-    TU_LOG(USBD_DBG, "FAILED\r\n");
+    TU_LOG_USBD("FAILED\r\n");
     TU_BREAKPOINT();
     return false;
   }
@@ -1276,122 +1364,150 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 // bytes should be written and second to keep the return value free to give back a boolean
 // success message. If total_bytes is too big, the FIFO will copy only what is available
 // into the USB buffer!
-bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
+bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes) {
   rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  TU_LOG(USBD_DBG, "  Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
+  TU_LOG_USBD("  Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
 
   // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() could return
   // and usbd task can preempt and clear the busy
-  _usbd_dev.ep_status[epnum][dir].busy = true;
+  _usbd_dev.ep_status[epnum][dir].busy = 1;
 
-  if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes))
-  {
-    TU_LOG(USBD_DBG, "OK\r\n");
+  if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes)) {
+    TU_LOG_USBD("OK\r\n");
     return true;
-  }else
-  {
+  } else {
     // DCD error, mark endpoint as ready to allow next transfer
-    _usbd_dev.ep_status[epnum][dir].busy = false;
+    _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
-    TU_LOG(USBD_DBG, "failed\r\n");
+    TU_LOG_USBD("failed\r\n");
     TU_BREAKPOINT();
     return false;
   }
 }
 
-bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   return _usbd_dev.ep_status[epnum][dir].busy;
 }
 
-void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   // only stalled if currently cleared
-  if ( !_usbd_dev.ep_status[epnum][dir].stalled )
-  {
-    TU_LOG(USBD_DBG, "    Stall EP %02X\r\n", ep_addr);
-    dcd_edpt_stall(rhport, ep_addr);
-    _usbd_dev.ep_status[epnum][dir].stalled = true;
-    _usbd_dev.ep_status[epnum][dir].busy = true;
-  }
+  TU_LOG_USBD("    Stall EP %02X\r\n", ep_addr);
+  dcd_edpt_stall(rhport, ep_addr);
+  _usbd_dev.ep_status[epnum][dir].stalled = 1;
+  _usbd_dev.ep_status[epnum][dir].busy = 1;
 }
 
-void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
   rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   // only clear if currently stalled
-  if ( _usbd_dev.ep_status[epnum][dir].stalled )
-  {
-    TU_LOG(USBD_DBG, "    Clear Stall EP %02X\r\n", ep_addr);
-    dcd_edpt_clear_stall(rhport, ep_addr);
-    _usbd_dev.ep_status[epnum][dir].stalled = false;
-    _usbd_dev.ep_status[epnum][dir].busy = false;
-  }
+  TU_LOG_USBD("    Clear Stall EP %02X\r\n", ep_addr);
+  dcd_edpt_clear_stall(rhport, ep_addr);
+  _usbd_dev.ep_status[epnum][dir].stalled = 0;
+  _usbd_dev.ep_status[epnum][dir].busy = 0;
 }
 
-bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   return _usbd_dev.ep_status[epnum][dir].stalled;
 }
 
 /**
  * usbd_edpt_close will disable an endpoint.
- *
  * In progress transfers on this EP may be delivered after this call.
- *
  */
-void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
-{
+void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+  (void) rhport; (void) ep_addr;
+  // ISO alloc/activate Should be used instead
+#else
   rhport = _usbd_rhport;
 
-  TU_ASSERT(dcd_edpt_close, /**/);
-  TU_LOG(USBD_DBG, "  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
+  TU_LOG_USBD("  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   dcd_edpt_close(rhport, ep_addr);
-  _usbd_dev.ep_status[epnum][dir].stalled = false;
-  _usbd_dev.ep_status[epnum][dir].busy = false;
-  _usbd_dev.ep_status[epnum][dir].claimed = false;
+  _usbd_dev.ep_status[epnum][dir].stalled = 0;
+  _usbd_dev.ep_status[epnum][dir].busy = 0;
+  _usbd_dev.ep_status[epnum][dir].claimed = 0;
+#endif
 
   return;
 }
 
-void usbd_sof_enable(uint8_t rhport, bool en)
-{
+void usbd_sof_enable(uint8_t rhport, sof_consumer_t consumer, bool en) {
   rhport = _usbd_rhport;
 
-  // TODO: Check needed if all drivers including the user sof_cb does not need an active SOF ISR any more.
-  // Only if all drivers switched off SOF calls the SOF interrupt may be disabled
-  dcd_sof_enable(rhport, en);
+  uint8_t consumer_old = _usbd_dev.sof_consumer;
+  // Keep track how many class instances need the SOF interrupt
+  if (en) {
+    _usbd_dev.sof_consumer |= (uint8_t)(1 << consumer);
+  } else {
+    _usbd_dev.sof_consumer &= (uint8_t)(~(1 << consumer));
+  }
+
+  // Test logically unequal
+  if(!_usbd_dev.sof_consumer != !consumer_old) {
+    dcd_sof_enable(rhport, _usbd_dev.sof_consumer);
+  }
+}
+
+bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+  rhport = _usbd_rhport;
+
+  TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX);
+  return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size);
+#else
+  (void) rhport; (void) ep_addr; (void) largest_packet_size;
+  return false;
+#endif
+}
+
+bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) {
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+  rhport = _usbd_rhport;
+
+  uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress);
+  uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress);
+
+  TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX);
+  TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
+
+  _usbd_dev.ep_status[epnum][dir].stalled = 0;
+  _usbd_dev.ep_status[epnum][dir].busy = 0;
+  _usbd_dev.ep_status[epnum][dir].claimed = 0;
+  return dcd_edpt_iso_activate(rhport, desc_ep);
+#else
+  (void) rhport; (void) desc_ep;
+  return false;
+#endif
 }
 
 #endif
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 731c57aad..de6007fb3 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -37,8 +37,23 @@ extern "C" {
 // Application API
 //--------------------------------------------------------------------+
 
-// Init device stack
-bool tud_init (uint8_t rhport);
+// New API to replace tud_init() to init device stack on specific roothub port
+bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
+
+// Init device stack on roothub port
+#if TUSB_VERSION_NUMBER > 2000  // 0.20.0
+TU_ATTR_DEPRECATED("Please use tusb_init(rhport, rh_init) instead")
+#endif
+TU_ATTR_ALWAYS_INLINE static inline bool tud_init (uint8_t rhport) {
+  const tusb_rhport_init_t rh_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL
+  };
+  return tud_rhport_init(rhport, &rh_init);
+}
+
+// Deinit device stack on roothub port
+bool tud_deinit(uint8_t rhport);
 
 // Check if device stack is already initialized
 bool tud_inited(void);
@@ -50,15 +65,14 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr);
 
 // Task function should be called in main/rtos loop
 TU_ATTR_ALWAYS_INLINE static inline
-void tud_task (void)
-{
+void tud_task (void) {
   tud_task_ext(UINT32_MAX, false);
 }
 
 // Check if there is pending events need processing by tud_task()
 bool tud_task_event_ready(void);
 
-#ifndef _TUSB_DCD_H_
+#ifndef TUSB_DCD_H_
 extern void dcd_int_handler(uint8_t rhport);
 #endif
 
@@ -80,8 +94,7 @@ bool tud_suspended(void);
 
 // Check if device is ready to transfer
 TU_ATTR_ALWAYS_INLINE static inline
-bool tud_ready(void)
-{
+bool tud_ready(void) {
   return tud_mounted() && !tud_suspended();
 }
 
@@ -96,6 +109,9 @@ bool tud_disconnect(void);
 // Return false on unsupported MCUs
 bool tud_connect(void);
 
+// Enable or disable the Start Of Frame callback support
+void tud_sof_cb_enable(bool en);
+
 // Carry out Data and Status stage of control transfer
 // - If len = 0, it is equivalent to sending status only
 // - If len > wLength : it will be truncated
@@ -105,7 +121,7 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
 bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request);
 
 //--------------------------------------------------------------------+
-// Application Callbacks (WEAK is optional)
+// Application Callbacks
 //--------------------------------------------------------------------+
 
 // Invoked when received GET DEVICE DESCRIPTOR request
@@ -122,34 +138,40 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid);
 
 // Invoked when received GET BOS DESCRIPTOR request
 // Application return pointer to descriptor
-TU_ATTR_WEAK uint8_t const * tud_descriptor_bos_cb(void);
+uint8_t const * tud_descriptor_bos_cb(void);
 
 // Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
 // device_qualifier descriptor describes information about a high-speed capable device that would
 // change if the device were operating at the other speed. If not highspeed capable stall this request.
-TU_ATTR_WEAK uint8_t const* tud_descriptor_device_qualifier_cb(void);
+uint8_t const* tud_descriptor_device_qualifier_cb(void);
 
 // Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 // Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
-TU_ATTR_WEAK uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index);
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index);
 
 // Invoked when device is mounted (configured)
-TU_ATTR_WEAK void tud_mount_cb(void);
+void tud_mount_cb(void);
 
 // Invoked when device is unmounted
-TU_ATTR_WEAK void tud_umount_cb(void);
+void tud_umount_cb(void);
 
 // Invoked when usb bus is suspended
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en);
+void tud_suspend_cb(bool remote_wakeup_en);
 
 // Invoked when usb bus is resumed
-TU_ATTR_WEAK void tud_resume_cb(void);
+void tud_resume_cb(void);
+
+// Invoked when there is a new usb event, which need to be processed by tud_task()/tud_task_ext()
+void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
+
+// Invoked when a new (micro) frame started
+void tud_sof_cb(uint32_t frame_count);
 
 // Invoked when received control request with VENDOR TYPE
-TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 
 //--------------------------------------------------------------------+
 // Binary Device Object Store (BOS) Descriptor Templates
@@ -217,8 +239,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0120),\
   /* CDC Call */\
   5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_CALL_MANAGEMENT, 0, (uint8_t)((_itfnum) + 1),\
-  /* CDC ACM: support line request */\
-  4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 2,\
+  /* CDC ACM: support line request + send break */\
+  4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 6,\
   /* CDC Union */\
   5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
   /* Endpoint Notification */\
@@ -293,7 +315,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* MIDI Streaming (MS) Interface */\
   9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 2, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_MIDI_STREAMING, AUDIO_FUNC_PROTOCOL_CODE_UNDEF, 0,\
   /* MS Header */\
-  7, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(7 + (_numcables) * TUD_MIDI_DESC_JACK_LEN)
+  7, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(7 + (_numcables) * TUD_MIDI_DESC_JACK_LEN + 2 * TUD_MIDI_DESC_EP_LEN(_numcables))
 
 #define TUD_MIDI_JACKID_IN_EMB(_cablenum) \
   (uint8_t)(((_cablenum) - 1) * 4 + 1)
@@ -317,6 +339,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, _stridx,\
   /* MS Out Jack (External), connected to In Jack Embedded */\
   9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, _stridx
+
 #define TUD_MIDI_DESC_JACK(_cablenum) TUD_MIDI_DESC_JACK_DESC(_cablenum, 0)
 
 #define TUD_MIDI_DESC_EP_LEN(_numcables) (9 + 4 + (_numcables))
@@ -346,8 +369,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 /* Standard Interface Association Descriptor (IAD) */
 #define TUD_AUDIO_DESC_IAD_LEN 8
-#define TUD_AUDIO_DESC_IAD(_firstitfs, _nitfs, _stridx) \
-  TUD_AUDIO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, _firstitfs, _nitfs, TUSB_CLASS_AUDIO, AUDIO_FUNCTION_SUBCLASS_UNDEFINED, AUDIO_FUNC_PROTOCOL_CODE_V2, _stridx
+#define TUD_AUDIO_DESC_IAD(_firstitf, _nitfs, _stridx) \
+  TUD_AUDIO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, _firstitf, _nitfs, TUSB_CLASS_AUDIO, AUDIO_FUNCTION_SUBCLASS_UNDEFINED, AUDIO_FUNC_PROTOCOL_CODE_V2, _stridx
 
 /* Standard AC Interface Descriptor(4.7.1) */
 #define TUD_AUDIO_DESC_STD_AC_LEN 9
@@ -391,6 +414,11 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 // For more channels, add definitions here
 
+/* Standard AC Interrupt Endpoint Descriptor(4.8.2.1) */
+#define TUD_AUDIO_DESC_STD_AC_INT_EP_LEN 7
+#define TUD_AUDIO_DESC_STD_AC_INT_EP(_ep, _interval) \
+  TUD_AUDIO_DESC_STD_AC_INT_EP_LEN, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(6), _interval
+
 /* Standard AS Interface Descriptor(4.9.1) */
 #define TUD_AUDIO_DESC_STD_AS_INT_LEN 9
 #define TUD_AUDIO_DESC_STD_AS_INT(_itfnum, _altset, _nEPs, _stridx) \
@@ -418,8 +446,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */
 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7
-#define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \
-  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval
+#define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _epsize, _interval) \
+  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_NO_SYNC | (uint8_t)TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(_epsize), _interval
 
 // AUDIO simple descriptor (UAC2) for 1 microphone input
 // - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source
@@ -442,7 +470,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 #define TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \
   /* Standard Interface Association Descriptor (IAD) */\
-  TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
   /* Standard AC Interface Descriptor(4.7.1) */\
   TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
   /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
@@ -466,7 +494,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -491,7 +519,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 #define TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \
   /* Standard Interface Association Descriptor (IAD) */\
-  TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
   /* Standard AC Interface Descriptor(4.7.1) */\
   TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
   /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
@@ -515,7 +543,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -537,9 +565,9 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
   + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN)
 
-#define TUD_AUDIO_SPEAKER_MONO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epsize, _epfb) \
+#define TUD_AUDIO_SPEAKER_MONO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epoutsize, _epfb, _epfbsize) \
   /* Standard Interface Association Descriptor (IAD) */\
-  TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
   /* Standard AC Interface Descriptor(4.7.1) */\
   TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
   /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
@@ -551,7 +579,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Output Terminal Descriptor(4.7.2.5) */\
   TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_OUT_DESKTOP_SPEAKER, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
   /* Feature Unit Descriptor(4.7.2.8) */\
-  TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00),\
+  TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00),\
   /* Standard AS Interface Descriptor(4.9.1) */\
   /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
   TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
@@ -563,11 +591,11 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
   /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_interval*/ 1)\
+  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_epsize*/ _epfbsize, /*_interval*/ 1)
 
 //   Calculate wMaxPacketSize of Endpoints
 #define TUD_AUDIO_EP_SIZE(_maxFrequency, _nBytesPerSample, _nChannels) \
@@ -603,7 +631,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 /* optional interrupt endpoint */ \
 // _int_pollingInterval : for LS/FS, expressed in frames (1ms each). 16 may be a good number?
 #define TUD_USBTMC_INT_DESCRIPTOR(_ep_interrupt, _ep_interrupt_size, _int_pollingInterval ) \
-  7, TUSB_DESC_ENDPOINT, _ep_interrupt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_interrupt_size), 0x16
+  7, TUSB_DESC_ENDPOINT, _ep_interrupt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_interrupt_size), _int_pollingInterval
 
 #define TUD_USBTMC_INT_DESCRIPTOR_LEN (7u)
 
@@ -648,7 +676,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 #define TUD_DFU_DESC_LEN(_alt_count)    (9 + (_alt_count) * 9)
 
 // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size
-// Note: Alternate count must be numberic or macro, string index is increased by one for each Alt interface
+// Note: Alternate count must be numeric or macro, string index is increased by one for each Alt interface
 #define TUD_DFU_DESCRIPTOR(_itfnum, _alt_count, _stridx, _attr, _timeout, _xfer_size) \
   TU_XSTRCAT(_TUD_DFU_ALT_,_alt_count)(_itfnum, 0, _stridx), \
   /* Function */ \
@@ -772,10 +800,6 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 #define TUD_BT_PROTOCOL_PRIMARY_CONTROLLER  0x01
 #define TUD_BT_PROTOCOL_AMP_CONTROLLER      0x02
 
-#ifndef CFG_TUD_BTH_ISO_ALT_COUNT
-#define CFG_TUD_BTH_ISO_ALT_COUNT 0
-#endif
-
 // Length of template descriptor: 38 bytes + number of ISO alternatives * 23
 #define TUD_BTH_DESC_LEN (8 + 9 + 7 + 7 + 7 + (CFG_TUD_BTH_ISO_ALT_COUNT) * (9 + 7 + 7))
 
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 187547ae3..c9700fd9d 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -32,98 +32,90 @@
 #include "tusb.h"
 #include "device/usbd_pvt.h"
 
-#if CFG_TUSB_DEBUG >= 2
-extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
-#endif
+//--------------------------------------------------------------------+
+// Callback weak stubs (called if application does not provide)
+//--------------------------------------------------------------------+
+TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, const tusb_control_request_t* request) {
+  (void) rhport;
+  (void) request;
+}
 
-enum
-{
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+enum {
   EDPT_CTRL_OUT = 0x00,
-  EDPT_CTRL_IN  = 0x80
+  EDPT_CTRL_IN = 0x80
 };
 
-typedef struct
-{
+typedef struct {
   tusb_control_request_t request;
-
   uint8_t* buffer;
   uint16_t data_len;
   uint16_t total_xferred;
-
   usbd_control_xfer_cb_t complete_cb;
 } usbd_control_xfer_t;
 
 static usbd_control_xfer_t _ctrl_xfer;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
-static uint8_t _usbd_ctrl_buf[/*CFG_TUD_ENDPOINT0_SIZE*/ 64];
+CFG_TUD_MEM_SECTION static struct {
+  TUD_EPBUF_DEF(buf, CFG_TUD_ENDPOINT0_SIZE);
+} _ctrl_epbuf;
 
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
 
 // Queue ZLP status transaction
-static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request)
-{
+static inline bool status_stage_xact(uint8_t rhport, const tusb_control_request_t* request) {
   // Opposite to endpoint in Data Phase
-  uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN;
+  const uint8_t ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN;
   return usbd_edpt_xfer(rhport, ep_addr, NULL, 0);
 }
 
 // Status phase
-bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
-{
-  _ctrl_xfer.request       = (*request);
-  _ctrl_xfer.buffer        = NULL;
+bool tud_control_status(uint8_t rhport, const tusb_control_request_t* request) {
+  _ctrl_xfer.request = (*request);
+  _ctrl_xfer.buffer = NULL;
   _ctrl_xfer.total_xferred = 0;
-  _ctrl_xfer.data_len      = 0;
+  _ctrl_xfer.data_len = 0;
 
-  return _status_stage_xact(rhport, request);
+  return status_stage_xact(rhport, request);
 }
 
 // Queue a transaction in Data Stage
 // Each transaction has up to Endpoint0's max packet size.
 // This function can also transfer an zero-length packet
-static bool _data_stage_xact(uint8_t rhport)
-{
-  uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE);
-
+static bool data_stage_xact(uint8_t rhport) {
+  const uint16_t xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE);
   uint8_t ep_addr = EDPT_CTRL_OUT;
 
-  if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN )
-  {
+  if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) {
     ep_addr = EDPT_CTRL_IN;
-    if ( xact_len ) memcpy(_usbd_ctrl_buf, _ctrl_xfer.buffer, xact_len);
+    if (xact_len) {
+      TU_VERIFY(0 == tu_memcpy_s(_ctrl_epbuf.buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len));
+    }
   }
 
-  return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len);
+  return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _ctrl_epbuf.buf : NULL, xact_len);
 }
 
 // Transmit data to/from the control endpoint.
 // If the request's wLength is zero, a status packet is sent instead.
-bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, void* buffer, uint16_t len)
-{
-  _ctrl_xfer.request       = (*request);
-  _ctrl_xfer.buffer        = (uint8_t*) buffer;
+bool tud_control_xfer(uint8_t rhport, const tusb_control_request_t* request, void* buffer, uint16_t len) {
+  _ctrl_xfer.request = (*request);
+  _ctrl_xfer.buffer = (uint8_t*) buffer;
   _ctrl_xfer.total_xferred = 0U;
-  _ctrl_xfer.data_len      = tu_min16(len, request->wLength);
+  _ctrl_xfer.data_len = tu_min16(len, request->wLength);
 
-  if (request->wLength > 0U)
-  {
-    if(_ctrl_xfer.data_len > 0U)
-    {
+  if (request->wLength > 0U) {
+    if (_ctrl_xfer.data_len > 0U) {
       TU_ASSERT(buffer);
     }
-
-//    TU_LOG2("  Control total data length is %u bytes\r\n", _ctrl_xfer.data_len);
-
-    // Data stage
-    TU_ASSERT( _data_stage_xact(rhport) );
-  }
-  else
-  {
-    // Status stage
-    TU_ASSERT( _status_stage_xact(rhport, request) );
+    TU_ASSERT(data_stage_xact(rhport));
+  } else {
+    TU_ASSERT(status_stage_xact(rhport, request));
   }
 
   return true;
@@ -132,49 +124,42 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
 //--------------------------------------------------------------------+
 // USBD API
 //--------------------------------------------------------------------+
-
 void usbd_control_reset(void);
-void usbd_control_set_request(tusb_control_request_t const *request);
-void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp );
-bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void usbd_control_set_request(const tusb_control_request_t* request);
+void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp);
+bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
-void usbd_control_reset(void)
-{
+void usbd_control_reset(void) {
   tu_varclr(&_ctrl_xfer);
 }
 
 // Set complete callback
-void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp )
-{
+void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp) {
   _ctrl_xfer.complete_cb = fp;
 }
 
 // for dcd_set_address where DCD is responsible for status response
-void usbd_control_set_request(tusb_control_request_t const *request)
-{
-  _ctrl_xfer.request       = (*request);
-  _ctrl_xfer.buffer        = NULL;
+void usbd_control_set_request(const tusb_control_request_t* request) {
+  _ctrl_xfer.request = (*request);
+  _ctrl_xfer.buffer = NULL;
   _ctrl_xfer.total_xferred = 0;
-  _ctrl_xfer.data_len      = 0;
+  _ctrl_xfer.data_len = 0;
 }
 
 // callback when a transaction complete on
 // - DATA stage of control endpoint or
 // - Status stage
-bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) result;
 
   // Endpoint Address is opposite to direction bit, this is Status Stage complete event
-  if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction )
-  {
+  if (tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction) {
     TU_ASSERT(0 == xferred_bytes);
 
     // invoke optional dcd hook if available
-    if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
+    dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
 
-    if (_ctrl_xfer.complete_cb)
-    {
+    if (_ctrl_xfer.complete_cb) {
       // TODO refactor with usbd_driver_print_control_complete_name
       _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_ACK, &_ctrl_xfer.request);
     }
@@ -182,11 +167,10 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
     return true;
   }
 
-  if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT )
-  {
+  if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) {
     TU_VERIFY(_ctrl_xfer.buffer);
-    memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes);
-    TU_LOG_MEM(2, _usbd_ctrl_buf, xferred_bytes, 2);
+    memcpy(_ctrl_xfer.buffer, _ctrl_epbuf.buf, xferred_bytes);
+    TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2);
   }
 
   _ctrl_xfer.total_xferred += (uint16_t) xferred_bytes;
@@ -194,37 +178,31 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
 
   // Data Stage is complete when all request's length are transferred or
   // a short packet is sent including zero-length packet.
-  if ( (_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) || (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE) )
-  {
+  if ((_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) ||
+      (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE)) {
     // DATA stage is complete
     bool is_ok = true;
 
     // invoke complete callback if set
     // callback can still stall control in status phase e.g out data does not make sense
-    if ( _ctrl_xfer.complete_cb )
-    {
-      #if CFG_TUSB_DEBUG >= 2
+    if (_ctrl_xfer.complete_cb) {
+      #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
       usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
       #endif
 
       is_ok = _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_DATA, &_ctrl_xfer.request);
     }
 
-    if ( is_ok )
-    {
-      // Send status
-      TU_ASSERT( _status_stage_xact(rhport, &_ctrl_xfer.request) );
-    }else
-    {
+    if (is_ok) {
+      TU_ASSERT(status_stage_xact(rhport, &_ctrl_xfer.request));
+    } else {
       // Stall both IN and OUT control endpoint
       dcd_edpt_stall(rhport, EDPT_CTRL_OUT);
       dcd_edpt_stall(rhport, EDPT_CTRL_IN);
     }
-  }
-  else
-  {
+  } else {
     // More data to transfer
-    TU_ASSERT( _data_stage_xact(rhport) );
+    TU_ASSERT(data_stage_xact(rhport));
   }
 
   return true;
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 6fad46db3..190d6fd7f 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,27 +23,36 @@
  *
  * This file is part of the TinyUSB stack.
  */
-#ifndef USBD_PVT_H_
-#define USBD_PVT_H_
+#ifndef TUSB_USBD_PVT_H_
+#define TUSB_USBD_PVT_H_
 
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
+#include "common/tusb_private.h"
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+#define TU_LOG_USBD(...)   TU_LOG(CFG_TUD_LOG_LEVEL, __VA_ARGS__)
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+typedef enum {
+  SOF_CONSUMER_USER = 0,
+  SOF_CONSUMER_AUDIO,
+} sof_consumer_t;
+
 //--------------------------------------------------------------------+
 // Class Driver API
 //--------------------------------------------------------------------+
 
-typedef struct
-{
-  #if CFG_TUSB_DEBUG >= 2
+typedef struct {
   char const* name;
-  #endif
-
   void     (* init             ) (void);
+  bool     (* deinit           ) (void);
   void     (* reset            ) (uint8_t rhport);
   uint16_t (* open             ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);
   bool     (* control_xfer_cb  ) (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
@@ -52,7 +61,7 @@ typedef struct
 } usbd_class_driver_t;
 
 // Invoked when initializing device stack to get additional class drivers.
-// Can optionally implemented by application to extend/overwrite class driver support.
+// Can be implemented by application to extend/overwrite class driver support.
 // Note: The drivers array must be accessible at all time when stack is active
 usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
 
@@ -96,26 +105,35 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr);
 // Check if endpoint is stalled
 bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr);
 
+// Allocate packet buffer used by ISO endpoints
+bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
+
+// Configure and enable an ISO endpoint according to descriptor
+bool usbd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc);
+
 // Check if endpoint is ready (not busy and not stalled)
 TU_ATTR_ALWAYS_INLINE static inline
-bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) {
   return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr);
 }
 
 // Enable SOF interrupt
-void usbd_sof_enable(uint8_t rhport, bool en);
+void usbd_sof_enable(uint8_t rhport, sof_consumer_t consumer, bool en);
 
 /*------------------------------------------------------------------*/
 /* Helper
  *------------------------------------------------------------------*/
 
 bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in);
-void usbd_defer_func( osal_task_func_t func, void* param, bool in_isr );
+void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr);
 
 
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
+void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
+#endif
+
 #ifdef __cplusplus
  }
 #endif
 
-#endif /* USBD_PVT_H_ */
+#endif
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 97b668d79..56b6fdb5d 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -39,8 +39,10 @@
 // Configuration
 //--------------------------------------------------------------------+
 
+// Max number of endpoints pair per device
+// TODO optimize memory usage
 #ifndef CFG_TUH_ENDPOINT_MAX
-  #define CFG_TUH_ENDPOINT_MAX   (CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3 + CFG_TUH_MIDI*2)
+  #define CFG_TUH_ENDPOINT_MAX   16
 //  #ifdef TUP_HCD_ENDPOINT_MAX
 //    #define CFG_TUH_ENDPPOINT_MAX   TUP_HCD_ENDPOINT_MAX
 //  #else
@@ -51,26 +53,21 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-typedef enum
-{
+typedef enum {
   HCD_EVENT_DEVICE_ATTACH,
   HCD_EVENT_DEVICE_REMOVE,
   HCD_EVENT_XFER_COMPLETE,
 
-  // Not an HCD event, just a convenient way to defer ISR function
-  USBH_EVENT_FUNC_CALL,
-
+  USBH_EVENT_FUNC_CALL, // Not an HCD event
   HCD_EVENT_COUNT
 } hcd_eventid_t;
 
-typedef struct
-{
+typedef struct {
   uint8_t rhport;
   uint8_t event_id;
   uint8_t dev_addr;
 
-  union
-  {
+  union {
     // Attach, Remove
     struct {
       uint8_t hub_addr;
@@ -91,29 +88,46 @@ typedef struct
       void* param;
     }func_call;
   };
-
 } hcd_event_t;
 
-typedef struct
-{
+typedef struct {
   uint8_t rhport;
   uint8_t hub_addr;
   uint8_t hub_port;
   uint8_t speed;
 } hcd_devtree_info_t;
 
+//--------------------------------------------------------------------+
+// Memory API
+//--------------------------------------------------------------------+
+
+// clean/flush data cache: write cache -> memory.
+// Required before an DMA TX transfer to make sure data is in memory
+bool hcd_dcache_clean(void const* addr, uint32_t data_size);
+
+// invalidate data cache: mark cache as invalid, next read will read from memory
+// Required BOTH before and after an DMA RX transfer
+bool hcd_dcache_invalidate(void const* addr, uint32_t data_size);
+
+// clean and invalidate data cache
+// Required before an DMA transfer where memory is both read/write by DMA
+bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size);
+
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
 
-// optional hcd configuration, called by tuh_config()
-bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_ATTR_WEAK;
+// optional hcd configuration, called by tuh_configure()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
 
 // Initialize controller to host mode
-bool hcd_init(uint8_t rhport);
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
+
+// De-initialize controller
+bool hcd_deinit(uint8_t rhport);
 
 // Interrupt Handler
-void hcd_int_handler(uint8_t rhport);
+void hcd_int_handler(uint8_t rhport, bool in_isr);
 
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport);
@@ -131,10 +145,11 @@ uint32_t hcd_frame_number(uint8_t rhport);
 // Get the current connect status of roothub port
 bool hcd_port_connect_status(uint8_t rhport);
 
-// Reset USB bus on the port
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport);
 
-// TODO implement later
+// Complete bus reset sequence, may be required by some controllers
 void hcd_port_reset_end(uint8_t rhport);
 
 // Get port link speed
@@ -148,16 +163,20 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
 //--------------------------------------------------------------------+
 
 // Open an endpoint
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
+bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc);
 
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
+bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]);
 
 // clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
 // USBH implemented API
@@ -175,20 +194,19 @@ extern void hcd_event_handler(hcd_event_t const* event, bool in_isr);
 
 // Helper to send device attach event
 TU_ATTR_ALWAYS_INLINE static inline
-void hcd_event_device_attach(uint8_t rhport, bool in_isr)
-{
+void hcd_event_device_attach(uint8_t rhport, bool in_isr) {
   hcd_event_t event;
   event.rhport              = rhport;
   event.event_id            = HCD_EVENT_DEVICE_ATTACH;
   event.connection.hub_addr = 0;
   event.connection.hub_port = 0;
+
   hcd_event_handler(&event, in_isr);
 }
 
 // Helper to send device removal event
 TU_ATTR_ALWAYS_INLINE static inline
-void hcd_event_device_remove(uint8_t rhport, bool in_isr)
-{
+void hcd_event_device_remove(uint8_t rhport, bool in_isr) {
   hcd_event_t event;
   event.rhport              = rhport;
   event.event_id            = HCD_EVENT_DEVICE_REMOVE;
@@ -200,10 +218,8 @@ void hcd_event_device_remove(uint8_t rhport, bool in_isr)
 
 // Helper to send USB transfer event
 TU_ATTR_ALWAYS_INLINE static inline
-void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
-{
-  hcd_event_t event =
-  {
+void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr) {
+  hcd_event_t event = {
     .rhport   = 0, // TODO correct rhport
     .event_id = HCD_EVENT_XFER_COMPLETE,
     .dev_addr = dev_addr,
@@ -212,7 +228,6 @@ void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred
   event.xfer_complete.result = result;
   event.xfer_complete.len = xferred_bytes;
 
-
   hcd_event_handler(&event, in_isr);
 }
 
diff --git a/src/host/hub.c b/src/host/hub.c
index 3da5358b2..e97014443 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -30,9 +30,13 @@
 
 #include "hcd.h"
 #include "usbh.h"
-#include "usbh_classdriver.h"
+#include "usbh_pvt.h"
 #include "hub.h"
 
+// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
+#define HUB_DEBUG   2
+#define TU_LOG_DRV(...)   TU_LOG(HUB_DEBUG, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -41,14 +45,14 @@ typedef struct
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t port_count;
-  uint8_t status_change; // data from status change interrupt endpoint
 
-  hub_port_status_response_t port_status;
-  hub_status_response_t hub_status;
+  CFG_TUH_MEM_ALIGN uint8_t status_change;
+  CFG_TUH_MEM_ALIGN hub_port_status_response_t port_status;
+  CFG_TUH_MEM_ALIGN hub_status_response_t hub_status;
 } hub_interface_t;
 
-CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB];
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
+CFG_TUH_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB];
+CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
 
 TU_ATTR_ALWAYS_INLINE
 static inline hub_interface_t* get_itf(uint8_t dev_addr)
@@ -178,9 +182,13 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
 //--------------------------------------------------------------------+
 // CLASS-USBH API (don't require to verify parameters)
 //--------------------------------------------------------------------+
-void hub_init(void)
-{
+bool hub_init(void) {
   tu_memclr(hub_data, sizeof(hub_data));
+  return true;
+}
+
+bool hub_deinit(void) {
+  return true;
 }
 
 bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
@@ -202,7 +210,7 @@ bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf
 
   TU_ASSERT(TUSB_DESC_ENDPOINT  == desc_ep->bDescriptorType &&
             TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
-  
+
   TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep));
 
   hub_interface_t* p_hub = get_itf(dev_addr);
@@ -218,7 +226,10 @@ void hub_close(uint8_t dev_addr)
   TU_VERIFY(dev_addr > CFG_TUH_DEVICE_MAX, );
   hub_interface_t* p_hub = get_itf(dev_addr);
 
-  if (p_hub->ep_in) tu_memclr(p_hub, sizeof( hub_interface_t));
+  if (p_hub->ep_in) {
+    TU_LOG_DRV("  HUB close addr = %d\r\n", dev_addr);
+    tu_memclr(p_hub, sizeof( hub_interface_t));
+  }
 }
 
 bool hub_edpt_status_xfer(uint8_t dev_addr)
@@ -320,34 +331,35 @@ static void connection_clear_conn_change_complete (tuh_xfer_t* xfer);
 static void connection_port_reset_complete (tuh_xfer_t* xfer);
 
 // callback as response of interrupt endpoint polling
-bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports
   (void) ep_addr;
-  TU_ASSERT(result == XFER_RESULT_SUCCESS);
+  TU_VERIFY(result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
 
-  TU_LOG2("  Hub Status Change = 0x%02X\r\n", p_hub->status_change);
+  uint8_t const status_change = p_hub->status_change;
+  TU_LOG2("  Hub Status Change = 0x%02X\r\n", status_change);
 
-  // Hub bit 0 is for the hub device events
-  if (tu_bit_test(p_hub->status_change, 0))
-  {
-    if (hub_port_get_status(dev_addr, 0, &p_hub->hub_status, hub_get_status_complete, 0) == false)
-    {
+  if ( status_change == 0 ) {
+    // The status change event was neither for the hub, nor for any of its ports.
+    // This shouldn't happen, but it does with some devices.
+    // Initiate the next interrupt poll here.
+    return hub_edpt_status_xfer(dev_addr);
+  }
+
+  if (tu_bit_test(status_change, 0)) {
+    // Hub bit 0 is for the hub device events
+    if (hub_port_get_status(dev_addr, 0, &p_hub->hub_status, hub_get_status_complete, 0) == false) {
       //Hub status control transfer failed, retry
       hub_edpt_status_xfer(dev_addr);
     }
   }
-  else
-  {
+  else {
     // Hub bits 1 to n are hub port events
-    for (uint8_t port=1; port <= p_hub->port_count; port++)
-    {
-      if ( tu_bit_test(p_hub->status_change, port) )
-      {
-        if (hub_port_get_status(dev_addr, port, &p_hub->port_status, hub_port_get_status_complete, 0) == false)
-        {
+    for (uint8_t port=1; port <= p_hub->port_count; port++) {
+      if ( tu_bit_test(status_change, port) ) {
+        if (hub_port_get_status(dev_addr, port, &p_hub->port_status, hub_port_get_status_complete, 0) == false) {
           //Hub status control transfer failed, retry
           hub_edpt_status_xfer(dev_addr);
         }
@@ -357,7 +369,6 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   }
 
   // NOTE: next status transfer is queued by usbh.c after handling this request
-
   return true;
 }
 
@@ -428,9 +439,12 @@ static void hub_port_get_status_complete (tuh_xfer_t* xfer)
     // Other changes are: L1 state
     // TODO clear change
 
-    // prepare for next hub status
-    // TODO continue with status_change, or maybe we can do it again with status
-    hub_edpt_status_xfer(daddr);
+    else
+    {
+      // prepare for next hub status
+      // TODO continue with status_change, or maybe we can do it again with status
+      hub_edpt_status_xfer(daddr);
+    }
   }
 }
 
diff --git a/src/host/hub.h b/src/host/hub.h
index 390740e1f..385efe6b2 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -187,16 +187,14 @@ bool hub_port_get_status    (uint8_t hub_addr, uint8_t hub_port, void* resp,
 bool hub_edpt_status_xfer(uint8_t dev_addr);
 
 // Reset a port
-static inline bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port,
-                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+TU_ATTR_ALWAYS_INLINE static inline
+bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb, user_data);
 }
 
 // Clear Reset Change
-static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port,
-                                               tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+TU_ATTR_ALWAYS_INLINE static inline
+bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return hub_port_clear_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET_CHANGE, complete_cb, user_data);
 }
 
@@ -204,7 +202,8 @@ static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_por
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void hub_init       (void);
+bool hub_init       (void);
+bool hub_deinit     (void);
 bool hub_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 bool hub_set_config (uint8_t dev_addr, uint8_t itf_num);
 bool hub_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 44b4d3217..6f7a8b8bf 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -30,47 +30,70 @@
 
 #include "host/hcd.h"
 #include "tusb.h"
-#include "common/tusb_private.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 #include "hub.h"
 
 //--------------------------------------------------------------------+
 // USBH Configuration
 //--------------------------------------------------------------------+
-
 #ifndef CFG_TUH_TASK_QUEUE_SZ
-#define CFG_TUH_TASK_QUEUE_SZ   16
+  #define CFG_TUH_TASK_QUEUE_SZ   16
 #endif
 
 #ifndef CFG_TUH_INTERFACE_MAX
-#define CFG_TUH_INTERFACE_MAX   8
+  #define CFG_TUH_INTERFACE_MAX   8
 #endif
 
-// Debug level of USBD
-#define USBH_DBG_LVL   2
+//--------------------------------------------------------------------+
+// Weak stubs: invoked if no strong implementation is available
+//--------------------------------------------------------------------+
+TU_ATTR_WEAK bool hcd_deinit(uint8_t rhport) {
+  (void) rhport;
+  return false;
+}
+
+TU_ATTR_WEAK bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  (void) cfg_id;
+  (void) cfg_param;
+  return false;
+}
+
+TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
+  (void) rhport;
+  (void) eventid;
+  (void) in_isr;
+}
+
+TU_ATTR_WEAK bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
+  (void) addr; (void) data_size;
+  return false;
+}
+
+TU_ATTR_WEAK bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) {
+  (void) addr; (void) data_size;
+  return false;
+}
+
+TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
+  (void) addr; (void) data_size;
+  return false;
+}
 
 //--------------------------------------------------------------------+
 // USBH-HCD common data structure
 //--------------------------------------------------------------------+
-
-// device0 struct must be strictly a subset of normal device struct
-// TODO refactor later
-typedef struct
-{
+typedef struct {
   // port
   uint8_t rhport;
   uint8_t hub_addr;
   uint8_t hub_port;
-  uint8_t speed;
 
-  struct TU_ATTR_PACKED
-  {
-    volatile uint8_t connected  : 1;
-    volatile uint8_t addressed  : 1;
-    volatile uint8_t configured : 1;
-    volatile uint8_t suspended  : 1;
+  struct TU_ATTR_PACKED {
+             uint8_t speed       : 4; // packed speed to save footprint
+    volatile uint8_t enumerating : 1; // enumeration is in progress, false if not connected or all interfaces are configured
+    uint8_t TU_RESERVED : 3;
   };
-
 } usbh_dev0_t;
 
 typedef struct {
@@ -82,10 +105,12 @@ typedef struct {
 
   // Device State
   struct TU_ATTR_PACKED {
-    volatile uint8_t connected  : 1;
-    volatile uint8_t addressed  : 1;
-    volatile uint8_t configured : 1;
-    volatile uint8_t suspended  : 1;
+    volatile uint8_t connected  : 1; // After 1st transfer
+    volatile uint8_t addressed  : 1; // After SET_ADDR
+    volatile uint8_t configured : 1; // After SET_CONFIG and all drivers are configured
+    volatile uint8_t suspended  : 1; // Bus suspended
+
+    // volatile uint8_t removing : 1; // Physically disconnected, waiting to be processed by usbh
   };
 
   // Device Descriptor
@@ -120,91 +145,105 @@ typedef struct {
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-
-// Invalid driver ID in itf2drv[] ep2drv[][] mapping
-enum { DRVID_INVALID = 0xFFu };
-enum { CONTROLLER_INVALID = 0xFFu };
-
-#if CFG_TUSB_DEBUG >= 2
-  #define DRIVER_NAME(_name)    .name = _name,
+#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
+  #define DRIVER_NAME(_name)  _name
 #else
-  #define DRIVER_NAME(_name)
+  #define DRIVER_NAME(_name)  NULL
 #endif
 
-static usbh_class_driver_t const usbh_class_drivers[] =
-{
+static usbh_class_driver_t const usbh_class_drivers[] = {
   #if CFG_TUH_CDC
-    {
-      DRIVER_NAME("CDC")
+  {
+      .name       = DRIVER_NAME("CDC"),
       .init       = cdch_init,
+      .deinit     = cdch_deinit,
       .open       = cdch_open,
       .set_config = cdch_set_config,
       .xfer_cb    = cdch_xfer_cb,
       .close      = cdch_close
-    },
+  },
   #endif
 
   #if CFG_TUH_MSC
-    {
-      DRIVER_NAME("MSC")
+  {
+      .name       = DRIVER_NAME("MSC"),
       .init       = msch_init,
+      .deinit     = msch_deinit,
       .open       = msch_open,
       .set_config = msch_set_config,
       .xfer_cb    = msch_xfer_cb,
       .close      = msch_close
-    },
+  },
   #endif
 
   #if CFG_TUH_HID
-    {
-      DRIVER_NAME("HID")
+  {
+      .name       = DRIVER_NAME("HID"),
       .init       = hidh_init,
+      .deinit     = hidh_deinit,
       .open       = hidh_open,
       .set_config = hidh_set_config,
       .xfer_cb    = hidh_xfer_cb,
       .close      = hidh_close
-    },
+  },
   #endif
 
   #if CFG_TUH_MIDI
-    {
-      DRIVER_NAME("MIDI")
+  {
+      .name       = DRIVER_NAME("MIDI"),
       .init       = midih_init,
       .open       = midih_open,
       .set_config = midih_set_config,
       .xfer_cb    = midih_xfer_cb,
       .close      = midih_close
-    },
+  },
   #endif
 
   #if CFG_TUH_HUB
-    {
-      DRIVER_NAME("HUB")
+  {
+      .name       = DRIVER_NAME("HUB"),
       .init       = hub_init,
+      .deinit     = hub_deinit,
       .open       = hub_open,
       .set_config = hub_set_config,
       .xfer_cb    = hub_xfer_cb,
       .close      = hub_close
-    },
+  },
   #endif
 
   #if CFG_TUH_VENDOR
-    {
-      DRIVER_NAME("VENDOR")
-      .init       = cush_init,
-      .open       = cush_open_subtask,
-      .xfer_cb    = cush_isr,
-      .close      = cush_close
-    }
+  {
+    .name       = DRIVER_NAME("VENDOR"),
+    .init       = cush_init,
+    .deinit     = cush_deinit,
+    .open       = cush_open,
+    .set_config = cush_set_config,
+    .xfer_cb    = cush_isr,
+    .close      = cush_close
+  }
   #endif
 };
 
-enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
-
-enum { RESET_DELAY = 500 };  // 200 USB specs say only 50ms but many devices require much longer
-
+enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
 enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
+// Additional class drivers implemented by application
+tu_static usbh_class_driver_t const * _app_driver = NULL;
+tu_static uint8_t _app_driver_count = 0;
+
+#define TOTAL_DRIVER_COUNT    (_app_driver_count + BUILTIN_DRIVER_COUNT)
+
+static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) {
+  usbh_class_driver_t const *driver = NULL;
+
+  if ( drv_id < _app_driver_count ) {
+    driver = &_app_driver[drv_id];
+  } else if ( drv_id < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0) {
+    driver = &usbh_class_drivers[drv_id - _app_driver_count];
+  }
+
+  return driver;
+}
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -213,7 +252,7 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1
 // sum of end device + hub
 #define TOTAL_DEVICES   (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB)
 
-static uint8_t _usbh_controller = CONTROLLER_INVALID;
+static uint8_t _usbh_controller = TUSB_INDEX_INVALID_8;
 
 // Device with address = 0 for enumeration
 static usbh_dev0_t _dev0;
@@ -221,30 +260,14 @@ static usbh_dev0_t _dev0;
 // all devices excluding zero-address
 // hub address start from CFG_TUH_DEVICE_MAX+1
 // TODO: hub can has its own simpler struct to save memory
-CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES];
-
-// Mutex for claiming endpoint, only needed when using with preempted RTOS
-#if TUSB_OPT_MUTEX
-static osal_mutex_def_t _usbh_mutexdef;
-static osal_mutex_t _usbh_mutex;
-
-TU_ATTR_ALWAYS_INLINE static inline void usbh_lock(void)
-{
-  osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void usbh_unlock(void)
-{
-  osal_mutex_unlock(_usbh_mutex);
-}
+static usbh_device_t _usbh_devices[TOTAL_DEVICES];
 
+// Mutex for claiming endpoint
+#if OSAL_MUTEX_REQUIRED
+  static osal_mutex_def_t _usbh_mutexdef;
+  static osal_mutex_t _usbh_mutex;
 #else
-
-#define _usbh_mutex   NULL
-
-#define usbh_lock()
-#define usbh_unlock()
-
+  #define _usbh_mutex   NULL
 #endif
 
 // Event queue
@@ -252,15 +275,10 @@ TU_ATTR_ALWAYS_INLINE static inline void usbh_unlock(void)
 OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
-static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
-
-// Control transfer: since most controller does not support multiple control transfer
-// on multiple devices concurrently. And control transfer is not used much except enumeration
-// We will only execute control transfer one at a time.
-struct
-{
-  tusb_control_request_t request TU_ATTR_ALIGNED(4);
+// Control transfers: since most controllers do not support multiple control transfers
+// on multiple devices concurrently and control transfers are not used much except for
+// enumeration, we will only execute control transfers one at a time.
+static struct {
   uint8_t* buffer;
   tuh_xfer_cb_t complete_cb;
   uintptr_t user_data;
@@ -268,61 +286,48 @@ struct
   uint8_t daddr;
   volatile uint8_t stage;
   volatile uint16_t actual_len;
-}_ctrl_xfer;
+} _ctrl_xfer;
+
+typedef struct {
+  TUH_EPBUF_TYPE_DEF(tusb_control_request_t, request);
+  TUH_EPBUF_DEF(ctrl, CFG_TUH_ENUMERATION_BUFSIZE);
+} usbh_epbuf_t;
+
+CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf;
 
 //------------- Helper Function -------------//
 
-TU_ATTR_ALWAYS_INLINE
-static inline usbh_device_t* get_device(uint8_t dev_addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) {
   TU_VERIFY(dev_addr > 0 && dev_addr <= TOTAL_DEVICES, NULL);
   return &_usbh_devices[dev_addr-1];
 }
 
 static bool enum_new_device(hcd_event_t* event);
-static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port);
+static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port);
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
-#if CFG_TUSB_OS == OPT_OS_NONE
-// TODO rework time-related function later
-void osal_task_delay(uint32_t msec)
-{
-  (void) msec;
-
-  const uint32_t start = hcd_frame_number(_usbh_controller);
-  while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
-}
-#endif
-
-//--------------------------------------------------------------------+
-// PUBLIC API (Parameter Verification is required)
-//--------------------------------------------------------------------+
-
-bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param)
-{
-  if (hcd_configure)
-  {
-    return hcd_configure(rhport, cfg_id, cfg_param);
-  }else
-  {
-    return false;
-  }
+TU_ATTR_ALWAYS_INLINE static inline bool queue_event(hcd_event_t const * event, bool in_isr) {
+  TU_ASSERT(osal_queue_send(_usbh_q, event, in_isr));
+  tuh_event_hook_cb(event->rhport, event->event_id, in_isr);
+  return true;
 }
 
-bool tuh_mounted(uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
+//--------------------------------------------------------------------+
+// Device API
+//--------------------------------------------------------------------+
+
+bool tuh_mounted(uint8_t dev_addr) {
+  usbh_device_t *dev = get_device(dev_addr);
   TU_VERIFY(dev);
   return dev->configured;
 }
 
-bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
-{
+bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) {
   *vid = *pid = 0;
 
-  usbh_device_t const* dev = get_device(dev_addr);
-  TU_VERIFY(dev && dev->configured);
+  usbh_device_t const *dev = get_device(dev_addr);
+  TU_VERIFY(dev && dev->addressed && dev->vid != 0);
 
   *vid = dev->vid;
   *pid = dev->pid;
@@ -330,70 +335,144 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
   return true;
 }
 
-tusb_speed_t tuh_speed_get (uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
+tusb_speed_t tuh_speed_get(uint8_t dev_addr) {
+  usbh_device_t *dev = get_device(dev_addr);
   return (tusb_speed_t) (dev ? get_device(dev_addr)->speed : _dev0.speed);
 }
 
-static void clear_device(usbh_device_t* dev)
-{
+bool tuh_rhport_is_active(uint8_t rhport) {
+  return _usbh_controller == rhport;
+}
+
+bool tuh_rhport_reset_bus(uint8_t rhport, bool active) {
+  TU_VERIFY(tuh_rhport_is_active(rhport));
+  if ( active ) {
+    hcd_port_reset(rhport);
+  } else {
+    hcd_port_reset_end(rhport);
+  }
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// PUBLIC API (Parameter Verification is required)
+//--------------------------------------------------------------------+
+
+bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) {
+  return hcd_configure(rhport, cfg_id, cfg_param);
+}
+
+static void clear_device(usbh_device_t* dev) {
   tu_memclr(dev, sizeof(usbh_device_t));
-  memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
-  memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
+  memset(dev->itf2drv, TUSB_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping
+  memset(dev->ep2drv , TUSB_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping
 }
 
-bool tuh_inited(void)
-{
-  return _usbh_controller != CONTROLLER_INVALID;
+bool tuh_inited(void) {
+  return _usbh_controller != TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_init(uint8_t controller_id)
-{
-  // skip if already initialized
-  if ( tuh_inited() ) return true;
+bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  if (tuh_rhport_is_active(rhport)) {
+    return true; // skip if already initialized
+  }
 
-  TU_LOG2("USBH init on controller %u\r\n", controller_id);
-  TU_LOG2_INT(sizeof(usbh_device_t));
-  TU_LOG2_INT(sizeof(hcd_event_t));
-  TU_LOG2_INT(sizeof(_ctrl_xfer));
-  TU_LOG2_INT(sizeof(tuh_xfer_t));
+  TU_LOG_USBH("USBH init on controller %u, speed = %s\r\n", rhport,
+    rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
 
-  // Event queue
-  _usbh_q = osal_queue_create( &_usbh_qdef );
-  TU_ASSERT(_usbh_q != NULL);
+  // Init host stack if not already
+  if (!tuh_inited()) {
+    TU_LOG_INT_USBH(sizeof(usbh_device_t));
+    TU_LOG_INT_USBH(sizeof(hcd_event_t));
+    TU_LOG_INT_USBH(sizeof(_ctrl_xfer));
+    TU_LOG_INT_USBH(sizeof(tuh_xfer_t));
+    TU_LOG_INT_USBH(sizeof(tu_fifo_t));
+    TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t));
 
-#if TUSB_OPT_MUTEX
-  // Mutex
-  _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
-  TU_ASSERT(_usbh_mutex);
+    // Event queue
+    _usbh_q = osal_queue_create(&_usbh_qdef);
+    TU_ASSERT(_usbh_q != NULL);
+
+#if OSAL_MUTEX_REQUIRED
+    // Init mutex
+    _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
+    TU_ASSERT(_usbh_mutex);
 #endif
 
-  // Device
-  tu_memclr(&_dev0, sizeof(_dev0));
-  tu_memclr(_usbh_devices, sizeof(_usbh_devices));
-  tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer));
+    // Get application driver if available
+    if (usbh_app_driver_get_cb) {
+      _app_driver = usbh_app_driver_get_cb(&_app_driver_count);
+    }
 
-  for(uint8_t i=0; i<TOTAL_DEVICES; i++)
-  {
-    clear_device(&_usbh_devices[i]);
+    // Device
+    tu_memclr(&_dev0, sizeof(_dev0));
+    tu_memclr(_usbh_devices, sizeof(_usbh_devices));
+    tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer));
+
+    for (uint8_t i = 0; i < TOTAL_DEVICES; i++) {
+      clear_device(&_usbh_devices[i]);
+    }
+
+    // Class drivers
+    for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+      usbh_class_driver_t const* driver = get_driver(drv_id);
+      if (driver) {
+        TU_LOG_USBH("%s init\r\n", driver->name);
+        driver->init();
+      }
+    }
   }
 
-  // Class drivers
-  for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
-  {
-    TU_LOG2("%s init\r\n", usbh_class_drivers[drv_id].name);
-    usbh_class_drivers[drv_id].init();
-  }
-
-  _usbh_controller = controller_id;;
-
-  TU_ASSERT(hcd_init(controller_id));
-  hcd_int_enable(controller_id);
+  // Init host controller
+  _usbh_controller = rhport;
+  TU_ASSERT(hcd_init(rhport, rh_init));
+  hcd_int_enable(rhport);
 
   return true;
 }
 
+bool tuh_deinit(uint8_t rhport) {
+  if (!tuh_rhport_is_active(rhport)) return true;
+
+  // deinit host controller
+  hcd_int_disable(rhport);
+  hcd_deinit(rhport);
+  _usbh_controller = TUSB_INDEX_INVALID_8;
+
+  // "unplug" all devices on this rhport (hub_addr = 0, hub_port = 0)
+  process_removing_device(rhport, 0, 0);
+
+  // deinit host stack if no controller is active
+  if (!tuh_inited()) {
+    // Class drivers
+    for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+      usbh_class_driver_t const* driver = get_driver(drv_id);
+      if (driver && driver->deinit) {
+        TU_LOG_USBH("%s deinit\r\n", driver->name);
+        driver->deinit();
+      }
+    }
+
+    osal_queue_delete(_usbh_q);
+    _usbh_q = NULL;
+
+    #if OSAL_MUTEX_REQUIRED
+    // TODO make sure there is no task waiting on this mutex
+    osal_mutex_delete(_usbh_mutex);
+    _usbh_mutex = NULL;
+    #endif
+  }
+
+  return true;
+}
+
+bool tuh_task_event_ready(void) {
+  if (!tuh_inited()) {
+    return false; // Skip if stack is not initialized
+  }
+  return !osal_queue_empty(_usbh_q);
+}
+
 /* USB Host Driver task
  * This top level thread manages all host controller event and delegates events to class-specific drivers.
  * This should be called periodically within the mainloop or rtos thread.
@@ -402,7 +481,7 @@ bool tuh_init(uint8_t controller_id)
     int main(void)
     {
       application_init();
-      tusb_init();
+      tusb_init(0, TUSB_ROLE_HOST);
 
       while(1) // the mainloop
       {
@@ -412,83 +491,89 @@ bool tuh_init(uint8_t controller_id)
     }
     @endcode
  */
-void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
-{
+void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
   (void) in_isr; // not implemented yet
 
   // Skip if stack is not initialized
-  if ( !tusb_inited() ) return;
+  if (!tuh_inited()) return;
 
   // Loop until there is no more events in the queue
-  while (1)
-  {
+  while (1) {
     hcd_event_t event;
-    if ( !osal_queue_receive(_usbh_q, &event, timeout_ms) ) return;
+    if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) return;
 
-    switch (event.event_id)
-    {
+    switch (event.event_id) {
       case HCD_EVENT_DEVICE_ATTACH:
-        // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
-        // one device before enumerating another one.
-        TU_LOG2("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
-        enum_new_device(&event);
-      break;
+        // due to the shared control buffer, we must complete enumerating one device before enumerating another one.
+        // TODO better to have an separated queue for newly attached devices
+        if (_dev0.enumerating) {
+          // Some device can cause multiple duplicated attach events
+          // drop current enumerating and start over for a proper port reset
+          if (event.rhport == _dev0.rhport && event.connection.hub_addr == _dev0.hub_addr &&
+              event.connection.hub_port == _dev0.hub_port) {
+            // abort/cancel current enumeration and start new one
+            TU_LOG1("[%u:] USBH Device Attach (duplicated)\r\n", event.rhport);
+            tuh_edpt_abort_xfer(0, 0);
+            enum_new_device(&event);
+          } else {
+            TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
+
+            bool is_empty = osal_queue_empty(_usbh_q);
+            queue_event(&event, in_isr);
+
+            if (is_empty) {
+              // Exit if this is the only event in the queue, otherwise we may loop forever
+              return;
+            }
+          }
+        } else {
+          TU_LOG1("[%u:] USBH Device Attach\r\n", event.rhport);
+          _dev0.enumerating = 1;
+          enum_new_device(&event);
+        }
+        break;
 
       case HCD_EVENT_DEVICE_REMOVE:
-        TU_LOG2("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
-        process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port);
+        TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
+        process_removing_device(event.rhport, event.connection.hub_addr, event.connection.hub_port);
 
         #if CFG_TUH_HUB
         // TODO remove
-        if ( event.connection.hub_addr != 0)
-        {
+        if (event.connection.hub_addr != 0 && event.connection.hub_port != 0) {
           // done with hub, waiting for next data on status pipe
-          (void) hub_edpt_status_xfer( event.connection.hub_addr );
+          (void) hub_edpt_status_xfer(event.connection.hub_addr);
         }
         #endif
-      break;
+        break;
 
-      case HCD_EVENT_XFER_COMPLETE:
-      {
+      case HCD_EVENT_XFER_COMPLETE: {
         uint8_t const ep_addr = event.xfer_complete.ep_addr;
-        uint8_t const epnum   = tu_edpt_number(ep_addr);
-        uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
+        uint8_t const epnum = tu_edpt_number(ep_addr);
+        uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
 
-        TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+        TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len, tu_str_xfer_result[event.xfer_complete.result]);
 
-        if (event.dev_addr == 0)
-        {
+        if (event.dev_addr == 0) {
           // device 0 only has control endpoint
-          TU_ASSERT(epnum == 0, );
-          usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
-        }
-        else
-        {
+          TU_ASSERT(epnum == 0,);
+          usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
+        } else {
           usbh_device_t* dev = get_device(event.dev_addr);
-          TU_ASSERT(dev, );
+          TU_VERIFY(dev && dev->connected,);
 
-          dev->ep_status[epnum][ep_dir].busy    = 0;
+          dev->ep_status[epnum][ep_dir].busy = 0;
           dev->ep_status[epnum][ep_dir].claimed = 0;
 
-          if ( 0 == epnum )
-          {
-            usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
-          }else
-          {
-            uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
-            if(drv_id < USBH_CLASS_DRIVER_COUNT)
-            {
-              TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
-              usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
-            }
-            else
-            {
-#if CFG_TUH_API_EDPT_XFER
-              tuh_xfer_cb_t complete_cb = dev->ep_callback[epnum][ep_dir].complete_cb;
-              if ( complete_cb )
-              {
-                tuh_xfer_t xfer =
-                {
+          if (0 == epnum) {
+            usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
+          } else {
+            // Prefer application callback over built-in one if available. This occurs when tuh_edpt_xfer() is used
+            // with enabled driver e.g HID endpoint
+            #if CFG_TUH_API_EDPT_XFER
+            tuh_xfer_cb_t const complete_cb = dev->ep_callback[epnum][ep_dir].complete_cb;
+            if ( complete_cb ) {
+              // re-construct xfer info
+              tuh_xfer_t xfer = {
                   .daddr       = event.dev_addr,
                   .ep_addr     = ep_addr,
                   .result      = event.xfer_complete.result,
@@ -497,27 +582,33 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
                   .buffer      = NULL, // not available
                   .complete_cb = complete_cb,
                   .user_data   = dev->ep_callback[epnum][ep_dir].user_data
-                };
-
-                complete_cb(&xfer);
-              }else
-#endif
-              {
+              };
+              complete_cb(&xfer);
+            }else
+            #endif
+            {
+              uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
+              usbh_class_driver_t const* driver = get_driver(drv_id);
+              if (driver) {
+                TU_LOG_USBH("%s xfer callback\r\n", driver->name);
+                driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
+                                event.xfer_complete.len);
+              } else {
                 // no driver/callback responsible for this transfer
-                TU_ASSERT(false, );
+                TU_ASSERT(false,);
               }
-
             }
           }
         }
+        break;
       }
-      break;
 
       case USBH_EVENT_FUNC_CALL:
-        if ( event.func_call.func ) event.func_call.func(event.func_call.param);
-      break;
+        if (event.func_call.func) event.func_call.func(event.func_call.param);
+        break;
 
-      default: break;
+      default:
+        break;
     }
 
 #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
@@ -531,53 +622,54 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
 // Control transfer
 //--------------------------------------------------------------------+
 
-static void _control_blocking_complete_cb(tuh_xfer_t* xfer)
-{
+static void _control_blocking_complete_cb(tuh_xfer_t* xfer) {
   // update result
   *((xfer_result_t*) xfer->user_data) = xfer->result;
 }
 
 // TODO timeout_ms is not supported yet
-bool tuh_control_xfer (tuh_xfer_t* xfer)
-{
+bool tuh_control_xfer (tuh_xfer_t* xfer) {
   // EP0 with setup packet
   TU_VERIFY(xfer->ep_addr == 0 && xfer->setup);
 
+  // Check if device is still connected (enumerating for dev0)
+  const uint8_t daddr = xfer->daddr;
+  if (daddr == 0) {
+    TU_VERIFY(_dev0.enumerating);
+  } else {
+    const usbh_device_t* dev = get_device(daddr);
+    TU_VERIFY(dev && dev->connected);
+  }
+
   // pre-check to help reducing mutex lock
   TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
-
-  uint8_t const daddr = xfer->daddr;
-
-  // TODO probably better to use semaphore as resource management than mutex
-  usbh_lock();
+  (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
-  if (is_idle)
-  {
+  if (is_idle) {
     _ctrl_xfer.stage       = CONTROL_STAGE_SETUP;
     _ctrl_xfer.daddr       = daddr;
     _ctrl_xfer.actual_len  = 0;
 
-    _ctrl_xfer.request     = (*xfer->setup);
     _ctrl_xfer.buffer      = xfer->buffer;
     _ctrl_xfer.complete_cb = xfer->complete_cb;
     _ctrl_xfer.user_data   = xfer->user_data;
+    _usbh_epbuf.request    = (*xfer->setup);
   }
 
-  usbh_unlock();
+  (void) osal_mutex_unlock(_usbh_mutex);
 
   TU_VERIFY(is_idle);
   const uint8_t rhport = usbh_get_rhport(daddr);
 
-  TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
-  TU_LOG2_VAR(xfer->setup);
-  TU_LOG2("\r\n");
+  TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
+              (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
+                  tu_str_std_request[xfer->setup->bRequest] : "Class Request");
+  TU_LOG_BUF_USBH(xfer->setup, 8);
 
-  if (xfer->complete_cb)
-  {
-    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
-  }else
-  {
+  if (xfer->complete_cb) {
+    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_usbh_epbuf.request) );
+  }else {
     // blocking if complete callback is not provided
     // change callback to internal blocking, and result as user argument
     volatile xfer_result_t result = XFER_RESULT_INVALID;
@@ -586,19 +678,21 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
     _ctrl_xfer.user_data   = (uintptr_t) &result;
     _ctrl_xfer.complete_cb = _control_blocking_complete_cb;
 
-    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
-
-    while (result == XFER_RESULT_INVALID)
-    {
-      // only need to call task if not preempted RTOS
-      #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO
-      tuh_task();
-      #endif
+    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_usbh_epbuf.request) );
 
+    while (result == XFER_RESULT_INVALID) {
+      // Note: this can be called within an callback ie. part of tuh_task()
+      // therefore event with RTOS tuh_task() still need to be invoked
+      if (tuh_task_event_ready()) {
+        tuh_task();
+      }
       // TODO probably some timeout to prevent hanged
     }
 
-    // update transfer result
+    // update transfer result, user_data is expected to point to xfer_result_t
+    if (xfer->user_data != 0) {
+      *((xfer_result_t*) xfer->user_data) = result;
+    }
     xfer->result     = result;
     xfer->actual_len = _ctrl_xfer.actual_len;
   }
@@ -606,21 +700,18 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
-{
-  usbh_lock();
+TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) {
+  (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
   _ctrl_xfer.stage = stage;
-  usbh_unlock();
+  (void) osal_mutex_unlock(_usbh_mutex);
 }
 
-static void _xfer_complete(uint8_t daddr, xfer_result_t result)
-{
-  TU_LOG2("\r\n");
+static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) {
+  TU_LOG_USBH("\r\n");
 
   // duplicate xfer since user can execute control transfer within callback
-  tusb_control_request_t const request = _ctrl_xfer.request;
-  tuh_xfer_t xfer_temp =
-  {
+  tusb_control_request_t const request = _usbh_epbuf.request;
+  tuh_xfer_t xfer_temp = {
     .daddr       = daddr,
     .ep_addr     = 0,
     .result      = result,
@@ -631,60 +722,63 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result)
     .user_data   = _ctrl_xfer.user_data
   };
 
-  usbh_lock();
-  _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
-  usbh_unlock();
+  _set_control_xfer_stage(CONTROL_STAGE_IDLE);
 
-  if (xfer_temp.complete_cb)
-  {
+  if (xfer_temp.complete_cb) {
     xfer_temp.complete_cb(&xfer_temp);
   }
 }
 
-static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) ep_addr;
 
-  const uint8_t rhport = usbh_get_rhport(dev_addr);
-  tusb_control_request_t const * request = &_ctrl_xfer.request;
+  const uint8_t rhport = usbh_get_rhport(daddr);
+  tusb_control_request_t const * request = &_usbh_epbuf.request;
 
-  if (XFER_RESULT_SUCCESS != result)
-  {
-    TU_LOG1("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
+  if (XFER_RESULT_SUCCESS != result) {
+    TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %" PRIu32 "\r\n", rhport, daddr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    TU_LOG_BUF_USBH(request, 8);
 
     // terminate transfer if any stage failed
-    _xfer_complete(dev_addr, result);
-  }else
-  {
-    switch(_ctrl_xfer.stage)
-    {
+    _control_xfer_complete(daddr, result);
+  }else {
+    switch(_ctrl_xfer.stage) {
       case CONTROL_STAGE_SETUP:
-        if (request->wLength)
-        {
+        if (request->wLength) {
           // DATA stage: initial data toggle is always 1
           _set_control_xfer_stage(CONTROL_STAGE_DATA);
-          TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
+          TU_ASSERT( hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
           return true;
         }
         TU_ATTR_FALLTHROUGH;
 
       case CONTROL_STAGE_DATA:
-        if (request->wLength)
-        {
-          TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG2_MEM(_ctrl_xfer.buffer, xferred_bytes, 2);
+        if (request->wLength) {
+          TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, daddr);
+          TU_LOG_MEM_USBH(_ctrl_xfer.buffer, xferred_bytes, 2);
         }
 
         _ctrl_xfer.actual_len = (uint16_t) xferred_bytes;
 
         // ACK stage: toggle is always 1
         _set_control_xfer_stage(CONTROL_STAGE_ACK);
-        TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0) );
-      break;
+        TU_ASSERT( hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, 1 - request->bmRequestType_bit.direction), NULL, 0) );
+        break;
 
-      case CONTROL_STAGE_ACK:
-        _xfer_complete(dev_addr, result);
-      break;
+      case CONTROL_STAGE_ACK: {
+        // Abort all pending transfers if SET_CONFIGURATION request
+        // NOTE: should we force closing all non-control endpoints in the future?
+        if (request->bRequest == TUSB_REQ_SET_CONFIGURATION && request->bmRequestType == 0x00) {
+          for(uint8_t epnum=1; epnum<CFG_TUH_ENDPOINT_MAX; epnum++) {
+            for(uint8_t dir=0; dir<2; dir++) {
+              tuh_edpt_abort_xfer(daddr, tu_edpt_addr(epnum, dir));
+            }
+          }
+        }
+
+        _control_xfer_complete(daddr, result);
+        break;
+      }
 
       default: return false;
     }
@@ -697,17 +791,15 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 //
 //--------------------------------------------------------------------+
 
-bool tuh_edpt_xfer(tuh_xfer_t* xfer)
-{
-  uint8_t const daddr   = xfer->daddr;
+bool tuh_edpt_xfer(tuh_xfer_t* xfer) {
+  uint8_t const daddr = xfer->daddr;
   uint8_t const ep_addr = xfer->ep_addr;
 
   TU_VERIFY(daddr && ep_addr);
-
   TU_VERIFY(usbh_edpt_claim(daddr, ep_addr));
 
-  if ( !usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, (uint16_t) xfer->buflen, xfer->complete_cb, xfer->user_data) )
-  {
+  if (!usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, (uint16_t) xfer->buflen,
+                                    xfer->complete_cb, xfer->user_data)) {
     usbh_edpt_release(daddr, ep_addr);
     return false;
   }
@@ -715,69 +807,104 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer)
   return true;
 }
 
+bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) {
+  TU_LOG_USBH("[%u] Aborted transfer on EP %02X\r\n", daddr, ep_addr);
+
+  const uint8_t epnum = tu_edpt_number(ep_addr);
+  const uint8_t dir   = tu_edpt_dir(ep_addr);
+
+  if (epnum == 0) {
+    // Also include dev0 for aborting enumerating
+    const uint8_t rhport = usbh_get_rhport(daddr);
+
+    // control transfer: only 1 control at a time, check if we are aborting the current one
+    TU_VERIFY(daddr == _ctrl_xfer.daddr && _ctrl_xfer.stage != CONTROL_STAGE_IDLE);
+    hcd_edpt_abort_xfer(rhport, daddr, ep_addr);
+    _set_control_xfer_stage(CONTROL_STAGE_IDLE); // reset control transfer state to idle
+  } else {
+    usbh_device_t* dev = get_device(daddr);
+    TU_VERIFY(dev);
+
+    TU_VERIFY(dev->ep_status[epnum][dir].busy); // non-control skip if not busy
+    hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr);
+
+    // mark as ready and release endpoint if transfer is aborted
+    dev->ep_status[epnum][dir].busy = false;
+    tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex);
+  }
+
+  return true;
+}
+
 //--------------------------------------------------------------------+
 // USBH API For Class Driver
 //--------------------------------------------------------------------+
 
-uint8_t usbh_get_rhport(uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
+uint8_t usbh_get_rhport(uint8_t dev_addr) {
+  usbh_device_t *dev = get_device(dev_addr);
   return dev ? dev->rhport : _dev0.rhport;
 }
 
-uint8_t* usbh_get_enum_buf(void)
-{
-  return _usbh_ctrl_buf;
+uint8_t *usbh_get_enum_buf(void) {
+  return _usbh_epbuf.ctrl;
 }
 
-void usbh_int_set(bool enabled)
-{
-  // TODO all host controller if multiple is used
-  if (enabled)
-  {
+void usbh_int_set(bool enabled) {
+  // TODO all host controller if multiple are used since they shared the same event queue
+  if (enabled) {
     hcd_int_enable(_usbh_controller);
-  }else
-  {
+  } else {
     hcd_int_disable(_usbh_controller);
   }
 }
 
+void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) {
+  hcd_event_t event = { 0 };
+  event.event_id = USBH_EVENT_FUNC_CALL;
+  event.func_call.func = func;
+  event.func_call.param = param;
+
+  queue_event(&event, in_isr);
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
 
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
-{
+// Claim an endpoint for transfer
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr) {
+  // Note: addr0 only use tuh_control_xfer
   usbh_device_t* dev = get_device(dev_addr);
-
-  // addr0 only use tuh_control_xfer
-  TU_ASSERT(dev);
+  TU_ASSERT(dev && dev->connected);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  return tu_edpt_claim(&dev->ep_status[epnum][dir], _usbh_mutex);
+  TU_VERIFY(tu_edpt_claim(&dev->ep_status[epnum][dir], _usbh_mutex));
+  TU_LOG_USBH("[%u] Claimed EP 0x%02x\r\n", dev_addr, ep_addr);
+
+  return true;
 }
 
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
-{
+// Release an claimed endpoint due to failed transfer attempt
+bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr) {
+  // Note: addr0 only use tuh_control_xfer
   usbh_device_t* dev = get_device(dev_addr);
-
-  // addr0 only use tuh_control_xfer
-  TU_ASSERT(dev);
+  TU_VERIFY(dev && dev->connected);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  return tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex);
+  TU_VERIFY(tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex));
+  TU_LOG_USBH("[%u] Released EP 0x%02x\r\n", dev_addr, ep_addr);
+
+  return true;
 }
 
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
-                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+// Submit an transfer
+// TODO call usbh_edpt_release if failed
+bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes,
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   (void) complete_cb;
   (void) user_data;
 
@@ -785,10 +912,10 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
   TU_VERIFY(dev);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
-  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
+  TU_LOG_USBH("  Queue EP %02X with %u bytes ... \r\n", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(ep_state->busy == 0);
@@ -802,27 +929,22 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
   dev->ep_callback[epnum][dir].user_data   = user_data;
 #endif
 
-  if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
-  {
-    TU_LOG2("OK\r\n");
+  if (hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes)) {
+    TU_LOG_USBH("OK\r\n");
     return true;
-  }else
-  {
+  } else {
     // HCD error, mark endpoint as ready to allow next transfer
-    ep_state->busy    = 0;
+    ep_state->busy = 0;
     ep_state->claimed = 0;
     TU_LOG1("Failed\r\n");
-    TU_BREAKPOINT();
+//    TU_BREAKPOINT();
     return false;
   }
 }
 
-static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
-{
-  TU_LOG2("[%u:%u] Open EP0 with Size = %u\r\n", usbh_get_rhport(dev_addr), dev_addr, max_packet_size);
-
-  tusb_desc_endpoint_t ep0_desc =
-  {
+static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size) {
+  TU_LOG_USBH("[%u:%u] Open EP0 with Size = %u\r\n", usbh_get_rhport(dev_addr), dev_addr, max_packet_size);
+  tusb_desc_endpoint_t ep0_desc = {
     .bLength          = sizeof(tusb_desc_endpoint_t),
     .bDescriptorType  = TUSB_DESC_ENDPOINT,
     .bEndpointAddress = 0,
@@ -834,21 +956,18 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
   return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
 }
 
-bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
-{
-  TU_ASSERT( tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)) );
-
+bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) {
+  TU_ASSERT(tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)));
   return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep);
 }
 
-bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) {
   usbh_device_t* dev = get_device(dev_addr);
   TU_VERIFY(dev);
 
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
   return dev->ep_status[epnum][dir].busy;
 }
 
@@ -856,33 +975,38 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 // HCD Event Handler
 //--------------------------------------------------------------------+
 
-void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
-{
+void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info) {
   usbh_device_t const* dev = get_device(dev_addr);
-
-  if (dev)
-  {
-    devtree_info->rhport   = dev->rhport;
+  if (dev) {
+    devtree_info->rhport = dev->rhport;
     devtree_info->hub_addr = dev->hub_addr;
     devtree_info->hub_port = dev->hub_port;
-    devtree_info->speed    = dev->speed;
-  }else
-  {
-    devtree_info->rhport   = _dev0.rhport;
+    devtree_info->speed = dev->speed;
+  } else {
+    devtree_info->rhport = _dev0.rhport;
     devtree_info->hub_addr = _dev0.hub_addr;
     devtree_info->hub_port = _dev0.hub_port;
-    devtree_info->speed    = _dev0.speed;
+    devtree_info->speed = _dev0.speed;
   }
 }
 
-TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
-{
-  switch (event->event_id)
-  {
-    default:
-      osal_queue_send(_usbh_q, event, in_isr);
-    break;
+TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) {
+  switch (event->event_id) {
+    case HCD_EVENT_DEVICE_REMOVE:
+      // FIXME device remove from a hub need an HCD API for hcd to free up endpoint
+      // mark device as removing to prevent further xfer before the event is processed in usbh task
+
+      // Check if dev0 is removed
+      if ((event->rhport == _dev0.rhport) && (event->connection.hub_addr == _dev0.hub_addr) &&
+          (event->connection.hub_port == _dev0.hub_port)) {
+        _dev0.enumerating = 0;
+      }
+      break;
+
+    default: break;
   }
+
+  queue_event(event, in_isr);
 }
 
 //--------------------------------------------------------------------+
@@ -890,14 +1014,11 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
 //--------------------------------------------------------------------+
 
 // generic helper to get a descriptor
-// if blocking, user_data could be pointed to xfer_result
+// if blocking, user_data is pointed to xfer_result
 static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                            tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
+                            tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_DEVICE,
       .type      = TUSB_REQ_TYPE_STANDARD,
       .direction = TUSB_DIR_IN
@@ -907,9 +1028,7 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
     .wIndex   = tu_htole16(language_id),
     .wLength  = tu_htole16(len)
   };
-
-  tuh_xfer_t xfer =
-  {
+  tuh_xfer_t xfer = {
     .daddr       = daddr,
     .ep_addr     = 0,
     .setup       = &request,
@@ -918,41 +1037,29 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
     .user_data   = user_data
   };
 
-  bool const ret = tuh_control_xfer(&xfer);
-
-  // if blocking, user_data could be pointed to xfer_result
-  if ( !complete_cb && user_data )
-  {
-    *((xfer_result_t*) user_data) = xfer.result;
-  }
-
-  return ret;
+  return tuh_control_xfer(&xfer);
 }
 
 bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
-                        tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                        tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return _get_descriptor(daddr, type, index, 0x0000, buffer, len, complete_cb, user_data);
 }
 
 bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   len = tu_min16(len, sizeof(tusb_desc_device_t));
   return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb, user_data);
 }
 
 bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
-                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb, user_data);
 }
 
 //------------- String Descriptor -------------//
 
 bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return _get_descriptor(daddr, TUSB_DESC_STRING, index, language_id, buffer, len, complete_cb, user_data);
 }
 
@@ -967,8 +1074,7 @@ bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id,
 
 // Get product string descriptor
 bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                       tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                                       tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_product);
   return tuh_descriptor_get_string(daddr, dev->i_product, language_id, buffer, len, complete_cb, user_data);
@@ -976,81 +1082,87 @@ bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void
 
 // Get serial string descriptor
 bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_serial);
   return tuh_descriptor_get_string(daddr, dev->i_serial, language_id, buffer, len, complete_cb, user_data);
 }
 
 // Get HID report descriptor
-// if blocking, user_data could be pointed to xfer_result
+// if blocking, user_data is pointed to xfer_result
 bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
-                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  TU_LOG2("HID Get Report Descriptor\r\n");
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = tu_htole16(TU_U16(desc_type, index)),
-    .wIndex   = tu_htole16((uint16_t) itf_num),
-    .wLength  = len
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_USBH("HID Get Report Descriptor\r\n");
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_STANDARD,
+          .direction = TUSB_DIR_IN
+      },
+      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+      .wValue   = tu_htole16(TU_U16(desc_type, index)),
+      .wIndex   = tu_htole16((uint16_t) itf_num),
+      .wLength  = len
+  };
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = buffer,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = buffer,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
-  };
-
-  bool const ret = tuh_control_xfer(&xfer);
-
-  // if blocking, user_data could be pointed to xfer_result
-  if ( !complete_cb && user_data )
-  {
-    *((xfer_result_t*) user_data) = xfer.result;
-  }
-
-  return ret;
+  return tuh_control_xfer(&xfer);
 }
 
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
-                           tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  TU_LOG2("Set Configuration = %d\r\n", config_num);
-
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = TUSB_REQ_SET_CONFIGURATION,
-    .wValue   = tu_htole16(config_num),
-    .wIndex   = 0,
-    .wLength  = 0
+                           tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_USBH("Set Configuration = %d\r\n", config_num);
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_DEVICE,
+          .type      = TUSB_REQ_TYPE_STANDARD,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = TUSB_REQ_SET_CONFIGURATION,
+      .wValue   = tu_htole16(config_num),
+      .wIndex   = 0,
+      .wLength  = 0
+  };
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
+  return tuh_control_xfer(&xfer);
+}
+
+bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
+                       tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_USBH("Set Interface %u Alternate %u\r\n", itf_num, itf_alt);
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_STANDARD,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = TUSB_REQ_SET_INTERFACE,
+      .wValue   = tu_htole16(itf_alt),
+      .wIndex   = tu_htole16(itf_num),
+      .wLength  = 0
+  };
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
   };
 
   return tuh_control_xfer(&xfer);
@@ -1065,109 +1177,147 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
   TU_VERIFY(_async_func(__VA_ARGS__, NULL, (uintptr_t) &result), XFER_RESULT_TIMEOUT); \
   return (uint8_t) result
 
-uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index,
+                                void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get, daddr, type, index, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_device, daddr, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index,
+                                              void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_configuration, daddr, index, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index,
+                                           void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_hid_report, daddr, itf_num, desc_type, index, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id,
+                                       void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_string, daddr, index, language_id, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id,
+                                                    void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_manufacturer_string, daddr, language_id, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id,
+                                               void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_product_string, daddr, language_id, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id,
+                                              void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_serial_string, daddr, language_id, buffer, len);
 }
 
 //--------------------------------------------------------------------+
-//
+// Detaching
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE
-static inline bool is_hub_addr(uint8_t daddr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) {
   return (CFG_TUH_HUB > 0) && (daddr > CFG_TUH_DEVICE_MAX);
 }
 
+//static void mark_removing_device_isr(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) {
+//  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) {
+//    usbh_device_t *dev = &_usbh_devices[dev_id];
+//    uint8_t const daddr = dev_id + 1;
+//
+//    // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
+//    if (dev->rhport == rhport && dev->connected &&
+//        (hub_addr == 0 || dev->hub_addr == hub_addr) &&
+//        (hub_port == 0 || dev->hub_port == hub_port)) {
+//      if (is_hub_addr(daddr)) {
+//        // If the device itself is a usb hub, mark all downstream devices.
+//        // FIXME recursive calls
+//        mark_removing_device_isr(rhport, daddr, 0);
+//      }
+//
+//      dev->removing = 1;
+//    }
+//  }
+//}
+
 // a device unplugged from rhport:hub_addr:hub_port
-static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
-{
+static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) {
   //------------- find the all devices (star-network) under port that is unplugged -------------//
   // TODO mark as disconnected in ISR, also handle dev0
-  for ( uint8_t dev_id = 0; dev_id < TU_ARRAY_SIZE(_usbh_devices); dev_id++ )
-  {
-    usbh_device_t* dev = &_usbh_devices[dev_id];
-    uint8_t const dev_addr = dev_id+1;
+  uint32_t removing_hubs = 0;
+  do {
+    for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) {
+      usbh_device_t* dev = &_usbh_devices[dev_id];
+      uint8_t const daddr = dev_id + 1;
 
-    // TODO Hub multiple level
-    if (dev->rhport == rhport   &&
-        (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr = 0 means roothub
-        (hub_port == 0 || dev->hub_port == hub_port) && // hub_port = 0 means all devices of downstream hub
-        dev->connected)
-    {
-      TU_LOG2("  Address = %u\r\n", dev_addr);
+      // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
+      if (dev->rhport == rhport && dev->connected &&
+          (hub_addr == 0 || dev->hub_addr == hub_addr) &&
+          (hub_port == 0 || dev->hub_port == hub_port)) {
+        TU_LOG_USBH("[%u:%u:%u] unplugged address = %u\r\n", rhport, hub_addr, hub_port, daddr);
 
-      if (is_hub_addr(dev_addr))
-      {
-        TU_LOG(USBH_DBG_LVL, "HUB address = %u is unmounted\r\n", dev_addr);
-        // If the device itself is a usb hub, unplug downstream devices.
-        // FIXME un-roll recursive calls to prevent potential stack overflow
-        process_device_unplugged(rhport, dev_addr, 0);
-      }else
-      {
-        // Invoke callback before closing driver
-        if (tuh_umount_cb) tuh_umount_cb(dev_addr);
+        if (is_hub_addr(daddr)) {
+          TU_LOG_USBH("  is a HUB device %u\r\n", daddr);
+          removing_hubs |= TU_BIT(dev_id - CFG_TUH_DEVICE_MAX);
+        } else {
+          // Invoke callback before closing driver (maybe call it later ?)
+          if (tuh_umount_cb) tuh_umount_cb(daddr);
+        }
+
+        // Close class driver
+        for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+          usbh_class_driver_t const* driver = get_driver(drv_id);
+          if (driver) driver->close(daddr);
+        }
+
+        hcd_device_close(rhport, daddr);
+        clear_device(dev);
+
+        // abort on-going control xfer on this device if any
+        if (_ctrl_xfer.daddr == daddr) _set_control_xfer_stage(CONTROL_STAGE_IDLE);
       }
-
-      // Close class driver
-      for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
-      {
-        TU_LOG2("%s close\r\n", usbh_class_drivers[drv_id].name);
-        usbh_class_drivers[drv_id].close(dev_addr);
-      }
-
-      hcd_device_close(rhport, dev_addr);
-      clear_device(dev);
-      // abort on-going control xfer if any
-      if (_ctrl_xfer.daddr == dev_addr) _set_control_xfer_stage(CONTROL_STAGE_IDLE);
     }
-  }
+
+    // if removing a hub, we need to remove its downstream devices
+    #if CFG_TUH_HUB
+    if (removing_hubs == 0) break;
+
+    // find a marked hub to process
+    for (uint8_t h_id = 0; h_id < CFG_TUH_HUB; h_id++) {
+      if (tu_bit_test(removing_hubs, h_id)) {
+        removing_hubs &= ~TU_BIT(h_id);
+
+        // update hub_addr and hub_port for next loop
+        hub_addr = h_id + 1 + CFG_TUH_DEVICE_MAX;
+        hub_port = 0;
+        break;
+      }
+    }
+    #else
+    (void) removing_hubs;
+    break;
+    #endif
+  } while(1);
 }
 
 //--------------------------------------------------------------------+
 // Enumeration Process
 // is a lengthy process with a series of control transfer to configure
 // newly attached device.
-// NOTE: due to the shared _usbh_ctrl_buf, we must complete enumerating
+// NOTE: due to the shared control buffer, we must complete enumerating
 // one device before enumerating another one.
 //--------------------------------------------------------------------+
 
+enum {
+  ENUM_RESET_DELAY_MS = 50,       // USB specs: 10 to 50ms
+  ENUM_DEBOUNCING_DELAY_MS = 450, // when plug/unplug a device, physical connection can be bouncing and may
+                                  // generate a series of attach/detach event. This delay wait for stable connection
+};
+
 enum {
   ENUM_IDLE,
   ENUM_RESET_1,         // 1st reset when attached
@@ -1191,329 +1341,345 @@ static bool _parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configu
 static void enum_full_complete(void);
 
 // process device enumeration
-static void process_enumeration(tuh_xfer_t* xfer)
-{
-  if (XFER_RESULT_SUCCESS != xfer->result)
-  {
-    // stop enumeration, maybe we could retry this
-    enum_full_complete();
+static void process_enumeration(tuh_xfer_t* xfer) {
+  // Retry a few times with transfers in enumeration since device can be unstable when starting up
+  enum {
+    ATTEMPT_COUNT_MAX = 3,
+    ATTEMPT_DELAY_MS = 100
+  };
+  static uint8_t failed_count = 0;
+
+  if (XFER_RESULT_SUCCESS != xfer->result) {
+    // retry if not reaching max attempt
+    bool retry = _dev0.enumerating && (failed_count < ATTEMPT_COUNT_MAX);
+    if ( retry ) {
+      failed_count++;
+      tusb_time_delay_ms_api(ATTEMPT_DELAY_MS); // delay a bit
+      TU_LOG1("Enumeration attempt %u\r\n", failed_count);
+      retry = tuh_control_xfer(xfer);
+    }
+
+    if (!retry) {
+      enum_full_complete();
+    }
+
     return;
   }
+  failed_count = 0;
 
   uint8_t const daddr = xfer->daddr;
   uintptr_t const state = xfer->user_data;
 
-  switch(state)
-  {
-#if CFG_TUH_HUB
+  switch (state) {
+    #if CFG_TUH_HUB
     //case ENUM_HUB_GET_STATUS_1: break;
 
-    case ENUM_HUB_CLEAR_RESET_1:
-    {
+    case ENUM_HUB_CLEAR_RESET_1: {
       hub_port_status_response_t port_status;
-      memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
+      memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t));
 
-      if ( !port_status.status.connection )
-      {
+      if (!port_status.status.connection) {
         // device unplugged while delaying, nothing else to do
         enum_full_complete();
         return;
       }
 
       _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
-                    (port_status.status.low_speed ) ? TUSB_SPEED_LOW  : TUSB_SPEED_FULL;
+                    (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
 
       // Acknowledge Port Reset Change
-      if (port_status.change.reset)
-      {
-        hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_ADDR0_DEVICE_DESC);
+      if (port_status.change.reset) {
+        hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port,
+                                    process_enumeration, ENUM_ADDR0_DEVICE_DESC);
       }
+      break;
     }
-    break;
 
     case ENUM_HUB_GET_STATUS_2:
-      osal_task_delay(RESET_DELAY);
-      TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2), );
-    break;
+      tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS);
+      TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl,
+                                    process_enumeration, ENUM_HUB_CLEAR_RESET_2),);
+      break;
 
-    case ENUM_HUB_CLEAR_RESET_2:
-    {
+    case ENUM_HUB_CLEAR_RESET_2: {
       hub_port_status_response_t port_status;
-      memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
+      memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t));
 
       // Acknowledge Port Reset Change if Reset Successful
-      if (port_status.change.reset)
-      {
-        TU_ASSERT( hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_SET_ADDR), );
+      if (port_status.change.reset) {
+        TU_ASSERT(hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port,
+                                              process_enumeration, ENUM_SET_ADDR),);
       }
+      break;
     }
-    break;
-#endif
+    #endif
 
-    case ENUM_ADDR0_DEVICE_DESC:
-    {
+    case ENUM_ADDR0_DEVICE_DESC: {
       // TODO probably doesn't need to open/close each enumeration
       uint8_t const addr0 = 0;
-      TU_ASSERT( usbh_edpt_control_open(addr0, 8), );
+      TU_ASSERT(usbh_edpt_control_open(addr0, 8),);
 
       // Get first 8 bytes of device descriptor for Control Endpoint size
-      TU_LOG2("Get 8 byte of Device Descriptor\r\n");
-      TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, process_enumeration, ENUM_SET_ADDR), );
+      TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n");
+      TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_epbuf.ctrl, 8,
+                                          process_enumeration, ENUM_SET_ADDR),);
+      break;
     }
-    break;
 
 #if 0
-    case ENUM_RESET_2:
-      // TODO not used by now, but may be needed for some devices !?
-      // Reset device again before Set Address
-      TU_LOG2("Port reset2 \r\n");
-      if (_dev0.hub_addr == 0)
-      {
-        // connected directly to roothub
-        hcd_port_reset( _dev0.rhport );
-        osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
-                                      // sof of controller may not running while reseting
-        hcd_port_reset_end(_dev0.rhport);
-        // TODO: fall through to SET ADDRESS, refactor later
-      }
-      #if CFG_TUH_HUB
-      else
-      {
-        // after RESET_DELAY the hub_port_reset() already complete
-        TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_HUB_GET_STATUS_2), );
-        break;
-      }
-      #endif
-      __attribute__((fallthrough));
+      case ENUM_RESET_2:
+        // TODO not used by now, but may be needed for some devices !?
+        // Reset device again before Set Address
+        TU_LOG_USBH("Port reset2 \r\n");
+        if (_dev0.hub_addr == 0) {
+          // connected directly to roothub
+          hcd_port_reset( _dev0.rhport );
+          tusb_time_delay_ms_api(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
+                                        // sof of controller may not running while resetting
+          hcd_port_reset_end(_dev0.rhport);
+          // TODO: fall through to SET ADDRESS, refactor later
+        }
+#if CFG_TUH_HUB
+        else {
+          // after RESET_DELAY the hub_port_reset() already complete
+          TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port,
+                                    process_enumeration, ENUM_HUB_GET_STATUS_2), );
+          break;
+        }
+#endif
+        TU_ATTR_FALLTHROUGH;
 #endif
 
     case ENUM_SET_ADDR:
       enum_request_set_addr();
-    break;
+      break;
 
-    case ENUM_GET_DEVICE_DESC:
-    {
-      uint8_t const new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue);
+    case ENUM_GET_DEVICE_DESC: {
+      // Allow 2ms for address recovery time, Ref USB Spec 9.2.6.3
+      tusb_time_delay_ms_api(2);
+
+      const uint8_t new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue);
 
       usbh_device_t* new_dev = get_device(new_addr);
-      TU_ASSERT(new_dev, );
+      TU_ASSERT(new_dev,);
       new_dev->addressed = 1;
 
       // Close device 0
       hcd_device_close(_dev0.rhport, 0);
 
       // open control pipe for new address
-      TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size), );
+      TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->ep0_size),);
 
       // Get full device descriptor
-      TU_LOG2("Get Device Descriptor\r\n");
-      TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC), );
+      TU_LOG_USBH("Get Device Descriptor\r\n");
+      TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t),
+                                          process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC),);
+      break;
     }
-    break;
 
-    case ENUM_GET_9BYTE_CONFIG_DESC:
-    {
-      tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+    case ENUM_GET_9BYTE_CONFIG_DESC: {
+      tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl;
       usbh_device_t* dev = get_device(daddr);
-      TU_ASSERT(dev, );
+      TU_ASSERT(dev,);
 
-      dev->vid            = desc_device->idVendor;
-      dev->pid            = desc_device->idProduct;
+      dev->vid = desc_device->idVendor;
+      dev->pid = desc_device->idProduct;
       dev->i_manufacturer = desc_device->iManufacturer;
-      dev->i_product      = desc_device->iProduct;
-      dev->i_serial       = desc_device->iSerialNumber;
+      dev->i_product = desc_device->iProduct;
+      dev->i_serial = desc_device->iSerialNumber;
 
       if (tuh_desc_device_cb) tuh_desc_device_cb(daddr, (tusb_desc_device_t const*) _usbh_ctrl_buf);
 
       // Get 9-byte for total length
       uint8_t const config_idx = CONFIG_NUM - 1;
-      TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
-      TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC), );
+      TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n");
+      TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9,
+                                                 process_enumeration, ENUM_GET_FULL_CONFIG_DESC),);
+      break;
     }
-    break;
 
-    case ENUM_GET_FULL_CONFIG_DESC:
-    {
-      uint8_t const * desc_config = _usbh_ctrl_buf;
+    case ENUM_GET_FULL_CONFIG_DESC: {
+      uint8_t const* desc_config = _usbh_epbuf.ctrl;
 
       // Use offsetof to avoid pointer to the odd/misaligned address
-      uint16_t const total_len = tu_le16toh( tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
+      uint16_t const total_len = tu_le16toh(
+          tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)));
 
       // TODO not enough buffer to hold configuration descriptor
-      TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE, );
+      TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE,);
 
       // Get full configuration descriptor
       uint8_t const config_idx = CONFIG_NUM - 1;
-      TU_LOG2("Get Configuration[0] Descriptor\r\n");
-      TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG), );
+      TU_LOG_USBH("Get Configuration[0] Descriptor\r\n");
+      TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, total_len,
+                                                 process_enumeration, ENUM_SET_CONFIG),);
+      break;
     }
-    break;
 
     case ENUM_SET_CONFIG:
-      // Got the whole configuration descriptor. Make a copy
       if (tuh_desc_config_cb) tuh_desc_config_cb(daddr, (const tusb_desc_configuration_t*) _usbh_ctrl_buf);
 
-      // Parse configuration & set up drivers
-      // Driver open aren't allowed to make any usb transfer yet
-      TU_ASSERT( _parse_configuration_descriptor(daddr, (const tusb_desc_configuration_t*  ) _usbh_ctrl_buf), );
+      TU_ASSERT(tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER),);
+      break;
 
-      TU_ASSERT( tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER), );
-    break;
-
-    case ENUM_CONFIG_DRIVER:
-    {
-      TU_LOG2("Device configured\r\n");
+    case ENUM_CONFIG_DRIVER: {
+      TU_LOG_USBH("Device configured\r\n");
       usbh_device_t* dev = get_device(daddr);
-      TU_ASSERT(dev, );
+      TU_ASSERT(dev,);
 
       dev->configured = 1;
 
-      // Start the Set Configuration process for interfaces (itf = DRVID_INVALID)
+      // Parse configuration & set up drivers
+      // driver_open() must not make any usb transfer
+      TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),);
+
+      // Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8)
       // Since driver can perform control transfer within its set_config, this is done asynchronously.
       // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
-      // TODO use separated API instead of using DRVID_INVALID
-      usbh_driver_set_config_complete(daddr, DRVID_INVALID);
+      // TODO use separated API instead of using TUSB_INDEX_INVALID_8
+      usbh_driver_set_config_complete(daddr, TUSB_INDEX_INVALID_8);
+      break;
     }
-    break;
 
     default:
       // stop enumeration if unknown state
       enum_full_complete();
-    break;
+      break;
   }
 }
 
-static bool enum_new_device(hcd_event_t* event)
-{
-  _dev0.rhport   = event->rhport;
+
+
+static bool enum_new_device(hcd_event_t* event) {
+  _dev0.rhport = event->rhport;
   _dev0.hub_addr = event->connection.hub_addr;
   _dev0.hub_port = event->connection.hub_port;
 
-  if (_dev0.hub_addr == 0)
-  {
-    // connected/disconnected directly with roothub
-    // wait until device is stable TODO non blocking
+  if (_dev0.hub_addr == 0) {
+    // connected directly to roothub
     hcd_port_reset(_dev0.rhport);
-    osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
-                                  // sof of controller may not running while reseting
-    hcd_port_reset_end( _dev0.rhport);
+
+    // Since we are in middle of rhport reset, frame number is not available yet.
+    // need to depend on tusb_time_millis_api()
+    tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS);
+
+    hcd_port_reset_end(_dev0.rhport);
+
+    // wait until device connection is stable TODO non blocking
+    tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS);
 
     // device unplugged while delaying
-    if ( !hcd_port_connect_status(_dev0.rhport) ) return true;
+    if (!hcd_port_connect_status(_dev0.rhport)) {
+      enum_full_complete();
+      return true;
+    }
 
-    _dev0.speed = hcd_port_speed_get(_dev0.rhport );
-    TU_LOG2("%s Speed\r\n", tu_str_speed[_dev0.speed]);
+    _dev0.speed = hcd_port_speed_get(_dev0.rhport);
+    TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_dev0.speed]);
 
     // fake transfer to kick-off the enumeration process
     tuh_xfer_t xfer;
-    xfer.daddr     = 0;
-    xfer.result    = XFER_RESULT_SUCCESS;
+    xfer.daddr = 0;
+    xfer.result = XFER_RESULT_SUCCESS;
     xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
 
     process_enumeration(&xfer);
-
   }
 #if CFG_TUH_HUB
-  else
-  {
-    // connected/disconnected via external hub
-    // wait until device is stable
-    osal_task_delay(RESET_DELAY);
+  else {
+    // connected via external hub
+    // wait until device connection is stable TODO non blocking
+    tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS);
 
     // ENUM_HUB_GET_STATUS
-    //TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete, 0) );
-    TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_1) );
+    TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl,
+                                  process_enumeration, ENUM_HUB_CLEAR_RESET_1));
   }
 #endif // hub
 
   return true;
 }
 
-static uint8_t get_new_address(bool is_hub)
-{
+static uint8_t get_new_address(bool is_hub) {
   uint8_t start;
   uint8_t end;
-  if ( is_hub )
-  {
+
+  if ( is_hub ) {
     start = CFG_TUH_DEVICE_MAX;
     end   = start + CFG_TUH_HUB;
-  }else
-  {
+  }else {
     start = 0;
     end   = start + CFG_TUH_DEVICE_MAX;
   }
 
-  for ( uint8_t idx = start; idx < end; idx++)
-  {
+  for (uint8_t idx = start; idx < end; idx++) {
     if (!_usbh_devices[idx].connected) return (idx+1);
   }
 
   return 0; // invalid address
 }
 
-static bool enum_request_set_addr(void)
-{
-  tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+static bool enum_request_set_addr(void) {
+  tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl;
 
   // Get new address
   uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
   TU_ASSERT(new_addr != 0);
-
-  TU_LOG2("Set Address = %d\r\n", new_addr);
+  TU_LOG_USBH("Set Address = %d\r\n", new_addr);
 
   usbh_device_t* new_dev = get_device(new_addr);
-
-  new_dev->rhport    = _dev0.rhport;
-  new_dev->hub_addr  = _dev0.hub_addr;
-  new_dev->hub_port  = _dev0.hub_port;
-  new_dev->speed     = _dev0.speed;
+  new_dev->rhport = _dev0.rhport;
+  new_dev->hub_addr = _dev0.hub_addr;
+  new_dev->hub_port = _dev0.hub_port;
+  new_dev->speed = _dev0.speed;
   new_dev->connected = 1;
-  new_dev->ep0_size  = desc_device->bMaxPacketSize0;
+  new_dev->ep0_size = desc_device->bMaxPacketSize0;
 
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = TUSB_REQ_SET_ADDRESS,
-    .wValue   = tu_htole16(new_addr),
-    .wIndex   = 0,
-    .wLength  = 0
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_DEVICE,
+          .type      = TUSB_REQ_TYPE_STANDARD,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = TUSB_REQ_SET_ADDRESS,
+      .wValue   = tu_htole16(new_addr),
+      .wIndex   = 0,
+      .wLength  = 0
+  };
+  tuh_xfer_t xfer = {
+      .daddr       = 0, // dev0
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = process_enumeration,
+      .user_data   = ENUM_GET_DEVICE_DESC
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = 0, // dev0
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = process_enumeration,
-    .user_data   = ENUM_GET_DEVICE_DESC
-  };
-
-  TU_ASSERT( tuh_control_xfer(&xfer) );
-
+  TU_ASSERT(tuh_control_xfer(&xfer));
   return true;
 }
 
-static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
-{
+static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) {
   usbh_device_t* dev = get_device(dev_addr);
-
-  uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
+  uint16_t const total_len = tu_le16toh(desc_cfg->wTotalLength);
+  uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + total_len;
   uint8_t const* p_desc   = tu_desc_next(desc_cfg);
 
+  TU_LOG_USBH("Parsing Configuration descriptor (wTotalLength = %u)\r\n", total_len);
+
   // parse each interfaces
-  while( p_desc < desc_end )
-  {
+  while( p_desc < desc_end ) {
+    if ( 0 == tu_desc_len(p_desc) ) {
+      // A zero length descriptor indicates that the device is off spec (e.g. wrong wTotalLength).
+      // Parsed interfaces should still be usable
+      TU_LOG_USBH("Encountered a zero-length descriptor after %u bytes\r\n", (uint32_t)p_desc - (uint32_t)desc_cfg);
+      break;
+    }
+
     uint8_t assoc_itf_count = 1;
 
     // Class will always starts with Interface Association (if any) and then Interface descriptor
-    if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
-    {
+    if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) {
       tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
       assoc_itf_count = desc_iad->bInterfaceCount;
 
@@ -1529,12 +1695,21 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
 
 #if CFG_TUH_MIDI
     // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD
-    // manually increase the associated count
+    // manually force associated count = 2
     if (1                              == assoc_itf_count              &&
         TUSB_CLASS_AUDIO               == desc_itf->bInterfaceClass    &&
         AUDIO_SUBCLASS_CONTROL         == desc_itf->bInterfaceSubClass &&
-        AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol)
-    {
+        AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) {
+      assoc_itf_count = 2;
+    }
+#endif
+
+#if CFG_TUH_CDC
+    // Some legacy CDC device does not use IAD but rather use device class as hint to combine 2 interfaces
+    // manually force associated count = 2
+    if (1                                        == assoc_itf_count              &&
+        TUSB_CLASS_CDC                           == desc_itf->bInterfaceClass    &&
+        CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == desc_itf->bInterfaceSubClass) {
       assoc_itf_count = 2;
     }
 #endif
@@ -1543,23 +1718,18 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     // Find driver for this interface
-    uint8_t drv_id;
-    for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
-    {
-      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
-
-      if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
-      {
+    for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+      usbh_class_driver_t const * driver = get_driver(drv_id);
+      if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) {
         // open successfully
-        TU_LOG2("  %s opened\r\n", driver->name);
+        TU_LOG_USBH("  %s opened\r\n", driver->name);
 
         // bind (associated) interfaces to found driver
-        for(uint8_t i=0; i<assoc_itf_count; i++)
-        {
+        for(uint8_t i=0; i<assoc_itf_count; i++) {
           uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
 
           // Interface number must not be used already
-          TU_ASSERT( DRVID_INVALID == dev->itf2drv[itf_num] );
+          TU_ASSERT( TUSB_INDEX_INVALID_8 == dev->itf2drv[itf_num] );
           dev->itf2drv[itf_num] = drv_id;
         }
 
@@ -1569,10 +1739,9 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
         break; // exit driver find loop
       }
 
-      if( drv_id >= USBH_CLASS_DRIVER_COUNT )
-      {
-        TU_LOG(USBH_DBG_LVL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
-               desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
+      if ( drv_id == TOTAL_DRIVER_COUNT - 1 ) {
+        TU_LOG_USBH("[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+               dev->rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
       }
     }
 
@@ -1583,42 +1752,39 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
   return true;
 }
 
-void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
-{
+void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) {
   usbh_device_t* dev = get_device(dev_addr);
 
-  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++)
-  {
+  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++) {
     // continue with next valid interface
-    // TODO skip IAD binding interface such as CDCs
+    // IAD binding interface such as CDCs should return itf_num + 1 when complete
+    // with usbh_driver_set_config_complete()
     uint8_t const drv_id = dev->itf2drv[itf_num];
-    if (drv_id != DRVID_INVALID)
-    {
-      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
-      TU_LOG2("%s set config: itf = %u\r\n", driver->name, itf_num);
+    usbh_class_driver_t const * driver = get_driver(drv_id);
+    if (driver) {
+      TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);
       driver->set_config(dev_addr, itf_num);
       break;
     }
   }
 
   // all interface are configured
-  if (itf_num == CFG_TUH_INTERFACE_MAX)
-  {
+  if (itf_num == CFG_TUH_INTERFACE_MAX) {
     enum_full_complete();
 
-    if (is_hub_addr(dev_addr))
-    {
-      TU_LOG(USBH_DBG_LVL, "HUB address = %u is mounted\r\n", dev_addr);
-    }else
-    {
+    if (is_hub_addr(dev_addr)) {
+      TU_LOG_USBH("HUB address = %u is mounted\r\n", dev_addr);
+    }else {
       // Invoke callback if available
       if (tuh_mount_cb) tuh_mount_cb(dev_addr);
     }
   }
 }
 
-static void enum_full_complete(void)
-{
+static void enum_full_complete(void) {
+  // mark enumeration as complete
+  _dev0.enumerating = 0;
+
 #if CFG_TUH_HUB
   // get next hub status
   if (_dev0.hub_addr) hub_edpt_status_xfer(_dev0.hub_addr);
diff --git a/src/host/usbh.h b/src/host/usbh.h
index b39d1f205..500b044f8 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -47,18 +47,17 @@ typedef void (*tuh_xfer_cb_t)(tuh_xfer_t* xfer);
 // it is advised to initialize it using member name
 // Note2: not all field is available/meaningful in callback,
 // some info is not saved by usbh to save SRAM
-struct tuh_xfer_s
-{
+struct tuh_xfer_s {
   uint8_t daddr;
   uint8_t ep_addr;
-
+  uint8_t TU_RESERVED;      // reserved
   xfer_result_t result;
+
   uint32_t actual_len;      // excluding setup packet
 
-  union
-  {
+  union {
     tusb_control_request_t const* setup; // setup packet pointer if control transfer
-    uint32_t buflen;        // expected length if not control transfer (not available in callback)
+    uint32_t buflen;                     // expected length if not control transfer (not available in callback)
   };
 
   uint8_t* buffer;           // not available in callback if not control transfer
@@ -68,12 +67,31 @@ struct tuh_xfer_s
   // uint32_t timeout_ms;    // place holder, not supported yet
 };
 
-// ConfigID for tuh_config()
-enum
-{
-  TUH_CFGID_RPI_PIO_USB_CONFIGURATION = OPT_MCU_RP2040 << 8 // cfg_param: pio_usb_configuration_t
+// Subject to change
+typedef struct {
+  uint8_t daddr;
+  tusb_desc_interface_t desc;
+} tuh_itf_info_t;
+
+// ConfigID for tuh_configure()
+enum {
+  TUH_CFGID_INVALID = 0,
+  TUH_CFGID_RPI_PIO_USB_CONFIGURATION = 100, // cfg_param: pio_usb_configuration_t
+  TUH_CFGID_MAX3421 = 200,
 };
 
+typedef struct {
+  uint8_t max_nak; // max NAK per endpoint per frame to save CPU/SPI bus usage
+  uint8_t cpuctl; // R16: CPU Control Register
+  uint8_t pinctl; // R17: Pin Control Register. FDUPSPI bit is ignored
+} tuh_configure_max3421_t;
+
+typedef union {
+  // For TUH_CFGID_RPI_PIO_USB_CONFIGURATION use pio_usb_configuration_t
+
+  tuh_configure_max3421_t max3421;
+} tuh_configure_param_t;
+
 //--------------------------------------------------------------------+
 // APPLICATION CALLBACK
 //--------------------------------------------------------------------+
@@ -84,12 +102,18 @@ TU_ATTR_WEAK void tuh_desc_device_cb(uint8_t daddr, const tusb_desc_device_t *de
 // Give the application an opportunity to grab the configuration descriptor
 TU_ATTR_WEAK void tuh_desc_config_cb(uint8_t daddr, const tusb_desc_configuration_t *desc_config);
 
-// Invoked when device is mounted (configured)
+// Invoked when a device is mounted (configured)
 TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
 
-/// Invoked when device is unmounted (bus reset/unplugged)
+// Invoked when a device failed to mount during enumeration process
+// TU_ATTR_WEAK void tuh_mount_failed_cb (uint8_t daddr);
+
+// Invoked when a device is unmounted (detached)
 TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 
+// Invoked when there is a new usb event, which need to be processed by tuh_task()/tuh_task_ext()
+void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
+
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
@@ -98,12 +122,28 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 // Should be called before tuh_init()
 // - cfg_id   : configure ID (TBD)
 // - cfg_param: configure data, structure depends on the ID
-bool tuh_configure(uint8_t controller_id, uint32_t cfg_id, const void* cfg_param);
+bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
+
+// New API to replace tuh_init() to init host stack on specific roothub port
+bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
 
 // Init host stack
-bool tuh_init(uint8_t controller_id);
+#if TUSB_VERSION_NUMBER > 2000  // 0.20.0
+TU_ATTR_DEPRECATED("Please use tusb_init(rhport, rh_init) instead")
+#endif
+TU_ATTR_ALWAYS_INLINE static inline bool tuh_init(uint8_t rhport) {
+  const tusb_rhport_init_t rh_init = {
+    .role = TUSB_ROLE_HOST,
+    .speed = TUH_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL,
+  };
+  return tuh_rhport_init(rhport, &rh_init);
+}
 
-// Check if host stack is already initialized
+// Deinit host stack on rhport
+bool tuh_deinit(uint8_t rhport);
+
+// Check if host stack is already initialized with any roothub ports
+// To check if an rhport is initialized, use tuh_rhport_is_active()
 bool tuh_inited(void);
 
 // Task function should be called in main/rtos loop, extended version of tuh_task()
@@ -113,20 +153,37 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr);
 
 // Task function should be called in main/rtos loop
 TU_ATTR_ALWAYS_INLINE static inline
-void tuh_task(void)
-{
+void tuh_task(void) {
   tuh_task_ext(UINT32_MAX, false);
 }
 
+// Check if there is pending events need processing by tuh_task()
+bool tuh_task_event_ready(void);
+
 #ifndef _TUSB_HCD_H_
-extern void hcd_int_handler(uint8_t rhport);
+extern void hcd_int_handler(uint8_t rhport, bool in_isr);
 #endif
 
-// Interrupt handler, name alias to HCD
-#define tuh_int_handler   hcd_int_handler
+// Interrupt handler alias to HCD with in_isr as optional parameter
+#define _tuh_int_handler_arg0()                   TU_VERIFY_STATIC(false, "tuh_int_handler() must have 1 or 2 arguments")
+#define _tuh_int_handler_arg1(_rhport)            hcd_int_handler(_rhport, true)
+#define _tuh_int_handler_arg2(_rhport, _in_isr)   hcd_int_handler(_rhport, _in_isr)
+#define tuh_int_handler(...)   TU_FUNC_OPTIONAL_ARG(_tuh_int_handler, __VA_ARGS__)
 
+// Check if roothub port is initialized and active as a host
+bool tuh_rhport_is_active(uint8_t rhport);
+
+// Assert/de-assert Bus Reset signal to roothub port. USB specs: it should last 10-50ms
+bool tuh_rhport_reset_bus(uint8_t rhport, bool active);
+
+//--------------------------------------------------------------------+
+// Device API
+//--------------------------------------------------------------------+
+
+// Get VID/PID of device
 bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid);
 
+// Get speed of device
 tusb_speed_t tuh_speed_get(uint8_t daddr);
 
 // Check if device is connected and configured
@@ -134,8 +191,7 @@ bool tuh_mounted(uint8_t daddr);
 
 // Check if device is suspended
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_suspended(uint8_t daddr)
-{
+bool tuh_suspended(uint8_t daddr) {
   // TODO implement suspend & resume on host
   (void) daddr;
   return false;
@@ -143,8 +199,7 @@ bool tuh_suspended(uint8_t daddr)
 
 // Check if device is ready to communicate with
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_ready(uint8_t daddr)
-{
+bool tuh_ready(uint8_t daddr) {
   return tuh_mounted(daddr) && !tuh_suspended(daddr);
 }
 
@@ -162,15 +217,26 @@ bool tuh_control_xfer(tuh_xfer_t* xfer);
 //  - sync : blocking if complete callback is NULL.
 bool tuh_edpt_xfer(tuh_xfer_t* xfer);
 
-// Open an non-control endpoint
-bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
+// Open a non-control endpoint
+bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep);
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr);
 
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
 // true on success, false if there is on-going control transfer or incorrect parameters
+// if complete_cb == NULL i.e blocking, user_data should be pointed to xfer_reuslt_t*
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
                            tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
+// Set Interface (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
+// if complete_cb == NULL i.e blocking, user_data should be pointed to xfer_reuslt_t*
+bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
+                       tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
 //--------------------------------------------------------------------+
 // Descriptors Asynchronous (non-blocking)
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_pvt.h
similarity index 75%
rename from src/host/usbh_classdriver.h
rename to src/host/usbh_pvt.h
index c156afea0..95de915e9 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_pvt.h
@@ -24,32 +24,46 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_USBH_CLASSDRIVER_H_
-#define _TUSB_USBH_CLASSDRIVER_H_
+#ifndef _TUSB_USBH_PVT_H_
+#define _TUSB_USBH_PVT_H_
 
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
+#include "common/tusb_private.h"
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+#define TU_LOG_USBH(...)      TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_MEM_USBH(...)  TU_LOG_MEM(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_BUF_USBH(...)  TU_LOG_BUF(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_INT_USBH(...)  TU_LOG_INT(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_HEX_USBH(...)  TU_LOG_HEX(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+
+enum {
+  USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
+};
+
 //--------------------------------------------------------------------+
 // Class Driver API
 //--------------------------------------------------------------------+
 
 typedef struct {
-  #if CFG_TUSB_DEBUG >= 2
   char const* name;
-  #endif
-
-  void (* const init       )(void);
+  bool (* const init       )(void);
+  bool (* const deinit     )(void);
   bool (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
   bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
   bool (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
   void (* const close      )(uint8_t dev_addr);
 } usbh_class_driver_t;
 
+// Invoked when initializing host stack to get additional class drivers.
+// Can be implemented by application to extend/overwrite class driver support.
+// Note: The drivers array must be accessible at all time when stack is active
+usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
+
 // Call by class driver to tell USBH that it has complete the enumeration
 void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num);
 
@@ -59,6 +73,8 @@ uint8_t* usbh_get_enum_buf(void);
 
 void usbh_int_set(bool enabled);
 
+void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr);
+
 //--------------------------------------------------------------------+
 // USBH Endpoint API
 //--------------------------------------------------------------------+
@@ -68,12 +84,10 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 TU_ATTR_ALWAYS_INLINE
-static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) {
   return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0);
 }
 
-
 // Claim an endpoint before submitting a transfer.
 // If caller does not make any transfer, it must release endpoint for others.
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
diff --git a/src/osal/osal.h b/src/osal/osal.h
index 9d11866df..38d45da44 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -33,17 +33,24 @@
 
 #include "common/tusb_common.h"
 
-// Return immediately
-#define OSAL_TIMEOUT_NOTIMEOUT     (0)
-// Default timeout
-#define OSAL_TIMEOUT_NORMAL        (10)
-// Wait forever
-#define OSAL_TIMEOUT_WAIT_FOREVER  (UINT32_MAX)
-
-#define OSAL_TIMEOUT_CONTROL_XFER  OSAL_TIMEOUT_WAIT_FOREVER
-
 typedef void (*osal_task_func_t)( void * );
 
+// Timeout
+#define OSAL_TIMEOUT_NOTIMEOUT     (0)          // Return immediately
+#define OSAL_TIMEOUT_NORMAL        (10)         // Default timeout
+#define OSAL_TIMEOUT_WAIT_FOREVER  (UINT32_MAX) // Wait forever
+#define OSAL_TIMEOUT_CONTROL_XFER  OSAL_TIMEOUT_WAIT_FOREVER
+
+// Mutex is required when using a preempted RTOS or MCU has multiple cores
+#if (CFG_TUSB_OS == OPT_OS_NONE) && !TUP_MCU_MULTIPLE_CORE
+  #define OSAL_MUTEX_REQUIRED   0
+  #define OSAL_MUTEX_DEF(_name) uint8_t :0
+#else
+  #define OSAL_MUTEX_REQUIRED   1
+  #define OSAL_MUTEX_DEF(_name) osal_mutex_def_t _name
+#endif
+
+// OS thin implementation
 #if CFG_TUSB_OS == OPT_OS_NONE
   #include "osal_none.h"
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
@@ -56,6 +63,8 @@ typedef void (*osal_task_func_t)( void * );
   #include "osal_rtthread.h"
 #elif CFG_TUSB_OS == OPT_OS_RTX4
   #include "osal_rtx4.h"
+#elif CFG_TUSB_OS == OPT_OS_ZEPHYR
+  #include "osal_zephyr.h"
 #elif CFG_TUSB_OS == OPT_OS_CUSTOM
   #include "tusb_os_custom.h" // implemented by application
 #else
@@ -67,15 +76,18 @@ typedef void (*osal_task_func_t)( void * );
 // Should be implemented as static inline function in osal_port.h header
 /*
    osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
+   bool osal_semaphore_delete(osal_semaphore_t semd_hdl);
    bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
    bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec);
    void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed
 
    osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef);
+   bool osal_mutex_delete(osal_mutex_t mutex_hdl)
    bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec);
    bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
 
    osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
+   bool osal_queue_delete(osal_queue_t qhdl);
    bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec);
    bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
    bool osal_queue_empty(osal_queue_t qhdl);
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 52db336f5..a3a0f3a3f 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_FREERTOS_H_
-#define _TUSB_OSAL_FREERTOS_H_
+#ifndef TUSB_OSAL_FREERTOS_H_
+#define TUSB_OSAL_FREERTOS_H_
 
 // FreeRTOS Headers
 #include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h)
@@ -37,48 +37,93 @@
 extern "C" {
 #endif
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec)
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+#if configSUPPORT_STATIC_ALLOCATION
+  typedef StaticSemaphore_t osal_semaphore_def_t;
+  typedef StaticSemaphore_t osal_mutex_def_t;
+#else
+  // not used therefore defined to smallest possible type to save space
+  typedef uint8_t osal_semaphore_def_t;
+  typedef uint8_t osal_mutex_def_t;
+#endif
+
+typedef SemaphoreHandle_t osal_semaphore_t;
+typedef SemaphoreHandle_t osal_mutex_t;
+typedef QueueHandle_t osal_queue_t;
+
+typedef struct
 {
-  if (msec == OSAL_TIMEOUT_WAIT_FOREVER) return portMAX_DELAY;
-  if (msec == 0) return 0;
+  uint16_t depth;
+  uint16_t item_sz;
+  void*    buf;
+
+#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+  char const* name;
+#endif
+
+#if configSUPPORT_STATIC_ALLOCATION
+  StaticQueue_t sq;
+#endif
+} osal_queue_def_t;
+
+#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+  #define _OSAL_Q_NAME(_name) .name = #_name
+#else
+  #define _OSAL_Q_NAME(_name)
+#endif
+
+// _int_set is not used with an RTOS
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
+  static _type _name##_##buf[_depth];\
+  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, _OSAL_Q_NAME(_name) }
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) {
+  if ( msec == OSAL_TIMEOUT_WAIT_FOREVER ) return portMAX_DELAY;
+  if ( msec == 0 ) return 0;
 
   uint32_t ticks = pdMS_TO_TICKS(msec);
 
   // configTICK_RATE_HZ is less than 1000 and 1 tick > 1 ms
   // we still need to delay at least 1 tick
-  if (ticks == 0) ticks =1 ;
+  if ( ticks == 0 ) ticks = 1;
 
   return ticks;
 }
 
-//--------------------------------------------------------------------+
-// TASK API
-//--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
-{
-  vTaskDelay( pdMS_TO_TICKS(msec) );
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
+  vTaskDelay(pdMS_TO_TICKS(msec));
 }
 
 //--------------------------------------------------------------------+
 // Semaphore API
 //--------------------------------------------------------------------+
-typedef StaticSemaphore_t osal_semaphore_def_t;
-typedef SemaphoreHandle_t osal_semaphore_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) {
+#if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateBinaryStatic(semdef);
+#else
+  (void) semdef;
+  return xSemaphoreCreateBinary();
+#endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
-  if ( !in_isr )
-  {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  vSemaphoreDelete(semd_hdl);
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
+  if ( !in_isr ) {
     return xSemaphoreGive(sem_hdl) != 0;
-  }
-  else
-  {
-    BaseType_t xHigherPriorityTaskWoken;
+  } else {
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken);
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
@@ -92,34 +137,37 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
   return xSemaphoreTake(sem_hdl, _osal_ms2tick(msec));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
   xQueueReset(sem_hdl);
 }
 
 //--------------------------------------------------------------------+
 // MUTEX API (priority inheritance)
 //--------------------------------------------------------------------+
-typedef StaticSemaphore_t osal_mutex_def_t;
-typedef SemaphoreHandle_t osal_mutex_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
+#if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateMutexStatic(mdef);
+#else
+  (void) mdef;
+  return xSemaphoreCreateMutex();
+#endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  vSemaphoreDelete(mutex_hdl);
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   return xSemaphoreGive(mutex_hdl);
 }
 
@@ -127,45 +175,40 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 // QUEUE API
 //--------------------------------------------------------------------+
 
-// _int_set is not used with an RTOS
-#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
-  static _type _name##_##buf[_depth];\
-  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
+  osal_queue_t q;
 
-typedef struct
-{
-  uint16_t depth;
-  uint16_t item_sz;
-  void*    buf;
+#if configSUPPORT_STATIC_ALLOCATION
+  q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+#else
+  q = xQueueCreate(qdef->depth, qdef->item_sz);
+#endif
 
-  StaticQueue_t sq;
-}osal_queue_def_t;
+#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+  vQueueAddToRegistry(q, qdef->name);
+#endif
 
-typedef QueueHandle_t osal_queue_t;
-
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
-  return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+  return q;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  vQueueDelete(qhdl);
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   return xQueueReceive(qhdl, data, _osal_ms2tick(msec));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
-  if ( !in_isr )
-  {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
+  if ( !in_isr ) {
     return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0;
-  }
-  else
-  {
-    BaseType_t xHigherPriorityTaskWoken;
+  } else {
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken);
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
-    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7
+    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 (IDF v5)
     if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
 #else
     portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
@@ -175,13 +218,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   return uxQueueMessagesWaiting(qhdl) == 0;
 }
 
 #ifdef __cplusplus
- }
+}
 #endif
 
 #endif
diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h
index b8ea2087c..16def0d2a 100644
--- a/src/osal/osal_mynewt.h
+++ b/src/osal/osal_mynewt.h
@@ -36,8 +36,7 @@
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   os_time_delay( os_time_ms_to_ticks32(msec) );
 }
 
@@ -47,25 +46,26 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 typedef struct os_sem  osal_semaphore_def_t;
 typedef struct os_sem* osal_semaphore_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) {
   return (os_sem_init(semdef, 0) == OS_OK) ? (osal_semaphore_t) semdef : NULL;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  (void) semd_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   (void) in_isr;
   return os_sem_release(sem_hdl) == OS_OK;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
   uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec);
   return os_sem_pend(sem_hdl, ticks) == OS_OK;
 }
 
-static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
-{
+static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) {
   // TODO implement later
 }
 
@@ -75,19 +75,21 @@ static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
 typedef struct os_mutex osal_mutex_def_t;
 typedef struct os_mutex* osal_mutex_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
   return (os_mutex_init(mdef) == OS_OK) ? (osal_mutex_t) mdef : NULL;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
   uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec);
   return os_mutex_pend(mutex_hdl, ticks) == OS_OK;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   return os_mutex_release(mutex_hdl) == OS_OK;
 }
 
@@ -101,8 +103,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
   static struct os_event _name##_##evbuf[_depth];\
   osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .evbuf =  _name##_##evbuf};\
 
-typedef struct
-{
+typedef struct {
   uint16_t depth;
   uint16_t item_sz;
   void*    buf;
@@ -116,17 +117,20 @@ typedef struct
 
 typedef osal_queue_def_t* osal_queue_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
-  if ( OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usbd queue") ) return NULL;
-  if ( OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usbd evqueue") ) return NULL;
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
+  if ( OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usb queue") ) return NULL;
+  if ( OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usb evqueue") ) return NULL;
 
   os_eventq_init(&qdef->evq);
   return (osal_queue_t) qdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  (void) qhdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   (void) msec; // os_eventq_get() does not take timeout, always behave as msec = WAIT_FOREVER
 
   struct os_event* ev;
@@ -139,8 +143,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v
   return true;
 }
 
-static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
+static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) {
   (void) in_isr;
 
   // get a block from mem pool for data
@@ -150,8 +153,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
 
   // get a block from event pool to put into queue
   struct os_event* ev = (struct os_event*) os_memblock_get(&qhdl->epool);
-  if (!ev)
-  {
+  if (!ev) {
     os_memblock_put(&qhdl->mpool, ptr);
     return false;
   }
@@ -163,8 +165,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   return STAILQ_EMPTY(&qhdl->evq.evq_list);
 }
 
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 9c80e4548..40e9bb83a 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,54 +24,59 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_NONE_H_
-#define _TUSB_OSAL_NONE_H_
+#ifndef TUSB_OSAL_NONE_H_
+#define TUSB_OSAL_NONE_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
 
+#if CFG_TUH_ENABLED
+// currently only needed/available in host mode
+TU_ATTR_WEAK void osal_task_delay(uint32_t msec);
+#endif
 
 //--------------------------------------------------------------------+
 // Binary Semaphore API
 //--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
   volatile uint16_t count;
-}osal_semaphore_def_t;
+} osal_semaphore_def_t;
 
 typedef osal_semaphore_def_t* osal_semaphore_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) {
   semdef->count = 0;
   return semdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  (void) semd_hdl;
+  return true; // nothing to do
+}
+
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   (void) in_isr;
   sem_hdl->count++;
   return true;
 }
 
 // TODO blocking for now
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
   (void) msec;
 
-  while (sem_hdl->count == 0) { }
+  while (sem_hdl->count == 0) {}
   sem_hdl->count--;
 
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) {
   sem_hdl->count = 0;
 }
 
@@ -82,32 +87,45 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t s
 typedef osal_semaphore_def_t osal_mutex_def_t;
 typedef osal_semaphore_t osal_mutex_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+#if OSAL_MUTEX_REQUIRED
+// Note: multiple cores MCUs usually do provide IPC API for mutex
+// or we can use std atomic function
+
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
   mdef->count = 1;
   return mdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   return osal_semaphore_post(mutex_hdl, false);
 }
 
+#else
+
+#define osal_mutex_create(_mdef)          (NULL)
+#define osal_mutex_lock(_mutex_hdl, _ms)  (true)
+#define osal_mutex_unlock(_mutex_hdl)     (true)
+
+#endif
+
 //--------------------------------------------------------------------+
 // QUEUE API
 //--------------------------------------------------------------------+
 #include "common/tusb_fifo.h"
 
-typedef struct
-{
-  void (*interrupt_set)(bool);
+typedef struct {
+  void (* interrupt_set)(bool);
   tu_fifo_t ff;
-}osal_queue_def_t;
+} osal_queue_def_t;
 
 typedef osal_queue_def_t* osal_queue_t;
 
@@ -119,63 +137,48 @@ typedef osal_queue_def_t* osal_queue_t;
     .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \
   }
 
-// lock queue by disable USB interrupt
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl)
-{
-  // disable dcd/hcd interrupt
-  qhdl->interrupt_set(false);
-}
-
-// unlock queue
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl)
-{
-  // enable dcd/hcd interrupt
-  qhdl->interrupt_set(true);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
   tu_fifo_clear(&qdef->ff);
   return (osal_queue_t) qdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  (void) qhdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   (void) msec; // not used, always behave as msec = 0
 
-  _osal_q_lock(qhdl);
-  bool success = tu_fifo_read(&qhdl->ff, data);
-  _osal_q_unlock(qhdl);
+  qhdl->interrupt_set(false);
+  const bool success = tu_fifo_read(&qhdl->ff, data);
+  qhdl->interrupt_set(true);
 
   return success;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) {
   if (!in_isr) {
-    _osal_q_lock(qhdl);
+    qhdl->interrupt_set(false);
   }
 
-  bool success = tu_fifo_write(&qhdl->ff, data);
+  const bool success = tu_fifo_write(&qhdl->ff, data);
 
   if (!in_isr) {
-    _osal_q_unlock(qhdl);
+    qhdl->interrupt_set(true);
   }
 
-  TU_ASSERT(success);
-
   return success;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   // Skip queue lock/unlock since this function is primarily called
   // with interrupt disabled before going into low power mode
   return tu_fifo_empty(&qhdl->ff);
 }
 
 #ifdef __cplusplus
- }
+}
 #endif
 
-#endif /* _TUSB_OSAL_NONE_H_ */
+#endif
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index 8b428d642..315de0950 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_PICO_H_
-#define _TUSB_OSAL_PICO_H_
+#ifndef TUSB_OSAL_PICO_H_
+#define TUSB_OSAL_PICO_H_
 
 #include "pico/time.h"
 #include "pico/sem.h"
@@ -33,42 +33,42 @@
 #include "pico/critical_section.h"
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   sleep_ms(msec);
 }
 
 //--------------------------------------------------------------------+
 // Binary Semaphore API
 //--------------------------------------------------------------------+
-typedef struct semaphore osal_semaphore_def_t, *osal_semaphore_t;
+typedef struct semaphore osal_semaphore_def_t, * osal_semaphore_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) {
   sem_init(semdef, 0, 255);
   return semdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  (void) semd_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   (void) in_isr;
   sem_release(sem_hdl);
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
   return sem_acquire_timeout_ms(sem_hdl, msec);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) {
   sem_reset(sem_hdl, 0);
 }
 
@@ -76,21 +76,23 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t s
 // MUTEX API
 // Within tinyusb, mutex is never used in ISR context
 //--------------------------------------------------------------------+
-typedef struct mutex osal_mutex_def_t, *osal_mutex_t;
+typedef struct mutex osal_mutex_def_t, * osal_mutex_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
   mutex_init(mdef);
   return mdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
   return mutex_enter_timeout_ms(mutex_hdl, msec);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   mutex_exit(mutex_hdl);
   return true;
 }
@@ -100,75 +102,53 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 //--------------------------------------------------------------------+
 #include "common/tusb_fifo.h"
 
-typedef struct
-{
-    tu_fifo_t ff;
-    struct critical_section critsec; // osal_queue may be used in IRQs, so need critical section
+typedef struct {
+  tu_fifo_t ff;
+  struct critical_section critsec; // osal_queue may be used in IRQs, so need critical section
 } osal_queue_def_t;
 
 typedef osal_queue_def_t* osal_queue_t;
 
 // role device/host is used by OS NONE for mutex (disable usb isr) only
-#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)       \
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)    \
   uint8_t _name##_buf[_depth*sizeof(_type)];              \
   osal_queue_def_t _name = {                              \
     .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \
   }
 
-// lock queue by disable USB interrupt
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl)
-{
-  critical_section_enter_blocking(&qhdl->critsec);
-}
-
-// unlock queue
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl)
-{
-  critical_section_exit(&qhdl->critsec);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
   critical_section_init(&qdef->critsec);
   tu_fifo_clear(&qdef->ff);
   return (osal_queue_t) qdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  osal_queue_def_t* qdef = (osal_queue_def_t*) qhdl;
+  critical_section_deinit(&qdef->critsec);
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   (void) msec; // not used, always behave as msec = 0
 
-  // TODO: revisit... docs say that mutexes are never used from IRQ context,
-  //  however osal_queue_recieve may be. therefore my assumption is that
-  //  the fifo mutex is not populated for queues used from an IRQ context
-  //assert(!qhdl->ff.mutex);
-
-  _osal_q_lock(qhdl);
+  critical_section_enter_blocking(&qhdl->critsec);
   bool success = tu_fifo_read(&qhdl->ff, data);
-  _osal_q_unlock(qhdl);
+  critical_section_exit(&qhdl->critsec);
 
   return success;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
-  // TODO: revisit... docs say that mutexes are never used from IRQ context,
-  //  however osal_queue_recieve may be. therefore my assumption is that
-  //  the fifo mutex is not populated for queues used from an IRQ context
-  //assert(!qhdl->ff.mutex);
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) {
   (void) in_isr;
 
-  _osal_q_lock(qhdl);
+  critical_section_enter_blocking(&qhdl->critsec);
   bool success = tu_fifo_write(&qhdl->ff, data);
-  _osal_q_unlock(qhdl);
-
-  TU_ASSERT(success);
+  critical_section_exit(&qhdl->critsec);
 
   return success;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   // TODO: revisit; whether this is true or not currently, tu_fifo_empty is a single
   //  volatile read.
 
@@ -178,7 +158,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
 }
 
 #ifdef __cplusplus
- }
+}
 #endif
 
-#endif /* _TUSB_OSAL_PICO_H_ */
+#endif
diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index f8452bfb2..c27814835 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 tfx2001 (2479727366@qq.com)
+ * Copyright (c) 2020 yekai (2857693944@qq.com)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,8 +25,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_RTTHREAD_H_
-#define _TUSB_OSAL_RTTHREAD_H_
+#ifndef TUSB_OSAL_RTTHREAD_H_
+#define TUSB_OSAL_RTTHREAD_H_
 
 // RT-Thread Headers
 #include "rtthread.h"
@@ -47,23 +48,27 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
 typedef struct rt_semaphore osal_semaphore_def_t;
 typedef rt_sem_t osal_semaphore_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t
-osal_semaphore_create(osal_semaphore_def_t *semdef) {
-    rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_PRIO);
-    return semdef;
+TU_ATTR_ALWAYS_INLINE static inline
+osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) {
+  rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_PRIO);
+  return semdef;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  return RT_EOK == rt_sem_detach(semd_hdl);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
-    (void) in_isr;
-    return rt_sem_release(sem_hdl) == RT_EOK;
+  (void) in_isr;
+  return rt_sem_release(sem_hdl) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
-    return rt_sem_take(sem_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
+  return rt_sem_take(sem_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
-    // TODO: implement
+  rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, 0);
 }
 
 //--------------------------------------------------------------------+
@@ -73,16 +78,20 @@ typedef struct rt_mutex osal_mutex_def_t;
 typedef rt_mutex_t osal_mutex_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
-    rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_PRIO);
-    return mdef;
+  rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_PRIO);
+  return mdef;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  return RT_EOK == rt_mutex_detach(mutex_hdl);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
-    return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
+  return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
-    return rt_mutex_release(mutex_hdl) == RT_EOK;
+  return rt_mutex_release(mutex_hdl) == RT_EOK;
 }
 
 //--------------------------------------------------------------------+
@@ -105,28 +114,35 @@ typedef struct {
 typedef rt_mq_t osal_queue_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) {
-    rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz,
-               qdef->item_sz * qdef->depth, RT_IPC_FLAG_PRIO);
-    return &(qdef->sq);
+  rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz,
+             qdef->item_sz * qdef->depth, RT_IPC_FLAG_PRIO);
+  return &(qdef->sq);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  return RT_EOK == rt_mq_detach(qhdl);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void *data, uint32_t msec) {
-
-    rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec);
-    return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK;
+  rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec);
+#if RT_VERSION_MAJOR >= 5
+  return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) > 0;
+#else
+  return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK;
+#endif  /* RT_VERSION_MAJOR >= 5 */
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
-    (void) in_isr;
-    return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK;
+  (void) in_isr;
+  return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
-    return (qhdl->entry) == 0;
+  return (qhdl->entry) == 0;
 }
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* _TUSB_OSAL_RTTHREAD_H_ */
+#endif
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
index dea1c12c8..35909e4d6 100644
--- a/src/osal/osal_rtx4.h
+++ b/src/osal/osal_rtx4.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Tian Yunhao (t123yh)
@@ -25,8 +25,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_RTX4_H_
-#define _TUSB_OSAL_RTX4_H_
+#ifndef TUSB_OSAL_RTX4_H_
+#define TUSB_OSAL_RTX4_H_
 
 #include <rtl.h>
 
@@ -37,8 +37,7 @@ extern "C" {
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   uint16_t hi = msec >> 16;
   uint16_t lo = msec;
   while (hi--) {
@@ -48,12 +47,13 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint16_t msec2wait(uint32_t msec) {
-  if (msec == OSAL_TIMEOUT_WAIT_FOREVER)
+  if (msec == OSAL_TIMEOUT_WAIT_FOREVER) {
     return 0xFFFF;
-  else if (msec >= 0xFFFE)
+  } else if (msec >= 0xFFFE) {
     return 0xFFFE;
-  else
+  } else {
     return msec;
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -67,6 +67,11 @@ TU_ATTR_ALWAYS_INLINE static inline OS_ID osal_semaphore_create(osal_semaphore_d
   return semdef;
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  (void) semd_hdl;
+  return true; // nothing to do
+}
+
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   if ( !in_isr ) {
     os_sem_send(sem_hdl);
@@ -90,19 +95,21 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c
 typedef OS_MUT osal_mutex_def_t;
 typedef OS_ID osal_mutex_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
   os_mut_init(mdef);
   return mdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) {
   return os_mut_wait(mutex_hdl, msec2wait(msec)) != OS_R_TMO;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   return os_mut_release(mutex_hdl) == OS_R_OK;
 }
 
@@ -115,10 +122,8 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
   os_mbx_declare(_name##__mbox, _depth);              \
   _declare_box(_name##__pool, sizeof(_type), _depth); \
   osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox };
-  
 
-typedef struct
-{
+typedef struct {
   uint16_t depth;
   uint16_t item_sz;
   U32* pool;
@@ -127,15 +132,13 @@ typedef struct
 
 typedef osal_queue_def_t* osal_queue_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
   os_mbx_init(qdef->mbox, (qdef->depth + 4) * 4);
   _init_box(qdef->pool, ((qdef->item_sz+3)/4)*(qdef->depth) + 3, qdef->item_sz);
   return qdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   void* buf;
   os_mbx_wait(qhdl->mbox, &buf, msec2wait(msec));
   memcpy(data, buf, qhdl->item_sz);
@@ -143,23 +146,23 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  (void) qhdl;
+  return true; // nothing to do ?
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) {
   void* buf = _alloc_box(qhdl->pool);
   memcpy(buf, data, qhdl->item_sz);
-  if ( !in_isr )
-  {
+  if ( !in_isr ) {
     os_mbx_send(qhdl->mbox, buf, 0xFFFF);
-  }
-  else
-  {
+  } else {
     isr_mbx_send(qhdl->mbox, buf);
   }
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   return os_mbx_check(qhdl->mbox) == qhdl->depth;
 }
 
diff --git a/src/osal/osal_zephyr.h b/src/osal/osal_zephyr.h
new file mode 100644
index 000000000..8ecb13c6d
--- /dev/null
+++ b/src/osal/osal_zephyr.h
@@ -0,0 +1,123 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#ifndef TUSB_OSAL_ZEPHYR_H
+#define TUSB_OSAL_ZEPHYR_H
+
+#include <zephyr/kernel.h>
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
+  k_msleep(msec);
+}
+
+//--------------------------------------------------------------------+
+// Binary Semaphore API
+//--------------------------------------------------------------------+
+typedef struct k_sem osal_semaphore_def_t, * osal_semaphore_t;
+
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) {
+  k_sem_init(semdef, 0, 255);
+  return semdef;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  (void) semd_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
+  (void) in_isr;
+  k_sem_give(sem_hdl);
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
+  return 0 == k_sem_take(sem_hdl, K_MSEC(msec));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) {
+  k_sem_reset(sem_hdl);
+}
+
+//--------------------------------------------------------------------+
+// MUTEX API
+//--------------------------------------------------------------------+
+typedef struct k_mutex osal_mutex_def_t, *osal_mutex_t;
+
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
+  if ( 0 == k_mutex_init(mdef) ) {
+    return mdef;
+  } else {
+    return NULL;
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
+  return 0 == k_mutex_lock(mutex_hdl, K_MSEC(msec));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
+  return 0 == k_mutex_unlock(mutex_hdl);
+}
+
+//--------------------------------------------------------------------+
+// QUEUE API
+//--------------------------------------------------------------------+
+typedef struct k_msgq osal_queue_def_t, * osal_queue_t;
+
+// role device/host is used by OS NONE for mutex (disable usb isr) only
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)  K_MSGQ_DEFINE(_name, sizeof(_type), _depth, 4)
+
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
+  // K_MSGQ_DEFINE already initializes the queue
+  return (osal_queue_t) qdef;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  (void) qhdl;
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
+  return 0 == k_msgq_get(qhdl, data, K_MSEC(msec));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) {
+  return 0 == k_msgq_put(qhdl, data,  in_isr ? K_NO_WAIT : K_FOREVER);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
+  return 0 == k_msgq_num_used_get(qhdl);
+}
+
+#endif
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
new file mode 100644
index 000000000..c5e924266
--- /dev/null
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -0,0 +1,1076 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+#include <stdatomic.h>
+#include "host/hcd.h"
+#include "host/usbh.h"
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Command format is
+// Reg [7:3] | 0 [2] | Dir [1] | Ack [0]
+
+enum {
+  CMDBYTE_WRITE = 0x02,
+};
+
+enum {
+  RCVVFIFO_ADDR = 1u  << 3, // 0x08
+  SNDFIFO_ADDR  = 2u  << 3, // 0x10
+  SUDFIFO_ADDR  = 4u  << 3, // 0x20
+  RCVBC_ADDR    = 6u  << 3, // 0x30
+  SNDBC_ADDR    = 7u  << 3, // 0x38
+  USBIRQ_ADDR   = 13u << 3, // 0x68
+  USBIEN_ADDR   = 14u << 3, // 0x70
+  USBCTL_ADDR   = 15u << 3, // 0x78
+  CPUCTL_ADDR   = 16u << 3, // 0x80
+  PINCTL_ADDR   = 17u << 3, // 0x88
+  REVISION_ADDR = 18u << 3, // 0x90
+  // 19 is not used
+  IOPINS1_ADDR  = 20u << 3, // 0xA0
+  IOPINS2_ADDR  = 21u << 3, // 0xA8
+  GPINIRQ_ADDR  = 22u << 3, // 0xB0
+  GPINIEN_ADDR  = 23u << 3, // 0xB8
+  GPINPOL_ADDR  = 24u << 3, // 0xC0
+  HIRQ_ADDR     = 25u << 3, // 0xC8
+  HIEN_ADDR     = 26u << 3, // 0xD0
+  MODE_ADDR     = 27u << 3, // 0xD8
+  PERADDR_ADDR  = 28u << 3, // 0xE0
+  HCTL_ADDR     = 29u << 3, // 0xE8
+  HXFR_ADDR     = 30u << 3, // 0xF0
+  HRSL_ADDR     = 31u << 3, // 0xF8
+};
+
+enum {
+  USBIRQ_OSCOK_IRQ  = 1u << 0,
+  USBIRQ_NOVBUS_IRQ = 1u << 5,
+  USBIRQ_VBUS_IRQ   = 1u << 6,
+};
+
+enum {
+  USBCTL_PWRDOWN = 1u << 4,
+  USBCTL_CHIPRES = 1u << 5,
+};
+
+enum {
+  CPUCTL_IE        = 1u << 0,
+  CPUCTL_PULSEWID0 = 1u << 6,
+  CPUCTL_PULSEWID1 = 1u << 7,
+};
+
+enum {
+  PINCTL_GPXA     = 1u << 0,
+  PINCTL_GPXB     = 1u << 1,
+  PINCTL_POSINT   = 1u << 2,
+  PINCTL_INTLEVEL = 1u << 3,
+  PINCTL_FDUPSPI  = 1u << 4,
+};
+
+enum {
+  HIRQ_BUSEVENT_IRQ = 1u << 0,
+  HIRQ_RWU_IRQ      = 1u << 1,
+  HIRQ_RCVDAV_IRQ   = 1u << 2,
+  HIRQ_SNDBAV_IRQ   = 1u << 3,
+  HIRQ_SUSDN_IRQ    = 1u << 4,
+  HIRQ_CONDET_IRQ   = 1u << 5,
+  HIRQ_FRAME_IRQ    = 1u << 6,
+  HIRQ_HXFRDN_IRQ   = 1u << 7,
+};
+
+enum {
+  MODE_HOST      = 1u << 0,
+  MODE_LOWSPEED  = 1u << 1,
+  MODE_HUBPRE    = 1u << 2,
+  MODE_SOFKAENAB = 1u << 3,
+  MODE_SEPIRQ    = 1u << 4,
+  MODE_DELAYISO  = 1u << 5,
+  MODE_DMPULLDN  = 1u << 6,
+  MODE_DPPULLDN  = 1u << 7,
+};
+
+enum {
+  HCTL_BUSRST    = 1u << 0,
+  HCTL_FRMRST    = 1u << 1,
+  HCTL_SAMPLEBUS = 1u << 2,
+  HCTL_SIGRSM    = 1u << 3,
+  HCTL_RCVTOG0   = 1u << 4,
+  HCTL_RCVTOG1   = 1u << 5,
+  HCTL_SNDTOG0   = 1u << 6,
+  HCTL_SNDTOG1   = 1u << 7,
+};
+
+enum {
+  HXFR_EPNUM_MASK = 0x0f,
+  HXFR_SETUP      = 1u << 4,
+  HXFR_OUT_NIN    = 1u << 5,
+  HXFR_ISO        = 1u << 6,
+  HXFR_HS         = 1u << 7,
+};
+
+enum {
+  HRSL_RESULT_MASK = 0x0f,
+  HRSL_RCVTOGRD    = 1u << 4,
+  HRSL_SNDTOGRD    = 1u << 5,
+  HRSL_KSTATUS     = 1u << 6,
+  HRSL_JSTATUS     = 1u << 7,
+};
+
+enum {
+  HRSL_SUCCESS = 0,
+  HRSL_BUSY,
+  HRSL_BAD_REQ,
+  HRSL_UNDEF,
+  HRSL_NAK,
+  HRSL_STALL,
+  HRSL_TOG_ERR,
+  HRSL_WRONG_PID,
+  HRSL_BAD_BYTECOUNT,
+  HRSL_PID_ERR,
+  HRSL_PKT_ERR,
+  HRSL_CRC_ERR,
+  HRSL_K_ERR,
+  HRSL_J_ERR,
+  HRSL_TIMEOUT,
+  HRSL_BABBLE,
+};
+
+enum {
+  DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ | HIRQ_RCVDAV_IRQ
+};
+
+enum {
+  MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame to save CPU/SPI bus usage
+};
+
+enum {
+  EP_STATE_IDLE        = 0,
+  EP_STATE_COMPLETE    = 1,
+  EP_STATE_ABORTING    = 2,
+  EP_STATE_ATTEMPT_1   = 3, // Number of attempts to transfer in a frame. Incremented after each NAK
+  EP_STATE_ATTEMPT_MAX = 15
+};
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t ep_num   : 4;
+  uint8_t is_setup : 1;
+  uint8_t is_out   : 1;
+  uint8_t is_iso   : 1;
+} hxfr_bm_t;
+
+TU_VERIFY_STATIC(sizeof(hxfr_bm_t) == 1, "size is not correct");
+
+typedef struct {
+  uint8_t daddr;
+
+  union {
+    hxfr_bm_t hxfr_bm;
+    uint8_t hxfr;
+  };
+
+  struct TU_ATTR_PACKED {
+    uint8_t state        : 4;
+    uint8_t data_toggle  : 1;
+    uint16_t packet_size : 11;
+  };
+
+  uint16_t total_len;
+  uint16_t xferred_len;
+  uint8_t* buf;
+} max3421_ep_t;
+
+TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 12, "size is not correct");
+
+typedef struct {
+  volatile uint16_t frame_count;
+
+  // cached register
+  uint8_t sndbc;
+  uint8_t hirq;
+  uint8_t hien;
+  uint8_t mode;
+  uint8_t peraddr;
+  union {
+    hxfr_bm_t hxfr_bm;
+    uint8_t hxfr;
+  };
+
+  // owner of data in SNDFIFO, for retrying NAKed without re-writing to FIFO
+  struct {
+    uint8_t daddr;
+    uint8_t hxfr;
+  }sndfifo_owner;
+
+  atomic_flag busy; // busy transferring
+
+#if OSAL_MUTEX_REQUIRED
+  OSAL_MUTEX_DEF(spi_mutexdef);
+  osal_mutex_t spi_mutex;
+#endif
+
+  max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
+} max3421_data_t;
+
+static max3421_data_t _hcd_data;
+
+// max NAK before giving up in a frame. 0 means infinite NAKs
+static tuh_configure_max3421_t _tuh_cfg = {
+    .max_nak = MAX_NAK_DEFAULT,
+    .cpuctl = 0, // default: INT pulse width = 10.6 us
+    .pinctl = 0, // default: negative edge interrupt
+};
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E
+// - spi_cs_api(), spi_xfer_api(), int_api(): must be implemented by application
+// - reg_read(), reg_write(): is implemented by this driver, can be used by application
+//--------------------------------------------------------------------+
+
+// API to control MAX3421 SPI CS
+extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes);
+
+// API to enable/disable MAX3421 INTR pin interrupt
+extern void tuh_max3421_int_api(uint8_t rhport, bool enabled);
+
+// API to read MAX3421's register. Implemented by TinyUSB
+uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
+
+// API to write MAX3421's register. Implemented by TinyUSB
+bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
+
+//--------------------------------------------------------------------+
+// SPI Commands and Helper
+//--------------------------------------------------------------------+
+
+#define reg_read  tuh_max3421_reg_read
+#define reg_write tuh_max3421_reg_write
+
+static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
+  // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
+  if (!in_isr) {
+    (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+    tuh_max3421_int_api(rhport, false);
+  }
+
+  // assert CS
+  tuh_max3421_spi_cs_api(rhport, true);
+}
+
+static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
+  // de-assert CS
+  tuh_max3421_spi_cs_api(rhport, false);
+
+  // mutex unlock and re-enable interrupt
+  if (!in_isr) {
+    tuh_max3421_int_api(rhport, true);
+    (void) osal_mutex_unlock(_hcd_data.spi_mutex);
+  }
+}
+
+uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
+  uint8_t tx_buf[2] = {reg, 0};
+  uint8_t rx_buf[2] = {0, 0};
+
+  max3421_spi_lock(rhport, in_isr);
+  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
+  max3421_spi_unlock(rhport, in_isr);
+
+  _hcd_data.hirq = rx_buf[0];
+  return ret ? rx_buf[1] : 0;
+}
+
+bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) {
+  uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
+  uint8_t rx_buf[2] = {0, 0};
+
+  max3421_spi_lock(rhport, in_isr);
+  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
+  max3421_spi_unlock(rhport, in_isr);
+
+  // HIRQ register since we are in full-duplex mode
+  _hcd_data.hirq = rx_buf[0];
+
+  return ret;
+}
+
+//--------------------------------------------------------------------
+// Register helper
+//--------------------------------------------------------------------
+TU_ATTR_ALWAYS_INLINE static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
+  reg_write(rhport, HIRQ_ADDR, data, in_isr);
+  // HIRQ write 1 is clear
+  _hcd_data.hirq &= (uint8_t) ~data;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
+  _hcd_data.hien = data;
+  reg_write(rhport, HIEN_ADDR, data, in_isr);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) {
+  _hcd_data.mode = data;
+  reg_write(rhport, MODE_ADDR, data, in_isr);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) {
+  if ( _hcd_data.peraddr == data ) return; // no need to change address
+
+  _hcd_data.peraddr = data;
+  reg_write(rhport, PERADDR_ADDR, data, in_isr);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) {
+  _hcd_data.hxfr = data;
+  reg_write(rhport, HXFR_ADDR, data, in_isr);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
+  _hcd_data.sndbc = data;
+  reg_write(rhport, SNDBC_ADDR, data, in_isr);
+}
+
+//--------------------------------------------------------------------
+// FIFO access (receive, send, setup)
+//--------------------------------------------------------------------
+static void hwfifo_write(uint8_t rhport, uint8_t reg, const uint8_t* buffer, uint8_t len, bool in_isr) {
+  uint8_t hirq;
+  reg |= CMDBYTE_WRITE;
+
+  max3421_spi_lock(rhport, in_isr);
+
+  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
+  _hcd_data.hirq = hirq;
+  tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
+
+  max3421_spi_unlock(rhport, in_isr);
+}
+
+// Write to SNDFIFO if len > 0 and update SNDBC
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_send(uint8_t rhport, const uint8_t* buffer, uint8_t len, bool in_isr) {
+  if (len) {
+    hwfifo_write(rhport, SNDFIFO_ADDR, buffer, len, in_isr);
+  }
+  sndbc_write(rhport, len, in_isr);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_setup(uint8_t rhport, const uint8_t* buffer, bool in_isr) {
+  hwfifo_write(rhport, SUDFIFO_ADDR, buffer, 8, in_isr);
+}
+
+static void hwfifo_receive(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
+  uint8_t hirq;
+  uint8_t const reg = RCVVFIFO_ADDR;
+
+  max3421_spi_lock(rhport, in_isr);
+
+  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
+  _hcd_data.hirq = hirq;
+  tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len);
+
+  max3421_spi_unlock(rhport, in_isr);
+}
+
+//--------------------------------------------------------------------+
+// Endpoint helper
+//--------------------------------------------------------------------+
+
+static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
+  uint8_t const is_out = 1-ep_dir;
+  for(size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    // control endpoint is bi-direction (skip check)
+    if (daddr == ep->daddr && ep_num == ep->hxfr_bm.ep_num && (ep_num == 0 || is_out == ep->hxfr_bm.is_out)) {
+      return ep;
+    }
+  }
+
+  return NULL;
+}
+
+// daddr = 0 and ep_num = 0 means find a free (allocate) endpoint
+TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * allocate_ep(void) {
+  return find_ep_not_addr0(0, 0, 0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
+  if (daddr == 0 && ep_num == 0) {
+    return &_hcd_data.ep[0];
+  }else{
+    return find_ep_not_addr0(daddr, ep_num, ep_dir);
+  }
+}
+
+// free all endpoints belong to device address
+static void free_ep(uint8_t daddr) {
+  for (size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    if (ep->daddr == daddr) {
+      tu_memclr(ep, sizeof(max3421_ep_t));
+    }
+  }
+}
+
+// Check if endpoint has a queued transfer and not reach max NAK in this frame
+TU_ATTR_ALWAYS_INLINE static inline bool is_ep_pending(max3421_ep_t const * ep) {
+  uint8_t const state = ep->state;
+  return ep->packet_size && (state >= EP_STATE_ATTEMPT_1) &&
+         (_tuh_cfg.max_nak == 0 || state < EP_STATE_ATTEMPT_1 + _tuh_cfg.max_nak);
+}
+
+// Find the next pending endpoint using round-robin scheduling, starting from next endpoint.
+// return NULL if not found
+// TODO respect interrupt endpoint's interval
+static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
+  size_t const idx = (size_t) (cur_ep - _hcd_data.ep);
+
+  // starting from next endpoint
+  for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    if (is_ep_pending(ep)) {
+      return ep;
+    }
+  }
+
+  // wrap around including current endpoint
+  for (size_t i = 0; i <= idx; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    if (is_ep_pending(ep)) {
+      return ep;
+    }
+  }
+
+  return NULL;
+}
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// optional hcd configuration, called by tuh_configure()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  TU_VERIFY(cfg_id == TUH_CFGID_MAX3421 && cfg_param != NULL);
+
+  tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
+  _tuh_cfg = cfg->max3421;
+  _tuh_cfg.max_nak = tu_min8(_tuh_cfg.max_nak, EP_STATE_ATTEMPT_MAX-EP_STATE_ATTEMPT_1);
+  return true;
+}
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+
+  tuh_max3421_int_api(rhport, false);
+
+  TU_LOG2_INT(sizeof(max3421_ep_t));
+  TU_LOG2_INT(sizeof(max3421_data_t));
+  TU_LOG2_INT(offsetof(max3421_data_t, ep));
+
+  tu_memclr(&_hcd_data, sizeof(_hcd_data));
+  _hcd_data.peraddr = 0xff; // invalid
+
+#if OSAL_MUTEX_REQUIRED
+  _hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef);
+#endif
+
+  // NOTE: driver does not seem to work without nRST pin signal
+
+  // full duplex, interrupt negative edge
+  reg_write(rhport, PINCTL_ADDR, _tuh_cfg.pinctl | PINCTL_FDUPSPI, false);
+
+  // v1 is 0x01, v2 is 0x12, v3 is 0x13
+  // Note: v1 and v2 has host OUT errata whose workaround is not implemented in this driver
+  uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
+  TU_LOG2_HEX(revision);
+  TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
+
+  // reset
+  reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
+  reg_write(rhport, USBCTL_ADDR, 0, false);
+  while( !(reg_read(rhport, USBIRQ_ADDR, false) & USBIRQ_OSCOK_IRQ) ) {
+    // wait for oscillator to stabilize
+  }
+
+  // Mode: Host and DP/DM pull down
+  mode_write(rhport, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST, false);
+
+  // frame reset & bus reset, this will trigger CONDET IRQ if device is already connected
+  reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false);
+
+  // clear all previously pending IRQ
+  hirq_write(rhport, 0xff, false);
+
+  // Enable IRQ
+  hien_write(rhport, DEFAULT_HIEN, false);
+
+  tuh_max3421_int_api(rhport, true);
+
+  // Enable Interrupt pin
+  reg_write(rhport, CPUCTL_ADDR, _tuh_cfg.cpuctl | CPUCTL_IE, false);
+
+  return true;
+}
+
+bool hcd_deinit(uint8_t rhport) {
+  (void) rhport;
+
+  // disable interrupt
+  tuh_max3421_int_api(rhport, false);
+
+  // reset max3421 and power down
+  reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
+  reg_write(rhport, USBCTL_ADDR, USBCTL_PWRDOWN, false);
+
+  #if OSAL_MUTEX_REQUIRED
+  osal_mutex_delete(_hcd_data.spi_mutex);
+  _hcd_data.spi_mutex = NULL;
+  #endif
+
+  return true;
+}
+
+// Enable USB interrupt
+// Not actually enable GPIO interrupt, just set variable to prevent handler to process
+void hcd_int_enable (uint8_t rhport) {
+  tuh_max3421_int_api(rhport, true);
+}
+
+// Disable USB interrupt
+// Not actually disable GPIO interrupt, just set variable to prevent handler to process
+void hcd_int_disable(uint8_t rhport) {
+  tuh_max3421_int_api(rhport, false);
+}
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport) {
+  (void) rhport;
+  return (uint32_t ) _hcd_data.frame_count;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport) {
+  (void) rhport;
+  return (_hcd_data.mode & MODE_SOFKAENAB) ? true : false;
+}
+
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
+void hcd_port_reset(uint8_t rhport) {
+  reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, false);
+}
+
+// Complete bus reset sequence, may be required by some controllers
+void hcd_port_reset_end(uint8_t rhport) {
+  reg_write(rhport, HCTL_ADDR, 0, false);
+}
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  (void) rhport;
+  return (_hcd_data.mode & MODE_LOWSPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
+}
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc) {
+  (void) rhport;
+
+  uint8_t const ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
+  tusb_dir_t const ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
+
+  max3421_ep_t * ep;
+  if (daddr == 0 && ep_num == 0) {
+    ep = &_hcd_data.ep[0];
+  }else {
+    ep = allocate_ep();
+    TU_ASSERT(ep);
+    ep->daddr = daddr;
+    ep->hxfr_bm.ep_num = (uint8_t) (ep_num & 0x0f);
+    ep->hxfr_bm.is_out = (ep_dir == TUSB_DIR_OUT) ? 1 : 0;
+    ep->hxfr_bm.is_iso = (TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer) ? 1 : 0;
+  }
+
+  ep->packet_size = (uint16_t) (tu_edpt_packet_size(ep_desc) & 0x7ff);
+
+  return true;
+}
+
+/* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes.
+ * Then the microcontroller writes the SNDBC register, which this does three things:
+ * 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send.
+ * 2. Connects the SNDFIFO and SNDBC register to the USB logic for USB transmission.
+ * 3. Clears the SNDBAVIRQ interrupt flag. If the second FIFO is available for ÂĩC loading, the SNDBAVIRQ immediately re-asserts.
+
+                                               +-----------+
+                                           --->| SNDBC-A   |
+                                          /    | SNDFIFO-A |
+                                         /     +-----------+
+      +------+       +-------------+    /                              +----------+
+      | MCU  |------>| R2: SNDFIFO |----     << Write R7 Flip >>    ---| MAX3241E |
+      |(hcd) |       | R7: SNDBC   |                               /   |   SIE    |
+      +------+       +-------------+                              /    +----------+
+                                              +-----------+      /
+                                               | SNDBC-B   |    /
+                                               | SNDFIFO-B |<---
+                                               +-----------+
+  Note: xact_out() is called when starting a new transfer, continue a transfer (isr) or retry a transfer (NAK)
+        For NAK retry, we do not need to write to FIFO or SNDBC register again.
+*/
+static void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  // Page 12: Programming BULK-OUT Transfers
+  // TODO: double buffering for ISO transfer
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+    const uint8_t hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+  }
+
+  // Only write to sndfifo and sdnbc register if it is not a NAKed retry
+  if (!(ep->daddr == _hcd_data.sndfifo_owner.daddr && ep->hxfr == _hcd_data.sndfifo_owner.hxfr)) {
+    // skip SNDBAV IRQ check, overwrite sndfifo if needed
+    const uint8_t xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+    hwfifo_send(rhport, ep->buf, xact_len, in_isr);
+  }
+  _hcd_data.sndfifo_owner.daddr = ep->daddr;
+  _hcd_data.sndfifo_owner.hxfr = ep->hxfr;
+
+  hxfr_write(rhport, ep->hxfr, in_isr);
+}
+
+static void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  // Page 13: Programming BULK-IN Transfers
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+
+    uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+  }
+
+  hxfr_write(rhport, ep->hxfr, in_isr);
+}
+
+static void xact_setup(uint8_t rhport, max3421_ep_t *ep, bool in_isr) {
+  peraddr_write(rhport, ep->daddr, in_isr);
+  hwfifo_setup(rhport, ep->buf, in_isr);
+  hxfr_write(rhport, HXFR_SETUP, in_isr);
+}
+
+static void xact_generic(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  if (ep->hxfr_bm.ep_num == 0 ) {
+    // setup
+    if (ep->hxfr_bm.is_setup) {
+      xact_setup(rhport, ep, in_isr);
+      return;
+    }
+
+    // status
+    if (ep->buf == NULL || ep->total_len == 0) {
+      const uint8_t hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN));
+      peraddr_write(rhport, ep->daddr, in_isr);
+      hxfr_write(rhport, hxfr, in_isr);
+      return;
+    }
+  }
+
+  if (ep->hxfr_bm.is_out) {
+    xact_out(rhport, ep, switch_ep, in_isr);
+  }else {
+    xact_in(rhport, ep, switch_ep, in_isr);
+  }
+}
+
+// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
+  max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
+  TU_VERIFY(ep);
+
+  if (ep_num == 0) {
+    // control transfer can switch direction
+    ep->hxfr_bm.is_out = ep_dir ? 0 : 1;
+    ep->hxfr_bm.is_setup = 0;
+    ep->data_toggle = 1;
+  }
+
+  ep->buf = buffer;
+  ep->total_len = buflen;
+  ep->xferred_len = 0;
+  ep->state = EP_STATE_ATTEMPT_1;
+
+  // carry out transfer if not busy
+  if (!atomic_flag_test_and_set(&_hcd_data.busy)) {
+    xact_generic(rhport, ep, true, false);
+  }
+
+  return true;
+}
+
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
+  max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
+  TU_VERIFY(ep);
+
+  if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) {
+    hcd_int_disable(rhport);
+    ep->state = EP_STATE_ABORTING;
+    hcd_int_enable(rhport);
+  }
+
+  return true;
+}
+
+// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
+  (void) rhport;
+
+  max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
+  TU_ASSERT(ep);
+
+  ep->hxfr_bm.is_out = 1;
+  ep->hxfr_bm.is_setup = 1;
+  ep->buf = (uint8_t*)(uintptr_t) setup_packet;
+  ep->total_len = 8;
+  ep->xferred_len = 0;
+  ep->state = EP_STATE_ATTEMPT_1;
+
+  // carry out transfer if not busy
+  if (!atomic_flag_test_and_set(&_hcd_data.busy)) {
+    xact_setup(rhport, ep, false);
+  }
+
+  return true;
+}
+
+// clear stall, data toggle is also reset to DATA0
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+//--------------------------------------------------------------------+
+// Interrupt Handler
+//--------------------------------------------------------------------+
+
+static void handle_connect_irq(uint8_t rhport, bool in_isr) {
+  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
+  uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
+
+  uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
+  TU_LOG2_HEX(jk);
+
+  switch(jk) {
+    case 0x00:                          // SEO is disconnected
+    case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal
+      mode_write(rhport, new_mode, in_isr);
+
+      // port reset anyway, this will help to stable bus signal for next connection
+      reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, in_isr);
+      hcd_event_device_remove(rhport, in_isr);
+      reg_write(rhport, HCTL_ADDR, 0, in_isr);
+      break;
+
+    default: {
+      // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset
+      if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) {
+        break;
+      }
+
+      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
+      // However, since we are always in full speed mode, we can just check J-state
+      if (jk == HRSL_KSTATUS) {
+        new_mode |= MODE_LOWSPEED;
+        TU_LOG3("Low speed\r\n");
+      }else {
+        TU_LOG3("Full speed\r\n");
+      }
+      new_mode |= MODE_SOFKAENAB;
+      mode_write(rhport, new_mode, in_isr);
+
+      // FIXME multiple MAX3421 rootdevice address is not 1
+      uint8_t const daddr = 1;
+      free_ep(daddr);
+
+      hcd_event_device_attach(rhport, in_isr);
+      break;
+    }
+  }
+}
+
+static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl, bool in_isr) {
+  uint8_t const ep_dir = 1-ep->hxfr_bm.is_out;
+  uint8_t const ep_addr = tu_edpt_addr(ep->hxfr_bm.ep_num, ep_dir);
+
+  // save data toggle
+  if (ep_dir) {
+    ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1u : 0u;
+  }else {
+    ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1u : 0u;
+  }
+
+  ep->state = EP_STATE_IDLE;
+  hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, in_isr);
+
+  // Find next pending endpoint
+  max3421_ep_t * next_ep = find_next_pending_ep(ep);
+  if (next_ep) {
+    xact_generic(rhport, next_ep, true, in_isr);
+  }else {
+    // no more pending
+    atomic_flag_clear(&_hcd_data.busy);
+  }
+}
+
+static void handle_xfer_done(uint8_t rhport, bool in_isr) {
+  const uint8_t hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
+  const uint8_t hresult = hrsl & HRSL_RESULT_MASK;
+  const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num;
+  const uint8_t hxfr_type = _hcd_data.hxfr & 0xf0;
+  const uint8_t ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
+
+  max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
+  TU_VERIFY(ep, );
+
+  xfer_result_t xfer_result;
+  switch(hresult) {
+    case HRSL_NAK:
+      if (ep->state == EP_STATE_ABORTING) {
+        ep->state = EP_STATE_IDLE;
+      } else {
+        if (ep_num == 0) {
+          // control endpoint -> retry immediately and return
+          hxfr_write(rhport, _hcd_data.hxfr, in_isr);
+          return;
+        }
+        if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) {
+          ep->state++;
+        }
+      }
+
+      max3421_ep_t * next_ep = find_next_pending_ep(ep);
+      if (ep == next_ep) {
+        // this endpoint is only one pending -> retry immediately
+        hxfr_write(rhport, _hcd_data.hxfr, in_isr);
+      } else if (next_ep) {
+        // switch to next pending endpoint
+        xact_generic(rhport, next_ep, true, in_isr);
+      } else {
+        // no more pending in this frame -> clear busy
+        atomic_flag_clear(&_hcd_data.busy);
+      }
+      return;
+
+    case HRSL_BAD_REQ:
+      // occurred when initialized without any pending transfer. Skip for now
+      return;
+
+    case HRSL_SUCCESS:
+      xfer_result = XFER_RESULT_SUCCESS;
+      break;
+
+    case HRSL_STALL:
+      xfer_result = XFER_RESULT_STALLED;
+      break;
+
+    default:
+      TU_LOG3("HRSL: %02X\r\n", hrsl);
+      xfer_result = XFER_RESULT_FAILED;
+      break;
+  }
+
+  if (xfer_result != XFER_RESULT_SUCCESS) {
+    xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
+    return;
+  }
+
+  if (ep_dir) {
+    // IN transfer: fifo data is already received in RCVDAV IRQ
+
+    // mark control handshake as complete
+    if (hxfr_type & HXFR_HS) {
+      ep->state = EP_STATE_COMPLETE;
+    }
+
+    // short packet or all bytes transferred
+    if (ep->state == EP_STATE_COMPLETE) {
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
+    }else {
+      hxfr_write(rhport, _hcd_data.hxfr, in_isr); // more to transfer
+    }
+  } else {
+    // SETUP or OUT transfer
+
+    // clear sndfifo owner since data is sent
+    _hcd_data.sndfifo_owner.daddr = 0xff;
+    _hcd_data.sndfifo_owner.hxfr = 0xff;
+
+    uint8_t xact_len;
+
+    if (hxfr_type & HXFR_SETUP) {
+      xact_len = 8;
+    } else if (hxfr_type & HXFR_HS) {
+      xact_len = 0;
+    } else {
+      xact_len = _hcd_data.sndbc;
+    }
+
+    ep->xferred_len += xact_len;
+    ep->buf += xact_len;
+
+    if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
+    } else {
+      xact_out(rhport, ep, false, in_isr); // more to transfer
+    }
+  }
+}
+
+#if CFG_TUSB_DEBUG >= 3
+void print_hirq(uint8_t hirq) {
+  TU_LOG3_HEX(hirq);
+
+  if (hirq & HIRQ_HXFRDN_IRQ)   TU_LOG3(" HXFRDN");
+  if (hirq & HIRQ_FRAME_IRQ)    TU_LOG3(" FRAME");
+  if (hirq & HIRQ_CONDET_IRQ)   TU_LOG3(" CONDET");
+  if (hirq & HIRQ_SUSDN_IRQ)    TU_LOG3(" SUSDN");
+  if (hirq & HIRQ_SNDBAV_IRQ)   TU_LOG3(" SNDBAV");
+  if (hirq & HIRQ_RCVDAV_IRQ)   TU_LOG3(" RCVDAV");
+  if (hirq & HIRQ_RWU_IRQ)      TU_LOG3(" RWU");
+  if (hirq & HIRQ_BUSEVENT_IRQ) TU_LOG3(" BUSEVENT");
+
+  TU_LOG3("\r\n");
+}
+#else
+  #define print_hirq(hirq)
+#endif
+
+// Interrupt handler
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, in_isr) & _hcd_data.hien;
+  if (!hirq) return;
+//  print_hirq(hirq);
+
+  if (hirq & HIRQ_FRAME_IRQ) {
+    _hcd_data.frame_count++;
+
+    // reset all endpoints nak counter, retry with 1st pending ep.
+    max3421_ep_t* ep_retry = NULL;
+    for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+      max3421_ep_t* ep = &_hcd_data.ep[i];
+      if (ep->packet_size && ep->state > EP_STATE_ATTEMPT_1) {
+        ep->state = EP_STATE_ATTEMPT_1;
+
+        if (ep_retry == NULL) {
+          ep_retry = ep;
+        }
+      }
+    }
+
+    // start usb transfer if not busy
+    if (ep_retry != NULL && !atomic_flag_test_and_set(&_hcd_data.busy)) {
+      xact_generic(rhport, ep_retry, true, in_isr);
+    }
+  }
+
+  if (hirq & HIRQ_CONDET_IRQ) {
+    handle_connect_irq(rhport, in_isr);
+  }
+
+  // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or
+  // not call this handler again. So we need to loop until all IRQ are cleared
+  while (hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ)) {
+    if (hirq & HIRQ_RCVDAV_IRQ) {
+      const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num;
+      max3421_ep_t* ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
+      uint8_t xact_len = 0;
+
+      // RCVDAV_IRQ can trigger 2 times (dual buffered)
+      while (hirq & HIRQ_RCVDAV_IRQ) {
+        const uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr);
+        xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
+        if (xact_len) {
+          hwfifo_receive(rhport, ep->buf, xact_len, in_isr);
+          ep->buf += xact_len;
+          ep->xferred_len += xact_len;
+        }
+
+        // ack RCVDVAV IRQ
+        hirq_write(rhport, HIRQ_RCVDAV_IRQ, in_isr);
+        hirq = reg_read(rhport, HIRQ_ADDR, in_isr);
+      }
+
+      if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
+        ep->state = EP_STATE_COMPLETE;
+      }
+    }
+
+    if (hirq & HIRQ_HXFRDN_IRQ) {
+      hirq_write(rhport, HIRQ_HXFRDN_IRQ, in_isr);
+      handle_xfer_done(rhport, in_isr);
+    }
+
+    hirq = reg_read(rhport, HIRQ_ADDR, in_isr);
+  }
+
+  // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
+  hirq &= (uint8_t) ~HIRQ_SNDBAV_IRQ;
+  if (hirq) {
+    hirq_write(rhport, hirq, in_isr);
+  }
+}
+
+#endif
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 2445593fe..34a8be3b6 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright 2021 Bridgetek Pte Ltd
@@ -24,23 +24,20 @@
  * This file is part of the TinyUSB stack.
  */
 
-/* 
- * Contains code adapted from Bridgetek Pte Ltd via license terms stated 
+/*
+ * Contains code adapted from Bridgetek Pte Ltd via license terms stated
  * in https://brtchip.com/BRTSourceCodeLicenseAgreement
  */
 
 #include "tusb_option.h"
 
 #if CFG_TUD_ENABLED && \
-  (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X) 
+  (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X)
 
 #include <stdint.h>
 #include <ft900.h>
 #include <registers/ft900_registers.h>
 
-#include "board.h"
-#include "bsp/board.h"
-
 #define USBD_USE_STREAMS
 
 #include "device/dcd.h"
@@ -50,17 +47,21 @@
 //--------------------------------------------------------------------+
 
 // Board code will determine the state of VBUS from USB host.
-extern int8_t board_ft90x_vbus(void);
+extern int8_t board_ft9xx_vbus(void);
+extern int board_uart_write(void const *buf, int len);
 
 // Static array to store an incoming SETUP request for processing by tinyusb.
-static uint8_t _ft90x_setup_packet[8];
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN
+static uint8_t _ft9xx_setup_packet[8];
 
-struct ft90x_xfer_state
+struct ft9xx_xfer_state
 {
+  volatile uint8_t ready; // OUT Transfer has been received and waiting for transfer.
   volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
-  volatile int16_t total_size; // Total transfer size in bytes for this transfer.
-  volatile int16_t remain_size; // Total remaining in transfer.
-  volatile uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
+
+  int16_t total_size; // Total transfer size in bytes for this transfer.
+  int16_t remain_size; // Total remaining in transfer.
+  uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
 
   uint8_t type; // Endpoint type. Of type USBD_ENDPOINT_TYPE from endpoint descriptor.
   uint8_t dir; // Endpoint direction. TUSB_DIR_OUT or TUSB_DIR_IN. For control endpoint this is the current direction.
@@ -68,32 +69,32 @@ struct ft90x_xfer_state
   uint16_t size; // Max packet size for endpoint from endpoint descriptor.
 };
 // Endpoint description array for each endpoint.
-static struct ft90x_xfer_state ep_xfer[USBD_MAX_ENDPOINT_COUNT];
+static struct ft9xx_xfer_state ep_xfer[USBD_MAX_ENDPOINT_COUNT];
 // USB speed.
 static tusb_speed_t _speed;
 
 // Interrupt handlers.
-void _ft90x_usbd_ISR(void); // Interrupt handler for USB device.
-void ft90x_usbd_pm_ISR(void); // Interrupt handler for USB device for power management (called by board).
+void _ft9xx_usbd_ISR(void); // Interrupt handler for USB device.
+void ft9xx_usbd_pm_ISR(void); // Interrupt handler for USB device for power management (called by board).
 
 // Internal functions forward declarations.
-static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
-static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
-static void _ft90x_reset_edpts(void);
-static inline void _ft90x_phy_enable(bool en);
-static void _ft90x_usb_speed(void);
-static void _dcd_ft90x_attach(void);
-static void _dcd_ft90x_detach(void) __attribute__((unused));
-static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length);
-static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length);
+static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
+static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
+static void _ft9xx_reset_edpts(void);
+static inline void _ft9xx_phy_enable(bool en);
+static void _ft9xx_usb_speed(void);
+static void _dcd_ft9xx_attach(void);
+static void _dcd_ft9xx_detach(void) __attribute__((unused));
+static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length);
+static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length);
 
 // Internal functions.
 
 // Manage an OUT transfer from the host.
 // This can be up-to the maximum packet size of the endpoint.
-// Continuation of a transfer beyond the maximum packet size is performed 
+// Continuation of a transfer beyond the maximum packet size is performed
 // by the interrupt handler.
-static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
+static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
 {
   //Note: this is called from only the interrupt handler when an OUT transfer is called.
   uint16_t ep_size = ep_xfer[ep_number].size;
@@ -108,7 +109,7 @@ static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_
     //;
 
   // Send the first packet of max packet size
-  xfer_bytes = _ft90x_dusb_out(ep_number, (uint8_t *)buffer, xfer_bytes);
+  xfer_bytes = _ft9xx_dusb_out(ep_number, (uint8_t *)buffer, xfer_bytes);
   if (ep_number == USBD_EP_0)
   {
     // Set flags to indicate data ready.
@@ -124,9 +125,9 @@ static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_
 
 // Manage an IN transfer to the host.
 // This can be up-to the maximum packet size of the endpoint.
-// Continuation of a transfer beyond the maximum packet size is performed 
+// Continuation of a transfer beyond the maximum packet size is performed
 // by the interrupt handler.
-static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
+static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
 {
   //Note: this may be called from the interrupt handler or from normal code.
   uint8_t end = 0;
@@ -154,17 +155,24 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
   }
   else
   {
-    uint8_t sr_reg;
     // If there is data to transmit then wait until the IN buffer
     // for the endpoint is empty.
-    do
+    // This does not apply to interrupt endpoints.
+    if (ep_xfer[ep_number].type != TUSB_XFER_INTERRUPT)
     {
-      sr_reg = USBD_EP_SR_REG(ep_number);
-    } while (sr_reg & MASK_USBD_EPxSR_INPRDY);
-    
+      uint8_t sr_reg;
+      do
+      {
+        sr_reg = USBD_EP_SR_REG(ep_number);
+      } while (sr_reg & MASK_USBD_EPxSR_INPRDY);
+    }
   }
 
-  xfer_bytes = _ft90x_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes);
+  // Do not send a ZLP for interrupt endpoints.
+  if ((ep_xfer[ep_number].type != TUSB_XFER_INTERRUPT) || (xfer_bytes > 0))
+  {
+    xfer_bytes = _ft9xx_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes);
+  }
 
   if (ep_number == USBD_EP_0)
   {
@@ -188,25 +196,25 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
   return xfer_bytes;
 }
 
-// Reset all non-control endpoints to a default state. 
+// Reset all non-control endpoints to a default state.
 // Control endpoint is always enabled and ready. All others disabled.
-static void _ft90x_reset_edpts(void)
+static void _ft9xx_reset_edpts(void)
 {
   // Disable all endpoints and remove configuration values.
   for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++)
   {
     // Clear settings.
-    tu_memclr(&ep_xfer[i], sizeof(struct ft90x_xfer_state));
+    tu_memclr(&ep_xfer[i], sizeof(struct ft9xx_xfer_state));
     // Disable hardware.
     USBD_EP_CR_REG(i) = 0;
   }
-  
+
   // Enable interrupts from USB device control.
   USBD_REG(cmie) = MASK_USBD_CMIE_ALL;
 }
 
 // Enable or disable the USB PHY.
-static inline void _ft90x_phy_enable(bool en)
+static inline void _ft9xx_phy_enable(bool en)
 {
   if (en)
     SYS->PMCFG_L |= MASK_SYS_PMCFG_DEV_PHY_EN;
@@ -215,7 +223,7 @@ static inline void _ft90x_phy_enable(bool en)
 }
 
 // Safely connect to the USB.
-static void _dcd_ft90x_attach(void)
+static void _dcd_ft9xx_attach(void)
 {
   uint8_t reg;
 
@@ -271,7 +279,7 @@ static void _dcd_ft90x_attach(void)
 }
 
 // Gracefully disconnect from the USB.
-static void _dcd_ft90x_detach(void)
+static void _dcd_ft9xx_detach(void)
 {
   // Disable device connect/disconnect/host reset detection.
   SYS->PMCFG_L = SYS->PMCFG_L & (~MASK_SYS_PMCFG_DEV_DETECT_EN);
@@ -311,9 +319,9 @@ static void _dcd_ft90x_detach(void)
 }
 
 // Determine the speed of the USB to which we are connected.
-// Set the speed of the PHY accordingly. 
+// Set the speed of the PHY accordingly.
 // High speed can be disabled through CFG_TUSB_RHPORT0_MODE or CFG_TUD_MAX_SPEED settings.
-static void _ft90x_usb_speed(void)
+static void _ft9xx_usb_speed(void)
 {
 	uint8_t  fctrl_val;
 
@@ -371,16 +379,16 @@ static void _ft90x_usb_speed(void)
 }
 
 // Send a buffer to the USB IN FIFO.
-// When the macro USBD_USE_STREAMS is defined this will stream a buffer of data 
+// When the macro USBD_USE_STREAMS is defined this will stream a buffer of data
 // to the FIFO using the most efficient MCU streamout combination.
-// If streaming is disabled then it will send each byte of the buffer in turn 
+// If streaming is disabled then it will send each byte of the buffer in turn
 // to the FIFO. The is no reason to not stream.
 // The total number of bytes sent to the FIFO is returned.
-static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length)
+static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length)
 {
   uint16_t bytes_read = 0;
   uint16_t buff_size = length;
-  
+
 #ifdef USBD_USE_STREAMS
   volatile uint8_t *data_reg;
 
@@ -415,7 +423,7 @@ static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_
     bytes_read = buff_size;
   }
 #else // USBD_USE_STREAMS
-  
+
   bytes_read = buff_size;
   while (buff_size--)
   {
@@ -430,17 +438,17 @@ static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_
 // Receive a buffer from the USB OUT FIFO.
 // When the macro USBD_USE_STREAMS is defined this will stream from the FIFO
 // to a buffer of data using the most efficient MCU streamin combination.
-// If streaming is disabled then it will receive each byte from the FIFO in turn 
+// If streaming is disabled then it will receive each byte from the FIFO in turn
 // to the buffer. The is no reason to not stream.
 // The total number of bytes received from the FIFO is returned.
-static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length)
+static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length)
 {
 #ifdef USBD_USE_STREAMS
   volatile uint8_t *data_reg;
 #endif // USBD_USE_STREAMS
   uint16_t bytes_read = 0;
   uint16_t buff_size = length;
-  
+
   if (length > 0)
   {
     if (ep_number == USBD_EP_0)
@@ -509,22 +517,23 @@ static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len
  *------------------------------------------------------------------*/
 
 // Initialize controller to device mode
-void dcd_init(uint8_t rhport)
-{
-  TU_LOG2("FT90x initialisation\r\n");
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+  TU_LOG2("FT9xx initialisation\r\n");
 
-  _dcd_ft90x_attach();
+  _dcd_ft9xx_attach();
 
-  interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft90x_usbd_ISR);
+  interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft9xx_usbd_ISR);
 
   dcd_connect(rhport);
+  return true;
 }
 
 // Enable device interrupt
 void dcd_int_enable(uint8_t rhport)
 {
   (void)rhport;
-  TU_LOG3("FT90x int enable\r\n");
+  TU_LOG3("FT9xx int enable\r\n");
 
   // Peripheral devices interrupt enable.
   interrupt_enable_globally();
@@ -534,7 +543,7 @@ void dcd_int_enable(uint8_t rhport)
 void dcd_int_disable(uint8_t rhport)
 {
   (void)rhport;
-  TU_LOG3("FT90x int disable\r\n");
+  TU_LOG3("FT9xx int disable\r\n");
 
   // Peripheral devices interrupt disable.
   interrupt_disable_globally();
@@ -587,8 +596,8 @@ void dcd_remote_wakeup(uint8_t rhport)
 
   SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
 
-  // Atleast 2 ms of delay needed for RESUME Data K state.
-  delayms(2); 
+  // At least 2 ms of delay needed for RESUME Data K state.
+  delayms(2);
 
   SYS->MSC0CFG &= ~MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
 
@@ -600,20 +609,20 @@ void dcd_remote_wakeup(uint8_t rhport)
 void dcd_connect(uint8_t rhport)
 {
   (void)rhport;
-  TU_LOG2("FT90x connect\r\n");
+  TU_LOG2("FT9xx connect\r\n");
 
   CRITICAL_SECTION_BEGIN
   // Is device connected?
-  if (board_ft90x_vbus())
+  if (board_ft9xx_vbus())
   {
     // Clear/disable address register.
     USBD_REG(faddr) = 0;
-    _ft90x_phy_enable(true);
+    _ft9xx_phy_enable(true);
 
     // Determine bus speed and signal speed to tusb.
-    _ft90x_usb_speed();
+    _ft9xx_usb_speed();
   }
-  
+
   // Setup the control endpoint only.
 #if CFG_TUD_ENDPOINT0_SIZE == 64
   USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_64 << BIT_USBD_EP0_MAX_SIZE);
@@ -636,17 +645,17 @@ void dcd_connect(uint8_t rhport)
   USBD_REG(epie) = (MASK_USBD_EPIE_EP0IE);
 
   // Restore default endpoint state.
-  _ft90x_reset_edpts();
+  _ft9xx_reset_edpts();
 }
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
 void dcd_disconnect(uint8_t rhport)
 {
   (void)rhport;
-  TU_LOG2("FT90x disconnect\r\n");
+  TU_LOG2("FT9xx disconnect\r\n");
 
   // Disable the USB PHY.
-  _ft90x_phy_enable(false);
+  _ft9xx_phy_enable(false);
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -674,12 +683,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
   uint8_t ep_reg_data = 0;
   int16_t total_ram;
 
-  TU_LOG2("FT90x endpoint open %d %c\r\n", ep_number, ep_dir?'I':'O');
+  TU_LOG2("FT9xx endpoint open %d %c\r\n", ep_number, ep_dir?'I':'O');
 
   // Check that the requested endpoint number is allowable.
   if (ep_number >= USBD_MAX_ENDPOINT_COUNT)
   {
-    TU_LOG1("FT90x endpoint not valid: requested %d max %d\r\n", ep_number, USBD_MAX_ENDPOINT_COUNT);
+    TU_LOG1("FT9xx endpoint not valid: requested %d max %d\r\n", ep_number, USBD_MAX_ENDPOINT_COUNT);
     return false;
   }
 
@@ -691,10 +700,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
   }
   if (ep_reg_size > USBD_EP_MAX_SIZE_1024)
   {
-    TU_LOG1("FT90x endpoint size not valid: requested %d max 1024\r\n", ep_size);
+    TU_LOG1("FT9xx endpoint size not valid: requested %d max 1024\r\n", ep_size);
     return false;
   }
-  // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the 
+  // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the
   // requested size.
   ep_buff_size = 8 << ep_reg_size;
 
@@ -706,21 +715,21 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     if (ep_xfer[ep_number].type != USBD_EP_TYPE_DISABLED)
     {
       // This could be because an endpoint has been assigned with the same number.
-      // On FT90x, IN and OUT endpoints may not have the same number. e.g. There 
+      // On FT9xx, IN and OUT endpoints may not have the same number. e.g. There
       // cannot been an 0x81 and 0x01 endpoint.
-      TU_LOG1("FT90x endpoint %d already assigned\r\n", ep_number);
+      TU_LOG1("FT9xx endpoint %d already assigned\r\n", ep_number);
       return false;
     }
 
     // Check that there is enough buffer RAM to allocate to this new endpoint.
     // Available buffer RAM depends on the device revision.
     // The IN and OUT buffer RAM should be the same size.
-    if (ep_dir == USBD_DIR_IN) 
+    if (ep_dir == USBD_DIR_IN)
       total_ram = USBD_RAMTOTAL_IN;
     else
       total_ram = USBD_RAMTOTAL_OUT;
     // Work out how much has been allocated to existing endpoints.
-    // The total RAM allocated shoudl alsyes be a positive number as this
+    // The total RAM allocated should always be a positive number as this
     // algorithm should not let it go below zero.
     for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++)
     {
@@ -732,23 +741,28 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
         }
       }
     }
-    // The control endpoint is taken into account as well.
-    total_ram -= ep_xfer[0].buff_size;
+
+    if (sys_check_ft900_revB())
+    {
+      // The control endpoint is taken into account as well on RevB silicon.
+      total_ram -= ep_xfer[0].buff_size;
+    }
+
     // Make sure we have enough space. The corner case is having zero bytes
     // free which means that total_ram must be signed as zero bytes free is
     // allowable.
     if (total_ram < ep_buff_size)
     {
-      TU_LOG1("FT90x insufficient buffer RAM for endpoint %d\r\n", ep_number);
-      return false;    
+      TU_LOG1("FT9xx insufficient buffer RAM for endpoint %d\r\n", ep_number);
+      return false;
     }
 
     // Set the type of this endpoint in the control register.
-    if (ep_type == USBD_EP_BULK)
+    if (ep_type == TUSB_XFER_BULK)
       ep_reg_data |= (USBD_EP_DIS_BULK << BIT_USBD_EP_CONTROL_DIS);
-    else if (ep_type == USBD_EP_INT)
+    else if (ep_type == TUSB_XFER_INTERRUPT)
       ep_reg_data |= (USBD_EP_DIS_INT << BIT_USBD_EP_CONTROL_DIS);
-    else if (ep_type == USBD_EP_ISOC)
+    else if (ep_type == TUSB_XFER_ISOCHRONOUS)
       ep_reg_data |= (USBD_EP_DIS_ISO << BIT_USBD_EP_CONTROL_DIS);
     // Set the direction of this endpoint in the control register.
     if (ep_dir == USBD_DIR_IN)
@@ -756,9 +770,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     // Do not perform double buffering.
     //if (<double buffering flag> != USBD_DB_OFF)
     //ep_reg_data |= MASK_USBD_EPxCR_DB;
-    // Set the control endpoint for this endpoint.
+    // Set the control register for this endpoint.
     USBD_EP_CR_REG(ep_number) = ep_reg_data;
-    TU_LOG2("FT90x endpoint setting %x\r\n", ep_reg_data);
+    TU_LOG2("FT9xx endpoint setting %x\r\n", ep_reg_data);
   }
   else
   {
@@ -766,14 +780,15 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     USBD_EP_CR_REG(USBD_EP_0) = (ep_reg_size << BIT_USBD_EP0_MAX_SIZE);
   }
 
+  CRITICAL_SECTION_BEGIN
   // Store the endpoint characteristics for later reference.
   ep_xfer[ep_number].dir = ep_dir;
   ep_xfer[ep_number].type = ep_type;
   ep_xfer[ep_number].size = ep_size;
   ep_xfer[ep_number].buff_size = ep_buff_size;
 
-  CRITICAL_SECTION_BEGIN
   // Clear register transaction continuation and signalling state.
+  ep_xfer[ep_number].ready = 0;
   ep_xfer[ep_number].valid = 0;
   ep_xfer[ep_number].buff_ptr = NULL;
   ep_xfer[ep_number].total_size = 0;
@@ -788,7 +803,7 @@ void dcd_edpt_close_all(uint8_t rhport)
 {
   (void)rhport;
   // Reset the endpoint configurations.
-  _ft90x_reset_edpts();
+  _ft9xx_reset_edpts();
 }
 
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
@@ -796,7 +811,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
 {
   (void)rhport;
   uint8_t ep_number = tu_edpt_number(ep_addr);
-  uint8_t dir = tu_edpt_dir(ep_addr);
+  uint8_t ep_dir = tu_edpt_dir(ep_addr);
   uint16_t xfer_bytes;
   bool status = false;
 
@@ -806,19 +821,17 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
   // ep_xfer is used to tell the interrupt handler what to do.
   // ep_xfer can be used at interrupt level to continue transfers.
   CRITICAL_SECTION_BEGIN
+
   // Transfer currently in progress.
   if (ep_xfer[ep_number].valid == 0)
   {
-    status = true;
-
     ep_xfer[ep_number].total_size = total_bytes;
     ep_xfer[ep_number].remain_size = total_bytes;
     ep_xfer[ep_number].buff_ptr = buffer;
-    ep_xfer[ep_number].valid = 1;
-    
+
     if (ep_number == USBD_EP_0)
     {
-      ep_xfer[USBD_EP_0].dir = dir;
+      ep_xfer[USBD_EP_0].dir = ep_dir;
     }
     else
     {
@@ -827,18 +840,53 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
       USBD_REG(epie) = USBD_REG(epie) | (1 << ep_number);
     }
 
-    if (dir == TUSB_DIR_IN)
+    if (ep_dir == TUSB_DIR_IN)
     {
       // For IN transfers send the first packet as a starter. Interrupt handler to complete
       // this if it is larger than one packet.
-      xfer_bytes = _ft90x_edpt_xfer_in(ep_number, buffer, total_bytes);
+      xfer_bytes = _ft9xx_edpt_xfer_in(ep_number, buffer, total_bytes);
 
       ep_xfer[ep_number].buff_ptr += xfer_bytes;
       ep_xfer[ep_number].remain_size -= xfer_bytes;
+
+      // Tell the interrupt handler to signal dcd_event_xfer_complete on completion.
+      ep_xfer[ep_number].valid = 1;
     }
+    else // (dir == TUSB_DIR_OUT)
+    {
+      // For OUT transfers on the control endpoint.
+      // The host may already have performed the first data transfer after the SETUP packet
+      // before the transfer is setup for it.
+      if (ep_xfer[ep_number].ready)
+      {
+        // We have received a data packet on the endpoint without a transfer
+        // being initialised. This can be because the host has sent this packet before
+        // a new transfer has been initiated on the endpoint.
+        // We will now stream the data from the FIFO.
+        ep_xfer[ep_number].ready = 0;
+
+        // Transfer incoming data from an OUT packet to the buffer.
+        xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, buffer, total_bytes);
+
+        // Report completion of the transfer.
+        dcd_event_xfer_complete(BOARD_TUD_RHPORT, ep_number /*| TUSB_DIR_OUT_MASK */, xfer_bytes, XFER_RESULT_SUCCESS, false);
+      }
+      else
+      {
+        // Tell the interrupt handler to wait for the packet to be received and
+        // then report the transfer complete with dcd_event_xfer_complete.
+        ep_xfer[ep_number].valid = 1;
+      }
+    }
+    status = true;
   }
+  else
+  {
+    // Note: should not arrive here.
+  }
+
   CRITICAL_SECTION_END
-  
+
   return status;
 }
 
@@ -875,7 +923,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   CRITICAL_SECTION_END
 }
 
-// Clear stall (non-control endpoint), data toggle is also reset to DATA0 
+// Clear stall (non-control endpoint), data toggle is also reset to DATA0
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t ep_number = tu_edpt_number(ep_addr);
@@ -889,6 +937,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
     USBD_EP_SR_REG(ep_number) = MASK_USBD_EPxSR_CLR_TOGGLE;
 
     // Allow transfers to restart.
+    ep_xfer[ep_number].ready = 0;
     ep_xfer[ep_number].valid = 0;
     ep_xfer[ep_number].remain_size = 0;
     CRITICAL_SECTION_END
@@ -897,9 +946,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
 // Interrupt handling.
 
-void _ft90x_usbd_ISR(void)
+void _ft9xx_usbd_ISR(void)
 {
-  tud_int_handler(BOARD_TUD_RHPORT); // Resolves to dcd_int_handler().
+  dcd_int_handler(BOARD_TUD_RHPORT);
 }
 
 void dcd_int_handler(uint8_t rhport)
@@ -936,7 +985,7 @@ void dcd_int_handler(uint8_t rhport)
     if (cmif & MASK_USBD_CMIF_RSTIRQ) //Handle Reset interrupt
     {
       // Reset endpoints to default state.
-      _ft90x_reset_edpts();
+      _ft9xx_reset_edpts();
       dcd_event_bus_reset(BOARD_TUD_RHPORT, _speed, true);
     }
     if (cmif & MASK_USBD_CMIF_SUSIRQ) //Handle Suspend interrupt
@@ -962,7 +1011,6 @@ void dcd_int_handler(uint8_t rhport)
     {
       // Clear interrupt register.
       USBD_REG(epif) = MASK_USBD_EPIF_EP0IRQ;
-
       // Test for an incoming SETUP request on the control endpoint.
       if (USBD_EP_SR_REG(USBD_EP_0) & MASK_USBD_EP0SR_SETUP)
       {
@@ -976,16 +1024,19 @@ void dcd_int_handler(uint8_t rhport)
           USBD_EP_SR_REG(USBD_EP_0) = MASK_USBD_EP0SR_STALL;
         }
 
-        // Host has sent a SETUP packet. Recieve this into the setup packet store.
-        _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request));
-        
+        // Host has sent a SETUP packet. Receive this into the SETUP packet store.
+        _ft9xx_dusb_out(USBD_EP_0, (uint8_t *)_ft9xx_setup_packet, sizeof(USB_device_request));
+
         // Send the packet to tinyusb.
-        dcd_event_setup_received(BOARD_TUD_RHPORT, _ft90x_setup_packet, true);
+        dcd_event_setup_received(BOARD_TUD_RHPORT, _ft9xx_setup_packet, true);
 
         // Clear the interrupt that signals a SETUP packet is received.
         USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_SETUP);
 
-        // Allow new transfers on the control endpoint.
+        // Any SETUP packet will clear the incoming FIFO.
+        ep_xfer[USBD_EP_0].ready = 0;
+
+        // Allow new DATA and ACK transfers on the control endpoint.
         ep_xfer[USBD_EP_0].valid = 0;
         return;
       }
@@ -996,17 +1047,31 @@ void dcd_int_handler(uint8_t rhport)
         {
           xfer_bytes = (uint16_t)ep_xfer[USBD_EP_0].total_size;
 
-          // Transfer incoming data from an OUT packet to the buffer supplied.        
+          // Transfer incoming data from an OUT packet to the buffer supplied.
           if (ep_xfer[USBD_EP_0].dir == TUSB_DIR_OUT)
-          { 
-            xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, (uint8_t *)ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
+          {
+            xfer_bytes = _ft9xx_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
           }
           // Now signal completion of data packet.
-          dcd_event_xfer_complete(BOARD_TUD_RHPORT, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true);
+          dcd_event_xfer_complete(BOARD_TUD_RHPORT, USBD_EP_0 | (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0),
+            xfer_bytes, XFER_RESULT_SUCCESS, true);
+
+          // Incoming FIFO has been cleared.
+          ep_xfer[USBD_EP_0].ready = 0;
 
           // Allow new transfers on the control endpoint.
           ep_xfer[USBD_EP_0].valid = 0;
         }
+        // No transfer is in flight for EP0.
+        else
+        {
+          // We have received a data packet on the control endpoint without a transfer
+          // being initialised. This can be because the host has sent this packet before
+          // a new transfer has been initiated on the control endpoint.
+          // We will record that there is data in the FIFO for dcd_edpt_xfer to obtain
+          // once the transfer is initiated.
+          ep_xfer[USBD_EP_0].ready = 1;
+        }
       }
     }
     else // !(epif & MASK_USBD_EPIF_EP0IRQ)
@@ -1026,7 +1091,6 @@ void dcd_int_handler(uint8_t rhport)
         if (ep_xfer[ep_number].valid)
         {
           xfer_bytes = 0;
-          uint8_t ep_dirmask = (ep_xfer[ep_number].dir ? TUSB_DIR_IN_MASK : 0);
 
           // Clear interrupt register for this endpoint.
           USBD_REG(epif) = MASK_USBD_EPIF_IRQ(ep_number);
@@ -1034,10 +1098,15 @@ void dcd_int_handler(uint8_t rhport)
           // Start or continue an OUT transfer.
           if (ep_xfer[ep_number].dir == TUSB_DIR_OUT)
           {
-            xfer_bytes = _ft90x_edpt_xfer_out(ep_number, 
-                            (uint8_t *)ep_xfer[ep_number].buff_ptr, 
+            xfer_bytes = _ft9xx_edpt_xfer_out(ep_number,
+                            ep_xfer[ep_number].buff_ptr,
                             (uint16_t)ep_xfer[ep_number].remain_size);
 
+            // Report each OUT packet received to the stack.
+            dcd_event_xfer_complete(BOARD_TUD_RHPORT,
+                                      ep_number /* | TUSB_DIR_OUT_MASK */,
+                                      xfer_bytes, XFER_RESULT_SUCCESS, true);
+
             ep_xfer[ep_number].buff_ptr += xfer_bytes;
             ep_xfer[ep_number].remain_size -= xfer_bytes;
           }
@@ -1046,40 +1115,58 @@ void dcd_int_handler(uint8_t rhport)
           {
             if (ep_xfer[ep_number].remain_size > 0)
             {
-              xfer_bytes = _ft90x_edpt_xfer_in(ep_number, 
-                            (uint8_t *)ep_xfer[ep_number].buff_ptr, 
+              xfer_bytes = _ft9xx_edpt_xfer_in(ep_number,
+                            ep_xfer[ep_number].buff_ptr,
                             (uint16_t)ep_xfer[ep_number].remain_size);
 
               ep_xfer[ep_number].buff_ptr += xfer_bytes;
               ep_xfer[ep_number].remain_size -= xfer_bytes;
             }
+
+            if (ep_xfer[ep_number].remain_size == 0)
+            {
+              dcd_event_xfer_complete(BOARD_TUD_RHPORT,
+                                      ep_number | TUSB_DIR_IN_MASK,
+                                      ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
+            }
           }
 
           // When the transfer is complete...
           if (ep_xfer[ep_number].remain_size == 0)
           {
-            // Signal tinyUSB.
-            dcd_event_xfer_complete(BOARD_TUD_RHPORT, ep_number | ep_dirmask, ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
-
-            // Allow new transfers on this endpoint.
+            // Finish this transfer and allow new transfers on this endpoint.
             ep_xfer[ep_number].valid = 0;
 
             // Disable the interrupt for this endpoint now it is complete.
             USBD_REG(epie) = USBD_REG(epie) & (~(1 << ep_number));
           }
+
+          ep_xfer[ep_number].ready = 0;
+        }
+        // No OUT transfer is in flight for this endpoint.
+        else
+        {
+          if (ep_xfer[ep_number].dir == TUSB_DIR_OUT)
+          {
+            // We will record that there is data in the FIFO for dcd_edpt_xfer to obtain
+            // once the transfer is initiated.
+            // Strictly this should not happen for a non-control endpoint. Interrupts
+            // are disabled when there are no transfers setup for an endpoint.
+            ep_xfer[ep_number].ready = 1;
+          }
         }
       }
     }
   }
 }
 
-// Power management interrupt handler. 
+// Power management interrupt handler.
 // This handles USB device related power management interrupts only.
-void ft90x_usbd_pm_ISR(void)
+void ft9xx_usbd_pm_ISR(void)
 {
     uint16_t pmcfg = SYS->PMCFG_H;
 
-  // Main interrupt handler is responible for 
+  // Main interrupt handler is responible for
   if (pmcfg & MASK_SYS_PMCFG_DEV_CONN_DEV)
   {
       // Signal connection interrupt
diff --git a/hw/bsp/kuiic/board.h b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h
similarity index 70%
rename from hw/bsp/kuiic/board.h
rename to src/portable/chipidea/ci_fs/ci_fs_kinetis.h
index 78ad83a2e..31e14a546 100644
--- a/hw/bsp/kuiic/board.h
+++ b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h
@@ -1,7 +1,7 @@
-/* 
+/*
  * The MIT License (MIT)
  *
- * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,22 +24,26 @@
  * This file is part of the TinyUSB stack.
  */
 
-
-#ifndef BOARD_H_
-#define BOARD_H_
+#ifndef _CI_FS_KINETIS_H
+#define _CI_FS_KINETIS_H
 
 #include "fsl_device_registers.h"
 
-// LED
-#define LED_PIN_CLOCK         kCLOCK_PortA
-#define LED_GPIO              GPIOA
-#define LED_PORT              PORTA
-#define LED_PIN               2
-#define LED_STATE_ON          1
+//static const ci_fs_controller_t _ci_controller[] = {
+//    {.reg_base = USB0_BASE, .irqnum = USB0_IRQn}
+//};
 
-// UART
-#define UART_PORT             LPUART1
-#define UART_PIN_RX           3u
-#define UART_PIN_TX           0u
+#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USB0_BASE)
+#define CI_REG                  CI_FS_REG(0)
 
-#endif /* BOARD_H_ */
+void dcd_int_enable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_EnableIRQ(USB0_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_DisableIRQ(USB0_IRQn);
+}
+
+#endif
diff --git a/src/portable/chipidea/ci_fs/ci_fs_mcx.h b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
new file mode 100644
index 000000000..4b93a03a7
--- /dev/null
+++ b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_FS_MCX_H
+#define _CI_FS_MCX_H
+
+#include "fsl_device_registers.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_MCXN9
+  #define CI_FS_REG(_port)  ((ci_fs_regs_t*) USBFS0_BASE)
+  #define CIFS_IRQN 				USB0_FS_IRQn
+
+#elif CFG_TUSB_MCU == OPT_MCU_MCXA15
+  #define CI_FS_REG(_port)  ((ci_fs_regs_t*) USB0_BASE)
+  #define CIFS_IRQN         USB0_IRQn
+
+#else
+  #error "MCU is not supported"
+#endif
+
+#define CI_REG              CI_FS_REG(0)
+
+void dcd_int_enable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_EnableIRQ(CIFS_IRQN);
+}
+
+void dcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_DisableIRQ(CIFS_IRQN);
+}
+
+#endif
diff --git a/src/portable/chipidea/ci_fs/ci_fs_type.h b/src/portable/chipidea/ci_fs/ci_fs_type.h
new file mode 100644
index 000000000..5a5e53fb0
--- /dev/null
+++ b/src/portable/chipidea/ci_fs/ci_fs_type.h
@@ -0,0 +1,118 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_FS_TYPE_H
+#define _CI_FS_TYPE_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Note: some MCUs can only access these registers in 8-bit mode
+// align 4 is used to get rid of reserved fields
+#define _va32     volatile TU_ATTR_ALIGNED(4)
+
+typedef struct {
+  _va32 uint8_t PER_ID;                 // [00] Peripheral ID register
+  _va32 uint8_t ID_COMP;                // [04] Peripheral ID complement register
+  _va32 uint8_t REV;                    // [08] Peripheral revision register
+  _va32 uint8_t ADD_INFO;               // [0C] Peripheral additional info register
+  _va32 uint8_t OTG_ISTAT;              // [10] OTG Interrupt Status Register
+  _va32 uint8_t OTG_ICTRL;              // [14] OTG Interrupt Control Register
+  _va32 uint8_t OTG_STAT;               // [18] OTG Status Register
+  _va32 uint8_t OTG_CTRL;               // [1C] OTG Control register
+  uint32_t reserved_20[24];             // [20]
+  _va32 uint8_t INT_STAT;               // [80] Interrupt status register
+  _va32 uint8_t INT_EN;                 // [84] Interrupt enable register
+  _va32 uint8_t ERR_STAT;               // [88] Error interrupt status register
+  _va32 uint8_t ERR_ENB;                // [8C] Error interrupt enable register
+  _va32 uint8_t STAT;                   // [90] Status register
+  _va32 uint8_t CTL;                    // [94] Control register
+  _va32 uint8_t ADDR;                   // [98] Address register
+  _va32 uint8_t BDT_PAGE1;              // [9C] BDT page register 1
+  _va32 uint8_t FRM_NUML;               // [A0] Frame number register
+  _va32 uint8_t FRM_NUMH;               // [A4] Frame number register
+  _va32 uint8_t TOKEN;                  // [A8] Token register
+  _va32 uint8_t SOF_THLD;               // [AC] SOF threshold register
+  _va32 uint8_t BDT_PAGE2;              // [B0] BDT page register 2
+  _va32 uint8_t BDT_PAGE3;              // [B4] BDT page register 3
+
+  uint32_t reserved_b8;                 // [B8]
+  uint32_t reserved_bc;                 // [BC]
+
+  struct {
+    _va32 uint8_t CTL;
+  }EP[16];                              // [C0] Endpoint control register
+
+  //----- Following is only found available in NXP Kinetis
+  _va32 uint8_t USBCTRL;                // [100] USB Control register,
+  _va32 uint8_t OBSERVE;                // [104] USB OTG Observe register,
+  _va32 uint8_t CONTROL;                // [108] USB OTG Control register,
+  _va32 uint8_t USBTRC0;                // [10C] USB Transceiver Control Register 0,
+  uint32_t reserved_110;                // [110]
+  _va32 uint8_t USBFRMADJUST;           // [114] Frame Adjust Register,
+
+  //----- Following is only found available in NXP MCX
+  uint32_t reserved_118[3];             // [118]
+  _va32 uint8_t KEEP_ALIVE_CTRL;        // [124] Keep Alive Mode Control,
+  _va32 uint8_t KEEP_ALIVE_WKCTRL;      // [128] Keep Alive Mode Wakeup Control,
+  _va32 uint8_t MISCCTRL;               // [12C] Miscellaneous Control,
+  _va32 uint8_t STALL_IL_DIS;           // [130] Peripheral Mode Stall Disable for Endpoints[ 7..0] IN
+  _va32 uint8_t STALL_IH_DIS;           // [134] Peripheral Mode Stall Disable for Endpoints[15..8] IN
+  _va32 uint8_t STALL_OL_DIS;           // [138] Peripheral Mode Stall Disable for Endpoints[ 7..0] OUT
+  _va32 uint8_t STALL_OH_DIS;           // [13C] Peripheral Mode Stall Disable for Endpoints[15..8] OUT
+  _va32 uint8_t CLK_RECOVER_CTRL;       // [140] USB Clock Recovery Control,
+  _va32 uint8_t CLK_RECOVER_IRC_EN;     // [144] FIRC Oscillator Enable,
+  uint32_t reserved_148[3];             // [148]
+  _va32 uint8_t CLK_RECOVER_INT_EN;     // [154] Clock Recovery Combined Interrupt Enable,
+  uint32_t reserved_158;                // [158]
+  _va32 uint8_t CLK_RECOVER_INT_STATUS; // [15C] Clock Recovery Separated Interrupt Status,
+} ci_fs_regs_t;
+
+TU_VERIFY_STATIC(sizeof(ci_fs_regs_t) == 0x160, "Size is not correct");
+
+typedef struct
+{
+  uint32_t reg_base;
+  uint32_t irqnum;
+} ci_fs_controller_t;
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
new file mode 100644
index 000000000..11ddb683f
--- /dev/null
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -0,0 +1,568 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_FS)
+
+#include "device/dcd.h"
+#include "ci_fs_type.h"
+
+#if defined(TUP_USBIP_CHIPIDEA_FS_KINETIS)
+  #include "ci_fs_kinetis.h"
+#elif defined(TUP_USBIP_CHIPIDEA_FS_MCX)
+  #include "ci_fs_mcx.h"
+#else
+  #error "MCU is not supported"
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+enum {
+  TOK_PID_OUT   = 0x1u,
+  TOK_PID_IN    = 0x9u,
+  TOK_PID_SETUP = 0xDu,
+};
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t head;
+    struct {
+      union {
+        struct {
+               uint16_t           :  2;
+          __IO uint16_t tok_pid   :  4;
+               uint16_t data      :  1;
+          __IO uint16_t own       :  1;
+               uint16_t           :  8;
+        };
+        struct {
+               uint16_t           :  2;
+               uint16_t bdt_stall :  1;
+               uint16_t dts       :  1;
+               uint16_t ninc      :  1;
+               uint16_t keep      :  1;
+               uint16_t           : 10;
+        };
+      };
+      __IO uint16_t bc : 10;
+           uint16_t    :  6;
+    };
+  };
+  uint8_t *addr;
+}buffer_descriptor_t;
+
+TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t state;
+    struct {
+      uint32_t max_packet_size :11;
+      uint32_t                 : 5;
+      uint32_t odd             : 1;
+      uint32_t                 :15;
+    };
+  };
+  uint16_t length;
+  uint16_t remaining;
+}endpoint_state_t;
+
+TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
+
+typedef struct
+{
+  union {
+    /* [#EP][OUT,IN][EVEN,ODD] */
+    buffer_descriptor_t bdt[16][2][2];
+    uint16_t            bda[512];
+  };
+  TU_ATTR_ALIGNED(4) union {
+    endpoint_state_t endpoint[16][2];
+    endpoint_state_t endpoint_unified[16 * 2];
+  };
+  uint8_t setup_packet[8];
+  uint8_t addr;
+}dcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+// BDT(Buffer Descriptor Table) must be 256-byte aligned
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+
+TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
+
+static void prepare_next_setup_packet(uint8_t rhport)
+{
+  const unsigned out_odd = _dcd.endpoint[0][0].odd;
+  const unsigned in_odd  = _dcd.endpoint[0][1].odd;
+  TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, );
+
+  _dcd.bdt[0][0][out_odd].data     = 0;
+  _dcd.bdt[0][0][out_odd ^ 1].data = 1;
+  _dcd.bdt[0][1][in_odd].data      = 1;
+  _dcd.bdt[0][1][in_odd ^ 1].data  = 0;
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
+                _dcd.setup_packet, sizeof(_dcd.setup_packet));
+}
+
+static void process_stall(uint8_t rhport)
+{
+  for (int i = 0; i < 16; ++i) {
+    uint32_t const ep_ctl = CI_REG->EP[i].CTL;
+
+    if (ep_ctl & USB_ENDPT_EPSTALL_MASK) {
+      // prepare next setup if endpoint0
+      if ( i == 0 ) prepare_next_setup_packet(rhport);
+
+      // clear stall bit
+      CI_REG->EP[i].CTL = ep_ctl & ~USB_ENDPT_EPSTALL_MASK;
+    }
+  }
+}
+
+static void process_tokdne(uint8_t rhport)
+{
+  const unsigned s = CI_REG->STAT;
+  CI_REG->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
+
+  uint8_t const epnum = (s >> USB_STAT_ENDP_SHIFT);
+  uint8_t const dir   = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT;
+  unsigned const odd  = (s & USB_STAT_ODD_MASK) ? 1 : 0;
+
+  buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
+  endpoint_state_t    *ep = &_dcd.endpoint_unified[s >> 3];
+
+  /* fetch pid before discarded by the next steps */
+  const unsigned pid = bd->tok_pid;
+
+  /* reset values for a next transfer */
+  bd->bdt_stall = 0;
+  bd->dts       = 1;
+  bd->ninc      = 0;
+  bd->keep      = 0;
+  /* update the odd variable to prepare for the next transfer */
+  ep->odd       = odd ^ 1;
+  if (pid == TOK_PID_SETUP) {
+    dcd_event_setup_received(rhport, bd->addr, true);
+    CI_REG->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+    return;
+  }
+
+  const unsigned bc = bd->bc;
+  const unsigned remaining = ep->remaining - bc;
+  if (remaining && bc == ep->max_packet_size) {
+    /* continue the transferring consecutive data */
+    ep->remaining = remaining;
+    const int next_remaining = remaining - ep->max_packet_size;
+    if (next_remaining > 0) {
+      /* prepare to the after next transfer */
+      bd->addr += ep->max_packet_size * 2;
+      bd->bc    = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
+      __DSB();
+      bd->own   = 1; /* the own bit must set after addr */
+    }
+    return;
+  }
+  const unsigned length = ep->length;
+  dcd_event_xfer_complete(rhport,
+                          tu_edpt_addr(epnum, dir),
+                          length - remaining, XFER_RESULT_SUCCESS, true);
+  if (0 == epnum && 0 == length) {
+    /* After completion a ZLP of control transfer,
+     * it prepares for the next steup transfer. */
+    if (_dcd.addr) {
+      /* When the transfer was the SetAddress,
+       * the device address should be updated here. */
+      CI_REG->ADDR = _dcd.addr;
+      _dcd.addr  = 0;
+    }
+    prepare_next_setup_packet(rhport);
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  CI_REG->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
+  CI_REG->CTL     |= USB_CTL_ODDRST_MASK;
+  CI_REG->ADDR     = 0;
+  CI_REG->INT_EN   = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | USB_INTEN_SLEEPEN_MASK |
+                     USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
+
+  CI_REG->EP[0].CTL = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
+  for (unsigned i = 1; i < 16; ++i) {
+    CI_REG->EP[i].CTL = 0;
+  }
+  buffer_descriptor_t *bd = _dcd.bdt[0][0];
+  for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+    bd->head = 0;
+  }
+  const endpoint_state_t ep0 = {
+    .max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
+    .odd             = 0,
+    .length          = 0,
+    .remaining       = 0,
+  };
+  _dcd.endpoint[0][0] = ep0;
+  _dcd.endpoint[0][1] = ep0;
+  tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
+  _dcd.addr = 0;
+  prepare_next_setup_packet(rhport);
+  CI_REG->CTL &= ~USB_CTL_ODDRST_MASK;
+  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+}
+
+static void process_bus_sleep(uint8_t rhport)
+{
+  // Enable resume & disable suspend interrupt
+  const unsigned inten = CI_REG->INT_EN;
+
+  CI_REG->INT_EN   = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
+  CI_REG->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK;
+  CI_REG->USBCTRL |= USB_USBCTRL_SUSP_MASK;
+
+  dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+}
+
+static void process_bus_resume(uint8_t rhport)
+{
+  // Enable suspend & disable resume interrupt
+  const unsigned inten = CI_REG->INT_EN;
+
+  CI_REG->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; // will also clear USB_USBTRC0_USB_RESUME_INT_MASK
+  CI_REG->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK;
+  CI_REG->INT_EN   = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+
+  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rhport;
+  (void) rh_init;
+
+  // save crystal-less setting (if available)
+  #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
+  uint32_t clk_recover_irc_en = CI_REG->CLK_RECOVER_IRC_EN;
+  uint32_t clk_recover_ctrl = CI_REG->CLK_RECOVER_CTRL;
+  #endif
+
+  CI_REG->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
+  while (CI_REG->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
+
+  // restore crystal-less setting (if available)
+  #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
+  CI_REG->CLK_RECOVER_IRC_EN = clk_recover_irc_en;
+  CI_REG->CLK_RECOVER_CTRL  |= clk_recover_ctrl;
+  #endif
+
+  tu_memclr(&_dcd, sizeof(_dcd));
+  CI_REG->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
+  CI_REG->BDT_PAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >> 8);
+  CI_REG->BDT_PAGE2 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
+  CI_REG->BDT_PAGE3 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
+
+  CI_REG->INT_EN = USB_INTEN_USBRSTEN_MASK;
+
+  dcd_connect(rhport);
+  // NVIC_ClearPendingIRQ(CIFS_IRQN);
+  return true;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  _dcd.addr = dev_addr & 0x7F;
+  /* Response with status first before changing device address */
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+
+  CI_REG->CTL |= USB_CTL_RESUME_MASK;
+
+  unsigned cnt = SystemCoreClock / 1000;
+  while (cnt--) __NOP();
+
+  CI_REG->CTL &= ~USB_CTL_RESUME_MASK;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  CI_REG->USBCTRL  = 0;
+  CI_REG->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
+  CI_REG->CTL     |= USB_CTL_USBENSOFEN_MASK;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+  CI_REG->CTL      = 0;
+  CI_REG->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+
+  const unsigned ep_addr  = ep_desc->bEndpointAddress;
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  const unsigned xfer     = ep_desc->bmAttributes.xfer;
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  const unsigned odd      = ep->odd;
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+
+  /* No support for control transfer */
+  TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
+
+  ep->max_packet_size = tu_edpt_packet_size(ep_desc);
+  unsigned val = USB_ENDPT_EPCTLDIS_MASK;
+  val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
+  val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+  CI_REG->EP[epn].CTL |= val;
+
+  if (xfer != TUSB_XFER_ISOCHRONOUS) {
+    bd[odd].dts      = 1;
+    bd[odd].data     = 0;
+    bd[odd ^ 1].dts  = 1;
+    bd[odd ^ 1].data = 1;
+  }
+
+  return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport)
+{
+  dcd_int_disable(rhport);
+
+  for (unsigned i = 1; i < 16; ++i) {
+    CI_REG->EP[i].CTL = 0;
+  }
+
+  dcd_int_enable(rhport);
+
+  buffer_descriptor_t *bd = _dcd.bdt[1][0];
+  for (unsigned i = 2; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+    bd->head = 0;
+  }
+
+  endpoint_state_t *ep = &_dcd.endpoint[1][0];
+  for (unsigned i = 2; i < sizeof(_dcd.endpoint)/sizeof(*ep); ++i, ++ep) {
+    /* Clear except the odd */
+    ep->max_packet_size = 0;
+    ep->length          = 0;
+    ep->remaining       = 0;
+  }
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+  const unsigned msk      = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+
+  dcd_int_disable(rhport);
+
+  CI_REG->EP[epn].CTL &= ~msk;
+  ep->max_packet_size = 0;
+  ep->length          = 0;
+  ep->remaining       = 0;
+  bd[0].head          = 0;
+  bd[1].head          = 0;
+
+  dcd_int_enable(rhport);
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
+  TU_ASSERT(0 == bd->own);
+
+  dcd_int_disable(rhport);
+
+  ep->length    = total_bytes;
+  ep->remaining = total_bytes;
+
+  const unsigned mps = ep->max_packet_size;
+  if (total_bytes > mps) {
+    buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
+    /* When total_bytes is greater than the max packet size,
+     * it prepares to the next transfer to avoid NAK in advance. */
+    next->bc   = total_bytes >= 2 * mps ? mps: total_bytes - mps;
+    next->addr = buffer + mps;
+    next->own  = 1;
+  }
+  bd->bc   = total_bytes >= mps ? mps: total_bytes;
+  bd->addr = buffer;
+  __DSB();
+  bd->own  = 1; /* This bit must be set last */
+
+  dcd_int_enable(rhport);
+
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  const unsigned epn = tu_edpt_number(ep_addr);
+
+  if (0 == epn) {
+    CI_REG->EP[epn].CTL |=  USB_ENDPT_EPSTALL_MASK;
+  } else {
+    const unsigned dir      = tu_edpt_dir(ep_addr);
+    const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+    buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd];
+    TU_ASSERT(0 == bd->own,);
+
+    dcd_int_disable(rhport);
+
+    bd->bdt_stall = 1;
+    __DSB();
+    bd->own       = 1; /* This bit must be set last */
+
+    dcd_int_enable(rhport);
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  TU_VERIFY(epn,);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+  TU_VERIFY(bd[odd].own,);
+
+  dcd_int_disable(rhport);
+
+  bd[odd].own = 0;
+  __DSB();
+
+  // clear stall
+  bd[odd].bdt_stall  = 0;
+
+  // Reset data toggle
+  bd[odd    ].data = 0;
+  bd[odd ^ 1].data = 1;
+
+  // We already cleared this in ISR, but just clear it here to be safe
+  const uint32_t ep_ctl = CI_REG->EP[epn].CTL;
+  if (ep_ctl & USB_ENDPT_EPSTALL_MASK) {
+    CI_REG->EP[epn].CTL = ep_ctl & ~USB_ENDPT_EPSTALL_MASK;
+  }
+
+  dcd_int_enable(rhport);
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_int_handler(uint8_t rhport)
+{
+  uint32_t is  = CI_REG->INT_STAT;
+  uint32_t msk = CI_REG->INT_EN;
+
+  // clear non-enabled interrupts
+  CI_REG->INT_STAT = is & ~msk;
+  is &= msk;
+
+  if (is & USB_ISTAT_ERROR_MASK) {
+    /* TODO: */
+    uint32_t es = CI_REG->ERR_STAT;
+    CI_REG->ERR_STAT = es;
+    CI_REG->INT_STAT = is; /* discard any pending events */
+  }
+
+  if (is & USB_ISTAT_USBRST_MASK) {
+    CI_REG->INT_STAT = is; /* discard any pending events */
+    process_bus_reset(rhport);
+  }
+
+  if (is & USB_ISTAT_SLEEP_MASK) {
+    // TU_LOG2("Suspend: "); TU_LOG2_HEX(is);
+
+    // Note Host usually has extra delay after bus reset (without SOF), which could falsely
+    // detected as Sleep event. Though usbd has debouncing logic so we are good
+    CI_REG->INT_STAT = USB_ISTAT_SLEEP_MASK;
+    process_bus_sleep(rhport);
+  }
+
+#if 0 // ISTAT_RESUME never trigger, probably for host mode ?
+  if (is & USB_ISTAT_RESUME_MASK) {
+    // TU_LOG2("ISTAT Resume: "); TU_LOG2_HEX(is);
+    KHCI->ISTAT = USB_ISTAT_RESUME_MASK;
+    process_bus_resume(rhport);
+  }
+#endif
+
+  if (CI_REG->USBTRC0 & USB_USBTRC0_USB_RESUME_INT_MASK) {
+     // TU_LOG2("USBTRC0 Resume: "); TU_LOG2_HEX(is); TU_LOG2_HEX(KHCI->USBTRC0);
+    process_bus_resume(rhport);
+  }
+
+  if (is & USB_ISTAT_SOFTOK_MASK) {
+    CI_REG->INT_STAT = USB_ISTAT_SOFTOK_MASK;
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+
+  if (is & USB_ISTAT_STALL_MASK) {
+    CI_REG->INT_STAT = USB_ISTAT_STALL_MASK;
+    process_stall(rhport);
+  }
+
+  if (is & USB_ISTAT_TOKDNE_MASK) {
+    process_tokdne(rhport);
+  }
+}
+
+#endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index 2de0d9cb4..75d1d55b8 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -37,22 +37,82 @@
 #define USB2_BASE USB_OTG2_BASE
 #endif
 
+// RT1040 calls its only USB USB_OTG (no 1)
+#if defined(MIMXRT1042_SERIES)
+#define USB_OTG1_IRQn USB_OTG_IRQn
+#endif
+
 static const ci_hs_controller_t _ci_controller[] =
 {
   // RT1010 and RT1020 only has 1 USB controller
   #if FSL_FEATURE_SOC_USBHS_COUNT == 1
-    { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
+    { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn }
   #else
-    { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
-    { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
+    { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn},
+    { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn}
   #endif
 };
 
-#define CI_DCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
-#define CI_DCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
+#define CI_HS_REG(_port)        ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
 
-#define CI_HCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
-#define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
+//------------- DCD -------------//
+#define CI_DCD_INT_ENABLE(_p)   NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum)
+#define CI_DCD_INT_DISABLE(_p)  NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum)
 
+//------------- HCD -------------//
+#define CI_HCD_INT_ENABLE(_p)   NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum)
+#define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum)
+
+//------------- DCache -------------//
+#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
+#if __CORTEX_M == 7
+TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
+  if (size & (CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) {
+    size = (size & ~(CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) + CFG_TUD_MEM_DCACHE_LINE_SIZE;
+  }
+  return size;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) {
+  return !(0x20000000 <= addr && addr < 0x20100000);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (imxrt_is_cache_mem(addr32)) {
+    TU_ASSERT(tu_is_aligned32(addr32));
+    data_size = round_up_to_cache_line_size(data_size);
+    SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
+  }
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (imxrt_is_cache_mem(addr32)) {
+    // Invalidating does not push cached changes back to RAM so we need to be
+    // *very* careful when we do it. If we're not aligned, then we risk resetting
+    // values back to their RAM state.
+    TU_ASSERT(tu_is_aligned32(addr32));
+    data_size = round_up_to_cache_line_size(data_size);
+    SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
+  }
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (imxrt_is_cache_mem(addr32)) {
+    TU_ASSERT(tu_is_aligned32(addr32));
+    data_size = round_up_to_cache_line_size(data_size);
+    SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
+  }
+  return true;
+}
+
+#elif __CORTEX_M == 4
+#error "Secondary M4 core's cache controller is not supported yet."
+#endif
+#endif
 
 #endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
index 8c2e7dfa6..178eec419 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
@@ -27,15 +27,26 @@
 #ifndef _CI_HS_LPC18_43_H_
 #define _CI_HS_LPC18_43_H_
 
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 // LPCOpen for 18xx & 43xx
 #include "chip.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 static const ci_hs_controller_t _ci_controller[] =
 {
-  { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
-  { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
+  { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },
+  { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn }
 };
 
+#define CI_HS_REG(_port)        ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
+
 #define CI_DCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
 #define CI_DCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
 
diff --git a/src/portable/chipidea/ci_hs/ci_hs_mcx.h b/src/portable/chipidea/ci_hs/ci_hs_mcx.h
new file mode 100644
index 000000000..f940f4a9d
--- /dev/null
+++ b/src/portable/chipidea/ci_hs/ci_hs_mcx.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_HS_MCX_H_
+#define _CI_HS_MCX_H_
+
+#include "fsl_device_registers.h"
+
+// NOTE: MCX N9 has 2 different USB Controller
+// - USB0 is KHCI FullSpeed
+// - USB1 is ChipIdea HighSpeed, therefore rhport = 1 is actually index 0
+
+static const ci_hs_controller_t _ci_controller[] = {
+    {.reg_base = USBHS1__USBC_BASE, .irqnum = USB1_HS_IRQn}
+};
+
+TU_ATTR_ALWAYS_INLINE static inline ci_hs_regs_t* CI_HS_REG(uint8_t port) {
+  (void) port;
+  return ((ci_hs_regs_t*) _ci_controller[0].reg_base);
+}
+
+#define CI_DCD_INT_ENABLE(_p)   do { (void) _p; NVIC_EnableIRQ (_ci_controller[0].irqnum); } while (0)
+#define CI_DCD_INT_DISABLE(_p)  do { (void) _p; NVIC_DisableIRQ(_ci_controller[0].irqnum); } while (0)
+
+#define CI_HCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
+#define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
+
+
+#endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h
index 728a86b86..2f3aa3694 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_type.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_type.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -31,13 +31,21 @@
  extern "C" {
 #endif
 
+// DCCPARAMS
+enum {
+  DCCPARAMS_DEN_MASK = 0x1Fu, ///< DEN bit 4:0
+};
+
 // USBCMD
 enum {
   USBCMD_RUN_STOP         = TU_BIT(0),
   USBCMD_RESET            = TU_BIT(1),
   USBCMD_SETUP_TRIPWIRE   = TU_BIT(13),
-  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
-// Interrupt Threshold bit 23:16
+  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14), // This bit is used as a semaphore to ensure the to proper addition of a
+                                        // new dTD to an active (primed) endpoint’s linked list. This bit is set and
+                                        // cleared by software during the process of adding a new dTD
+
+  USBCMD_INTR_THRESHOLD_MASK = 0x00FF0000u, // Interrupt Threshold bit 23:16
 };
 
 // PORTSC1
@@ -72,6 +80,7 @@ enum {
 
 // USBMode
 enum {
+  USBMOD_CM_MASK    = TU_BIT(0) | TU_BIT(1),
   USBMODE_CM_DEVICE = 2,
   USBMODE_CM_HOST   = 3,
 
@@ -134,7 +143,6 @@ typedef struct
 {
   uint32_t reg_base;
   uint32_t irqnum;
-  uint8_t  ep_count; // Max bi-directional Endpoints
 }ci_hs_controller_t;
 
 #ifdef __cplusplus
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index c7cc3e0e8..a716dc24c 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -28,16 +28,33 @@
 
 #if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_HS)
 
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
 #include "device/dcd.h"
 #include "ci_hs_type.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
   #include "ci_hs_imxrt.h"
+
+#if CFG_TUD_MEM_DCACHE_ENABLE
+bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean(addr, data_size);
+}
+
+bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_invalidate(addr, data_size);
+}
+
+bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean_invalidate(addr, data_size);
+}
+#endif
+
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_MCXN9)
+  // MCX N9 only port 1 use this controller
+  #include "ci_hs_mcx.h"
+
 #else
   #error "Unsupported MCUs"
 #endif
@@ -46,15 +63,6 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-#define CI_HS_REG(_port)      ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
-
-#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
-  #define CleanInvalidateDCache_by_Addr   SCB_CleanInvalidateDCache_by_Addr
-#else
-  #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
-#endif
-
-
 // ENDPTCTRL
 enum {
   ENDPTCTRL_STALL          = TU_BIT(0),
@@ -155,9 +163,19 @@ typedef struct {
   dcd_qtd_t qtd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
 }dcd_data_t;
 
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(2048)
 static dcd_data_t _dcd_data;
 
+//--------------------------------------------------------------------+
+// Prototypes and Helper Functions
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE
+static inline uint8_t ci_ep_count(ci_hs_regs_t const* dcd_reg)
+{
+  return dcd_reg->DCCPARAMS & DCCPARAMS_DEN_MASK;
+}
+
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
@@ -172,7 +190,8 @@ static void bus_reset(uint8_t rhport)
   // endpoint type of the unused direction must be changed from the control type to any other
   // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
   // for the data PID tracking on the active endpoint.
-  for( uint8_t i=1; i < _ci_controller[rhport].ep_count; i++)
+  uint8_t const ep_count = ci_ep_count(dcd_reg);
+  for( uint8_t i=1; i < ep_count; i++)
   {
     dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
   }
@@ -199,34 +218,46 @@ static void bus_reset(uint8_t rhport)
   _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
 
   _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
+
+  dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 }
 
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
   tu_memclr(&_dcd_data, sizeof(dcd_data_t));
 
   ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
+  TU_ASSERT(ci_ep_count(dcd_reg) <= TUP_DCD_ENDPOINT_MAX);
+
   // Reset controller
   dcd_reg->USBCMD |= USBCMD_RESET;
   while( dcd_reg->USBCMD & USBCMD_RESET ) {}
 
   // Set mode to device, must be set immediately after reset
-  dcd_reg->USBMODE = USBMODE_CM_DEVICE;
+  uint32_t usbmode = dcd_reg->USBMODE & ~USBMOD_CM_MASK;
+  usbmode |= USBMODE_CM_DEVICE;
+  dcd_reg->USBMODE = usbmode;
+
   dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
 
 #if !TUD_OPT_HIGH_SPEED
   dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
 #endif
 
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 
   dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
   dcd_reg->USBSTS  = dcd_reg->USBSTS;
   dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
 
-  dcd_reg->USBCMD &= ~0x00FF0000;     // Interrupt Threshold Interval = 0
-  dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
+  uint32_t usbcmd = dcd_reg->USBCMD;
+  usbcmd &= ~USBCMD_INTR_THRESHOLD_MASK; // Interrupt Threshold Interval = 0
+  usbcmd |= USBCMD_RUN_STOP; // run
+
+  dcd_reg->USBCMD = usbcmd;
+
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -268,10 +299,12 @@ void dcd_disconnect(uint8_t rhport)
 
 void dcd_sof_enable(uint8_t rhport, bool en)
 {
-  (void) rhport;
-  (void) en;
-
-  // TODO implement later
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
+  if (en) {
+      dcd_reg->USBINTR |= INTR_SOF;
+  } else {
+      dcd_reg->USBINTR &= ~INTR_SOF;
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -280,9 +313,7 @@ void dcd_sof_enable(uint8_t rhport, bool en)
 
 static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
 {
-  // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
-  // address to 32-byte boundaries. Buffer must be word aligned
-  CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
+  dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes);
 
   tu_memclr(p_qtd, sizeof(dcd_qtd_t));
 
@@ -339,8 +370,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
 
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
+
   // Must not exceed max endpoint number
-  TU_ASSERT( epnum < _ci_controller[rhport].ep_count );
+  TU_ASSERT(epnum < ci_ep_count(dcd_reg));
 
   //------------- Prepare Queue Head -------------//
   dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
@@ -355,11 +388,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 
   p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
 
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 
   // Enable EP Control
-  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
-
   uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
 
   if ( dir == TUSB_DIR_OUT )
@@ -378,7 +409,8 @@ void dcd_edpt_close_all (uint8_t rhport)
   ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
   // Disable all non-control endpoints
-  for( uint8_t epnum=1; epnum < _ci_controller[rhport].ep_count; epnum++)
+  uint8_t const ep_count = ci_ep_count(dcd_reg);
+  for (uint8_t epnum = 1; epnum < ep_count; epnum++)
   {
     _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1;
     _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1;
@@ -416,7 +448,7 @@ static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
   p_qhd->qtd_overlay.next   = (uint32_t) p_qtd; // link qtd to qhd
 
   // flush cache
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 
   if ( epnum == 0 )
   {
@@ -447,7 +479,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
   return true;
 }
 
+#if !CFG_TUD_MEM_DCACHE_ENABLE
 // fifo has to be aligned to 4k boundary
+// It's incompatible with dcache enabled transfer, since neither address nor size is aligned to cache line
 bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
 {
   uint8_t const epnum = tu_edpt_number(ep_addr);
@@ -493,8 +527,6 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
           page++;
         }
       }
-
-      CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
     }
     else
     {
@@ -509,6 +541,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 
   return true;
 }
+#endif
 
 //--------------------------------------------------------------------+
 // ISR
@@ -541,7 +574,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
       tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
     }
   }
-  
+
   // only number of bytes in the IOC qtd
   dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
 }
@@ -607,20 +640,11 @@ void dcd_int_handler(uint8_t rhport)
   if (int_status & INTR_USB)
   {
     // Make sure we read the latest version of _dcd_data.
-    CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+    dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 
     uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
     dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
 
-    if (dcd_reg->ENDPTSETUPSTAT)
-    {
-      //------------- Set up Received -------------//
-      // 23.10.10.2 Operational model for setup transfers
-      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
-
-      dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
-    }
-
     // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
     // nothing to do, we will submit xfer as error to usbd
     // if (int_status & INTR_ERROR) { }
@@ -633,11 +657,21 @@ void dcd_int_handler(uint8_t rhport)
         if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
       }
     }
+
+    // Set up Received
+    // 23.10.10.2 Operational model for setup transfers
+    // Must be after normal transfer complete since it is possible to have both previous control status + new setup
+    // in the same frame and we should handle previous status first.
+    if (dcd_reg->ENDPTSETUPSTAT) {
+      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
+      dcd_event_setup_received(rhport, (uint8_t *) (uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
+    }
   }
 
   if (int_status & INTR_SOF)
   {
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+    const uint32_t frame = dcd_reg->FRINDEX;
+    dcd_event_sof(rhport, frame, true);
   }
 }
 
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index d0396daea..c4c342a70 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -28,8 +28,7 @@
 
 // Chipidea Highspeed USB IP implement EHCI for host functionality
 
-#if CFG_TUH_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT)
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_EHCI)
 
 //--------------------------------------------------------------------+
 // INCLUDE
@@ -39,55 +38,74 @@
 #include "portable/ehci/ehci_api.h"
 #include "ci_hs_type.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  #include "ci_hs_imxrt.h"
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
+
+#include "ci_hs_imxrt.h"
+
+#if CFG_TUH_MEM_DCACHE_ENABLE
+bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean(addr, data_size);
+}
+
+bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_invalidate(addr, data_size);
+}
+
+bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean_invalidate(addr, data_size);
+}
+#endif
+
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
-  #include "ci_hs_lpc18_43.h"
+
+#include "ci_hs_lpc18_43.h"
+
 #else
-  #error "Unsupported MCUs"
+#error "Unsupported MCUs"
 #endif
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-#define CI_HS_REG(_port)      ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
-
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
 
-bool hcd_init(uint8_t rhport)
-{
-  ci_hs_regs_t* hcd_reg = CI_HS_REG(rhport);
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+  ci_hs_regs_t *hcd_reg = CI_HS_REG(rhport);
 
   // Reset controller
   hcd_reg->USBCMD |= USBCMD_RESET;
-  while( hcd_reg->USBCMD & USBCMD_RESET ) {}
+  while ( hcd_reg->USBCMD & USBCMD_RESET ) {}
 
   // Set mode to device, must be set immediately after reset
 #if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
   // LPC18XX/43XX need to set VBUS Power Select to HIGH
   // RHPORT1 is fullspeed only (need external PHY for Highspeed)
   hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
-  if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+  if (rhport == 1) {
+    hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+  }
 #else
   hcd_reg->USBMODE = USBMODE_CM_HOST;
 #endif
 
   // FIXME force full speed, still have issue with Highspeed enumeration
+  // probably due to physical connection bouncing when plug/unplug
+  // 1. Have issue when plug/unplug devices, maybe the port is not reset properly
+  // 2. Also does not seems to detect disconnection
   hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
 
   return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD);
 }
 
-void hcd_int_enable(uint8_t rhport)
-{
+void hcd_int_enable(uint8_t rhport) {
   CI_HCD_INT_ENABLE(rhport);
 }
 
-void hcd_int_disable(uint8_t rhport)
-{
+void hcd_int_disable(uint8_t rhport) {
   CI_HCD_INT_DISABLE(rhport);
 }
 
diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 0bb8b6e41..56ecb7575 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -243,7 +243,7 @@ static struct
 
 // Converts xfer pointer to epnum (0,1,2,3) regardless of xfer direction
 #define XFER_EPNUM(xfer)      ((xfer - &_dcd.xfer_status[0][0]) >> 1)
-// Converts xfer pinter to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number)
+// Converts xfer pointer to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number)
 #define XFER_REGS(xfer)       ep_regs[XFER_EPNUM(xfer)]
 // Converts epnum (0,1,2,3) to EPx_REGS pointer
 #define EPNUM_REGS(epnum)     ep_regs[epnum]
@@ -651,7 +651,7 @@ static void handle_epx_tx_ev(xfer_ctl_t *xfer)
   }
   if (txs & USB_USB_TXS1_REG_USB_TX_URUN_Msk)
   {
-    TU_LOG1("EP %d FIFO underrun\n", epnum);
+    TU_LOG1("EP %d FIFO underrun\r\n", epnum);
   }
   // Start next or repeated packet.
   start_tx_packet(xfer);
@@ -804,15 +804,16 @@ static void handle_ep0_nak(void)
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   _dcd.init_called = true;
-  if (_dcd.vbus_present)
-  {
+  if (_dcd.vbus_present) {
     dcd_connect(rhport);
   }
+
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -895,6 +896,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
   return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0;
 }
 
+void tusb_vbus_changed(bool present);
 void tusb_vbus_changed(bool present)
 {
   if (present && !_dcd.vbus_present)
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 76ba2a921..01bbf62bf 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -48,8 +48,8 @@
 #ifdef TUP_USBIP_CHIPIDEA_HS
   // NXP Transdimension: 8 elements
   #define FRAMELIST_SIZE_BIT_VALUE      7u
-  #define FRAMELIST_SIZE_USBCMD_VALUE   (((FRAMELIST_SIZE_BIT_VALUE &  3) << EHCI_USBCMD_POS_FRAMELIST_SIZE) | \
-                                         ((FRAMELIST_SIZE_BIT_VALUE >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB))
+  #define FRAMELIST_SIZE_USBCMD_VALUE   (((FRAMELIST_SIZE_BIT_VALUE &  3) << EHCI_USBCMD_FRAMELIST_SIZE_SHIFT) | \
+                                         ((FRAMELIST_SIZE_BIT_VALUE >> 2) << EHCI_USBCMD_CHIPIDEA_FRAMELIST_SIZE_MSB_SHIFT))
 #else
   // STD EHCI: 256 elements
   #define FRAMELIST_SIZE_BIT_VALUE      2u
@@ -58,7 +58,8 @@
 
 #define FRAMELIST_SIZE                  (1024 >> FRAMELIST_SIZE_BIT_VALUE)
 
-#define QHD_MAX      (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX)
+// Total queue head pool. TODO should be user configurable and more optimize memory usage in the future
+#define QHD_MAX      (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB)
 #define QTD_MAX      QHD_MAX
 
 typedef struct
@@ -79,62 +80,97 @@ typedef struct
   ehci_qhd_t qhd_pool[QHD_MAX];
   ehci_qtd_t qtd_pool[QTD_MAX] TU_ATTR_ALIGNED(32);
 
-  ehci_registers_t* regs;
+  ehci_registers_t* regs;         // operational register
+  ehci_cap_registers_t* cap_regs; // capability register
 
   volatile uint32_t uframe_number;
 }ehci_data_t;
 
 // Periodic frame list must be 4K alignment
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
+CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
+
+//--------------------------------------------------------------------+
+// Debug
+//--------------------------------------------------------------------+
+#if 0 && CFG_TUSB_DEBUG >= (EHCI_DBG + 1)
+static inline void print_portsc(ehci_registers_t* regs) {
+  TU_LOG_HEX(EHCI_DBG, regs->portsc);
+  TU_LOG(EHCI_DBG, "  Connect Status : %u\r\n", regs->portsc_bm.current_connect_status);
+  TU_LOG(EHCI_DBG, "  Connect Change : %u\r\n", regs->portsc_bm.connect_status_change);
+  TU_LOG(EHCI_DBG, "  Enabled        : %u\r\n", regs->portsc_bm.port_enabled);
+  TU_LOG(EHCI_DBG, "  Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change);
+
+  TU_LOG(EHCI_DBG, "  OverCurr Change: %u\r\n", regs->portsc_bm.over_current_change);
+  TU_LOG(EHCI_DBG, "  Force Resume   : %u\r\n", regs->portsc_bm.force_port_resume);
+  TU_LOG(EHCI_DBG, "  Suspend        : %u\r\n", regs->portsc_bm.suspend);
+  TU_LOG(EHCI_DBG, "  Reset          : %u\r\n", regs->portsc_bm.port_reset);
+  TU_LOG(EHCI_DBG, "  Power          : %u\r\n", regs->portsc_bm.port_power);
+}
+
+static inline void print_intr(uint32_t intr) {
+  TU_LOG_HEX(EHCI_DBG, intr);
+  TU_LOG(EHCI_DBG, "  USB Interrupt      : %u\r\n", (intr & EHCI_INT_MASK_USB) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  USB Error          : %u\r\n", (intr & EHCI_INT_MASK_ERROR) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  Port Change Detect : %u\r\n", (intr & EHCI_INT_MASK_PORT_CHANGE) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  Frame List Rollover: %u\r\n", (intr & EHCI_INT_MASK_FRAMELIST_ROLLOVER) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  Host System Error  : %u\r\n", (intr & EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  Async Advance      : %u\r\n", (intr & EHCI_INT_MASK_ASYNC_ADVANCE) ? 1 : 0);
+//  TU_LOG(EHCI_DBG, "  Interrupt on Async: %u\r\n", (intr & EHCI_INT_MASK_NXP_ASYNC));
+//  TU_LOG(EHCI_DBG, "  Periodic Schedule : %u\r\n", (intr & EHCI_INT_MASK_NXP_PERIODIC));
+}
+
+#else
+#define print_portsc(_reg)
+#endif
 
 //--------------------------------------------------------------------+
 // PROTOTYPE
 //--------------------------------------------------------------------+
-static inline ehci_link_t* get_period_head(uint8_t rhport, uint32_t interval_ms)
-{
-  (void) rhport;
-  return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min32(FRAMELIST_SIZE, interval_ms) ) ];
-}
 
-static inline ehci_qhd_t* qhd_control(uint8_t dev_addr)
-{
-  return &ehci_data.control[dev_addr].qhd;
-}
-
-static inline ehci_qhd_t* qhd_async_head(uint8_t rhport)
-{
-  (void) rhport;
-  // control qhd of dev0 is used as async head
-  return qhd_control(0);
-}
-
-static inline ehci_qtd_t* qtd_control(uint8_t dev_addr)
-{
-  return &ehci_data.control[dev_addr].qtd;
-}
-
-
-static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd);
-static inline ehci_qhd_t* qhd_find_free (void);
-static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
-
-// determine if a queue head has bus-related error
-static inline bool qhd_has_xact_error (ehci_qhd_t * p_qhd)
-{
-  return (p_qhd->qtd_overlay.buffer_err || p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err);
-  //p_qhd->qtd_overlay.non_hs_period_missed_uframe || p_qhd->qtd_overlay.pingstate_err TODO split transaction error
-}
+// weak dcache for non-cacheable MCU
+TU_ATTR_WEAK bool hcd_dcache_clean(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; return true; }
+TU_ATTR_WEAK bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; return true; }
+TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; return true; }
 
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_find_free (void);
+static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
+static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd);
+static void qhd_remove_qtd(ehci_qhd_t *qhd);
 
-static inline ehci_qtd_t* qtd_find_free (void);
-static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd);
-static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new);
-static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd);
-static void qtd_init (ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void);
+static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes);
 
-static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
-static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer);
+TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport);
+TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
+TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next (ehci_link_t const *p_link);
+static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr);
+
+static void ehci_disable_schedule(ehci_registers_t* regs, bool is_period) {
+  // maybe have a timeout for status
+  if (is_period) {
+    regs->command_bm.periodic_enable = 0;
+    while(regs->status_bm.periodic_status) {}
+  } else {
+    regs->command_bm.async_enable = 0;
+    while(regs->status_bm.async_status) {} // should have a timeout
+  }
+}
+
+static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) {
+  // maybe have a timeout for status
+  if (is_period) {
+    regs->command_bm.periodic_enable = 1;
+    while ( 0 == regs->status_bm.periodic_status ) {}
+  } else {
+    regs->command_bm.async_enable = 1;
+    while( 0 == regs->status_bm.async_status ) {}
+  }
+}
 
 //--------------------------------------------------------------------+
 // HCD API
@@ -152,11 +188,16 @@ void hcd_port_reset(uint8_t rhport)
 
   ehci_registers_t* regs = ehci_data.regs;
 
-//  regs->portsc_bm.port_enabled = 0; // disable port before reset
-//  regs->portsc_bm.port_reset = 1;
+  // skip if already in reset
+  if (regs->portsc_bm.port_reset) {
+    return;
+  }
 
-  uint32_t portsc = regs->portsc;
+  // mask out Write-1-to-Clear bits
+  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C;
 
+  // EHCI Table 2-16 PortSC
+  // when software writes Port Reset bit to a one, it must also write a zero to the Port Enable bit.
   portsc &= ~(EHCI_PORTSC_MASK_PORT_EANBLED);
   portsc |= EHCI_PORTSC_MASK_PORT_RESET;
 
@@ -166,11 +207,18 @@ void hcd_port_reset(uint8_t rhport)
 void hcd_port_reset_end(uint8_t rhport)
 {
   (void) rhport;
-
-#if 0
   ehci_registers_t* regs = ehci_data.regs;
-  regs->portsc_bm.port_reset = 0;
-#endif
+
+  // skip if reset is already complete
+  if (!regs->portsc_bm.port_reset) {
+    return;
+  }
+
+  // mask out all change bits since they are Write 1 to clear
+  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C;
+  portsc &= ~EHCI_PORTSC_MASK_PORT_RESET;
+
+  regs->portsc = portsc;
 }
 
 bool hcd_port_connect_status(uint8_t rhport)
@@ -185,138 +233,126 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
   return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed
 }
 
-static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
-{
-  for(ehci_link_t* prev = list_head;
-      !prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head);
-      prev = list_next(prev) )
-  {
-    // TODO check type for ISO iTD and siTD
-    // TODO Suppress cast-align warning
-    #pragma GCC diagnostic push
-    #pragma GCC diagnostic ignored "-Wcast-align"
-    ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev);
-    #pragma GCC diagnostic pop
-    if ( qhd->dev_addr == dev_addr )
-    {
-      // TODO deactive all TD, wait for QHD to inactive before removal
-      prev->address = qhd->next.address;
-
-      // EHCI 4.8.2 link the removed qhd to async head (which always reachable by Host Controller)
-      qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1);
-
-      if ( qhd->int_smask )
-      {
-        // period list queue element is guarantee to be free in the next frame (1 ms)
-        qhd->used = 0;
-      }else
-      {
-        // async list use async advance handshake
-        // mark as removing, will completely re-usable when async advance isr occurs
-        qhd->removing = 1;
-      }
-    }
-  }
-}
-
 // Close all opened endpoint belong to this device
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
+void hcd_device_close(uint8_t rhport, uint8_t daddr)
 {
   // skip dev0
-  if (dev_addr == 0) return;
+  if (daddr == 0) {
+    return;
+  }
 
   // Remove from async list
-  list_remove_qhd_by_addr( (ehci_link_t*) qhd_async_head(rhport), dev_addr );
+  list_remove_qhd_by_daddr((ehci_link_t *) list_get_async_head(rhport), daddr);
 
   // Remove from all interval period list
-  for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++)
-  {
-    list_remove_qhd_by_addr( (ehci_link_t*) &ehci_data.period_head_arr[i], dev_addr);
+  for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) {
+    list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr);
   }
 
   // Async doorbell (EHCI 4.8.2 for operational details)
   ehci_data.regs->command_bm.async_adv_doorbell = 1;
 }
 
-bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
-{
-  (void) capability_reg; // not used yet
+static void init_periodic_list(uint8_t rhport) {
+  (void) rhport;
 
-  tu_memclr(&ehci_data, sizeof(ehci_data_t));
-
-  ehci_data.regs = (ehci_registers_t* ) operatial_reg;
-
-  ehci_registers_t* regs = ehci_data.regs;
-
-  //------------- CTRLDSSEGMENT Register (skip) -------------//
-  //------------- USB INT Register -------------//
-  regs->inten  = 0;                 // 1. disable all the interrupt
-  regs->status = EHCI_INT_MASK_ALL; // 2. clear all status
-
-  regs->inten  = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE |
-                 EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER;
-
-  //------------- Asynchronous List -------------//
-  ehci_qhd_t * const async_head = qhd_async_head(rhport);
-  tu_memclr(async_head, sizeof(ehci_qhd_t));
-
-  async_head->next.address                    = (uint32_t) async_head; // circular list, next is itself
-  async_head->next.type                       = EHCI_QTYPE_QHD;
-  async_head->head_list_flag                  = 1;
-  async_head->qtd_overlay.halted              = 1; // inactive most of time
-  async_head->qtd_overlay.next.terminate      = 1; // TODO removed if verified
-
-  regs->async_list_addr = (uint32_t) async_head;
-
-  //------------- Periodic List -------------//
   // Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only
-  for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ )
-  {
+  for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ ) {
     ehci_data.period_head_arr[i].int_smask          = 1; // queue head in period list must have smask non-zero
     ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive
   }
 
-  ehci_link_t * const framelist  = ehci_data.period_framelist;
-  ehci_link_t * const period_1ms = get_period_head(rhport, 1u);
-
+  // TODO EHCI_FRAMELIST_SIZE with other size than 8
   // all links --> period_head_arr[0] (1ms)
   // 0, 2, 4, 6 etc --> period_head_arr[1] (2ms)
   // 1, 5 --> period_head_arr[2] (4ms)
   // 3 --> period_head_arr[3] (8ms)
 
-  // TODO EHCI_FRAMELIST_SIZE with other size than 8
-  for(uint32_t i=0; i<FRAMELIST_SIZE; i++)
-  {
-    framelist[i].address = (uint32_t) period_1ms;
-    framelist[i].type    = EHCI_QTYPE_QHD;
+  ehci_link_t * const framelist  = ehci_data.period_framelist;
+  ehci_link_t * const head_1ms = (ehci_link_t *) &ehci_data.period_head_arr[0];
+  ehci_link_t * const head_2ms = (ehci_link_t *) &ehci_data.period_head_arr[1];
+  ehci_link_t * const head_4ms = (ehci_link_t *) &ehci_data.period_head_arr[2];
+  ehci_link_t * const head_8ms = (ehci_link_t *) &ehci_data.period_head_arr[3];
+
+  for (uint32_t i = 0; i < FRAMELIST_SIZE; i++) {
+    framelist[i].address = (uint32_t) head_1ms;
+    framelist[i].type = EHCI_QTYPE_QHD;
   }
 
-  for(uint32_t i=0; i<FRAMELIST_SIZE; i+=2)
-  {
-    list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD);
+  for (uint32_t i = 0; i < FRAMELIST_SIZE; i += 2) {
+    list_insert(framelist + i, head_2ms, EHCI_QTYPE_QHD);
   }
 
-  for(uint32_t i=1; i<FRAMELIST_SIZE; i+=4)
-  {
-    list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD);
+  for (uint32_t i = 1; i < FRAMELIST_SIZE; i += 4) {
+    list_insert(framelist + i, head_4ms, EHCI_QTYPE_QHD);
   }
 
-  list_insert(framelist+3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
+  list_insert(framelist + 3, head_8ms, EHCI_QTYPE_QHD);
 
-  period_1ms->terminate    = 1;
+  head_1ms->terminate = 1;
+}
 
-  regs->periodic_list_base = (uint32_t) framelist;
+bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
+{
+  tu_memclr(&ehci_data, sizeof(ehci_data_t));
+
+  ehci_data.regs = (ehci_registers_t*) operatial_reg;
+  ehci_data.cap_regs = (ehci_cap_registers_t*) capability_reg;
+
+  ehci_registers_t* regs = ehci_data.regs;
+
+  // EHCI 4.1 Host Controller Initialization
+
+  //------------- CTRLDSSEGMENT Register (skip) -------------//
+
+  //------------- USB INT Register -------------//
+
+  // disable all the interrupt
+  regs->inten  = 0;
+
+  // clear all status except port change since device maybe connected before this driver is initialized
+  regs->status = (EHCI_INT_MASK_ALL & ~EHCI_INT_MASK_PORT_CHANGE);
+
+  // Enable interrupts
+  regs->inten  = EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
+                 EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_FRAMELIST_ROLLOVER;
+
+  //------------- Asynchronous List -------------//
+  ehci_qhd_t * const async_head = list_get_async_head(rhport);
+  tu_memclr(async_head, sizeof(ehci_qhd_t));
+
+  async_head->next.address               = (uint32_t) async_head; // circular list, next is itself
+  async_head->next.type                  = EHCI_QTYPE_QHD;
+  async_head->head_list_flag             = 1;
+  async_head->qtd_overlay.halted         = 1; // inactive most of time
+  async_head->qtd_overlay.next.terminate = 1; // TODO removed if verified
+
+  regs->async_list_addr = (uint32_t) async_head;
+
+  //------------- Periodic List -------------//
+  init_periodic_list(rhport);
+  regs->periodic_list_base = (uint32_t) ehci_data.period_framelist;
+
+  hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t));
 
   //------------- TT Control (NXP only) -------------//
   regs->nxp_tt_control = 0;
 
   //------------- USB CMD Register -------------//
-  regs->command |= TU_BIT(EHCI_USBCMD_POS_RUN_STOP) | TU_BIT(EHCI_USBCMD_POS_ASYNC_ENABLE) |
-                   TU_BIT(EHCI_USBCMD_POS_PERIOD_ENABLE) |  // TODO enable period list only there is int/iso endpoint
+  regs->command |= EHCI_USBCMD_RUN_STOP | EHCI_USBCMD_PERIOD_SCHEDULE_ENABLE | EHCI_USBCMD_ASYNC_SCHEDULE_ENABLE |
                    FRAMELIST_SIZE_USBCMD_VALUE;
 
   //------------- ConfigFlag Register (skip) -------------//
-  regs->portsc_bm.port_power = 1; // enable port power
+
+  // enable port power bit in portsc. The function of this bit depends on the value of the Port
+  // Power Control (PPC) field in the HCSPARAMS register.
+  if (ehci_data.cap_regs->hcsparams_bm.port_power_control) {
+    // mask out all change bits since they are Write 1 to clear
+    uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_W1C);
+    portsc |= EHCI_PORTSC_MASK_PORT_POWER;
+
+    regs->portsc = portsc;
+  }
 
   return true;
 }
@@ -347,15 +383,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
 
   //------------- Prepare Queue Head -------------//
-  ehci_qhd_t * p_qhd;
-
-  if ( ep_desc->bEndpointAddress == 0 )
-  {
-    p_qhd = qhd_control(dev_addr);
-  }else
-  {
-    p_qhd = qhd_find_free();
-  }
+  ehci_qhd_t *p_qhd = (ep_desc->bEndpointAddress == 0) ? qhd_control(dev_addr) : qhd_find_free();
   TU_ASSERT(p_qhd);
 
   qhd_init(p_qhd, dev_addr, ep_desc);
@@ -370,11 +398,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   {
     case TUSB_XFER_CONTROL:
     case TUSB_XFER_BULK:
-      list_head = (ehci_link_t*) qhd_async_head(rhport);
+      list_head = (ehci_link_t*) list_get_async_head(rhport);
     break;
 
     case TUSB_XFER_INTERRUPT:
-      list_head = get_period_head(rhport, p_qhd->interval_ms);
+      list_head = list_get_period_head(rhport, p_qhd->interval_ms);
     break;
 
     case TUSB_XFER_ISOCHRONOUS:
@@ -383,12 +411,13 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 
     default: break;
   }
-
   TU_ASSERT(list_head);
 
-  // TODO might need to disable async/period list
   list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD);
 
+  hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t));
+  hcd_dcache_clean(list_head, sizeof(ehci_qhd_t));
+
   return true;
 }
 
@@ -400,16 +429,17 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   ehci_qtd_t* td  = &ehci_data.control[dev_addr].qtd;
 
   qtd_init(td, setup_packet, 8);
-  td->pid          = EHCI_PID_SETUP;
-  td->int_on_complete = 1;
-  td->next.terminate  = 1;
+  td->pid = EHCI_PID_SETUP;
 
-  // sw region
-  qhd->p_qtd_list_head = td;
-  qhd->p_qtd_list_tail = td;
+  hcd_dcache_clean(setup_packet, 8);
 
-  // attach TD
-  qhd->qtd_overlay.next.address = (uint32_t) td;
+  // Control endpoint never be stalled. Skip reset Data Toggle since it is fixed per stage
+  if (qhd->qtd_overlay.halted) {
+    qhd->qtd_overlay.halted = false;
+  }
+
+  // attach TD to QHD -> start transferring
+  qhd_attach_qtd(qhd, td);
 
   return true;
 }
@@ -421,51 +451,84 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  if ( epnum == 0 )
-  {
-    ehci_qhd_t* qhd = qhd_control(dev_addr);
-    ehci_qtd_t* qtd = qtd_control(dev_addr);
+  ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr);
+  ehci_qtd_t* qtd;
 
+  if (epnum == 0) {
+    // Control endpoint never be stalled. Skip reset Data Toggle since it is fixed per stage
+    if (qhd->qtd_overlay.halted) {
+      qhd->qtd_overlay.halted = false;
+    }
+
+    qtd = qtd_control(dev_addr);
     qtd_init(qtd, buffer, buflen);
 
-    // first first data toggle is always 1 (data & setup stage)
+    // first data toggle is always 1 (data & setup stage)
     qtd->data_toggle = 1;
     qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
-    qtd->int_on_complete = 1;
-    qtd->next.terminate  = 1;
+  } else {
+    // skip if endpoint is halted
+    TU_VERIFY(!qhd->qtd_overlay.halted);
 
-    // sw region
-    qhd->p_qtd_list_head = qtd;
-    qhd->p_qtd_list_tail = qtd;
+    qtd = qtd_find_free();
+    TU_ASSERT(qtd);
 
-    // attach TD
-    qhd->qtd_overlay.next.address = (uint32_t) qtd;
-  }else
-  {
-    ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
-    ehci_qtd_t *p_qtd = qtd_find_free();
-    TU_ASSERT(p_qtd);
-
-    qtd_init(p_qtd, buffer, buflen);
-    p_qtd->pid = p_qhd->pid;
-
-    // Insert TD to QH
-    qtd_insert_to_qhd(p_qhd, p_qtd);
-
-    p_qhd->p_qtd_list_tail->int_on_complete = 1;
-
-    // attach head QTD to QHD start transferring
-    p_qhd->qtd_overlay.next.address = (uint32_t) p_qhd->p_qtd_list_head;
+    qtd_init(qtd, buffer, buflen);
+    qtd->pid = qhd->pid;
   }
 
+  // IN transfer: invalidate buffer, OUT transfer: clean buffer
+  if (dir) {
+    hcd_dcache_invalidate(buffer, buflen);
+  }else {
+    hcd_dcache_clean(buffer, buflen);
+  }
+
+  // attach TD to QHD -> start transferring
+  qhd_attach_qtd(qhd, qtd);
+
   return true;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
-  ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
-  p_qhd->qtd_overlay.halted = 0;
-  // TODO reset data toggle ?
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+
+  // TODO ISO not supported yet
+  ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr);
+  ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+  TU_VERIFY(qtd != NULL); // no queued transfer
+
+  hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
+  TU_VERIFY(qtd->active); // transfer is already complete
+
+  // HC is still processing, disable HC list schedule before making changes
+  bool const is_period = (qhd->interval_ms > 0);
+
+  ehci_disable_schedule(ehci_data.regs, is_period);
+
+  // check active bit again just in case HC has just processed the TD
+  bool const still_active = qtd->active;
+  if (still_active) {
+    // remove TD from QH overlay
+    qhd->qtd_overlay.next.terminate = 1;
+    hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
+
+    // remove TD from QH software list
+    qhd_remove_qtd(qhd);
+  }
+
+  ehci_enable_schedule(ehci_data.regs, is_period);
+
+  return still_active; // true if removed an active transfer
+}
+
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport;
+  ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr);
+  qhd->qtd_overlay.halted = 0;
+  qhd->qtd_overlay.data_toggle = 0;
+  hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
+
   return true;
 }
 
@@ -476,292 +539,271 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 // async_advance is handshake between usb stack & ehci controller.
 // This isr mean it is safe to modify previously removed queue head from async list.
 // In tinyusb, queue head is only removed when device is unplugged.
-static void async_advance_isr(uint8_t rhport)
+TU_ATTR_ALWAYS_INLINE static inline
+void async_advance_isr(uint8_t rhport)
 {
   (void) rhport;
 
-  ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
-  for(uint32_t i = 0; i < QHD_MAX; i++)
-  {
-    if ( qhd_pool[i].removing )
-    {
+  ehci_qhd_t *qhd_pool = ehci_data.qhd_pool;
+  for (uint32_t i = 0; i < QHD_MAX; i++) {
+    if (qhd_pool[i].removing) {
       qhd_pool[i].removing = 0;
-      qhd_pool[i].used     = 0;
+      qhd_pool[i].used = 0;
     }
   }
 }
 
-static void port_connect_status_change_isr(uint8_t rhport)
-{
+TU_ATTR_ALWAYS_INLINE static inline
+void port_connect_status_change_isr(uint8_t rhport) {
   // NOTE There is an sequence plug->unplug->â€Ļ..-> plug if device is powering with pre-plugged device
-  if (ehci_data.regs->portsc_bm.current_connect_status)
-  {
+  if ( ehci_data.regs->portsc_bm.current_connect_status ) {
     hcd_port_reset(rhport);
     hcd_event_device_attach(rhport, true);
-  }else // device unplugged
+  } else // device unplugged
   {
     hcd_event_device_remove(rhport, true);
   }
 }
 
-static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
-{
-  // free all TDs from the head td to the first active TD
-  while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active)
-  {
-    ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head;
-    bool const is_ioc = (qtd->int_on_complete != 0);
-    uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0);
+// Check queue head for potential transfer complete (successful or error)
+TU_ATTR_ALWAYS_INLINE static inline
+void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
+  hcd_dcache_invalidate(qhd, sizeof(ehci_qhd_t)); // HC may have updated the overlay
+  volatile ehci_qtd_t *qtd_overlay = &qhd->qtd_overlay;
 
-    p_qhd->total_xferred_bytes += qtd->expected_bytes - qtd->total_bytes;
+  // process non-active (completed) QHD with attached (scheduled) TD
+  if ( !qtd_overlay->active && qhd->attached_qtd != NULL ) {
+    xfer_result_t xfer_result;
 
-    // TD need to be freed and removed from qhd, before invoking callback
-    qtd->used = 0; // free QTD
-    qtd_remove_1st_from_qhd(p_qhd);
-
-    if (is_ioc)
-    {
-      hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, p_qhd->total_xferred_bytes, XFER_RESULT_SUCCESS, true);
-      p_qhd->total_xferred_bytes = 0;
-    }
-  }
-}
-
-static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
-{
-  ehci_qhd_t *p_qhd = async_head;
-  do
-  {
-    if ( !p_qhd->qtd_overlay.halted ) // halted or error is processed in error isr
-    {
-      qhd_xfer_complete_isr(p_qhd);
-    }
-    p_qhd = qhd_next(p_qhd);
-  }while(p_qhd != async_head); // async list traversal, stop if loop around
-}
-
-static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms)
-{
-  uint16_t max_loop = 0;
-  uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u);
-  ehci_link_t next_item = * get_period_head(hostid, interval_ms);
-
-  // TODO abstract max loop guard for period
-  while( !next_item.terminate &&
-      !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) &&
-      max_loop < (QHD_MAX + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUH_DEVICE_MAX)
-  {
-    switch ( next_item.type )
-    {
-      case EHCI_QTYPE_QHD:
-      {
-        ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address);
-        if ( !p_qhd_int->qtd_overlay.halted )
-        {
-          qhd_xfer_complete_isr(p_qhd_int);
-        }
+    if ( qtd_overlay->halted ) {
+      if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
+        // Error count = 0 often occurs when device disconnected, or other bus-related error
+        // clear halted bit if not caused by STALL to allow more transfer
+        xfer_result = XFER_RESULT_FAILED;
+        qtd_overlay->halted = false;
+        TU_LOG3("  QHD xfer err count: %d\r\n", qtd_overlay->err_count);
+        // TU_BREAKPOINT(); // TODO skip unplugged device
+      }else {
+        // no error bits are set, endpoint is halted due to STALL
+        xfer_result = XFER_RESULT_STALLED;
       }
+    } else {
+      xfer_result = XFER_RESULT_SUCCESS;
+    }
+
+    ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+    hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); // HC may have written back TD
+
+    uint8_t const dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0;
+    uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
+
+    // invalidate dcache if IN transfer with data
+    if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) {
+      hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
+    }
+
+    // remove and free TD before invoking callback
+    qhd_remove_qtd(qhd);
+
+    // notify usbh
+    uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
+    hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true);
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline
+void proccess_async_xfer_isr(ehci_qhd_t * const list_head)
+{
+  ehci_qhd_t *qhd = list_head;
+
+  do {
+    qhd_xfer_complete_isr(qhd);
+    qhd = qhd_next(qhd);
+  } while ( qhd != list_head ); // async list traversal, stop if loop around
+}
+
+TU_ATTR_ALWAYS_INLINE static inline
+void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms)
+{
+  uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u);
+  ehci_link_t next_link = *list_get_period_head(rhport, interval_ms);
+
+  while (!next_link.terminate) {
+    if (interval_ms > 1 && period_1ms_addr == tu_align32(next_link.address)) {
+      // 1ms period list is end of list for all larger interval
       break;
-
-      case EHCI_QTYPE_ITD: // TODO support hs/fs ISO
-      case EHCI_QTYPE_SITD:
-      case EHCI_QTYPE_FSTN:
-				
-      default: break;
     }
 
-    next_item = *list_next(&next_item);
-    max_loop++;
-  }
-}
+    uintptr_t const entry_addr = tu_align32(next_link.address);
 
-static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
-{
-  if ( (p_qhd->dev_addr != 0 && p_qhd->qtd_overlay.halted) || // addr0 cannot be protocol STALL
-        qhd_has_xact_error(p_qhd) )
-  {
-    // current qhd has error in transaction
-    xfer_result_t error_event;
-
-    // no error bits are set, endpoint is halted due to STALL
-    error_event = qhd_has_xact_error(p_qhd) ? XFER_RESULT_FAILED : XFER_RESULT_STALLED;
-
-    p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
-
-//    if ( XFER_RESULT_FAILED == error_event )    TU_BREAKPOINT(); // TODO skip unplugged device
-
-    p_qhd->p_qtd_list_head->used = 0; // free QTD
-    qtd_remove_1st_from_qhd(p_qhd);
-
-    if ( 0 == p_qhd->ep_number )
-    {
-      // control cannot be halted --> clear all qtd list
-      p_qhd->p_qtd_list_head = NULL;
-      p_qhd->p_qtd_list_tail = NULL;
-
-      p_qhd->qtd_overlay.next.terminate      = 1;
-      p_qhd->qtd_overlay.alternate.terminate = 1;
-      p_qhd->qtd_overlay.halted              = 0;
-
-      ehci_qtd_t *p_setup = qtd_control(p_qhd->dev_addr);
-      p_setup->used = 0;
-    }
-
-    // call USBH callback
-    hcd_event_xfer_complete(p_qhd->dev_addr, tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0), p_qhd->total_xferred_bytes, error_event, true);
-
-    p_qhd->total_xferred_bytes = 0;
-  }
-}
-
-static void xfer_error_isr(uint8_t hostid)
-{
-  //------------- async list -------------//
-  ehci_qhd_t * const async_head = qhd_async_head(hostid);
-  ehci_qhd_t *p_qhd = async_head;
-  do
-  {
-    qhd_xfer_error_isr( p_qhd );
-    p_qhd = qhd_next(p_qhd);
-  }while(p_qhd != async_head); // async list traversal, stop if loop around
-
-  //------------- TODO refractor period list -------------//
-  uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u);
-  for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2)
-  {
-    ehci_link_t next_item = * get_period_head(hostid, interval_ms);
-
-    // TODO abstract max loop guard for period
-    while( !next_item.terminate &&
-           !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) )
-    {
-      switch ( next_item.type )
-      {
-        case EHCI_QTYPE_QHD:
-        {
-          ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address);
-          qhd_xfer_error_isr(p_qhd_int);
-        }
+    switch (next_link.type) {
+      case EHCI_QTYPE_QHD: {
+        ehci_qhd_t *qhd = (ehci_qhd_t *) entry_addr;
+        qhd_xfer_complete_isr(qhd);
+      }
         break;
 
-				// TODO support hs/fs ISO
-        case EHCI_QTYPE_ITD:
-        case EHCI_QTYPE_SITD:
-        case EHCI_QTYPE_FSTN:
-        default: break;
-      }
-
-      next_item = *list_next(&next_item);
+      // TODO support hs/fs ISO
+      case EHCI_QTYPE_ITD:
+      case EHCI_QTYPE_SITD:
+      case EHCI_QTYPE_FSTN:
+      default:
+        break;
     }
+
+    next_link = *list_next(&next_link);
   }
 }
 
-#if CFG_TUSB_DEBUG >= EHCI_DBG
-
-static inline void print_portsc(ehci_registers_t* regs)
-{
-  TU_LOG_HEX(EHCI_DBG, regs->portsc);
-  TU_LOG(EHCI_DBG, "  Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status);
-  TU_LOG(EHCI_DBG, "  Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change);
-  TU_LOG(EHCI_DBG, "  Port Enabled          : %u\r\n", regs->portsc_bm.port_enabled);
-  TU_LOG(EHCI_DBG, "  Port Enabled Change   : %u\r\n", regs->portsc_bm.port_enable_change);
-
-  TU_LOG(EHCI_DBG, "  Port Reset            : %u\r\n", regs->portsc_bm.port_reset);
-  TU_LOG(EHCI_DBG, "  Port Power            : %u\r\n", regs->portsc_bm.port_power);
-}
-
-#else
-
-#define print_portsc(_reg)
-
-#endif
-
 //------------- Host Controller Driver's Interrupt Handler -------------//
-void hcd_int_handler(uint8_t rhport)
-{
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void) in_isr;
   ehci_registers_t* regs = ehci_data.regs;
+  uint32_t const int_status = regs->status;
 
-  uint32_t int_status = regs->status;
-  int_status &= regs->inten;
-  
-  regs->status = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;
-
-  if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER)
-  {
-    ehci_data.uframe_number += (FRAMELIST_SIZE << 3);
+  if (int_status & EHCI_INT_MASK_HC_HALTED) {
+    // something seriously wrong, maybe forget to flush/invalidate cache
+    TU_BREAKPOINT();
+    TU_LOG1("  HC halted\r\n");
+    return;
   }
 
-  if (int_status & EHCI_INT_MASK_PORT_CHANGE)
-  {
-    uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_ALL;
-    print_portsc(regs);
+  if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER) {
+    ehci_data.uframe_number += (FRAMELIST_SIZE << 3);
+    regs->status = EHCI_INT_MASK_FRAMELIST_ROLLOVER; // Acknowledge
+  }
 
-    if (regs->portsc_bm.connect_status_change)
-    {
+  if (int_status & EHCI_INT_MASK_PORT_CHANGE) {
+    // Including: Force port resume, over-current change, enable/disable change and connect status change.
+    uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_W1C;
+    // print_portsc(regs);
+
+    if (regs->portsc_bm.connect_status_change) {
       port_connect_status_change_isr(rhport);
     }
 
     regs->portsc |= port_status; // Acknowledge change bits in portsc
+    regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge
   }
 
-  if (int_status & EHCI_INT_MASK_ERROR)
-  {
-    xfer_error_isr(rhport);
-  }
+  // A USB transfer is completed (OK or error)
+  uint32_t const usb_int = int_status & (EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR);
+  if (usb_int) {
+    proccess_async_xfer_isr(list_get_async_head(rhport));
 
-  //------------- some QTD/SITD/ITD with IOC set is completed -------------//
-  if (int_status & EHCI_INT_MASK_NXP_ASYNC)
-  {
-    async_list_xfer_complete_isr( qhd_async_head(rhport) );
-  }
-
-  if (int_status & EHCI_INT_MASK_NXP_PERIODIC)
-  {
-    for (uint32_t i=1; i <= FRAMELIST_SIZE; i *= 2)
-    {
-      period_list_xfer_complete_isr( rhport, i );
+    for ( uint32_t i = 1; i <= FRAMELIST_SIZE; i *= 2 ) {
+      process_period_xfer_isr(rhport, i);
     }
+
+    regs->status = usb_int; // Acknowledge
   }
 
   //------------- There is some removed async previously -------------//
-  if (int_status & EHCI_INT_MASK_ASYNC_ADVANCE) // need to place after EHCI_INT_MASK_NXP_ASYNC
-  {
+  // need to place after EHCI_INT_MASK_NXP_ASYNC
+  if (int_status & EHCI_INT_MASK_ASYNC_ADVANCE) {
     async_advance_isr(rhport);
+    regs->status = EHCI_INT_MASK_ASYNC_ADVANCE; // Acknowledge
   }
 }
 
 //--------------------------------------------------------------------+
-// HELPER
+// List Managing Helper
 //--------------------------------------------------------------------+
 
+// Get head of periodic list
+TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms) {
+  (void) rhport;
+  return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min32(FRAMELIST_SIZE, interval_ms) ) ];
+}
 
-//------------- queue head helper -------------//
-static inline ehci_qhd_t* qhd_find_free (void)
+// Get head of async list
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport) {
+  (void) rhport;
+  return qhd_control(0); // control qhd of dev0 is used as async head
+}
+
+TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next(ehci_link_t const *p_link) {
+  return (ehci_link_t*) tu_align32(p_link->address);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
 {
-  for (uint32_t i=0; i<QHD_MAX; i++)
-  {
+  new->address = current->address;
+  current->address = ((uint32_t) new) | (new_type << 1);
+}
+
+// Remove all queue head belong to this device address
+static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) {
+  ehci_link_t* prev = list_head;
+
+  while (prev && !prev->terminate) {
+    ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev);
+
+    // done if loop back to head
+    if ( (uintptr_t) qhd == (uintptr_t) list_head) {
+      break;
+    }
+
+    if ( qhd->dev_addr == dev_addr ) {
+      // TODO deactivate all TD, wait for QHD to inactive before removal
+      prev->address = qhd->next.address;
+
+      // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller)
+      qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1);
+
+      if ( qhd->int_smask )
+      {
+        // period list queue element is guarantee to be free in the next frame (1 ms)
+        qhd->used = 0;
+      }else
+      {
+        // async list use async advance handshake
+        // mark as removing, will completely re-usable when async advance isr occurs
+        qhd->removing = 1;
+      }
+
+      hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
+      hcd_dcache_clean(prev, sizeof(ehci_qhd_t));
+    }else {
+      prev = list_next(prev);
+    }
+  }
+}
+
+
+//--------------------------------------------------------------------+
+// Queue Header helper
+//--------------------------------------------------------------------+
+
+// Get queue head for control transfer (always available)
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr) {
+  return &ehci_data.control[dev_addr].qhd;
+}
+
+// Find a free queue head
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_find_free(void) {
+  for ( uint32_t i = 0; i < QHD_MAX; i++ ) {
     if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i];
   }
-
   return NULL;
 }
 
-static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd)
-{
-  return (ehci_qhd_t*) tu_align32(p_qhd->next.address);
+// Next queue head link
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_next(ehci_qhd_t const *p_qhd) {
+  return (ehci_qhd_t *) tu_align32(p_qhd->next.address);
 }
 
-static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
-{
-  ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
+// Get queue head from device + endpoint address
+static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) {
+  if ( 0 == tu_edpt_number(ep_addr) ) {
+    return qhd_control(dev_addr);
+  }
 
-  for(uint32_t i=0; i<QHD_MAX; i++)
-  {
+  ehci_qhd_t *qhd_pool = ehci_data.qhd_pool;
+
+  for ( uint32_t i = 0; i < QHD_MAX; i++ ) {
     if ( (qhd_pool[i].dev_addr == dev_addr) &&
-          ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) )
-    {
+         ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) ) {
       return &qhd_pool[i];
     }
   }
@@ -769,50 +811,11 @@ static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
   return NULL;
 }
 
-//------------- TD helper -------------//
-static inline ehci_qtd_t* qtd_find_free(void)
-{
-  for (uint32_t i=0; i<QTD_MAX; i++)
-  {
-    if ( !ehci_data.qtd_pool[i].used ) return &ehci_data.qtd_pool[i];
-  }
-
-  return NULL;
-}
-
-static inline ehci_qtd_t* qtd_next(ehci_qtd_t const * p_qtd )
-{
-  return (ehci_qtd_t*) tu_align32(p_qtd->next.address);
-}
-
-static inline void qtd_remove_1st_from_qhd(ehci_qhd_t *p_qhd)
-{
-  if (p_qhd->p_qtd_list_head == p_qhd->p_qtd_list_tail) // last TD --> make it NULL
-  {
-    p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = NULL;
-  }else
-  {
-    p_qhd->p_qtd_list_head = qtd_next( p_qhd->p_qtd_list_head );
-  }
-}
-
-static inline void qtd_insert_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new)
-{
-  if (p_qhd->p_qtd_list_head == NULL) // empty list
-  {
-    p_qhd->p_qtd_list_head               = p_qhd->p_qtd_list_tail = p_qtd_new;
-  }else
-  {
-    p_qhd->p_qtd_list_tail->next.address = (uint32_t) p_qtd_new;
-    p_qhd->p_qtd_list_tail               = p_qtd_new;
-  }
-}
-
+// Init queue head with endpoint descriptor
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
   // address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise)
-  if (dev_addr != 0)
-  {
+  if (dev_addr != 0) {
     tu_memclr(p_qhd, sizeof(ehci_qhd_t));
   }
 
@@ -839,7 +842,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
     if (TUSB_SPEED_HIGH == p_qhd->ep_speed)
     {
       TU_ASSERT( interval <= 16, );
-      if ( interval < 4) // sub milisecond interval
+      if ( interval < 4) // sub millisecond interval
       {
         p_qhd->interval_ms = 0;
         p_qhd->int_smask   = (interval == 1) ? TU_BIN8(11111111) :
@@ -862,58 +865,84 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
     p_qhd->int_smask = p_qhd->fl_int_cmask = 0;
   }
 
-  p_qhd->fl_hub_addr     = devtree_info.hub_addr;
-  p_qhd->fl_hub_port     = devtree_info.hub_port;
-  p_qhd->mult            = 1; // TODO not use high bandwidth/park mode yet
+  p_qhd->fl_hub_addr  = devtree_info.hub_addr;
+  p_qhd->fl_hub_port  = devtree_info.hub_port;
+  p_qhd->mult         = 1; // TODO not use high bandwidth/park mode yet
 
   //------------- HCD Management Data -------------//
-  p_qhd->used            = 1;
-  p_qhd->removing        = 0;
-  p_qhd->p_qtd_list_head = NULL;
-  p_qhd->p_qtd_list_tail = NULL;
+  p_qhd->used         = 1;
+  p_qhd->removing     = 0;
+  p_qhd->attached_qtd = NULL;
   p_qhd->pid = tu_edpt_dir(ep_desc->bEndpointAddress) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint
 
   //------------- active, but no TD list -------------//
   p_qhd->qtd_overlay.halted              = 0;
   p_qhd->qtd_overlay.next.terminate      = 1;
   p_qhd->qtd_overlay.alternate.terminate = 1;
+
   if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT)
   {
     p_qhd->qtd_overlay.ping_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11
   }
 }
 
-static void qtd_init(ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes)
-{
-  tu_memclr(p_qtd, sizeof(ehci_qtd_t));
+// Attach a TD to queue head
+static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd) {
+  qhd->attached_qtd = qtd;
+  qhd->attached_buffer = qtd->buffer[0];
 
-  p_qtd->used                = 1;
+  // clean and invalidate cache before physically write
+  hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t));
 
-  p_qtd->next.terminate      = 1; // init to null
-  p_qtd->alternate.terminate = 1; // not used, always set to terminated
-  p_qtd->active              = 1;
-  p_qtd->err_count           = 3; // TODO 3 consecutive errors tolerance
-  p_qtd->data_toggle         = 0;
-  p_qtd->total_bytes         = total_bytes;
-  p_qtd->expected_bytes      = total_bytes;
+  qhd->qtd_overlay.next.address = (uint32_t) qtd;
+  hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
+}
 
-  p_qtd->buffer[0] = (uint32_t) buffer;
-  for(uint8_t i=1; i<5; i++)
-  {
-    p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
+// Remove an attached TD from queue head
+static void qhd_remove_qtd(ehci_qhd_t *qhd) {
+  ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+
+  qhd->attached_qtd = NULL;
+  qhd->attached_buffer = 0;
+  hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
+
+  qtd->used = 0; // free QTD
+  hcd_dcache_clean(qtd, sizeof(ehci_qtd_t));
+}
+
+//--------------------------------------------------------------------+
+// Queue TD helper
+//--------------------------------------------------------------------+
+
+// Get TD for control transfer (always available)
+TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr) {
+  return &ehci_data.control[dev_addr].qtd;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t *qtd_find_free(void) {
+  for (uint32_t i = 0; i < QTD_MAX; i++) {
+    if (!ehci_data.qtd_pool[i].used) return &ehci_data.qtd_pool[i];
+  }
+  return NULL;
+}
+
+static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) {
+  tu_memclr(qtd, sizeof(ehci_qtd_t));
+  qtd->used                = 1;
+
+  qtd->next.terminate      = 1; // init to null
+  qtd->alternate.terminate = 1; // not used, always set to terminated
+  qtd->active              = 1;
+  qtd->err_count           = 3; // TODO 3 consecutive errors tolerance
+  qtd->data_toggle         = 0;
+  qtd->int_on_complete     = 1;
+  qtd->total_bytes         = total_bytes;
+  qtd->expected_bytes      = total_bytes;
+
+  qtd->buffer[0] = (uint32_t) buffer;
+  for(uint8_t i=1; i<5; i++) {
+    qtd->buffer[i] |= tu_align4k(qtd->buffer[i - 1] ) + 4096;
   }
 }
 
-//------------- List Managing Helper -------------//
-static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
-{
-  new->address = current->address;
-  current->address = ((uint32_t) new) | (new_type << 1);
-}
-
-static inline ehci_link_t* list_next(ehci_link_t *p_link_pointer)
-{
-  return (ehci_link_t*) tu_align32(p_link_pointer->address);
-}
-
 #endif
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index ff9ae12e7..457adc1d3 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -81,6 +81,8 @@ typedef union {
 	};
 }ehci_link_t;
 
+TU_VERIFY_STATIC( sizeof(ehci_link_t) == 4, "size is not correct" );
+
 /// Queue Element Transfer Descriptor
 /// Qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with TU_ATTR_ALIGNED(32)
 typedef struct
@@ -114,7 +116,7 @@ typedef struct
 	volatile uint32_t current_page         : 3  ; ///< Index into the qTD buffer pointer list
 	uint32_t int_on_complete               : 1  ; ///< Interrupt on complete
 	volatile uint32_t total_bytes          : 15 ; ///< Transfer bytes, decreased during transaction
-	volatile uint32_t data_toggle          : 1  ; ///< Data Toogle bit
+	volatile uint32_t data_toggle          : 1  ; ///< Data Toggle bit
 
 
 	/// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
@@ -160,13 +162,14 @@ typedef struct TU_ATTR_ALIGNED(32)
 	uint8_t used;
 	uint8_t removing; // removed from asyn list, waiting for async advance
 	uint8_t pid;
-	uint8_t interval_ms; // polling interval in frames (or milisecond)
+	uint8_t interval_ms; // polling interval in frames (or millisecond)
 
-	uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
-	uint8_t reserved2[2];
+	uint8_t TU_RESERVED[4];
 
-	ehci_qtd_t * volatile p_qtd_list_head;	// head of the scheduled TD list
-	ehci_qtd_t * volatile p_qtd_list_tail;	// tail of the scheduled TD list
+  // Attached TD management, note usbh will only queue 1 TD per QHD.
+  // buffer for dcache invalidate since td's buffer is modified by HC and finding initial buffer address is not trivial
+  uint32_t attached_buffer;
+	ehci_qtd_t * volatile attached_qtd;
 } ehci_qhd_t;
 
 TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" );
@@ -225,7 +228,7 @@ typedef struct TU_ATTR_ALIGNED(32)
 	uint16_t reserved ; ///< reserved
 
 	// Word 3: siTD Transfer Status and Control
-	// Status [7:0] TODO indentical to qTD Token'status --> refractor later
+	// Status [7:0] TODO identical to qTD Token'status --> refactor later
 	volatile uint32_t                 : 1  ; // reserved
 	volatile uint32_t split_state     : 1  ;
 	volatile uint32_t missed_uframe   : 1  ;
@@ -245,14 +248,6 @@ typedef struct TU_ATTR_ALIGNED(32)
 	/// Word 4-5: Buffer Pointer List
 	uint32_t buffer[2];		// buffer[1] TP: Transaction Position - T-Count: Transaction Count
 
-// 	union{
-// 		uint32_t BufferPointer1;
-// 		struct  {
-// 			volatile uint32_t TCount : 3;
-// 			volatile uint32_t TPosition : 2;
-// 		};
-// 	};
-
 	/*---------- Word 6 ----------*/
 	ehci_link_t back;
 
@@ -267,53 +262,63 @@ TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" );
 //--------------------------------------------------------------------+
 // EHCI Operational Register
 //--------------------------------------------------------------------+
-enum ehci_interrupt_mask_{
+enum {
+  // Bit 0-5 has maskable in interrupt enabled register
   EHCI_INT_MASK_USB                   = TU_BIT(0),
   EHCI_INT_MASK_ERROR                 = TU_BIT(1),
   EHCI_INT_MASK_PORT_CHANGE           = TU_BIT(2),
-
   EHCI_INT_MASK_FRAMELIST_ROLLOVER    = TU_BIT(3),
   EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR = TU_BIT(4),
   EHCI_INT_MASK_ASYNC_ADVANCE         = TU_BIT(5),
+
   EHCI_INT_MASK_NXP_SOF               = TU_BIT(7),
 
-  EHCI_INT_MASK_NXP_ASYNC             = TU_BIT(18),
-  EHCI_INT_MASK_NXP_PERIODIC          = TU_BIT(19),
+  EHCI_INT_MASK_HC_HALTED             = TU_BIT(12),
+  EHCI_INT_MASK_RECLAIMATION          = TU_BIT(13),
+  EHCI_INT_MASK_PERIODIC_SCHED_STATUS = TU_BIT(14),
+  EHCI_INT_MASK_ASYNC_SCHED_STATUS    = TU_BIT(15),
 
   EHCI_INT_MASK_ALL                   =
       EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
       EHCI_INT_MASK_FRAMELIST_ROLLOVER | EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR |
-      EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF |
-      EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC
+      EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF
 };
 
-enum ehci_usbcmd_pos_ {
-  EHCI_USBCMD_POS_RUN_STOP               = 0,
-  EHCI_USBCMD_POS_FRAMELIST_SIZE         = 2,
-  EHCI_USBCMD_POS_PERIOD_ENABLE          = 4,
-  EHCI_USBCMD_POS_ASYNC_ENABLE           = 5,
-  EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB = 15,
-  EHCI_USBCMD_POS_INTERRUPT_THRESHOLD    = 16
+enum {
+  EHCI_USBCMD_FRAMELIST_SIZE_SHIFT              = 2, // [2..3]
+  EHCI_USBCMD_CHIPIDEA_FRAMELIST_SIZE_MSB_SHIFT = 15,
+  EHCI_USBCMD_INTERRUPT_THRESHOLD_SHIFT         = 16
 };
 
-enum ehci_portsc_change_mask_{
+enum {
+  EHCI_USBCMD_RUN_STOP                       = TU_BIT(0), // [0..0] 1 = Run, 0 = Stop
+  EHCI_USBCMD_HCRESET                        = TU_BIT(1), // [1..1] SW write 1 to reset HC, clear by HC when complete
+  EHCI_USBCMD_PERIOD_SCHEDULE_ENABLE         = TU_BIT(4), // [4..4] Enable periodic schedule
+  EHCI_USBCMD_ASYNC_SCHEDULE_ENABLE          = TU_BIT(5), // [5..5] Enable async schedule
+  EHCI_USBCMD_INTR_ON_ASYNC_ADVANCE_DOORBELL = TU_BIT(6), // [6..6] Tell HC to interrupt next time it advances async list. Clear by HC
+};
+
+enum {
   EHCI_PORTSC_MASK_CURRENT_CONNECT_STATUS = TU_BIT(0),
   EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE  = TU_BIT(1),
   EHCI_PORTSC_MASK_PORT_EANBLED           = TU_BIT(2),
-  EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE     = TU_BIT(3),
+  EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE     = TU_BIT(3),
   EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE    = TU_BIT(5),
+  EHCI_PORTSC_MASK_FORCE_RESUME           = TU_BIT(6),
+  EHCI_PORTSC_MASK_PORT_SUSPEND           = TU_BIT(7),
   EHCI_PORTSC_MASK_PORT_RESET             = TU_BIT(8),
+  EHCI_PORTSC_MASK_PORT_POWER             = TU_BIT(12),
 
-  EHCI_PORTSC_MASK_ALL =
-      EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
-      EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE |
-      EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
+  EHCI_PORTSC_MASK_W1C =
+    EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
+    EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE |
+    EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
 };
 
 typedef volatile struct
 {
   union {
-    uint32_t command;
+    uint32_t command; // 0x00
 
     struct {
       uint32_t run_stop               : 1 ; ///< 1=Run. 0=Stop
@@ -333,7 +338,7 @@ typedef volatile struct
   };
 
   union {
-    uint32_t status;
+    uint32_t status; // 0x04
 
     struct {
       uint32_t usb                   : 1  ; ///< qTD with IOC is retired
@@ -350,14 +355,14 @@ typedef volatile struct
       uint32_t periodic_status       : 1  ; ///< Periodic schedule status
       uint32_t async_status          : 1  ; ///< Async schedule status
       uint32_t                       : 2  ;
-      uint32_t nxp_int_async         : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected andthe packet is on the asynchronous schedule.
-      uint32_t nxp_int_period        : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the periodic schedule.
+      uint32_t nxp_int_async         : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule.
+      uint32_t nxp_int_period        : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule.
       uint32_t                       : 12 ;
     }status_bm;
   };
 
   union{
-    uint32_t inten;
+    uint32_t inten; // 0x08
 
     struct {
       uint32_t usb                   : 1  ;
@@ -375,43 +380,87 @@ typedef volatile struct
     }inten_bm;
   };
 
-  uint32_t frame_index        ; ///< Micro frame counter
-  uint32_t ctrl_ds_seg        ; ///< Control Data Structure Segment
-  uint32_t periodic_list_base ; ///< Beginning address of perodic frame list
-  uint32_t async_list_addr    ; ///< Address of next async QHD to be executed
+  uint32_t frame_index        ; ///< 0x0C Micro frame counter
+  uint32_t ctrl_ds_seg        ; ///< 0x10 Control Data Structure Segment
+  uint32_t periodic_list_base ; ///< 0x14 Beginning address of perodic frame list
+  uint32_t async_list_addr    ; ///< 0x18 Address of next async QHD to be executed
   uint32_t nxp_tt_control     ; ///< nxp embedded transaction translator (reserved by EHCI specs)
   uint32_t reserved[8]        ;
-  uint32_t config_flag        ; ///< not used by NXP
+  uint32_t config_flag        ; ///< 0x40 not used by NXP
 
   union {
-    uint32_t portsc             ; ///< port status and control
-    struct {
-      uint32_t current_connect_status      : 1; ///< 0: No device, 1: Device is present on port
-      uint32_t connect_status_change       : 1; ///< Change in Current Connect Status
-      uint32_t port_enabled                : 1; ///< Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable
-      uint32_t port_enable_change          : 1; ///< Port Enabled has changed
-      uint32_t over_current_active         : 1; ///< Port has an over-current condition
-      uint32_t over_current_change         : 1; ///< Change to Over-current Active
-      uint32_t force_port_resume           : 1; ///< Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit.
-      uint32_t suspend                     : 1; ///< Port in suspend state
-      uint32_t port_reset                  : 1; ///< 1=Port is in Reset. 0=Port is not in Reset
-      uint32_t nxp_highspeed_status        : 1; ///< NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode
-      uint32_t line_status                 : 2; ///< D+/D- state: 00: SE0, 10: J-state, 01: K-state
-      uint32_t port_power                  : 1; ///< 0= power off, 1= power on
-      uint32_t port_owner                  : 1; ///< not used by NXP
-      uint32_t port_indicator_control      : 2; ///< 00b: off, 01b: Amber, 10b: green, 11b: undefined
-      uint32_t port_test_control           : 4; ///< Port test mode, not used by tinyusb
-      uint32_t wake_on_connect_enable      : 1; ///< Enables device connects as wake-up events
-      uint32_t wake_on_disconnect_enable   : 1; ///< Enables device disconnects as wake-up events
-      uint32_t wake_on_over_current_enable : 1; ///< Enables over-current conditions as wake-up events
-      uint32_t nxp_phy_clock_disable       : 1; ///< NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock
-      uint32_t nxp_port_force_fullspeed    : 1; ///< NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
-      uint32_t TU_RESERVED                 : 1;
-      uint32_t nxp_port_speed              : 2; ///< NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed
+    // mixed with RW and R/WC bits, care should be taken when writing to this register
+    uint32_t portsc           ; ///< 0x44 port status and control
+    const struct {
+      uint32_t current_connect_status      : 1; ///< 00: 0: No device, 1: Device is present on port
+      uint32_t connect_status_change       : 1; ///< 01: [R/WC] Change in Current Connect Status
+      uint32_t port_enabled                : 1; ///< 02: Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable
+      uint32_t port_enable_change          : 1; ///< 03: [R/WC] Port Enabled has changed
+      uint32_t over_current_active         : 1; ///< 04: Port has an over-current condition
+      uint32_t over_current_change         : 1; ///< 05: [R/WC] Change to Over-current Active
+      uint32_t force_port_resume           : 1; ///< 06: Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit.
+      uint32_t suspend                     : 1; ///< 07: Port in suspend state
+      uint32_t port_reset                  : 1; ///< 08: 1=Port is in Reset. 0=Port is not in Reset
+      uint32_t nxp_highspeed_status        : 1; ///< 09: NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode
+      uint32_t line_status                 : 2; ///< 10-11: D+/D- state: 00: SE0, 10: J-state, 01: K-state
+      uint32_t port_power                  : 1; ///< 12: 0= power off, 1= power on
+      uint32_t port_owner                  : 1; ///< 13: not used by NXP
+      uint32_t port_indicator_control      : 2; ///< 14-15: 00b: off, 01b: Amber, 10b: green, 11b: undefined
+      uint32_t port_test_control           : 4; ///< 16-19: Port test mode, not used by tinyusb
+      uint32_t wake_on_connect_enable      : 1; ///< 20: Enables device connects as wake-up events
+      uint32_t wake_on_disconnect_enable   : 1; ///< 21: Enables device disconnects as wake-up events
+      uint32_t wake_on_over_current_enable : 1; ///< 22: Enables over-current conditions as wake-up events
+      uint32_t nxp_phy_clock_disable       : 1; ///< 23: NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock
+      uint32_t nxp_port_force_fullspeed    : 1; ///< 24: NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
+      uint32_t TU_RESERVED                 : 1; ///< 25
+      uint32_t nxp_port_speed              : 2; ///< 26-27: NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed
       uint32_t TU_RESERVED                 : 4;
     }portsc_bm;
   };
-}ehci_registers_t;
+} ehci_registers_t;
+
+//--------------------------------------------------------------------+
+// Capability Registers
+//--------------------------------------------------------------------+
+typedef volatile struct {
+  uint8_t caplength;   // 0x00
+  uint8_t TU_RESERVED; // 0x01
+  uint16_t hciversion; // 0x02
+
+  union {
+    uint32_t hcsparams; // 0x04
+    struct {
+      uint32_t num_ports          : 4; // [00:03]
+      uint32_t port_power_control : 1; // [04]
+      uint32_t TU_RESERVED        : 2; // [05:06]
+      uint32_t port_route_rule    : 1; // [07]
+      uint32_t n_pcc              : 4; // [08:11] Number of Ports per Companion Controller
+      uint32_t n_cc               : 4; // [12:15] Number of Companion Controllers
+      uint32_t port_ind           : 1; // [16] Port Indicators
+      uint32_t TU_RESERVED        : 3; // [17:19]
+      uint32_t n_ptt              : 4; // [20:23] ChipIdea: Number of Ports per Transaction Translator
+      uint32_t n_tt               : 4; // [24:27] ChipIdea: Number of Transaction Translators
+      uint32_t TU_RESERVED        : 4; // [28:31]
+    } hcsparams_bm;
+  };
+
+  union {
+    uint32_t hccparams; // 0x08
+    struct {
+      uint32_t addr_64bit                   : 1; // [00] 64-bit Addressing Capability
+      uint32_t programmable_frame_list_flag : 1; // [01] Programmable Frame List Flag
+      uint32_t async_park_cap               : 1; // [02] Asynchronous Schedule Park Capability
+      uint32_t TU_RESERVED                  : 1; // [03]
+      uint32_t iso_schedule_threshold       : 4; // [4:7] Isochronous Scheduling Threshold
+      uint32_t eecp                         : 8; // [8:15] EHCI Extended Capabilities Pointer
+      uint32_t TU_RESERVED                  : 16;// [16:31]
+    } hccparams_bm;
+  };
+
+  uint32_t hcsp_portroute; // 0x0C HCSP Port Route Register
+} ehci_cap_registers_t;
+
+TU_VERIFY_STATIC(sizeof(ehci_cap_registers_t) == 16, "size is not correct");
 
 #ifdef __cplusplus
  }
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index 0b75af627..1b6aae026 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -31,16 +31,27 @@
 #if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2) ||  (CFG_TUSB_MCU == OPT_MCU_ESP32S3)) && CFG_TUD_ENABLED)
 
 // Espressif
-#include "freertos/xtensa_api.h"
+#include "xtensa/xtensa_api.h"
+
 #include "esp_intr_alloc.h"
 #include "esp_log.h"
 #include "soc/dport_reg.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/usb_periph.h"
+#include "soc/usb_reg.h"
+#include "soc/usb_struct.h"
 #include "soc/periph_defs.h" // for interrupt source
 
 #include "device/dcd.h"
 
+#ifndef USB_OUT_EP_NUM
+#define USB_OUT_EP_NUM ((int) (sizeof(USB0.out_ep_reg) / sizeof(USB0.out_ep_reg[0])))
+#endif
+
+#ifndef USB_IN_EP_NUM
+#define USB_IN_EP_NUM ((int) (sizeof(USB0.in_ep_reg) / sizeof(USB0.in_ep_reg[0])))
+#endif
+
 // Max number of bi-directional endpoints including EP0
 // Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0
 // We should probably prohibit enabling Endpoint IN > 4 (not done yet)
@@ -161,8 +172,8 @@ static void enum_done_processing(void)
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
   ESP_LOGV(TAG, "DCD init - Start");
 
   // A. Disconnect
@@ -196,9 +207,11 @@ void dcd_init(uint8_t rhport)
                  USB_USBRSTMSK_M   |
                  USB_ENUMDONEMSK_M |
                  USB_RESETDETMSK_M |
+                 USB_WKUPINT_M |
                  USB_DISCONNINTMSK_M; // host most only
 
   dcd_connect(rhport);
+  return true;
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
@@ -741,7 +754,7 @@ static void handle_epin_ints(void)
 
       // XFER Timeout
       if (USB0.in_ep_reg[n].diepint & USB_D_TIMEOUT0_M) {
-        // Clear interrupt or enpoint will hang.
+        // Clear interrupt or endpoint will hang.
         USB0.in_ep_reg[n].diepint = USB_D_TIMEOUT0_M;
         // Maybe retry?
       }
@@ -874,4 +887,3 @@ void dcd_int_disable (uint8_t rhport)
 }
 
 #endif // #if OPT_MCU_ESP32S2 || OPT_MCU_ESP32S3
-
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 0ba53d4d0..4fce08dd9 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -1,7 +1,8 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji KITAYAMA
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -26,8 +27,10 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && \
-  TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_MUSB)
+
+#define MUSB_DEBUG 2
+#define MUSB_REGS(rhport)   ((musb_regs_t*) MUSB_BASES[rhport])
 
 #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
 /* GCC warns that an address may be unaligned, even though
@@ -35,48 +38,30 @@
 _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
 #endif
 
+#include "musb_type.h"
 #include "device/dcd.h"
 
-#if TU_CHECK_MCU(OPT_MCU_MSP432E4)
-  #include "musb_msp432e.h"
-
-#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129)
-  #include "musb_tm4c.h"
-
-  // HACK generalize later
-  #include "musb_type.h"
-  #define FIFO0_WORD FIFO0
-  #define FIFO1_WORD FIFO1
-
+// Following symbols must be defined by port header
+// - musb_dcd_int_enable/disable/clear/get_enable
+// - musb_dcd_int_handler_enter/exit
+#if defined(TUP_USBIP_MUSB_TI)
+  #include "musb_ti.h"
+#elif defined(TUP_USBIP_MUSB_ADI)
+  #include "musb_max32.h"
 #else
-  #error "Unsupported MCUs"
+  #error "Unsupported MCU"
 #endif
 
 /*------------------------------------------------------------------
  * MACRO TYPEDEF CONSTANT ENUM DECLARATION
  *------------------------------------------------------------------*/
+
 #define REQUEST_TYPE_INVALID  (0xFFu)
 
-typedef struct {
-  uint_fast16_t beg; /* offset of including first element */
-  uint_fast16_t end; /* offset of excluding the last element */
-} free_block_t;
-
-typedef struct TU_ATTR_PACKED {
-  uint16_t TXMAXP;
-  uint8_t  TXCSRL;
-  uint8_t  TXCSRH;
-  uint16_t RXMAXP;
-  uint8_t  RXCSRL;
-  uint8_t  RXCSRH;
-  uint16_t RXCOUNT;
-  uint16_t RESERVED[3];
-} hw_endpoint_t;
-
 typedef union {
-  uint8_t   u8;
-  uint16_t  u16;
-  uint32_t  u32;
+  volatile uint8_t   u8;
+  volatile uint16_t  u16;
+  volatile uint32_t  u32;
 } hw_fifo_t;
 
 typedef struct TU_ATTR_PACKED
@@ -92,134 +77,97 @@ typedef struct
   uint16_t     remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
   int8_t       status_out;
   pipe_state_t pipe0;
-  pipe_state_t pipe[2][7];   /* pipe[direction][endpoint number - 1] */
+  pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX-1];   /* pipe[direction][endpoint number - 1] */
   uint16_t     pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */
 } dcd_data_t;
 
-/*------------------------------------------------------------------
- * INTERNAL OBJECT & FUNCTION DECLARATION
- *------------------------------------------------------------------*/
 static dcd_data_t _dcd;
 
+//--------------------------------------------------------------------
+// HW FIFO Helper
+// Note: Index register is already set by caller
+//--------------------------------------------------------------------
 
-static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
-{
-  free_block_t *cur = beg;
-  for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ;
-  return cur;
-}
+#if MUSB_CFG_DYNAMIC_FIFO
 
-static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size)
-{
-  free_block_t *p = find_containing_block(blks, blks + num, addr);
-  TU_ASSERT(p != blks + num, -2);
-  if (p->beg == addr) {
-    /* Shrink block */
-    p->beg = addr + size;
-    if (p->beg != p->end) return 0;
-    /* remove block */
-    free_block_t *end = blks + num;
-    while (p + 1 < end) {
-      *p = *(p + 1);
-      ++p;
-    }
-    return -1;
-  } else {
-    /* Split into 2 blocks */
-    free_block_t tmp = {
-      .beg = addr + size,
-      .end = p->end
-    };
-    p->end = addr;
-    if (p->beg == p->end) {
-      if (tmp.beg != tmp.end) {
-        *p = tmp;
-        return 0;
-      }
-      /* remove block */
-      free_block_t *end = blks + num;
-      while (p + 1 < end) {
-        *p = *(p + 1);
-        ++p;
-      }
-      return -1;
-    }
-    if (tmp.beg == tmp.end) return 0;
-    blks[num] = tmp;
-    return 1;
+// musb is configured to use dynamic FIFO sizing.
+// FF Size is encodded: 1 << (fifo_size[3:0] + 3) = 8 << fifo_size[3:0]
+// FF Address is 8*ff_addr[12:0]
+// First 64 bytes are reserved for EP0
+static uint32_t alloced_fifo_bytes;
+
+// ffsize is log2(mps) - 3 (round up)
+TU_ATTR_ALWAYS_INLINE static inline uint8_t hwfifo_byte2size(uint16_t nbytes) {
+  uint8_t ffsize = 28 - tu_min8(28, __builtin_clz(nbytes));
+  if ((8u << ffsize) < nbytes) {
+    ++ffsize;
   }
+  return ffsize;
 }
 
-static inline unsigned free_block_size(free_block_t const *blk)
-{
-  return blk->end - blk->beg;
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned is_rx) {
+  (void) epnum;
+  musb->fifo_size[is_rx] = 0;
+  musb->fifo_addr[is_rx] = 0;
 }
 
-#if 0
-static inline void print_block_list(free_block_t const *blk, unsigned num)
-{
-  TU_LOG1("*************\n");
-  for (unsigned i = 0; i < num; ++i) {
-    TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end);
-    ++blk;
+TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned is_rx, unsigned mps,
+                                                       bool double_packet) {
+  (void) epnum;
+  uint8_t ffsize = hwfifo_byte2size(mps);
+  mps = 8 << ffsize; // round up to the next power of 2
+
+  if (double_packet) {
+    ffsize |= MUSB_FIFOSZ_DOUBLE_PACKET;
+    mps <<= 1;
   }
+
+  TU_ASSERT(alloced_fifo_bytes + mps <= MUSB_CFG_DYNAMIC_FIFO_SIZE);
+  musb->fifo_addr[is_rx] = alloced_fifo_bytes / 8;
+  musb->fifo_size[is_rx] = ffsize;
+
+  alloced_fifo_bytes += mps;
+  return true;
 }
+
 #else
-#define print_block_list(a,b)
+
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned is_rx) {
+  (void) musb; (void) epnum; (void) is_rx;
+  // nothing to do for static FIFO
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned is_rx, unsigned mps,
+                                                       bool double_packet) {
+  (void) epnum; (void) mps;
+  if (!double_packet) {
+    #if defined(TUP_USBIP_MUSB_ADI)
+    musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx);
+    #else
+    if (is_rx) {
+      musb->rx_doulbe_packet_disable |= 1u << epnum;
+    } else {
+      musb->tx_double_packet_disable |= 1u << epnum;
+    }
+    #endif
+  }
+
+  return true;
+}
+
 #endif
 
-static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
-{
-  free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)];
-  unsigned num_blocks = 1;
-
-  /* Initialize free memory block list */
-  free_blocks[0].beg = 64 / 8;
-  free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */
-  for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
-    uint_fast16_t addr;
-    int num;
-    USB0->EPIDX = i;
-    addr = USB0->TXFIFOADD;
-    if (addr) {
-      unsigned sz  = USB0->TXFIFOSZ;
-      unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0);
-      num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
-      TU_ASSERT(-2 < num, 0);
-      num_blocks += num;
-      print_block_list(free_blocks, num_blocks);
-    }
-    addr = USB0->RXFIFOADD;
-    if (addr) {
-      unsigned sz  = USB0->RXFIFOSZ;
-      unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0);
-      num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
-      TU_ASSERT(-2 < num, 0);
-      num_blocks += num;
-      print_block_list(free_blocks, num_blocks);
+// Flush FIFO and clear data toggle
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_flush(musb_regs_t* musb, unsigned epnum, unsigned is_rx, bool clear_dtog) {
+  (void) epnum;
+  const uint8_t csrl_dtog = clear_dtog ? MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx) : 0;
+  musb_ep_maxp_csr_t* maxp_csr = &musb->indexed_csr.maxp_csr[is_rx];
+  // may need to flush twice for double packet
+  for (unsigned i=0; i<2; i++) {
+    if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) {
+      maxp_csr->csrl = MUSB_CSRL_FLUSH_FIFO(is_rx) | csrl_dtog;
     }
   }
-  print_block_list(free_blocks, num_blocks);
-
-  /* Find the best fit memory block */
-  uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3;
-  free_block_t const *min = NULL;
-  uint_fast16_t    min_sz = 0xFFFFu;
-  free_block_t const *end = &free_blocks[num_blocks];
-  for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) {
-    uint_fast16_t sz = free_block_size(cur);
-    if (sz < size_in_8byte_unit) continue;
-    if (size_in_8byte_unit == sz) return cur->beg;
-    if (sz < min_sz) min = cur;
-  }
-  TU_ASSERT(min, 0);
-  return min->beg;
-}
-
-static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1)
-{
-  volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1);
-  return regs + epnum_minus1;
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -284,11 +232,14 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
   ops[dir].tu_fifo_advance(f, total_len - rem);
 }
 
-static void process_setup_packet(uint8_t rhport)
-{
+static void process_setup_packet(uint8_t rhport) {
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+
+  // Read setup packet
   uint32_t *p = (void*)&_dcd.setup_packet;
-  p[0]        = USB0->FIFO0_WORD;
-  p[1]        = USB0->FIFO0_WORD;
+  volatile uint32_t *fifo_ptr = &musb_regs->fifo[0];
+  p[0] = *fifo_ptr;
+  p[1] = *fifo_ptr;
 
   _dcd.pipe0.buf       = NULL;
   _dcd.pipe0.length    = 0;
@@ -299,12 +250,16 @@ static void process_setup_packet(uint8_t rhport)
   _dcd.remaining_ctrl   = len;
   const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType);
   /* Clear RX FIFO and reverse the transaction direction */
-  if (len && dir_in) USB0->CSRL0 = USB_CSRL0_RXRDYC;
+  if (len && dir_in) {
+    musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0);
+    ep_csr->csr0l = MUSB_CSRL0_RXRDYC;
+  }
 }
 
-static bool handle_xfer_in(uint_fast8_t ep_addr)
+static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr)
 {
-  unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+  unsigned epnum = tu_edpt_number(ep_addr);
+  unsigned epnum_minus1 = epnum - 1;
   pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
   const unsigned rem  = pipe->remaining;
 
@@ -313,44 +268,49 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
     return true;
   }
 
-  volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
-  const unsigned mps = regs->TXMAXP;
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum);
+  const unsigned mps = ep_csr->tx_maxp;
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
-  // TU_LOG1("   %p mps %d len %d rem %d\n", buf, mps, len, rem);
+  volatile void *fifo_ptr = &musb_regs->fifo[epnum];
+  // TU_LOG1("   %p mps %d len %d rem %d\r\n", buf, mps, len, rem);
   if (len) {
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
-      pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
+      pipe_write_packet(buf, fifo_ptr, len);
       pipe->buf       = buf + len;
     }
     pipe->remaining = rem - len;
   }
-  regs->TXCSRL = USB_TXCSRL1_TXRDY;
-  // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
+  ep_csr->tx_csrl = MUSB_TXCSRL1_TXRDY;
+  // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum, ep_csr->tx_csrl, rem - len);
   return false;
 }
 
-static bool handle_xfer_out(uint_fast8_t ep_addr)
+static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr)
 {
-  unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+  unsigned epnum = tu_edpt_number(ep_addr);
+  unsigned epnum_minus1 = epnum - 1;
   pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
-  volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
-  // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL);
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum);
+  // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, ep_csr->rx_csrl);
 
-  TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY);
+  TU_ASSERT(ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY);
 
-  const unsigned mps = regs->RXMAXP;
+  const unsigned mps = ep_csr->rx_maxp;
   const unsigned rem = pipe->remaining;
-  const unsigned vld = regs->RXCOUNT;
+  const unsigned vld = ep_csr->rx_count;
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
+  volatile void *fifo_ptr = &musb_regs->fifo[epnum];
   if (len) {
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) {
-      pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
+      pipe_read_packet(buf, fifo_ptr, len);
       pipe->buf       = buf + len;
     }
     pipe->remaining = rem - len;
@@ -359,15 +319,14 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
     pipe->buf = NULL;
     return NULL != buf;
   }
-  regs->RXCSRL = 0; /* Clear RXRDY bit */
+  ep_csr->rx_csrl = 0; /* Clear RXRDY bit */
   return false;
 }
 
 static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
-  (void)rhport;
-
-  unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+  unsigned epnum = tu_edpt_number(ep_addr);
+  unsigned epnum_minus1 = epnum - 1;
   unsigned dir_in       = tu_edpt_dir(ep_addr);
 
   pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1];
@@ -376,10 +335,11 @@ static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16
   pipe->remaining    = total_bytes;
 
   if (dir_in) {
-    handle_xfer_in(ep_addr);
+    handle_xfer_in(rhport, ep_addr);
   } else {
-    volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
-    if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0;
+    musb_regs_t* musb_regs = MUSB_REGS(rhport);
+    musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum);
+    if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) ep_csr->rx_csrl = 0;
   }
   return true;
 }
@@ -388,7 +348,8 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
 {
   (void)rhport;
   TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */
-
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0);
   const unsigned req = _dcd.setup_packet.bmRequestType;
   TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0);
 
@@ -399,14 +360,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
      * may have already finished and received the next setup packet
      * without calling this function, so we have no choice but to
      * invoke the callback function of status packet here. */
-    // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
+    // TU_LOG1(" STATUS OUT ep_csr->csr0l = %x\r\n", ep_csr->csr0l);
     _dcd.status_out = 0;
     if (req == REQUEST_TYPE_INVALID) {
       dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
     } else {
       /* The next setup packet has already been received, it aborts
        * invoking callback function to avoid confusing TUSB stack. */
-      TU_LOG1("Drop CONTROL_STAGE_ACK\n");
+      TU_LOG1("Drop CONTROL_STAGE_ACK\r\n");
     }
     return true;
   }
@@ -415,8 +376,9 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
     TU_ASSERT(total_bytes <= _dcd.remaining_ctrl);
     const unsigned rem = _dcd.remaining_ctrl;
     const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes);
+    volatile void *fifo_ptr = &musb_regs->fifo[0];
     if (dir_in) {
-      pipe_write_packet(buffer, &USB0->FIFO0_WORD, len);
+      pipe_write_packet(buffer, fifo_ptr, len);
 
       _dcd.pipe0.buf       = buffer + len;
       _dcd.pipe0.length    = len;
@@ -427,45 +389,48 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
         _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */
         _dcd.status_out = 1;
         /* Flush TX FIFO and reverse the transaction direction. */
-        USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
+        ep_csr->csr0l = MUSB_CSRL0_TXRDY | MUSB_CSRL0_DATAEND;
       } else {
-        USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
+        ep_csr->csr0l = MUSB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
       }
-      // TU_LOG1(" IN USB0->CSRL0 = %x\n", USB0->CSRL0);
+      // TU_LOG1(" IN ep_csr->csr0l = %x\r\n", ep_csr->csr0l);
     } else {
-      // TU_LOG1(" OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
+      // TU_LOG1(" OUT ep_csr->csr0l = %x\r\n", ep_csr->csr0l);
       _dcd.pipe0.buf       = buffer;
       _dcd.pipe0.length    = len;
       _dcd.pipe0.remaining = len;
-      USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
+      ep_csr->csr0l = MUSB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
     }
   } else if (dir_in) {
-    // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\n", USB0->CSRL0);
+    // TU_LOG1(" STATUS IN ep_csr->csr0l  = %x\r\n", ep_csr->csr0l);
     _dcd.pipe0.buf = NULL;
     _dcd.pipe0.length    = 0;
     _dcd.pipe0.remaining = 0;
     /* Clear RX FIFO and reverse the transaction direction */
-    USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
+    ep_csr->csr0l = MUSB_CSRL0_RXRDYC | MUSB_CSRL0_DATAEND;
   }
   return true;
 }
 
 static void process_ep0(uint8_t rhport)
 {
-  uint_fast8_t csrl = USB0->CSRL0;
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0);
+  uint_fast8_t csrl = ep_csr->csr0l;
 
-  // TU_LOG1(" EP0 USB0->CSRL0 = %x\n", csrl);
+  // TU_LOG1(" EP0 ep_csr->csr0l = %x\r\n", csrl);
+  // 21.1.5: endpoint 0 service routine as peripheral
 
-  if (csrl & USB_CSRL0_STALLED) {
+  if (csrl & MUSB_CSRL0_STALLED) {
     /* Returned STALL packet to HOST. */
-    USB0->CSRL0 = 0; /* Clear STALL */
+    ep_csr->csr0l = 0; /* Clear STALL */
     return;
   }
 
   unsigned req = _dcd.setup_packet.bmRequestType;
-  if (csrl & USB_CSRL0_SETEND) {
-    TU_LOG1("   ABORT by the next packets\n");
-    USB0->CSRL0 = USB_CSRL0_SETENDC;
+  if (csrl & MUSB_CSRL0_SETEND) {
+    TU_LOG1("   ABORT by the next packets\r\n");
+    ep_csr->csr0l = MUSB_CSRL0_SETENDC;
     if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
       /* DATA stage was aborted by receiving STATUS or SETUP packet. */
       _dcd.pipe0.buf = NULL;
@@ -476,23 +441,24 @@ static void process_ep0(uint8_t rhport)
                               XFER_RESULT_SUCCESS, true);
     }
     req = REQUEST_TYPE_INVALID;
-    if (!(csrl & USB_CSRL0_RXRDY)) return; /* Received SETUP packet */
+    if (!(csrl & MUSB_CSRL0_RXRDY)) return; /* Received SETUP packet */
   }
 
-  if (csrl & USB_CSRL0_RXRDY) {
+  if (csrl & MUSB_CSRL0_RXRDY) {
     /* Received SETUP or DATA OUT packet */
     if (req == REQUEST_TYPE_INVALID) {
       /* SETUP */
-      TU_ASSERT(sizeof(tusb_control_request_t) == USB0->COUNT0,);
+      TU_ASSERT(sizeof(tusb_control_request_t) == ep_csr->count0,);
       process_setup_packet(rhport);
       return;
     }
     if (_dcd.pipe0.buf) {
       /* DATA OUT */
-      const unsigned vld = USB0->COUNT0;
+      const unsigned vld = ep_csr->count0;
       const unsigned rem = _dcd.pipe0.remaining;
       const unsigned len = TU_MIN(TU_MIN(rem, 64), vld);
-      pipe_read_packet(_dcd.pipe0.buf, &USB0->FIFO0_WORD, len);
+      volatile void *fifo_ptr = &musb_regs->fifo[0];
+      pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len);
 
       _dcd.pipe0.remaining = rem - len;
       _dcd.remaining_ctrl -= len;
@@ -512,7 +478,7 @@ static void process_ep0(uint8_t rhport)
     /* STATUS IN */
     if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) {
       /* The address must be changed on completion of the control transfer. */
-      USB0->FADDR = (uint8_t)_dcd.setup_packet.wValue;
+      musb_regs->faddr = (uint8_t)_dcd.setup_packet.wValue;
     }
     _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
     dcd_event_xfer_complete(rhport,
@@ -534,118 +500,149 @@ static void process_ep0(uint8_t rhport)
 static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
 {
   bool completed;
-  const unsigned dir_in     = tu_edpt_dir(ep_addr);
-  const unsigned epn_minus1 = tu_edpt_number(ep_addr) - 1;
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  const unsigned epn = tu_edpt_number(ep_addr);
+  const unsigned epn_minus1 = epn - 1;
 
-  volatile hw_endpoint_t *regs = edpt_regs(epn_minus1);
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn);
   if (dir_in) {
-    // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL);
-    if (regs->TXCSRL & USB_TXCSRL1_STALLED) {
-      regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN);
+    // TU_LOG1(" TX CSRL%d = %x\r\n", epn, ep_csr->tx_csrl);
+    if (ep_csr->tx_csrl & MUSB_TXCSRL1_STALLED) {
+      ep_csr->tx_csrl &= ~(MUSB_TXCSRL1_STALLED | MUSB_TXCSRL1_UNDRN);
       return;
     }
-    completed = handle_xfer_in(ep_addr);
+    completed = handle_xfer_in(rhport, ep_addr);
   } else {
-    // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL);
-    if (regs->RXCSRL & USB_RXCSRL1_STALLED) {
-      regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER);
+    // TU_LOG1(" RX CSRL%d = %x\r\n", epn, ep_csr->rx_csrl);
+    if (ep_csr->rx_csrl & MUSB_RXCSRL1_STALLED) {
+      ep_csr->rx_csrl &= ~(MUSB_RXCSRL1_STALLED | MUSB_RXCSRL1_OVER);
       return;
     }
-    completed = handle_xfer_out(ep_addr);
+    completed = handle_xfer_out(rhport, ep_addr);
   }
 
   if (completed) {
-    pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1];
+    pipe_state_t *pipe = &_dcd.pipe[dir_in][epn_minus1];
     dcd_event_xfer_complete(rhport, ep_addr,
                             pipe->length - pipe->remaining,
                             XFER_RESULT_SUCCESS, true);
   }
 }
 
-static void process_bus_reset(uint8_t rhport)
-{
-  /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF),
-   * a control transfer state is SETUP or STATUS stage. */
+// Upon BUS RESET is detected, hardware havs already done:
+// faddr = 0, index = 0, flushes all ep fifos, clears all ep csr, enabled all ep interrupts
+static void process_bus_reset(uint8_t rhport) {
+  musb_regs_t* musb = MUSB_REGS(rhport);
+
+#if MUSB_CFG_DYNAMIC_FIFO
+  alloced_fifo_bytes = CFG_TUD_ENDPOINT0_SIZE;
+#endif
+
+  /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), a control transfer state is SETUP or STATUS stage. */
   _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
   _dcd.status_out = 0;
   /* When pipe0.buf has not NULL, DATA stage works in progress. */
   _dcd.pipe0.buf = NULL;
 
-  USB0->TXIE = 1; /* Enable only EP0 */
-  USB0->RXIE = 0; 
+  musb->intr_txen = 1; /* Enable only EP0 */
+  musb->intr_rxen = 0;
 
   /* Clear FIFO settings */
   for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
-    USB0->EPIDX     = i;
-    USB0->TXFIFOSZ  = 0;
-    USB0->TXFIFOADD = 0;
-    USB0->RXFIFOSZ  = 0;
-    USB0->RXFIFOADD = 0;
+    musb->index = i;
+    hwfifo_reset(musb, i, 0);
+    hwfifo_reset(musb, i, 1);
   }
-  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+  dcd_event_bus_reset(rhport, (musb->power & MUSB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true);
 }
 
 /*------------------------------------------------------------------
  * Device API
  *------------------------------------------------------------------*/
 
-void dcd_init(uint8_t rhport)
-{
-  (void)rhport;
-  USB0->IE |= USB_IE_SUSPND;
-  NVIC_ClearPendingIRQ(USB0_IRQn);
+#if CFG_TUSB_DEBUG >= MUSB_DEBUG
+void print_musb_info(musb_regs_t* musb_regs) {
+  // print version, epinfo, raminfo, config_data0, fifo_size
+  TU_LOG1("musb version = %u.%u\r\n", musb_regs->hwvers_bit.major, musb_regs->hwvers_bit.minor);
+  TU_LOG1("Number of endpoints: %u TX, %u RX\r\n", musb_regs->epinfo_bit.tx_ep_num, musb_regs->epinfo_bit.rx_ep_num);
+  TU_LOG1("RAM Info: %u DMA Channel, %u RAM address width\r\n", musb_regs->raminfo_bit.dma_channel, musb_regs->raminfo_bit.ram_bits);
 
+  musb_regs->index = 0;
+  TU_LOG1("config_data0 = 0x%x\r\n", musb_regs->indexed_csr.config_data0);
+
+#if MUSB_CFG_DYNAMIC_FIFO
+  TU_LOG1("Dynamic FIFO configuration\r\n");
+#else
+  for (uint8_t i=1; i <= musb_regs->epinfo_bit.tx_ep_num; i++) {
+    musb_regs->index = i;
+    TU_LOG1("FIFO %u Size: TX %u RX %u\r\n", i, musb_regs->indexed_csr.fifo_size_bit.tx, musb_regs->indexed_csr.fifo_size_bit.rx);
+  }
+#endif
+}
+#endif
+
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+
+#if CFG_TUSB_DEBUG >= MUSB_DEBUG
+  print_musb_info(musb_regs);
+#endif
+
+  musb_regs->intr_usben |= MUSB_IE_SUSPND;
+  musb_dcd_int_clear(rhport);
+  musb_dcd_phy_init(rhport);
   dcd_connect(rhport);
+  return true;
 }
 
-void dcd_int_enable(uint8_t rhport)
-{
-  (void)rhport;
-  NVIC_EnableIRQ(USB0_IRQn);
+void dcd_int_enable(uint8_t rhport) {
+  musb_dcd_int_enable(rhport);
 }
 
-void dcd_int_disable(uint8_t rhport)
-{
-  (void)rhport;
-  NVIC_DisableIRQ(USB0_IRQn);
+void dcd_int_disable(uint8_t rhport) {
+  musb_dcd_int_disable(rhport);
 }
 
 // Receive Set Address request, mcu port must also include status IN response
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
-  (void)rhport;
   (void)dev_addr;
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0);
+
   _dcd.pipe0.buf       = NULL;
   _dcd.pipe0.length    = 0;
   _dcd.pipe0.remaining = 0;
   /* Clear RX FIFO to return ACK. */
-  USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
+  ep_csr->csr0l = MUSB_CSRL0_RXRDYC | MUSB_CSRL0_DATAEND;
 }
 
 // Wake up host
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void)rhport;
-  USB0->POWER |= USB_POWER_RESUME;
+void dcd_remote_wakeup(uint8_t rhport) {
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_regs->power |= MUSB_POWER_RESUME;
 
   unsigned cnt = SystemCoreClock / 1000;
   while (cnt--) __NOP();
 
-  USB0->POWER &= ~USB_POWER_RESUME;
+  musb_regs->power &= ~MUSB_POWER_RESUME;
 }
 
 // Connect by enabling internal pull-up resistor on D+/D-
 void dcd_connect(uint8_t rhport)
 {
-  (void)rhport;
-  USB0->POWER |= USB_POWER_SOFTCONN;
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_regs->power |= TUD_OPT_HIGH_SPEED ? MUSB_POWER_HSENAB : 0;
+  musb_regs->power |= MUSB_POWER_SOFTCONN;
 }
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
 void dcd_disconnect(uint8_t rhport)
 {
-  (void)rhport;
-  USB0->POWER &= ~USB_POWER_SOFTCONN;
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_regs->power &= ~MUSB_POWER_SOFTCONN;
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -659,129 +656,119 @@ void dcd_sof_enable(uint8_t rhport, bool en)
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
+// static void edpt_setup(musb_regs_t* musb, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_size){
+//   const unsigned epn     = tu_edpt_number(ep_addr);
+//   const unsigned dir_in  = tu_edpt_dir(ep_addr);
+// }
 
 // Configure endpoint's registers according to descriptor
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
-{
-  (void) rhport;
-
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) {
   const unsigned ep_addr = ep_desc->bEndpointAddress;
   const unsigned epn     = tu_edpt_number(ep_addr);
   const unsigned dir_in  = tu_edpt_dir(ep_addr);
-  const unsigned xfer    = ep_desc->bmAttributes.xfer;
   const unsigned mps     = tu_edpt_packet_size(ep_desc);
 
-  TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX);
-
   pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
   pipe->buf       = NULL;
   pipe->length    = 0;
   pipe->remaining = 0;
 
-  volatile hw_endpoint_t *regs = edpt_regs(epn - 1);
-  if (dir_in) {
-    regs->TXMAXP = mps;
-    regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0;
-    if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
-      regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
-    else
-      regs->TXCSRL = USB_TXCSRL1_CLRDT;
-    USB0->TXIE |= TU_BIT(epn);
-  } else {
-    regs->RXMAXP = mps;
-    regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0;
-    if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
-      regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
-    else
-      regs->RXCSRL = USB_RXCSRL1_CLRDT;
-    USB0->RXIE |= TU_BIT(epn);
-  }
+  musb_regs_t* musb = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn);
+  const uint8_t is_rx = 1 - dir_in;
+  musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx];
 
-  /* Setup FIFO */
-  int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps));
-  if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3;
-  unsigned addr = find_free_memory(size_in_log2_minus3);
-  TU_ASSERT(addr);
-
-  USB0->EPIDX = epn;
+  maxp_csr->maxp = mps;
+  maxp_csr->csrh = 0;
+#if MUSB_CFG_SHARED_FIFO
   if (dir_in) {
-    USB0->TXFIFOADD = addr;
-    USB0->TXFIFOSZ  = size_in_log2_minus3;
-  } else {
-    USB0->RXFIFOADD = addr;
-    USB0->RXFIFOSZ  = size_in_log2_minus3;
+    maxp_csr->csrh |= MUSB_CSRH_TX_MODE;
   }
+#endif
+
+  hwfifo_flush(musb, epn, is_rx, true);
+
+  TU_ASSERT(hwfifo_config(musb, epn, is_rx, mps, false));
+  musb->intren_ep[is_rx] |= TU_BIT(epn);
+
+  return true;
+}
+
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
+  const unsigned epn    = tu_edpt_number(ep_addr);
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  musb_regs_t* musb = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn);
+  const uint8_t is_rx = 1 - dir_in;
+  ep_csr->maxp_csr[is_rx].csrh = 0;
+  return hwfifo_config(musb, epn, is_rx, largest_packet_size, true);
+}
+
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc ) {
+  const unsigned ep_addr = ep_desc->bEndpointAddress;
+  const unsigned epn     = tu_edpt_number(ep_addr);
+  const unsigned dir_in  = tu_edpt_dir(ep_addr);
+  const unsigned mps     = tu_edpt_packet_size(ep_desc);
+
+  unsigned const ie = musb_dcd_get_int_enable(rhport);
+  musb_dcd_int_disable(rhport);
+
+  pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
+  pipe->buf       = NULL;
+  pipe->length    = 0;
+  pipe->remaining = 0;
+
+  musb_regs_t* musb = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn);
+  const uint8_t is_rx = 1 - dir_in;
+  musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx];
+
+  maxp_csr->maxp = mps;
+  maxp_csr->csrh |= MUSB_CSRH_ISO;
+#if MUSB_CFG_SHARED_FIFO
+  if (dir_in) {
+    maxp_csr->csrh |= MUSB_CSRH_TX_MODE;
+  }
+#endif
+
+  hwfifo_flush(musb, epn, is_rx, true);
+
+#if MUSB_CFG_DYNAMIC_FIFO
+  // fifo space is already allocated, keep the address and just change packet size
+  musb->fifo_size[is_rx] = hwfifo_byte2size(mps) | MUSB_FIFOSZ_DOUBLE_PACKET;
+#endif
+
+  musb->intren_ep[is_rx] |= TU_BIT(epn);
+
+  if (ie) musb_dcd_int_enable(rhport);
 
   return true;
 }
 
 void dcd_edpt_close_all(uint8_t rhport)
 {
-  (void) rhport;
-  volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1;
-  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
-  NVIC_DisableIRQ(USB0_IRQn);
-  USB0->TXIE = 1; /* Enable only EP0 */
-  USB0->RXIE = 0; 
+  musb_regs_t* musb = MUSB_REGS(rhport);
+  unsigned const ie = musb_dcd_get_int_enable(rhport);
+  musb_dcd_int_disable(rhport);
+
+  musb->intr_txen = 1; /* Enable only EP0 */
+  musb->intr_rxen = 0;
   for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
-    regs->TXMAXP = 0;
-    regs->TXCSRH = 0;
-    if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
-      regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
-    else
-      regs->TXCSRL = USB_TXCSRL1_CLRDT;
-
-    regs->RXMAXP = 0;
-    regs->RXCSRH = 0;
-    if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
-      regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
-    else
-      regs->RXCSRL = USB_RXCSRL1_CLRDT;
-
-    USB0->EPIDX     = i;
-    USB0->TXFIFOSZ  = 0;
-    USB0->TXFIFOADD = 0;
-    USB0->RXFIFOSZ  = 0;
-    USB0->RXFIFOADD = 0;
+    musb_ep_csr_t* ep_csr = get_ep_csr(musb, i);
+    for (unsigned d = 0; d < 2; d++) {
+      musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[d];
+      hwfifo_flush(musb, i, d, true);
+      hwfifo_reset(musb, i, d);
+      maxp_csr->maxp = 0;
+      maxp_csr->csrh = 0;
+    }
   }
-  if (ie) NVIC_EnableIRQ(USB0_IRQn);
-}
 
-void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
-{
-  (void)rhport;
-  unsigned const epn    = tu_edpt_number(ep_addr);
-  unsigned const dir_in = tu_edpt_dir(ep_addr);
+#if MUSB_CFG_DYNAMIC_FIFO
+  alloced_fifo_bytes = CFG_TUD_ENDPOINT0_SIZE;
+#endif
 
-  hw_endpoint_t volatile *regs = edpt_regs(epn - 1);
-  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
-  NVIC_DisableIRQ(USB0_IRQn);
-  if (dir_in) {
-    USB0->TXIE  &= ~TU_BIT(epn);
-    regs->TXMAXP = 0;
-    regs->TXCSRH = 0;
-    if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
-      regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
-    else
-      regs->TXCSRL = USB_TXCSRL1_CLRDT;
-
-    USB0->EPIDX     = epn;
-    USB0->TXFIFOSZ  = 0;
-    USB0->TXFIFOADD = 0;
-  } else {
-    USB0->RXIE  &= ~TU_BIT(epn);
-    regs->RXMAXP = 0;
-    regs->RXCSRH = 0;
-    if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
-      regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
-    else
-      regs->RXCSRL = USB_RXCSRL1_CLRDT;
-
-    USB0->EPIDX     = epn;
-    USB0->RXFIFOSZ  = 0;
-    USB0->RXFIFOADD = 0;
-  }
-  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  if (ie) musb_dcd_int_enable(rhport);
 }
 
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
@@ -789,120 +776,129 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
-  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
-  NVIC_DisableIRQ(USB0_IRQn);
+  unsigned const ie = musb_dcd_get_int_enable(rhport);
+  musb_dcd_int_disable(rhport);
+
   if (epnum) {
     _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1);
     ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes);
-  } else
+  } else {
     ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
-  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  }
+
+  if (ie) musb_dcd_int_enable(rhport);
   return ret;
 }
 
-// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
+// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack
+// - optional, however, must be listed in usbd.c
 bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   TU_ASSERT(epnum);
-  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
-  NVIC_DisableIRQ(USB0_IRQn);
+  unsigned const ie = musb_dcd_get_int_enable(rhport);
+  musb_dcd_int_disable(rhport);
   _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1);
   ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes);
-  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  if (ie) musb_dcd_int_enable(rhport);
   return ret;
 }
 
 // Stall endpoint
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  (void)rhport;
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+  unsigned const ie = musb_dcd_get_int_enable(rhport);
+  musb_dcd_int_disable(rhport);
+
   unsigned const epn = tu_edpt_number(ep_addr);
-  unsigned const ie  = NVIC_GetEnableIRQ(USB0_IRQn);
-  NVIC_DisableIRQ(USB0_IRQn);
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn);
+
   if (0 == epn) {
     if (!ep_addr) { /* Ignore EP80 */
       _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
       _dcd.pipe0.buf = NULL;
-      USB0->CSRL0 = USB_CSRL0_STALL;
+      ep_csr->csr0l = MUSB_CSRL0_STALL;
     }
   } else {
-    volatile hw_endpoint_t *regs = edpt_regs(epn - 1);
-    if (tu_edpt_dir(ep_addr)) { /* IN */
-      regs->TXCSRL = USB_TXCSRL1_STALL;
-    } else { /* OUT */
-      TU_ASSERT(!(regs->RXCSRL & USB_RXCSRL1_RXRDY),);
-      regs->RXCSRL = USB_RXCSRL1_STALL;
-    }
+    const uint8_t is_rx = 1 - tu_edpt_dir(ep_addr);
+    ep_csr->maxp_csr[is_rx].csrl = MUSB_CSRL_SEND_STALL(is_rx);
   }
-  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+
+  if (ie) musb_dcd_int_enable(rhport);
 }
 
 // clear stall, data toggle is also reset to DATA0
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
+  unsigned const ie = musb_dcd_get_int_enable(rhport);
+  musb_dcd_int_disable(rhport);
+
   unsigned const epn = tu_edpt_number(ep_addr);
-  hw_endpoint_t volatile *regs = edpt_regs(epn - 1);
-  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
-  NVIC_DisableIRQ(USB0_IRQn);
-  if (tu_edpt_dir(ep_addr)) { /* IN */
-    regs->TXCSRL = USB_TXCSRL1_CLRDT;
-  } else { /* OUT */
-    regs->RXCSRL = USB_RXCSRL1_CLRDT; 
-  }
-  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn);
+  const uint8_t is_rx = 1 - tu_edpt_dir(ep_addr);
+
+  ep_csr->maxp_csr[is_rx].csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx);
+
+  if (ie) musb_dcd_int_enable(rhport);
 }
 
 /*-------------------------------------------------------------------
  * ISR
  *-------------------------------------------------------------------*/
-void dcd_int_handler(uint8_t rhport)
-{
-  uint_fast8_t is, txis, rxis;
+void dcd_int_handler(uint8_t rhport) {
+  musb_regs_t* musb_regs = MUSB_REGS(rhport);
+  const uint8_t saved_index = musb_regs->index; // save endpoint index
 
-  is   = USB0->IS;   /* read and clear interrupt status */
-  txis = USB0->TXIS; /* read and clear interrupt status */
-  rxis = USB0->RXIS; /* read and clear interrupt status */
-  // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
+  //Part specific ISR setup/entry
+  musb_dcd_int_handler_enter(rhport);
 
-  is &= USB0->IE; /* Clear disabled interrupts */
-  if (is & USB_IS_DISCON) {
+  uint_fast8_t intr_usb = musb_regs->intr_usb; // a read will clear this interrupt status
+  uint_fast8_t intr_tx = musb_regs->intr_tx; // a read will clear this interrupt status
+  uint_fast8_t intr_rx = musb_regs->intr_rx; // a read will clear this interrupt status
+  // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis);
+
+  intr_usb &= musb_regs->intr_usben; /* Clear disabled interrupts */
+  if (intr_usb & MUSB_IS_DISCON) {
   }
-  if (is & USB_IS_SOF) {
+  if (intr_usb & MUSB_IS_SOF) {
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
-  if (is & USB_IS_RESET) {
+  if (intr_usb & MUSB_IS_RESET) {
     process_bus_reset(rhport);
   }
-  if (is & USB_IS_RESUME) {
+  if (intr_usb & MUSB_IS_RESUME) {
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
   }
-  if (is & USB_IS_SUSPEND) {
+  if (intr_usb & MUSB_IS_SUSPEND) {
     dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
   }
 
-  txis &= USB0->TXIE; /* Clear disabled interrupts */
-  if (txis & USB_TXIE_EP0) {
+  intr_tx &= musb_regs->intr_txen; /* Clear disabled interrupts */
+  if (intr_tx & TU_BIT(0)) {
     process_ep0(rhport);
-    txis &= ~TU_BIT(0);
+    intr_tx &= ~TU_BIT(0);
   }
-  while (txis) {
-    unsigned const num = __builtin_ctz(txis);
+  while (intr_tx) {
+    unsigned const num = __builtin_ctz(intr_tx);
     process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN));
-    txis &= ~TU_BIT(num);
+    intr_tx &= ~TU_BIT(num);
   }
-  rxis &= USB0->RXIE; /* Clear disabled interrupts */
-  while (rxis) {
-    unsigned const num = __builtin_ctz(rxis);
+
+  intr_rx &= musb_regs->intr_rxen; /* Clear disabled interrupts */
+  while (intr_rx) {
+    unsigned const num = __builtin_ctz(intr_rx);
     process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT));
-    rxis &= ~TU_BIT(num);
+    intr_rx &= ~TU_BIT(num);
   }
+
+  musb_regs->index = saved_index; // restore endpoint index
 }
 
 #endif
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 85e18e3aa..1c0740193 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji KITAYAMA
@@ -37,16 +37,10 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
 
 #include "host/hcd.h"
 
-#if TU_CHECK_MCU(OPT_MCU_MSP432E4)
-  #include "musb_msp432e.h"
-
-#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129)
-  #include "musb_tm4c.h"
-
-  // HACK generalize later
-  #include "musb_type.h"
-  #define FIFO0_WORD FIFO0
+#include "musb_type.h"
 
+#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+  #include "musb_ti.h"
 #else
   #error "Unsupported MCUs"
 #endif
@@ -418,7 +412,7 @@ static void process_ep0(uint8_t rhport)
   (void)rhport;
 
   uint_fast8_t csrl = USB0->CSRL0;
-  // TU_LOG1(" EP0 CSRL = %x\n", csrl);
+  // TU_LOG1(" EP0 CSRL = %x\r\n", csrl);
 
   unsigned const dev_addr = USB0->TXFUNCADDR0;
   unsigned const req = _hcd.bmRequestType;
@@ -508,7 +502,7 @@ static void process_pipe_tx(uint8_t rhport, uint_fast8_t pipenum)
 
   volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
   unsigned const csrl = regs->TXCSRL;
-  // TU_LOG1(" TXCSRL%d = %x\n", pipenum, csrl);
+  // TU_LOG1(" TXCSRL%d = %x\r\n", pipenum, csrl);
   if (csrl & (USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) {
     if (csrl & USB_TXCSRL1_TXRDY)
       regs->TXCSRL = (csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) | USB_TXCSRL1_FLUSH;
@@ -537,7 +531,7 @@ static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum)
 
   volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
   unsigned const csrl = regs->RXCSRL;
-  // TU_LOG1(" RXCSRL%d = %x\n", pipenum, csrl);
+  // TU_LOG1(" RXCSRL%d = %x\r\n", pipenum, csrl);
   if (csrl & (USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) {
     if (csrl & USB_RXCSRL1_RXRDY)
       regs->RXCSRL = (csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) | USB_RXCSRL1_FLUSH;
@@ -562,9 +556,9 @@ static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum)
  * Host API
  *------------------------------------------------------------------*/
 
-bool hcd_init(uint8_t rhport)
-{
-  (void)rhport;
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rhport;
+  (void) rh_init;
 
   NVIC_ClearPendingIRQ(USB0_IRQn);
   _hcd.bmRequestType = REQUEST_TYPE_INVALID;
@@ -588,7 +582,7 @@ void hcd_int_disable(uint8_t rhport)
 uint32_t hcd_frame_number(uint8_t rhport)
 {
   (void)rhport;
-  /* The device must be reset at least once after connection 
+  /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
   return USB0->FRAME;
@@ -822,9 +816,17 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
   return ret;
 }
 
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
 // clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   unsigned const pipenum = find_pipe(dev_addr, ep_addr);
   if (!pipenum) return false;
   hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
@@ -839,14 +841,16 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 /*-------------------------------------------------------------------
  * ISR
  *-------------------------------------------------------------------*/
-void hcd_int_handler(uint8_t rhport)
+void hcd_int_handler(uint8_t rhport, bool in_isr)
 {
+  (void) in_isr;
+
   uint_fast8_t is, txis, rxis;
 
   is   = USB0->IS;   /* read and clear interrupt status */
   txis = USB0->TXIS; /* read and clear interrupt status */
   rxis = USB0->RXIS; /* read and clear interrupt status */
-  // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
+  // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis);
 
   is &= USB0->IE; /* Clear disabled interrupts */
   if (is & USB_IS_RESUME) {
diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h
new file mode 100644
index 000000000..35849b5f8
--- /dev/null
+++ b/src/portable/mentor/musb/musb_max32.h
@@ -0,0 +1,150 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_MUSB_MAX32_H_
+#define TUSB_MUSB_MAX32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mxc_device.h"
+#include "usbhs_regs.h"
+
+#define MUSB_CFG_SHARED_FIFO   1 // shared FIFO for TX and RX endpoints
+#define MUSB_CFG_DYNAMIC_FIFO  0 // dynamic EP FIFO sizing
+
+const uintptr_t MUSB_BASES[] = { MXC_BASE_USBHS };
+
+#if CFG_TUD_ENABLED
+#define USBHS_M31_CLOCK_RECOVERY
+
+// Mapping of IRQ numbers to port. Currently just 1.
+static const IRQn_Type musb_irqs[] = {
+    USB_IRQn
+};
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_enable(uint8_t rhport) {
+  NVIC_EnableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_disable(uint8_t rhport) {
+  NVIC_DisableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) {
+  #ifdef NVIC_GetEnableIRQ // only defined in CMSIS 5
+  return NVIC_GetEnableIRQ(musb_irqs[rhport]);
+  #else
+  uint32_t IRQn = (uint32_t) musb_irqs[rhport];
+  return ((NVIC->ISER[IRQn >> 5UL] & (1UL << (IRQn & 0x1FUL))) != 0UL) ? 1UL : 0UL;
+  #endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_clear(uint8_t rhport) {
+  NVIC_ClearPendingIRQ(musb_irqs[rhport]);
+}
+
+static inline void musb_dcd_int_handler_enter(uint8_t rhport) {
+  mxc_usbhs_regs_t* hs_phy = MXC_USBHS;
+  uint32_t mxm_int, mxm_int_en, mxm_is;
+
+  //Handle PHY specific events
+  mxm_int = hs_phy->mxm_int;
+  mxm_int_en = hs_phy->mxm_int_en;
+  mxm_is = mxm_int & mxm_int_en;
+  hs_phy->mxm_int = mxm_is;
+
+  if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+  }
+}
+
+static inline void musb_dcd_phy_init(uint8_t rhport) {
+  (void) rhport;
+  mxc_usbhs_regs_t* hs_phy = MXC_USBHS;
+
+  // Interrupt for VBUS disconnect
+  hs_phy->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS;
+
+  musb_dcd_int_clear(rhport);
+
+  // Unsuspend the MAC
+  hs_phy->mxm_suspend = 0;
+
+  // Configure PHY
+  hs_phy->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11);
+  hs_phy->m31_phy_xcfgi_63_32 = 0;
+  hs_phy->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64);
+  hs_phy->m31_phy_xcfgi_127_96 = 0;
+
+  #ifdef USBHS_M31_CLOCK_RECOVERY
+  hs_phy->m31_phy_noncry_rstb = 1;
+  hs_phy->m31_phy_noncry_en = 1;
+  hs_phy->m31_phy_outclksel = 0;
+  hs_phy->m31_phy_coreclkin = 0;
+  hs_phy->m31_phy_xtlsel = 2; /* Select 25 MHz clock */
+  #else
+  hs_phy->m31_phy_noncry_rstb = 0;
+  hs_phy->m31_phy_noncry_en = 0;
+  hs_phy->m31_phy_outclksel = 1;
+  hs_phy->m31_phy_coreclkin = 1;
+  hs_phy->m31_phy_xtlsel = 3; /* Select 30 MHz clock */
+  #endif
+  hs_phy->m31_phy_pll_en = 1;
+  hs_phy->m31_phy_oscouten = 1;
+
+  /* Reset PHY */
+  hs_phy->m31_phy_ponrst = 0;
+  hs_phy->m31_phy_ponrst = 1;
+}
+
+// static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) {
+//   (void) mps;
+//
+//   //Most likely the caller has already grabbed the right register block. But
+//   //as a precaution save and restore the register bank anyways
+//   unsigned saved_index = musb_periph_inst[rhport]->index;
+//
+//   musb_periph_inst[rhport]->index = epnum;
+//
+//   //Disable double buffering
+//   if (dir_in) {
+//     musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE);
+//   } else {
+//     musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS);
+//   }
+//
+//   musb_periph_inst[rhport]->index = saved_index;
+// }
+
+#endif // CFG_TUD_ENABLED
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // TUSB_MUSB_MAX32_H_
diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h
new file mode 100644
index 000000000..d17e836ee
--- /dev/null
+++ b/src/portable/mentor/musb/musb_ti.h
@@ -0,0 +1,91 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_MUSB_TI_H_
+#define TUSB_MUSB_TI_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_TM4C123
+  #include "TM4C123.h"
+  #define FIFO0_WORD FIFO0
+  #define FIFO1_WORD FIFO1
+//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129
+#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4
+  #include "msp.h"
+#else
+  #error "Unsupported MCUs"
+#endif
+
+#define MUSB_CFG_SHARED_FIFO       0
+#define MUSB_CFG_DYNAMIC_FIFO      1
+#define MUSB_CFG_DYNAMIC_FIFO_SIZE 4096
+
+const uintptr_t MUSB_BASES[] = { USB0_BASE };
+
+// Header supports both device and host modes. Only include what's necessary
+#if CFG_TUD_ENABLED
+
+// Mapping of IRQ numbers to port. Currently just 1.
+static const IRQn_Type  musb_irqs[] = {
+    USB0_IRQn
+};
+
+static inline void musb_dcd_phy_init(uint8_t rhport){
+  (void)rhport;
+  //Nothing to do for this part
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_enable(uint8_t rhport) {
+  NVIC_EnableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_disable(uint8_t rhport) {
+  NVIC_DisableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) {
+  return NVIC_GetEnableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_clear(uint8_t rhport) {
+  NVIC_ClearPendingIRQ(musb_irqs[rhport]);
+}
+
+static inline void musb_dcd_int_handler_enter(uint8_t rhport) {
+  (void)rhport;
+  //Nothing to do for this part
+}
+
+#endif // CFG_TUD_ENABLED
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif // TUSB_MUSB_TI_H_
diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h
index 8f83305a5..4e448c0ed 100644
--- a/src/portable/mentor/musb/musb_type.h
+++ b/src/portable/mentor/musb/musb_type.h
@@ -1,3 +1,29 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
 /******************************************************************************
 *
 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
@@ -32,2590 +58,696 @@
 *
 *******************************************************************************/
 
-#ifndef _TUSB_MUSB_TYPE_H_
-#define _TUSB_MUSB_TYPE_H_
+#ifndef TUSB_MUSB_TYPE_H_
+#define TUSB_MUSB_TYPE_H_
+
+#include "stdint.h"
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FADDR register.
-//
-//*****************************************************************************
-#define USB_FADDR_M             0x0000007F  // Function Address
-#define USB_FADDR_S             0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_POWER register.
-//
-//*****************************************************************************
-#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
-#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
-#define USB_POWER_HSENAB        0x00000020  // High Speed Enable
-#define USB_POWER_HSMODE        0x00000010  // High Speed Enable
-#define USB_POWER_RESET         0x00000008  // RESET Signaling
-#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
-#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
-#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXIS register.
-//
-//*****************************************************************************
-#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
-#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
-#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
-#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
-#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
-#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
-#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
-#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXIS register.
-//
-//*****************************************************************************
-#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
-#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
-#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
-#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
-#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
-#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
-#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXIE register.
-//
-//*****************************************************************************
-#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
-#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
-#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
-#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
-#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
-#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
-#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
-#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
-                                            // Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXIE register.
-//
-//*****************************************************************************
-#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
-#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
-#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
-#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
-#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
-#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
-#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IS register.
-//
-//*****************************************************************************
-#define USB_IS_VBUSERR          0x00000080  // VBUS Error (OTG only)
-#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST (OTG only)
-#define USB_IS_DISCON           0x00000020  // Session Disconnect (OTG only)
-#define USB_IS_CONN             0x00000010  // Session Connect
-#define USB_IS_SOF              0x00000008  // Start of Frame
-#define USB_IS_BABBLE           0x00000004  // Babble Detected
-#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
-#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
-#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IE register.
-//
-//*****************************************************************************
-#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt (OTG
-                                            // only)
-#define USB_IE_SESREQ           0x00000040  // Enable Session Request (OTG
-                                            // only)
-#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
-#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
-#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
-#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
-#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
-#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
-#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FRAME register.
-//
-//*****************************************************************************
-#define USB_FRAME_M             0x000007FF  // Frame Number
-#define USB_FRAME_S             0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPIDX register.
-//
-//*****************************************************************************
-#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
-#define USB_EPIDX_EPIDX_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TEST register.
-//
-//*****************************************************************************
-#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
-#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
-#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
-#define USB_TEST_FORCEHS        0x00000010  // Force High-Speed Mode
-#define USB_TEST_TESTPKT        0x00000008  // Test Packet Mode Enable
-#define USB_TEST_TESTK          0x00000004  // Test_K Mode Enable
-#define USB_TEST_TESTJ          0x00000002  // Test_J Mode Enable
-#define USB_TEST_TESTSE0NAK     0x00000001  // Test_SE0_NAK Test Mode Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO0 register.
-//
-//*****************************************************************************
-#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO0_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO1 register.
-//
-//*****************************************************************************
-#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO1_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO2 register.
-//
-//*****************************************************************************
-#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO2_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO3 register.
-//
-//*****************************************************************************
-#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO3_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO4 register.
-//
-//*****************************************************************************
-#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO4_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO5 register.
-//
-//*****************************************************************************
-#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO5_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO6 register.
-//
-//*****************************************************************************
-#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO6_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO7 register.
-//
-//*****************************************************************************
-#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO7_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DEVCTL register.
-//
-//*****************************************************************************
-#define USB_DEVCTL_DEV          0x00000080  // Device Mode (OTG only)
-#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
-#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
-#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level (OTG only)
-#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
-#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
-#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
-#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
-#define USB_DEVCTL_HOST         0x00000004  // Host Mode
-#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request (OTG only)
-#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End (OTG only)
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CCONF register.
-//
-//*****************************************************************************
-#define USB_CCONF_TXEDMA        0x00000002  // TX Early DMA Enable
-#define USB_CCONF_RXEDMA        0x00000001  // TX Early DMA Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
-//
-//*****************************************************************************
-#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
-#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
-#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
-#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
-#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
-#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64
-#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128
-#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256
-#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512
-#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024
-#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
-//
-//*****************************************************************************
-#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
-#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
-#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
-#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
-#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
-#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64
-#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128
-#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256
-#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512
-#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024
-#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFIFOADD
-// register.
-//
-//*****************************************************************************
-#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
-#define USB_TXFIFOADD_ADDR_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFIFOADD
-// register.
-//
-//*****************************************************************************
-#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
-#define USB_RXFIFOADD_ADDR_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL
-// register.
-//
-//*****************************************************************************
-#define USB_ULPIVBUSCTL_USEEXTVBUSIND                                         \
-                                0x00000002  // Use External VBUS Indicator
-#define USB_ULPIVBUSCTL_USEEXTVBUS                                            \
-                                0x00000001  // Use External VBUS
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_ULPIREGDATA
-// register.
-//
-//*****************************************************************************
-#define USB_ULPIREGDATA_REGDATA_M                                             \
-                                0x000000FF  // Register Data
-#define USB_ULPIREGDATA_REGDATA_S                                             \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_ULPIREGADDR
-// register.
-//
-//*****************************************************************************
-#define USB_ULPIREGADDR_ADDR_M  0x000000FF  // Register Address
-#define USB_ULPIREGADDR_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_ULPIREGCTL
-// register.
-//
-//*****************************************************************************
-#define USB_ULPIREGCTL_RDWR     0x00000004  // Read/Write Control
-#define USB_ULPIREGCTL_REGCMPLT 0x00000002  // Register Access Complete
-#define USB_ULPIREGCTL_REGACC   0x00000001  // Initiate Register Access
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPINFO register.
-//
-//*****************************************************************************
-#define USB_EPINFO_RXEP_M       0x000000F0  // RX Endpoints
-#define USB_EPINFO_TXEP_M       0x0000000F  // TX Endpoints
-#define USB_EPINFO_RXEP_S       4
-#define USB_EPINFO_TXEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RAMINFO register.
-//
-//*****************************************************************************
-#define USB_RAMINFO_DMACHAN_M   0x000000F0  // DMA Channels
-#define USB_RAMINFO_RAMBITS_M   0x0000000F  // RAM Address Bus Width
-#define USB_RAMINFO_DMACHAN_S   4
-#define USB_RAMINFO_RAMBITS_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CONTIM register.
-//
-//*****************************************************************************
-#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
-#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
-#define USB_CONTIM_WTCON_S      4
-#define USB_CONTIM_WTID_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VPLEN register.
-//
-//*****************************************************************************
-#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
-#define USB_VPLEN_VPLEN_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_HSEOF register.
-//
-//*****************************************************************************
-#define USB_HSEOF_HSEOFG_M      0x000000FF  // HIgh-Speed End-of-Frame Gap
-#define USB_HSEOF_HSEOFG_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FSEOF register.
-//
-//*****************************************************************************
-#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
-#define USB_FSEOF_FSEOFG_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LSEOF register.
-//
-//*****************************************************************************
-#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
-#define USB_LSEOF_LSEOFG_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR0_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR0
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR0_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT0
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT0_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR1_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR1_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT1
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT1_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR1_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR1_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT1
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT1_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR2_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR2
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR2_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT2
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT2_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR2_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR2
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR2_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT2
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT2_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR3_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR3
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR3_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT3
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT3_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR3_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR3
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR3_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT3
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT3_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR4_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR4_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT4
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT4_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR4_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR4_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT4
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT4_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR5_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR5_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT5
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT5_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR5_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR5_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT5
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT5_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR6_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR6_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT6
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT6_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR6_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR6_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT6
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT6_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR7_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR7_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT7
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT7_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR7_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR7_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT7
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT7_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CSRL0 register.
-//
-//*****************************************************************************
-#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
-#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
-#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
-#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
-#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
-#define USB_CSRL0_STALL         0x00000020  // Send Stall
-#define USB_CSRL0_SETEND        0x00000010  // Setup End
-#define USB_CSRL0_ERROR         0x00000010  // Error
-#define USB_CSRL0_DATAEND       0x00000008  // Data End
-#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
-#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
-#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
-#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CSRH0 register.
-//
-//*****************************************************************************
-#define USB_CSRH0_DISPING       0x00000008  // PING Disable
-#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
-#define USB_CSRH0_DT            0x00000002  // Data Toggle
-#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_COUNT0 register.
-//
-//*****************************************************************************
-#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
-#define USB_COUNT0_COUNT_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TYPE0 register.
-//
-//*****************************************************************************
-#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
-#define USB_TYPE0_SPEED_HIGH    0x00000040  // High
-#define USB_TYPE0_SPEED_FULL    0x00000080  // Full
-#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_NAKLMT register.
-//
-//*****************************************************************************
-#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
-#define USB_NAKLMT_NAKLMT_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP1_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL1_ERROR       0x00000004  // Error
-#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH1_MODE        0x00000020  // Mode
-#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP1_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL1_OVER        0x00000004  // Overrun
-#define USB_RXCSRL1_ERROR       0x00000004  // Error
-#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
-#define USB_RXCSRH1_INCOMPRX    0x00000001  // Incomplete RX Transmission
-                                            // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT1_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE1_SPEED_HIGH  0x00000040  // High
-#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE1_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL1
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL1_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL1_TXPOLL_M                                              \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL1_TXPOLL_S                                              \
-                                0
-#define USB_TXINTERVAL1_NAKLMT_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE1_SPEED_HIGH  0x00000040  // High
-#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE1_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL1
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL1_TXPOLL_M                                              \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL1_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL1_TXPOLL_S                                              \
-                                0
-#define USB_RXINTERVAL1_NAKLMT_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP2_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL2_ERROR       0x00000004  // Error
-#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH2_MODE        0x00000020  // Mode
-#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP2_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL2_ERROR       0x00000004  // Error
-#define USB_RXCSRL2_OVER        0x00000004  // Overrun
-#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
-#define USB_RXCSRH2_INCOMPRX    0x00000001  // Incomplete RX Transmission
-                                            // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT2_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE2_SPEED_HIGH  0x00000040  // High
-#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE2_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL2
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL2_TXPOLL_M                                              \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL2_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL2_NAKLMT_S                                              \
-                                0
-#define USB_TXINTERVAL2_TXPOLL_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE2_SPEED_HIGH  0x00000040  // High
-#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE2_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL2
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL2_TXPOLL_M                                              \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL2_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL2_TXPOLL_S                                              \
-                                0
-#define USB_RXINTERVAL2_NAKLMT_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP3_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL3_ERROR       0x00000004  // Error
-#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH3_MODE        0x00000020  // Mode
-#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP3_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL3_ERROR       0x00000004  // Error
-#define USB_RXCSRL3_OVER        0x00000004  // Overrun
-#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
-#define USB_RXCSRH3_INCOMPRX    0x00000001  // Incomplete RX Transmission
-                                            // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT3_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE3_SPEED_HIGH  0x00000040  // High
-#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE3_TEP_S       0
+#ifndef __IO
+  #define __IO volatile
+#endif
+
+#ifndef __I
+  #define __I  volatile const
+#endif
+
+#ifndef __O
+  #define __O  volatile
+#endif
+
+#ifndef __R
+  #define __R  volatile const
+#endif
+
+typedef struct TU_ATTR_PACKED {
+  __IO uint16_t maxp;          // 0x00, 0x04: MAXP
+  __IO uint8_t  csrl;          // 0x02, 0x06: CSRL
+  __IO uint8_t  csrh;          // 0x03, 0x07: CSRH
+}musb_ep_maxp_csr_t;
+
+// 0: TX (device IN, host OUT)
+// 1: RX (device OUT, host IN)
+typedef struct TU_ATTR_PACKED {
+  union {
+    struct {
+      __IO uint16_t tx_maxp;       // 0x00: TXMAXP
+      union {
+        __IO uint8_t csr0l;        // 0x02: CSR0
+        __IO uint8_t tx_csrl;      // 0x02: TX CSRL
+      };
+      union {
+        __IO uint8_t csr0h;        // 0x03: CSR0H
+        __IO uint8_t tx_csrh;      // 0x03: TX CSRH
+      };
+
+      __IO uint16_t rx_maxp;       // 0x04: RX MAXP
+      __IO uint8_t  rx_csrl;       // 0x06: RX CSRL
+      __IO uint8_t  rx_csrh;       // 0x07: RX CSRH
+    };
+
+    musb_ep_maxp_csr_t maxp_csr[2];
+  };
+
+  union {
+    __IO uint16_t count0;      // 0x08: COUNT0
+    __IO uint16_t rx_count;    // 0x08: RX COUNT
+  };
+  union {
+    __IO uint8_t type0;        // 0x0A: TYPE0 (host only)
+    __IO uint8_t tx_type;      // 0x0A: TX TYPE
+  };
+  __IO uint8_t tx_interval;    // 0x0B: TX INTERVAL
+  __IO uint8_t rx_type;        // 0x0C: RX TYPE
+  __IO uint8_t rx_interval;    // 0x0D: RX INTERVAL
+  __IO uint8_t reserved_0x0e;  // 0x0E: Reserved
+  union {
+    __IO uint8_t config_data0; // 0x0F: CONFIG DATA
+    struct {
+      __IO uint8_t utmi_data_width : 1; // [0] UTMI Data Width
+      __IO uint8_t softconn_en     : 1; // [1] Soft Connect Enable
+      __IO uint8_t dynamic_fifo    : 1; // [2] Dynamic FIFO Sizing
+      __IO uint8_t hb_tx_en        : 1; // [3] High Bandwidth TX ISO Enable
+      __IO uint8_t hb_rx_en        : 1; // [4] High Bandwidth RX ISO Enable
+      __IO uint8_t big_endian      : 1; // [5] Big Endian
+      __IO uint8_t mp_tx_en        : 1; // [6] Auto splitting BULK TX Enable
+      __IO uint8_t mp_rx_en        : 1; // [7] Auto amalgamation BULK RX Enable
+    } config_data0_bit;
+
+    __IO uint8_t fifo_size;    // 0x0F: FIFO_SIZE
+    struct {
+      __IO uint8_t tx : 4;  // [3:0] TX FIFO Size
+      __IO uint8_t rx : 4;  // [7:4] RX FIFO Size
+    }fifo_size_bit;
+  };
+} musb_ep_csr_t;
+
+TU_VERIFY_STATIC(sizeof(musb_ep_csr_t) == 16, "size is not correct");
+
+typedef struct TU_ATTR_PACKED {
+  //------------- Common -------------//
+  __IO uint8_t  faddr;             // 0x00: FADDR
+  union {
+    __IO uint8_t  power;             // 0x01: POWER
+    struct {
+      __IO uint8_t suspend_mode_en : 1; // [0] SUSPEND Mode Enable
+      __IO uint8_t suspend_mode    : 1; // [1] SUSPEND Mode
+      __IO uint8_t resume_mode     : 1; // [2] RESUME
+      __IO uint8_t reset           : 1; // [3] RESET
+      __IO uint8_t highspeed_mode  : 1; // [4] High Speed Mode
+      __IO uint8_t highspeed_en    : 1; // [5] High Speed Enable
+      __IO uint8_t soft_conn       : 1; // [6] Soft Connect/Disconnect
+      __IO uint8_t iso_update      : 1; // [7] Isochronous Update
+    } power_bit;
+  };
+
+  union {
+    struct {
+      __IO uint16_t intr_tx;           // 0x02: INTR_TX
+      __IO uint16_t intr_rx;           // 0x04: INTR_RX
+    };
+
+    __IO uint16_t intr_ep[2];         // 0x02-0x05: INTR_EP0-1
+  };
+
+  union {
+    struct {
+      __IO uint16_t intr_txen;         // 0x06: INTR_TXEN
+      __IO uint16_t intr_rxen;         // 0x08: INTR_RXEN
+    };
+
+    __IO uint16_t intren_ep[2];       // 0x06-0x09: INTREN_EP0-1
+  };
+
+  __IO uint8_t  intr_usb;          // 0x0A: INTRUSB
+  __IO uint8_t  intr_usben;        // 0x0B: INTRUSBEN
+
+  __IO uint16_t frame;             // 0x0C: FRAME
+  __IO uint8_t  index;             // 0x0E: INDEX
+  __IO uint8_t  testmode;          // 0x0F: TESTMODE
+
+  //------------- Endpoint CSR (indexed) -------------//
+  musb_ep_csr_t indexed_csr;       // 0x10-0x1F: Indexed CSR 0-15
+
+  //------------- FIFOs -------------//
+  __IO uint32_t fifo[16];          // 0x20-0x5C: FIFO 0-15
+
+  // Common (2)
+  __IO uint8_t  devctl;            // 0x60: DEVCTL
+  __IO uint8_t  misc;              // 0x61: MISC
+
+  //------------- Dynammic FIFO (indexed) -------------//
+  union {
+    struct {
+      __IO uint8_t  txfifo_sz;         // 0x62: TXFIFO_SZ
+      __IO uint8_t  rxfifo_sz;         // 0x63: RXFIFO_SZ
+    };
+    __IO uint8_t fifo_size[2];
+  };
+
+  union {
+    struct {
+      __IO uint16_t txfifo_addr;       // 0x64: TXFIFO_ADDR
+      __IO uint16_t rxfifo_addr;       // 0x66: RXFIFO_ADDR
+    };
+    __IO uint16_t fifo_addr[2];
+  };
+
+  //------------- Additional Control and Configuration -------------//
+  union {
+    __O  uint32_t vcontrol;        // 0x68: PHY VCONTROL
+    __IO uint32_t vstatus;         // 0x68: PHY VSTATUS
+  };
+  union {
+    __IO uint16_t hwvers;            // 0x6C: HWVERS
+    struct {
+      __IO uint16_t minor : 10;     // [9:0] Minor
+      __IO uint16_t major : 5;      // [14:10] Major
+      __IO uint16_t rc    : 1;      // [15] Release Candidate
+    } hwvers_bit;
+  };
+  __R  uint16_t rsv_0x6e_0x77[5];  // 0x6E-0x77: Reserved
+
+   //------------- Additional Configuration -------------//
+  union {
+    __IO uint8_t  epinfo;            // 0x78: EPINFO
+    struct {
+      __IO uint8_t tx_ep_num : 4;    // [3:0] TX Endpoints
+      __IO uint8_t rx_ep_num : 4;    // [7:4] RX Endpoints
+    } epinfo_bit;
+  };
+  union {
+    __IO uint8_t  raminfo;           // 0x79: RAMINFO
+    struct {
+      __IO uint8_t ram_bits    : 4;  // [3:0] RAM Address Bus Width
+      __IO uint8_t dma_channel : 4;  // [7:4] DMA Channels
+    }raminfo_bit;
+  };
+  union {
+    __IO uint8_t  link_info;       // 0x7A: LINK_INFO
+    __IO uint8_t  adi_softreset;   // 0x7A: AnalogDevice SOFTRESET
+  };
+  __IO uint8_t  vplen;             // 0x7B: VPLEN
+  __IO uint8_t  hs_eof1;           // 0x7C: HS_EOF1
+  __IO uint8_t  fs_eof1;           // 0x7D: FS_EOF1
+  __IO uint8_t  ls_eof1;           // 0x7E: LS_EOF1
+  __IO uint8_t  soft_rst;          // 0x7F: SOFT_RST
+
+  //------------- Target Endpoints (multipoint option) -------------//
+  __IO uint16_t ctuch;             // 0x80: CTUCH
+  __IO uint16_t cthsrtn;           // 0x82: CTHSRTN
+  __R  uint32_t rsv_0x84_0xff[31]; // 0x84-0xFF: Reserved
+
+  //------------- Non-Indexed Endpoint CSRs -------------//
+  // TI tm4c can access this directly, but should use indexed_csr for portability
+  musb_ep_csr_t abs_csr[16];        // 0x100-0x1FF: EP0-15 CSR
+
+  //------------- DMA -------------//
+  __IO uint8_t dma_intr;             // 0x200: DMA_INTR
+  __R  uint8_t rsv_0x201_0x203[3];   // 0x201-0x203: Reserved
+  struct {
+    __IO uint16_t cntl;             // 0x204: DMA_CNTL
+    __IO uint16_t rsv_0x206;        // 0x206: Reserved
+    __IO uint32_t addr;             // 0x208: DMA_ADDR
+    __IO uint32_t count;            // 0x20C: DMA_COUNT
+    __IO uint32_t rsv_0x210;        // 0x210: Reserved
+  }dma[8];
+  __R  uint32_t rsv_0x284_0x2FF[31]; // 0x284-0x2FF: Reserved
+
+  //------------- Extended -------------//
+  __R uint32_t rsv_0x300;           // 0x300: Reserved
+  struct {
+    __IO uint16_t count;            // 0x304: REQ_PACKET_COUNT
+    __R  uint16_t rsv_0x306;        // 0x306: Reserved
+  }req_packet[15];
+
+  __IO uint16_t rx_doulbe_packet_disable; // 0x340: RX_DOUBLE_PACKET_DISABLE
+  __IO uint16_t tx_double_packet_disable; // 0x342: TX_DOUBLE_PACKET_DISABLE
+
+  __IO uint16_t chirp_timeout;            // 0x344: CHIRP_TIMEOUT
+  __IO uint16_t hs_to_utm;                // 0x346: HS_TO_UTM delay
+  __IO uint16_t hs_timeout_adder;         // 0x348: HS_TIMEOUT_ADDER
+
+  __R uint8_t rsv_34A_34f[6];             // 0x34A-0x34F: Reserved
+} musb_regs_t;
+
+TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x350, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Helper
+//--------------------------------------------------------------------+
+TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_regs, unsigned epnum) {
+  musb_regs->index = epnum;
+  return &musb_regs->indexed_csr;
+}
+
+//--------------------------------------------------------------------+
+// Register Bit Field
+//--------------------------------------------------------------------+
+
+// 0x01: Power
+#define MUSB_POWER_ISOUP         0x0080  // Isochronous Update
+#define MUSB_POWER_SOFTCONN      0x0040  // Soft Connect/Disconnect
+#define MUSB_POWER_HSENAB        0x0020  // High Speed Enable
+#define MUSB_POWER_HSMODE        0x0010  // High Speed Enable
+#define MUSB_POWER_RESET         0x0008  // RESET Signaling
+#define MUSB_POWER_RESUME        0x0004  // RESUME Signaling
+#define MUSB_POWER_SUSPEND       0x0002  // SUSPEND Mode
+#define MUSB_POWER_PWRDNPHY      0x0001  // Power Down PHY
+
+// Interrupt TX/RX Status and Enable: each bit is for an endpoint
+
+// 0x6c: HWVERS
+#define MUSB_HWVERS_RC_SHIFT    15
+#define MUSB_HWVERS_RC_MASK     0x8000
+#define MUSB_HWVERS_MAJOR_SHIFT 10
+#define MUSB_HWVERS_MAJOR_MASK  0x7C00
+#define MUSB_HWVERS_MINOR_SHIFT 0
+#define MUSB_HWVERS_MINOR_MASK  0x03FF
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL3
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL3_TXPOLL_M                                              \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL3_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL3_TXPOLL_S                                              \
-                                0
-#define USB_TXINTERVAL3_NAKLMT_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE3_SPEED_HIGH  0x00000040  // High
-#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE3_TEP_S       0
+// 0x12, 0x16: TX/RX CSRL
+#define MUSB_CSRL_PACKET_READY(_rx)      (1u << 0)
+#define MUSB_CSRL_FLUSH_FIFO(_rx)        (1u << ((_rx) ? 4 : 3))
+#define MUSB_CSRL_SEND_STALL(_rx)        (1u << ((_rx) ? 5 : 4))
+#define MUSB_CSRL_STALLED(_rx)           (1u << ((_rx) ? 6 : 5))
+#define MUSB_CSRL_CLEAR_DATA_TOGGLE(_rx) (1u << ((_rx) ? 7 : 6))
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL3
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL3_TXPOLL_M                                              \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL3_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL3_TXPOLL_S                                              \
-                                0
-#define USB_RXINTERVAL3_NAKLMT_S                                              \
-                                0
+// 0x13, 0x17: TX/RX CSRH
+#define MUSB_CSRH_DISABLE_DOUBLE_PACKET(_rx) (1u << 1)
+#define MUSB_CSRH_TX_MODE                    (1u << 5) // 1 = TX, 0 = RX. only relevant for SHARED FIFO
+#define MUSB_CSRH_ISO                        (1u << 6)
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP4_MAXLOAD_S   0
+// 0x62, 0x63: TXFIFO_SZ, RXFIFO_SZ
+#define MUSB_FIFOSZ_DOUBLE_PACKET            (1u << 4)
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL4_ERROR       0x00000004  // Error
-#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+// The following are defines for the bit fields in the MUSB_O_IS register.
 //
 //*****************************************************************************
-#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH4_MODE        0x00000020  // Mode
-#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
+#define MUSB_IS_VBUSERR          0x0080  // VBUS Error (OTG only)
+#define MUSB_IS_SESREQ           0x0040  // SESSION REQUEST (OTG only)
+#define MUSB_IS_DISCON           0x0020  // Session Disconnect (OTG only)
+#define MUSB_IS_CONN             0x0010  // Session Connect
+#define MUSB_IS_SOF              0x0008  // Start of Frame
+#define MUSB_IS_BABBLE           0x0004  // Babble Detected
+#define MUSB_IS_RESET            0x0004  // RESET Signaling Detected
+#define MUSB_IS_RESUME           0x0002  // RESUME Signaling Detected
+#define MUSB_IS_SUSPEND          0x0001  // SUSPEND Signaling Detected
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+// The following are defines for the bit fields in the MUSB_O_IE register.
 //
 //*****************************************************************************
-#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP4_MAXLOAD_S   0
+#define MUSB_IE_VBUSERR          0x0080  // Enable VBUS Error Interrupt (OTG only)
+#define MUSB_IE_SESREQ           0x0040  // Enable Session Request (OTG only)
+#define MUSB_IE_DISCON           0x0020  // Enable Disconnect Interrupt
+#define MUSB_IE_CONN             0x0010  // Enable Connect Interrupt
+#define MUSB_IE_SOF              0x0008  // Enable Start-of-Frame Interrupt
+#define MUSB_IE_BABBLE           0x0004  // Enable Babble Interrupt
+#define MUSB_IE_RESET            0x0004  // Enable RESET Interrupt
+#define MUSB_IE_RESUME           0x0002  // Enable RESUME Interrupt
+#define MUSB_IE_SUSPND           0x0001  // Enable SUSPEND Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+// The following are defines for the bit fields in the MUSB_O_FRAME register.
 //
 //*****************************************************************************
-#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL4_OVER        0x00000004  // Overrun
-#define USB_RXCSRL4_ERROR       0x00000004  // Error
-#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
+#define MUSB_FRAME_M             0x07FF  // Frame Number
+#define MUSB_FRAME_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+// The following are defines for the bit fields in the MUSB_O_TEST register.
 //
 //*****************************************************************************
-#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
-#define USB_RXCSRH4_INCOMPRX    0x00000001  // Incomplete RX Transmission
-                                            // Status
+#define MUSB_TEST_FORCEH         0x0080  // Force Host Mode
+#define MUSB_TEST_FIFOACC        0x0040  // FIFO Access
+#define MUSB_TEST_FORCEFS        0x0020  // Force Full-Speed Mode
+#define MUSB_TEST_FORCEHS        0x0010  // Force High-Speed Mode
+#define MUSB_TEST_TESTPKT        0x0008  // Test Packet Mode Enable
+#define MUSB_TEST_TESTK          0x0004  // Test_K Mode Enable
+#define MUSB_TEST_TESTJ          0x0002  // Test_J Mode Enable
+#define MUSB_TEST_TESTSE0NAK     0x0001  // Test_SE0_NAK Test Mode Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+// The following are defines for the bit fields in the MUSB_O_DEVCTL register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT4_COUNT_S    0
+#define MUSB_DEVCTL_DEV          0x0080  // Device Mode (OTG only)
+#define MUSB_DEVCTL_FSDEV        0x0040  // Full-Speed Device Detected
+#define MUSB_DEVCTL_LSDEV        0x0020  // Low-Speed Device Detected
+#define MUSB_DEVCTL_VBUS_M       0x0018  // VBUS Level (OTG only)
+#define MUSB_DEVCTL_VBUS_NONE    0x0000  // Below SessionEnd
+#define MUSB_DEVCTL_VBUS_SEND    0x0008  // Above SessionEnd, below AValid
+#define MUSB_DEVCTL_VBUS_AVALID  0x0010  // Above AValid, below VBUSValid
+#define MUSB_DEVCTL_VBUS_VALID   0x0018  // Above VBUSValid
+#define MUSB_DEVCTL_HOST         0x0004  // Host Mode
+#define MUSB_DEVCTL_HOSTREQ      0x0002  // Host Request (OTG only)
+#define MUSB_DEVCTL_SESSION      0x0001  // Session Start/End (OTG only)
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+// The following are defines for the bit fields in the MUSB_O_CCONF register.
 //
 //*****************************************************************************
-#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE4_SPEED_HIGH  0x00000040  // High
-#define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE4_TEP_S       0
+#define MUSB_CCONF_TXEDMA        0x0002  // TX Early DMA Enable
+#define MUSB_CCONF_RXEDMA        0x0001  // TX Early DMA Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// The following are defines for the bit fields in the MUSB_O_ULPIVBUSCTL
 // register.
 //
 //*****************************************************************************
-#define USB_TXINTERVAL4_TXPOLL_M                                              \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL4_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL4_NAKLMT_S                                              \
-                                0
-#define USB_TXINTERVAL4_TXPOLL_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE4_SPEED_HIGH  0x00000040  // High
-#define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE4_TEP_S       0
+#define MUSB_ULPIVBUSCTL_USEEXTVBUSIND  0x0002  // Use External VBUS Indicator
+#define MUSB_ULPIVBUSCTL_USEEXTVBUS     0x0001  // Use External VBUS
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// The following are defines for the bit fields in the MUSB_O_ULPIREGDATA
 // register.
 //
 //*****************************************************************************
-#define USB_RXINTERVAL4_TXPOLL_M                                              \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL4_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL4_NAKLMT_S                                              \
-                                0
-#define USB_RXINTERVAL4_TXPOLL_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP5_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL5_ERROR       0x00000004  // Error
-#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH5_MODE        0x00000020  // Mode
-#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP5_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL5_ERROR       0x00000004  // Error
-#define USB_RXCSRL5_OVER        0x00000004  // Overrun
-#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
-#define USB_RXCSRH5_INCOMPRX    0x00000001  // Incomplete RX Transmission
-                                            // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT5_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE5_SPEED_HIGH  0x00000040  // High
-#define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE5_TEP_S       0
-
+#define MUSB_ULPIREGDATA_REGDATA_M      0x00FF  // Register Data
+#define MUSB_ULPIREGDATA_REGDATA_S      0
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// The following are defines for the bit fields in the MUSB_O_ULPIREGADDR
 // register.
 //
 //*****************************************************************************
-#define USB_TXINTERVAL5_TXPOLL_M                                              \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL5_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL5_NAKLMT_S                                              \
-                                0
-#define USB_TXINTERVAL5_TXPOLL_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE5_SPEED_HIGH  0x00000040  // High
-#define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE5_TEP_S       0
+#define MUSB_ULPIREGADDR_ADDR_M  0x00FF  // Register Address
+#define MUSB_ULPIREGADDR_ADDR_S  0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// The following are defines for the bit fields in the MUSB_O_ULPIREGCTL
 // register.
 //
 //*****************************************************************************
-#define USB_RXINTERVAL5_TXPOLL_M                                              \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL5_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL5_TXPOLL_S                                              \
-                                0
-#define USB_RXINTERVAL5_NAKLMT_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP6_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL6_ERROR       0x00000004  // Error
-#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH6_MODE        0x00000020  // Mode
-#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
+#define MUSB_ULPIREGCTL_RDWR     0x0004  // Read/Write Control
+#define MUSB_ULPIREGCTL_REGCMPLT 0x0002  // Register Access Complete
+#define MUSB_ULPIREGCTL_REGACC   0x0001  // Initiate Register Access
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+// The following are defines for the bit fields in the MUSB_O_EPINFO register.
 //
 //*****************************************************************************
-#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP6_MAXLOAD_S   0
+#define MUSB_EPINFO_RXEP_M       0x00F0  // RX Endpoints
+#define MUSB_EPINFO_TXEP_M       0x000F  // TX Endpoints
+#define MUSB_EPINFO_RXEP_S       4
+#define MUSB_EPINFO_TXEP_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+// The following are defines for the bit fields in the MUSB_O_RAMINFO register.
 //
 //*****************************************************************************
-#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL6_ERROR       0x00000004  // Error
-#define USB_RXCSRL6_OVER        0x00000004  // Overrun
-#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
+#define MUSB_RAMINFO_DMACHAN_M   0x00F0  // DMA Channels
+#define MUSB_RAMINFO_RAMBITS_M   0x000F  // RAM Address Bus Width
+#define MUSB_RAMINFO_DMACHAN_S   4
+#define MUSB_RAMINFO_RAMBITS_S   0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+// The following are defines for the bit fields in the MUSB_O_CONTIM register.
 //
 //*****************************************************************************
-#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
-#define USB_RXCSRH6_INCOMPRX    0x00000001  // Incomplete RX Transmission
-                                            // Status
+#define MUSB_CONTIM_WTCON_M      0x00F0  // Connect Wait
+#define MUSB_CONTIM_WTID_M       0x000F  // Wait ID
+#define MUSB_CONTIM_WTCON_S      4
+#define MUSB_CONTIM_WTID_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+// The following are defines for the bit fields in the MUSB_O_VPLEN register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT6_COUNT_S    0
+#define MUSB_VPLEN_VPLEN_M       0x00FF  // VBUS Pulse Length
+#define MUSB_VPLEN_VPLEN_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+// The following are defines for the bit fields in the MUSB_O_HSEOF register.
 //
 //*****************************************************************************
-#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE6_SPEED_HIGH  0x00000040  // High
-#define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE6_TEP_S       0
+#define MUSB_HSEOF_HSEOFG_M      0x00FF  // HIgh-Speed End-of-Frame Gap
+#define MUSB_HSEOF_HSEOFG_S      0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXINTERVAL6
-// register.
+// The following are defines for the bit fields in the MUSB_O_FSEOF register.
 //
 //*****************************************************************************
-#define USB_TXINTERVAL6_TXPOLL_M                                              \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL6_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL6_TXPOLL_S                                              \
-                                0
-#define USB_TXINTERVAL6_NAKLMT_S                                              \
-                                0
+#define MUSB_FSEOF_FSEOFG_M      0x00FF  // Full-Speed End-of-Frame Gap
+#define MUSB_FSEOF_FSEOFG_S      0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+// The following are defines for the bit fields in the MUSB_O_LSEOF register.
 //
 //*****************************************************************************
-#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE6_SPEED_HIGH  0x00000040  // High
-#define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE6_TEP_S       0
+#define MUSB_LSEOF_LSEOFG_M      0x00FF  // Low-Speed End-of-Frame Gap
+#define MUSB_LSEOF_LSEOFG_S      0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXINTERVAL6
-// register.
+// The following are defines for the bit fields in the MUSB_O_CSRL0 register.
 //
 //*****************************************************************************
-#define USB_RXINTERVAL6_TXPOLL_M                                              \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL6_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL6_NAKLMT_S                                              \
-                                0
-#define USB_RXINTERVAL6_TXPOLL_S                                              \
-                                0
+#define MUSB_CSRL0_NAKTO         0x0080  // NAK Timeout
+#define MUSB_CSRL0_SETENDC       0x0080  // Setup End Clear
+#define MUSB_CSRL0_STATUS        0x0040  // STATUS Packet
+#define MUSB_CSRL0_RXRDYC        0x0040  // RXRDY Clear
+#define MUSB_CSRL0_REQPKT        0x0020  // Request Packet
+#define MUSB_CSRL0_STALL         0x0020  // Send Stall
+#define MUSB_CSRL0_SETEND        0x0010  // Setup End
+#define MUSB_CSRL0_ERROR         0x0010  // Error
+#define MUSB_CSRL0_DATAEND       0x0008  // Data End
+#define MUSB_CSRL0_SETUP         0x0008  // Setup Packet
+#define MUSB_CSRL0_STALLED       0x0004  // Endpoint Stalled
+#define MUSB_CSRL0_TXRDY         0x0002  // Transmit Packet Ready
+#define MUSB_CSRL0_RXRDY         0x0001  // Receive Packet Ready
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+// The following are defines for the bit fields in the MUSB_O_CSRH0 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP7_MAXLOAD_S   0
+#define MUSB_CSRH0_DISPING       0x0008  // PING Disable
+#define MUSB_CSRH0_DTWE          0x0004  // Data Toggle Write Enable
+#define MUSB_CSRH0_DT            0x0002  // Data Toggle
+#define MUSB_CSRH0_FLUSH         0x0001  // Flush FIFO
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+// The following are defines for the bit fields in the MUSB_O_TYPE0 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL7_ERROR       0x00000004  // Error
-#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
+#define MUSB_TYPE0_SPEED_M       0x00C0  // Operating Speed
+#define MUSB_TYPE0_SPEED_HIGH    0x0040  // High
+#define MUSB_TYPE0_SPEED_FULL    0x0080  // Full
+#define MUSB_TYPE0_SPEED_LOW     0x00C0  // Low
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+// The following are defines for the bit fields in the MUSB_O_NAKLMT register.
 //
 //*****************************************************************************
-#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH7_MODE        0x00000020  // Mode
-#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
+#define MUSB_NAKLMT_NAKLMT_M     0x001F  // EP0 NAK Limit
+#define MUSB_NAKLMT_NAKLMT_S     0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+// The following are defines for the bit fields in the MUSB_O_TXCSRL1 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP7_MAXLOAD_S   0
+#define MUSB_TXCSRL1_NAKTO       0x0080  // NAK Timeout
+#define MUSB_TXCSRL1_CLRDT       0x0040  // Clear Data Toggle
+#define MUSB_TXCSRL1_STALLED     0x0020  // Endpoint Stalled
+#define MUSB_TXCSRL1_STALL       0x0010  // Send STALL
+#define MUSB_TXCSRL1_SETUP       0x0010  // Setup Packet
+#define MUSB_TXCSRL1_FLUSH       0x0008  // Flush FIFO
+#define MUSB_TXCSRL1_ERROR       0x0004  // Error
+#define MUSB_TXCSRL1_UNDRN       0x0004  // Underrun
+#define MUSB_TXCSRL1_FIFONE      0x0002  // FIFO Not Empty
+#define MUSB_TXCSRL1_TXRDY       0x0001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+// The following are defines for the bit fields in the MUSB_O_TXCSRH1 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL7_ERROR       0x00000004  // Error
-#define USB_RXCSRL7_OVER        0x00000004  // Overrun
-#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
+#define MUSB_TXCSRH1_AUTOSET     0x0080  // Auto Set
+#define MUSB_TXCSRH1_ISO         0x0040  // Isochronous Transfers
+#define MUSB_TXCSRH1_MODE        0x0020  // Mode
+#define MUSB_TXCSRH1_DMAEN       0x0010  // DMA Request Enable
+#define MUSB_TXCSRH1_FDT         0x0008  // Force Data Toggle
+#define MUSB_TXCSRH1_DMAMOD      0x0004  // DMA Request Mode
+#define MUSB_TXCSRH1_DTWE        0x0002  // Data Toggle Write Enable
+#define MUSB_TXCSRH1_DT          0x0001  // Data Toggle
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+// The following are defines for the bit fields in the MUSB_O_RXCSRL1 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
-#define USB_RXCSRH7_INCOMPRX    0x00000001  // Incomplete RX Transmission
-                                            // Status
+#define MUSB_RXCSRL1_CLRDT       0x0080  // Clear Data Toggle
+#define MUSB_RXCSRL1_STALLED     0x0040  // Endpoint Stalled
+#define MUSB_RXCSRL1_STALL       0x0020  // Send STALL
+#define MUSB_RXCSRL1_REQPKT      0x0020  // Request Packet
+#define MUSB_RXCSRL1_FLUSH       0x0010  // Flush FIFO
+#define MUSB_RXCSRL1_DATAERR     0x0008  // Data Error
+#define MUSB_RXCSRL1_NAKTO       0x0008  // NAK Timeout
+#define MUSB_RXCSRL1_OVER        0x0004  // Overrun
+#define MUSB_RXCSRL1_ERROR       0x0004  // Error
+#define MUSB_RXCSRL1_FULL        0x0002  // FIFO Full
+#define MUSB_RXCSRL1_RXRDY       0x0001  // Receive Packet Ready
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+// The following are defines for the bit fields in the MUSB_O_RXCSRH1 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT7_COUNT_S    0
+#define MUSB_RXCSRH1_AUTOCL      0x0080  // Auto Clear
+#define MUSB_RXCSRH1_AUTORQ      0x0040  // Auto Request
+#define MUSB_RXCSRH1_ISO         0x0040  // Isochronous Transfers
+#define MUSB_RXCSRH1_DMAEN       0x0020  // DMA Request Enable
+#define MUSB_RXCSRH1_DISNYET     0x0010  // Disable NYET
+#define MUSB_RXCSRH1_PIDERR      0x0010  // PID Error
+#define MUSB_RXCSRH1_DMAMOD      0x0008  // DMA Request Mode
+#define MUSB_RXCSRH1_DTWE        0x0004  // Data Toggle Write Enable
+#define MUSB_RXCSRH1_DT          0x0002  // Data Toggle
+#define MUSB_RXCSRH1_INCOMPRX    0x0001  // Incomplete RX Transmission Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+// The following are defines for the bit fields in the MUSB_O_TXTYPE1 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE7_SPEED_HIGH  0x00000040  // High
-#define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE7_TEP_S       0
+#define MUSB_TXTYPE1_SPEED_M     0x00C0  // Operating Speed
+#define MUSB_TXTYPE1_SPEED_DFLT  0x0000  // Default
+#define MUSB_TXTYPE1_SPEED_HIGH  0x0040  // High
+#define MUSB_TXTYPE1_SPEED_FULL  0x0080  // Full
+#define MUSB_TXTYPE1_SPEED_LOW   0x00C0  // Low
+#define MUSB_TXTYPE1_PROTO_M     0x0030  // Protocol
+#define MUSB_TXTYPE1_PROTO_CTRL  0x0000  // Control
+#define MUSB_TXTYPE1_PROTO_ISOC  0x0010  // Isochronous
+#define MUSB_TXTYPE1_PROTO_BULK  0x0020  // Bulk
+#define MUSB_TXTYPE1_PROTO_INT   0x0030  // Interrupt
+#define MUSB_TXTYPE1_TEP_M       0x000F  // Target Endpoint Number
+#define MUSB_TXTYPE1_TEP_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// The following are defines for the bit fields in the MUSB_O_TXINTERVAL1
 // register.
 //
 //*****************************************************************************
-#define USB_TXINTERVAL7_TXPOLL_M                                              \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL7_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL7_NAKLMT_S                                              \
-                                0
-#define USB_TXINTERVAL7_TXPOLL_S                                              \
-                                0
+#define MUSB_TXINTERVAL1_NAKLMT_M 0x00FF  // NAK Limit
+#define MUSB_TXINTERVAL1_TXPOLL_M 0x00FF  // TX Polling
+#define MUSB_TXINTERVAL1_TXPOLL_S 0
+#define MUSB_TXINTERVAL1_NAKLMT_S 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+// The following are defines for the bit fields in the MUSB_O_RXTYPE1 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE7_SPEED_HIGH  0x00000040  // High
-#define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE7_TEP_S       0
+#define MUSB_RXTYPE1_SPEED_M     0x00C0  // Operating Speed
+#define MUSB_RXTYPE1_SPEED_DFLT  0x0000  // Default
+#define MUSB_RXTYPE1_SPEED_HIGH  0x0040  // High
+#define MUSB_RXTYPE1_SPEED_FULL  0x0080  // Full
+#define MUSB_RXTYPE1_SPEED_LOW   0x00C0  // Low
+#define MUSB_RXTYPE1_PROTO_M     0x0030  // Protocol
+#define MUSB_RXTYPE1_PROTO_CTRL  0x0000  // Control
+#define MUSB_RXTYPE1_PROTO_ISOC  0x0010  // Isochronous
+#define MUSB_RXTYPE1_PROTO_BULK  0x0020  // Bulk
+#define MUSB_RXTYPE1_PROTO_INT   0x0030  // Interrupt
+#define MUSB_RXTYPE1_TEP_M       0x000F  // Target Endpoint Number
+#define MUSB_RXTYPE1_TEP_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// The following are defines for the bit fields in the MUSB_O_RXINTERVAL1
 // register.
 //
 //*****************************************************************************
-#define USB_RXINTERVAL7_TXPOLL_M                                              \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL7_NAKLMT_M                                              \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL7_NAKLMT_S                                              \
-                                0
-#define USB_RXINTERVAL7_TXPOLL_S                                              \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAINTR register.
-//
-//*****************************************************************************
-#define USB_DMAINTR_CH7         0x00000080  // Channel 7 DMA Interrupt
-#define USB_DMAINTR_CH6         0x00000040  // Channel 6 DMA Interrupt
-#define USB_DMAINTR_CH5         0x00000020  // Channel 5 DMA Interrupt
-#define USB_DMAINTR_CH4         0x00000010  // Channel 4 DMA Interrupt
-#define USB_DMAINTR_CH3         0x00000008  // Channel 3 DMA Interrupt
-#define USB_DMAINTR_CH2         0x00000004  // Channel 2 DMA Interrupt
-#define USB_DMAINTR_CH1         0x00000002  // Channel 1 DMA Interrupt
-#define USB_DMAINTR_CH0         0x00000001  // Channel 0 DMA Interrupt
+#define MUSB_RXINTERVAL1_TXPOLL_M 0x00FF  // RX Polling
+#define MUSB_RXINTERVAL1_NAKLMT_M 0x00FF  // NAK Limit
+#define MUSB_RXINTERVAL1_TXPOLL_S 0
+#define MUSB_RXINTERVAL1_NAKLMT_S 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_DMACTL0 register.
+// The following are defines for the bit fields in the MUSB_O_DMACTL0 register.
 //
 //*****************************************************************************
-#define USB_DMACTL0_BRSTM_M     0x00000600  // Burst Mode
-#define USB_DMACTL0_BRSTM_ANY   0x00000000  // Bursts of unspecified length
-#define USB_DMACTL0_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
-#define USB_DMACTL0_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+#define MUSB_DMACTL0_BRSTM_M     0x0600  // Burst Mode
+#define MUSB_DMACTL0_BRSTM_ANY   0x0000  // Bursts of unspecified length
+#define MUSB_DMACTL0_BRSTM_INC4  0x0200  // INCR4 or unspecified length
+#define MUSB_DMACTL0_BRSTM_INC8  0x0400  // INCR8, INCR4 or unspecified
                                             // length
-#define USB_DMACTL0_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+#define MUSB_DMACTL0_BRSTM_INC16 0x0600  // INCR16, INCR8, INCR4 or
                                             // unspecified length
-#define USB_DMACTL0_ERR         0x00000100  // Bus Error Bit
-#define USB_DMACTL0_EP_M        0x000000F0  // Endpoint number
-#define USB_DMACTL0_IE          0x00000008  // DMA Interrupt Enable
-#define USB_DMACTL0_MODE        0x00000004  // DMA Transfer Mode
-#define USB_DMACTL0_DIR         0x00000002  // DMA Direction
-#define USB_DMACTL0_ENABLE      0x00000001  // DMA Transfer Enable
-#define USB_DMACTL0_EP_S        4
+#define MUSB_DMACTL0_ERR         0x0100  // Bus Error Bit
+#define MUSB_DMACTL0_EP_M        0x00F0  // Endpoint number
+#define MUSB_DMACTL0_IE          0x0008  // DMA Interrupt Enable
+#define MUSB_DMACTL0_MODE        0x0004  // DMA Transfer Mode
+#define MUSB_DMACTL0_DIR         0x0002  // DMA Direction
+#define MUSB_DMACTL0_ENABLE      0x0001  // DMA Transfer Enable
+#define MUSB_DMACTL0_EP_S        4
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_DMAADDR0 register.
+// The following are defines for the bit fields in the MUSB_O_DMAADDR0 register.
 //
 //*****************************************************************************
-#define USB_DMAADDR0_ADDR_M     0xFFFFFFFC  // DMA Address
-#define USB_DMAADDR0_ADDR_S     2
+#define MUSB_DMAADDR0_ADDR_M     0xFFFFFFFC  // DMA Address
+#define MUSB_DMAADDR0_ADDR_S     2
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_DMACOUNT0
+// The following are defines for the bit fields in the MUSB_O_DMACOUNT0
 // register.
 //
 //*****************************************************************************
-#define USB_DMACOUNT0_COUNT_M   0xFFFFFFFC  // DMA Count
-#define USB_DMACOUNT0_COUNT_S   2
+#define MUSB_DMACOUNT0_COUNT_M   0xFFFFFFFC  // DMA Count
+#define MUSB_DMACOUNT0_COUNT_S   2
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_DMACTL1 register.
+// The following are defines for the bit fields in the MUSB_O_CTO register.
 //
 //*****************************************************************************
-#define USB_DMACTL1_BRSTM_M     0x00000600  // Burst Mode
-#define USB_DMACTL1_BRSTM_ANY   0x00000000  // Bursts of unspecified length
-#define USB_DMACTL1_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
-#define USB_DMACTL1_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
-                                            // length
-#define USB_DMACTL1_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
-                                            // unspecified length
-#define USB_DMACTL1_ERR         0x00000100  // Bus Error Bit
-#define USB_DMACTL1_EP_M        0x000000F0  // Endpoint number
-#define USB_DMACTL1_IE          0x00000008  // DMA Interrupt Enable
-#define USB_DMACTL1_MODE        0x00000004  // DMA Transfer Mode
-#define USB_DMACTL1_DIR         0x00000002  // DMA Direction
-#define USB_DMACTL1_ENABLE      0x00000001  // DMA Transfer Enable
-#define USB_DMACTL1_EP_S        4
+#define MUSB_CTO_CCTV_M          0xFFFF  // Configurable Chirp Timeout Value
+#define MUSB_CTO_CCTV_S          0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_DMAADDR1 register.
+// The following are defines for the bit fields in the MUSB_O_HHSRTN register.
 //
 //*****************************************************************************
-#define USB_DMAADDR1_ADDR_M     0xFFFFFFFC  // DMA Address
-#define USB_DMAADDR1_ADDR_S     2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT1
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT1_COUNT_M   0xFFFFFFFC  // DMA Count
-#define USB_DMACOUNT1_COUNT_S   2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL2 register.
-//
-//*****************************************************************************
-#define USB_DMACTL2_BRSTM_M     0x00000600  // Burst Mode
-#define USB_DMACTL2_BRSTM_ANY   0x00000000  // Bursts of unspecified length
-#define USB_DMACTL2_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
-#define USB_DMACTL2_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
-                                            // length
-#define USB_DMACTL2_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
-                                            // unspecified length
-#define USB_DMACTL2_ERR         0x00000100  // Bus Error Bit
-#define USB_DMACTL2_EP_M        0x000000F0  // Endpoint number
-#define USB_DMACTL2_IE          0x00000008  // DMA Interrupt Enable
-#define USB_DMACTL2_MODE        0x00000004  // DMA Transfer Mode
-#define USB_DMACTL2_DIR         0x00000002  // DMA Direction
-#define USB_DMACTL2_ENABLE      0x00000001  // DMA Transfer Enable
-#define USB_DMACTL2_EP_S        4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR2 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR2_ADDR_M     0xFFFFFFFC  // DMA Address
-#define USB_DMAADDR2_ADDR_S     2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT2
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT2_COUNT_M   0xFFFFFFFC  // DMA Count
-#define USB_DMACOUNT2_COUNT_S   2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL3 register.
-//
-//*****************************************************************************
-#define USB_DMACTL3_BRSTM_M     0x00000600  // Burst Mode
-#define USB_DMACTL3_BRSTM_ANY   0x00000000  // Bursts of unspecified length
-#define USB_DMACTL3_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
-#define USB_DMACTL3_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
-                                            // length
-#define USB_DMACTL3_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
-                                            // unspecified length
-#define USB_DMACTL3_ERR         0x00000100  // Bus Error Bit
-#define USB_DMACTL3_EP_M        0x000000F0  // Endpoint number
-#define USB_DMACTL3_IE          0x00000008  // DMA Interrupt Enable
-#define USB_DMACTL3_MODE        0x00000004  // DMA Transfer Mode
-#define USB_DMACTL3_DIR         0x00000002  // DMA Direction
-#define USB_DMACTL3_ENABLE      0x00000001  // DMA Transfer Enable
-#define USB_DMACTL3_EP_S        4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR3 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR3_ADDR_M     0xFFFFFFFC  // DMA Address
-#define USB_DMAADDR3_ADDR_S     2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT3
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT3_COUNT_M   0xFFFFFFFC  // DMA Count
-#define USB_DMACOUNT3_COUNT_S   2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL4 register.
-//
-//*****************************************************************************
-#define USB_DMACTL4_BRSTM_M     0x00000600  // Burst Mode
-#define USB_DMACTL4_BRSTM_ANY   0x00000000  // Bursts of unspecified length
-#define USB_DMACTL4_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
-#define USB_DMACTL4_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
-                                            // length
-#define USB_DMACTL4_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
-                                            // unspecified length
-#define USB_DMACTL4_ERR         0x00000100  // Bus Error Bit
-#define USB_DMACTL4_EP_M        0x000000F0  // Endpoint number
-#define USB_DMACTL4_IE          0x00000008  // DMA Interrupt Enable
-#define USB_DMACTL4_MODE        0x00000004  // DMA Transfer Mode
-#define USB_DMACTL4_DIR         0x00000002  // DMA Direction
-#define USB_DMACTL4_ENABLE      0x00000001  // DMA Transfer Enable
-#define USB_DMACTL4_EP_S        4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR4 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR4_ADDR_M     0xFFFFFFFC  // DMA Address
-#define USB_DMAADDR4_ADDR_S     2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT4
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT4_COUNT_M   0xFFFFFFFC  // DMA Count
-#define USB_DMACOUNT4_COUNT_S   2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL5 register.
-//
-//*****************************************************************************
-#define USB_DMACTL5_BRSTM_M     0x00000600  // Burst Mode
-#define USB_DMACTL5_BRSTM_ANY   0x00000000  // Bursts of unspecified length
-#define USB_DMACTL5_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
-#define USB_DMACTL5_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
-                                            // length
-#define USB_DMACTL5_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
-                                            // unspecified length
-#define USB_DMACTL5_ERR         0x00000100  // Bus Error Bit
-#define USB_DMACTL5_EP_M        0x000000F0  // Endpoint number
-#define USB_DMACTL5_IE          0x00000008  // DMA Interrupt Enable
-#define USB_DMACTL5_MODE        0x00000004  // DMA Transfer Mode
-#define USB_DMACTL5_DIR         0x00000002  // DMA Direction
-#define USB_DMACTL5_ENABLE      0x00000001  // DMA Transfer Enable
-#define USB_DMACTL5_EP_S        4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR5 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR5_ADDR_M     0xFFFFFFFC  // DMA Address
-#define USB_DMAADDR5_ADDR_S     2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT5
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT5_COUNT_M   0xFFFFFFFC  // DMA Count
-#define USB_DMACOUNT5_COUNT_S   2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL6 register.
-//
-//*****************************************************************************
-#define USB_DMACTL6_BRSTM_M     0x00000600  // Burst Mode
-#define USB_DMACTL6_BRSTM_ANY   0x00000000  // Bursts of unspecified length
-#define USB_DMACTL6_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
-#define USB_DMACTL6_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
-                                            // length
-#define USB_DMACTL6_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
-                                            // unspecified length
-#define USB_DMACTL6_ERR         0x00000100  // Bus Error Bit
-#define USB_DMACTL6_EP_M        0x000000F0  // Endpoint number
-#define USB_DMACTL6_IE          0x00000008  // DMA Interrupt Enable
-#define USB_DMACTL6_MODE        0x00000004  // DMA Transfer Mode
-#define USB_DMACTL6_DIR         0x00000002  // DMA Direction
-#define USB_DMACTL6_ENABLE      0x00000001  // DMA Transfer Enable
-#define USB_DMACTL6_EP_S        4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR6 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR6_ADDR_M     0xFFFFFFFC  // DMA Address
-#define USB_DMAADDR6_ADDR_S     2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT6
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT6_COUNT_M   0xFFFFFFFC  // DMA Count
-#define USB_DMACOUNT6_COUNT_S   2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL7 register.
-//
-//*****************************************************************************
-#define USB_DMACTL7_BRSTM_M     0x00000600  // Burst Mode
-#define USB_DMACTL7_BRSTM_ANY   0x00000000  // Bursts of unspecified length
-#define USB_DMACTL7_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
-#define USB_DMACTL7_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
-                                            // length
-#define USB_DMACTL7_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
-                                            // unspecified length
-#define USB_DMACTL7_ERR         0x00000100  // Bus Error Bit
-#define USB_DMACTL7_EP_M        0x000000F0  // Endpoint number
-#define USB_DMACTL7_IE          0x00000008  // DMA Interrupt Enable
-#define USB_DMACTL7_MODE        0x00000004  // DMA Transfer Mode
-#define USB_DMACTL7_DIR         0x00000002  // DMA Direction
-#define USB_DMACTL7_ENABLE      0x00000001  // DMA Transfer Enable
-#define USB_DMACTL7_EP_S        4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR7 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR7_ADDR_M     0xFFFFFFFC  // DMA Address
-#define USB_DMAADDR7_ADDR_S     2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT7
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT7_COUNT_M   0xFFFFFFFC  // DMA Count
-#define USB_DMACOUNT7_COUNT_S   2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT1_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT2_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT3_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT4_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT5_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT6_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT7_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
-                                            // Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
-                                            // Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CTO register.
-//
-//*****************************************************************************
-#define USB_CTO_CCTV_M          0x0000FFFF  // Configurable Chirp Timeout Value
-#define USB_CTO_CCTV_S          0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_HHSRTN register.
-//
-//*****************************************************************************
-#define USB_HHSRTN_HHSRTN_M     0x0000FFFF  // HIgh Speed to UTM Operating
+#define MUSB_HHSRTN_HHSRTN_M     0xFFFF  // HIgh Speed to UTM Operating
                                             // Delay
-#define USB_HHSRTN_HHSRTN_S     0
+#define MUSB_HHSRTN_HHSRTN_S     0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_HSBT register.
+// The following are defines for the bit fields in the MUSB_O_HSBT register.
 //
 //*****************************************************************************
-#define USB_HSBT_HSBT_M         0x0000000F  // High Speed Timeout Adder
-#define USB_HSBT_HSBT_S         0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMATTR register.
-//
-//*****************************************************************************
-#define USB_LPMATTR_ENDPT_M     0x0000F000  // Endpoint
-#define USB_LPMATTR_RMTWAK      0x00000100  // Remote Wake
-#define USB_LPMATTR_HIRD_M      0x000000F0  // Host Initiated Resume Duration
-#define USB_LPMATTR_LS_M        0x0000000F  // Link State
-#define USB_LPMATTR_LS_L1       0x00000001  // Sleep State (L1)
-#define USB_LPMATTR_ENDPT_S     12
-#define USB_LPMATTR_HIRD_S      4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMCNTRL register.
-//
-//*****************************************************************************
-#define USB_LPMCNTRL_NAK        0x00000010  // LPM NAK
-#define USB_LPMCNTRL_EN_M       0x0000000C  // LPM Enable
-#define USB_LPMCNTRL_EN_NONE    0x00000000  // LPM and Extended transactions
-                                            // are not supported. In this case,
-                                            // the USB does not respond to LPM
-                                            // transactions and LPM
-                                            // transactions cause a timeout
-#define USB_LPMCNTRL_EN_EXT     0x00000004  // LPM is not supported but
-                                            // extended transactions are
-                                            // supported. In this case, the USB
-                                            // does respond to an LPM
-                                            // transaction with a STALL
-#define USB_LPMCNTRL_EN_LPMEXT  0x0000000C  // The USB supports LPM extended
-                                            // transactions. In this case, the
-                                            // USB responds with a NYET or an
-                                            // ACK as determined by the value
-                                            // of TXLPM and other conditions
-#define USB_LPMCNTRL_RES        0x00000002  // LPM Resume
-#define USB_LPMCNTRL_TXLPM      0x00000001  // Transmit LPM Transaction Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMIM register.
-//
-//*****************************************************************************
-#define USB_LPMIM_ERR           0x00000020  // LPM Error Interrupt Mask
-#define USB_LPMIM_RES           0x00000010  // LPM Resume Interrupt Mask
-#define USB_LPMIM_NC            0x00000008  // LPM NC Interrupt Mask
-#define USB_LPMIM_ACK           0x00000004  // LPM ACK Interrupt Mask
-#define USB_LPMIM_NY            0x00000002  // LPM NY Interrupt Mask
-#define USB_LPMIM_STALL         0x00000001  // LPM STALL Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMRIS register.
-//
-//*****************************************************************************
-#define USB_LPMRIS_ERR          0x00000020  // LPM Interrupt Status
-#define USB_LPMRIS_RES          0x00000010  // LPM Resume Interrupt Status
-#define USB_LPMRIS_NC           0x00000008  // LPM NC Interrupt Status
-#define USB_LPMRIS_ACK          0x00000004  // LPM ACK Interrupt Status
-#define USB_LPMRIS_NY           0x00000002  // LPM NY Interrupt Status
-#define USB_LPMRIS_LPMST        0x00000001  // LPM STALL Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMFADDR register.
-//
-//*****************************************************************************
-#define USB_LPMFADDR_ADDR_M     0x0000007F  // LPM Function Address
-#define USB_LPMFADDR_ADDR_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPC register.
-//
-//*****************************************************************************
-#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
-#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
-#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
-#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
-#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
-#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
-#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
-#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
-#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
-#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
-                                            // Configuration
-#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
-#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
-#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
-                                            // (OTG only)
-#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
-                                            // (OTG only)
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCRIS register.
-//
-//*****************************************************************************
-#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCIM register.
-//
-//*****************************************************************************
-#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCISC register.
-//
-//*****************************************************************************
-#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
-                                            // and Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRRIS register.
-//
-//*****************************************************************************
-#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRIM register.
-//
-//*****************************************************************************
-#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRISC register.
-//
-//*****************************************************************************
-#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
-                                            // Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_GPCS register.
-//
-//*****************************************************************************
-#define USB_GPCS_DEVMOD_M       0x00000007  // Device Mode
-#define USB_GPCS_DEVMOD_OTG     0x00000000  // Use USB0VBUS and USB0ID pin
-#define USB_GPCS_DEVMOD_HOST    0x00000002  // Force USB0VBUS and USB0ID low
-#define USB_GPCS_DEVMOD_DEV     0x00000003  // Force USB0VBUS and USB0ID high
-#define USB_GPCS_DEVMOD_HOSTVBUS                                              \
-                                0x00000004  // Use USB0VBUS and force USB0ID
-                                            // low
-#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005  // Use USB0VBUS and force USB0ID
-                                            // high
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDC register.
-//
-//*****************************************************************************
-#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCRIS register.
-//
-//*****************************************************************************
-#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCIM register.
-//
-//*****************************************************************************
-#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCISC register.
-//
-//*****************************************************************************
-#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
-                                            // Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_PP register.
-//
-//*****************************************************************************
-#define USB_PP_ECNT_M           0x0000FF00  // Endpoint Count
-#define USB_PP_USB_M            0x000000C0  // USB Capability
-#define USB_PP_USB_DEVICE       0x00000040  // DEVICE
-#define USB_PP_USB_HOSTDEVICE   0x00000080  // HOST
-#define USB_PP_USB_OTG          0x000000C0  // OTG
-#define USB_PP_ULPI             0x00000020  // ULPI Present
-#define USB_PP_PHY              0x00000010  // PHY Present
-#define USB_PP_TYPE_M           0x0000000F  // Controller Type
-#define USB_PP_TYPE_0           0x00000000  // The first-generation USB
-                                            // controller
-#define USB_PP_TYPE_1           0x00000001  // The second-generation USB
-                                            // controller revision
-#define USB_PP_ECNT_S           8
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_PC register.
-//
-//*****************************************************************************
-#define USB_PC_ULPIEN           0x00010000  // ULPI Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CC register.
-//
-//*****************************************************************************
-#define USB_CC_CLKEN            0x00000200  // USB Clock Enable
-#define USB_CC_CSD              0x00000100  // Clock Source/Direction
-#define USB_CC_CLKDIV_M         0x0000000F  // PLL Clock Divisor
-#define USB_CC_CLKDIV_S         0
+#define MUSB_HSBT_HSBT_M         0x000F  // High Speed Timeout Adder
+#define MUSB_HSBT_HSBT_S         0
 
 #ifdef __cplusplus
  }
diff --git a/src/portable/microchip/pic/README.md b/src/portable/microchip/pic/README.md
new file mode 100644
index 000000000..7ba6a4a96
--- /dev/null
+++ b/src/portable/microchip/pic/README.md
@@ -0,0 +1,51 @@
+# Microchip PIC Chipidea FS Driver
+
+This driver adds support for Microchip PIC microcontrollers with full-speed Chipidea USB peripheral to the TinyUSB stack. It supports the following families:
+
+- PIC32MX (untested)
+- PIC32MM
+- PIC32MK (untested)
+- PIC24FJ
+- PIC24EP (untested)
+- dsPIC33EP (untested)
+
+Currently only the device mode is supported.
+
+
+## Important Notes
+
+### Handling of shared VBUS & GPIO pin
+
+Some PICs have the USB VBUS pin bonded with a GPIO pin in the chip package. This driver does **NOT** handle the potential conflict between the VBUS and GPIO functionalities.
+
+Developers must ensure that the GPIO pin is tristated when the VBUS pin is managed by the USB peripheral in order to prevent damaging the chip.
+
+This design choice allows developers the flexibility to use the GPIO functionality for controlling VBUS in device mode if desired.
+
+
+## TODO
+
+### Handle USB remote wakeup timing correctly
+
+The Chipidea FS IP doesn't handle the RESUME signal automatically and it must be managed in software. It needs to be asserted for exactly 10ms, and this is impossible to do without per-device support due to BSP differences. For now, a simple for-based loop is used.
+
+### 8-bit PIC support
+
+The 8-bit PICs also uses the Chipidea FS IP. Technically it's possible to support them as well.
+
+Possible difficulties:
+- Memory size constraints (1KB/8KB ballpark)
+- A third BDT layout (now we have two)
+- Different compiler-specific directives
+- Compiler bugs if you use SDCC
+
+
+## Author
+[ReimuNotMoe](https://github.com/ReimuNotMoe) at SudoMaker, Ltd.
+
+
+## Credits
+
+This driver is based on:
+- Microchip's USB driver (usb_device.c)
+- TinyUSB's NXP KHCI driver (dcd_khci.c)
diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c
index 6cf0e6285..b4a698199 100644
--- a/src/portable/microchip/pic/dcd_pic.c
+++ b/src/portable/microchip/pic/dcd_pic.c
@@ -1,8 +1,11 @@
-/* 
+/*
  * The MIT License (MIT)
  *
- * Copyright (c) 2020 Koji Kitayama
- * Copyright (c) 2022 Reimu NotMoe <reimu@sudomaker.com>
+ * Copyright (c) 2022-2024 SudoMaker, Ltd.
+ * Author: Mike Yang (Reimu NotMoe) <reimu@sudomaker.com>
+ *
+ * Based on usb_device.c - Copyright (c) 2015 Microchip Technology Inc.
+ * Based on dcd_khci.c   - Copyright (c) 2020 Koji Kitayama
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -189,7 +192,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) volatile static dcd_data_t _dcd;
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) volatile static dcd_data_t _dcd;
 
 #if TU_PIC_INT_SIZE == 4
 TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
@@ -313,12 +316,23 @@ static void prepare_next_setup_packet(uint8_t rhport)
 {
   const unsigned out_odd = _dcd.endpoint[0][0].odd;
   const unsigned in_odd  = _dcd.endpoint[0][1].odd;
-  TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, );
+
+  // Abandon any previous control transfers that might have been using EP0.
+  // Ordinarily, nothing actually needs abandoning, since the previous control
+  // transfer would have completed successfully prior to the host sending the
+  // next SETUP packet. However, in a timeout error case, or after an EP0
+  // STALL event, one or more UOWN bits might still be set. If so, we should
+  // clear the UOWN bits, so the EP0 IN/OUT endpoints are in a known inactive
+  // state, ready for re-arming by the `dcd_edpt_xfer' function that will be
+  // called next.
 
   _dcd.bdt[0][0][out_odd].data     = 0;
+  _dcd.bdt[0][0][out_odd].own      = 0;
   _dcd.bdt[0][0][out_odd ^ 1].data = 1;
   _dcd.bdt[0][1][in_odd].data      = 1;
+  _dcd.bdt[0][1][in_odd].own       = 0;
   _dcd.bdt[0][1][in_odd ^ 1].data  = 0;
+  _dcd.bdt[0][1][in_odd ^ 1].own   = 0;
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
           _dcd.setup_packet, sizeof(_dcd.setup_packet));
 }
@@ -470,23 +484,22 @@ static void process_bus_resume(uint8_t rhport)
 /*------------------------------------------------------------------*/
 /* Device API
  *------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
   intr_disable(rhport);
   intr_clear(rhport);
 
-#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
-  TRISBbits.TRISB6 = 1;
-#endif
-
   tu_memclr(&_dcd, sizeof(_dcd));
 
 #if TU_PIC_INT_SIZE == 4
+  // The USBBUSY bit is present on PIC32s and we're required to check it
+  // prior to powering on the USB peripheral (see DS61126F page 27)
+  while (U1PWRCbits.USBBUSY);
   U1PWRCSET = _U1PWRC_USBPWR_MASK;
 #else
   U1PWRCbits.USBPWR = 1;
 #endif
-  
+
 #if TU_PIC_INT_SIZE == 4
   uint32_t bdt_phys = KVA_TO_PA((uintptr_t)_dcd.bdt);
 
@@ -502,6 +515,20 @@ void dcd_init(uint8_t rhport)
   U1IE = _U1IE_URSTIE_MASK;
 
   dcd_connect(rhport);
+  return true;
+}
+
+bool dcd_deinit(uint8_t rhport)
+{
+  U1CON = 0;
+  U1IE = 0;
+  U1OTGIE = 0;
+#if TU_PIC_INT_SIZE == 4
+  U1PWRCCLR = _U1PWRC_USUSPEND_MASK | _U1PWRC_USBPWR_MASK;
+#else
+  U1PWRC &= ~(_U1PWRC_USUSPEND_MASK | _U1PWRC_USBPWR_MASK);
+#endif
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -528,8 +555,25 @@ void dcd_remote_wakeup(uint8_t rhport)
 #else
   U1CONbits.RESUME = 1;
 #endif
-  unsigned cnt = 25000000 / 1000;
+
+  // FIXME: Assert RESUME signal correctly, requires device-specific handling
+  // For now we use a hardcoded cycle-based delay which attempts to delay 10ms
+  // at the most common CPU frequencies. On PIC32s we assume the loop body
+  // takes 3 cycles. On 16-bit PICs we assume the XC16 compiler is in use and
+  // use its `__delay_ms' function.
+
+#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
+  uint32_t cnt = 24000000 / 1000 / 3;
   while (cnt--) asm volatile("nop");
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX
+  uint32_t cnt = 40000000 / 1000 / 3;
+  while (cnt--) asm volatile("nop");
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
+  uint32_t cnt = 120000000 / 1000 / 3;
+  while (cnt--) asm volatile("nop");
+#else
+  __delay_ms(10);
+#endif
 
 #if TU_PIC_INT_SIZE == 4
   U1CONCLR = _U1CON_RESUME_MASK;
@@ -737,8 +781,11 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 //--------------------------------------------------------------------+
 void dcd_int_handler(uint8_t rhport)
 {
-  uint32_t is  = U1IR;
-  uint32_t msk = U1IE;
+  uint32_t is, msk;
+
+  // Part 1 - "USB interrupts"
+  is = U1IR;
+  msk = U1IE;
 
   U1IR = is & ~msk;
   is &= msk;
@@ -746,7 +793,7 @@ void dcd_int_handler(uint8_t rhport)
   if (is & _U1IR_UERRIF_MASK) {
     uint32_t es = U1EIR;
     U1EIR = es;
-    U1IR   = is; /* discard any pending events */
+    U1IR = is; /* discard any pending events */
   }
 
   if (is & _U1IR_URSTIF_MASK) {
@@ -757,29 +804,66 @@ void dcd_int_handler(uint8_t rhport)
   if (is & _U1IR_IDLEIF_MASK) {
     // Note Host usually has extra delay after bus reset (without SOF), which could falsely
     // detected as Sleep event. Though usbd has debouncing logic so we are good
+
+    /*
+     * NOTE: Do not clear U1OTGIRbits.ACTVIF here!
+     * Reason:
+     * ACTVIF is only generated once an IDLEIF has been generated.
+     * This is a 1:1 ratio interrupt generation.
+     * For every IDLEIF, there will be only one ACTVIF regardless of
+     * the number of subsequent bus transitions.
+     *
+     * If the ACTIF is cleared here, a problem could occur when:
+     * [       IDLE       ][bus activity ->
+     * <--- 3 ms ----->     ^
+     *                ^     ACTVIF=1
+     *                IDLEIF=1
+     *  #           #           #           #   (#=Program polling flags)
+     *                          ^
+     *                          This polling loop will see both
+     *                          IDLEIF=1 and ACTVIF=1.
+     *                          However, the program services IDLEIF first
+     *                          because ACTIVIE=0.
+     *                          If this routine clears the only ACTIVIF,
+     *                          then it can never get out of the suspend
+     *                          mode.
+     */
+    U1OTGIESET = _U1OTGIE_ACTVIE_MASK;
     U1IR = _U1IR_IDLEIF_MASK;
     process_bus_sleep(rhport);
   }
 
-  if (is & _U1IR_RESUMEIF_MASK) {
-    U1IR = _U1IR_RESUMEIF_MASK;
-    process_bus_resume(rhport);
-  }
-
   if (is & _U1IR_SOFIF_MASK) {
     U1IR = _U1IR_SOFIF_MASK;
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
 
   if (is & _U1IR_STALLIF_MASK) {
-    U1IR = _U1IR_STALLIF_MASK;
     process_stall(rhport);
+    U1IR = _U1IR_STALLIF_MASK;
   }
 
   if (is & _U1IR_TRNIF_MASK) {
     process_tokdne(rhport);
   }
 
+  // Part 2 - "USB OTG interrupts"
+  is = U1OTGIR;
+  msk = U1OTGIE;
+
+  U1OTGIR = is & ~msk;
+  is &= msk;
+
+  if (is & _U1OTGIR_ACTVIF_MASK) {
+#if TU_PIC_INT_SIZE == 4
+    U1OTGIECLR = _U1OTGIE_ACTVIE_MASK;
+#else
+    U1OTGIE &= ~_U1OTGIE_ACTVIE_MASK;
+#endif
+    U1OTGIR = _U1OTGIR_ACTVIF_MASK;
+    process_bus_resume(rhport);
+  }
+
   intr_clear(rhport);
 }
 
diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c
index 9ad755670..8709baf67 100644
--- a/src/portable/microchip/pic32mz/dcd_pic32mz.c
+++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c
@@ -120,8 +120,8 @@ static ep0_stage_t ep0_get_stage(void)
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
   // Disable endpoint interrupts for now
   USB_REGS->INTRRXEbits.w = 0;
   USB_REGS->INTRTXEbits.w = 0;
@@ -129,6 +129,7 @@ void dcd_init(uint8_t rhport)
   USB_REGS->INTRUSBEbits.w = 7;
 
   dcd_connect(rhport);
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/microchip/pic32mz/usbhs_registers.h b/src/portable/microchip/pic32mz/usbhs_registers.h
index 757e3f083..03fe78bbd 100644
--- a/src/portable/microchip/pic32mz/usbhs_registers.h
+++ b/src/portable/microchip/pic32mz/usbhs_registers.h
@@ -21,16 +21,16 @@
 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
 *******************************************************************************/
 /*******************************************************************************
-  USBHS Peripheral Library Register Defintions 
+  USBHS Peripheral Library Register Definitions
 
   File Name:
     usbhs_registers.h
 
   Summary:
-    USBHS PLIB Register Defintions
+    USBHS PLIB Register Definitions
 
   Description:
-    This file contains the constants and defintions which are required by the
+    This file contains the constants and definitions which are required by the
     the USBHS library.
 *******************************************************************************/
 
@@ -50,16 +50,16 @@
 #define USBHS_REG_INTRRX        0x004
 #define USBHS_REG_INTRTXE       0x006
 #define USBHS_REG_INTRRXE       0x008
-#define USBHS_REG_INTRUSB       0x00A 
-#define USBHS_REG_INTRUSBE      0x00B 
+#define USBHS_REG_INTRUSB       0x00A
+#define USBHS_REG_INTRUSBE      0x00B
 #define USBHS_REG_FRAME         0x00C
 #define USBHS_REG_INDEX         0x00E
 #define USBHS_REG_TESTMODE      0x00F
 
 /*******************************************************
- * Endpoint Control Status Registers (CSR). These values 
+ * Endpoint Control Status Registers (CSR). These values
  * should be added to either the 0x10 to access the
- * register through Indexed CSR. To access the actual 
+ * register through Indexed CSR. To access the actual
  * CSR, see ahead in this header file.
  ******************************************************/
 
@@ -99,20 +99,20 @@
 #define USBHS_EP_DEVICE_RX_SEND_STALL 0x20
 
 /* FADDR - Device Function Address */
-typedef union 
+typedef union
 {
-    struct __attribute__((packed)) 
+    struct __attribute__((packed))
     {
         unsigned FUNC:7;
         unsigned :1;
     };
 
-    uint8_t w;  
+    uint8_t w;
 
 } __USBHS_FADDR_t;
 
 /* POWER - Control Resume and Suspend signalling */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -126,14 +126,14 @@ typedef union
         unsigned ISOUPD:1;
     };
     struct
-    {   
+    {
         uint8_t w;
     };
 
 } __USBHS_POWER_t;
 
 /* INTRTXE - Transmit endpoint interrupt enable */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -155,7 +155,7 @@ typedef union
 } __USBHS_INTRTXE_t;
 
 /* INTRRXE - Receive endpoint interrupt enable */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -198,7 +198,7 @@ typedef union
 } __USBHS_INTRUSBE_t;
 
 /* FRAME - Frame number */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -213,7 +213,7 @@ typedef union
 } __USBHS_FRAME_t;
 
 /* INDEX - Endpoint index */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -228,7 +228,7 @@ typedef union
 } __USBHS_INDEX_t;
 
 /* TESTMODE - Test mode register */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -248,7 +248,7 @@ typedef union
 
 } __USBHS_TESTMODE_t;
 
-/* COUNT0 - Indicates the amount of data received in endpoint 0 */ 
+/* COUNT0 - Indicates the amount of data received in endpoint 0 */
 typedef union
 {
     struct __attribute__((packed))
@@ -627,7 +627,7 @@ typedef union
     };
     uint16_t w;
 
-} __USBHS_TXMAXP_t;  
+} __USBHS_TXMAXP_t;
 
 /* TXFIFOSZ - Size of the transmit endpoint FIFO */
 typedef struct __attribute__((packed))
@@ -781,7 +781,7 @@ typedef union
 
 } __USBHS_DMACNTL_t;
 
-/* Endpoint Control and Status Register Set */    
+/* Endpoint Control and Status Register Set */
 typedef struct __attribute__((packed))
 {
     volatile __USBHS_TXMAXP_t TXMAXPbits;
@@ -906,7 +906,7 @@ typedef struct __attribute__((aligned(4),packed))
 
     volatile __USBHS_TXFIFOADD_t   TXFIFOADDbits;
     volatile __USBHS_RXFIFOADD_t   RXFIFOADDbits;
-    
+
     volatile uint32_t   VCONTROL;
     volatile uint16_t   HWVERS;
     volatile uint8_t    padding1[10];
@@ -923,7 +923,7 @@ typedef struct __attribute__((aligned(4),packed))
     volatile __USBHS_TARGET_ADDR_t  TADDR[16];
     volatile __USBHS_EPCSR_t        EPCSR[16];
     volatile uint32_t               DMA_INTR;
-    volatile __USBHS_DMA_CHANNEL_t  DMA_CHANNEL[8]; 
+    volatile __USBHS_DMA_CHANNEL_t  DMA_CHANNEL[8];
     volatile uint32_t               RQPKTXOUNT[16];
 
 } usbhs_registers_t;
diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 976d3dfd0..357aa1549 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -78,9 +78,9 @@ static void bus_reset(void)
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
-void dcd_init (uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   // Reset to get in a clean state.
   USB->DEVICE.CTRLA.bit.SWRST = true;
@@ -102,6 +102,8 @@ void dcd_init (uint8_t rhport)
 
   USB->DEVICE.INTFLAG.reg |= USB->DEVICE.INTFLAG.reg; // clear pending
   USB->DEVICE.INTENSET.reg = /* USB_DEVICE_INTENSET_SOF | */ USB_DEVICE_INTENSET_EORST;
+
+  return true;
 }
 
 #if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X
@@ -183,9 +185,12 @@ void dcd_connect(uint8_t rhport)
 void dcd_sof_enable(uint8_t rhport, bool en)
 {
   (void) rhport;
-  (void) en;
 
-  // TODO implement later
+  if (en) {
+    USB->DEVICE.INTENSET.bit.SOF = 1;
+  } else {
+    USB->DEVICE.INTENCLR.bit.SOF = 1;
+  }
 }
 
 /*------------------------------------------------------------------*/
@@ -330,7 +335,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 //--------------------------------------------------------------------+
 // Interrupt Handler
 //--------------------------------------------------------------------+
-void maybe_transfer_complete(void) {
+static void maybe_transfer_complete(void) {
   uint32_t epints = USB->DEVICE.EPINTSMRY.reg;
 
   for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) {
@@ -374,7 +379,9 @@ void dcd_int_handler (uint8_t rhport)
   if ( int_status & USB_DEVICE_INTFLAG_SOF )
   {
     USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
-    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+    const uint32_t frame = USB->DEVICE.FNUM.bit.FNUM;
+    dcd_event_sof(0, frame, true);
+    //dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
   }
 
   // SAMD doesn't distinguish between Suspend and Disconnect state.
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
index 814e680fb..a5c768839 100644
--- a/src/portable/microchip/samg/dcd_samg.c
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -52,37 +52,31 @@ typedef struct
 // Endpoint 0-5, each can only be either OUT or In
 xfer_desc_t _dcd_xfer[EP_COUNT];
 
-void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize)
-{
+TU_ATTR_ALWAYS_INLINE static inline void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize) {
   xfer->epsize = epsize;
 }
 
-void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes)
-{
+TU_ATTR_ALWAYS_INLINE static inline void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes) {
   xfer->buffer     = buffer;
   // xfer->ff         = NULL; // TODO support dcd_edpt_xfer_fifo API
   xfer->total_len  = total_bytes;
   xfer->actual_len = 0;
 }
 
-void xfer_end(xfer_desc_t* xfer)
-{
+TU_ATTR_ALWAYS_INLINE static inline void xfer_end(xfer_desc_t* xfer) {
   xfer->buffer     = NULL;
   // xfer->ff         = NULL; // TODO support dcd_edpt_xfer_fifo API
   xfer->total_len  = 0;
   xfer->actual_len = 0;
 }
 
-uint16_t xfer_packet_len(xfer_desc_t* xfer)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint16_t xfer_packet_len(xfer_desc_t* xfer) {
   // also cover zero-length packet
   return tu_min16(xfer->total_len - xfer->actual_len, xfer->epsize);
 }
 
-void xfer_packet_done(xfer_desc_t* xfer)
-{
+TU_ATTR_ALWAYS_INLINE static inline void xfer_packet_done(xfer_desc_t* xfer) {
   uint16_t const xact_len = xfer_packet_len(xfer);
-
   xfer->buffer += xact_len;
   xfer->actual_len += xact_len;
 }
@@ -90,19 +84,15 @@ void xfer_packet_done(xfer_desc_t* xfer)
 //------------- Transaction helpers -------------//
 
 // Write data to EP FIFO, return number of written bytes
-static void xact_ep_write(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
-{
-  for(uint16_t i=0; i<xact_len; i++)
-  {
+static void xact_ep_write(uint8_t epnum, uint8_t* buffer, uint16_t xact_len) {
+  for(uint16_t i=0; i<xact_len; i++) {
     UDP->UDP_FDR[epnum] = (uint32_t) buffer[i];
   }
 }
 
 // Read data from EP FIFO
-static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
-{
-  for(uint16_t i=0; i<xact_len; i++)
-  {
+static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len) {
+  for(uint16_t i=0; i<xact_len; i++) {
     buffer[i] = (uint8_t) UDP->UDP_FDR[epnum];
   }
 }
@@ -112,24 +102,24 @@ static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
 #define CSR_NO_EFFECT_1_ALL (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 | UDP_CSR_STALLSENT | UDP_CSR_RXSETUP | UDP_CSR_TXCOMP)
 
 // Per Specs: CSR need synchronization each write
-static inline void csr_write(uint8_t epnum, uint32_t value)
-{
+TU_ATTR_ALWAYS_INLINE static inline void csr_write(uint8_t epnum, uint32_t value) {
   uint32_t const csr = value;
   UDP->UDP_CSR[epnum] = csr;
 
   volatile uint32_t nop_count;
-  for (nop_count = 0; nop_count < 20; nop_count ++) __NOP();
+  for (nop_count = 0; nop_count < 20; nop_count ++) {
+    __NOP();
+  }
 }
 
 // Per Specs: CSR need synchronization each write
-static inline void csr_set(uint8_t epnum, uint32_t mask)
+TU_ATTR_ALWAYS_INLINE static inline void csr_set(uint8_t epnum, uint32_t mask)
 {
   csr_write(epnum, UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL | mask);
 }
 
 // Per Specs: CSR need synchronization each write
-static inline void csr_clear(uint8_t epnum, uint32_t mask)
-{
+TU_ATTR_ALWAYS_INLINE static inline void csr_clear(uint8_t epnum, uint32_t mask) {
   csr_write(epnum, (UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL) & ~mask);
 }
 
@@ -155,10 +145,13 @@ static void bus_reset(void)
 }
 
 // Initialize controller to device mode
-void dcd_init (uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rhport;
+  (void) rh_init;
+
   tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
   dcd_connect(rhport);
+  return true;
 }
 
 // Enable device interrupt
@@ -277,6 +270,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   return true;
 }
 
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport; (void) ep_addr;
+  // TODO implement dcd_edpt_close()
+}
+
 void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/portable/microchip/samx7x/common_usb_regs.h b/src/portable/microchip/samx7x/common_usb_regs.h
index d232f0bcb..db4a81e0e 100644
--- a/src/portable/microchip/samx7x/common_usb_regs.h
+++ b/src/portable/microchip/samx7x/common_usb_regs.h
@@ -2007,7 +2007,7 @@
 
 /** \brief DEVDMA hardware registers */
 typedef struct
-{  
+{
   __IO uint32_t DEVDMANXTDSC; /**< (DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */
   __IO uint32_t DEVDMAADDRESS; /**< (DEVDMA Offset: 0x04) Device DMA Channel Address Register */
   __IO uint32_t DEVDMACONTROL; /**< (DEVDMA Offset: 0x08) Device DMA Channel Control Register */
@@ -2016,7 +2016,7 @@ typedef struct
 
 /** \brief HSTDMA hardware registers */
 typedef struct
-{  
+{
   __IO uint32_t HSTDMANXTDSC; /**< (HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */
   __IO uint32_t HSTDMAADDRESS; /**< (HSTDMA Offset: 0x04) Host DMA Channel Address Register */
   __IO uint32_t HSTDMACONTROL; /**< (HSTDMA Offset: 0x08) Host DMA Channel Control Register */
@@ -2025,7 +2025,7 @@ typedef struct
 
 /** \brief USBHS hardware registers */
 typedef struct
-{  
+{
   __IO uint32_t DEVCTRL;  /**< (USBHS Offset: 0x00) Device General Control Register */
   __I  uint32_t DEVISR;   /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */
   __O  uint32_t DEVICR;   /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 7507c0f69..8aec1568d 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -42,7 +42,7 @@
 #  define USE_SOF         0
 #endif
 
-// Dual bank can imporve performance, but need 2 times bigger packet buffer
+// Dual bank can improve performance, but need 2 times bigger packet buffer
 // As SAM7x has only 4KB packet buffer, use with caution !
 // Enable in FS mode as packets are smaller
 #ifndef USE_DUAL_BANK
@@ -77,7 +77,7 @@ static tusb_speed_t get_speed(void);
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
 
 // DMA descriptors shouldn't be placed in ITCM !
-CFG_TUSB_MEM_SECTION static dma_desc_t dma_desc[6];
+CFG_TUD_MEM_SECTION static dma_desc_t dma_desc[6];
 
 static xfer_ctl_t xfer_status[EP_MAX];
 
@@ -104,9 +104,10 @@ TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, in
 //------------------------------------------------------------------
 
 // Initialize controller to device mode
-void dcd_init (uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
   dcd_connect(rhport);
+  return true;
 }
 
 // Enable device interrupt
@@ -241,7 +242,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
     if (int_status & DEVEPTISR_RXOUTI)
     {
       uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
-      
+
       if (count && xfer->total_len)
       {
         uint16_t remain = xfer->total_len - xfer->queued_len;
@@ -252,7 +253,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         if (xfer->buffer)
         {
           memcpy(xfer->buffer + xfer->queued_len, ptr, count);
-        } else 
+        } else
         {
           tu_fifo_write_n(xfer->fifo, ptr, count);
         }
@@ -281,7 +282,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete
         dcd_transmit_packet(xfer, 0);
-      } else 
+      } else
       {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
@@ -292,7 +293,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         }
       }
     }
-  } else 
+  } else
   {
     if (int_status & DEVEPTISR_RXOUTI)
     {
@@ -333,7 +334,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete
         dcd_transmit_packet(xfer, ep_ix);
-      } else 
+      } else
       {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
@@ -359,7 +360,7 @@ static void dcd_dma_handler(uint8_t ep_ix)
   if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR)
   {
     dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
-  } else 
+  } else
   {
     dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
   }
@@ -507,12 +508,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
       // Enable Endpoint 0 Interrupts
       USB_REG->DEVIER = DEVIER_PEP_0;
       return true;
-    } else 
+    } else
     {
       // Endpoint configuration is not successful
       return false;
     }
-  } else 
+  } else
   {
     // Enable the endpoint
     USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos);
@@ -544,7 +545,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     {
       USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos);
       return true;
-    } else 
+    } else
     {
       // Endpoint configuration is not successful
       return false;
@@ -583,7 +584,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
     {
       memcpy(ptr, xfer->buffer + xfer->queued_len, len);
     }
-    else 
+    else
     {
       tu_fifo_read_n(xfer->fifo, ptr, len);
     }
@@ -595,7 +596,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
   {
     // Control endpoint: clear the interrupt flag to send the data
     USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC;
-  } else 
+  } else
   {
     // Other endpoint types: clear the FIFO control flag to send the data
     USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
@@ -616,7 +617,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
   xfer->fifo = NULL;
-  
+
   if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
     // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
@@ -644,16 +645,16 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     }
     __set_PRIMASK(irq_state);
 
-    // Here a ZLP has been recieved
+    // Here a ZLP has been received
     // and the DMA transfer must be not started.
     // It is the end of transfer
     return false;
-  } else 
+  } else
   {
     if (dir == TUSB_DIR_OUT)
     {
       USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
-    } else 
+    } else
     {
       dcd_transmit_packet(xfer,epnum);
     }
@@ -701,20 +702,20 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 
     // Clean invalidate cache of linear part
     CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31);
-    
+
     USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.ptr_lin;
     if (info.len_wrap)
     {
       // Clean invalidate cache of wrapped part
       CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), info.len_wrap + 31);
-      
+
       dma_desc[epnum - 1].next_desc = 0;
       dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
       dma_desc[epnum - 1].chnl_ctrl =
         udd_dma_ctrl_wrap | (info.len_wrap << DEVDMACONTROL_BUFF_LENGTH_Pos);
       // Clean cache of wrapped DMA descriptor
       CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t));
-      
+
       udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST;
       USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
     } else {
@@ -734,7 +735,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     }
     __set_PRIMASK(irq_state);
 
-    // Here a ZLP has been recieved
+    // Here a ZLP has been received
     // and the DMA transfer must be not started.
     // It is the end of transfer
     return false;
@@ -743,7 +744,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     if (dir == TUSB_DIR_OUT)
     {
       USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
-    } else 
+    } else
     {
       dcd_transmit_packet(xfer,epnum);
     }
diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index 39b09db68..1ce3da27e 100644
--- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -110,7 +110,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
 
 TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
 
@@ -245,9 +245,9 @@ static void process_bus_active(uint8_t rhport)
 /*------------------------------------------------------------------*/
 /* Device API
  *------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   tu_memclr(&_dcd, sizeof(_dcd));
   USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >>  8);
@@ -256,6 +256,7 @@ void dcd_init(uint8_t rhport)
 
   dcd_connect(rhport);
   NVIC_ClearPendingIRQ(USB_FS_IRQn);
+  return true;
 }
 #define USB_DEVICE_INTERRUPT_PRIORITY (3U)
 void dcd_int_enable(uint8_t rhport)
@@ -283,7 +284,18 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   /* Response with status first before changing device address */
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
+
+#ifdef __GNUC__ // caused by extra declaration of SystemCoreClock in freeRTOSConfig.h
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
 extern u32 SystemCoreClock;
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index ca37d799f..9e5f5117f 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -29,10 +29,23 @@
 #if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_NRF5X
 
 #include <stdatomic.h>
+
+// Suppress warning caused by nrfx driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wcast-align"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 #include "nrf.h"
-#include "nrf_clock.h"
-#include "nrf_power.h"
-#include "nrfx_usbd_errata.h"
+#include "nrfx_clock.h"
+#include "nrf_erratas.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #include "device/dcd.h"
 
 // TODO remove later
@@ -43,28 +56,46 @@
 #include "mcu/mcu.h"
 #endif
 
+/* Try to detect nrfx version if not configured with CFG_TUD_NRF_NRFX_VERSION
+ * nrfx v1 and v2 are concurrently developed. There is no NRFX_VERSION only MDK VERSION which is as follows:
+ * - v3.0.0: 8.53.1 (conflict with v2.11.0), v3.1.0: 8.55.0 ...
+ * - v2.11.0: 8.53.1, v2.6.0: 8.44.1, v2.5.0: 8.40.2, v2.4.0: 8.37.0, v2.3.0: 8.35.0, v2.2.0: 8.32.1, v2.1.0: 8.30.2, v2.0.0: 8.29.0
+ * - v1.9.0: 8.40.3, v1.8.6: 8.35.0 (conflict with v2.3.0), v1.8.5: 8.32.3, v1.8.4: 8.32.1 (conflict with v2.2.0),
+ *   v1.8.2: 8.32.1 (conflict with v2.2.0), v1.8.1: 8.27.1
+ * Therefore the check for v1 would be:
+ * - MDK < 8.29.0 (v2.0), MDK == 8.32.3, 8.40.3
+ * - in case of conflict User of those version must upgrade to other 1.x version or set CFG_TUD_NRF_NRFX_VERSION
+*/
+#ifndef CFG_TUD_NRF_NRFX_VERSION
+  #define _MDK_VERSION  (10000*MDK_MAJOR_VERSION + 100*MDK_MINOR_VERSION + MDK_MICRO_VERSION)
+
+  #if _MDK_VERSION < 82900 || _MDK_VERSION == 83203 || _MDK_VERSION == 84003
+    // nrfx <= 1.8.1, or 1.8.5 or 1.9.0
+    #define CFG_TUD_NRF_NRFX_VERSION 1
+  #else
+    #define CFG_TUD_NRF_NRFX_VERSION 2
+  #endif
+#endif
+
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
  *------------------------------------------------------------------*/
-enum
-{
+enum {
   // Max allowed by USB specs
-  MAX_PACKET_SIZE   = 64,
+  MAX_PACKET_SIZE = 64,
 
   // Mask of all END event (IN & OUT) for all endpoints. ENDEPIN0-7, ENDEPOUT0-7, ENDISOIN, ENDISOOUT
   EDPT_END_ALL_MASK = (0xff << USBD_INTEN_ENDEPIN0_Pos) | (0xff << USBD_INTEN_ENDEPOUT0_Pos) |
                       USBD_INTENCLR_ENDISOIN_Msk | USBD_INTEN_ENDISOOUT_Msk
 };
 
-enum
-{
-  EP_ISO_NUM   = 8, // Endpoint number is fixed (8) for ISOOUT and ISOIN
+enum {
+  EP_ISO_NUM = 8, // Endpoint number is fixed (8) for ISOOUT and ISOIN
   EP_CBI_COUNT = 8  // Control Bulk Interrupt endpoints count
 };
 
 // Transfer Descriptor
-typedef struct
-{
+typedef struct {
   uint8_t* buffer;
   uint16_t total_len;
   volatile uint16_t actual_len;
@@ -82,120 +113,95 @@ typedef struct
 } xfer_td_t;
 
 // Data for managing dcd
-static struct
-{
+static struct {
   // All 8 endpoints including control IN & OUT (offset 1)
   // +1 for ISO endpoints
   xfer_td_t xfer[EP_CBI_COUNT + 1][2];
 
   // nRF can only carry one DMA at a time, this is used to guard the access to EasyDMA
-  atomic_bool dma_running;
-}_dcd;
+  atomic_flag dma_running;
+
+  // Track whether sof has been manually enabled
+  bool sof_enabled;
+} _dcd;
 
 /*------------------------------------------------------------------*/
 /* Control / Bulk / Interrupt (CBI) Transfer
  *------------------------------------------------------------------*/
 
-// NVIC_GetEnableIRQ is only available in CMSIS v5
-#ifndef NVIC_GetEnableIRQ
-static inline uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif
-
 // check if we are in ISR
-TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void) {
   return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) ? true : false;
 }
 
 // helper to start DMA
-static void start_dma(volatile uint32_t* reg_startep)
-{
+static void start_dma(volatile uint32_t* reg_startep) {
   (*reg_startep) = 1;
-  __ISB(); __DSB();
+  __ISB();
+  __DSB();
 
   // TASKS_EP0STATUS, TASKS_EP0RCVOUT seem to need EasyDMA to be available
   // However these don't trigger any DMA transfer and got ENDED event subsequently
   // Therefore dma_pending is corrected right away
-  if ( (reg_startep == &NRF_USBD->TASKS_EP0STATUS) || (reg_startep == &NRF_USBD->TASKS_EP0RCVOUT) )
-  {
+  if ((reg_startep == &NRF_USBD->TASKS_EP0STATUS) || (reg_startep == &NRF_USBD->TASKS_EP0RCVOUT)) {
     atomic_flag_clear(&_dcd.dma_running);
   }
 }
 
-static void edpt_dma_start(volatile uint32_t* reg_startep)
-{
-  if ( atomic_flag_test_and_set(&_dcd.dma_running) )
-  {
-    usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
-  }else
-  {
+static void edpt_dma_start(volatile uint32_t* reg_startep) {
+  if (atomic_flag_test_and_set(&_dcd.dma_running)) {
+    usbd_defer_func((osal_task_func_t)(uintptr_t ) edpt_dma_start, (void*) (uintptr_t) reg_startep, is_in_isr());
+  } else {
     start_dma(reg_startep);
   }
 }
 
 // DMA is complete
-static void edpt_dma_end(void)
-{
-  TU_ASSERT(_dcd.dma_running, );
+static void edpt_dma_end(void) {
   atomic_flag_clear(&_dcd.dma_running);
 }
 
 // helper getting td
-static inline xfer_td_t* get_td(uint8_t epnum, uint8_t dir)
-{
+static inline xfer_td_t* get_td(uint8_t epnum, uint8_t dir) {
   return &_dcd.xfer[epnum][dir];
 }
 
 static void xact_out_dma(uint8_t epnum);
+
 // Function wraps xact_out_dma which wants uint8_t while usbd_defer_func wants void (*)(void *)
-static void xact_out_dma_wrapper(void *epnum)
-{
-  xact_out_dma((uint8_t)((uintptr_t)epnum));
+static void xact_out_dma_wrapper(void* epnum) {
+  xact_out_dma((uint8_t) ((uintptr_t) epnum));
 }
 
 // Start DMA to move data from Endpoint -> RAM
-static void xact_out_dma(uint8_t epnum)
-{
+static void xact_out_dma(uint8_t epnum) {
   xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
   uint32_t xact_len;
 
   // DMA can't be active during read of SIZE.EPOUT or SIZE.ISOOUT, so try to lock,
-  // If already running deffer call regardless if it was called from ISR or task,
-  if ( atomic_flag_test_and_set(&_dcd.dma_running) )
-  {
-    usbd_defer_func((osal_task_func_t)xact_out_dma_wrapper, (void *)(uint32_t)epnum, is_in_isr());
+  // If already running defer call regardless if it was called from ISR or task,
+  if (atomic_flag_test_and_set(&_dcd.dma_running)) {
+    usbd_defer_func((osal_task_func_t) xact_out_dma_wrapper, (void*) (uint32_t) epnum, is_in_isr());
     return;
   }
-  if (epnum == EP_ISO_NUM)
-  {
+  if (epnum == EP_ISO_NUM) {
     xact_len = NRF_USBD->SIZE.ISOOUT;
     // If ZERO bit is set, ignore ISOOUT length
-    if (xact_len & USBD_SIZE_ISOOUT_ZERO_Msk)
-    {
+    if (xact_len & USBD_SIZE_ISOOUT_ZERO_Msk) {
       xact_len = 0;
       atomic_flag_clear(&_dcd.dma_running);
-    }
-    else
-    {
-      // Trigger DMA move data from Endpoint -> SRAM
-      NRF_USBD->ISOOUT.PTR = (uint32_t) xfer->buffer;
-      NRF_USBD->ISOOUT.MAXCNT = xact_len;
+    } else {
+      if (xfer->started) {
+        // Trigger DMA move data from Endpoint -> SRAM
+        NRF_USBD->ISOOUT.PTR = (uint32_t) xfer->buffer;
+        NRF_USBD->ISOOUT.MAXCNT = xact_len;
 
-      start_dma(&NRF_USBD->TASKS_STARTISOOUT);
+        start_dma(&NRF_USBD->TASKS_STARTISOOUT);
+      } else {
+        atomic_flag_clear(&_dcd.dma_running);
+      }
     }
-  }
-  else
-  {
+  } else {
     // limit xact len to remaining length
     xact_len = tu_min16((uint16_t) NRF_USBD->SIZE.EPOUT[epnum], xfer->total_len - xfer->actual_len);
 
@@ -209,14 +215,13 @@ static void xact_out_dma(uint8_t epnum)
 
 // Prepare for a CBI transaction IN, call at the start
 // it start DMA to transfer data from RAM -> Endpoint
-static void xact_in_dma(uint8_t epnum)
-{
+static void xact_in_dma(uint8_t epnum) {
   xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN);
 
   // Each transaction is up to Max Packet Size
   uint16_t const xact_len = tu_min16(xfer->total_len - xfer->actual_len, xfer->mps);
 
-  NRF_USBD->EPIN[epnum].PTR    = (uint32_t) xfer->buffer;
+  NRF_USBD->EPIN[epnum].PTR = (uint32_t) xfer->buffer;
   NRF_USBD->EPIN[epnum].MAXCNT = xact_len;
 
   edpt_dma_start(&NRF_USBD->TASKS_STARTEPIN[epnum]);
@@ -225,26 +230,24 @@ static void xact_in_dma(uint8_t epnum)
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
-void dcd_init (uint8_t rhport)
-{
-  TU_LOG1("dcd init\r\n");
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
+  TU_LOG2("dcd init\r\n");
+  return true;
 }
 
-void dcd_int_enable(uint8_t rhport)
-{
+void dcd_int_enable(uint8_t rhport) {
   (void) rhport;
   NVIC_EnableIRQ(USBD_IRQn);
 }
 
-void dcd_int_disable(uint8_t rhport)
-{
+void dcd_int_disable(uint8_t rhport) {
   (void) rhport;
   NVIC_DisableIRQ(USBD_IRQn);
 }
 
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
   (void) rhport;
   (void) dev_addr;
   // Set Address is automatically update by hw controller, nothing to do
@@ -259,8 +262,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   NRF_USBD->INTENSET = USBD_INTEN_USBEVENT_Msk;
 }
 
-void dcd_remote_wakeup(uint8_t rhport)
-{
+void dcd_remote_wakeup(uint8_t rhport) {
   (void) rhport;
 
   // Bring controller out of low power mode
@@ -269,8 +271,7 @@ void dcd_remote_wakeup(uint8_t rhport)
 }
 
 // disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(uint8_t rhport)
-{
+void dcd_disconnect(uint8_t rhport) {
   (void) rhport;
   NRF_USBD->USBPULLUP = 0;
 
@@ -280,53 +281,51 @@ void dcd_disconnect(uint8_t rhport)
 }
 
 // connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(uint8_t rhport)
-{
+void dcd_connect(uint8_t rhport) {
   (void) rhport;
   NRF_USBD->USBPULLUP = 1;
 }
 
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
   (void) rhport;
-  (void) en;
-
-  // TODO implement later
+  if (en) {
+    _dcd.sof_enabled = true;
+    NRF_USBD->INTENSET = USBD_INTENSET_SOF_Msk;
+  } else {
+    _dcd.sof_enabled = false;
+    NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
+  }
 }
 
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
   (void) rhport;
 
   uint8_t const ep_addr = desc_edpt->bEndpointAddress;
-  uint8_t const epnum   = tu_edpt_number(ep_addr);
-  uint8_t const dir     = tu_edpt_dir(ep_addr);
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   _dcd.xfer[epnum][dir].mps = tu_edpt_packet_size(desc_edpt);
 
-  if (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS)
-  {
-    if (dir == TUSB_DIR_OUT)
-    {
+  if (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) {
+    if (dir == TUSB_DIR_OUT) {
       NRF_USBD->INTENSET = TU_BIT(USBD_INTEN_ENDEPOUT0_Pos + epnum);
       NRF_USBD->EPOUTEN |= TU_BIT(epnum);
 
       // Write any value to SIZE register will allow nRF to ACK/accept data
       NRF_USBD->SIZE.EPOUT[epnum] = 0;
-    }else
-    {
+    } else {
       NRF_USBD->INTENSET = TU_BIT(USBD_INTEN_ENDEPIN0_Pos + epnum);
-      NRF_USBD->EPINEN  |= TU_BIT(epnum);
+      NRF_USBD->EPINEN |= TU_BIT(epnum);
     }
-  }
-  else
-  {
+    // clear stall and reset DataToggle
+    NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
+    NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
+  } else {
     TU_ASSERT(epnum == EP_ISO_NUM);
-    if (dir == TUSB_DIR_OUT)
-    {
+    if (dir == TUSB_DIR_OUT) {
       // SPLIT ISO buffer when ISO IN endpoint is already opened.
       if (_dcd.xfer[EP_ISO_NUM][TUSB_DIR_IN].mps) NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN;
 
@@ -339,9 +338,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
       // Enable SOF and ISOOUT interrupts, and ISOOUT endpoint.
       NRF_USBD->INTENSET = USBD_INTENSET_ENDISOOUT_Msk | USBD_INTENSET_SOF_Msk;
       NRF_USBD->EPOUTEN |= USBD_EPOUTEN_ISOOUT_Msk;
-    }
-    else
-    {
+    } else {
       NRF_USBD->EVENTS_ENDISOIN = 0;
 
       // SPLIT ISO buffer when ISO OUT endpoint is already opened.
@@ -352,43 +349,38 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
       // Enable SOF and ISOIN interrupts, and ISOIN endpoint.
       NRF_USBD->INTENSET = USBD_INTENSET_ENDISOIN_Msk | USBD_INTENSET_SOF_Msk;
-      NRF_USBD->EPINEN  |= USBD_EPINEN_ISOIN_Msk;
+      NRF_USBD->EPINEN |= USBD_EPINEN_ISOIN_Msk;
     }
   }
 
-  // clear stall and reset DataToggle
-  NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
-  NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
-
-  __ISB(); __DSB();
+  __ISB();
+  __DSB();
 
   return true;
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
-{
+void dcd_edpt_close_all(uint8_t rhport) {
   // disable interrupt to prevent race condition
   dcd_int_disable(rhport);
 
   // disable all non-control (bulk + interrupt) endpoints
-  for ( uint8_t ep = 1; ep < EP_CBI_COUNT; ep++ )
-  {
+  for (uint8_t ep = 1; ep < EP_CBI_COUNT; ep++) {
     NRF_USBD->INTENCLR = TU_BIT(USBD_INTEN_ENDEPOUT0_Pos + ep) | TU_BIT(USBD_INTEN_ENDEPIN0_Pos + ep);
 
     NRF_USBD->TASKS_STARTEPIN[ep] = 0;
     NRF_USBD->TASKS_STARTEPOUT[ep] = 0;
 
-    tu_memclr(_dcd.xfer[ep], 2*sizeof(xfer_td_t));
+    tu_memclr(_dcd.xfer[ep], 2 * sizeof(xfer_td_t));
   }
 
   // disable both ISO
   NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk | USBD_INTENCLR_ENDISOOUT_Msk | USBD_INTENCLR_ENDISOIN_Msk;
   NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_OneDir;
 
-  NRF_USBD->TASKS_STARTISOIN  = 0;
+  NRF_USBD->TASKS_STARTISOIN = 0;
   NRF_USBD->TASKS_STARTISOOUT = 0;
 
-  tu_memclr(_dcd.xfer[EP_ISO_NUM], 2*sizeof(xfer_td_t));
+  tu_memclr(_dcd.xfer[EP_ISO_NUM], 2 * sizeof(xfer_td_t));
 
   // de-activate all non-control
   NRF_USBD->EPOUTEN = 1UL;
@@ -397,107 +389,89 @@ void dcd_edpt_close_all (uint8_t rhport)
   dcd_int_enable(rhport);
 }
 
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if (epnum != EP_ISO_NUM)
-  {
+  if (epnum != EP_ISO_NUM) {
     // CBI
-    if (dir == TUSB_DIR_OUT)
-    {
+    if (dir == TUSB_DIR_OUT) {
       NRF_USBD->INTENCLR = TU_BIT(USBD_INTEN_ENDEPOUT0_Pos + epnum);
       NRF_USBD->EPOUTEN &= ~TU_BIT(epnum);
-    }
-    else
-    {
+    } else {
       NRF_USBD->INTENCLR = TU_BIT(USBD_INTEN_ENDEPIN0_Pos + epnum);
       NRF_USBD->EPINEN &= ~TU_BIT(epnum);
     }
-  }
-  else
-  {
+  } else {
     _dcd.xfer[EP_ISO_NUM][dir].mps = 0;
     // ISO
-    if (dir == TUSB_DIR_OUT)
-    {
+    if (dir == TUSB_DIR_OUT) {
       NRF_USBD->INTENCLR = USBD_INTENCLR_ENDISOOUT_Msk;
       NRF_USBD->EPOUTEN &= ~USBD_EPOUTEN_ISOOUT_Msk;
       NRF_USBD->EVENTS_ENDISOOUT = 0;
-    }
-    else
-    {
+    } else {
       NRF_USBD->INTENCLR = USBD_INTENCLR_ENDISOIN_Msk;
       NRF_USBD->EPINEN &= ~USBD_EPINEN_ISOIN_Msk;
     }
     // One of the ISO endpoints closed, no need to split buffers any more.
     NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_OneDir;
     // When both ISO endpoint are close there is no need for SOF any more.
-    if (_dcd.xfer[EP_ISO_NUM][TUSB_DIR_IN].mps + _dcd.xfer[EP_ISO_NUM][TUSB_DIR_OUT].mps == 0) NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
+    if (_dcd.xfer[EP_ISO_NUM][TUSB_DIR_IN].mps + _dcd.xfer[EP_ISO_NUM][TUSB_DIR_OUT].mps == 0)
+      NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
   }
   _dcd.xfer[epnum][dir].started = false;
-  __ISB(); __DSB();
+  __ISB();
+  __DSB();
 }
 
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   xfer_td_t* xfer = get_td(epnum, dir);
 
   TU_ASSERT(!xfer->started);
-  xfer->buffer     = buffer;
-  xfer->total_len  = total_bytes;
+  xfer->buffer = buffer;
+  xfer->total_len = total_bytes;
   xfer->actual_len = 0;
 
   // Control endpoint with zero-length packet and opposite direction to 1st request byte --> status stage
   bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE));
 
-  if ( control_status )
-  {
-    // Status Phase also requires EasyDMA has to be available as well !!!!
-    edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
-
+  if (control_status) {
     // The nRF doesn't interrupt on status transmit so we queue up a success response.
     dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, is_in_isr());
-  }
-  else if ( dir == TUSB_DIR_OUT )
-  {
+
+    // Status Phase also requires EasyDMA has to be available as well !!!!
+    edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
+  } else if (dir == TUSB_DIR_OUT) {
     xfer->started = true;
-    if ( epnum == 0 )
-    {
+    if (epnum == 0) {
       // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA
       edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT);
-    }else
-    {
+    } else {
       // started just set, it could start DMA transfer if interrupt was trigger after this line
       // code only needs to start transfer (from Endpoint to RAM) when data_received was set
       // before started was set. If started is NOT set but data_received is, it means that
       // current transfer was already finished and next data is already present in endpoint and
       // can be consumed by future transfer
-      __ISB(); __DSB();
-      if ( xfer->data_received && xfer->started )
-      {
+      __ISB();
+      __DSB();
+      if (xfer->data_received && xfer->started) {
         // Data is already received previously
         // start DMA to copy to SRAM
         xfer->data_received = false;
         xact_out_dma(epnum);
-      }
-      else
-      {
+      } else {
         // nRF auto accept next Bulk/Interrupt OUT packet
         // nothing to do
       }
     }
-  }
-  else
-  {
+  } else {
     // Start DMA to copy data from RAM -> Endpoint
     xact_in_dma(epnum);
   }
@@ -505,42 +479,37 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   return true;
 }
 
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   xfer_td_t* xfer = get_td(epnum, dir);
 
-  if ( epnum == 0 )
-  {
+  if (epnum == 0) {
     NRF_USBD->TASKS_EP0STALL = 1;
-  }else if (epnum != EP_ISO_NUM)
-  {
+  } else if (epnum != EP_ISO_NUM) {
     NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_Stall << USBD_EPSTALL_STALL_Pos) | ep_addr;
 
     // Note: nRF can auto ACK packet OUT before get stalled.
     // There maybe data in endpoint fifo already, we need to pull it out
-    if ( (dir == TUSB_DIR_OUT) && xfer->data_received )
-    {
+    if ((dir == TUSB_DIR_OUT) && xfer->data_received) {
       xfer->data_received = false;
       xact_out_dma(epnum);
     }
   }
 
-  __ISB(); __DSB();
+  __ISB();
+  __DSB();
 }
 
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if ( epnum != 0 && epnum != EP_ISO_NUM )
-  {
+  if (epnum != 0 && epnum != EP_ISO_NUM) {
     // reset data toggle to DATA0
     // First write this register with VALUE=Nop to select the endpoint, then either read it to get the status from
     // VALUE, or write it again with VALUE=Data0 or Data1
@@ -553,26 +522,25 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
     // Write any value to SIZE register will allow nRF to ACK/accept data
     if (dir == TUSB_DIR_OUT) NRF_USBD->SIZE.EPOUT[epnum] = 0;
 
-    __ISB(); __DSB();
+    __ISB();
+    __DSB();
   }
 }
 
 /*------------------------------------------------------------------*/
 /* Interrupt Handler
  *------------------------------------------------------------------*/
-void bus_reset(void)
-{
+static void bus_reset(void) {
   // 6.35.6 USB controller automatically disabled all endpoints (except control)
   NRF_USBD->EPOUTEN = 1UL;
   NRF_USBD->EPINEN = 1UL;
 
-  for(int i=0; i<8; i++)
-  {
+  for (int i = 0; i < 8; i++) {
     NRF_USBD->TASKS_STARTEPIN[i] = 0;
     NRF_USBD->TASKS_STARTEPOUT[i] = 0;
   }
 
-  NRF_USBD->TASKS_STARTISOIN  = 0;
+  NRF_USBD->TASKS_STARTISOIN = 0;
   NRF_USBD->TASKS_STARTISOOUT = 0;
 
   // Clear USB Event Interrupt
@@ -582,43 +550,40 @@ void bus_reset(void)
   // Reset interrupt
   NRF_USBD->INTENCLR = NRF_USBD->INTEN;
   NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EPDATA_Msk |
-          USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_ENDEPOUT0_Msk;
+                       USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk |
+                       USBD_INTEN_ENDEPOUT0_Msk;
 
   tu_varclr(&_dcd);
   _dcd.xfer[0][TUSB_DIR_IN].mps = MAX_PACKET_SIZE;
   _dcd.xfer[0][TUSB_DIR_OUT].mps = MAX_PACKET_SIZE;
 }
 
-void dcd_int_handler(uint8_t rhport)
-{
+void dcd_int_handler(uint8_t rhport) {
   (void) rhport;
 
-  uint32_t const inten  = NRF_USBD->INTEN;
+  uint32_t const inten = NRF_USBD->INTEN;
   uint32_t int_status = 0;
 
   volatile uint32_t* regevt = &NRF_USBD->EVENTS_USBRESET;
 
-  for(uint8_t i=0; i<USBD_INTEN_EPDATA_Pos+1; i++)
-  {
-    if ( tu_bit_test(inten, i) && regevt[i]  )
-    {
+  for (uint8_t i = 0; i < USBD_INTEN_EPDATA_Pos + 1; i++) {
+    if (tu_bit_test(inten, i) && regevt[i]) {
       int_status |= TU_BIT(i);
 
       // event clear
       regevt[i] = 0;
-      __ISB(); __DSB();
+      __ISB();
+      __DSB();
     }
   }
 
-  if ( int_status & USBD_INTEN_USBRESET_Msk )
-  {
+  if (int_status & USBD_INTEN_USBRESET_Msk) {
     bus_reset();
     dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
   }
 
   // ISOIN: Data was moved to endpoint buffer, client will be notified in SOF
-  if ( int_status & USBD_INTEN_ENDISOIN_Msk )
-  {
+  if (int_status & USBD_INTEN_ENDISOIN_Msk) {
     xfer_td_t* xfer = get_td(EP_ISO_NUM, TUSB_DIR_IN);
 
     xfer->actual_len = NRF_USBD->ISOIN.AMOUNT;
@@ -627,50 +592,53 @@ void dcd_int_handler(uint8_t rhport)
     xfer->iso_in_transfer_ready = true;
   }
 
-  if ( int_status & USBD_INTEN_SOF_Msk )
-  {
+  if (int_status & USBD_INTEN_SOF_Msk) {
     bool iso_enabled = false;
 
     // ISOOUT: Transfer data gathered in previous frame from buffer to RAM
-    if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk)
-    {
+    if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk) {
       iso_enabled = true;
-      xact_out_dma(EP_ISO_NUM);
+      // Transfer from endpoint to RAM only if data is not corrupted
+      if ((int_status & USBD_INTEN_USBEVENT_Msk) == 0 ||
+          (NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_ISOOUTCRC_Msk) == 0) {
+        xact_out_dma(EP_ISO_NUM);
+      }
     }
 
     // ISOIN: Notify client that data was transferred
-    if (NRF_USBD->EPINEN & USBD_EPINEN_ISOIN_Msk)
-    {
+    if (NRF_USBD->EPINEN & USBD_EPINEN_ISOIN_Msk) {
       iso_enabled = true;
 
       xfer_td_t* xfer = get_td(EP_ISO_NUM, TUSB_DIR_IN);
-      if ( xfer->iso_in_transfer_ready )
-      {
+      if (xfer->iso_in_transfer_ready) {
         xfer->iso_in_transfer_ready = false;
         dcd_event_xfer_complete(0, EP_ISO_NUM | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
       }
     }
 
-    if ( !iso_enabled )
-    {
-      // ISO endpoint is not used, SOF is only enabled one-time for remote wakeup
-      // so we disable it now
-      NRF_USBD->INTENCLR = USBD_INTENSET_SOF_Msk;
+    if (!iso_enabled && !_dcd.sof_enabled) {
+      // SOF interrupt not manually enabled and ISO endpoint is not used,
+      // SOF is only enabled one-time for remote wakeup so we disable it now
+
+      NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
     }
 
-    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+    const uint32_t frame = NRF_USBD->FRAMECNTR;
+    dcd_event_sof(0, frame, true);
+    //dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
   }
 
-  if ( int_status & USBD_INTEN_USBEVENT_Msk )
-  {
-    TU_LOG(2, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
+  if (int_status & USBD_INTEN_USBEVENT_Msk) {
+    TU_LOG(3, "EVENTCAUSE = 0x%04" PRIX32 "\r\n", NRF_USBD->EVENTCAUSE);
 
-    enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk };
+    enum {
+      EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk |
+                       USBD_EVENTCAUSE_ISOOUTCRC_Msk
+    };
     uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK;
     NRF_USBD->EVENTCAUSE = evt_cause; // clear interrupt
 
-    if ( evt_cause & USBD_EVENTCAUSE_SUSPEND_Msk )
-    {
+    if (evt_cause & USBD_EVENTCAUSE_SUSPEND_Msk) {
       // Put controller into low power mode
       // Leave HFXO disable to application, since it may be used by other peripherals
       NRF_USBD->LOWPOWER = 1;
@@ -678,8 +646,7 @@ void dcd_int_handler(uint8_t rhport)
       dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
     }
 
-    if ( evt_cause & USBD_EVENTCAUSE_USBWUALLOWED_Msk )
-    {
+    if (evt_cause & USBD_EVENTCAUSE_USBWUALLOWED_Msk) {
       // USB is out of low power mode, and wakeup is allowed
       // Initiate RESUME signal
       NRF_USBD->DPDMVALUE = USBD_DPDMVALUE_STATE_Resume;
@@ -691,34 +658,29 @@ void dcd_int_handler(uint8_t rhport)
       NRF_USBD->INTENSET = USBD_INTENSET_SOF_Msk;
     }
 
-    if ( evt_cause & USBD_EVENTCAUSE_RESUME_Msk )
-    {
+    if (evt_cause & USBD_EVENTCAUSE_RESUME_Msk) {
       dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
     }
   }
 
   // Setup tokens are specific to the Control endpoint.
-  if ( int_status & USBD_INTEN_EP0SETUP_Msk )
-  {
-    uint8_t const setup[8] =
-    {
-      NRF_USBD->BMREQUESTTYPE , NRF_USBD->BREQUEST, NRF_USBD->WVALUEL , NRF_USBD->WVALUEH,
-      NRF_USBD->WINDEXL       , NRF_USBD->WINDEXH , NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
+  if (int_status & USBD_INTEN_EP0SETUP_Msk) {
+    uint8_t const setup[8] = {
+        NRF_USBD->BMREQUESTTYPE, NRF_USBD->BREQUEST, NRF_USBD->WVALUEL, NRF_USBD->WVALUEH,
+        NRF_USBD->WINDEXL, NRF_USBD->WINDEXH, NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
     };
 
     // nrf5x hw auto handle set address, there is no need to inform usb stack
-    tusb_control_request_t const * request = (tusb_control_request_t const *) setup;
+    tusb_control_request_t const* request = (tusb_control_request_t const*) setup;
 
-    if ( !(TUSB_REQ_RCPT_DEVICE   == request->bmRequestType_bit.recipient &&
-           TUSB_REQ_TYPE_STANDARD == request->bmRequestType_bit.type &&
-           TUSB_REQ_SET_ADDRESS   == request->bRequest) )
-    {
+    if (!(TUSB_REQ_RCPT_DEVICE == request->bmRequestType_bit.recipient &&
+          TUSB_REQ_TYPE_STANDARD == request->bmRequestType_bit.type &&
+          TUSB_REQ_SET_ADDRESS == request->bRequest)) {
       dcd_event_setup_received(0, setup, true);
     }
   }
 
-  if ( int_status & EDPT_END_ALL_MASK )
-  {
+  if (int_status & EDPT_END_ALL_MASK) {
     // DMA complete move data from SRAM <-> Endpoint
     // Must before endpoint transfer handling
     edpt_dma_end();
@@ -760,30 +722,24 @@ void dcd_int_handler(uint8_t rhport)
    * len if Host decides to sent fewer bytes, it this case transaction is also
    * complete and next transfer is not initiated here like for CBI.
    */
-  for(uint8_t epnum=0; epnum<EP_CBI_COUNT+1; epnum++)
-  {
-    if ( tu_bit_test(int_status, USBD_INTEN_ENDEPOUT0_Pos+epnum))
-    {
+  for (uint8_t epnum = 0; epnum < EP_CBI_COUNT + 1; epnum++) {
+    if (tu_bit_test(int_status, USBD_INTEN_ENDEPOUT0_Pos + epnum)) {
       xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
       uint16_t const xact_len = NRF_USBD->EPOUT[epnum].AMOUNT;
 
-      xfer->buffer     += xact_len;
+      xfer->buffer += xact_len;
       xfer->actual_len += xact_len;
 
       // Transfer complete if transaction len < Max Packet Size or total len is transferred
-      if ( (epnum != EP_ISO_NUM) && (xact_len == xfer->mps) && (xfer->actual_len < xfer->total_len) )
-      {
-        if ( epnum == 0 )
-        {
+      if ((epnum != EP_ISO_NUM) && (xact_len == xfer->mps) && (xfer->actual_len < xfer->total_len)) {
+        if (epnum == 0) {
           // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA
           edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT);
-        }else
-        {
+        } else {
           // nRF auto accept next Bulk/Interrupt OUT packet
           // nothing to do
         }
-      }else
-      {
+      } else {
         TU_ASSERT(xfer->started,);
         xfer->total_len = xfer->actual_len;
         xfer->started = false;
@@ -797,11 +753,11 @@ void dcd_int_handler(uint8_t rhport)
   }
 
   // Endpoint <-> Host ( In & OUT )
-  if ( int_status & (USBD_INTEN_EPDATA_Msk | USBD_INTEN_EP0DATADONE_Msk) )
-  {
+  if (int_status & (USBD_INTEN_EPDATA_Msk | USBD_INTEN_EP0DATADONE_Msk)) {
     uint32_t data_status = NRF_USBD->EPDATASTATUS;
     NRF_USBD->EPDATASTATUS = data_status;
-    __ISB(); __DSB();
+    __ISB();
+    __DSB();
 
     // EP0DATADONE is set with either Control Out on IN Data
     // Since EPDATASTATUS cannot be used to determine whether it is control OUT or IN.
@@ -810,22 +766,18 @@ void dcd_int_handler(uint8_t rhport)
     bool const is_control_out = (int_status & USBD_INTEN_EP0DATADONE_Msk) && !(NRF_USBD->BMREQUESTTYPE & TUSB_DIR_IN_MASK);
 
     // CBI In: Endpoint -> Host (transaction complete)
-    for(uint8_t epnum=0; epnum<EP_CBI_COUNT; epnum++)
-    {
-      if ( tu_bit_test(data_status, epnum) || (epnum == 0 && is_control_in) )
-      {
+    for (uint8_t epnum = 0; epnum < EP_CBI_COUNT; epnum++) {
+      if (tu_bit_test(data_status, epnum) || (epnum == 0 && is_control_in)) {
         xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN);
         uint8_t const xact_len = NRF_USBD->EPIN[epnum].AMOUNT;
 
-        xfer->buffer     += xact_len;
+        xfer->buffer += xact_len;
         xfer->actual_len += xact_len;
 
-        if ( xfer->actual_len < xfer->total_len )
-        {
+        if (xfer->actual_len < xfer->total_len) {
           // Start DMA to copy next data packet
           xact_in_dma(epnum);
-        } else
-        {
+        } else {
           // CBI IN complete
           dcd_event_xfer_complete(0, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
         }
@@ -833,17 +785,13 @@ void dcd_int_handler(uint8_t rhport)
     }
 
     // CBI OUT: Host -> Endpoint
-    for(uint8_t epnum=0; epnum<EP_CBI_COUNT; epnum++)
-    {
-      if ( tu_bit_test(data_status, 16+epnum) || (epnum == 0 && is_control_out) )
-      {
+    for (uint8_t epnum = 0; epnum < EP_CBI_COUNT; epnum++) {
+      if (tu_bit_test(data_status, 16 + epnum) || (epnum == 0 && is_control_out)) {
         xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
 
-        if ( xfer->started && xfer->actual_len < xfer->total_len )
-        {
+        if (xfer->started && xfer->actual_len < xfer->total_len) {
           xact_out_dma(epnum);
-        }else
-        {
+        } else {
           // Data overflow !!! Nah, nRF will auto accept next Bulk/Interrupt OUT packet
           // Mark this endpoint with data received
           xfer->data_received = true;
@@ -867,76 +815,80 @@ void dcd_int_handler(uint8_t rhport)
   #define SD_MAGIC_NUMBER   0x51B1E5DB
 #endif
 
-static inline bool is_sd_existed(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_sd_existed(void) {
   return *((uint32_t*)(SOFTDEVICE_INFO_STRUCT_ADDRESS+4)) == SD_MAGIC_NUMBER;
 }
 
 // check if SD is existed and enabled
-static inline bool is_sd_enabled(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_sd_enabled(void) {
   if ( !is_sd_existed() ) return false;
-
   uint8_t sd_en = false;
   (void) sd_softdevice_is_enabled(&sd_en);
   return sd_en;
 }
 #endif
 
-static bool hfclk_running(void)
-{
+static bool hfclk_running(void) {
 #ifdef SOFTDEVICE_PRESENT
-  if ( is_sd_enabled() )
-  {
+  if ( is_sd_enabled() ) {
     uint32_t is_running = 0;
     (void) sd_clock_hfclk_is_running(&is_running);
     return (is_running ? true : false);
   }
 #endif
 
+#if CFG_TUD_NRF_NRFX_VERSION == 1
+  return nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY);
+#else
   return nrf_clock_hf_is_running(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY);
+#endif
 }
 
-static void hfclk_enable(void)
-{
+static void hfclk_enable(void) {
 #if CFG_TUSB_OS == OPT_OS_MYNEWT
   usb_clock_request();
   return;
 #else
 
   // already running, nothing to do
-  if ( hfclk_running() ) return;
+  if (hfclk_running()) return;
 
 #ifdef SOFTDEVICE_PRESENT
-  if ( is_sd_enabled() )
-  {
+  if ( is_sd_enabled() ) {
     (void)sd_clock_hfclk_request();
     return;
   }
 #endif
 
+#if CFG_TUD_NRF_NRFX_VERSION == 1
+  nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED);
+  nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTART);
+#else
   nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
   nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTART);
 #endif
+#endif
 }
 
-static void hfclk_disable(void)
-{
+static void hfclk_disable(void) {
 #if CFG_TUSB_OS == OPT_OS_MYNEWT
   usb_clock_release();
   return;
 #else
 
 #ifdef SOFTDEVICE_PRESENT
-  if ( is_sd_enabled() )
-  {
+  if ( is_sd_enabled() ) {
     (void)sd_clock_hfclk_release();
     return;
   }
 #endif
 
+#if CFG_TUD_NRF_NRFX_VERSION == 1
+  nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
+#else
   nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
 #endif
+#endif
 }
 
 // Power & Clock Peripheral on nRF5x to manage USB
@@ -949,8 +901,8 @@ static void hfclk_disable(void)
 // Therefore this function must be called to handle USB power event by
 // - nrfx_power_usbevt_init() : if Softdevice is not used or enabled
 // - SoftDevice SOC event : if SD is used and enabled
-void tusb_hal_nrf_power_event (uint32_t event)
-{
+void tusb_hal_nrf_power_event(uint32_t event);
+void tusb_hal_nrf_power_event(uint32_t event) {
   // Value is chosen to be as same as NRFX_POWER_USB_EVT_* in nrfx_power.h
   enum {
     USB_EVT_DETECTED = 0,
@@ -958,51 +910,42 @@ void tusb_hal_nrf_power_event (uint32_t event)
     USB_EVT_READY = 2
   };
 
-#if CFG_TUSB_DEBUG >= 2
-  const char* const power_evt_str[] = { "Detected", "Removed", "Ready" };
-  TU_LOG(2, "Power USB event: %s\r\n", power_evt_str[event]);
+#if CFG_TUSB_DEBUG >= 3
+  const char* const power_evt_str[] = {"Detected", "Removed", "Ready"};
+  TU_LOG(3, "Power USB event: %s\r\n", power_evt_str[event]);
 #endif
 
-  switch ( event )
-  {
+  switch (event) {
     case USB_EVT_DETECTED:
-      if ( !NRF_USBD->ENABLE )
-      {
+      if (!NRF_USBD->ENABLE) {
         // Prepare for receiving READY event: disable interrupt since we will blocking wait
         NRF_USBD->INTENCLR = USBD_INTEN_USBEVENT_Msk;
         NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
-        __ISB(); __DSB(); // for sync
+        __ISB();
+        __DSB(); // for sync
 
 #ifdef NRF52_SERIES // NRF53 does not need this errata
         // ERRATA 171, 187, 166
-        if ( nrfx_usbd_errata_187() )
-        {
+        if (nrf52_errata_187()) {
           // CRITICAL_REGION_ENTER();
-          if ( *((volatile uint32_t *) (0x4006EC00)) == 0x00000000 )
-          {
-            *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-            *((volatile uint32_t *) (0x4006ED14)) = 0x00000003;
-            *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-          }
-          else
-          {
-            *((volatile uint32_t *) (0x4006ED14)) = 0x00000003;
+          if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) {
+            *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+            *((volatile uint32_t*) (0x4006ED14)) = 0x00000003;
+            *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+          } else {
+            *((volatile uint32_t*) (0x4006ED14)) = 0x00000003;
           }
           // CRITICAL_REGION_EXIT();
         }
 
-        if ( nrfx_usbd_errata_171() )
-        {
+        if (nrf52_errata_171()) {
           // CRITICAL_REGION_ENTER();
-          if ( *((volatile uint32_t *) (0x4006EC00)) == 0x00000000 )
-          {
-            *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-            *((volatile uint32_t *) (0x4006EC14)) = 0x000000C0;
-            *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-          }
-          else
-          {
-            *((volatile uint32_t *) (0x4006EC14)) = 0x000000C0;
+          if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) {
+            *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+            *((volatile uint32_t*) (0x4006EC14)) = 0x000000C0;
+            *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+          } else {
+            *((volatile uint32_t*) (0x4006EC14)) = 0x000000C0;
           }
           // CRITICAL_REGION_EXIT();
         }
@@ -1010,64 +953,58 @@ void tusb_hal_nrf_power_event (uint32_t event)
 
         // Enable the peripheral (will cause Ready event)
         NRF_USBD->ENABLE = 1;
-        __ISB(); __DSB(); // for sync
+        __ISB();
+        __DSB(); // for sync
 
         // Enable HFCLK
         hfclk_enable();
       }
-    break;
+      break;
 
     case USB_EVT_READY:
       // Skip if pull-up is enabled and HCLK is already running.
       // Application probably call this more than necessary.
-      if ( NRF_USBD->USBPULLUP && hfclk_running() ) break;
+      if (NRF_USBD->USBPULLUP && hfclk_running()) break;
 
       // Waiting for USBD peripheral enabled
-      while ( !(USBD_EVENTCAUSE_READY_Msk & NRF_USBD->EVENTCAUSE) ) { }
+      while (!(USBD_EVENTCAUSE_READY_Msk & NRF_USBD->EVENTCAUSE)) {}
 
       NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
-      __ISB(); __DSB(); // for sync
+      __ISB();
+      __DSB(); // for sync
 
 #ifdef NRF52_SERIES
-      if ( nrfx_usbd_errata_171() )
-      {
+      if (nrf52_errata_171()) {
         // CRITICAL_REGION_ENTER();
-        if ( *((volatile uint32_t *) (0x4006EC00)) == 0x00000000 )
-        {
-          *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-          *((volatile uint32_t *) (0x4006EC14)) = 0x00000000;
-          *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-        }
-        else
-        {
-          *((volatile uint32_t *) (0x4006EC14)) = 0x00000000;
+        if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) {
+          *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+          *((volatile uint32_t*) (0x4006EC14)) = 0x00000000;
+          *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+        } else {
+          *((volatile uint32_t*) (0x4006EC14)) = 0x00000000;
         }
 
         // CRITICAL_REGION_EXIT();
       }
 
-      if ( nrfx_usbd_errata_187() )
-      {
+      if (nrf52_errata_187()) {
         // CRITICAL_REGION_ENTER();
-        if ( *((volatile uint32_t *) (0x4006EC00)) == 0x00000000 )
-        {
-          *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-          *((volatile uint32_t *) (0x4006ED14)) = 0x00000000;
-          *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-        }
-        else
-        {
-          *((volatile uint32_t *) (0x4006ED14)) = 0x00000000;
+        if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) {
+          *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+          *((volatile uint32_t*) (0x4006ED14)) = 0x00000000;
+          *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+        } else {
+          *((volatile uint32_t*) (0x4006ED14)) = 0x00000000;
         }
         // CRITICAL_REGION_EXIT();
       }
 
-      if ( nrfx_usbd_errata_166() )
-      {
-        *((volatile uint32_t *) (NRF_USBD_BASE + 0x800)) = 0x7E3;
-        *((volatile uint32_t *) (NRF_USBD_BASE + 0x804)) = 0x40;
+      if (nrf52_errata_166()) {
+        *((volatile uint32_t*) (NRF_USBD_BASE + 0x800)) = 0x7E3;
+        *((volatile uint32_t*) (NRF_USBD_BASE + 0x804)) = 0x40;
 
-        __ISB(); __DSB();
+        __ISB();
+        __DSB();
       }
 #endif
 
@@ -1079,30 +1016,31 @@ void tusb_hal_nrf_power_event (uint32_t event)
 
       // Enable interrupt, priorities should be set by application
       NVIC_ClearPendingIRQ(USBD_IRQn);
+
       // Don't enable USBD interrupt yet, if dcd_init() did not finish yet
       // Interrupt will be enabled by tud_init(), when USB stack is ready
       // to handle interrupts.
-      if (tud_inited())
-      {
+      if (tud_inited()) {
         NVIC_EnableIRQ(USBD_IRQn);
       }
 
       // Wait for HFCLK
-      while ( !hfclk_running() ) { }
+      while (!hfclk_running()) {}
 
       // Enable pull up
       NRF_USBD->USBPULLUP = 1;
-      __ISB(); __DSB(); // for sync
-    break;
+      __ISB();
+      __DSB(); // for sync
+      break;
 
     case USB_EVT_REMOVED:
-      if ( NRF_USBD->ENABLE )
-      {
+      if (NRF_USBD->ENABLE) {
         // Abort all transfers
 
         // Disable pull up
         NRF_USBD->USBPULLUP = 0;
-        __ISB(); __DSB(); // for sync
+        __ISB();
+        __DSB(); // for sync
 
         // Disable Interrupt
         NVIC_DisableIRQ(USBD_IRQn);
@@ -1111,15 +1049,17 @@ void tusb_hal_nrf_power_event (uint32_t event)
         NRF_USBD->INTENCLR = NRF_USBD->INTEN;
 
         NRF_USBD->ENABLE = 0;
-        __ISB(); __DSB(); // for sync
+        __ISB();
+        __DSB(); // for sync
 
         hfclk_disable();
 
         dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, is_in_isr());
       }
-    break;
+      break;
 
-    default: break;
+    default:
+      break;
   }
 }
 
diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c
index 2fdc05f36..b0b6fe857 100644
--- a/src/portable/nuvoton/nuc120/dcd_nuc120.c
+++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c
@@ -27,9 +27,9 @@
 /*
   Theory of operation:
 
-  The NUC100/NUC120 USBD peripheral has six "EP"s, but each is simplex, 
-  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to 
-  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for 
+  The NUC100/NUC120 USBD peripheral has six "EP"s, but each is simplex,
+  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
+  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for
   EP0_IN and EP0_OUT respectively.  This leaves up to four for user usage.
 */
 
@@ -201,9 +201,9 @@ static const uint32_t enabled_irqs = USBD_INTSTS_FLDET_STS_Msk | USBD_INTSTS_BUS
   NUC100/NUC120 TinyUSB API driver implementation
 */
 
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   USBD->ATTR = 0x7D0;
 
@@ -215,6 +215,8 @@ void dcd_init(uint8_t rhport)
 
   USBD->INTSTS = enabled_irqs;
   USBD->INTEN  = enabled_irqs;
+
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index a56b5f8e8..f4af97ca7 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -27,9 +27,9 @@
 /*
   Theory of operation:
 
-  The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex, 
-  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to 
-  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for 
+  The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex,
+  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
+  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for
   EP0_IN and EP0_OUT respectively.  This leaves up to six for user usage.
 */
 
@@ -209,9 +209,9 @@ enum {
   NUC121/NUC125/NUC126 TinyUSB API driver implementation
 */
 
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
 #ifdef SUPPORT_LPM
   USBD->ATTR = 0x7D0 | USBD_LPMACK;
@@ -227,6 +227,8 @@ void dcd_init(uint8_t rhport)
 
   USBD->INTSTS = ENABLED_IRQS;
   USBD->INTEN  = ENABLED_IRQS;
+
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
index 886720e33..1c98a0a49 100644
--- a/src/portable/nuvoton/nuc505/dcd_nuc505.c
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -27,9 +27,9 @@
 /*
   Theory of operation:
 
-  The NUC505 USBD peripheral has twelve "EP"s, where each is simplex, in addition 
+  The NUC505 USBD peripheral has twelve "EP"s, where each is simplex, in addition
   to dedicated support for the control endpoint (EP0).  The non-user endpoints
-  are referred to as "user" EPs in this code, and follow the datasheet 
+  are referred to as "user" EPs in this code, and follow the datasheet
   nomenclature of EPA through EPL.
 */
 
@@ -181,7 +181,7 @@ static void dcd_userEP_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
     ep->EPINTEN = USBD_EPINTEN_TXPKIEN_Msk;
   }
 
-  /* provided buffers are thankfully 32-bit aligned, allowing most data to be transfered as 32-bit */
+  /* provided buffers are thankfully 32-bit aligned, allowing most data to be transferred as 32-bit */
 #if 0 // TODO support dcd_edpt_xfer_fifo API
   if (xfer->ff)
   {
@@ -279,9 +279,9 @@ static const uint32_t enabled_irqs = USBD_GINTEN_USBIEN_Msk | \
   NUC505 TinyUSB API driver implementation
 */
 
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   /* configure interrupts in their initial state; BUSINTEN and CEPINTEN will be subsequently and dynamically re-written as needed */
   USBD->GINTEN = enabled_irqs;
@@ -291,6 +291,8 @@ void dcd_init(uint8_t rhport)
   bus_reset();
 
   usb_attach();
+
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -389,7 +391,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
       while (total_bytes < USBD->CEPRXCNT);
       for (int count = 0; count < total_bytes; count++)
         *buffer++ = USBD->CEPDAT_BYTE;
-      
+
       dcd_event_xfer_complete(0, ep_addr, total_bytes, XFER_RESULT_SUCCESS, true);
     }
   }
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 13eb105cd..3d5e195a9 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Koji Kitayama
@@ -26,12 +26,14 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && ( \
-      ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \
-    )
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_FS)
 
-#include "fsl_device_registers.h"
-#define KHCI        USB0
+#ifdef TUP_USBIP_CHIPIDEA_FS_KINETIS
+  #include "fsl_device_registers.h"
+  #define KHCI        USB0
+#else
+  #error "MCU is not supported"
+#endif
 
 #include "device/dcd.h"
 
@@ -112,7 +114,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
 
 TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
 
@@ -263,13 +265,25 @@ static void process_bus_resume(uint8_t rhport)
 /*------------------------------------------------------------------*/
 /* Device API
  *------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
+
+  // save crystal-less setting (if available)
+  #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
+  uint32_t clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN;
+  uint32_t clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL;
+  #endif
 
   KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
 
+  // restore crystal-less setting (if available)
+  #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
+  KHCI->CLK_RECOVER_IRC_EN = clk_recover_irc_en;
+  KHCI->CLK_RECOVER_CTRL  |= clk_recover_ctrl;
+  #endif
+
   tu_memclr(&_dcd, sizeof(_dcd));
   KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
   KHCI->BDTPAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >>  8);
@@ -280,6 +294,8 @@ void dcd_init(uint8_t rhport)
 
   dcd_connect(rhport);
   NVIC_ClearPendingIRQ(USB0_IRQn);
+
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -296,7 +312,7 @@ void dcd_int_disable(uint8_t rhport)
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
-  _dcd.addr = dev_addr & 0x7F; 
+  _dcd.addr = dev_addr & 0x7F;
   /* Response with status first before changing device address */
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
@@ -526,9 +542,9 @@ void dcd_int_handler(uint8_t rhport)
   }
 
   if (is & USB_ISTAT_SLEEP_MASK) {
-    // TU_LOG2("Suspend: "); TU_LOG2_HEX(is);
+    // TU_LOG3("Suspend: "); TU_LOG2_HEX(is);
 
-    // Note Host usually has extra delay after bus reset (without SOF), which could falsely 
+    // Note Host usually has extra delay after bus reset (without SOF), which could falsely
     // detected as Sleep event. Though usbd has debouncing logic so we are good
     KHCI->ISTAT = USB_ISTAT_SLEEP_MASK;
     process_bus_sleep(rhport);
@@ -549,7 +565,7 @@ void dcd_int_handler(uint8_t rhport)
 
   if (is & USB_ISTAT_SOFTOK_MASK) {
     KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK;
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+    dcd_event_sof(rhport, tu_u16(KHCI->FRMNUMH, KHCI->FRMNUML), true);
   }
 
   if (is & USB_ISTAT_STALL_MASK) {
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 0f5fa6275..056dbf40b 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji Kitayama
@@ -26,12 +26,14 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && ( \
-      ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \
-    )
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_CHIPIDEA_FS)
 
-#include "fsl_device_registers.h"
-#define KHCI        USB0
+#ifdef TUP_USBIP_CHIPIDEA_FS_KINETIS
+  #include "fsl_device_registers.h"
+  #define KHCI        USB0
+#else
+  #error "MCU is not supported"
+#endif
 
 #include "host/hcd.h"
 
@@ -135,10 +137,10 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd;
-//CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _rx_buf[1024];
+CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd;
+//CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _rx_buf[1024];
 
-int find_pipe(uint8_t dev_addr, uint8_t ep_addr)
+static int find_pipe(uint8_t dev_addr, uint8_t ep_addr)
 {
   /* Find the target pipe */
   int num;
@@ -159,7 +161,7 @@ static int prepare_packets(int pipenum)
   buffer_descriptor_t *bd = _hcd.bdt[dir_tx];
   TU_ASSERT(0 == bd[odd].own, -1);
 
-  // TU_LOG1("  %p dir %d odd %d data %d\n", &bd[odd], dir_tx, odd, pipe->data);
+  // TU_LOG1("  %p dir %d odd %d data %d\r\n", &bd[odd], dir_tx, odd, pipe->data);
 
   ep->pipenum = pipenum;
 
@@ -249,7 +251,7 @@ static bool resume_transfer(int pipenum)
     flags |= USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPCTLDIS_MASK | USB_ENDPT_RETRYDIS_MASK;
     break;
   }
-  // TU_LOG1("  resume pipenum %d flags %x\n", pipenum, flags);
+  // TU_LOG1("  resume pipenum %d flags %x\r\n", pipenum, flags);
 
   KHCI->ENDPOINT[0].ENDPT = flags;
   KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | pipe->dev_addr;
@@ -300,7 +302,7 @@ static void process_tokdne(uint8_t rhport)
 
   int pipenum = ep->pipenum;
   int next_pipenum;
-  // TU_LOG1("TOKDNE %x PID %x pipe %d\n", s, pid, pipenum);
+  // TU_LOG1("TOKDNE %x PID %x pipe %d\r\n", s, pid, pipenum);
 
   xfer_result_t result;
   switch (pid) {
@@ -366,10 +368,9 @@ static void process_bus_reset(uint8_t rhport)
 /*------------------------------------------------------------------*/
 /* Host API
  *------------------------------------------------------------------*/
-bool hcd_init(uint8_t rhport)
-{
-  (void)rhport;
-
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rhport;
+  (void) rh_init;
   KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
 
@@ -414,7 +415,7 @@ void hcd_int_disable(uint8_t rhport)
 uint32_t hcd_frame_number(uint8_t rhport)
 {
   (void)rhport;
-  /* The device must be reset at least once after connection 
+  /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
   uint32_t frmnum = KHCI->FRMNUML;
@@ -445,6 +446,10 @@ void hcd_port_reset(uint8_t rhport)
   _hcd.need_reset = false;
 }
 
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+}
+
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void)rhport;
@@ -477,7 +482,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
-  // TU_LOG1("SETUP %u\n", dev_addr);
+  // TU_LOG1("SETUP %u\r\n", dev_addr);
   TU_ASSERT(0 == (_hcd.in_progress & TU_BIT(0)));
 
   int pipenum = find_pipe(dev_addr, 0);
@@ -508,7 +513,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 {
   (void)rhport;
   uint8_t const ep_addr = ep_desc->bEndpointAddress;
-  // TU_LOG1("O %u %x\n", dev_addr, ep_addr);
+  // TU_LOG1("O %u %x\r\n", dev_addr, ep_addr);
   /* Find a free pipe */
   pipe_state_t *p = &_hcd.pipe[0];
   pipe_state_t *end = &_hcd.pipe[CFG_TUH_ENDPOINT_MAX * 2];
@@ -541,7 +546,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
   (void)rhport;
-  // TU_LOG1("X %u %x %x %d\n", dev_addr, ep_addr, (uintptr_t)buffer, buflen);
+  // TU_LOG1("X %u %x %x %d\r\n", dev_addr, ep_addr, (uintptr_t)buffer, buflen);
 
   int pipenum = find_pipe(dev_addr, ep_addr);
   TU_ASSERT(0 <= pipenum);
@@ -560,8 +565,16 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return true;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   if (!tu_edpt_number(ep_addr)) return true;
   int num = find_pipe(dev_addr, ep_addr);
   if (num < 0) return false;
@@ -573,12 +586,13 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 /*--------------------------------------------------------------------+
  * ISR
  *--------------------------------------------------------------------+*/
-void hcd_int_handler(uint8_t rhport)
+void hcd_int_handler(uint8_t rhport, bool in_isr)
 {
+  (void) in_isr;
   uint32_t is  = KHCI->ISTAT;
   uint32_t msk = KHCI->INTEN;
 
-  // TU_LOG1("S %lx\n", is);
+  // TU_LOG1("S %lx\r\n", is);
 
   /* clear disabled interrupts */
   KHCI->ISTAT = (is & ~msk & ~USB_ISTAT_TOKDNE_MASK) | USB_ISTAT_SOFTOK_MASK;
@@ -587,7 +601,7 @@ void hcd_int_handler(uint8_t rhport)
   if (is & USB_ISTAT_ERROR_MASK) {
     unsigned err = KHCI->ERRSTAT;
     if (err) {
-      TU_LOG1(" ERR %x\n", err);
+      TU_LOG1(" ERR %x\r\n", err);
       KHCI->ERRSTAT = err;
     } else {
       KHCI->INTEN &= ~USB_ISTAT_ERROR_MASK;
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 0894a5eeb..855c59cd1 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -92,7 +92,7 @@ typedef struct
 
 } dcd_data_t;
 
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(128) static dcd_data_t _dcd;
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(128) static dcd_data_t _dcd;
 
 
 //--------------------------------------------------------------------+
@@ -167,9 +167,9 @@ static void bus_reset(void)
   tu_memclr(&_dcd, sizeof(dcd_data_t));
 }
 
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   //------------- user manual 11.13 usb device controller initialization -------------//
   // step 6 : set up control endpoint
@@ -186,6 +186,8 @@ void dcd_init(uint8_t rhport)
 
   // Clear pending IRQ
   NVIC_ClearPendingIRQ(USB_IRQn);
+
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -335,6 +337,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport; (void) ep_addr;
+  // TODO implement dcd_edpt_close()
+}
+
 void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.h b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
index 07daa32e4..654b80866 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
index ad9ed59b4..090d1ba69 100644
--- a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -30,6 +30,7 @@
     (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
 
 #include "chip.h"
+#include "host/hcd.h"
 
 void hcd_int_enable(uint8_t rhport)
 {
@@ -44,4 +45,3 @@ void hcd_int_disable(uint8_t rhport)
 }
 
 #endif
-
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 9b490c48c..7d5cfb5b0 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -34,20 +34,26 @@
  * - LPC54114
  * - LPC55s69
  */
-#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC13XX  || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC15XX  || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC51UXX || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC55XX)
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_IP3511)
 
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || CFG_TUSB_MCU == OPT_MCU_LPC15XX
+#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
   // LPCOpen
+  #ifdef __GNUC__
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+  #pragma GCC diagnostic ignored "-Wstrict-prototypes"
+  #endif
+
   #include "chip.h"
+
+  #ifdef __GNUC__
+  #pragma GCC diagnostic pop
+  #endif
+
 #else
   // SDK
   #include "fsl_device_registers.h"
@@ -80,7 +86,7 @@ typedef struct {
 enum {
   NBYTES_ISO_FS_MAX = 1023, // FS ISO
   NBYTES_ISO_HS_MAX = 1024, // HS ISO
-  NBYTES_CBI_FS_MAX = 64, // FS control/bulk/interrupt
+  NBYTES_CBI_FS_MAX = 64,   // FS control/bulk/interrupt. TODO some FS can do burst with higher size e.g 1024. Need to test
   NBYTES_CBI_HS_MAX = 32767 // can be up to all 15-bit, but only tested with 4096
 };
 
@@ -90,26 +96,36 @@ enum {
 };
 
 enum {
-  CMDSTAT_DEVICE_ADDR_MASK    = TU_BIT(7 )-1,
-  CMDSTAT_DEVICE_ENABLE_MASK  = TU_BIT(7 ),
-  CMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
-  CMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
-  CMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
-                                            // 23-22 is link speed (only available for HighSpeed port)
-  CMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
-  CMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
-  CMDSTAT_RESET_CHANGE_MASK   = TU_BIT(26),
-  CMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
+  DEVCMDSTAT_DEVICE_ADDR_MASK    = TU_BIT(7 )-1,
+  DEVCMDSTAT_DEVICE_ENABLE_MASK  = TU_BIT(7 ),
+  DEVCMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
+  DEVCMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
+  DEVCMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
+                                               // 23-22 is link speed (only available for HighSpeed port)
+  DEVCMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
+  DEVCMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
+  DEVCMDSTAT_RESET_CHANGE_MASK   = TU_BIT(26),
+  DEVCMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
 };
 
 enum {
-  CMDSTAT_SPEED_SHIFT = 22
+  DEVCMDSTAT_SPEED_SHIFT = 22
 };
 
 //--------------------------------------------------------------------+
 // Endpoint Command/Status List
 //--------------------------------------------------------------------+
 
+// EP Command/Status field definition
+enum {
+  EPCS_TYPE         = TU_BIT(26),
+  EPCS_RF_TV        = TU_BIT(27),
+  EPCS_TOGGLE_RESET = TU_BIT(28),
+  EPCS_STALL        = TU_BIT(29),
+  EPCS_DISABLED     = TU_BIT(30),
+  EPCS_ACTIVE       = TU_BIT(31),
+};
+
 // Endpoint Command/Status
 typedef union TU_ATTR_PACKED
 {
@@ -133,13 +149,13 @@ typedef union TU_ATTR_PACKED
 
   volatile struct {
     uint32_t TU_RESERVED  : 26;
-    uint32_t is_iso       : 1 ;
-    uint32_t toggle_mode  : 1 ;
+    uint32_t type         : 1 ;
+    uint32_t rf_tv        : 1 ; // rate feedback or toggle value
     uint32_t toggle_reset : 1 ;
     uint32_t stall        : 1 ;
     uint32_t disable      : 1 ;
     uint32_t active       : 1 ;
-  };
+  } cmd_sts;
 }ep_cmd_sts_t;
 
 TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
@@ -176,11 +192,12 @@ typedef struct
 // EP list must be 256-byte aligned
 //    Some MCU controller may require this variable to be placed in specific SRAM region.
 //    For example: LPC55s69 port1 Highspeed must be USB_RAM (0x40100000)
-//    Use CFG_TUSB_MEM_SECTION to place it accordingly.
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
+//    Use CFG_TUD_MEM_SECTION to place it accordingly.
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
 
 // Dummy buffer to fix ZLPs overwriting the buffer (probably an USB/DMA controller bug)
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
+// TODO find way to save memory
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
 
 //--------------------------------------------------------------------+
 // Multiple Controllers
@@ -188,59 +205,73 @@ CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
 
 typedef struct
 {
-  dcd_registers_t* regs;        // registers
-  const tusb_speed_t max_speed; // max link speed
-  const IRQn_Type irqnum;       // IRQ number
-  const uint8_t ep_pairs;       // Max bi-directional Endpoints
+  dcd_registers_t* regs;   // registers
+  const bool is_highspeed; // max link speed
+  const IRQn_Type irqnum;  // IRQ number
+  const uint8_t ep_pairs;  // Max bi-directional Endpoints
 }dcd_controller_t;
 
 #ifdef INCLUDE_FSL_DEVICE_REGISTERS
 
-static const dcd_controller_t _dcd_controller[] =
-{
-    { .regs = (dcd_registers_t*) USB0_BASE  , .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM    },
+static const dcd_controller_t _dcd_controller[] = {
+    { .regs = (dcd_registers_t*) USB0_BASE  , .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM    },
   #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
-    { .regs = (dcd_registers_t*) USBHSD_BASE, .max_speed = TUSB_SPEED_HIGH, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
+    { .regs = (dcd_registers_t*) USBHSD_BASE, .is_highspeed = true, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
   #endif
 };
 
 #else
 
-static const dcd_controller_t _dcd_controller[] =
-{
-  { .regs = (dcd_registers_t*) LPC_USB0_BASE, .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = 5 },
+static const dcd_controller_t _dcd_controller[] = {
+  { .regs = (dcd_registers_t*) LPC_USB0_BASE, .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = 5 },
 };
 
 #endif
 
+#if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
+  #define IP3511_HAS_HIGHSPEED
+#endif
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-static inline uint16_t get_buf_offset(void const * buffer)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint16_t get_buf_offset(void const * buffer) {
   uint32_t addr = (uint32_t) buffer;
   TU_ASSERT( (addr & 0x3f) == 0, 0 );
   return ( (addr >> 6) & 0xFFFFUL ) ;
 }
 
-static inline uint8_t ep_addr2id(uint8_t ep_addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t ep_addr2id(uint8_t ep_addr) {
   return 2*(ep_addr & 0x0F) + ((ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(ep_cmd_sts_t* ep_cs, bool is_highspeed) {
+  return is_highspeed ? (ep_cs[0].cmd_sts.type && !ep_cs[0].cmd_sts.rf_tv) : ep_cs->cmd_sts.type;
+}
+
+TU_ATTR_ALWAYS_INLINE TU_ATTR_UNUSED static inline bool ep_is_bulk(ep_cmd_sts_t* ep_cs) {
+  return (ep_cs[0].cmd_sts.type == 0) && (ep_cs[0].cmd_sts.rf_tv == 0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline ep_cmd_sts_t* get_ep_cs(uint8_t ep_id) {
+  return _dcd.ep[ep_id];
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool rhport_is_highspeed(uint8_t rhport) {
+  return _dcd_controller[rhport].is_highspeed;
+}
+
 //--------------------------------------------------------------------+
 // CONTROLLER API
 //--------------------------------------------------------------------+
 
-static void prepare_setup_packet(uint8_t rhport)
-{
-  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
-  {
-    _dcd.ep[0][1].buffer_fs.offset = get_buf_offset(_dcd.setup_packet);
-  }else
-  {
-    _dcd.ep[0][1].buffer_hs.offset = get_buf_offset(_dcd.setup_packet);
+static void prepare_setup_packet(uint8_t rhport) {
+  uint16_t const buf_offset = get_buf_offset(_dcd.setup_packet);
+  if ( _dcd_controller[rhport].is_highspeed ) {
+    _dcd.ep[0][1].buffer_hs.offset = buf_offset;
+  } else {
+    _dcd.ep[0][1].buffer_fs.offset = buf_offset;
   }
 }
 
@@ -258,8 +289,8 @@ static void edpt_reset_all(uint8_t rhport)
   }
   prepare_setup_packet(rhport);
 }
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
   edpt_reset_all(rhport);
 
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -268,10 +299,12 @@ void dcd_init(uint8_t rhport)
   dcd_reg->DATABUFSTART = tu_align((uint32_t) &_dcd, TU_BIT(22)); // 22-bit alignment
   dcd_reg->INTSTAT     |= dcd_reg->INTSTAT; // clear all pending interrupt
   dcd_reg->INTEN        = INT_DEVICE_STATUS_MASK;
-  dcd_reg->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
-                           CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+  dcd_reg->DEVCMDSTAT  |= DEVCMDSTAT_DEVICE_ENABLE_MASK | DEVCMDSTAT_DEVICE_CONNECT_MASK |
+                           DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK;
 
   NVIC_ClearPendingIRQ(_dcd_controller[rhport].irqnum);
+
+  return true;
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -291,7 +324,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   // Response with status first before changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 
-  dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
+  dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_ADDR_MASK;
   dcd_reg->DEVCMDSTAT |= dev_addr;
 }
 
@@ -303,13 +336,13 @@ void dcd_remote_wakeup(uint8_t rhport)
 void dcd_connect(uint8_t rhport)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
+  dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_DEVICE_CONNECT_MASK;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_CONNECT_MASK;
+  dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_CONNECT_MASK;
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -329,7 +362,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
   // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
   uint8_t const ep_id = ep_addr2id(ep_addr);
-  _dcd.ep[ep_id][0].stall = 1;
+  _dcd.ep[ep_id][0].cmd_sts.stall = 1;
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
@@ -338,21 +371,41 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
   uint8_t const ep_id = ep_addr2id(ep_addr);
 
-  _dcd.ep[ep_id][0].stall        = 0;
-  _dcd.ep[ep_id][0].toggle_reset = 1;
-  _dcd.ep[ep_id][0].toggle_mode  = 0;
+  _dcd.ep[ep_id][0].cmd_sts.stall        = 0;
+  _dcd.ep[ep_id][0].cmd_sts.toggle_reset = 1;
+  _dcd.ep[ep_id][0].cmd_sts.rf_tv        = 0;
 }
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   //------------- Prepare Queue Head -------------//
   uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
+  ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id);
 
   // Check if endpoint is available
-  TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
+  TU_ASSERT( ep_cs[0].cmd_sts.disable && ep_cs[1].cmd_sts.disable );
 
   edpt_reset(rhport, ep_id);
-  _dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+
+  switch (p_endpoint_desc->bmAttributes.xfer) {
+    case TUSB_XFER_ISOCHRONOUS:
+      ep_cs[0].cmd_sts.type = 1;
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      // What is interrupt endpoint in rate feedback mode ?
+      if ( rhport_is_highspeed(rhport) ) {
+        ep_cs[0].cmd_sts.type = 1;
+        ep_cs[0].cmd_sts.rf_tv = 1;
+      }
+      break;
+
+    case TUSB_XFER_BULK:
+      // nothing to do both type and rf_tv are 0
+      break;
+
+    default: break;
+  }
 
   // Enable EP interrupt
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -365,56 +418,64 @@ void dcd_edpt_close_all (uint8_t rhport)
 {
   for (uint8_t ep_id = 0; ep_id < 2*_dcd_controller[rhport].ep_pairs; ++ep_id)
   {
-    _dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
-    _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
+    _dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
+    _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
   }
 }
 
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  
+
   uint8_t ep_id = ep_addr2id(ep_addr);
-  _dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
-  _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
+  _dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
+  _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
 }
 
-static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
-{
+static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes) {
   uint16_t nbytes;
+  ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id);
 
-  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
-  {
-    nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
-    _dcd.ep[ep_id][0].buffer_fs.offset = buf_offset;
-    _dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes;
-  }else
-  {
-    nbytes = tu_min16(total_bytes, NBYTES_CBI_HS_MAX);
-    _dcd.ep[ep_id][0].buffer_hs.offset = buf_offset;
-    _dcd.ep[ep_id][0].buffer_hs.nbytes = nbytes;
+  const bool is_iso = ep_is_iso(ep_cs, _dcd_controller[rhport].is_highspeed);
+
+  if ( rhport_is_highspeed(rhport) ) {
+    nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_HS_MAX : NBYTES_CBI_HS_MAX);
+    #if TU_CHECK_MCU(OPT_MCU_LPC54)
+    // LPC54 Errata USB.1: In USB high-speed device mode, the NBytes field does not decrement after BULK OUT transfer.
+    // Suggested Work-around: Program the NByte to the max packet size (512)
+    // Actual Work-around: round up NByte to multiple of 4.
+    // Note: this can cause buffer overflowed and corrupt data if host send more data than total_bytes
+    if ( (ep_id > 1) && (ep_id & 0x01) == 0 && ep_is_bulk(ep_cs) ) {
+      if ( nbytes & 0x03 ) {
+        nbytes = tu_align4(nbytes) + 4;
+      }
+    }
+    #endif
+
+    ep_cs[0].buffer_hs.offset = buf_offset;
+    ep_cs[0].buffer_hs.nbytes = nbytes;
+  }else {
+    nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
+    ep_cs[0].buffer_fs.offset = buf_offset;
+    ep_cs[0].buffer_fs.nbytes = nbytes;
   }
 
   _dcd.dma[ep_id].nbytes = nbytes;
-
-  _dcd.ep[ep_id][0].active = 1;
+  ep_cs[0].cmd_sts.active = 1;
 }
 
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   uint8_t const ep_id = ep_addr2id(ep_addr);
 
+  if (!buffer || total_bytes == 0) {
+    // Although having no data, ZLPs can cause buffer overwritten to zeroes. Probably due to USB/DMA controller side
+    // effect/bug. Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART
+    buffer = (uint8_t *) (uint32_t) dummy;
+  }
+
   tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));
   _dcd.dma[ep_id].total_bytes = total_bytes;
 
-  if (!buffer)
-  {
-    // Although having no data, ZLPs can cause buffer overwritten to zeroes.
-    // Probably due to USB/DMA controller side effect/bug.
-    // Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART
-    buffer = (uint8_t*)(uint32_t)dummy;
-  }
-
   prepare_ep_xfer(rhport, ep_id, get_buf_offset(buffer), total_bytes);
 
   return true;
@@ -426,12 +487,12 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 static void bus_reset(uint8_t rhport)
 {
   tu_memclr(&_dcd, sizeof(dcd_data_t));
-  edpt_reset_all(rhport); 
+  edpt_reset_all(rhport);
 
   // disable all endpoints as specified by LPC55S69 UM Table 778
   for(uint8_t ep_id = 0; ep_id < 2*MAX_EP_PAIRS; ep_id++)
   {
-    _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
+    _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
   }
 
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -441,50 +502,49 @@ static void bus_reset(uint8_t rhport)
   dcd_reg->EPSKIP       = 0xFFFFFFFF;
 
   dcd_reg->INTSTAT      = dcd_reg->INTSTAT;                               // clear all pending interrupt
-  dcd_reg->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK;                    // clear setup received interrupt
+  dcd_reg->DEVCMDSTAT  |= DEVCMDSTAT_SETUP_RECEIVED_MASK;                    // clear setup received interrupt
   dcd_reg->INTEN        = INT_DEVICE_STATUS_MASK | TU_BIT(0) | TU_BIT(1); // enable device status & control endpoints
 }
 
-static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
-{
+static void process_xfer_isr(uint8_t rhport, uint32_t int_status) {
   uint8_t const max_ep = 2*_dcd_controller[rhport].ep_pairs;
 
-  for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ )
-  {
-    if ( tu_bit_test(int_status, ep_id) )
-    {
+  for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ ) {
+    if ( tu_bit_test(int_status, ep_id) ) {
       ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
       xfer_dma_t* xfer_dma = &_dcd.dma[ep_id];
 
-      if ( ep_id == 0 || ep_id == 1)
-      {
+      if ( ep_id <= 1 ) {
         // For control endpoint, we need to manually clear Active bit
-        ep_cs->active = 0;
+        ep_cs->cmd_sts.active = 0;
       }
 
       uint16_t buf_offset;
       uint16_t buf_nbytes;
 
-      if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL)
-      {
-        buf_offset = ep_cs->buffer_fs.offset;
-        buf_nbytes = ep_cs->buffer_fs.nbytes;
-      }else
-      {
+      if ( rhport_is_highspeed(rhport) ) {
         buf_offset = ep_cs->buffer_hs.offset;
         buf_nbytes = ep_cs->buffer_hs.nbytes;
+
+        #if TU_CHECK_MCU(OPT_MCU_LPC54)
+        // LPC54 Errata USB.2: In USB high-speed device mode, the NBytes field is not correct after BULK IN transfer
+        // There is no work-around. For EP in transfer, the NByte value can be ignored after a packet is transmitted.
+        if ( (ep_id > 1) && (ep_id & 0x01) == 1 && ep_is_bulk(ep_cs) ) {
+          buf_nbytes = 0;
+        }
+        #endif
+      } else {
+        buf_offset = ep_cs->buffer_fs.offset;
+        buf_nbytes = ep_cs->buffer_fs.nbytes;
       }
 
       xfer_dma->xferred_bytes += xfer_dma->nbytes - buf_nbytes;
 
-      if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
-      {
+      if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) ) {
         // There is more data to transfer
         // buff_offset has been already increased by hw to correct value for next transfer
         prepare_ep_xfer(rhport, ep_id, buf_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
-      }
-      else
-      {
+      } else {
         // for detecting ZLP
         xfer_dma->total_bytes = xfer_dma->xferred_bytes;
 
@@ -511,19 +571,16 @@ void dcd_int_handler(uint8_t rhport)
   //------------- Device Status -------------//
   if ( int_status & INT_DEVICE_STATUS_MASK )
   {
-    dcd_reg->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+    dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK;
 
-    if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
+    if ( cmd_stat & DEVCMDSTAT_RESET_CHANGE_MASK) // bus reset
     {
       bus_reset(rhport);
 
       tusb_speed_t speed = TUSB_SPEED_FULL;
-
-      if (_dcd_controller[rhport].max_speed == TUSB_SPEED_HIGH)
-      {
+      if ( _dcd_controller[rhport].is_highspeed ) {
         // 0 : reserved, 1 : full, 2 : high, 3: super
-        if ( 2 == ((cmd_stat >> CMDSTAT_SPEED_SHIFT) & 0x3UL) )
-        {
+        if ( 2 == ((cmd_stat >> DEVCMDSTAT_SPEED_SHIFT) & 0x3UL) ) {
           speed= TUSB_SPEED_HIGH;
         }
       }
@@ -531,35 +588,35 @@ void dcd_int_handler(uint8_t rhport)
       dcd_event_bus_reset(rhport, speed, true);
     }
 
-    if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
+    if (cmd_stat & DEVCMDSTAT_CONNECT_CHANGE_MASK)
     {
       // device disconnect
-      if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK)
       {
         // debouncing as this can be set when device is powering
         dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
       }
     }
 
-    if (cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
+    if (cmd_stat & DEVCMDSTAT_SUSPEND_CHANGE_MASK)
     {
       // suspend signal, bus idle for more than 3ms
       // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-      if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK)
       {
-        dcd_event_bus_signal(rhport, (cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true);
+        dcd_event_bus_signal(rhport, (cmd_stat & DEVCMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true);
       }
     }
   }
 
   // Setup Receive
-  if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
+  if ( tu_bit_test(int_status, 0) && (cmd_stat & DEVCMDSTAT_SETUP_RECEIVED_MASK) )
   {
     // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
-    _dcd.ep[0][0].active = _dcd.ep[1][0].active = 0;
-    _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 0;
+    _dcd.ep[0][0].cmd_sts.active = _dcd.ep[1][0].cmd_sts.active = 0;
+    _dcd.ep[0][0].cmd_sts.stall = _dcd.ep[1][0].cmd_sts.stall = 0;
 
-    dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
+    dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_SETUP_RECEIVED_MASK;
 
     dcd_event_setup_received(rhport, _dcd.setup_packet, true);
 
@@ -575,4 +632,3 @@ void dcd_int_handler(uint8_t rhport)
 }
 
 #endif
-
diff --git a/src/portable/nxp/transdimension/common_transdimension.h b/src/portable/nxp/transdimension/common_transdimension.h
deleted file mode 100644
index 69074de41..000000000
--- a/src/portable/nxp/transdimension/common_transdimension.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef COMMON_TRANSDIMENSION_H_
-#define COMMON_TRANSDIMENSION_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// USBCMD
-enum {
-  USBCMD_RUN_STOP         = TU_BIT(0),
-  USBCMD_RESET            = TU_BIT(1),
-  USBCMD_SETUP_TRIPWIRE   = TU_BIT(13),
-  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
-// Interrupt Threshold bit 23:16
-};
-
-// PORTSC1
-#define PORTSC1_PORT_SPEED_POS    26
-
-enum {
-  PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0),
-  PORTSC1_FORCE_PORT_RESUME      = TU_BIT(6),
-  PORTSC1_SUSPEND                = TU_BIT(7),
-  PORTSC1_FORCE_FULL_SPEED       = TU_BIT(24),
-  PORTSC1_PORT_SPEED             = TU_BIT(26) | TU_BIT(27)
-};
-
-// OTGSC
-enum {
-  OTGSC_VBUS_DISCHARGE          = TU_BIT(0),
-  OTGSC_VBUS_CHARGE             = TU_BIT(1),
-//  OTGSC_HWASSIST_AUTORESET    = TU_BIT(2),
-  OTGSC_OTG_TERMINATION         = TU_BIT(3), ///< Must set to 1 when OTG go to device mode
-  OTGSC_DATA_PULSING            = TU_BIT(4),
-  OTGSC_ID_PULLUP               = TU_BIT(5),
-//  OTGSC_HWASSIT_DATA_PULSE    = TU_BIT(6),
-//  OTGSC_HWASSIT_BDIS_ACONN    = TU_BIT(7),
-  OTGSC_ID                      = TU_BIT(8), ///< 0 = A device, 1 = B Device
-  OTGSC_A_VBUS_VALID            = TU_BIT(9),
-  OTGSC_A_SESSION_VALID         = TU_BIT(10),
-  OTGSC_B_SESSION_VALID         = TU_BIT(11),
-  OTGSC_B_SESSION_END           = TU_BIT(12),
-  OTGSC_1MS_TOGGLE              = TU_BIT(13),
-  OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14),
-};
-
-// USBMode
-enum {
-  USBMODE_CM_DEVICE = 2,
-  USBMODE_CM_HOST   = 3,
-
-  USBMODE_SLOM = TU_BIT(3),
-  USBMODE_SDIS = TU_BIT(4),
-
-  USBMODE_VBUS_POWER_SELECT = TU_BIT(5), // Need to be enabled for LPC18XX/43XX in host mode
-};
-
-// Device Registers
-typedef struct
-{
-  //------------- ID + HW Parameter Registers-------------//
-  __I  uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
-
-  //------------- Capability Registers-------------//
-  __I  uint8_t  CAPLENGTH;       ///< Capability Registers Length
-  __I  uint8_t  TU_RESERVED[1];
-  __I  uint16_t HCIVERSION;      ///< Host Controller Interface Version
-
-  __I  uint32_t HCSPARAMS;       ///< Host Controller Structural Parameters
-  __I  uint32_t HCCPARAMS;       ///< Host Controller Capability Parameters
-  __I  uint32_t TU_RESERVED[5];
-
-  __I  uint16_t DCIVERSION;      ///< Device Controller Interface Version
-  __I  uint8_t  TU_RESERVED[2];
-
-  __I  uint32_t DCCPARAMS;       ///< Device Controller Capability Parameters
-  __I  uint32_t TU_RESERVED[6];
-
-  //------------- Operational Registers -------------//
-  __IO uint32_t USBCMD;          ///< USB Command Register
-  __IO uint32_t USBSTS;          ///< USB Status Register
-  __IO uint32_t USBINTR;         ///< Interrupt Enable Register
-  __IO uint32_t FRINDEX;         ///< USB Frame Index
-  __I  uint32_t TU_RESERVED;
-  __IO uint32_t DEVICEADDR;      ///< Device Address
-  __IO uint32_t ENDPTLISTADDR;   ///< Endpoint List Address
-  __I  uint32_t TU_RESERVED;
-  __IO uint32_t BURSTSIZE;       ///< Programmable Burst Size
-  __IO uint32_t TXFILLTUNING;    ///< TX FIFO Fill Tuning
-       uint32_t TU_RESERVED[4];
-  __IO uint32_t ENDPTNAK;        ///< Endpoint NAK
-  __IO uint32_t ENDPTNAKEN;      ///< Endpoint NAK Enable
-  __I  uint32_t TU_RESERVED;
-  __IO uint32_t PORTSC1;         ///< Port Status & Control
-  __I  uint32_t TU_RESERVED[7];
-  __IO uint32_t OTGSC;           ///< On-The-Go Status & control
-  __IO uint32_t USBMODE;         ///< USB Device Mode
-  __IO uint32_t ENDPTSETUPSTAT;  ///< Endpoint Setup Status
-  __IO uint32_t ENDPTPRIME;      ///< Endpoint Prime
-  __IO uint32_t ENDPTFLUSH;      ///< Endpoint Flush
-  __I  uint32_t ENDPTSTAT;       ///< Endpoint Status
-  __IO uint32_t ENDPTCOMPLETE;   ///< Endpoint Complete
-  __IO uint32_t ENDPTCTRL[8];    ///< Endpoint Control 0 - 7
-} dcd_registers_t, hcd_registers_t;
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* COMMON_TRANSDIMENSION_H_ */
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
deleted file mode 100644
index 1f27a6872..000000000
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ /dev/null
@@ -1,672 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if CFG_TUD_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT)
-
-#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  #include "fsl_device_registers.h"
-  #define INCLUDE_FSL_DEVICE_REGISTERS
-#else
-  // LPCOpen for 18xx & 43xx
-  #include "chip.h"
-#endif
-
-#include "common/tusb_common.h"
-#include "device/dcd.h"
-#include "common_transdimension.h"
-
-#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
-  #define CleanInvalidateDCache_by_Addr   SCB_CleanInvalidateDCache_by_Addr
-#else
-  #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-// ENDPTCTRL
-enum {
-  ENDPTCTRL_STALL          = TU_BIT(0),
-  ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), // used for test only
-  ENDPTCTRL_TOGGLE_RESET   = TU_BIT(6),
-  ENDPTCTRL_ENABLE         = TU_BIT(7)
-};
-
-enum {
-  ENDPTCTRL_TYPE_POS  = 2, // Endpoint type is 2-bit field
-};
-
-// USBSTS, USBINTR
-enum {
-  INTR_USB         = TU_BIT(0),
-  INTR_ERROR       = TU_BIT(1),
-  INTR_PORT_CHANGE = TU_BIT(2),
-  INTR_RESET       = TU_BIT(6),
-  INTR_SOF         = TU_BIT(7),
-  INTR_SUSPEND     = TU_BIT(8),
-  INTR_NAK         = TU_BIT(16)
-};
-
-// Queue Transfer Descriptor
-typedef struct
-{
-  // Word 0: Next QTD Pointer
-  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
-
-  // Word 1: qTQ Token
-  uint32_t                      : 3  ;
-  volatile uint32_t xact_err    : 1  ;
-  uint32_t                      : 1  ;
-  volatile uint32_t buffer_err  : 1  ;
-  volatile uint32_t halted      : 1  ;
-  volatile uint32_t active      : 1  ;
-  uint32_t                      : 2  ;
-  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
-  uint32_t                      : 3  ;
-  uint32_t int_on_complete      : 1  ;
-  volatile uint32_t total_bytes : 15 ;
-  uint32_t                      : 1  ;
-
-  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
-  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
-
-  //--------------------------------------------------------------------+
-  // TD is 32 bytes aligned but occupies only 28 bytes
-  // Therefore there are 4 bytes padding that we can use.
-  //--------------------------------------------------------------------+
-  uint16_t expected_bytes;
-  uint8_t reserved[2];
-} dcd_qtd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
-
-// Queue Head
-typedef struct
-{
-  // Word 0: Capabilities and Characteristics
-  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
-  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
-  uint32_t max_packet_size         : 11 ; ///< Endpoint's wMaxPacketSize
-  uint32_t                         : 2  ;
-  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
-  uint32_t iso_mult                : 2  ; ///<
-
-  // Word 1: Current qTD Pointer
-  volatile uint32_t qtd_addr;
-
-  // Word 2-9: Transfer Overlay
-  volatile dcd_qtd_t qtd_overlay;
-
-  // Word 10-11: Setup request (control OUT only)
-  volatile tusb_control_request_t setup_request;
-
-  //--------------------------------------------------------------------+
-  // QHD is 64 bytes aligned but occupies only 48 bytes
-  // Therefore there are 16 bytes padding that we can use.
-  //--------------------------------------------------------------------+
-  tu_fifo_t * ff;
-  uint8_t reserved[12];
-} dcd_qhd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
-
-//--------------------------------------------------------------------+
-// Variables
-//--------------------------------------------------------------------+
-
-typedef struct
-{
-  dcd_registers_t* regs;  // registers
-  const IRQn_Type irqnum; // IRQ number
-  const uint8_t ep_count; // Max bi-directional Endpoints
-}dcd_controller_t;
-
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  static const dcd_controller_t _dcd_controller[] =
-  {
-    // RT1010 and RT1020 only has 1 USB controller
-    #if FSL_FEATURE_SOC_USBHS_COUNT == 1
-      { .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
-    #else
-      { .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
-      { .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
-    #endif
-  };
-
-#else
-  static const dcd_controller_t _dcd_controller[] =
-  {
-    { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
-    { .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
-  };
-#endif
-
-#define QTD_NEXT_INVALID 0x01
-
-typedef struct {
-  // Must be at 2K alignment
-  // Each endpoint with direction (IN/OUT) occupies a queue head
-  // for portability, TinyUSB only queue 1 TD for each Qhd
-  dcd_qhd_t qhd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64);
-  dcd_qtd_t qtd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
-}dcd_data_t;
-
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
-static dcd_data_t _dcd_data;
-
-//--------------------------------------------------------------------+
-// Controller API
-//--------------------------------------------------------------------+
-
-/// follows LPC43xx User Manual 23.10.3
-static void bus_reset(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  // The reset value for all endpoint types is the control endpoint. If one endpoint
-  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
-  // endpoint type of the unused direction must be changed from the control type to any other
-  // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
-  // for the data PID tracking on the active endpoint.
-  for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++)
-  {
-    dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
-  }
-
-  //------------- Clear All Registers -------------//
-  dcd_reg->ENDPTNAK       = dcd_reg->ENDPTNAK;
-  dcd_reg->ENDPTNAKEN     = 0;
-  dcd_reg->USBSTS         = dcd_reg->USBSTS;
-  dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
-  dcd_reg->ENDPTCOMPLETE  = dcd_reg->ENDPTCOMPLETE;
-
-  while (dcd_reg->ENDPTPRIME) {}
-  dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
-  while (dcd_reg->ENDPTFLUSH) {}
-
-  // read reset bit in portsc
-
-  //------------- Queue Head & Queue TD -------------//
-  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
-
-  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
-  _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1;
-  _dcd_data.qhd[0][0].max_packet_size  = _dcd_data.qhd[0][1].max_packet_size  = CFG_TUD_ENDPOINT0_SIZE;
-  _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
-
-  _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
-}
-
-void dcd_init(uint8_t rhport)
-{
-  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
-
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  // Reset controller
-  dcd_reg->USBCMD |= USBCMD_RESET;
-  while( dcd_reg->USBCMD & USBCMD_RESET ) {}
-
-  // Set mode to device, must be set immediately after reset
-  dcd_reg->USBMODE = USBMODE_CM_DEVICE;
-  dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
-
-#if !TUD_OPT_HIGH_SPEED
-  dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
-#endif
-
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
-  dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
-  dcd_reg->USBSTS  = dcd_reg->USBSTS;
-  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
-
-  dcd_reg->USBCMD &= ~0x00FF0000;     // Interrupt Threshold Interval = 0
-  dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
-}
-
-void dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  // Response with status first before changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->USBCMD |= USBCMD_RUN_STOP;
-}
-
-void dcd_disconnect(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
-}
-
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
-  (void) rhport;
-  (void) en;
-
-  // TODO implement later
-}
-
-//--------------------------------------------------------------------+
-// HELPER
-//--------------------------------------------------------------------+
-
-static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
-{
-  // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
-  // address to 32-byte boundaries. Buffer must be word aligned
-  CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
-
-  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
-
-  p_qtd->next            = QTD_NEXT_INVALID;
-  p_qtd->active          = 1;
-  p_qtd->total_bytes     = p_qtd->expected_bytes = total_bytes;
-  p_qtd->int_on_complete = true;
-
-  if (data_ptr != NULL)
-  {
-    p_qtd->buffer[0] = (uint32_t) data_ptr;
-
-    uint32_t const bufend = p_qtd->buffer[0] + total_bytes;
-    for(uint8_t i=1; i<5; i++)
-    {
-      uint32_t const next_page = tu_align4k( p_qtd->buffer[i-1] ) + 4096;
-      if ( bufend <= next_page ) break;
-
-      p_qtd->buffer[i] = next_page;
-
-      // TODO page[1] FRAME_N for ISO transfer
-    }
-  }
-}
-
-//--------------------------------------------------------------------+
-// DCD Endpoint Port
-//--------------------------------------------------------------------+
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
-
-  // flush to abort any primed buffer
-  dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  // data toggle also need to be reset
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
-  dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir  ? 16 : 0));
-}
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
-  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-
-  // Must not exceed max endpoint number
-  TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
-
-  //------------- Prepare Queue Head -------------//
-  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
-  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
-
-  p_qhd->zero_length_termination = 1;
-  p_qhd->max_packet_size         = tu_edpt_packet_size(p_endpoint_desc);
-  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
-  {
-    p_qhd->iso_mult = 1;
-  }
-
-  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
-
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
-  // Enable EP Control
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
-
-  if ( dir == TUSB_DIR_OUT )
-  {
-    dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0xFFFF0000u) | epctrl;
-  }else
-  {
-    dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0x0000FFFFu) | (epctrl << 16);
-  }
-
-  return true;
-}
-
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  // Disable all non-control endpoints
-  for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++)
-  {
-    _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1;
-    _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1;
-
-    dcd_reg->ENDPTFLUSH = TU_BIT(epnum) |  TU_BIT(epnum+16);
-    dcd_reg->ENDPTCTRL[epnum] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
-  }
-}
-
-void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1;
-
-  // Flush EP
-  uint32_t const flush_mask = TU_BIT(epnum + (dir ? 16 : 0));
-  dcd_reg->ENDPTFLUSH = flush_mask;
-  while(dcd_reg->ENDPTFLUSH & flush_mask);
-
-  // Clear EP enable
-  dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0));
-}
-
-static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
-  dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
-
-  p_qhd->qtd_overlay.halted = false;            // clear any previous error
-  p_qhd->qtd_overlay.next   = (uint32_t) p_qtd; // link qtd to qhd
-
-  // flush cache
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
-  if ( epnum == 0 )
-  {
-    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
-    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
-    while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
-  }
-
-  // start transfer
-  dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0));
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
-  dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
-
-  // Prepare qtd
-  qtd_init(p_qtd, buffer, total_bytes);
-
-  // Start qhd transfer
-  p_qhd->ff = NULL;
-  qhd_start_xfer(rhport, epnum, dir);
-
-  return true;
-}
-
-// fifo has to be aligned to 4k boundary
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
-  dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
-
-  tu_fifo_buffer_info_t fifo_info;
-
-  if (dir)
-  {
-    tu_fifo_get_read_info(ff, &fifo_info);
-  } else
-  {
-    tu_fifo_get_write_info(ff, &fifo_info);
-  }
-
-  if ( fifo_info.len_lin >= total_bytes )
-  {
-    // Linear length is enough for this transfer
-    qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes);
-  }
-  else
-  {
-    // linear part is not enough
-
-    // prepare TD up to linear length
-    qtd_init(p_qtd, fifo_info.ptr_lin, fifo_info.len_lin);
-
-    if ( !tu_offset4k((uint32_t) fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)) )
-    {
-      // If buffer is aligned to 4K & buffer size is multiple of 4K
-      // We can make use of buffer page array to also combine the linear + wrapped length
-      p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
-
-      for(uint8_t i = 1, page = 0; i < 5; i++)
-      {
-        // pick up buffer array where linear ends
-        if (p_qtd->buffer[i] == 0)
-        {
-          p_qtd->buffer[i] = (uint32_t) fifo_info.ptr_wrap + 4096 * page;
-          page++;
-        }
-      }
-
-      CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
-    }
-    else
-    {
-      // TODO we may need to carry the wrapped length after the linear part complete
-      // for now only transfer up to linear part
-    }
-  }
-
-  // Start qhd transfer
-  p_qhd->ff = ff;
-  qhd_start_xfer(rhport, epnum, dir);
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-
-static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir)
-{
-  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
-  dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
-
-  uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
-      ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
-
-  if ( result != XFER_RESULT_SUCCESS )
-  {
-    dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-    // flush to abort error buffer
-    dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
-  }
-
-  uint16_t const xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes;
-
-  if (p_qhd->ff)
-  {
-    if (dir == TUSB_DIR_IN)
-    {
-      tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes);
-    } else
-    {
-      tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
-    }
-  }
-  
-  // only number of bytes in the IOC qtd
-  dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
-}
-
-void dcd_int_handler(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  uint32_t const int_enable = dcd_reg->USBINTR;
-  uint32_t const int_status = dcd_reg->USBSTS & int_enable;
-  dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt
-
-  // disabled interrupt sources
-  if (int_status == 0) return;
-
-  // Set if the port controller enters the full or high-speed operational state.
-  // either from Bus Reset or Suspended state
-	if (int_status & INTR_PORT_CHANGE)
-	{
-	  // TU_LOG2("PortChange %08lx\r\n", dcd_reg->PORTSC1);
-
-	  // Reset interrupt is not enabled, we manually check if Port Change is due
-	  // to connection / disconnection
-	  if ( dcd_reg->USBSTS & INTR_RESET )
-	  {
-	    dcd_reg->USBSTS = INTR_RESET;
-
-	    if (dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS)
-	    {
-	      uint32_t const speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS;
-	      bus_reset(rhport);
-	      dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true);
-	    }else
-	    {
-	      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-	    }
-	  }
-	  else
-	  {
-	    // Triggered by resuming from suspended state
-	    if ( !(dcd_reg->PORTSC1 & PORTSC1_SUSPEND) )
-	    {
-	      dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-	    }
-	  }
-	}
-
-  if (int_status & INTR_SUSPEND)
-  {
-    // TU_LOG2("Suspend %08lx\r\n", dcd_reg->PORTSC1);
-
-    if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
-    {
-      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-      // Skip suspend event if we are not addressed
-      if ((dcd_reg->DEVICEADDR >> 25) & 0x0f)
-      {
-        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-      }
-    }
-  }
-
-  if (int_status & INTR_USB)
-  {
-    // Make sure we read the latest version of _dcd_data.
-    CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
-    uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
-    dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
-
-    if (dcd_reg->ENDPTSETUPSTAT)
-    {
-      //------------- Set up Received -------------//
-      // 23.10.10.2 Operational model for setup transfers
-      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
-
-      dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
-    }
-
-    // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
-    // nothing to do, we will submit xfer as error to usbd
-    // if (int_status & INTR_ERROR) { }
-
-    if ( edpt_complete )
-    {
-      for(uint8_t epnum = 0; epnum < TUP_DCD_ENDPOINT_MAX; epnum++)
-      {
-        if ( tu_bit_test(edpt_complete, epnum)    ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT);
-        if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
-      }
-    }
-  }
-
-  if (int_status & INTR_SOF)
-  {
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-  }
-}
-
-#endif
diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c
deleted file mode 100644
index 392764ff6..000000000
--- a/src/portable/nxp/transdimension/hcd_transdimension.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-// NXP Trans-Dimension USB IP implement EHCI for host functionality
-
-#if CFG_TUH_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT)
-
-#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  #include "fsl_device_registers.h"
-#else
-  // LPCOpen for 18xx & 43xx
-  #include "chip.h"
-#endif
-
-#include "common/tusb_common.h"
-#include "common_transdimension.h"
-#include "portable/ehci/ehci_api.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-// TODO can be merged with dcd_controller_t
-typedef struct
-{
-  uint32_t regs_base;     // registers base
-  const IRQn_Type irqnum; // IRQ number
-}hcd_controller_t;
-
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  static const hcd_controller_t _hcd_controller[] =
-  {
-    // RT1010 and RT1020 only has 1 USB controller
-    #if FSL_FEATURE_SOC_USBHS_COUNT == 1
-      { .regs_base = USB_BASE , .irqnum = USB_OTG1_IRQn }
-    #else
-      { .regs_base = USB1_BASE, .irqnum = USB_OTG1_IRQn },
-      { .regs_base = USB2_BASE, .irqnum = USB_OTG2_IRQn }
-    #endif
-  };
-
-#else
-  static const hcd_controller_t _hcd_controller[] =
-  {
-    { .regs_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },
-    { .regs_base = LPC_USB1_BASE, .irqnum = USB1_IRQn }
-  };
-#endif
-
-//--------------------------------------------------------------------+
-// Controller API
-//--------------------------------------------------------------------+
-
-bool hcd_init(uint8_t rhport)
-{
-  hcd_registers_t* hcd_reg = (hcd_registers_t*) _hcd_controller[rhport].regs_base;
-
-  // Reset controller
-  hcd_reg->USBCMD |= USBCMD_RESET;
-  while( hcd_reg->USBCMD & USBCMD_RESET ) {}
-
-  // Set mode to device, must be set immediately after reset
-#if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
-  // LPC18XX/43XX need to set VBUS Power Select to HIGH
-  // RHPORT1 is fullspeed only (need external PHY for Highspeed)
-  hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
-  if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
-#else
-  hcd_reg->USBMODE = USBMODE_CM_HOST;
-#endif
-
-  // FIXME force full speed, still have issue with Highspeed enumeration
-  hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
-
-  return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD);
-}
-
-void hcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(_hcd_controller[rhport].irqnum);
-}
-
-void hcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(_hcd_controller[rhport].irqnum);
-}
-
-#endif
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 3e523ebc2..ce35eab70 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -28,6 +28,10 @@
 
 #if CFG_TUH_ENABLED && defined(TUP_USBIP_OHCI)
 
+#ifndef TUP_OHCI_RHPORTS
+#error  OHCI is enabled, but TUP_OHCI_RHPORTS is not defined.
+#endif
+
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
@@ -141,7 +145,7 @@ enum {
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static ohci_data_t ohci_data;
+CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(256) static ohci_data_t ohci_data;
 
 static ohci_ed_t * const p_ed_head[] =
 {
@@ -153,34 +157,72 @@ static ohci_ed_t * const p_ed_head[] =
 
 static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed);
 static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr);
+static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd);
 
 //--------------------------------------------------------------------+
 // USBH-HCD API
 //--------------------------------------------------------------------+
-// Initialization according to 5.1.1.4
-bool hcd_init(uint8_t rhport)
+
+// If your system requires separation of virtual and physical memory, implement
+// tusb_app_virt_to_phys and tusb_app_virt_to_phys in your application.
+TU_ATTR_ALWAYS_INLINE static inline void *_phys_addr(void *virtual_address)
 {
+  if (tusb_app_virt_to_phys) return tusb_app_virt_to_phys(virtual_address);
+  return virtual_address;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address)
+{
+  if (tusb_app_phys_to_virt) return tusb_app_phys_to_virt(physical_address);
+  return physical_address;
+}
+
+// Initialization according to 5.1.1.4
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   //------------- Data Structure init -------------//
   tu_memclr(&ohci_data, sizeof(ohci_data_t));
   for(uint8_t i=0; i<32; i++)
-  { // assign all interrupt pointes to period head ed
-    ohci_data.hcca.interrupt_table[i] = (uint32_t) &ohci_data.period_head_ed;
+  { // assign all interrupt pointers to period head ed
+    ohci_data.hcca.interrupt_table[i] = (uint32_t) _phys_addr(&ohci_data.period_head_ed);
   }
 
   ohci_data.control[0].ed.skip  = 1;
   ohci_data.bulk_head_ed.skip   = 1;
   ohci_data.period_head_ed.skip = 1;
 
+  //If OHCI hardware is in SMM mode, gain ownership (Ref OHCI spec 5.1.1.3.3)
+  if (OHCI_REG->control_bit.interrupt_routing == 1)
+  {
+    OHCI_REG->command_status_bit.ownership_change_request = 1;
+    while (OHCI_REG->control_bit.interrupt_routing == 1) {}
+  }
+
+  //If OHCI hardware has come from warm-boot, signal resume (Ref OHCI spec 5.1.1.3.4)
+  else if (OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_RESET &&
+           OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_OPERATIONAL)
+  {
+    //Wait 20 ms. (Ref Usb spec 7.1.7.7)
+    OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_RESUME;
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+    // os_none implement task delay using usb frame counter which is not started yet
+    // therefore cause infinite delay.
+    // TODO find a way to delay in case of os none e.g __nop
+    osal_task_delay(20);
+#endif
+  }
+
   // reset controller
   OHCI_REG->command_status_bit.controller_reset = 1;
   while( OHCI_REG->command_status_bit.controller_reset ) {} // should not take longer than 10 us
 
   //------------- init ohci registers -------------//
-  OHCI_REG->control_head_ed = (uint32_t) &ohci_data.control[0].ed;
-  OHCI_REG->bulk_head_ed    = (uint32_t) &ohci_data.bulk_head_ed;
-  OHCI_REG->hcca            = (uint32_t) &ohci_data.hcca;
+  OHCI_REG->control_head_ed = (uint32_t) _phys_addr(&ohci_data.control[0].ed);
+  OHCI_REG->bulk_head_ed    = (uint32_t) _phys_addr(&ohci_data.bulk_head_ed);
+  OHCI_REG->hcca            = (uint32_t) _phys_addr(&ohci_data.hcca);
 
   OHCI_REG->interrupt_disable = OHCI_REG->interrupt_enable; // disable all interrupts
   OHCI_REG->interrupt_status  = OHCI_REG->interrupt_status; // clear current set bits
@@ -188,15 +230,21 @@ bool hcd_init(uint8_t rhport)
       OHCI_INT_UNRECOVERABLE_ERROR_MASK | OHCI_INT_FRAME_OVERFLOW_MASK | OHCI_INT_RHPORT_STATUS_CHANGE_MASK |
       OHCI_INT_MASTER_ENABLE_MASK;
 
-  OHCI_REG->control |= OHCI_CONTROL_CONTROL_BULK_RATIO | OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK |
+  OHCI_REG->control = OHCI_CONTROL_CONTROL_BULK_RATIO | OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK |
        OHCI_CONTROL_LIST_BULK_ENABLE_MASK | OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK; // TODO Isochronous
 
   OHCI_REG->frame_interval = (OHCI_FMINTERVAL_FSMPS << 16) | OHCI_FMINTERVAL_FI;
+  OHCI_REG->frame_interval ^= (1 << 31); //Must toggle when frame_interval is updated.
   OHCI_REG->periodic_start = (OHCI_FMINTERVAL_FI * 9) / 10; // Periodic start is 90% of frame interval
 
   OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)
   OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports
 
+#if CFG_TUSB_OS != OPT_OS_NONE
+  // TODO as above delay
+  osal_task_delay(OHCI_REG->rh_descriptorA_bit.power_on_to_good_time * 2); // Wait POTG after power up
+#endif
+
   return true;
 }
 
@@ -212,8 +260,7 @@ uint32_t hcd_frame_number(uint8_t rhport)
 //--------------------------------------------------------------------+
 void hcd_port_reset(uint8_t hostid)
 {
-  (void) hostid;
-  OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK;
+  OHCI_REG->rhport_status[hostid] = RHPORT_PORT_RESET_STATUS_MASK;
 }
 
 void hcd_port_reset_end(uint8_t rhport)
@@ -223,14 +270,12 @@ void hcd_port_reset_end(uint8_t rhport)
 
 bool hcd_port_connect_status(uint8_t hostid)
 {
-  (void) hostid;
-  return OHCI_REG->rhport_status_bit[0].current_connect_status;
+  return OHCI_REG->rhport_status_bit[hostid].current_connect_status;
 }
 
 tusb_speed_t hcd_port_speed_get(uint8_t hostid)
 {
-  (void) hostid;
-  return OHCI_REG->rhport_status_bit[0].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
+  return OHCI_REG->rhport_status_bit[hostid].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
 }
 
 // endpoints are tied to an address, which only reclaim after a long delay when enumerating
@@ -297,19 +342,24 @@ static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t
   p_ed->is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0);
 }
 
-static void gtd_init(ohci_gtd_t* p_td, uint8_t* data_ptr, uint16_t total_bytes)
-{
+static void gtd_init(ohci_gtd_t *p_td, uint8_t *data_ptr, uint16_t total_bytes) {
   tu_memclr(p_td, sizeof(ohci_gtd_t));
 
-  p_td->used                   = 1;
-  p_td->expected_bytes         = total_bytes;
+  p_td->used = 1;
+  gtd_get_extra_data(p_td)->expected_bytes = total_bytes;
 
-  p_td->buffer_rounding        = 1; // less than queued length is not a error
-  p_td->delay_interrupt        = OHCI_INT_ON_COMPLETE_NO;
-  p_td->condition_code         = OHCI_CCODE_NOT_ACCESSED;
+  p_td->buffer_rounding = 1; // less than queued length is not a error
+  p_td->delay_interrupt = OHCI_INT_ON_COMPLETE_NO;
+  p_td->condition_code = OHCI_CCODE_NOT_ACCESSED;
 
-  p_td->current_buffer_pointer = data_ptr;
-  p_td->buffer_end             = total_bytes ? (data_ptr + total_bytes-1) : data_ptr;
+  uint8_t *cbp = (uint8_t *) _phys_addr(data_ptr);
+
+  p_td->current_buffer_pointer = cbp;
+  if ( total_bytes ) {
+    p_td->buffer_end = _phys_addr(data_ptr + total_bytes - 1);
+  } else {
+    p_td->buffer_end = cbp;
+  }
 }
 
 static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
@@ -345,7 +395,7 @@ static ohci_ed_t * ed_find_free(void)
 static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed)
 {
   p_ed->next = p_pre->next;
-  p_pre->next = (uint32_t) p_ed;
+  p_pre->next = (uint32_t) _phys_addr(p_ed);
 }
 
 static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
@@ -354,20 +404,24 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
 
   while( p_prev->next )
   {
-    ohci_ed_t* ed = (ohci_ed_t*) p_prev->next;
+    ohci_ed_t* ed = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
 
     if (ed->dev_addr == dev_addr)
     {
-      // unlink ed
+      // Prevent Host Controller from processing this ED while we remove it
+      ed->skip = 1;
+
+      // unlink ed, will also move up p_prev
       p_prev->next = ed->next;
 
       // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
-      ed->next = (uint32_t) p_head;
+      ed->next = (uint32_t) _phys_addr(p_head);
       ed->used = 0;
+      ed->skip = 0;
+    }else
+    {
+      p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
     }
-
-    // check next valid since we could remove it
-    if (p_prev->next) p_prev = (ohci_ed_t*) p_prev->next;
   }
 }
 
@@ -386,11 +440,11 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
   // tail is always NULL
   if ( tu_align16(p_ed->td_head.address) == 0 )
   { // TD queue is empty --> head = TD
-    p_ed->td_head.address |= (uint32_t) p_gtd;
+    p_ed->td_head.address |= (uint32_t) _phys_addr(p_gtd);
   }
   else
   { // TODO currently only support queue up to 2 TD each endpoint at a time
-    ((ohci_gtd_t*) tu_align16(p_ed->td_head.address))->next = (uint32_t) p_gtd;
+    ((ohci_gtd_t*) tu_align16((uint32_t)_virt_addr((void *)p_ed->td_head.address)))->next = (uint32_t) _phys_addr(p_gtd);
   }
 }
 
@@ -439,14 +493,14 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   ohci_ed_t* ed   = &ohci_data.control[dev_addr].ed;
   ohci_gtd_t *qtd = &ohci_data.control[dev_addr].gtd;
 
-  gtd_init(qtd, (uint8_t*) setup_packet, 8);
+  gtd_init(qtd, (uint8_t*)(uintptr_t) setup_packet, 8);
   qtd->index           = dev_addr;
   qtd->pid             = PID_SETUP;
   qtd->data_toggle     = GTD_DT_DATA0;
-  qtd->delay_interrupt = 0;
+  qtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
 
   //------------- Attach TDs list to Control Endpoint -------------//
-  ed->td_head.address = (uint32_t) qtd;
+  ed->td_head.address = (uint32_t) _phys_addr(qtd);
 
   OHCI_REG->command_status_bit.control_list_filled = 1;
 
@@ -470,9 +524,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     gtd->index           = dev_addr;
     gtd->pid             = dir ? PID_IN : PID_OUT;
     gtd->data_toggle     = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1
-    gtd->delay_interrupt = 0;
+    gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
 
-    ed->td_head.address = (uint32_t) gtd;
+    ed->td_head.address = (uint32_t) _phys_addr(gtd);
 
     OHCI_REG->command_status_bit.control_list_filled = 1;
   }else
@@ -484,7 +538,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
     gtd_init(gtd, buffer, buflen);
     gtd->index = ed-ohci_data.ed_pool;
-    gtd->delay_interrupt = 0;
+    gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
 
     td_insert_to_ed(ed, gtd);
 
@@ -495,8 +549,16 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return true;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr);
 
   p_ed->is_stalled = 0;
@@ -520,16 +582,17 @@ static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head)
 
   while(td_head != NULL)
   {
+    td_head = _virt_addr(td_head);
     uint32_t next = td_head->next;
 
     // make current's item become reverse's first item
     td_head->next = (uint32_t) td_reverse_head;
-    td_reverse_head  = td_head;
+    td_reverse_head  = _phys_addr(td_head);
 
     td_head = (ohci_td_item_t*) next; // advance to next item
   }
 
-  return td_reverse_head;
+  return _virt_addr(td_reverse_head);
 }
 
 static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd)
@@ -548,6 +611,15 @@ static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
   }
 }
 
+static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd) {
+  if ( gtd_is_control(gtd) ) {
+    uint8_t idx = ((uintptr_t)gtd - (uintptr_t)&ohci_data.control->gtd) / sizeof(ohci_data.control[0]);
+    return &ohci_data.gtd_extra_control[idx];
+  }else {
+    return &ohci_data.gtd_extra[gtd - ohci_data.gtd_pool];
+  }
+}
+
 static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer)
 {
   // 5.2.9 OHCI sample code
@@ -565,6 +637,7 @@ static void done_queue_isr(uint8_t hostid)
 
   // done head is written in reversed order of completion --> need to reverse the done queue first
   ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) tu_align16(ohci_data.hcca.done_head) );
+  ohci_data.hcca.done_head = 0;
 
   while( td_head != NULL )
   {
@@ -578,8 +651,7 @@ static void done_queue_isr(uint8_t hostid)
     if ( (qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS) )
     {
       ohci_ed_t * const ed  = gtd_get_ed(qtd);
-
-      uint32_t const xferred_bytes = qtd->expected_bytes - gtd_xfer_byte_left((uint32_t) qtd->buffer_end, (uint32_t) qtd->current_buffer_pointer);
+      uint32_t const xferred_bytes = gtd_get_extra_data(qtd)->expected_bytes - gtd_xfer_byte_left((uint32_t) qtd->buffer_end, (uint32_t) qtd->current_buffer_pointer);
 
       // NOTE Assuming the current list is BULK and there is no other EDs in the list has queued TDs.
       // When there is a error resulting this ED is halted, and this EP still has other queued TD
@@ -588,7 +660,7 @@ static void done_queue_isr(uint8_t hostid)
       // --> HC will not process Control list (due to service ratio when Bulk list not empty)
       // To walk-around this, the halted ED will have TailP = HeadP (empty list condition), when clearing halt
       // the TailP must be set back to NULL for processing remaining TDs
-      if ((event != XFER_RESULT_SUCCESS))
+      if (event != XFER_RESULT_SUCCESS)
       {
         ed->td_tail &= 0x0Ful;
         ed->td_tail |= tu_align16(ed->td_head.address); // mark halted EP as empty queue
@@ -600,17 +672,21 @@ static void done_queue_isr(uint8_t hostid)
       hcd_event_xfer_complete(ed->dev_addr, tu_edpt_addr(ed->ep_number, dir), xferred_bytes, event, true);
     }
 
-    td_head = (ohci_td_item_t*) td_head->next;
+    td_head = (ohci_td_item_t*) _virt_addr((void *)td_head->next);
   }
 }
 
-void hcd_int_handler(uint8_t hostid)
-{
+void hcd_int_handler(uint8_t hostid, bool in_isr) {
+  (void) in_isr;
+
   uint32_t const int_en     = OHCI_REG->interrupt_enable;
   uint32_t const int_status = OHCI_REG->interrupt_status & int_en;
 
   if (int_status == 0) return;
 
+  // Disable MIE as per OHCI spec 5.3
+  OHCI_REG->interrupt_disable = OHCI_INT_MASTER_ENABLE_MASK;
+
   // Frame number overflow
   if ( int_status & OHCI_INT_FRAME_OVERFLOW_MASK )
   {
@@ -620,29 +696,30 @@ void hcd_int_handler(uint8_t hostid)
   //------------- RootHub status -------------//
   if ( int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK )
   {
-    uint32_t const rhport_status = OHCI_REG->rhport_status[0] & RHPORT_ALL_CHANGE_MASK;
-
-    // TODO dual port is not yet supported
-    if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK )
+    for (int i = 0; i < TUP_OHCI_RHPORTS; i++)
     {
-      // TODO check if remote wake-up
-      if ( OHCI_REG->rhport_status_bit[0].current_connect_status )
+      uint32_t const rhport_status = OHCI_REG->rhport_status[i] & RHPORT_ALL_CHANGE_MASK;
+      if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK )
       {
-        // TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
-        OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK;
-        hcd_event_device_attach(hostid, true);
-      }else
-      {
-        hcd_event_device_remove(hostid, true);
+        // TODO check if remote wake-up
+        if ( OHCI_REG->rhport_status_bit[i].current_connect_status )
+        {
+          // TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
+          OHCI_REG->rhport_status[i] = RHPORT_PORT_RESET_STATUS_MASK;
+          hcd_event_device_attach(i, true);
+        }else
+        {
+          hcd_event_device_remove(i, true);
+        }
       }
+
+      if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK)
+      {
+
+      }
+
+      OHCI_REG->rhport_status[i] = rhport_status; // acknowledge all interrupt
     }
-
-    if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK)
-    {
-
-    }
-
-    OHCI_REG->rhport_status[0] = rhport_status; // acknowledge all interrupt
   }
 
   //------------- Transfer Complete -------------//
@@ -652,6 +729,8 @@ void hcd_int_handler(uint8_t hostid)
   }
 
   OHCI_REG->interrupt_status = int_status; // Acknowledge handled interrupt
+
+  OHCI_REG->interrupt_enable = OHCI_INT_MASTER_ENABLE_MASK; // Enable MIE
 }
 //--------------------------------------------------------------------+
 // HELPER
@@ -659,4 +738,3 @@ void hcd_int_handler(uint8_t hostid)
 
 
 #endif
-
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 9fc954c8f..94bad5df7 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -34,7 +34,7 @@
 //--------------------------------------------------------------------+
 // OHCI CONFIGURATION & CONSTANTS
 //--------------------------------------------------------------------+
-#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enalbed
+#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enabled
 #define OHCI_PERIODIC_LIST (defined HOST_HCD_XFER_INTERRUPT || defined HOST_HCD_XFER_ISOCHRONOUS)
 
 // TODO merge OHCI with EHCI
@@ -45,6 +45,9 @@ enum {
 #define ED_MAX       (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX)
 #define GTD_MAX      ED_MAX
 
+// tinyUSB's OHCI implementation caps number of EDs to 8 bits
+TU_VERIFY_STATIC (ED_MAX <= 256, "Reduce CFG_TUH_DEVICE_MAX or CFG_TUH_ENDPOINT_MAX");
+
 //--------------------------------------------------------------------+
 // OHCI Data Structure
 //--------------------------------------------------------------------+
@@ -58,7 +61,9 @@ typedef struct {
 
 TU_VERIFY_STATIC( sizeof(ohci_hcca_t) == 256, "size is not correct" );
 
-typedef struct {
+// common link item for gtd and itd for list travel
+// use as pointer only
+typedef struct TU_ATTR_ALIGNED(16) {
   uint32_t reserved[2];
   volatile uint32_t next;
   uint32_t reserved2;
@@ -68,9 +73,8 @@ typedef struct TU_ATTR_ALIGNED(16)
 {
 	// Word 0
 	uint32_t used                    : 1;
-	uint32_t index                   : 4;  // endpoint index the td belongs to, or device address in case of control xfer
-  uint32_t expected_bytes          : 13; // TODO available for hcd
-
+  uint32_t index                   : 8; // endpoint index the gtd belongs to, or device address in case of control xfer
+  uint32_t                         : 9; // can be used
   uint32_t buffer_rounding         : 1;
   uint32_t pid                     : 2;
   uint32_t delay_interrupt         : 3;
@@ -79,7 +83,7 @@ typedef struct TU_ATTR_ALIGNED(16)
   volatile uint32_t condition_code : 4;
 
 	// Word 1
-	volatile uint8_t* current_buffer_pointer;
+	uint8_t* volatile current_buffer_pointer;
 
 	// Word 2 : next TD
 	volatile uint32_t next;
@@ -150,9 +154,12 @@ typedef struct TU_ATTR_ALIGNED(32)
 
 TU_VERIFY_STATIC( sizeof(ochi_itd_t) == 32, "size is not correct" );
 
+typedef struct {
+  uint16_t expected_bytes; // up to 8192 bytes so max is 13 bits
+} gtd_extra_data_t;
+
 // structure with member alignment required from large to small
-typedef struct TU_ATTR_ALIGNED(256)
-{
+typedef struct TU_ATTR_ALIGNED(256) {
   ohci_hcca_t hcca;
 
   ohci_ed_t bulk_head_ed; // static bulk head (dummy)
@@ -162,14 +169,17 @@ typedef struct TU_ATTR_ALIGNED(256)
   struct {
     ohci_ed_t ed;
     ohci_gtd_t gtd;
-  }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
+  } control[CFG_TUH_DEVICE_MAX + CFG_TUH_HUB + 1];
 
   //  ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
   ohci_ed_t ed_pool[ED_MAX];
   ohci_gtd_t gtd_pool[GTD_MAX];
 
-  volatile uint16_t frame_number_hi;
+  // extra data needed by TDs that can't fit in the TD struct
+  gtd_extra_data_t gtd_extra_control[CFG_TUH_DEVICE_MAX + CFG_TUH_HUB + 1];
+  gtd_extra_data_t gtd_extra[GTD_MAX];
 
+  volatile uint16_t frame_number_hi;
 } ohci_data_t;
 
 //--------------------------------------------------------------------+
@@ -230,8 +240,27 @@ typedef volatile struct
   uint32_t periodic_start;
   uint32_t lowspeed_threshold;
 
-  uint32_t rh_descriptorA;
-  uint32_t rh_descriptorB;
+  union {
+    uint32_t rh_descriptorA;
+    struct {
+      uint32_t number_downstream_ports     : 8;
+      uint32_t power_switching_mode        : 1;
+      uint32_t no_power_switching          : 1;
+      uint32_t device_type                 : 1;
+      uint32_t overcurrent_protection_mode : 1;
+      uint32_t no_over_current_protection  : 1;
+      uint32_t reserved                    : 11;
+      uint32_t power_on_to_good_time       : 8;
+    } rh_descriptorA_bit;
+  };
+
+  union {
+    uint32_t rh_descriptorB;
+    struct {
+      uint32_t device_removable        : 16;
+      uint32_t port_power_control_mask : 16;
+    } rh_descriptorB_bit;
+  };
 
   union {
     uint32_t rh_status;
@@ -248,7 +277,7 @@ typedef volatile struct
   };
 
   union {
-    uint32_t rhport_status[2]; // TODO NXP OHCI controller only has 2 ports
+    uint32_t rhport_status[TUP_OHCI_RHPORTS];
     struct {
       uint32_t current_connect_status             : 1;
       uint32_t port_enable_status                 : 1;
@@ -265,11 +294,11 @@ typedef volatile struct
       uint32_t port_over_current_indicator_change : 1;
       uint32_t port_reset_status_change           : 1;
       uint32_t TU_RESERVED                        : 11;
-    }rhport_status_bit[2];
+    }rhport_status_bit[TUP_OHCI_RHPORTS];
   };
 }ohci_registers_t;
 
-TU_VERIFY_STATIC( sizeof(ohci_registers_t) == 0x5c, "size is not correct");
+TU_VERIFY_STATIC( sizeof(ohci_registers_t) == (0x54 + (4 * TUP_OHCI_RHPORTS)), "size is not correct");
 
 #ifdef __cplusplus
  }
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index 1bc5594d8..60afbd435 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -50,12 +50,13 @@ static usb_descriptor_buffers_t desc;
  *------------------------------------------------------------------*/
 
 // Initialize controller to device mode
-void dcd_init (uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
-
+  (void) rh_init;
   static pio_usb_configuration_t config = PIO_USB_DEFAULT_CONFIG;
   usb_device = pio_usb_device_init(&config, &desc);
+
+  return true;
 }
 
 // Enable device interrupt
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 58b153ac3..6422afff1 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -48,17 +48,16 @@ static pio_usb_configuration_t pio_host_cfg = PIO_USB_DEFAULT_CONFIG;
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
-bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param)
-{
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) {
   (void) rhport;
   TU_VERIFY(cfg_id == TUH_CFGID_RPI_PIO_USB_CONFIGURATION);
   memcpy(&pio_host_cfg, cfg_param, sizeof(pio_usb_configuration_t));
   return true;
 }
 
-bool hcd_init(uint8_t rhport)
-{
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   // To run USB SOF interrupt in core1, call this init in core1
   pio_usb_host_init(&pio_host_cfg);
@@ -66,20 +65,17 @@ bool hcd_init(uint8_t rhport)
   return true;
 }
 
-void hcd_port_reset(uint8_t rhport)
-{
+void hcd_port_reset(uint8_t rhport) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_port_reset_start(pio_rhport);
 }
 
-void hcd_port_reset_end(uint8_t rhport)
-{
+void hcd_port_reset_end(uint8_t rhport) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_port_reset_end(pio_rhport);
 }
 
-bool hcd_port_connect_status(uint8_t rhport)
-{
+bool hcd_port_connect_status(uint8_t rhport) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
 
   root_port_t *root = PIO_USB_ROOT_PORT(pio_rhport);
@@ -88,33 +84,28 @@ bool hcd_port_connect_status(uint8_t rhport)
   return line_state != PORT_PIN_SE0;
 }
 
-tusb_speed_t hcd_port_speed_get(uint8_t rhport)
-{
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
   // TODO determine link speed
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return PIO_USB_ROOT_PORT(pio_rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW;
 }
 
 // Close all opened endpoint belong to this device
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
-{
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_close_device(pio_rhport, dev_addr);
 }
 
-uint32_t hcd_frame_number(uint8_t rhport)
-{
+uint32_t hcd_frame_number(uint8_t rhport) {
   (void) rhport;
-  return 0;
+  return pio_usb_host_get_frame_number();
 }
 
-void hcd_int_enable(uint8_t rhport)
-{
+void hcd_int_enable(uint8_t rhport) {
   (void) rhport;
 }
 
-void hcd_int_disable(uint8_t rhport)
-{
+void hcd_int_disable(uint8_t rhport) {
   (void) rhport;
 }
 
@@ -122,24 +113,26 @@ void hcd_int_disable(uint8_t rhport)
 // Endpoint API
 //--------------------------------------------------------------------+
 
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
-{
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *desc_ep) {
   hcd_devtree_info_t dev_tree;
   hcd_devtree_get_info(dev_addr, &dev_tree);
   bool const need_pre = (dev_tree.hub_addr && dev_tree.speed == TUSB_SPEED_LOW);
 
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
-  return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const*) desc_ep, need_pre);
+  return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre);
 }
 
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
-{
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen);
 }
 
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
-{
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
+  return pio_usb_host_endpoint_abort_transfer(pio_rhport, dev_addr, ep_addr);
+}
+
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_send_setup(pio_rhport, dev_addr, setup_packet);
 }
@@ -150,34 +143,32 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 //    // so if any transfer is active on epx, we are busy. Interrupt endpoints have their own
 //    // EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint
 //    // on that device
-//    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr);
+//    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\r\n", dev_addr, ep_addr);
 //    struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
 //    assert(ep);
 //    bool busy = ep->active;
-//    pico_trace("busy == %d\n", busy);
+//    pico_trace("busy == %d\r\n", busy);
 //    return busy;
 //}
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   (void) dev_addr;
   (void) ep_addr;
 
   return true;
 }
 
-static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rport, xfer_result_t result, volatile uint32_t* ep_reg)
-{
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t *rport, xfer_result_t result,
+                                                               volatile uint32_t *ep_reg) {
   (void) rport;
   const uint32_t ep_all = *ep_reg;
 
-  for(uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++)
-  {
+  for ( uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++ ) {
     uint32_t const mask = (1u << ep_idx);
 
-    if (ep_all & mask)
-    {
-      endpoint_t* ep = PIO_USB_ENDPOINT(ep_idx);
+    if ( ep_all & mask ) {
+      endpoint_t * ep = PIO_USB_ENDPOINT(ep_idx);
       hcd_event_xfer_complete(ep->dev_addr, ep->ep_num, ep->actual_len, result, true);
     }
   }
@@ -187,37 +178,31 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rpor
 }
 
 // IRQ Handler
-void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
-{
+void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id) {
   uint8_t const tu_rhport = root_id + 1;
-  root_port_t* rport = PIO_USB_ROOT_PORT(root_id);
+  root_port_t *rport = PIO_USB_ROOT_PORT(root_id);
   uint32_t const ints = rport->ints;
 
-  if ( ints & PIO_USB_INTS_CONNECT_BITS )
-  {
-    hcd_event_device_attach(tu_rhport, true);
-  }
-
-  if ( ints & PIO_USB_INTS_DISCONNECT_BITS )
-  {
-    hcd_event_device_remove(tu_rhport, true);
-  }
-
-  if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
-  {
+  if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_SUCCESS, &rport->ep_complete);
   }
 
-  if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS )
-  {
+  if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_STALLED, &rport->ep_stalled);
   }
 
-  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
-  {
+  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_FAILED, &rport->ep_error);
   }
 
+  if ( ints & PIO_USB_INTS_CONNECT_BITS ) {
+    hcd_event_device_attach(tu_rhport, true);
+  }
+
+  if ( ints & PIO_USB_INTS_DISCONNECT_BITS ) {
+    hcd_event_device_remove(tu_rhport, true);
+  }
+
   // clear all
   rport->ints &= ~ints;
 }
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 4952d29b1..af08b549d 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -29,6 +29,7 @@
 #if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUD_RPI_PIO_USB
 
 #include "pico.h"
+#include "hardware/sync.h"
 #include "rp2040_usb.h"
 
 #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
@@ -45,12 +46,8 @@
 /*------------------------------------------------------------------*/
 /* Low level controller
  *------------------------------------------------------------------*/
-
-#define usb_hw_set hw_set_alias(usb_hw)
-#define usb_hw_clear hw_clear_alias(usb_hw)
-
 // Init these in dcd_init
-static uint8_t *next_buffer_ptr;
+static uint8_t* next_buffer_ptr;
 
 // USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in.
 static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2];
@@ -58,79 +55,43 @@ static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2];
 // SOF may be used by remote wakeup as RESUME, this indicate whether SOF is actually used by usbd
 static bool _sof_enable = false;
 
-TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir)
-{
+TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir) {
   return &hw_endpoints[num][dir];
 }
 
-static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_addr(uint8_t ep_addr) {
   uint8_t num = tu_edpt_number(ep_addr);
   tusb_dir_t dir = tu_edpt_dir(ep_addr);
   return hw_endpoint_get_by_num(num, dir);
 }
 
-static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
-{
-  // size must be multiple of 64
-  uint size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
+// Allocate from the USB buffer space (max 3840 bytes)
+static void hw_endpoint_alloc(struct hw_endpoint* ep, size_t size) {
+  // round up size to multiple of 64
+  size = tu_round_up(ep->wMaxPacketSize, 64);
 
   // double buffered Bulk endpoint
-  if ( transfer_type == TUSB_XFER_BULK )
-  {
+  if (ep->transfer_type == TUSB_XFER_BULK) {
     size *= 2u;
   }
 
+  // assign buffer
   ep->hw_data_buf = next_buffer_ptr;
   next_buffer_ptr += size;
 
-  assert(((uintptr_t )next_buffer_ptr & 0b111111u) == 0);
-  uint dpram_offset = hw_data_offset(ep->hw_data_buf);
-  hard_assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
-
-  pico_info("  Allocated %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf);
-
-  // Fill in endpoint control register with buffer offset
-  uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint)transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
+  hard_assert(next_buffer_ptr < usb_dpram->epx_data + sizeof(usb_dpram->epx_data));
+  pico_info("  Allocated %d bytes (0x%p)\r\n", size,  ep->hw_data_buf);
+}
 
+// Enable endpoint
+TU_ATTR_ALWAYS_INLINE static inline void hw_endpoint_enable(struct hw_endpoint* ep) {
+  uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint) ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | hw_data_offset(ep->hw_data_buf);
   *ep->endpoint_control = reg;
 }
 
-static void _hw_endpoint_close(struct hw_endpoint *ep)
-{
-    // Clear hardware registers and then zero the struct
-    // Clears endpoint enable
-    *ep->endpoint_control = 0;
-    // Clears buffer available, etc
-    *ep->buffer_control = 0;
-    // Clear any endpoint state
-    memset(ep, 0, sizeof(struct hw_endpoint));
-
-    // Reclaim buffer space if all endpoints are closed
-    bool reclaim_buffers = true;
-    for ( uint8_t i = 1; i < USB_MAX_ENDPOINTS; i++ )
-    {
-        if (hw_endpoint_get_by_num(i, TUSB_DIR_OUT)->hw_data_buf != NULL || hw_endpoint_get_by_num(i, TUSB_DIR_IN)->hw_data_buf != NULL)
-        {
-            reclaim_buffers = false;
-            break;
-        }
-    }
-    if (reclaim_buffers)
-    {
-        next_buffer_ptr = &usb_dpram->epx_data[0];
-    }
-}
-
-static void hw_endpoint_close(uint8_t ep_addr)
-{
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    _hw_endpoint_close(ep);
-}
-
-static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
-{
-  struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+// main processing for dcd_edpt_iso_activate
+static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) {
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
 
   const uint8_t num = tu_edpt_number(ep_addr);
   const tusb_dir_t dir = tu_edpt_dir(ep_addr);
@@ -145,206 +106,232 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
   ep->transfer_type = transfer_type;
 
   // Every endpoint has a buffer control register in dpram
-  if ( dir == TUSB_DIR_IN )
-  {
+  if (dir == TUSB_DIR_IN) {
     ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
-  }
-  else
-  {
+  } else {
     ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out;
   }
 
   // Clear existing buffer control state
   *ep->buffer_control = 0;
 
-  if ( num == 0 )
-  {
+  if (num == 0) {
     // EP0 has no endpoint control register because the buffer offsets are fixed
     ep->endpoint_control = NULL;
 
     // Buffer offset is fixed (also double buffered)
     ep->hw_data_buf = (uint8_t*) &usb_dpram->ep0_buf_a[0];
-  }
-  else
-  {
+  } else {
     // Set the endpoint control register (starts at EP1, hence num-1)
-    if ( dir == TUSB_DIR_IN )
-    {
+    if (dir == TUSB_DIR_IN) {
       ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].in;
-    }
-    else
-    {
+    } else {
       ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out;
     }
-
-    // alloc a buffer and fill in endpoint control register
-    _hw_endpoint_alloc(ep, transfer_type);
   }
 }
 
-static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
-{
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    hw_endpoint_xfer_start(ep, buffer, total_bytes);
+// Init, allocate buffer and enable endpoint
+static void hw_endpoint_open(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) {
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
+  hw_endpoint_init(ep_addr, wMaxPacketSize, transfer_type);
+  const uint8_t num = tu_edpt_number(ep_addr);
+  if (num != 0) {
+    // EP0 is already enabled
+    hw_endpoint_alloc(ep, ep->wMaxPacketSize);
+    hw_endpoint_enable(ep);
+  }
 }
 
-static void __tusb_irq_path_func(hw_handle_buff_status)(void)
-{
-    uint32_t remaining_buffers = usb_hw->buf_status;
-    pico_trace("buf_status = 0x%08x\n", remaining_buffers);
-    uint bit = 1u;
-    for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
-    {
-        if (remaining_buffers & bit)
-        {
-            // clear this in advance
-            usb_hw_clear->buf_status = bit;
+static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
+  hw_endpoint_xfer_start(ep, buffer, total_bytes);
+}
 
-            // IN transfer for even i, OUT transfer for odd i
-            struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u));
+static void __tusb_irq_path_func(hw_handle_buff_status)(void) {
+  uint32_t remaining_buffers = usb_hw->buf_status;
+  pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers);
+  uint bit = 1u;
+  for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++) {
+    if (remaining_buffers & bit) {
+      // clear this in advance
+      usb_hw_clear->buf_status = bit;
 
-            // Continue xfer
-            bool done = hw_endpoint_xfer_continue(ep);
-            if (done)
-            {
-                // Notify
-                dcd_event_xfer_complete(0, ep->ep_addr, ep->xferred_len, XFER_RESULT_SUCCESS, true);
-                hw_endpoint_reset_transfer(ep);
-            }
-            remaining_buffers &= ~bit;
-        }
-        bit <<= 1u;
+      // IN transfer for even i, OUT transfer for odd i
+      struct hw_endpoint* ep = hw_endpoint_get_by_num(i >> 1u, (i & 1u) ? TUSB_DIR_OUT : TUSB_DIR_IN);
+
+      // Continue xfer
+      bool done = hw_endpoint_xfer_continue(ep);
+      if (done) {
+        // Notify
+        dcd_event_xfer_complete(0, ep->ep_addr, ep->xferred_len, XFER_RESULT_SUCCESS, true);
+        hw_endpoint_reset_transfer(ep);
+      }
+      remaining_buffers &= ~bit;
     }
+    bit <<= 1u;
+  }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void)
-{
-    // If we have finished this transfer on EP0 set pid back to 1 for next
-    // setup transfer. Also clear a stall in case
-    uint8_t addrs[] = {0x0, 0x80};
-    for (uint i = 0 ; i < TU_ARRAY_SIZE(addrs); i++)
-    {
-        struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]);
-        ep->next_pid = 1u;
+TU_ATTR_ALWAYS_INLINE static inline void reset_ep0(void) {
+  // If we have finished this transfer on EP0 set pid back to 1 for next
+  // setup transfer. Also clear a stall in case
+  for (uint8_t dir = 0; dir < 2; dir++) {
+    struct hw_endpoint* ep = hw_endpoint_get_by_num(0, dir);
+    if (ep->active) {
+      // Abort any pending transfer from a prior control transfer per USB specs
+      // Due to Errata RP2040-E2: ABORT flag is only applicable for B2 and later (unusable for B0, B1).
+      // Which means we are not guaranteed to safely abort pending transfer on B0 and B1.
+      uint32_t const abort_mask = (dir ? USB_EP_ABORT_EP0_IN_BITS : USB_EP_ABORT_EP0_OUT_BITS);
+      if (rp2040_chip_version() >= 2) {
+        usb_hw_set->abort = abort_mask;
+        while ((usb_hw->abort_done & abort_mask) != abort_mask) {}
+      }
+
+      _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_DATA1_PID | USB_BUF_CTRL_SEL);
+      hw_endpoint_reset_transfer(ep);
+
+      if (rp2040_chip_version() >= 2) {
+        usb_hw_clear->abort_done = abort_mask;
+        usb_hw_clear->abort = abort_mask;
+      }
     }
+    ep->next_pid = 1u;
+  }
 }
 
-static void __tusb_irq_path_func(reset_non_control_endpoints)(void)
-{
+static void __tusb_irq_path_func(reset_non_control_endpoints)(void) {
   // Disable all non-control
-  for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS-1; i++ )
-  {
+  for (uint8_t i = 0; i < USB_MAX_ENDPOINTS - 1; i++) {
     usb_dpram->ep_ctrl[i].in = 0;
     usb_dpram->ep_ctrl[i].out = 0;
   }
 
   // clear non-control hw endpoints
-  tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2*sizeof(hw_endpoint_t));
+  tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2 * sizeof(hw_endpoint_t));
 
   // reclaim buffer space
   next_buffer_ptr = &usb_dpram->epx_data[0];
 }
 
-static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
-{
-    uint32_t const status = usb_hw->ints;
-    uint32_t handled = 0;
+static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
+  uint32_t const status = usb_hw->ints;
+  uint32_t handled = 0;
 
-    if (status & USB_INTF_DEV_SOF_BITS)
-    {
-      handled |= USB_INTF_DEV_SOF_BITS;
+  if (status & USB_INTF_DEV_SOF_BITS) {
+    bool keep_sof_alive = false;
 
-      // disable SOF interrupt if it is used for RESUME in remote wakeup
-      if (!_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+    handled |= USB_INTF_DEV_SOF_BITS;
 
-      dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
-    }
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+    // Errata 15 workaround for Device Bulk-In endpoint
+    e15_last_sof = time_us_32();
 
-    // xfer events are handled before setup req. So if a transfer completes immediately
-    // before closing the EP, the events will be delivered in same order.
-    if (status & USB_INTS_BUFF_STATUS_BITS)
-    {
-        handled |= USB_INTS_BUFF_STATUS_BITS;
-        hw_handle_buff_status();
-    }
+    for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) {
+      struct hw_endpoint* ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN);
 
-    if (status & USB_INTS_SETUP_REQ_BITS)
-    {
-        handled |= USB_INTS_SETUP_REQ_BITS;
-        uint8_t const *setup = (uint8_t const *)&usb_dpram->setup_packet;
+      // Active Bulk IN endpoint requires SOF
+      if ((ep->transfer_type == TUSB_XFER_BULK) && ep->active) {
+        keep_sof_alive = true;
 
-        // reset pid to both 1 (data and ack)
-        reset_ep0_pid();
+        hw_endpoint_lock_update(ep, 1);
 
-        // Pass setup packet to tiny usb
-        dcd_event_setup_received(0, setup, true);
-        usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS;
-    }
-
-#if FORCE_VBUS_DETECT == 0
-    // Since we force VBUS detect On, device will always think it is connected and
-    // couldn't distinguish between disconnect and suspend
-    if (status & USB_INTS_DEV_CONN_DIS_BITS)
-    {
-        handled |= USB_INTS_DEV_CONN_DIS_BITS;
-
-        if ( usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS )
-        {
-          // Connected: nothing to do
-        }else
-        {
-          // Disconnected
-          dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+        // Deferred enable?
+        if (ep->pending) {
+          ep->pending = 0;
+          hw_endpoint_start_next_buffer(ep);
         }
 
-        usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS;
+        hw_endpoint_lock_update(ep, -1);
+      }
     }
 #endif
 
-    // SE0 for 2.5 us or more (will last at least 10ms)
-    if (status & USB_INTS_BUS_RESET_BITS)
+    // disable SOF interrupt if it is used for RESUME in remote wakeup
+    if (!keep_sof_alive && !_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+
+    dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
+  }
+
+  // xfer events are handled before setup req. So if a transfer completes immediately
+  // before closing the EP, the events will be delivered in same order.
+  if (status & USB_INTS_BUFF_STATUS_BITS) {
+    handled |= USB_INTS_BUFF_STATUS_BITS;
+    hw_handle_buff_status();
+  }
+
+  if (status & USB_INTS_SETUP_REQ_BITS) {
+    handled |= USB_INTS_SETUP_REQ_BITS;
+    uint8_t const* setup = remove_volatile_cast(uint8_t const*, &usb_dpram->setup_packet);
+
+    // reset pid to both 1 (data and ack)
+    reset_ep0();
+
+    // Pass setup packet to tiny usb
+    dcd_event_setup_received(0, setup, true);
+    usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS;
+  }
+
+#if FORCE_VBUS_DETECT == 0
+  // Since we force VBUS detect On, device will always think it is connected and
+  // couldn't distinguish between disconnect and suspend
+  if (status & USB_INTS_DEV_CONN_DIS_BITS)
+  {
+    handled |= USB_INTS_DEV_CONN_DIS_BITS;
+
+    if ( usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS )
     {
-        pico_trace("BUS RESET\n");
+      // Connected: nothing to do
+    }else
+    {
+      // Disconnected
+      dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+    }
 
-        handled |= USB_INTS_BUS_RESET_BITS;
+    usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS;
+  }
+#endif
 
-        usb_hw->dev_addr_ctrl = 0;
-        reset_non_control_endpoints();
-        dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
-        usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
+  // SE0 for 2.5 us or more (will last at least 10ms)
+  if (status & USB_INTS_BUS_RESET_BITS) {
+    pico_trace("BUS RESET\r\n");
+
+    handled |= USB_INTS_BUS_RESET_BITS;
+
+    usb_hw->dev_addr_ctrl = 0;
+    reset_non_control_endpoints();
+    dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
+    usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
 
 #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
-        // Only run enumeration walk-around if pull up is enabled
-        if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix();
+    // Only run enumeration workaround if pull up is enabled
+    if (usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS) rp2040_usb_device_enumeration_fix();
 #endif
-    }
+  }
 
-    /* Note from pico datasheet 4.1.2.6.4 (v1.2)
-     * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when
-     * the device is first connected but the bus is idle. The bus can be idle for a few ms before
-     * the host begins sending start of frame packets. You will also see a suspend interrupt
-     * when the device is disconnected if you do not have a VBUS detect circuit connected. This is
-     * because without VBUS detection, it is impossible to tell the difference between
-     * being disconnected and suspended.
-     */
-    if (status & USB_INTS_DEV_SUSPEND_BITS)
-    {
-        handled |= USB_INTS_DEV_SUSPEND_BITS;
-        dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
-        usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS;
-    }
+  /* Note from pico datasheet 4.1.2.6.4 (v1.2)
+   * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when
+   * the device is first connected but the bus is idle. The bus can be idle for a few ms before
+   * the host begins sending start of frame packets. You will also see a suspend interrupt
+   * when the device is disconnected if you do not have a VBUS detect circuit connected. This is
+   * because without VBUS detection, it is impossible to tell the difference between
+   * being disconnected and suspended.
+   */
+  if (status & USB_INTS_DEV_SUSPEND_BITS) {
+    handled |= USB_INTS_DEV_SUSPEND_BITS;
+    dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+    usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS;
+  }
 
-    if (status & USB_INTS_DEV_RESUME_FROM_HOST_BITS)
-    {
-        handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS;
-        dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
-        usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS;
-    }
+  if (status & USB_INTS_DEV_RESUME_FROM_HOST_BITS) {
+    handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS;
+    dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+    usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS;
+  }
 
-    if (status ^ handled)
-    {
-        panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
-    }
+  if (status ^ handled) {
+    panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
+  }
 }
 
 #define USB_INTS_ERROR_BITS ( \
@@ -358,10 +345,17 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 /* Controller API
  *------------------------------------------------------------------*/
 
-void dcd_init (uint8_t rhport)
-{
+// older SDK
+#ifndef PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY
+#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff
+#endif
+
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
   assert(rhport == 0);
 
+  TU_LOG(2, "Chip Version B%u\r\n", rp2040_chip_version());
+
   // Reset hardware to default state
   rp2040_usb_init();
 
@@ -373,9 +367,9 @@ void dcd_init (uint8_t rhport)
   irq_add_shared_handler(USBCTRL_IRQ, dcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY);
 
   // Init control endpoints
-  tu_memclr(hw_endpoints[0], 2*sizeof(hw_endpoint_t));
-  hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
-  hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
+  tu_memclr(hw_endpoints[0], 2 * sizeof(hw_endpoint_t));
+  hw_endpoint_open(0x0, 64, TUSB_XFER_CONTROL);
+  hw_endpoint_open(0x80, 64, TUSB_XFER_CONTROL);
 
   // Init non-control endpoints
   reset_non_control_endpoints();
@@ -388,27 +382,38 @@ void dcd_init (uint8_t rhport)
   // for the global interrupt enable...
   // Note: Force VBUS detect cause disconnection not detectable
   usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS;
-  usb_hw->inte     = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS |
-                     USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS |
-                     (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS);
+  usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS |
+                 USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS |
+                 (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS);
 
   dcd_connect(rhport);
+  return true;
 }
 
-void dcd_int_enable(__unused uint8_t rhport)
-{
-    assert(rhport == 0);
-    irq_set_enabled(USBCTRL_IRQ, true);
+bool dcd_deinit(uint8_t rhport) {
+  (void) rhport;
+
+  reset_non_control_endpoints();
+  irq_remove_handler(USBCTRL_IRQ, dcd_rp2040_irq);
+
+  // reset usb hardware into initial state
+  reset_block(RESETS_RESET_USBCTRL_BITS);
+  unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
+
+  return true;
 }
 
-void dcd_int_disable(__unused uint8_t rhport)
-{
-    assert(rhport == 0);
-    irq_set_enabled(USBCTRL_IRQ, false);
+void dcd_int_enable(__unused uint8_t rhport) {
+  assert(rhport == 0);
+  irq_set_enabled(USBCTRL_IRQ, true);
 }
 
-void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr)
-{
+void dcd_int_disable(__unused uint8_t rhport) {
+  assert(rhport == 0);
+  irq_set_enabled(USBCTRL_IRQ, false);
+}
+
+void dcd_set_address(__unused uint8_t rhport, __unused uint8_t dev_addr) {
   assert(rhport == 0);
 
   // Can't set device address in hardware until status xfer has complete
@@ -416,8 +421,7 @@ void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr)
   hw_endpoint_xfer(0x80, NULL, 0);
 }
 
-void dcd_remote_wakeup(__unused uint8_t rhport)
-{
+void dcd_remote_wakeup(__unused uint8_t rhport) {
   pico_info("dcd_remote_wakeup %d\n", rhport);
   assert(rhport == 0);
 
@@ -428,96 +432,113 @@ void dcd_remote_wakeup(__unused uint8_t rhport)
 }
 
 // disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(__unused uint8_t rhport)
-{
+void dcd_disconnect(__unused uint8_t rhport) {
   (void) rhport;
   usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
 }
 
 // connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(__unused uint8_t rhport)
-{
+void dcd_connect(__unused uint8_t rhport) {
   (void) rhport;
   usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
 }
 
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
   (void) rhport;
 
   _sof_enable = en;
 
-  if (en)
-  {
+  if (en) {
     usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
-  }else
-  {
+  }
+#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+  else {
+    // Don't clear immediately if the SOF workaround is in use.
+    // The SOF handler will conditionally disable the interrupt.
     usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
   }
+#endif
 }
 
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
 
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
-{
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) {
   (void) rhport;
 
-  if ( request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
-       request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
-       request->bRequest == TUSB_REQ_SET_ADDRESS )
-  {
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS) {
     usb_hw->dev_addr_ctrl = (uint8_t) request->wValue;
   }
 }
 
-bool dcd_edpt_open (__unused uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
-    assert(rhport == 0);
-    hw_endpoint_init(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer);
-    return true;
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
+  (void) rhport;
+  const uint8_t xfer_type = desc_edpt->bmAttributes.xfer;
+  TU_VERIFY(xfer_type != TUSB_XFER_ISOCHRONOUS);
+  hw_endpoint_open(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), xfer_type);
+  return true;
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
-{
+// New API: Allocate packet buffer used by ISO endpoints
+// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
+  (void) rhport;
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
+  hw_endpoint_init(ep_addr, largest_packet_size, TUSB_XFER_ISOCHRONOUS);
+  hw_endpoint_alloc(ep, largest_packet_size);
+  return true;
+}
+
+// New API: Configure and enable an ISO endpoint according to descriptor
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) {
+  (void) rhport;
+  const uint8_t ep_addr = ep_desc->bEndpointAddress;
+  // Fill in endpoint control register with buffer offset
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
+  TU_ASSERT(ep->hw_data_buf != NULL); // must be inited and buffer allocated
+  ep->wMaxPacketSize = ep_desc->wMaxPacketSize;
+
+  hw_endpoint_enable(ep);
+  return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport) {
   (void) rhport;
 
   // may need to use EP Abort
   reset_non_control_endpoints();
 }
 
-bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-    assert(rhport == 0);
-    hw_endpoint_xfer(ep_addr, buffer, total_bytes);
-    return true;
+bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+  assert(rhport == 0);
+  hw_endpoint_xfer(ep_addr, buffer, total_bytes);
+  return true;
 }
 
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
-  if ( tu_edpt_number(ep_addr) == 0 )
-  {
+  if (tu_edpt_number(ep_addr) == 0) {
     // A stall on EP0 has to be armed so it can be cleared on the next setup packet
-    usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
+    usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS
+                                                                     : USB_EP_STALL_ARM_EP0_OUT_BITS;
   }
 
-  struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
 
   // stall and clear current pending buffer
   // may need to use EP_ABORT
   _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_STALL);
 }
 
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
-  if (tu_edpt_number(ep_addr))
-  {
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+  if (tu_edpt_number(ep_addr)) {
+    struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
 
     // clear stall also reset toggle to DATA0, ready for next transfer
     ep->next_pid = 0;
@@ -525,16 +546,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   }
 }
 
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
-    (void) rhport;
-
-    pico_trace("dcd_edpt_close %02x\n", ep_addr);
-    hw_endpoint_close(ep_addr);
-}
-
-void __tusb_irq_path_func(dcd_int_handler)(uint8_t rhport)
-{
+void __tusb_irq_path_func(dcd_int_handler)(uint8_t rhport) {
   (void) rhport;
   dcd_rp2040_irq();
 }
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 10237d1f9..2c0a3fd49 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO_USB
+#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO_USB && !CFG_TUH_MAX3421
 
 #include "pico.h"
 #include "rp2040_usb.h"
@@ -56,9 +56,6 @@ static_assert(PICO_USB_HOST_INTERRUPT_ENDPOINTS <= USB_MAX_ENDPOINTS, "");
 static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
 #define epx (ep_pool[0])
 
-#define usb_hw_set   hw_set_alias(usb_hw)
-#define usb_hw_clear hw_clear_alias(usb_hw)
-
 // Flags we set by default in sie_ctrl (we add other bits on top)
 enum {
   SIE_CTRL_BASE = USB_SIE_CTRL_SOF_EN_BITS      | USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
@@ -81,89 +78,90 @@ static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
 
 TU_ATTR_ALWAYS_INLINE static inline uint8_t dev_speed(void)
 {
-    return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
+  return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
 }
 
-static bool need_pre(uint8_t dev_addr)
+TU_ATTR_ALWAYS_INLINE static inline bool need_pre(uint8_t dev_addr)
 {
-    // If this device is different to the speed of the root device
-    // (i.e. is a low speed device on a full speed hub) then need pre
-    return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
+  // If this device is different to the speed of the root device
+  // (i.e. is a low speed device on a full speed hub) then need pre
+  return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
 }
 
 static void __tusb_irq_path_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_result_t xfer_result)
 {
-    // Mark transfer as done before we tell the tinyusb stack
-    uint8_t dev_addr = ep->dev_addr;
-    uint8_t ep_addr = ep->ep_addr;
-    uint xferred_len = ep->xferred_len;
-    hw_endpoint_reset_transfer(ep);
-    hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
+  // Mark transfer as done before we tell the tinyusb stack
+  uint8_t dev_addr = ep->dev_addr;
+  uint8_t ep_addr = ep->ep_addr;
+  uint xferred_len = ep->xferred_len;
+  hw_endpoint_reset_transfer(ep);
+  hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
 }
 
 static void __tusb_irq_path_func(_handle_buff_status_bit)(uint bit, struct hw_endpoint *ep)
 {
-    usb_hw_clear->buf_status = bit;
-    // EP may have been stalled?
-    assert(ep->active);
-    bool done = hw_endpoint_xfer_continue(ep);
-    if (done)
-    {
-        hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
-    }
+  usb_hw_clear->buf_status = bit;
+  // EP may have been stalled?
+  assert(ep->active);
+  bool done = hw_endpoint_xfer_continue(ep);
+  if ( done )
+  {
+    hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
+  }
 }
 
 static void __tusb_irq_path_func(hw_handle_buff_status)(void)
 {
-    uint32_t remaining_buffers = usb_hw->buf_status;
-    pico_trace("buf_status 0x%08x\n", remaining_buffers);
+  uint32_t remaining_buffers = usb_hw->buf_status;
+  pico_trace("buf_status 0x%08lx\n", remaining_buffers);
 
-    // Check EPX first
-    uint bit = 0b1;
-    if (remaining_buffers & bit)
+  // Check EPX first
+  uint bit = 0b1;
+  if ( remaining_buffers & bit )
+  {
+    remaining_buffers &= ~bit;
+    struct hw_endpoint * ep = &epx;
+
+    uint32_t ep_ctrl = *ep->endpoint_control;
+    if ( ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS )
     {
+      TU_LOG(3, "Double Buffered: ");
+    }
+    else
+    {
+      TU_LOG(3, "Single Buffered: ");
+    }
+    TU_LOG_HEX(3, ep_ctrl);
+
+    _handle_buff_status_bit(bit, ep);
+  }
+
+  // Check "interrupt" (asynchronous) endpoints for both IN and OUT
+  for ( uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++ )
+  {
+    // EPX is bit 0 & 1
+    // IEP1 IN  is bit 2
+    // IEP1 OUT is bit 3
+    // IEP2 IN  is bit 4
+    // IEP2 OUT is bit 5
+    // IEP3 IN  is bit 6
+    // IEP3 OUT is bit 7
+    // etc
+    for ( uint j = 0; j < 2; j++ )
+    {
+      bit = 1 << (i * 2 + j);
+      if ( remaining_buffers & bit )
+      {
         remaining_buffers &= ~bit;
-        struct hw_endpoint *ep = &epx;
-
-        uint32_t ep_ctrl = *ep->endpoint_control;
-        if (ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS)
-        {
-          TU_LOG(3, "Double Buffered: ");
-        }else
-        {
-          TU_LOG(3, "Single Buffered: ");
-        }
-        TU_LOG_HEX(3, ep_ctrl);
-
-        _handle_buff_status_bit(bit, ep);
+        _handle_buff_status_bit(bit, &ep_pool[i]);
+      }
     }
+  }
 
-    // Check "interrupt" (asynchronous) endpoints for both IN and OUT
-    for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++)
-    {
-        // EPX is bit 0 & 1
-        // IEP1 IN  is bit 2
-        // IEP1 OUT is bit 3
-        // IEP2 IN  is bit 4
-        // IEP2 OUT is bit 5
-        // IEP3 IN  is bit 6
-        // IEP3 OUT is bit 7
-        // etc
-        for(uint j = 0; j < 2; j++)
-        {
-            bit = 1 << (i*2+j);
-            if (remaining_buffers & bit)
-            {
-                remaining_buffers &= ~bit;
-                _handle_buff_status_bit(bit, &ep_pool[i]);
-            }
-        }
-    }
-
-    if (remaining_buffers)
-    {
-        panic("Unhandled buffer %d\n", remaining_buffers);
-    }
+  if ( remaining_buffers )
+  {
+    panic("Unhandled buffer %d\n", remaining_buffers);
+  }
 }
 
 static void __tusb_irq_path_func(hw_trans_complete)(void)
@@ -186,198 +184,200 @@ static void __tusb_irq_path_func(hw_trans_complete)(void)
 
 static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
 {
-    uint32_t status = usb_hw->ints;
-    uint32_t handled = 0;
+  uint32_t status = usb_hw->ints;
+  uint32_t handled = 0;
 
-    if (status & USB_INTS_HOST_CONN_DIS_BITS)
+  if ( status & USB_INTS_HOST_CONN_DIS_BITS )
+  {
+    handled |= USB_INTS_HOST_CONN_DIS_BITS;
+
+    if ( dev_speed() )
     {
-        handled |= USB_INTS_HOST_CONN_DIS_BITS;
-        
-        if (dev_speed())
-        {
-            hcd_event_device_attach(RHPORT_NATIVE, true);
-        }
-        else
-        {
-            hcd_event_device_remove(RHPORT_NATIVE, true);
-        }
-
-        // Clear speed change interrupt
-        usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
+      hcd_event_device_attach(RHPORT_NATIVE, true);
+    }
+    else
+    {
+      hcd_event_device_remove(RHPORT_NATIVE, true);
     }
 
-    if (status & USB_INTS_STALL_BITS)
-    {
-        // We have rx'd a stall from the device
-        // NOTE THIS SHOULD HAVE PRIORITY OVER BUFF_STATUS
-        // AND TRANS_COMPLETE as the stall is an alternative response
-        // to one of those events
-        pico_trace("Stall REC\n");
-        handled |= USB_INTS_STALL_BITS;
-        usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
-        hw_xfer_complete(&epx, XFER_RESULT_STALLED);
-    }
+    // Clear speed change interrupt
+    usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
+  }
 
-    if (status & USB_INTS_BUFF_STATUS_BITS)
-    {
-        handled |= USB_INTS_BUFF_STATUS_BITS;
-        TU_LOG(2, "Buffer complete\n");
-        hw_handle_buff_status();
-    }
+  if ( status & USB_INTS_STALL_BITS )
+  {
+    // We have rx'd a stall from the device
+    // NOTE THIS SHOULD HAVE PRIORITY OVER BUFF_STATUS
+    // AND TRANS_COMPLETE as the stall is an alternative response
+    // to one of those events
+    pico_trace("Stall REC\n");
+    handled |= USB_INTS_STALL_BITS;
+    usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
+    hw_xfer_complete(&epx, XFER_RESULT_STALLED);
+  }
 
-    if (status & USB_INTS_TRANS_COMPLETE_BITS)
-    {
-        handled |= USB_INTS_TRANS_COMPLETE_BITS;
-        usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
-        TU_LOG(2, "Transfer complete\n");
-        hw_trans_complete();
-    }
+  if ( status & USB_INTS_BUFF_STATUS_BITS )
+  {
+    handled |= USB_INTS_BUFF_STATUS_BITS;
+    TU_LOG(2, "Buffer complete\r\n");
+    hw_handle_buff_status();
+  }
 
-    if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS)
-    {
-        handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
-        usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS;
-    }
+  if ( status & USB_INTS_TRANS_COMPLETE_BITS )
+  {
+    handled |= USB_INTS_TRANS_COMPLETE_BITS;
+    usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
+    TU_LOG(2, "Transfer complete\r\n");
+    hw_trans_complete();
+  }
 
-    if (status & USB_INTS_ERROR_DATA_SEQ_BITS)
-    {
-        usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
-        TU_LOG(3, "  Seq Error: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(*epx.buffer_control), tu_u32_high16(*epx.buffer_control));
-        panic("Data Seq Error \n");
-    }
+  if ( status & USB_INTS_ERROR_RX_TIMEOUT_BITS )
+  {
+    handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
+    usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS;
+  }
 
-    if (status ^ handled)
-    {
-        panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
-    }
+  if ( status & USB_INTS_ERROR_DATA_SEQ_BITS )
+  {
+    usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
+    TU_LOG(3, "  Seq Error: [0] = 0x%04u  [1] = 0x%04x\r\n",
+           tu_u32_low16(*epx.buffer_control),
+           tu_u32_high16(*epx.buffer_control));
+    panic("Data Seq Error \n");
+  }
+
+  if ( status ^ handled )
+  {
+    panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
+  }
 }
 
-void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport)
-{
+void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport, bool in_isr) {
   (void) rhport;
+  (void) in_isr;
   hcd_rp2040_irq();
 }
 
 static struct hw_endpoint *_next_free_interrupt_ep(void)
 {
-    struct hw_endpoint *ep = NULL;
-    for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++)
+  struct hw_endpoint * ep = NULL;
+  for ( uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++ )
+  {
+    ep = &ep_pool[i];
+    if ( !ep->configured )
     {
-        ep = &ep_pool[i];
-        if (!ep->configured)
-        {
-            // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
-            ep->interrupt_num = (uint8_t) (i - 1);
-            return ep;
-        }
+      // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
+      ep->interrupt_num = (uint8_t) (i - 1);
+      return ep;
     }
-    return ep;
+  }
+  return ep;
 }
 
 static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
 {
-    struct hw_endpoint *ep = NULL;
+  struct hw_endpoint * ep = NULL;
 
-    if (transfer_type != TUSB_XFER_CONTROL)
-    {
-        // Note: even though datasheet name these "Interrupt" endpoints. These are actually
-        // "Asynchronous" endpoints and can be used for other type such as: Bulk  (ISO need confirmation)
-        ep = _next_free_interrupt_ep();
-        pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
-        assert(ep);
-        ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
-        ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
-        // 0 for epx (double buffered): TODO increase to 1024 for ISO
-        // 2x64 for intep0
-        // 3x64 for intep1
-        // etc
-        ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)];
-    }
-    else
-    {
-        ep = &epx;
-        ep->buffer_control = &usbh_dpram->epx_buf_ctrl;
-        ep->endpoint_control = &usbh_dpram->epx_ctrl;
-        ep->hw_data_buf = &usbh_dpram->epx_data[0];
-    }
+  if ( transfer_type != TUSB_XFER_CONTROL )
+  {
+    // Note: even though datasheet name these "Interrupt" endpoints. These are actually
+    // "Asynchronous" endpoints and can be used for other type such as: Bulk  (ISO need confirmation)
+    ep = _next_free_interrupt_ep();
+    pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
+    assert(ep);
+    ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
+    ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
+    // 0 for epx (double buffered): TODO increase to 1024 for ISO
+    // 2x64 for intep0
+    // 3x64 for intep1
+    // etc
+    ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)];
+  }
+  else
+  {
+    ep = &epx;
+    ep->buffer_control = &usbh_dpram->epx_buf_ctrl;
+    ep->endpoint_control = &usbh_dpram->epx_ctrl;
+    ep->hw_data_buf = &usbh_dpram->epx_data[0];
+  }
 
-    return ep;
+  return ep;
 }
 
 static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
 {
-    // Already has data buffer, endpoint control, and buffer control allocated at this point
-    assert(ep->endpoint_control);
-    assert(ep->buffer_control);
-    assert(ep->hw_data_buf);
+  // Already has data buffer, endpoint control, and buffer control allocated at this point
+  assert(ep->endpoint_control);
+  assert(ep->buffer_control);
+  assert(ep->hw_data_buf);
 
-    uint8_t const num = tu_edpt_number(ep_addr);
-    tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+  uint8_t const num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
 
-    ep->ep_addr = ep_addr;
-    ep->dev_addr = dev_addr;
+  ep->ep_addr = ep_addr;
+  ep->dev_addr = dev_addr;
 
-    // For host, IN to host == RX, anything else rx == false
-    ep->rx = (dir == TUSB_DIR_IN);
+  // For host, IN to host == RX, anything else rx == false
+  ep->rx = (dir == TUSB_DIR_IN);
 
-    // Response to a setup packet on EP0 starts with pid of 1
-    ep->next_pid = (num == 0 ? 1u : 0u);
-    ep->wMaxPacketSize = wMaxPacketSize;
-    ep->transfer_type = transfer_type;
+  // Response to a setup packet on EP0 starts with pid of 1
+  ep->next_pid = (num == 0 ? 1u : 0u);
+  ep->wMaxPacketSize = wMaxPacketSize;
+  ep->transfer_type = transfer_type;
 
-    pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type);
-    pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf);
-    uint dpram_offset = hw_data_offset(ep->hw_data_buf);
-    // Bits 0-5 should be 0
-    assert(!(dpram_offset & 0b111111));
+  pico_trace("hw_endpoint_init dev %d ep %02X xfer %d\n", ep->dev_addr, ep->ep_addr, ep->transfer_type);
+  pico_trace("dev %d ep %02X setup buffer @ 0x%p\n", ep->dev_addr, ep->ep_addr, ep->hw_data_buf);
+  uint dpram_offset = hw_data_offset(ep->hw_data_buf);
+  // Bits 0-5 should be 0
+  assert(!(dpram_offset & 0b111111));
 
-    // Fill in endpoint control register with buffer offset
-    uint32_t ep_reg =  EP_CTRL_ENABLE_BITS
-                  | EP_CTRL_INTERRUPT_PER_BUFFER
-                  | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
-                  | dpram_offset;
-    if (bmInterval)
+  // Fill in endpoint control register with buffer offset
+  uint32_t ep_reg = EP_CTRL_ENABLE_BITS
+                    | EP_CTRL_INTERRUPT_PER_BUFFER
+                    | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
+                    | dpram_offset;
+  if ( bmInterval )
+  {
+    ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
+  }
+  *ep->endpoint_control = ep_reg;
+  pico_trace("endpoint control (0x%p) <- 0x%lx\n", ep->endpoint_control, ep_reg);
+  ep->configured = true;
+
+  if ( ep != &epx )
+  {
+    // Endpoint has its own addr_endp and interrupt bits to be setup!
+    // This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with:
+    // - device address
+    // - endpoint number / direction
+    // - preamble
+    uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
+
+    if ( dir == TUSB_DIR_OUT )
     {
-      ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
+      reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS;
     }
-    *ep->endpoint_control = ep_reg;
-    pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
-    ep->configured = true;
 
-    if (ep != &epx)
+    if ( need_pre(dev_addr) )
     {
-        // Endpoint has its own addr_endp and interrupt bits to be setup!
-        // This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with:
-        // - device address
-        // - endpoint number / direction
-        // - preamble
-        uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
-
-        if (dir == TUSB_DIR_OUT)
-        {
-            reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS;
-        }
-
-        if (need_pre(dev_addr))
-        {
-            reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS;
-        }
-        usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg;
-
-        // Finally, enable interrupt that endpoint
-        usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1);
-
-        // If it's an interrupt endpoint we need to set up the buffer control
-        // register
+      reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS;
     }
+    usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg;
+
+    // Finally, enable interrupt that endpoint
+    usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1);
+
+    // If it's an interrupt endpoint we need to set up the buffer control
+    // register
+  }
 }
 
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
-bool hcd_init(uint8_t rhport)
-{
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
   pico_trace("hcd_init %d\n", rhport);
   assert(rhport == 0);
 
@@ -409,6 +409,16 @@ bool hcd_init(uint8_t rhport)
   return true;
 }
 
+bool hcd_deinit(uint8_t rhport) {
+  (void) rhport;
+
+  irq_remove_handler(USBCTRL_IRQ, hcd_rp2040_irq);
+  reset_block(RESETS_RESET_USBCTRL_BITS);
+  unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
+
+  return true;
+}
+
 void hcd_port_reset(uint8_t rhport)
 {
   (void) rhport;
@@ -434,16 +444,17 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void) rhport;
   assert(rhport == 0);
+
   // TODO: Should enumval this register
-  switch (dev_speed())
+  switch ( dev_speed() )
   {
-      case 1:
-          return TUSB_SPEED_LOW;
-      case 2:
-          return TUSB_SPEED_FULL;
-      default:
-          panic("Invalid speed\n");
-          return TUSB_SPEED_INVALID;
+    case 1:
+      return TUSB_SPEED_LOW;
+    case 2:
+      return TUSB_SPEED_FULL;
+    default:
+      panic("Invalid speed\n");
+      // return TUSB_SPEED_INVALID;
   }
 }
 
@@ -476,8 +487,8 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 
 uint32_t hcd_frame_number(uint8_t rhport)
 {
-    (void) rhport;
-    return usb_hw->sof_rd;
+  (void) rhport;
+  return usb_hw->sof_rd;
 }
 
 void hcd_int_enable(uint8_t rhport)
@@ -501,117 +512,134 @@ void hcd_int_disable(uint8_t rhport)
 
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
-    (void) rhport;
+  (void) rhport;
 
-    pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
+  pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
 
-    // Allocated differently based on if it's an interrupt endpoint or not
-    struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
-    TU_ASSERT(ep);
+  // Allocated differently based on if it's an interrupt endpoint or not
+  struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
+  TU_ASSERT(ep);
 
-    _hw_endpoint_init(ep,
-        dev_addr,
-        ep_desc->bEndpointAddress,
-        tu_edpt_packet_size(ep_desc),
-        ep_desc->bmAttributes.xfer,
-        ep_desc->bInterval);
+  _hw_endpoint_init(ep,
+                    dev_addr,
+                    ep_desc->bEndpointAddress,
+                    tu_edpt_packet_size(ep_desc),
+                    ep_desc->bmAttributes.xfer,
+                    ep_desc->bInterval);
 
-    return true;
+  return true;
 }
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
-    (void) rhport;
+  (void) rhport;
 
-    pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
-    
-    uint8_t const ep_num = tu_edpt_number(ep_addr);
-    tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
+  pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
 
-    // Get appropriate ep. Either EPX or interrupt endpoint
-    struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
 
-    TU_ASSERT(ep);
+  // Get appropriate ep. Either EPX or interrupt endpoint
+  struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
 
-    // EP should be inactive
-    assert(!ep->active);
+  TU_ASSERT(ep);
 
-    // Control endpoint can change direction 0x00 <-> 0x80
-    if ( ep_addr != ep->ep_addr )
-    {
-      assert(ep_num == 0);
+  // EP should be inactive
+  assert(!ep->active);
 
-      // Direction has flipped on endpoint control so re init it but with same properties
-      _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
-    }
+  // Control endpoint can change direction 0x00 <-> 0x80
+  if ( ep_addr != ep->ep_addr )
+  {
+    assert(ep_num == 0);
 
-    // If a normal transfer (non-interrupt) then initiate using
-    // sie ctrl registers. Otherwise interrupt ep registers should
-    // already be configured
-    if (ep == &epx) {
-        hw_endpoint_xfer_start(ep, buffer, buflen);
+    // Direction has flipped on endpoint control so re init it but with same properties
+    _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
+  }
 
-        // That has set up buffer control, endpoint control etc
-        // for host we have to initiate the transfer
-        usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB));
+  // If a normal transfer (non-interrupt) then initiate using
+  // sie ctrl registers. Otherwise interrupt ep registers should
+  // already be configured
+  if ( ep == &epx )
+  {
+    hw_endpoint_xfer_start(ep, buffer, buflen);
 
-        uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
-                         (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS);
-        // Set pre if we are a low speed device on full speed hub
-        flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
+    // That has set up buffer control, endpoint control etc
+    // for host we have to initiate the transfer
+    usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB));
 
-        usb_hw->sie_ctrl = flags;
-    }else
-    {
-      hw_endpoint_xfer_start(ep, buffer, buflen);
-    }
+    uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
+                     (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS) |
+                     (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
+    // START_TRANS bit on SIE_CTRL seems to exhibit the same behavior as the AVAILABLE bit
+    // described in RP2040 Datasheet, release 2.1, section "4.1.2.5.1. Concurrent access".
+    // We write everything except the START_TRANS bit first, then wait some cycles.
+    usb_hw->sie_ctrl = flags & ~USB_SIE_CTRL_START_TRANS_BITS;
+    busy_wait_at_least_cycles(12);
+    usb_hw->sie_ctrl = flags;
+  }else
+  {
+    hw_endpoint_xfer_start(ep, buffer, buflen);
+  }
 
-    return true;
+  return true;
+}
+
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
 }
 
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
-    (void) rhport;
+  (void) rhport;
 
-    // Copy data into setup packet buffer
-    for(uint8_t i=0; i<8; i++)
-    {
-      usbh_dpram->setup_packet[i] = setup_packet[i];
-    }
+  // Copy data into setup packet buffer
+  for ( uint8_t i = 0; i < 8; i++ )
+  {
+    usbh_dpram->setup_packet[i] = setup_packet[i];
+  }
 
-    // Configure EP0 struct with setup info for the trans complete
-    struct hw_endpoint *ep = _hw_endpoint_allocate(0);
-    TU_ASSERT(ep);
+  // Configure EP0 struct with setup info for the trans complete
+  struct hw_endpoint * ep = _hw_endpoint_allocate(0);
+  TU_ASSERT(ep);
 
-    // EPX should be inactive
-    assert(!ep->active);
+  // EPX should be inactive
+  assert(!ep->active);
 
-    // EP0 out
-    _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
-    assert(ep->configured);
+  // EP0 out
+  _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
+  assert(ep->configured);
 
-    ep->remaining_len = 8;
-    ep->active        = true;
+  ep->remaining_len = 8;
+  ep->active = true;
 
-    // Set device address
-    usb_hw->dev_addr_ctrl = dev_addr;
+  // Set device address
+  usb_hw->dev_addr_ctrl = dev_addr;
 
-    // Set pre if we are a low speed device on full speed hub
-    uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
-                           (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
+  // Set pre if we are a low speed device on full speed hub
+  uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
+                         (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
 
-    usb_hw->sie_ctrl = flags;
+  // START_TRANS bit on SIE_CTRL seems to exhibit the same behavior as the AVAILABLE bit
+  // described in RP2040 Datasheet, release 2.1, section "4.1.2.5.1. Concurrent access".
+  // We write everything except the START_TRANS bit first, then wait some cycles.
+  usb_hw->sie_ctrl = flags & ~USB_SIE_CTRL_START_TRANS_BITS;
+  busy_wait_at_least_cycles(12);
+  usb_hw->sie_ctrl = flags;
 
-    return true;
+  return true;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
-    (void) dev_addr;
-    (void) ep_addr;
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
 
-    panic("hcd_clear_stall");
-    return true;
+  panic("hcd_clear_stall");
+  // return true;
 }
 
 #endif
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 25c013bd2..43f48da39 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -32,88 +32,97 @@
 #include <stdlib.h>
 #include "rp2040_usb.h"
 
-// Direction strings for debug
-const char *ep_dir_string[] = {
-        "out",
-        "in",
-};
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPE
+//--------------------------------------------------------------------+
+static void _hw_endpoint_xfer_sync(struct hw_endpoint* ep);
 
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) {
-    // todo add critsec as necessary to prevent issues between worker and IRQ...
-    //  note that this is perhaps as simple as disabling IRQs because it would make
-    //  sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+  static bool e15_is_bulkin_ep(struct hw_endpoint* ep);
+  static bool e15_is_critical_frame_period(struct hw_endpoint* ep);
+#else
+  #define e15_is_bulkin_ep(x)             (false)
+  #define e15_is_critical_frame_period(x) (false)
+#endif
+
+// if usb hardware is in host mode
+TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) {
+  return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false;
 }
 
-static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
-static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
-
 //--------------------------------------------------------------------+
-//
+// Implementation
 //--------------------------------------------------------------------+
+// Provide own byte by byte memcpy as not all copies are aligned
+static void unaligned_memcpy(void *dst, const void *src, size_t n) {
+  uint8_t *dst_byte = (uint8_t*)dst;
+  const uint8_t *src_byte = (const uint8_t*)src;
+  while (n--) {
+    *dst_byte++ = *src_byte++;
+  }
+}
 
-void rp2040_usb_init(void)
-{
+void rp2040_usb_init(void) {
   // Reset usb controller
   reset_block(RESETS_RESET_USBCTRL_BITS);
   unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
 
+#ifdef __GNUC__
   // Clear any previous state just in case
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Warray-bounds"
 #if __GNUC__ > 6
 #pragma GCC diagnostic ignored "-Wstringop-overflow"
 #endif
-  memset(usb_hw, 0, sizeof(*usb_hw));
+#endif
   memset(usb_dpram, 0, sizeof(*usb_dpram));
+#ifdef __GNUC__
 #pragma GCC diagnostic pop
+#endif
 
   // Mux the controller to the onboard usb phy
   usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
+
+  TU_LOG2_INT(sizeof(hw_endpoint_t));
 }
 
-void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
-{
+void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint* ep) {
   ep->active = false;
   ep->remaining_len = 0;
   ep->xferred_len = 0;
   ep->user_buf = 0;
 }
 
-void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
-    uint32_t value = 0;
-    if (and_mask) {
-        value = *ep->buffer_control & and_mask;
+void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint* ep, uint32_t and_mask,
+                                                               uint32_t or_mask) {
+  uint32_t value = 0;
+
+  if (and_mask) {
+    value = *ep->buffer_control & and_mask;
+  }
+
+  if (or_mask) {
+    value |= or_mask;
+    if (or_mask & USB_BUF_CTRL_AVAIL) {
+      if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) {
+        panic("ep %02X was already available", ep->ep_addr);
+      }
+      *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
+      // 4.1.2.5.1 Con-current access: 12 cycles (should be good for 48*12Mhz = 576Mhz) after write to buffer control
+      // Don't need delay in host mode as host is in charge
+      if ( !is_host_mode()) {
+        busy_wait_at_least_cycles(12);
+      }
     }
-    if (or_mask) {
-        value |= or_mask;
-        if (or_mask & USB_BUF_CTRL_AVAIL) {
-            if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) {
-                panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
-            }
-            *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
-            // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz)
-            // Don't need delay in host mode as host is in charge
-#if !CFG_TUH_ENABLED
-            __asm volatile (
-                    "b 1f\n"
-                    "1: b 1f\n"
-                    "1: b 1f\n"
-                    "1: b 1f\n"
-                    "1: b 1f\n"
-                    "1: b 1f\n"
-                    "1:\n"
-                    : : : "memory");
-#endif
-        }
-    }
-    *ep->buffer_control = value;
+  }
+
+  *ep->buffer_control = value;
 }
 
 // prepare buffer, return buffer control
-static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
-{
+static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint* ep, uint8_t buf_id) {
   uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
-  ep->remaining_len = (uint16_t)(ep->remaining_len - buflen);
+  ep->remaining_len = (uint16_t) (ep->remaining_len - buflen);
 
   uint32_t buf_ctrl = buflen | USB_BUF_CTRL_AVAIL;
 
@@ -121,10 +130,9 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep,
   buf_ctrl |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
   ep->next_pid ^= 1u;
 
-  if ( !ep->rx )
-  {
+  if (!ep->rx) {
     // Copy data from user buffer to hw buffer
-    memcpy(ep->hw_data_buf + buf_id*64, ep->user_buf, buflen);
+    unaligned_memcpy(ep->hw_data_buf + buf_id * 64, ep->user_buf, buflen);
     ep->user_buf += buflen;
 
     // Mark as full
@@ -134,8 +142,7 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep,
   // Is this the last buffer? Only really matters for host mode. Will trigger
   // the trans complete irq but also stop it polling. We only really care about
   // trans complete for setup packets being sent
-  if (ep->remaining_len == 0)
-  {
+  if (ep->remaining_len == 0) {
     buf_ctrl |= USB_BUF_CTRL_LAST;
   }
 
@@ -145,20 +152,22 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep,
 }
 
 // Prepare buffer control register value
-static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
-{
+void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint* ep) {
   uint32_t ep_ctrl = *ep->endpoint_control;
 
   // always compute and start with buffer 0
   uint32_t buf_ctrl = prepare_ep_buffer(ep, 0) | USB_BUF_CTRL_SEL;
 
-  // For now: skip double buffered for Device mode, OUT endpoint since
+  // For now: skip double buffered for OUT endpoint in Device mode, since
   // host could send < 64 bytes and cause short packet on buffer0
-  // NOTE this could happen to Host mode IN endpoint
-  bool const force_single = !(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr);
+  // NOTE: this could happen to Host mode IN endpoint
+  // Also, Host mode "interrupt" endpoint hardware is only single buffered,
+  // NOTE2: Currently Host bulk is implemented using "interrupt" endpoint
+  bool const is_host = is_host_mode();
+  bool const force_single = (!is_host && !tu_edpt_dir(ep->ep_addr)) ||
+                            (is_host && tu_edpt_number(ep->ep_addr) != 0);
 
-  if(ep->remaining_len && !force_single)
-  {
+  if (ep->remaining_len && !force_single) {
     // Use buffer 1 (double buffered) if there is still data
     // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt)
 
@@ -167,8 +176,7 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo
     // Set endpoint control double buffered bit if needed
     ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;
     ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER;
-  }else
-  {
+  } else {
     // Single buffered since 1 is enough
     ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
     ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
@@ -183,59 +191,60 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo
   _hw_endpoint_buffer_control_set_value32(ep, buf_ctrl);
 }
 
-void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
-{
-  _hw_endpoint_lock_update(ep, 1);
+void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t total_len) {
+  hw_endpoint_lock_update(ep, 1);
 
-  if ( ep->active )
-  {
+  if (ep->active) {
     // TODO: Is this acceptable for interrupt packets?
-    TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\n", tu_edpt_number(ep->ep_addr),
-              ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
-
+    TU_LOG(1, "WARN: starting new transfer on already active ep %02X\r\n", ep->ep_addr);
     hw_endpoint_reset_transfer(ep);
   }
 
   // Fill in info now that we're kicking off the hw
   ep->remaining_len = total_len;
-  ep->xferred_len   = 0;
-  ep->active        = true;
-  ep->user_buf      = buffer;
+  ep->xferred_len = 0;
+  ep->active = true;
+  ep->user_buf = buffer;
 
-  _hw_endpoint_start_next_buffer(ep);
-  _hw_endpoint_lock_update(ep, -1);
+  if (e15_is_bulkin_ep(ep)) {
+    usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
+  }
+
+  if (e15_is_critical_frame_period(ep)) {
+    ep->pending = 1;
+  } else {
+    hw_endpoint_start_next_buffer(ep);
+  }
+
+  hw_endpoint_lock_update(ep, -1);
 }
 
 // sync endpoint buffer and return transferred bytes
-static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
-{
+static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint* ep, uint8_t buf_id) {
   uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
-  if (buf_id)  buf_ctrl = buf_ctrl >> 16;
+  if (buf_id) buf_ctrl = buf_ctrl >> 16;
 
   uint16_t xferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
 
-  if ( !ep->rx )
-  {
+  if (!ep->rx) {
     // We are continuing a transfer here. If we are TX, we have successfully
     // sent some data can increase the length we have sent
     assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
 
-    ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes);
-  }else
-  {
+    ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes);
+  } else {
     // If we have received some data, so can increase the length
     // we have received AFTER we have copied it to the user buffer at the appropriate offset
     assert(buf_ctrl & USB_BUF_CTRL_FULL);
 
-    memcpy(ep->user_buf, ep->hw_data_buf + buf_id*64, xferred_bytes);
-    ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes);
+    unaligned_memcpy(ep->user_buf, ep->hw_data_buf + buf_id * 64, xferred_bytes);
+    ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes);
     ep->user_buf += xferred_bytes;
   }
 
   // Short packet
-  if (xferred_bytes < ep->wMaxPacketSize)
-  {
-    pico_trace("  Short packet on buffer %d with %u bytes\n", buf_id, xferred_bytes);
+  if (xferred_bytes < ep->wMaxPacketSize) {
+    pico_trace("  Short packet on buffer %d with %u bytes\r\n", buf_id, xferred_bytes);
     // Reduce total length as this is last packet
     ep->remaining_len = 0;
   }
@@ -243,8 +252,7 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uin
   return xferred_bytes;
 }
 
-static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep)
-{
+static void __tusb_irq_path_func(_hw_endpoint_xfer_sync)(struct hw_endpoint* ep) {
   // Update hw endpoint struct with info from hardware
   // after a buff status interrupt
 
@@ -255,14 +263,11 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep
   uint16_t buf0_bytes = sync_ep_buffer(ep, 0);
 
   // sync buffer 1 if double buffered
-  if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
-  {
-    if (buf0_bytes == ep->wMaxPacketSize)
-    {
+  if ((*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS) {
+    if (buf0_bytes == ep->wMaxPacketSize) {
       // sync buffer 1 if not short packet
       sync_ep_buffer(ep, 1);
-    }else
-    {
+    } else {
       // short packet on buffer 0
       // TODO couldn't figure out how to handle this case which happen with net_lwip_webserver example
       // At this time (currently trigger per 2 buffer), the buffer1 is probably filled with data from
@@ -294,13 +299,12 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep
 }
 
 // Returns true if transfer is complete
-bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
-{
-  _hw_endpoint_lock_update(ep, 1);
+bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) {
+  hw_endpoint_lock_update(ep, 1);
+
   // Part way through a transfer
-  if (!ep->active)
-  {
-    panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+  if (!ep->active) {
+    panic("Can't continue xfer on inactive ep %02X", ep->ep_addr);
   }
 
   // Update EP struct from hardware state
@@ -308,22 +312,71 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
 
   // Now we have synced our state with the hardware. Is there more data to transfer?
   // If we are done then notify tinyusb
-  if (ep->remaining_len == 0)
-  {
-    pico_trace("Completed transfer of %d bytes on ep %d %s\n",
-               ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+  if (ep->remaining_len == 0) {
+    pico_trace("Completed transfer of %d bytes on ep %02X\r\n", ep->xferred_len, ep->ep_addr);
     // Notify caller we are done so it can notify the tinyusb stack
-    _hw_endpoint_lock_update(ep, -1);
+    hw_endpoint_lock_update(ep, -1);
     return true;
-  }
-  else
-  {
-    _hw_endpoint_start_next_buffer(ep);
+  } else {
+    if (e15_is_critical_frame_period(ep)) {
+      ep->pending = 1;
+    } else {
+      hw_endpoint_start_next_buffer(ep);
+    }
   }
 
-  _hw_endpoint_lock_update(ep, -1);
+  hw_endpoint_lock_update(ep, -1);
   // More work to do
   return false;
 }
 
+//--------------------------------------------------------------------+
+// Errata 15
+//--------------------------------------------------------------------+
+
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+
+/* Don't mark IN buffers as available during the last 200us of a full-speed
+   frame. This avoids a situation seen with the USB2.0 hub on a Raspberry
+   Pi 4 where a late IN token before the next full-speed SOF can cause port
+   babble and a corrupt ACK packet. The nature of the data corruption has a
+   chance to cause device lockup.
+
+   Use the next SOF to mark delayed buffers as available. This reduces
+   available Bulk IN bandwidth by approximately 20%, and requires that the
+   SOF interrupt is enabled while these transfers are ongoing.
+
+   Inherit the top-level enable from the corresponding Pico-SDK flag.
+   Applications that will not use the device in a situation where it could
+   be plugged into a Pi 4 or Pi 400 (for example, when directly connected
+   to a commodity hub or other host) can turn off the flag in the SDK.
+*/
+
+volatile uint32_t e15_last_sof = 0;
+
+// check if Errata 15 is needed for this endpoint i.e device bulk-in
+static bool __tusb_irq_path_func(e15_is_bulkin_ep)(struct hw_endpoint* ep) {
+  return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
+          ep->transfer_type == TUSB_XFER_BULK);
+}
+
+// check if we need to apply Errata 15 workaround : i.e
+// Endpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame
+static bool __tusb_irq_path_func(e15_is_critical_frame_period)(struct hw_endpoint* ep) {
+  TU_VERIFY(e15_is_bulkin_ep(ep));
+
+  /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point.
+   * The device state machine cannot recover from receiving an incorrect PID
+   * when it is expecting an ACK.
+   */
+  uint32_t delta = time_us_32() - e15_last_sof;
+  if (delta < 800 || delta > 998) {
+    return false;
+  }
+  TU_LOG(3, "Avoiding sof %lu now %lu last %lu\r\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(),
+         e15_last_sof);
+  return true;
+}
+
+#endif // TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
 #endif
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index c72dae64c..d4d29a816 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -11,11 +11,21 @@
 #include "hardware/structs/usb.h"
 #include "hardware/irq.h"
 #include "hardware/resets.h"
+#include "hardware/timer.h"
 
 #if defined(PICO_RP2040_USB_DEVICE_ENUMERATION_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX)
 #define TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX PICO_RP2040_USB_DEVICE_ENUMERATION_FIX
 #endif
 
+#if defined(PICO_RP2040_USB_DEVICE_UFRAME_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX)
+#define TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX PICO_RP2040_USB_DEVICE_UFRAME_FIX
+#endif
+
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+#undef PICO_RP2040_USB_FAST_IRQ
+#define PICO_RP2040_USB_FAST_IRQ 1
+#endif
+
 #ifndef PICO_RP2040_USB_FAST_IRQ
 #define PICO_RP2040_USB_FAST_IRQ 0
 #endif
@@ -26,6 +36,9 @@
 #define __tusb_irq_path_func(x) x
 #endif
 
+#define usb_hw_set    ((usb_hw_t *) hw_set_alias_untyped(usb_hw))
+#define usb_hw_clear  ((usb_hw_t *) hw_clear_alias_untyped(usb_hw))
+
 #define pico_info(...)  TU_LOG(2, __VA_ARGS__)
 #define pico_trace(...) TU_LOG(3, __VA_ARGS__)
 
@@ -34,11 +47,11 @@ typedef struct hw_endpoint
 {
     // Is this a valid struct
     bool configured;
-    
+
     // Transfer direction (i.e. IN is rx for host but tx for device)
     // allows us to common up transfer functions
     bool rx;
-    
+
     uint8_t ep_addr;
     uint8_t next_pid;
 
@@ -51,20 +64,25 @@ typedef struct hw_endpoint
     // Buffer pointer in usb dpram
     uint8_t *hw_data_buf;
 
-    // Current transfer information
-    bool active;
-    uint16_t remaining_len;
-    uint16_t xferred_len;
-
     // User buffer in main memory
     uint8_t *user_buf;
 
+    // Current transfer information
+    uint16_t remaining_len;
+    uint16_t xferred_len;
+
     // Data needed from EP descriptor
     uint16_t wMaxPacketSize;
 
+    // Endpoint is in use
+    bool active;
+
     // Interrupt, bulk, etc
     uint8_t transfer_type;
-    
+
+    // Transfer scheduled but not active
+    uint8_t pending;
+
 #if CFG_TUH_ENABLED
     // Only needed for host
     uint8_t dev_addr;
@@ -72,36 +90,52 @@ typedef struct hw_endpoint
     // If interrupt endpoint
     uint8_t interrupt_num;
 #endif
+
 } hw_endpoint_t;
 
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+extern volatile uint32_t e15_last_sof;
+#endif
+
 void rp2040_usb_init(void);
 
 void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len);
 bool hw_endpoint_xfer_continue(struct hw_endpoint *ep);
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
+void hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
+
+TU_ATTR_ALWAYS_INLINE static inline void hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) {
+  // todo add critsec as necessary to prevent issues between worker and IRQ...
+  //  note that this is perhaps as simple as disabling IRQs because it would make
+  //  sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
+}
 
 void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) {
-    return *ep->buffer_control;
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) {
-    return _hw_endpoint_buffer_control_update32(ep, 0, value);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) {
-    return _hw_endpoint_buffer_control_update32(ep, ~value, value);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) {
-    return _hw_endpoint_buffer_control_update32(ep, ~value, 0);
-}
-
-static inline uintptr_t hw_data_offset(uint8_t *buf)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32 (struct hw_endpoint *ep)
 {
-    // Remove usb base from buffer pointer
-    return (uintptr_t)buf ^ (uintptr_t)usb_dpram;
+  return *ep->buffer_control;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32 (struct hw_endpoint *ep, uint32_t value)
+{
+  _hw_endpoint_buffer_control_update32(ep, 0, value);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32 (struct hw_endpoint *ep, uint32_t value)
+{
+  _hw_endpoint_buffer_control_update32(ep, ~value, value);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32 (struct hw_endpoint *ep, uint32_t value)
+{
+  _hw_endpoint_buffer_control_update32(ep, ~value, 0);
+}
+
+static inline uintptr_t hw_data_offset (uint8_t *buf)
+{
+  // Remove usb base from buffer pointer
+  return (uintptr_t) buf ^ (uintptr_t) usb_dpram;
 }
 
 extern const char *ep_dir_string[];
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
new file mode 100644
index 000000000..ecd28973c
--- /dev/null
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -0,0 +1,1032 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Koji Kitayama
+ * Portions copyrighted (c) 2021 Roland Winistoerfer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2)
+
+#include "device/dcd.h"
+#include "rusb2_type.h"
+
+#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+  #include "rusb2_rx.h"
+#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
+  #include "rusb2_ra.h"
+  #if defined(RENESAS_CORTEX_M23)
+    #define D0FIFO CFIFO
+    #define D0FIFOSEL CFIFOSEL
+    #define D0FIFOSEL_b CFIFOSEL_b
+    #define D1FIFOSEL CFIFOSEL
+    #define D1FIFOSEL_b CFIFOSEL_b
+    #define D0FIFOCTR CFIFOCTR
+    #define D0FIFOCTR_b CFIFOCTR_b
+  #endif
+
+#else
+  #error "Unsupported MCU"
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+enum {
+  PIPE_COUNT = 10,
+};
+
+typedef struct {
+  void      *buf;      /* the start address of a transfer data buffer */
+  uint16_t  length;    /* the number of bytes in the buffer */
+  uint16_t  remaining; /* the number of bytes remaining in the buffer */
+
+  uint8_t ep; /* an assigned endpoint address */
+  uint8_t ff; /* `buf` is TU_FUFO or POD */
+} pipe_state_t;
+
+typedef struct
+{
+  pipe_state_t pipe[PIPE_COUNT];
+  uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
+  // Track whether sof has been manually enabled
+  bool sof_enabled;
+} dcd_data_t;
+
+static dcd_data_t _dcd;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+
+
+// Transfer conditions specifiable for each pipe for most MCUs
+// - Pipe 0: Control transfer with 64-byte single buffer
+// - Pipes 1 and 2: Bulk or ISO
+// - Pipes 3 to 5: Bulk
+// - Pipes 6 to 9: Interrupt
+//
+// Note: for small mcu such as
+// - RA2A1: only pipe 4-7 are available, and no support for ISO
+static unsigned find_pipe(unsigned xfer_type) {
+  #if defined(BSP_MCU_GROUP_RA2A1)
+  const uint8_t pipe_idx_arr[4][2] = {
+      { 0, 0 }, // Control
+      { 0, 0 }, // Isochronous not supported
+      { 4, 5 }, // Bulk
+      { 6, 7 }, // Interrupt
+  };
+  #else
+  const uint8_t pipe_idx_arr[4][2] = {
+      { 0, 0 }, // Control
+      { 1, 2 }, // Isochronous
+      { 1, 5 }, // Bulk
+      { 6, 9 }, // Interrupt
+  };
+  #endif
+
+  // find backward since only pipe 1, 2 support ISO
+  const uint8_t idx_first = pipe_idx_arr[xfer_type][0];
+  const uint8_t idx_last  = pipe_idx_arr[xfer_type][1];
+
+  for (int i = idx_last; i >= idx_first; i--) {
+    if (0 == _dcd.pipe[i].ep) return i;
+  }
+
+  return 0;
+}
+
+static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num) {
+  if (num) {
+    return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]);
+  } else {
+    return (volatile uint16_t*)&(rusb->DCPCTR);
+  }
+}
+
+static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num) {
+  volatile reg_pipetre_t* tre = NULL;
+  if ((1 <= num) && (num <= 5)) {
+    tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E);
+  }
+  return tre;
+}
+
+static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) {
+  rusb2_reg_t *rusb = RUSB2_REG(rhport);
+  const unsigned epn = tu_edpt_number(ep_addr);
+
+  if (epn) {
+    const unsigned dir = tu_edpt_dir(ep_addr);
+    const unsigned num = _dcd.ep[dir][epn];
+    return get_pipectr(rusb, num);
+  } else {
+    return get_pipectr(rusb, 0);
+  }
+}
+
+static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb) {
+  return rusb->DCPMAXP_b.MXPS;
+}
+
+static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num) {
+  rusb->PIPESEL = num;
+  return rusb->PIPEMAXP;
+}
+
+static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num) {
+  while ( rusb->D0FIFOSEL_b.CURPIPE != num ) {}
+  while ( !rusb->D0FIFOCTR_b.FRDY ) {}
+}
+
+//--------------------------------------------------------------------+
+// Pipe FIFO
+//--------------------------------------------------------------------+
+
+// Write data buffer --> hw fifo
+static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
+{
+  (void) rusb;
+
+  volatile uint16_t *ff16;
+  volatile uint8_t *ff8;
+
+  // Highspeed FIFO is 32-bit
+  if ( rusb2_is_highspeed_reg(rusb) ) {
+    // TODO 32-bit access for better performance
+    ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
+    ff8  = (volatile uint8_t *) ((uintptr_t) fifo+3);
+  }else {
+    ff16 = (volatile uint16_t*) fifo;
+    ff8  = ((volatile uint8_t*) fifo);
+  }
+
+  uint8_t const* buf8 = (uint8_t const*) buf;
+
+  while (len >= 2) {
+    *ff16 = tu_unaligned_read16(buf8);
+    buf8 += 2;
+    len  -= 2;
+  }
+
+  if (len > 0) {
+    *ff8 = *buf8;
+    ++buf8;
+  }
+}
+
+// Read data buffer <-- hw fifo
+static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
+{
+  (void) rusb;
+
+  // TODO 16/32-bit access for better performance
+
+  uint8_t *p = (uint8_t*)buf;
+  volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
+  while (len--) *p++ = *reg;
+}
+
+// Write data sw fifo --> hw fifo
+static void pipe_write_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
+  tu_fifo_buffer_info_t info;
+  tu_fifo_get_read_info(f, &info);
+
+  uint16_t count = tu_min16(total_len, info.len_lin);
+  pipe_write_packet(rusb, info.ptr_lin, fifo, count);
+
+  uint16_t rem = total_len - count;
+  if (rem) {
+    rem = tu_min16(rem, info.len_wrap);
+    pipe_write_packet(rusb, info.ptr_wrap, fifo, rem);
+    count += rem;
+  }
+
+  tu_fifo_advance_read_pointer(f, count);
+}
+
+// Read data sw fifo <-- hw fifo
+static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
+  tu_fifo_buffer_info_t info;
+  tu_fifo_get_write_info(f, &info);
+
+  uint16_t count = tu_min16(total_len, info.len_lin);
+  pipe_read_packet(rusb, info.ptr_lin, fifo, count);
+
+  uint16_t rem = total_len - count;
+  if (rem) {
+    rem = tu_min16(rem, info.len_wrap);
+    pipe_read_packet(rusb, info.ptr_wrap, fifo, rem);
+    count += rem;
+  }
+
+  tu_fifo_advance_write_pointer(f, count);
+}
+
+//--------------------------------------------------------------------+
+// Pipe Transfer
+//--------------------------------------------------------------------+
+
+static bool pipe0_xfer_in(rusb2_reg_t* rusb)
+{
+  pipe_state_t *pipe = &_dcd.pipe[0];
+  const unsigned rem = pipe->remaining;
+
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+
+  const uint16_t mps = edpt0_max_packet_size(rusb);
+  const uint16_t len = tu_min16(mps, rem);
+  void          *buf = pipe->buf;
+
+  if (len) {
+    if (pipe->ff) {
+      pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
+    } else {
+      pipe_write_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len);
+      pipe->buf = (uint8_t*)buf + len;
+    }
+  }
+
+  if (len < mps) {
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+  }
+
+  pipe->remaining = rem - len;
+  return false;
+}
+
+static bool pipe0_xfer_out(rusb2_reg_t* rusb)
+{
+  pipe_state_t *pipe = &_dcd.pipe[0];
+  const unsigned rem = pipe->remaining;
+
+  const uint16_t mps = edpt0_max_packet_size(rusb);
+  const uint16_t vld = rusb->CFIFOCTR_b.DTLN;
+  const uint16_t len = tu_min16(tu_min16(rem, mps), vld);
+  void          *buf = pipe->buf;
+
+  if (len) {
+    if (pipe->ff) {
+      pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
+    } else {
+      pipe_read_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len);
+      pipe->buf = (uint8_t*)buf + len;
+    }
+  }
+
+  if (len < mps) {
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+  }
+
+  pipe->remaining = rem - len;
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return true;
+  }
+
+  return false;
+}
+
+static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
+{
+  pipe_state_t  *pipe = &_dcd.pipe[num];
+  const unsigned rem  = pipe->remaining;
+
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+  const uint16_t mps  = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+  const uint16_t len  = tu_min16(rem, mps);
+  void          *buf  = pipe->buf;
+
+  if (len) {
+    if (pipe->ff) {
+      pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
+    } else {
+      pipe_write_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe->buf = (uint8_t*)buf + len;
+    }
+  }
+
+  if (len < mps) {
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+  }
+
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  pipe->remaining = rem - len;
+
+  return false;
+}
+
+static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
+{
+  pipe_state_t  *pipe = &_dcd.pipe[num];
+  const uint16_t rem  = pipe->remaining;
+
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
+  const uint16_t mps = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+
+  const uint16_t vld  = rusb->D0FIFOCTR_b.DTLN;
+  const uint16_t len  = tu_min16(tu_min16(rem, mps), vld);
+  void          *buf  = pipe->buf;
+
+  if (len) {
+    if (pipe->ff) {
+      pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
+    } else {
+      pipe_read_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe->buf = (uint8_t*)buf + len;
+    }
+  }
+
+  if (len < mps) {
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+  }
+
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  pipe->remaining = rem - len;
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return NULL != buf;
+  }
+
+  return false;
+}
+
+static void process_setup_packet(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  if (0 == (rusb->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return;
+
+  rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+  uint16_t setup_packet[4] = {
+      tu_htole16(rusb->USBREQ),
+      tu_htole16(rusb->USBVAL),
+      tu_htole16(rusb->USBINDX),
+      tu_htole16(rusb->USBLENG)
+  };
+
+  rusb->INTSTS0 = ~((uint16_t) RUSB2_INTSTS0_VALID_Msk);
+  dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
+}
+
+static void process_status_completion(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  uint8_t ep_addr;
+  /* Check the data stage direction */
+  if (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) {
+    /* IN transfer. */
+    ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
+  } else {
+    /* OUT transfer. */
+    ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT);
+  }
+
+  dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true);
+}
+
+static bool process_pipe0_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+{
+  /* configure fifo direction and access unit settings */
+  if ( ep_addr ) {
+    /* IN, 2 bytes */
+    rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
+                     (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+    while ( !(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ) {}
+  } else {
+    /* OUT, a byte */
+    rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
+    while ( rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE ) {}
+  }
+
+  pipe_state_t *pipe = &_dcd.pipe[0];
+  pipe->ff        = buffer_type;
+  pipe->length    = total_bytes;
+  pipe->remaining = total_bytes;
+
+  if ( total_bytes ) {
+    pipe->buf = buffer;
+    if ( ep_addr ) {
+      /* IN */
+      TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80));
+      pipe0_xfer_in(rusb);
+    }
+    rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
+  } else {
+    /* ZLP */
+    pipe->buf = NULL;
+    rusb->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF;
+  }
+
+  return true;
+}
+
+static bool process_pipe_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+{
+  const unsigned epn = tu_edpt_number(ep_addr);
+  const unsigned dir = tu_edpt_dir(ep_addr);
+  const unsigned num = _dcd.ep[dir][epn];
+
+  TU_ASSERT(num);
+
+  pipe_state_t *pipe  = &_dcd.pipe[num];
+  pipe->ff        = buffer_type;
+  pipe->buf       = buffer;
+  pipe->length    = total_bytes;
+  pipe->remaining = total_bytes;
+
+  if (dir) {
+    /* IN */
+    if (total_bytes) {
+      pipe_xfer_in(rusb, num);
+    } else {
+      /* ZLP */
+      rusb->D0FIFOSEL = num;
+      pipe_wait_for_ready(rusb, num);
+      rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      rusb->D0FIFOSEL = 0;
+      /* if CURPIPE bits changes, check written value */
+      while (rusb->D0FIFOSEL_b.CURPIPE) {}
+    }
+  } else {
+    // OUT
+    volatile reg_pipetre_t *pt = get_pipetre(rusb, num);
+
+    if (pt) {
+      const uint16_t     mps = edpt_max_packet_size(rusb, num);
+      volatile uint16_t *ctr = get_pipectr(rusb, num);
+
+      if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK;
+
+      pt->TRE   = TU_BIT(8);
+      pt->TRN   = (total_bytes + mps - 1) / mps;
+      pt->TRENB = 1;
+      *ctr = RUSB2_PIPE_CTR_PID_BUF;
+    }
+  }
+
+  //  TU_LOG2("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
+  return true;
+}
+
+static bool process_edpt_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+{
+  const unsigned epn = tu_edpt_number(ep_addr);
+  if (0 == epn) {
+    return process_pipe0_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes);
+  } else {
+    return process_pipe_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes);
+  }
+}
+
+static void process_pipe0_bemp(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  bool completed = pipe0_xfer_in(rusb);
+  if (completed) {
+    pipe_state_t *pipe = &_dcd.pipe[0];
+    dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
+                            pipe->length, XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_pipe_brdy(uint8_t rhport, unsigned num)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  pipe_state_t  *pipe = &_dcd.pipe[num];
+  const unsigned dir  = tu_edpt_dir(pipe->ep);
+  bool completed;
+
+  if (dir) {
+    /* IN */
+    completed = pipe_xfer_in(rusb, num);
+  } else {
+    // OUT
+    if (num) {
+      completed = pipe_xfer_out(rusb, num);
+    } else {
+      completed = pipe0_xfer_out(rusb);
+    }
+  }
+  if (completed) {
+    dcd_event_xfer_complete(rhport, pipe->ep,
+                            pipe->length - pipe->remaining,
+                            XFER_RESULT_SUCCESS, true);
+    //  TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining);
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  rusb->BEMPENB = 1;
+  rusb->BRDYENB = 1;
+  rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  rusb->D1FIFOSEL = 0;
+  while (rusb->D1FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_CTR[0]));
+  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_TR[0].E));
+
+  for (int i = 1; i <= 5; ++i) {
+    rusb->PIPESEL = i;
+    rusb->PIPECFG = 0;
+    *ctr = RUSB2_PIPE_CTR_ACLRM_Msk;
+    *ctr = 0;
+    ++ctr;
+    *tre = TU_BIT(8);
+    tre += 2;
+  }
+
+  for (int i = 6; i <= 9; ++i) {
+    rusb->PIPESEL = i;
+    rusb->PIPECFG = 0;
+    *ctr = RUSB2_PIPE_CTR_ACLRM_Msk;
+    *ctr = 0;
+    ++ctr;
+  }
+  tu_varclr(&_dcd);
+
+  TU_LOG3("Bus reset, RHST = %u\r\n", rusb->DVSTCTR0_b.RHST);
+  tusb_speed_t speed;
+  switch(rusb->DVSTCTR0 & RUSB2_DVSTCTR0_RHST_Msk) {
+    case RUSB2_DVSTCTR0_RHST_LS:
+      speed = TUSB_SPEED_LOW;
+      break;
+
+    case RUSB2_DVSTCTR0_RHST_FS:
+      speed = TUSB_SPEED_FULL;
+      break;
+
+    case RUSB2_DVSTCTR0_RHST_HS:
+      speed = TUSB_SPEED_HIGH;
+      break;
+
+    default:
+      TU_ASSERT(false, );
+  }
+
+  dcd_event_bus_reset(rhport, speed, true);
+}
+
+static void process_set_address(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  const uint16_t addr = rusb->USBADDR_b.USBADDR;
+  if (!addr) return;
+
+  const tusb_control_request_t setup_packet = {
+#if defined(__CCRX__)
+      .bmRequestType = { 0 },  /* Note: CCRX needs the braces over this struct member */
+#else
+      .bmRequestType = 0,
+#endif
+      .bRequest      = TUSB_REQ_SET_ADDRESS,
+      .wValue        = addr,
+      .wIndex        = 0,
+      .wLength       = 0,
+  };
+
+  dcd_event_setup_received(rhport, (const uint8_t *) &setup_packet, true);
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+
+#if 0 // previously present in the rx driver before generalization
+static uint32_t disable_interrupt(void)
+{
+  uint32_t pswi;
+#if defined(__CCRX__)
+  pswi = get_psw() & 0x010000;
+  clrpsw_i();
+#else
+  pswi = __builtin_rx_mvfc(0) & 0x010000;
+  __builtin_rx_clrpsw('I');
+#endif
+  return pswi;
+}
+
+static void enable_interrupt(uint32_t pswi)
+{
+#if defined(__CCRX__)
+  set_psw(get_psw() | pswi);
+#else
+  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
+#endif
+}
+#endif
+
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb2_module_start(rhport, true);
+
+  // We disable SOF for now until needed later on.
+  // Since TinyUSB doesn't use SOF for now, and this interrupt often (1ms interval)
+  _dcd.sof_enabled = false;
+
+#ifdef RUSB2_SUPPORT_HIGHSPEED
+  if ( rusb2_is_highspeed_rhport(rhport) ) {
+    rusb->SYSCFG_b.HSE = 1;
+
+    // leave CLKSEL as default (0x11) 24Mhz
+
+    // Power and reset UTMI Phy
+    uint16_t physet = (rusb->PHYSET | RUSB2_PHYSET_PLLRESET_Msk) & ~RUSB2_PHYSET_DIRPD_Msk;
+    rusb->PHYSET = physet;
+    R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+    rusb->PHYSET_b.PLLRESET = 0;
+
+    // set UTMI to operating mode and wait for PLL lock confirmation
+    rusb->LPSTS_b.SUSPENDM = 1;
+    while (!rusb->PLLSTA_b.PLLLOCK) {}
+
+    rusb->SYSCFG_b.DRPD = 0;
+    rusb->SYSCFG_b.USBE = 1;
+
+    // Set CPU bus wait time (fine tunne later)
+    // rusb2->BUSWAIT |= 0x0F00U;
+
+    rusb->PHYSET_b.REPSEL = 1;
+  } else
+#endif
+  {
+    rusb->SYSCFG_b.SCKE = 1;
+    while (!rusb->SYSCFG_b.SCKE) {}
+    rusb->SYSCFG_b.DRPD = 0;
+    rusb->SYSCFG_b.DCFM = 0;
+    rusb->SYSCFG_b.USBE = 1;
+
+    // MCU specific PHY init
+    rusb2_phy_init();
+
+    rusb->PHYSLEW = 0x5;
+    rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
+  }
+
+  /* Setup default control pipe */
+  rusb->DCPMAXP_b.MXPS = 64;
+
+  rusb->INTSTS0 = 0;
+  rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
+                  RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (_dcd.sof_enabled ? RUSB2_INTSTS0_SOFR_Msk : 0) |
+                  RUSB2_INTSTS0_RESM_Msk;
+  rusb->BEMPENB = 1;
+  rusb->BRDYENB = 1;
+
+  // If VBUS (detect) pin is not used, application need to call tud_connect() manually after tud_init()
+  if (rusb->INTSTS0_b.VBSTS) {
+    dcd_connect(rhport);
+  }
+
+  return true;
+}
+
+void dcd_int_enable(uint8_t rhport) {
+  rusb2_int_enable(rhport);
+}
+
+void dcd_int_disable(uint8_t rhport) {
+  rusb2_int_disable(rhport);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb->DVSTCTR0_b.WKUP = 1;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  if ( rusb2_is_highspeed_rhport(rhport)) {
+    rusb->SYSCFG_b.CNEN = 1;
+  }
+  rusb->SYSCFG_b.DPRPU = 1;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb->SYSCFG_b.DPRPU = 0;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  _dcd.sof_enabled = en;
+  rusb->INTENB0_b.SOFE = en ? 1: 0;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void)rhport;
+
+  rusb2_reg_t * rusb = RUSB2_REG(rhport);
+  const unsigned ep_addr = ep_desc->bEndpointAddress;
+  const unsigned epn     = tu_edpt_number(ep_addr);
+  const unsigned dir     = tu_edpt_dir(ep_addr);
+  const unsigned xfer    = ep_desc->bmAttributes.xfer;
+
+  const unsigned mps = tu_edpt_packet_size(ep_desc);
+
+  if (xfer == TUSB_XFER_ISOCHRONOUS) {
+    // Fullspeed ISO is limit to 256 bytes
+    if ( !rusb2_is_highspeed_rhport(rhport) && mps > 256) {
+      return false;
+    }
+  }
+
+  const unsigned num = find_pipe(xfer);
+  TU_ASSERT(num);
+
+  _dcd.pipe[num].ep = ep_addr;
+  _dcd.ep[dir][epn] = num;
+
+  /* setup pipe */
+  dcd_int_disable(rhport);
+
+  if ( rusb2_is_highspeed_rhport(rhport) ) {
+    // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
+    //       depending on the allocation scheme
+    rusb->PIPEBUF = 0x7C08;
+  }
+
+  rusb->PIPESEL = num;
+  rusb->PIPEMAXP = mps;
+  volatile uint16_t *ctr = get_pipectr(rusb, num);
+  *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk;
+  *ctr = 0;
+  unsigned cfg = (dir << 4) | epn;
+
+  if (xfer == TUSB_XFER_BULK) {
+    cfg |= (RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk);
+  } else if (xfer == TUSB_XFER_INTERRUPT) {
+    cfg |= RUSB2_PIPECFG_TYPE_INT;
+  } else {
+    cfg |= (RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk);
+  }
+
+  rusb->PIPECFG = cfg;
+  rusb->BRDYSTS = 0x3FFu ^ TU_BIT(num);
+  rusb->BRDYENB |= TU_BIT(num);
+
+  if (dir || (xfer != TUSB_XFER_BULK)) {
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
+  }
+
+  // TU_LOG1("O %d %x %x\r\n", rusb->PIPESEL, rusb->PIPECFG, rusb->PIPEMAXP);
+  dcd_int_enable(rhport);
+
+  return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport)
+{
+  unsigned i = TU_ARRAY_SIZE(_dcd.pipe);
+  dcd_int_disable(rhport);
+  while (--i) { /* Close all pipes except 0 */
+    const unsigned ep_addr = _dcd.pipe[i].ep;
+    if (!ep_addr) continue;
+    dcd_edpt_close(rhport, ep_addr);
+  }
+  dcd_int_enable(rhport);
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  rusb2_reg_t * rusb = RUSB2_REG(rhport);
+  const unsigned epn = tu_edpt_number(ep_addr);
+  const unsigned dir = tu_edpt_dir(ep_addr);
+  const unsigned num = _dcd.ep[dir][epn];
+
+  rusb->BRDYENB &= ~TU_BIT(num);
+  volatile uint16_t *ctr = get_pipectr(rusb, num);
+  *ctr = 0;
+  rusb->PIPESEL = num;
+  rusb->PIPECFG = 0;
+  _dcd.pipe[num].ep = 0;
+  _dcd.ep[dir][epn] = 0;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  dcd_int_disable(rhport);
+  bool r = process_edpt_xfer(rusb, 0, ep_addr, buffer, total_bytes);
+  dcd_int_enable(rhport);
+
+  return r;
+}
+
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
+  TU_ASSERT(ff->item_size == 1);
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  dcd_int_disable(rhport);
+  bool r = process_edpt_xfer(rusb, 1, ep_addr, ff, total_bytes);
+  dcd_int_enable(rhport);
+
+  return r;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
+  if (!ctr) return;
+  dcd_int_disable(rhport);
+  const uint32_t pid = *ctr & 0x3;
+  *ctr = pid | RUSB2_PIPE_CTR_PID_STALL;
+  *ctr = RUSB2_PIPE_CTR_PID_STALL;
+  dcd_int_enable(rhport);
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  rusb2_reg_t * rusb = RUSB2_REG(rhport);
+  volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
+  if (!ctr) return;
+
+  dcd_int_disable(rhport);
+  *ctr = RUSB2_PIPE_CTR_SQCLR_Msk;
+
+  if (tu_edpt_dir(ep_addr)) { /* IN */
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
+  } else {
+    const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
+    rusb->PIPESEL = num;
+    if (rusb->PIPECFG_b.TYPE != 1) {
+      *ctr = RUSB2_PIPE_CTR_PID_BUF;
+    }
+  }
+  dcd_int_enable(rhport);
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+
+#if defined(__CCRX__)
+TU_ATTR_ALWAYS_INLINE static inline unsigned __builtin_ctz(unsigned int value) {
+  unsigned int count = 0;
+  while ((value & 1) == 0) {
+    value >>= 1;
+    count++;
+  }
+  return count;
+}
+#endif
+
+void dcd_int_handler(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  uint16_t is0 = rusb->INTSTS0;
+
+  /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
+  rusb->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk |
+                     RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk;
+
+  // VBUS changes
+  if ( is0 & RUSB2_INTSTS0_VBINT_Msk ) {
+    if ( rusb->INTSTS0_b.VBSTS ) {
+      dcd_connect(rhport);
+    } else {
+      dcd_disconnect(rhport);
+    }
+  }
+
+  // Resumed
+  if ( is0 & RUSB2_INTSTS0_RESM_Msk ) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+    if (!_dcd.sof_enabled) {
+      rusb->INTENB0_b.SOFE = 0;
+    }
+  }
+
+  // SOF received
+  if ( (is0 & RUSB2_INTSTS0_SOFR_Msk) && rusb->INTENB0_b.SOFE ) {
+    // USBD will exit suspended mode when SOF event is received
+    const uint32_t frame = rusb->FRMNUM_b.FRNM;
+    dcd_event_sof(rhport, frame, true);
+    if (!_dcd.sof_enabled) {
+      rusb->INTENB0_b.SOFE = 0;
+    }
+  }
+
+  // Device state changes
+  if ( is0 & RUSB2_INTSTS0_DVST_Msk ) {
+    switch (is0 & RUSB2_INTSTS0_DVSQ_Msk) {
+      case RUSB2_INTSTS0_DVSQ_STATE_DEF:
+        process_bus_reset(rhport);
+        break;
+
+      case RUSB2_INTSTS0_DVSQ_STATE_ADDR:
+        process_set_address(rhport);
+        break;
+
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP0:
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP1:
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP2:
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP3:
+        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+        if (!_dcd.sof_enabled) {
+          rusb->INTENB0_b.SOFE = 1;
+        }
+
+      default: break;
+    }
+  }
+
+//  if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) {
+//    rusb->NRDYSTS = 0;
+//  }
+
+  // Control transfer stage changes
+  if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) {
+    if ( is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA ) {
+      /* A setup packet has been received. */
+      process_setup_packet(rhport);
+    } else if ( 0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk) ) {
+      /* A ZLP has been sent/received. */
+      process_status_completion(rhport);
+    }
+  }
+
+  // Buffer empty
+  if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) {
+    const uint16_t s = rusb->BEMPSTS;
+    rusb->BEMPSTS = 0;
+    if ( s & 1 ) {
+      process_pipe0_bemp(rhport);
+    }
+  }
+
+  // Buffer ready
+  if ( is0 & RUSB2_INTSTS0_BRDY_Msk ) {
+    const unsigned m = rusb->BRDYENB;
+    unsigned s = rusb->BRDYSTS & m;
+    /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
+    rusb->BRDYSTS = ~s;
+    while (s) {
+      const unsigned num = __builtin_ctz(s);
+      process_pipe_brdy(rhport, num);
+      s &= ~TU_BIT(num);
+    }
+  }
+}
+
+#endif
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
new file mode 100644
index 000000000..4c81b05be
--- /dev/null
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -0,0 +1,844 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Koji Kitayama
+ * Portions copyrighted (c) 2021 Roland Winistoerfer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_RUSB2)
+
+#include "host/hcd.h"
+#include "rusb2_type.h"
+
+#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+  #include "rusb2_rx.h"
+#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
+  #include "rusb2_ra.h"
+#else
+  #error "Unsupported MCU"
+#endif
+
+#define TU_RUSB2_HCD_DBG   2
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+enum {
+  PIPE_COUNT = 10,
+};
+
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
+
+typedef union TU_ATTR_PACKED {
+  struct {
+    volatile uint16_t u8: 8;
+    volatile uint16_t   : 0;
+  };
+  volatile uint16_t u16;
+} hw_fifo_t;
+
+typedef struct TU_ATTR_PACKED {
+  void      *buf;      /* the start address of a transfer data buffer */
+  uint16_t  length;    /* the number of bytes in the buffer */
+  uint16_t  remaining; /* the number of bytes remaining in the buffer */
+  struct {
+    uint32_t ep  : 8;  /* an assigned endpoint address */
+    uint32_t dev : 8;  /* an assigned device address */
+    uint32_t ff  : 1;  /* `buf` is TU_FUFO or POD */
+    uint32_t     : 0;
+  };
+} pipe_state_t;
+
+TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_BIT_FIELD_ORDER_END
+
+typedef struct
+{
+  bool         need_reset; /* The device has not been reset after connection. */
+  pipe_state_t pipe[PIPE_COUNT];
+  uint8_t ep[4][2][15];   /* a lookup table for a pipe index from an endpoint address */
+  uint8_t      ctl_mps[5]; /* EP0 max packet size for each device */
+} hcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+static hcd_data_t _hcd;
+
+// TODO merged with DCD
+// Transfer conditions specifiable for each pipe for most MCUs
+// - Pipe 0: Control transfer with 64-byte single buffer
+// - Pipes 1 and 2: Bulk or ISO
+// - Pipes 3 to 5: Bulk
+// - Pipes 6 to 9: Interrupt
+//
+// Note: for small mcu such as
+// - RA2A1: only pipe 4-7 are available, and no support for ISO
+static unsigned find_pipe(unsigned xfer_type) {
+  const uint8_t pipe_idx_arr[4][2] = {
+      { 0, 0 }, // Control
+      { 1, 2 }, // Isochronous
+      { 1, 5 }, // Bulk
+      { 6, 9 }, // Interrupt
+  };
+
+  // find backward since only pipe 1, 2 support ISO
+  const uint8_t idx_first = pipe_idx_arr[xfer_type][0];
+  const uint8_t idx_last  = pipe_idx_arr[xfer_type][1];
+
+  for (int i = idx_last; i >= idx_first; i--) {
+    if (0 == _hcd.pipe[i].ep) return i;
+  }
+
+  return 0;
+}
+
+static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num)
+{
+  if (num) {
+    return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]);
+  } else {
+    return (volatile uint16_t*)&(rusb->DCPCTR);
+  }
+}
+
+static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num)
+{
+  volatile reg_pipetre_t* tre = NULL;
+  if ((1 <= num) && (num <= 5)) {
+    tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E);
+  }
+  return tre;
+}
+
+static volatile uint16_t* addr_to_pipectr(uint8_t rhport, uint8_t dev_addr, unsigned ep_addr)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  const unsigned epn = tu_edpt_number(ep_addr);
+
+  if (epn) {
+    const unsigned dir_in = tu_edpt_dir(ep_addr);
+    const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1];
+    return get_pipectr(rusb, num);
+  } else {
+    return get_pipectr(rusb, 0);
+  }
+}
+
+static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb)
+{
+  return rusb->DCPMAXP_b.MXPS;
+}
+
+static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num)
+{
+  rusb->PIPESEL = num;
+  return rusb->PIPEMAXP_b.MXPS;
+}
+
+static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num)
+{
+  while (rusb->D0FIFOSEL_b.CURPIPE != num) ;
+  while (!rusb->D0FIFOCTR_b.FRDY) {}
+}
+
+static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  // NOTE: unlike DCD, Highspeed 32-bit FIFO does not need to adjust the fifo address
+  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
+  uintptr_t addr = (uintptr_t)buf;
+  while (len >= 2) {
+    reg->u16 = *(const uint16_t *)addr;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    reg->u8 = *(const uint8_t *)addr;
+    ++addr;
+  }
+}
+
+static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  uint8_t *p   = (uint8_t*)buf;
+  volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
+  while (len--) *p++ = *reg;
+}
+
+static bool pipe0_xfer_in(rusb2_reg_t* rusb)
+{
+  pipe_state_t *pipe = &_hcd.pipe[0];
+  const unsigned rem = pipe->remaining;
+
+  const unsigned mps = edpt0_max_packet_size(rusb);
+  const unsigned vld = rusb->CFIFOCTR_b.DTLN;
+  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf = pipe->buf;
+  if (len) {
+    rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+    pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) {
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+  }
+  pipe->remaining = rem - len;
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return true;
+  }
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
+  return false;
+}
+
+static bool pipe0_xfer_out(rusb2_reg_t* rusb)
+{
+  pipe_state_t *pipe = &_hcd.pipe[0];
+  const unsigned rem = pipe->remaining;
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+  const unsigned mps = edpt0_max_packet_size(rusb);
+  const unsigned len = TU_MIN(mps, rem);
+  void          *buf = pipe->buf;
+  if (len) {
+    pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) {
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+  }
+  pipe->remaining = rem - len;
+  return false;
+}
+
+static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
+{
+  pipe_state_t  *pipe = &_hcd.pipe[num];
+  const unsigned rem  = pipe->remaining;
+
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
+  const unsigned mps  = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+  const unsigned vld  = rusb->D0FIFOCTR_b.DTLN;
+  const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf  = pipe->buf;
+  if (len) {
+    pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) {
+    rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BCLR_Msk;
+  }
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  pipe->remaining = rem - len;
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return NULL != buf;
+  }
+  return false;
+}
+
+static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
+{
+  pipe_state_t  *pipe = &_hcd.pipe[num];
+  const unsigned rem  = pipe->remaining;
+
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+  const unsigned mps  = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+  const unsigned len  = TU_MIN(rem, mps);
+  void          *buf  = pipe->buf;
+  if (len) {
+    pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) {
+    rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BVAL_Msk;
+  }
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  pipe->remaining = rem - len;
+  return false;
+}
+
+static bool process_pipe0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+{
+  (void)dev_addr;
+
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+
+  /* configure fifo direction and access unit settings */
+  if (dir_in) { /* IN, a byte */
+    rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
+    while (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
+  } else { /* OUT, 2 bytes */
+    rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
+                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+    while (!(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
+  }
+
+  pipe_state_t *pipe = &_hcd.pipe[0];
+  pipe->ep        = ep_addr;
+  pipe->length    = buflen;
+  pipe->remaining = buflen;
+  if (buflen) {
+    pipe->buf     = buffer;
+    if (!dir_in) { /* OUT */
+      TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80));
+      pipe0_xfer_out(rusb);
+    }
+  } else { /* ZLP */
+    pipe->buf        = NULL;
+    if (!dir_in) { /* OUT */
+      rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    }
+    if (dir_in == rusb->DCPCFG_b.DIR) {
+      TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == rusb->DCPCTR_b.PID);
+      rusb->DCPCTR_b.SQSET = 1;
+      rusb->DCPCFG_b.DIR = dir_in ^ 1;
+    }
+  }
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
+  return true;
+}
+
+static bool process_pipe_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  const unsigned epn    = tu_edpt_number(ep_addr);
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  const unsigned num    = _hcd.ep[dev_addr - 1][dir_in][epn - 1];
+
+  TU_ASSERT(num);
+
+  pipe_state_t *pipe  = &_hcd.pipe[num];
+  pipe->buf       = buffer;
+  pipe->length    = buflen;
+  pipe->remaining = buflen;
+  if (!dir_in) { /* OUT */
+    if (buflen) {
+      pipe_xfer_out(rusb, num);
+    } else { /* ZLP */
+      rusb->D0FIFOSEL = num;
+      pipe_wait_for_ready(rusb, num);
+      rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BVAL_Msk;
+      rusb->D0FIFOSEL = 0;
+      while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+    }
+  } else {
+    volatile uint16_t     *ctr = get_pipectr(rusb, num);
+    volatile reg_pipetre_t *pt = get_pipetre(rusb, num);
+    if (pt) {
+      const unsigned     mps = edpt_max_packet_size(rusb, num);
+      if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK;
+      pt->TRE   = TU_BIT(8);
+      pt->TRN   = (buflen + mps - 1) / mps;
+      pt->TRENB = 1;
+    }
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
+  }
+  return true;
+}
+
+static bool process_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+{
+  const unsigned epn = tu_edpt_number(ep_addr);
+  if (0 == epn) {
+    return process_pipe0_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
+  } else {
+    return process_pipe_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
+  }
+}
+
+static void process_pipe0_bemp(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  bool completed = pipe0_xfer_out(rusb);
+  if (completed) {
+    pipe_state_t *pipe = &_hcd.pipe[0];
+    hcd_event_xfer_complete(pipe->dev,
+                            tu_edpt_addr(0, TUSB_DIR_OUT),
+                            pipe->length - pipe->remaining,
+                            XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_pipe_nrdy(uint8_t rhport, unsigned num)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  xfer_result_t result;
+  uint16_t volatile *ctr = get_pipectr(rusb, num);
+  TU_LOG(TU_RUSB2_HCD_DBG, "NRDY %d %x\r\n", num, *ctr);
+  switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) {
+    default: return;
+    case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
+    case RUSB2_PIPE_CTR_PID_STALL2: result = XFER_RESULT_STALLED; break;
+    case RUSB2_PIPE_CTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
+  }
+  pipe_state_t *pipe = &_hcd.pipe[num];
+  hcd_event_xfer_complete(pipe->dev, pipe->ep,
+                          pipe->length - pipe->remaining,
+                          result, true);
+}
+
+static void process_pipe_brdy(uint8_t rhport, unsigned num)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  pipe_state_t  *pipe   = &_hcd.pipe[num];
+  const unsigned dir_in = tu_edpt_dir(pipe->ep);
+  bool completed;
+
+  if (dir_in) { /* IN */
+    if (num) {
+      completed = pipe_xfer_in(rusb, num);
+    } else {
+      completed = pipe0_xfer_in(rusb);
+    }
+  } else {
+    completed = pipe_xfer_out(rusb, num);
+  }
+  if (completed) {
+    hcd_event_xfer_complete(pipe->dev, pipe->ep,
+                            pipe->length - pipe->remaining,
+                            XFER_RESULT_SUCCESS, true);
+    TU_LOG(TU_RUSB2_HCD_DBG, "C %d %d\r\n", num, pipe->length - pipe->remaining);
+  }
+}
+
+/*------------------------------------------------------------------*/
+/* Host API
+ *------------------------------------------------------------------*/
+
+#if 0 // previously present in the rx driver before generalization
+static uint32_t disable_interrupt(void)
+{
+  uint32_t pswi;
+#if defined(__CCRX__)
+  pswi = get_psw() & 0x010000;
+  clrpsw_i();
+#else
+  pswi = __builtin_rx_mvfc(0) & 0x010000;
+  __builtin_rx_clrpsw('I');
+#endif
+  return pswi;
+}
+
+static void enable_interrupt(uint32_t pswi)
+{
+#if defined(__CCRX__)
+  set_psw(get_psw() | pswi);
+#else
+  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
+#endif
+}
+#endif
+
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb2_module_start(rhport, true);
+
+#ifdef RUSB2_SUPPORT_HIGHSPEED
+  if (rusb2_is_highspeed_rhport(rhport) ) {
+    rusb->SYSCFG_b.HSE = 1;
+    rusb->PHYSET_b.HSEB = 0;
+    rusb->PHYSET_b.DIRPD = 0;
+    R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+    rusb->PHYSET_b.PLLRESET = 0;
+    rusb->LPSTS_b.SUSPENDM = 1;
+    while ( !rusb->PLLSTA_b.PLLLOCK );
+    rusb->SYSCFG_b.DRPD = 1;
+    rusb->SYSCFG_b.DCFM = 1;
+    rusb->SYSCFG_b.DPRPU = 0;
+    rusb->SYSCFG_b.CNEN = 1;
+    rusb->BUSWAIT |= 0x0F00U;
+    rusb->SOFCFG_b.INTL = 1;
+    rusb->DVSTCTR0_b.VBUSEN = 1;
+    rusb->CFIFOSEL_b.MBW = 1;
+    rusb->D0FIFOSEL_b.MBW = 1;
+    rusb->D1FIFOSEL_b.MBW = 1;
+    rusb->INTSTS0 = 0;
+    for ( volatile int i = 0; i < 30000; ++i );
+    rusb->SYSCFG_b.USBE = 1;
+  } else
+#endif
+  {
+    rusb->SYSCFG_b.SCKE = 1;
+    while ( !rusb->SYSCFG_b.SCKE ) {}
+    rusb->SYSCFG_b.DCFM = 1;         // Host function
+    rusb->SYSCFG_b.DPRPU = 0;        // Disable D+ pull up
+    rusb->SYSCFG_b.DRPD = 1;         // Enable D+/D- pull down
+
+    rusb->DVSTCTR0_b.VBUSEN = 1;
+    for ( volatile int i = 0; i < 30000; ++i ) {} // FIXME do we need to wait here? how long ?
+    //R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS);
+    rusb->SYSCFG_b.USBE = 1;
+
+    // MCU specific PHY init
+    rusb2_phy_init();
+
+    rusb->PHYSLEW = 0x5;
+    rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
+  }
+
+  /* Setup default control pipe */
+  rusb->DCPCFG  = RUSB2_PIPECFG_SHTNAK_Msk;
+  rusb->DCPMAXP = 64;
+  rusb->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk;
+  rusb->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk;
+  rusb->BEMPENB = 1;
+  rusb->NRDYENB = 1;
+  rusb->BRDYENB = 1;
+
+  return true;
+}
+
+void hcd_int_enable(uint8_t rhport) {
+  rusb2_int_enable(rhport);
+}
+
+void hcd_int_disable(uint8_t rhport) {
+  rusb2_int_disable(rhport);
+}
+
+uint32_t hcd_frame_number(uint8_t rhport)
+{
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  /* The device must be reset at least once after connection
+   * in order to start the frame counter. */
+  if (_hcd.need_reset) hcd_port_reset(rhport);
+  return rusb->FRMNUM_b.FRNM;
+}
+
+/*--------------------------------------------------------------------+
+ * Port API
+ *--------------------------------------------------------------------+*/
+bool hcd_port_connect_status(uint8_t rhport) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  return rusb->INTSTS1_b.ATTCH ? true : false;
+}
+
+void hcd_port_reset(uint8_t rhport) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+  while (rusb->DCPCTR_b.PBUSY) {}
+
+  hcd_int_disable(rhport);
+  rusb->DVSTCTR0_b.UACT = 0;
+  if (rusb->DCPCTR_b.SUREQ) {
+    rusb->DCPCTR_b.SUREQCLR = 1;
+  }
+  hcd_int_enable(rhport);
+
+  /* Reset should be asserted 10-20ms. */
+  rusb->DVSTCTR0_b.USBRST = 1;
+  for (volatile int i = 0; i < 2400000; ++i) {}
+  rusb->DVSTCTR0_b.USBRST = 0;
+
+  rusb->DVSTCTR0_b.UACT = 1;
+  _hcd.need_reset = false;
+}
+
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+}
+
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  switch (rusb->DVSTCTR0_b.RHST) {
+    case RUSB2_DVSTCTR0_RHST_HS: return TUSB_SPEED_HIGH;
+    case RUSB2_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
+    case RUSB2_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW;
+    default: return TUSB_SPEED_INVALID;
+  }
+}
+
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  uint16_t volatile *ctr;
+
+  TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */
+  if (!dev_addr) return;
+
+  _hcd.ctl_mps[dev_addr] = 0;
+  uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0];
+
+  for (int i = 0; i < 2 * 15; ++i, ++ep) {
+    unsigned num = *ep;
+    if (!num || (dev_addr != _hcd.pipe[num].dev)) continue;
+
+    ctr = (uint16_t volatile*)&rusb->PIPE_CTR[num - 1];
+    *ctr = 0;
+    rusb->NRDYENB &= ~TU_BIT(num);
+    rusb->BRDYENB &= ~TU_BIT(num);
+    rusb->PIPESEL = num;
+    rusb->PIPECFG = 0;
+    rusb->PIPEMAXP = 0;
+
+    _hcd.pipe[num].ep  = 0;
+    _hcd.pipe[num].dev = 0;
+    *ep                = 0;
+  }
+}
+
+/*--------------------------------------------------------------------+
+ * Endpoints API
+ *--------------------------------------------------------------------+*/
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
+{
+  TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
+
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\r\n", dev_addr, rusb->DCPCTR);
+
+  TU_ASSERT(0 == rusb->DCPCTR_b.SUREQ);
+
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+
+  _hcd.pipe[0].buf       = NULL;
+  _hcd.pipe[0].length    = 8;
+  _hcd.pipe[0].remaining = 0;
+  _hcd.pipe[0].dev       = dev_addr;
+
+  while (rusb->DCPCTR_b.PBUSY) ;
+  rusb->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
+
+  /* Set direction in advance for DATA stage */
+  uint8_t const bmRequesttype = setup_packet[0];
+  rusb->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
+
+  uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
+  rusb->USBREQ  = tu_htole16(p[0]);
+  rusb->USBVAL  = p[1];
+  rusb->USBINDX = p[2];
+  rusb->USBLENG = p[3];
+
+  rusb->DCPCTR_b.SUREQ = 1;
+  return true;
+}
+
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc)
+{
+  TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  const unsigned ep_addr = ep_desc->bEndpointAddress;
+  const unsigned epn     = tu_edpt_number(ep_addr);
+  const unsigned mps     = tu_edpt_packet_size(ep_desc);
+
+  if (0 == epn) {
+    rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+    hcd_devtree_info_t devtree;
+    hcd_devtree_get_info(dev_addr, &devtree);
+    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &rusb->DEVADD[0];
+    devadd += dev_addr;
+    while (rusb->DCPCTR_b.PBUSY) {}
+    rusb->DCPMAXP = (dev_addr << 12) | mps;
+    *devadd = (TUSB_SPEED_FULL == devtree.speed) ? RUSB2_DEVADD_USBSPD_FS : RUSB2_DEVADD_USBSPD_LS;
+    _hcd.ctl_mps[dev_addr] = mps;
+    return true;
+  }
+
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  const unsigned xfer   = ep_desc->bmAttributes.xfer;
+  if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
+    /* USBa supports up to 256 bytes */
+    return false;
+  }
+  const unsigned num = find_pipe(xfer);
+  if (!num) return false;
+
+  _hcd.pipe[num].dev = dev_addr;
+  _hcd.pipe[num].ep  = ep_addr;
+  _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num;
+
+  /* setup pipe */
+  hcd_int_disable(rhport);
+
+  rusb->PIPESEL = num;
+  rusb->PIPEMAXP = (dev_addr << 12) | mps;
+  volatile uint16_t *ctr = get_pipectr(rusb, num);
+  *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk;
+  *ctr = 0;
+
+  unsigned cfg = ((1 ^ dir_in) << 4) | epn;
+  if (xfer == TUSB_XFER_BULK) {
+    cfg |= RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk;
+  } else if (xfer == TUSB_XFER_INTERRUPT) {
+    cfg |= RUSB2_PIPECFG_TYPE_INT;
+  } else {
+    cfg |= RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk;
+  }
+
+  rusb->PIPECFG = cfg;
+  rusb->BRDYSTS = 0x3FFu ^ TU_BIT(num);
+  rusb->NRDYENB |= TU_BIT(num);
+  rusb->BRDYENB |= TU_BIT(num);
+
+  if (!dir_in) {
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
+  }
+
+  hcd_int_enable(rhport);
+
+  return true;
+}
+
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
+{
+  bool r;
+  hcd_int_disable(rhport);
+  TU_LOG(TU_RUSB2_HCD_DBG, "X %d %x %u\r\n", dev_addr, ep_addr, buflen);
+  r = process_edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
+  hcd_int_enable(rhport);
+  return r;
+}
+
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  uint16_t volatile *ctr = addr_to_pipectr(rhport, dev_addr, ep_addr);
+  TU_ASSERT(ctr);
+
+  const uint32_t pid = *ctr & 0x3;
+  if (pid & 2) {
+    *ctr = pid & 2;
+    *ctr = 0;
+  }
+  *ctr = RUSB2_PIPE_CTR_SQCLR_Msk;
+  unsigned const epn = tu_edpt_number(ep_addr);
+  if (!epn) return true;
+
+  if (!tu_edpt_dir(ep_addr)) { /* OUT */
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
+  }
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+#if defined(__CCRX__)
+TU_ATTR_ALWAYS_INLINE static inline unsigned __builtin_ctz(unsigned int value) {
+  unsigned int count = 0;
+  while ((value & 1) == 0) {
+    value >>= 1;
+    count++;
+  }
+  return count;
+}
+#endif
+
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void) in_isr;
+
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  unsigned is0 = rusb->INTSTS0;
+  unsigned is1 = rusb->INTSTS1;
+
+  /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
+  rusb->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
+  rusb->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
+
+  TU_LOG3("IS %04x %04x\r\n", is0, is1);
+  is1 &= rusb->INTENB1;
+  is0 &= rusb->INTENB0;
+
+  if (is1 & RUSB2_INTSTS1_SACK_Msk) {
+    /* Set DATA1 in advance for the next transfer. */
+    rusb->DCPCTR_b.SQSET = 1;
+    hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
+  }
+
+  if (is1 & RUSB2_INTSTS1_SIGN_Msk) {
+    hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
+  }
+
+  if (is1 & RUSB2_INTSTS1_ATTCH_Msk) {
+    rusb->DVSTCTR0_b.UACT = 1;
+    _hcd.need_reset = true;
+    rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
+    hcd_event_device_attach(rhport, true);
+  }
+
+  if (is1 & RUSB2_INTSTS1_DTCH_Msk) {
+    rusb->DVSTCTR0_b.UACT = 0;
+    if (rusb->DCPCTR_b.SUREQ) {
+      rusb->DCPCTR_b.SUREQCLR = 1;
+    }
+    rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk;
+    hcd_event_device_remove(rhport, true);
+  }
+
+  if (is0 & RUSB2_INTSTS0_BEMP_Msk) {
+    const unsigned s = rusb->BEMPSTS;
+    rusb->BEMPSTS = 0;
+    if (s & 1) {
+      process_pipe0_bemp(rhport);
+    }
+  }
+
+  if (is0 & RUSB2_INTSTS0_NRDY_Msk) {
+    const unsigned m = rusb->NRDYENB;
+    unsigned s = rusb->NRDYSTS & m;
+    rusb->NRDYSTS = ~s;
+    while (s) {
+      const unsigned num = __builtin_ctz(s);
+      process_pipe_nrdy(rhport, num);
+      s &= ~TU_BIT(num);
+    }
+  }
+  if (is0 & RUSB2_INTSTS0_BRDY_Msk) {
+    const unsigned m = rusb->BRDYENB;
+    unsigned s = rusb->BRDYSTS & m;
+    /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
+    rusb->BRDYSTS = ~s;
+    while (s) {
+      const unsigned num = __builtin_ctz(s);
+      process_pipe_brdy(rhport, num);
+      s &= ~TU_BIT(num);
+    }
+  }
+}
+
+#endif
diff --git a/src/common/tusb_timeout.h b/src/portable/renesas/rusb2/rusb2_common.c
similarity index 54%
rename from src/common/tusb_timeout.h
rename to src/portable/renesas/rusb2/rusb2_common.c
index ce53955f0..72e65736b 100644
--- a/src/common/tusb_timeout.h
+++ b/src/portable/renesas/rusb2/rusb2_common.c
@@ -1,7 +1,7 @@
-/* 
+/*
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,57 +24,39 @@
  * This file is part of the TinyUSB stack.
  */
 
-/** \ingroup Group_Common Common Files
- *  \defgroup Group_TimeoutTimer timeout timer
- *  @{ */
+#include "tusb_option.h"
 
-#ifndef _TUSB_TIMEOUT_H_
-#define _TUSB_TIMEOUT_H_
+#if defined(TUP_USBIP_RUSB2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED)
 
-#include <stdbool.h>
-#include <stdint.h>
+#include "rusb2_type.h"
 
-#ifdef __cplusplus
-extern "C" {
+#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+#include "rusb2_rx.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
+#include "rusb2_ra.h"
+
+// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
+rusb2_controller_t rusb2_controller[] = {
+    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
+    #ifdef RUSB2_SUPPORT_HIGHSPEED
+    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
+    #endif
+};
+
+// Application API for setting IRQ number. May throw warnings for missing prototypes.
+void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum);
+void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
+  rusb2_controller[rhport].irqnum = irqnum;
+}
+
+//  void osal_task_delay(uint32_t msec) {
+//    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
+//  }
+
+#else
+  #error "Unsupported MCU"
 #endif
 
-typedef struct {
-  uint32_t start;
-  uint32_t interval;
-}tu_timeout_t;
-
-#if 0
-
-extern uint32_t tusb_hal_millis(void);
-
-static inline void tu_timeout_set(tu_timeout_t* tt, uint32_t msec)
-{
-  tt->interval = msec;
-  tt->start    = tusb_hal_millis();
-}
-
-static inline bool tu_timeout_expired(tu_timeout_t* tt)
-{
-  return ( tusb_hal_millis() - tt->start ) >= tt->interval;
-}
-
-// For used with periodic event to prevent drift
-static inline void tu_timeout_reset(tu_timeout_t* tt)
-{
-  tt->start += tt->interval;
-}
-
-static inline void tu_timeout_restart(tu_timeout_t* tt)
-{
-  tt->start = tusb_hal_millis();
-}
 
 #endif
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_TIMEOUT_H_ */
-
-/** @} */
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
new file mode 100644
index 000000000..4774d2e2c
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -0,0 +1,109 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Rafael Silva (@perigoso)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _RUSB2_RA_H_
+#define _RUSB2_RA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#pragma GCC diagnostic ignored "-Wundef"
+
+// extra push due to https://github.com/renesas/fsp/pull/278
+#pragma GCC diagnostic push
+#endif
+
+/* renesas fsp api */
+#include "bsp_api.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+// IAR does not have __builtin_ctz
+#if defined(__ICCARM__)
+  #define __builtin_ctz(x)   __iar_builtin_CLZ(__iar_builtin_RBIT(x))
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+typedef struct {
+  uint32_t reg_base;
+  int32_t irqnum;
+}rusb2_controller_t;
+
+#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
+  #define RUSB2_SUPPORT_HIGHSPEED
+  #define RUSB2_CONTROLLER_COUNT 2
+
+  #define rusb2_is_highspeed_rhport(_p)  (_p == 1)
+  #define rusb2_is_highspeed_reg(_reg)   (_reg == RUSB2_REG(1))
+#else
+  #define RUSB2_CONTROLLER_COUNT 1
+
+  #define rusb2_is_highspeed_rhport(_p)  (false)
+  #define rusb2_is_highspeed_reg(_reg)   (false)
+#endif
+
+extern rusb2_controller_t rusb2_controller[];
+#define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
+
+//--------------------------------------------------------------------+
+// RUSB2 API
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
+  uint32_t const mask = 1U << (11+rhport);
+  if (start) {
+    R_MSTP->MSTPCRB &= ~mask;
+  }else {
+    R_MSTP->MSTPCRB |= mask;
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) {
+  NVIC_EnableIRQ(rusb2_controller[rhport].irqnum);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) {
+  NVIC_DisableIRQ(rusb2_controller[rhport].irqnum);
+}
+
+// MCU specific PHY init
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) {
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RUSB2_RA_H_ */
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
new file mode 100644
index 000000000..7bf4be47e
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -0,0 +1,94 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Koji Kitayama
+ * Portions copyrighted (c) 2021 Roland Winistoerfer
+ * Copyright (c) 2022 Rafael Silva (@perigoso)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _RUSB2_RX_H_
+#define _RUSB2_RX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "iodefine.h"
+
+#define RUSB2_REG_BASE (0x000A0000)
+
+TU_ATTR_ALWAYS_INLINE static inline rusb2_reg_t* RUSB2_REG(uint8_t rhport) {
+  (void) rhport;
+  return (rusb2_reg_t *) RUSB2_REG_BASE;
+}
+
+
+#define rusb2_is_highspeed_rhport(_p)  (false)
+#define rusb2_is_highspeed_reg(_reg)   (false)
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+
+// Start/Stop MSTP TODO implement later
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
+  (void) rhport;
+  (void) start;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
+  IEN(PERIB, INTB185) = 1;
+#else
+  IEN(USB0, USBI0) = 1;
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
+  IEN(PERIB, INTB185) = 0;
+#else
+  IEN(USB0, USBI0) = 0;
+#endif
+}
+
+// MCU specific PHY init
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
+{
+#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
+  IR(PERIB, INTB185) = 0;
+#else
+  IR(USB0, USBI0) = 0;
+#endif
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RUSB2_RX_H_ */
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
new file mode 100644
index 000000000..dd88f66a7
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -0,0 +1,1780 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Rafael Silva (@perigoso)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_RUSB2_TYPE_H_
+#define _TUSB_RUSB2_TYPE_H_
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// CCRX specific attribute to generate a Code that Accesses Variables in the Declared Size
+#ifdef __CCRX__
+  #define _ccrx_evenaccess __evenaccess
+#else
+  #define _ccrx_evenaccess
+#endif
+
+/*--------------------------------------------------------------------*/
+/* Register Definitions                                           */
+/*--------------------------------------------------------------------*/
+
+/* Start of definition of packed structs (used by the CCRX toolchain) */
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
+
+// TODO same as RUSB2_PIPE_TR_t
+typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
+  union {
+    struct {
+      uint16_t      : 8;
+      uint16_t TRCLR: 1;
+      uint16_t TRENB: 1;
+      uint16_t      : 0;
+    };
+    uint16_t TRE;
+  };
+  uint16_t TRN;
+} reg_pipetre_t;
+
+typedef struct {
+  union {
+    volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
+
+    struct TU_ATTR_PACKED {
+      uint16_t                : 8;
+      volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
+      volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
+      uint16_t                : 6;
+    } E_b;
+  };
+
+  union {
+    volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
+    } N_b;
+  };
+} RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */
+
+
+/* RUSB2 Registers Structure */
+typedef struct _ccrx_evenaccess {
+  union {
+    volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t USBE  : 1; /* [0..0] USB Operation Enable */
+      uint16_t                : 2;
+      volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */
+      volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
+      volatile uint16_t DRPD  : 1; /* [5..5] D+/D- Line Resistor Control */
+      volatile uint16_t DCFM  : 1; /* [6..6] Controller Function Select */
+      volatile uint16_t HSE   : 1; // [7..7] High-Speed Operation Enable
+      volatile uint16_t CNEN  : 1; /* [8..8] CNEN Single End Receiver Enable */
+      uint16_t                : 1;
+      volatile uint16_t SCKE  : 1; /* [10..10] USB Clock Enable */
+      uint16_t                : 5;
+    } SYSCFG_b;
+  };
+
+  union {
+    volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
+      uint16_t                : 12;
+    } BUSWAIT_b;
+  };
+
+  union {
+    volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t LNST   : 2; /* [1..0] USB Data Line Status Monitor */
+      volatile const uint16_t IDMON  : 1; /* [2..2] External ID0 Input Pin Monitor */
+      uint16_t                       : 2;
+      volatile const uint16_t SOFEA  : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
+      volatile const uint16_t HTACT  : 1; /* [6..6] USB Host Sequencer Status Monitor */
+      uint16_t                       : 7;
+      volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
+    } SYSSTS0_b;
+  };
+
+  union {
+    volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
+      uint16_t                        : 15;
+    } PLLSTA_b;
+  };
+
+  union {
+    volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */
+      uint16_t                     : 1;
+      volatile uint16_t UACT       : 1; /* [4..4] USB Bus Enable */
+      volatile uint16_t RESUME     : 1; /* [5..5] Resume Output */
+      volatile uint16_t USBRST     : 1; /* [6..6] USB Bus Reset Output */
+      volatile uint16_t RWUPE      : 1; /* [7..7] Wakeup Detection Enable */
+      volatile uint16_t WKUP       : 1; /* [8..8] Wakeup Output */
+      volatile uint16_t VBUSEN     : 1; /* [9..9] USB_VBUSEN Output Pin Control */
+      volatile uint16_t EXICEN     : 1; /* [10..10] USB_EXICEN Output Pin Control */
+      volatile uint16_t HNPBTOA    : 1; /* [11..11] Host Negotiation Protocol (HNP) */
+      uint16_t                     : 4;
+    } DVSTCTR0_b;
+  };
+  volatile const uint16_t RESERVED;
+
+  union {
+    volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t UTST : 4; /* [3..0] Test Mode */
+      uint16_t               : 12;
+    } TESTMODE_b;
+  };
+  volatile const uint16_t RESERVED1;
+  volatile const uint32_t RESERVED2;
+
+  union {
+    volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */
+
+    struct TU_ATTR_PACKED {
+      union {
+        volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */
+        volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */
+      };
+
+      union {
+        volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */
+
+        struct TU_ATTR_PACKED {
+          volatile const uint8_t RESERVED3;
+          volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */
+        };
+      };
+    };
+  };
+
+  union {
+    volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */
+
+    struct TU_ATTR_PACKED {
+      union {
+        volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */
+        volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */
+      };
+
+      union {
+        volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */
+
+        struct TU_ATTR_PACKED {
+          volatile const uint8_t RESERVED4;
+          volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */
+        };
+      };
+    };
+  };
+
+  union {
+    volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */
+
+    struct TU_ATTR_PACKED {
+      union {
+        volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */
+        volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */
+      };
+
+      union {
+        volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */
+
+        struct TU_ATTR_PACKED {
+          volatile const uint8_t RESERVED5;
+          volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */
+        };
+      };
+    };
+  };
+
+  union {
+    volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */
+      uint16_t                  : 1;
+      volatile uint16_t ISEL    : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
+      uint16_t                  : 2;
+      volatile uint16_t BIGEND  : 1; /* [8..8] CFIFO Port Endian Control */
+      uint16_t                  : 1;
+      volatile uint16_t MBW     : 2; /* [11..10] CFIFO Port Access Bit Width */
+      uint16_t                  : 2;
+      volatile uint16_t REW     : 1; /* [14..14] Buffer Pointer Rewind */
+      volatile uint16_t RCNT    : 1; /* [15..15] Read Count Mode */
+    } CFIFOSEL_b;
+  };
+
+  union {
+    volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t                     : 1;
+      volatile const uint16_t FRDY : 1;  /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR       : 1;  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL       : 1;  /* [15..15] Buffer Memory Valid Flag */
+    } CFIFOCTR_b;
+  };
+  volatile const uint32_t RESERVED6;
+
+  union {
+    volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
+      uint16_t                  : 4;
+      volatile uint16_t BIGEND  : 1; /* [8..8] FIFO Port Endian Control */
+      uint16_t                  : 1;
+      volatile uint16_t MBW     : 2; /* [11..10] FIFO Port Access Bit Width */
+      volatile uint16_t DREQE   : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+      volatile uint16_t DCLRM   : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+      volatile uint16_t REW     : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
+      volatile uint16_t RCNT    : 1; /* [15..15] Read Count Mode */
+    } D0FIFOSEL_b;
+  };
+
+  union {
+    volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t                     : 1;
+      volatile const uint16_t FRDY : 1;  /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR       : 1;  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL       : 1;  /* [15..15] Buffer Memory Valid Flag */
+    } D0FIFOCTR_b;
+  };
+
+  union {
+    volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
+      uint16_t                  : 4;
+      volatile uint16_t BIGEND  : 1; /* [8..8] FIFO Port Endian Control */
+      uint16_t                  : 1;
+      volatile uint16_t MBW     : 2; /* [11..10] FIFO Port Access Bit Width */
+      volatile uint16_t DREQE   : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+      volatile uint16_t DCLRM   : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+      volatile uint16_t REW     : 1; /* [14..14] Buffer Pointer Rewind */
+      volatile uint16_t RCNT    : 1; /* [15..15] Read Count Mode */
+    } D1FIFOSEL_b;
+  };
+
+  union {
+    volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t                     : 1;
+      volatile const uint16_t FRDY : 1;  /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR       : 1;  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL       : 1;  /* [15..15] Buffer Memory Valid Flag */
+    } D1FIFOCTR_b;
+  };
+
+  union {
+    volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
+
+    struct TU_ATTR_PACKED {
+      uint16_t                : 8;
+      volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
+      volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
+      volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
+      volatile uint16_t CTRE  : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */
+      volatile uint16_t DVSE  : 1; /* [12..12] Device State Transition Interrupt Enable */
+      volatile uint16_t SOFE  : 1; /* [13..13] Frame Number Update Interrupt Enable */
+      volatile uint16_t RSME  : 1; /* [14..14] Resume Interrupt Enable */
+      volatile uint16_t VBSE  : 1; /* [15..15] VBUS Interrupt Enable */
+    } INTENB0_b;
+  };
+
+  union {
+    volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */
+      uint16_t                     : 3;
+      volatile uint16_t SACKE      : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */
+      volatile uint16_t SIGNE      : 1; /* [5..5] Setup Transaction Error Interrupt Enable */
+      volatile uint16_t EOFERRE    : 1; /* [6..6] EOF Error Detection Interrupt Enable */
+               uint16_t            : 1;
+      volatile uint16_t LPMENDE    : 1; /*!< [8..8] LPM Transaction End Interrupt Enable                               */
+      volatile uint16_t L1RSMENDE  : 1; /*!< [9..9] L1 Resume End Interrupt Enable                                     */
+               uint16_t            : 1;
+      volatile uint16_t ATTCHE     : 1; /* [11..11] Connection Detection Interrupt Enable */
+      volatile uint16_t DTCHE      : 1; /* [12..12] Disconnection Detection Interrupt Enable */
+      uint16_t                     : 1;
+      volatile uint16_t BCHGE      : 1; /* [14..14] USB Bus Change Interrupt Enable */
+      volatile uint16_t OVRCRE     : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */
+    } INTENB1_b;
+  };
+  volatile const uint16_t RESERVED7;
+
+  union {
+    volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
+      uint16_t                     : 6;
+    } BRDYENB_b;
+  };
+
+  union {
+    volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
+      uint16_t                     : 6;
+    } NRDYENB_b;
+  };
+
+  union {
+    volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
+      uint16_t                     : 6;
+    } BEMPENB_b;
+  };
+
+  union {
+    volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */
+
+    struct TU_ATTR_PACKED {
+      uint16_t                        : 4;
+      volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */
+      volatile uint16_t INTL          : 1; /* [5..5] Interrupt Output Sense Select */
+      volatile uint16_t BRDYM         : 1; /* [6..6] BRDY Interrupt Status Clear Timing */
+      uint16_t                        : 1;
+      volatile uint16_t TRNENSEL      : 1; /* [8..8] Transaction-Enabled Time Select */
+      uint16_t                        : 7;
+    } SOFCFG_b;
+  };
+
+  union {
+    volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t DIRPD    : 1; /* [0..0] Power-Down Control */
+      volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */
+      uint16_t                   : 1;
+      volatile uint16_t CDPEN    : 1; /* [3..3] Charging Downstream Port Enable */
+      volatile uint16_t CLKSEL   : 2; /* [5..4] Input System Clock Frequency */
+      uint16_t                   : 2;
+      volatile uint16_t REPSEL   : 2; /* [9..8] Terminating Resistance Adjustment Cycle */
+      uint16_t                   : 1;
+      volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */
+      uint16_t                   : 3;
+      volatile uint16_t HSEB     : 1; /* [15..15] CL-Only Mode */
+    } PHYSET_b;
+  };
+
+  union {
+    volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t CTSQ  : 3; /* [2..0] Control Transfer Stage */
+      volatile uint16_t VALID       : 1; /* [3..3] USB Request Reception */
+      volatile const uint16_t DVSQ  : 3; /* [6..4] Device State */
+      volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */
+      volatile const uint16_t BRDY  : 1; /* [8..8] Buffer Ready Interrupt Status */
+      volatile const uint16_t NRDY  : 1; /* [9..9] Buffer Not Ready Interrupt Status */
+      volatile const uint16_t BEMP  : 1; /* [10..10] Buffer Empty Interrupt Status */
+      volatile uint16_t CTRT        : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */
+      volatile uint16_t DVST        : 1; /* [12..12] Device State Transition Interrupt Status */
+      volatile uint16_t SOFR        : 1; /* [13..13] Frame Number Refresh Interrupt Status */
+      volatile uint16_t RESM        : 1; /* [14..14] Resume Interrupt Status */
+      volatile uint16_t VBINT       : 1; /* [15..15] VBUS Interrupt Status */
+    } INTSTS0_b;
+  };
+
+  union {
+    volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */
+      uint16_t                    : 3;
+      volatile uint16_t SACK      : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */
+      volatile uint16_t SIGN      : 1; /* [5..5] Setup Transaction Error Interrupt Status */
+      volatile uint16_t EOFERR    : 1; /* [6..6] EOF Error Detection Interrupt Status */
+      uint16_t                    : 1;
+      volatile uint16_t LPMEND    : 1; /* [8..8] LPM Transaction End Interrupt Status */
+      volatile uint16_t L1RSMEND  : 1; /* [9..9] L1 Resume End Interrupt Status */
+      uint16_t                    : 1;
+      volatile uint16_t ATTCH     : 1; /* [11..11] ATTCH Interrupt Status */
+      volatile uint16_t DTCH      : 1; /* [12..12] USB Disconnection Detection Interrupt Status */
+      uint16_t                    : 1;
+      volatile uint16_t BCHG      : 1; /* [14..14] USB Bus Change Interrupt Status */
+      volatile uint16_t OVRCR     : 1; /* [15..15] Overcurrent Input Change Interrupt Status */
+    } INTSTS1_b;
+  };
+  volatile const uint16_t RESERVED8;
+
+  union {
+    volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
+      uint16_t                    : 6;
+    } BRDYSTS_b;
+  };
+
+  union {
+    volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
+      uint16_t                    : 6;
+    } NRDYSTS_b;
+  };
+
+  union {
+    volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
+      uint16_t                    : 6;
+    } BEMPSTS_b;
+  };
+
+  union {
+    volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */
+      uint16_t                     : 3;
+      volatile uint16_t CRCE       : 1; /* [14..14] Receive Data Error */
+      volatile uint16_t OVRN       : 1; /* [15..15] Overrun/Underrun Detection Status */
+    } FRMNUM_b;
+  };
+
+  union {
+    volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */
+      uint16_t                      : 12;
+      volatile uint16_t DVCHG       : 1; /* [15..15] Device State Change */
+    } UFRMNUM_b;
+  };
+
+  union {
+    volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */
+      uint16_t                        : 1;
+      volatile uint16_t STSRECOV0     : 3; /* [10..8] Status Recovery */
+      uint16_t                        : 5;
+    } USBADDR_b;
+  };
+  volatile const uint16_t RESERVED9;
+
+  union {
+    volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
+      volatile uint16_t BREQUEST      : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
+    } USBREQ_b;
+  };
+
+  union {
+    volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */
+    } USBVAL_b;
+  };
+
+  union {
+    volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */
+    } USBINDX_b;
+  };
+
+  union {
+    volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */
+    } USBLENG_b;
+  };
+
+  union {
+    volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */
+
+    struct TU_ATTR_PACKED {
+      uint16_t                 : 4;
+      volatile uint16_t DIR    : 1; /* [4..4] Transfer Direction */
+      uint16_t                 : 2;
+      volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
+      volatile uint16_t CNTMD  : 1; /* [8..8] Continuous Transfer Mode */
+      uint16_t                 : 7;
+    } DCPCFG_b;
+  };
+
+  union {
+    volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t MXPS   : 7; /* [6..0] Maximum Packet Size */
+      uint16_t                 : 5;
+      volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
+    } DCPMAXP_b;
+  };
+
+  union {
+    volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PID         : 2; /* [1..0] Response PID */
+      volatile uint16_t CCPL        : 1; /* [2..2] Control Transfer End Enable */
+      uint16_t                      : 2;
+      volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
+      volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */
+      volatile uint16_t SQSET       : 1; /* [7..7] Sequence Toggle Bit Set */
+      volatile uint16_t SQCLR       : 1; /* [8..8] Sequence Toggle Bit Clear */
+      uint16_t                      : 2;
+      volatile uint16_t SUREQCLR    : 1; /* [11..11] SUREQ Bit Clear */
+      volatile uint16_t CSSTS       : 1; /* [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status                  */
+      volatile uint16_t CSCLR       : 1; /* [13..13] Split Transaction CSPLIT Status Clear                            */
+      volatile uint16_t SUREQ       : 1; /* [14..14] Setup Token Transmission */
+      volatile const uint16_t BSTS  : 1; /* [15..15] Buffer Status */
+    } DCPCTR_b;
+  };
+  volatile const uint16_t RESERVED10;
+
+  union {
+    volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
+      uint16_t                  : 12;
+    } PIPESEL_b;
+  };
+  volatile const uint16_t RESERVED11;
+
+  union {
+    volatile uint16_t PIPECFG;      /* (@ 0x00000068) Pipe Configuration Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t EPNUM  : 4; /* [3..0] Endpoint Number */
+      volatile uint16_t DIR    : 1; /* [4..4] Transfer Direction */
+      uint16_t                 : 2;
+      volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
+      volatile uint16_t CNTMD  : 1; /* [8..8] Continuous Transfer Mode                                           */
+      volatile uint16_t DBLB   : 1; /* [9..9] Double Buffer Mode */
+      volatile uint16_t BFRE   : 1; /* [10..10] BRDY Interrupt Operation Specification */
+      uint16_t                 : 3;
+      volatile uint16_t TYPE   : 2; /* [15..14] Transfer Type */
+    } PIPECFG_b;
+  };
+
+  union {
+    volatile uint16_t PIPEBUF;         /*!< (@ 0x0000006A) Pipe Buffer Register                                       */
+
+    struct {
+      volatile uint16_t BUFNMB  : 8; // [7..0] Buffer NumberThese bits specify the FIFO buffer number of the selected pipe (04h to 87h)
+      uint16_t                  : 2;
+      volatile uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes         */
+      uint16_t                  : 1;
+    } PIPEBUF_b;
+  };
+
+  union {
+    volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t MXPS   : 11; /* [10..0] Maximum Packet Size */
+      uint16_t                 : 1;
+      volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
+    } PIPEMAXP_b;
+  };
+
+  union {
+    volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */
+      uint16_t               : 9;
+      volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */
+      uint16_t               : 3;
+    } PIPEPERI_b;
+  };
+
+  union {
+    volatile uint16_t PIPE_CTR[9];        /* (@ 0x00000070) Pipe [0..8] Control Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t PID          : 2; /* [1..0] Response PID */
+      uint16_t                       : 3;
+      volatile const uint16_t PBUSY  : 1; /* [5..5] Pipe Busy */
+      volatile const uint16_t SQMON  : 1; /* [6..6] Sequence Toggle Bit Confirmation */
+      volatile uint16_t SQSET        : 1; /* [7..7] Sequence Toggle Bit Set */
+      volatile uint16_t SQCLR        : 1; /* [8..8] Sequence Toggle Bit Clear */
+      volatile uint16_t ACLRM        : 1; /* [9..9] Auto Buffer Clear Mode */
+      volatile uint16_t ATREPM       : 1; /* [10..10] Auto Response Mode */
+      uint16_t                       : 1;
+      volatile const uint16_t CSSTS  : 1; /* [12..12] CSSTS Status */
+      volatile uint16_t CSCLR        : 1; /* [13..13] CSPLIT Status Clear */
+      volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */
+      volatile const uint16_t BSTS   : 1; /* [15..15] Buffer Status */
+    } PIPE_CTR_b[9];
+  };
+  volatile const uint16_t RESERVED13;
+  volatile const uint32_t RESERVED14[3];
+  volatile RUSB2_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */
+  volatile const uint32_t RESERVED15[3];
+
+  union {
+    volatile uint16_t USBBCCTRL0;             /* (@ 0x000000B0) BC Control Register 0 */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t RPDME0           : 1; /* [0..0] D- Pin Pull-Down Control */
+      volatile uint16_t IDPSRCE0         : 1; /* [1..1] D+ Pin IDPSRC Output Control */
+      volatile uint16_t IDMSINKE0        : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t VDPSRCE0         : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
+      volatile uint16_t IDPSINKE0        : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t VDMSRCE0         : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
+      uint16_t                           : 1;
+      volatile uint16_t BATCHGE0         : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
+      volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */
+      volatile const uint16_t PDDETSTS0  : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */
+      uint16_t                           : 6;
+    } USBBCCTRL0_b;
+  };
+  volatile const uint16_t RESERVED16;
+  volatile const uint32_t RESERVED17[4];
+
+  union {
+    volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
+      uint16_t                  : 15;
+    } UCKSEL_b;
+  };
+  volatile const uint16_t RESERVED18;
+  volatile const uint32_t RESERVED19;
+
+  union {
+    volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */
+      uint16_t                  : 6;
+      volatile uint16_t VDCEN   : 1; /* [7..7] USB Regulator On/Off Control */
+      uint16_t                  : 8;
+    } USBMC_b;
+  };
+  volatile const uint16_t RESERVED20;
+
+  union {
+    volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
+
+    struct TU_ATTR_PACKED {
+      uint16_t                  : 6;
+      volatile uint16_t USBSPD  : 2; /* [7..6] Transfer Speed of Communication Target Device */
+      volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
+      volatile uint16_t UPPHUB  : 4; /* [14..11] Communication Target Connecting Hub Register */
+      uint16_t                  : 1;
+    } DEVADD_b[10];
+  };
+  volatile const uint32_t RESERVED21[3];
+
+  union {
+    volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */
+      volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
+      volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
+      volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
+      uint32_t                  : 28;
+    } PHYSLEW_b;
+  };
+  volatile const uint32_t RESERVED22[3];
+
+  union {
+    volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
+
+    struct TU_ATTR_PACKED {
+      uint16_t                : 7;
+      volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
+      uint16_t                : 8;
+    } LPCTRL_b;
+  };
+
+  union {
+    volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
+
+    struct TU_ATTR_PACKED {
+      uint16_t                   : 14;
+      volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
+      uint16_t                   : 1;
+    } LPSTS_b;
+  };
+  volatile const uint32_t RESERVED23[15];
+
+  union {
+    volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t IDPSRCE         : 1; /* [0..0] IDPSRC Control */
+      volatile uint16_t IDMSINKE        : 1; /* [1..1] IDMSINK Control */
+      volatile uint16_t VDPSRCE         : 1; /* [2..2] VDPSRC Control */
+      volatile uint16_t IDPSINKE        : 1; /* [3..3] IDPSINK Control */
+      volatile uint16_t VDMSRCE         : 1; /* [4..4] VDMSRC Control */
+      volatile uint16_t DCPMODE         : 1; /* [5..5] DCP Mode Control */
+      uint16_t                          : 2;
+      volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
+      volatile const uint16_t PDDETSTS  : 1; /* [9..9] PDDET Status */
+      uint16_t                          : 6;
+    } BCCTRL_b;
+  };
+  volatile const uint16_t RESERVED24;
+
+  union {
+    volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t L1RESPEN   : 1; /* [0..0] L1 Response Enable */
+      volatile uint16_t L1RESPMD   : 2; /* [2..1] L1 Response Mode */
+      volatile uint16_t L1NEGOMD   : 1; /* [3..3] L1 Response Negotiation Control. */
+      volatile const uint16_t DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
+      volatile uint16_t HIRDTHR    : 4; /* [11..8] L1 Response Negotiation Threshold Value */
+      uint16_t                     : 2;
+      volatile uint16_t L1EXTMD    : 1; /* [14..14] PHY Control Mode at L1 Return */
+      uint16_t                     : 1;
+    } PL1CTRL1_b;
+  };
+
+  union {
+    volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
+
+    struct TU_ATTR_PACKED {
+      uint16_t                  : 8;
+      volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
+      volatile uint16_t RWEMON  : 1;  /* [12..12] RWE Value Monitor */
+      uint16_t                  : 3;
+    } PL1CTRL2_b;
+  };
+
+  union {
+    volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t L1REQ          : 1;       /* [0..0] L1 Transition Request */
+      volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
+      uint16_t                         : 13;
+    } HL1CTRL1_b;
+  };
+
+  union {
+    volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */
+      uint16_t                 : 4;
+      volatile uint16_t HIRD   : 4; /* [11..8] LPM Token HIRD */
+      volatile uint16_t L1RWE  : 1; /* [12..12] LPM Token L1 Remote Wake Enable */
+      uint16_t                 : 2;
+      volatile uint16_t BESL   : 1; /* [15..15] BESL & Alternate HIRD */
+    } HL1CTRL2_b;
+  };
+
+  volatile uint32_t RESERVED25_1;
+
+  union {
+    volatile uint16_t PHYTRIM1;          /*!< (@ 0x00000150) PHY Timing Register 1                                      */
+
+    struct {
+      volatile uint16_t DRISE      : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function              */
+      volatile uint16_t DFALL      : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function             */
+               uint16_t            : 3;
+      volatile uint16_t PCOMPENB   : 1; /*!< [7..7] PVDD Start-up Detection                                            */
+      volatile uint16_t HSIUP      : 4; /*!< [11..8] HS Output Level Setting                                           */
+      volatile uint16_t IMPOFFSET  : 3; /*!< [14..12] terminating resistance offset value setting.Offset value for adjusting the terminating resistance.                           */
+               uint16_t            : 1;
+    } PHYTRIM1_b;
+  };
+
+  union {
+    volatile uint16_t PHYTRIM2;         /*!< (@ 0x00000152) PHY Timing Register 2                                      */
+
+    struct {
+      volatile  uint16_t SQU      : 4; /*!< [3..0] Squelch Detection Level                                            */
+      uint16_t                    : 3;
+      volatile  uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode                                     */
+      volatile  uint16_t PDR      : 2; /*!< [9..8] HS Output Adjustment Function                                      */
+      uint16_t                    : 2;
+      volatile  uint16_t DIS      : 3; /*!< [14..12] Disconnect Detection Level                                       */
+      uint16_t                    : 1;
+    } PHYTRIM2_b;
+  };
+  volatile uint32_t RESERVED25_2[3];
+
+  union {
+    volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
+
+    struct TU_ATTR_PACKED {
+      uint32_t                         : 20;
+      volatile const uint32_t DOVCAHM  : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
+      volatile const uint32_t DOVCBHM  : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
+      uint32_t                         : 1;
+      volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
+      uint32_t                         : 8;
+    } DPUSR0R_b;
+  };
+
+  union {
+    volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
+
+    struct TU_ATTR_PACKED {
+      uint32_t                        : 4;
+      volatile uint32_t DOVCAHE       : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
+      volatile uint32_t DOVCBHE       : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
+      uint32_t                        : 1;
+      volatile uint32_t DVBSTSHE      : 1; /* [7..7] VBUS Interrupt Enable/Clear */
+      uint32_t                        : 12;
+      volatile const uint32_t DOVCAH  : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */
+      volatile const uint32_t DOVCBH  : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
+      uint32_t                        : 1;
+      volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
+      uint32_t                        : 8;
+    } DPUSR1R_b;
+  };
+
+  union {
+    volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
+
+    struct TU_ATTR_PACKED {
+      volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
+      volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
+      uint16_t                      : 2;
+      volatile const uint16_t DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
+      volatile const uint16_t DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
+      uint16_t                      : 2;
+      volatile uint16_t DPINTE      : 1; /* [8..8] DP Interrupt Enable Clear */
+      volatile uint16_t DMINTE      : 1; /* [9..9] DM Interrupt Enable Clear */
+      uint16_t                      : 6;
+    } DPUSR2R_b;
+  };
+
+  union {
+    volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint16_t FIXPHY   : 1; /* [0..0] USB Transceiver Control Fix */
+      volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
+      uint16_t                   : 14;
+    } DPUSRCR_b;
+  };
+  volatile const uint32_t RESERVED26[165];
+
+  union {
+    volatile uint32_t
+      DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint32_t SRPC0         : 1; /* [0..0] USB Single End Receiver Control */
+      volatile uint32_t RPUE0         : 1; /* [1..1] DP Pull-Up Resistor Control */
+      uint32_t                        : 1;
+      volatile uint32_t DRPD0         : 1; /* [3..3] D+/D- Pull-Down Resistor Control */
+      volatile uint32_t FIXPHY0       : 1; /* [4..4] USB Transceiver Output Fix */
+      uint32_t                        : 11;
+      volatile const uint32_t DP0     : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
+      volatile const uint32_t DM0     : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
+      uint32_t                        : 2;
+      volatile const uint32_t DOVCA0  : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
+      volatile const uint32_t DOVCB0  : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
+      uint32_t                        : 1;
+      volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
+      uint32_t                        : 8;
+    } DPUSR0R_FS_b;
+  };
+
+  union {
+    volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */
+
+    struct TU_ATTR_PACKED {
+      volatile uint32_t DPINTE0        : 1; /* [0..0] USB DP Interrupt Enable/Clear */
+      volatile uint32_t DMINTE0        : 1; /* [1..1] USB DM Interrupt Enable/Clear */
+      uint32_t                         : 2;
+      volatile uint32_t DOVRCRAE0      : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */
+      volatile uint32_t DOVRCRBE0      : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */
+      uint32_t                         : 1;
+      volatile uint32_t DVBSE0         : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */
+      uint32_t                         : 8;
+      volatile const uint32_t DPINT0   : 1; /* [16..16] USB DP Interrupt Source Recovery */
+      volatile const uint32_t DMINT0   : 1; /* [17..17] USB DM Interrupt Source Recovery */
+      uint32_t                         : 2;
+      volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */
+      volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
+      uint32_t                         : 1;
+      volatile const uint32_t DVBINT0  : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
+      uint32_t                         : 8;
+    } DPUSR1R_FS_b;
+  };
+} rusb2_reg_t; /* Size = 1032 (0x408) */
+
+TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
+TU_ATTR_BIT_FIELD_ORDER_END
+
+/*--------------------------------------------------------------------*/
+/* Register Bit Definitions                                           */
+/*--------------------------------------------------------------------*/
+
+// PIPE_TR
+// E
+#define RUSB2_PIPE_TR_E_TRENB_Pos       (9UL)        /* TRENB (Bit 9) */
+#define RUSB2_PIPE_TR_E_TRENB_Msk       (0x200UL)    /* TRENB (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_TR_E_TRCLR_Pos       (8UL)        /* TRCLR (Bit 8) */
+#define RUSB2_PIPE_TR_E_TRCLR_Msk       (0x100UL)    /* TRCLR (Bitfield-Mask: 0x01) */
+
+// N
+#define RUSB2_PIPE_TR_N_TRNCNT_Pos      (0UL)        /* TRNCNT (Bit 0) */
+#define RUSB2_PIPE_TR_N_TRNCNT_Msk      (0xffffUL)   /* TRNCNT (Bitfield-Mask: 0xffff) */
+
+// Core Registers
+
+// SYSCFG
+#define RUSB2_SYSCFG_SCKE_Pos           (10UL)       /* SCKE (Bit 10) */
+#define RUSB2_SYSCFG_SCKE_Msk           (0x400UL)    /* SCKE (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_CNEN_Pos           (8UL)        /* CNEN (Bit 8) */
+#define RUSB2_SYSCFG_CNEN_Msk           (0x100UL)    /* CNEN (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_HSE_Pos            (7UL)        /*!< HSE (Bit 7)                                           */
+#define RUSB2_SYSCFG_HSE_Msk            (0x80UL)     /*!< HSE (Bitfield-Mask: 0x01)                             */
+#define RUSB2_SYSCFG_DCFM_Pos           (6UL)        /* DCFM (Bit 6) */
+#define RUSB2_SYSCFG_DCFM_Msk           (0x40UL)     /* DCFM (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_DRPD_Pos           (5UL)        /* DRPD (Bit 5) */
+#define RUSB2_SYSCFG_DRPD_Msk           (0x20UL)     /* DRPD (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_DPRPU_Pos          (4UL)        /* DPRPU (Bit 4) */
+#define RUSB2_SYSCFG_DPRPU_Msk          (0x10UL)     /* DPRPU (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_DMRPU_Pos          (3UL)        /* DMRPU (Bit 3) */
+#define RUSB2_SYSCFG_DMRPU_Msk          (0x8UL)      /* DMRPU (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_USBE_Pos           (0UL)        /* USBE (Bit 0) */
+#define RUSB2_SYSCFG_USBE_Msk           (0x1UL)      /* USBE (Bitfield-Mask: 0x01) */
+
+// BUSWAIT
+#define RUSB2_BUSWAIT_BWAIT_Pos         (0UL)        /* BWAIT (Bit 0) */
+#define RUSB2_BUSWAIT_BWAIT_Msk         (0xfUL)      /* BWAIT (Bitfield-Mask: 0x0f) */
+
+// SYSSTS0
+#define RUSB2_SYSSTS0_OVCMON_Pos        (14UL)       /* OVCMON (Bit 14) */
+#define RUSB2_SYSSTS0_OVCMON_Msk        (0xc000UL)   /* OVCMON (Bitfield-Mask: 0x03) */
+#define RUSB2_SYSSTS0_HTACT_Pos         (6UL)        /* HTACT (Bit 6) */
+#define RUSB2_SYSSTS0_HTACT_Msk         (0x40UL)     /* HTACT (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSSTS0_SOFEA_Pos         (5UL)        /* SOFEA (Bit 5) */
+#define RUSB2_SYSSTS0_SOFEA_Msk         (0x20UL)     /* SOFEA (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSSTS0_IDMON_Pos         (2UL)        /* IDMON (Bit 2) */
+#define RUSB2_SYSSTS0_IDMON_Msk         (0x4UL)      /* IDMON (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSSTS0_LNST_Pos          (0UL)        /* LNST (Bit 0) */
+#define RUSB2_SYSSTS0_LNST_Msk          (0x3UL)      /* LNST (Bitfield-Mask: 0x03) */
+
+// PLLSTA
+#define RUSB2_PLLSTA_PLLLOCK_Pos        (0UL)        /* PLLLOCK (Bit 0) */
+#define RUSB2_PLLSTA_PLLLOCK_Msk        (0x1UL)      /* PLLLOCK (Bitfield-Mask: 0x01) */
+
+// DVSTCTR0
+#define RUSB2_DVSTCTR0_HNPBTOA_Pos      (11UL)       /* HNPBTOA (Bit 11) */
+#define RUSB2_DVSTCTR0_HNPBTOA_Msk      (0x800UL)    /* HNPBTOA (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_EXICEN_Pos       (10UL)       /* EXICEN (Bit 10) */
+#define RUSB2_DVSTCTR0_EXICEN_Msk       (0x400UL)    /* EXICEN (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_VBUSEN_Pos       (9UL)        /* VBUSEN (Bit 9) */
+#define RUSB2_DVSTCTR0_VBUSEN_Msk       (0x200UL)    /* VBUSEN (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_WKUP_Pos         (8UL)        /* WKUP (Bit 8) */
+#define RUSB2_DVSTCTR0_WKUP_Msk         (0x100UL)    /* WKUP (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_RWUPE_Pos        (7UL)        /* RWUPE (Bit 7) */
+#define RUSB2_DVSTCTR0_RWUPE_Msk        (0x80UL)     /* RWUPE (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_USBRST_Pos       (6UL)        /* USBRST (Bit 6) */
+#define RUSB2_DVSTCTR0_USBRST_Msk       (0x40UL)     /* USBRST (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_RESUME_Pos       (5UL)        /* RESUME (Bit 5) */
+#define RUSB2_DVSTCTR0_RESUME_Msk       (0x20UL)     /* RESUME (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_UACT_Pos         (4UL)        /* UACT (Bit 4) */
+#define RUSB2_DVSTCTR0_UACT_Msk         (0x10UL)     /* UACT (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_RHST_Pos         (0UL)        /* RHST (Bit 0) */
+#define RUSB2_DVSTCTR0_RHST_Msk         (0x7UL)      /* RHST (Bitfield-Mask: 0x07) */
+
+// TESTMODE
+#define RUSB2_TESTMODE_UTST_Pos         (0UL)        /* UTST (Bit 0) */
+#define RUSB2_TESTMODE_UTST_Msk         (0xfUL)      /* UTST (Bitfield-Mask: 0x0f) */
+
+// CFIFOSEL
+#define RUSB2_CFIFOSEL_RCNT_Pos         (15UL)       /* RCNT (Bit 15) */
+#define RUSB2_CFIFOSEL_RCNT_Msk         (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOSEL_REW_Pos          (14UL)       /* REW (Bit 14) */
+#define RUSB2_CFIFOSEL_REW_Msk          (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOSEL_MBW_Pos          (10UL)       /* MBW (Bit 10) */
+#define RUSB2_CFIFOSEL_MBW_Msk          (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define RUSB2_CFIFOSEL_BIGEND_Pos       (8UL)        /* BIGEND (Bit 8) */
+#define RUSB2_CFIFOSEL_BIGEND_Msk       (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOSEL_ISEL_Pos         (5UL)        /* ISEL (Bit 5) */
+#define RUSB2_CFIFOSEL_ISEL_Msk         (0x20UL)     /* ISEL (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOSEL_CURPIPE_Pos      (0UL)        /* CURPIPE (Bit 0) */
+#define RUSB2_CFIFOSEL_CURPIPE_Msk      (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+
+// CFIFOCTR
+#define RUSB2_CFIFOCTR_BVAL_Pos         (15UL)       /* BVAL (Bit 15) */
+#define RUSB2_CFIFOCTR_BVAL_Msk         (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOCTR_BCLR_Pos         (14UL)       /* BCLR (Bit 14) */
+#define RUSB2_CFIFOCTR_BCLR_Msk         (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOCTR_FRDY_Pos         (13UL)       /* FRDY (Bit 13) */
+#define RUSB2_CFIFOCTR_FRDY_Msk         (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOCTR_DTLN_Pos         (0UL)        /* DTLN (Bit 0) */
+#define RUSB2_CFIFOCTR_DTLN_Msk         (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+
+// D0FIFOSEL
+#define RUSB2_D0FIFOSEL_RCNT_Pos        (15UL)       /* RCNT (Bit 15) */
+#define RUSB2_D0FIFOSEL_RCNT_Msk        (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_REW_Pos         (14UL)       /* REW (Bit 14) */
+#define RUSB2_D0FIFOSEL_REW_Msk         (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_DCLRM_Pos       (13UL)       /* DCLRM (Bit 13) */
+#define RUSB2_D0FIFOSEL_DCLRM_Msk       (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_DREQE_Pos       (12UL)       /* DREQE (Bit 12) */
+#define RUSB2_D0FIFOSEL_DREQE_Msk       (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_MBW_Pos         (10UL)       /* MBW (Bit 10) */
+#define RUSB2_D0FIFOSEL_MBW_Msk         (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define RUSB2_D0FIFOSEL_BIGEND_Pos      (8UL)        /* BIGEND (Bit 8) */
+#define RUSB2_D0FIFOSEL_BIGEND_Msk      (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_CURPIPE_Pos     (0UL)        /* CURPIPE (Bit 0) */
+#define RUSB2_D0FIFOSEL_CURPIPE_Msk     (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+
+// D0FIFOCTR
+#define RUSB2_D0FIFOCTR_BVAL_Pos        (15UL)       /* BVAL (Bit 15) */
+#define RUSB2_D0FIFOCTR_BVAL_Msk        (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOCTR_BCLR_Pos        (14UL)       /* BCLR (Bit 14) */
+#define RUSB2_D0FIFOCTR_BCLR_Msk        (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOCTR_FRDY_Pos        (13UL)       /* FRDY (Bit 13) */
+#define RUSB2_D0FIFOCTR_FRDY_Msk        (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOCTR_DTLN_Pos        (0UL)        /* DTLN (Bit 0) */
+#define RUSB2_D0FIFOCTR_DTLN_Msk        (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+
+// D1FIFOSEL
+#define RUSB2_D1FIFOSEL_RCNT_Pos        (15UL)       /* RCNT (Bit 15) */
+#define RUSB2_D1FIFOSEL_RCNT_Msk        (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_REW_Pos         (14UL)       /* REW (Bit 14) */
+#define RUSB2_D1FIFOSEL_REW_Msk         (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_DCLRM_Pos       (13UL)       /* DCLRM (Bit 13) */
+#define RUSB2_D1FIFOSEL_DCLRM_Msk       (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_DREQE_Pos       (12UL)       /* DREQE (Bit 12) */
+#define RUSB2_D1FIFOSEL_DREQE_Msk       (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_MBW_Pos         (10UL)       /* MBW (Bit 10) */
+#define RUSB2_D1FIFOSEL_MBW_Msk         (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define RUSB2_D1FIFOSEL_BIGEND_Pos      (8UL)        /* BIGEND (Bit 8) */
+#define RUSB2_D1FIFOSEL_BIGEND_Msk      (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_CURPIPE_Pos     (0UL)        /* CURPIPE (Bit 0) */
+#define RUSB2_D1FIFOSEL_CURPIPE_Msk     (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+
+// D1FIFOCTR
+#define RUSB2_D1FIFOCTR_BVAL_Pos        (15UL)       /* BVAL (Bit 15) */
+#define RUSB2_D1FIFOCTR_BVAL_Msk        (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOCTR_BCLR_Pos        (14UL)       /* BCLR (Bit 14) */
+#define RUSB2_D1FIFOCTR_BCLR_Msk        (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOCTR_FRDY_Pos        (13UL)       /* FRDY (Bit 13) */
+#define RUSB2_D1FIFOCTR_FRDY_Msk        (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOCTR_DTLN_Pos        (0UL)        /* DTLN (Bit 0) */
+#define RUSB2_D1FIFOCTR_DTLN_Msk        (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+
+// INTENB0
+#define RUSB2_INTENB0_VBSE_Pos          (15UL)       /* VBSE (Bit 15) */
+#define RUSB2_INTENB0_VBSE_Msk          (0x8000UL)   /* VBSE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_RSME_Pos          (14UL)       /* RSME (Bit 14) */
+#define RUSB2_INTENB0_RSME_Msk          (0x4000UL)   /* RSME (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_SOFE_Pos          (13UL)       /* SOFE (Bit 13) */
+#define RUSB2_INTENB0_SOFE_Msk          (0x2000UL)   /* SOFE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_DVSE_Pos          (12UL)       /* DVSE (Bit 12) */
+#define RUSB2_INTENB0_DVSE_Msk          (0x1000UL)   /* DVSE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_CTRE_Pos          (11UL)       /* CTRE (Bit 11) */
+#define RUSB2_INTENB0_CTRE_Msk          (0x800UL)    /* CTRE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_BEMPE_Pos         (10UL)       /* BEMPE (Bit 10) */
+#define RUSB2_INTENB0_BEMPE_Msk         (0x400UL)    /* BEMPE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_NRDYE_Pos         (9UL)        /* NRDYE (Bit 9) */
+#define RUSB2_INTENB0_NRDYE_Msk         (0x200UL)    /* NRDYE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_BRDYE_Pos         (8UL)        /* BRDYE (Bit 8) */
+#define RUSB2_INTENB0_BRDYE_Msk         (0x100UL)    /* BRDYE (Bitfield-Mask: 0x01) */
+
+// INTENB1
+#define RUSB2_INTENB1_OVRCRE_Pos        (15UL)       /* OVRCRE (Bit 15) */
+#define RUSB2_INTENB1_OVRCRE_Msk        (0x8000UL)   /* OVRCRE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_BCHGE_Pos         (14UL)       /* BCHGE (Bit 14) */
+#define RUSB2_INTENB1_BCHGE_Msk         (0x4000UL)   /* BCHGE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_DTCHE_Pos         (12UL)       /* DTCHE (Bit 12) */
+#define RUSB2_INTENB1_DTCHE_Msk         (0x1000UL)   /* DTCHE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_ATTCHE_Pos        (11UL)       /* ATTCHE (Bit 11) */
+#define RUSB2_INTENB1_ATTCHE_Msk        (0x800UL)    /* ATTCHE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_L1RSMENDE_Pos     (9UL)        /*!< L1RSMENDE (Bit 9)                                     */
+#define RUSB2_INTENB1_L1RSMENDE_Msk     (0x200UL)    /*!< L1RSMENDE (Bitfield-Mask: 0x01)                       */
+#define RUSB2_INTENB1_LPMENDE_Pos       (8UL)        /*!< LPMENDE (Bit 8)                                       */
+#define RUSB2_INTENB1_LPMENDE_Msk       (0x100UL)    /*!< LPMENDE (Bitfield-Mask: 0x01)                         */
+#define RUSB2_INTENB1_EOFERRE_Pos       (6UL)        /* EOFERRE (Bit 6) */
+#define RUSB2_INTENB1_EOFERRE_Msk       (0x40UL)     /* EOFERRE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_SIGNE_Pos         (5UL)        /* SIGNE (Bit 5) */
+#define RUSB2_INTENB1_SIGNE_Msk         (0x20UL)     /* SIGNE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_SACKE_Pos         (4UL)        /* SACKE (Bit 4) */
+#define RUSB2_INTENB1_SACKE_Msk         (0x10UL)     /* SACKE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_PDDETINTE0_Pos    (0UL)        /* PDDETINTE0 (Bit 0) */
+#define RUSB2_INTENB1_PDDETINTE0_Msk    (0x1UL)      /* PDDETINTE0 (Bitfield-Mask: 0x01) */
+
+// BRDYENB
+#define RUSB2_BRDYENB_PIPEBRDYE_Pos     (0UL)        /* PIPEBRDYE (Bit 0) */
+#define RUSB2_BRDYENB_PIPEBRDYE_Msk     (0x1UL)      /* PIPEBRDYE (Bitfield-Mask: 0x01) */
+
+// NRDYENB
+#define RUSB2_NRDYENB_PIPENRDYE_Pos     (0UL)        /* PIPENRDYE (Bit 0) */
+#define RUSB2_NRDYENB_PIPENRDYE_Msk     (0x1UL)      /* PIPENRDYE (Bitfield-Mask: 0x01) */
+
+// BEMPENB
+#define RUSB2_BEMPENB_PIPEBEMPE_Pos     (0UL)        /* PIPEBEMPE (Bit 0) */
+#define RUSB2_BEMPENB_PIPEBEMPE_Msk     (0x1UL)      /* PIPEBEMPE (Bitfield-Mask: 0x01) */
+
+// SOFCFG
+#define RUSB2_SOFCFG_TRNENSEL_Pos       (8UL)        /* TRNENSEL (Bit 8) */
+#define RUSB2_SOFCFG_TRNENSEL_Msk       (0x100UL)    /* TRNENSEL (Bitfield-Mask: 0x01) */
+#define RUSB2_SOFCFG_BRDYM_Pos          (6UL)        /* BRDYM (Bit 6) */
+#define RUSB2_SOFCFG_BRDYM_Msk          (0x40UL)     /* BRDYM (Bitfield-Mask: 0x01) */
+#define RUSB2_SOFCFG_INTL_Pos           (5UL)        /* INTL (Bit 5) */
+#define RUSB2_SOFCFG_INTL_Msk           (0x20UL)     /* INTL (Bitfield-Mask: 0x01) */
+#define RUSB2_SOFCFG_EDGESTS_Pos        (4UL)        /* EDGESTS (Bit 4) */
+#define RUSB2_SOFCFG_EDGESTS_Msk        (0x10UL)     /* EDGESTS (Bitfield-Mask: 0x01) */
+
+// PHYSET
+#define RUSB2_PHYSET_HSEB_Pos           (15UL)       /* HSEB (Bit 15) */
+#define RUSB2_PHYSET_HSEB_Msk           (0x8000UL)   /* HSEB (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSET_REPSTART_Pos       (11UL)       /* REPSTART (Bit 11) */
+#define RUSB2_PHYSET_REPSTART_Msk       (0x800UL)    /* REPSTART (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSET_REPSEL_Pos         (8UL)        /* REPSEL (Bit 8) */
+#define RUSB2_PHYSET_REPSEL_Msk         (0x300UL)    /* REPSEL (Bitfield-Mask: 0x03) */
+#define RUSB2_PHYSET_CLKSEL_Pos         (4UL)        /* CLKSEL (Bit 4) */
+#define RUSB2_PHYSET_CLKSEL_Msk         (0x30UL)     /* CLKSEL (Bitfield-Mask: 0x03) */
+#define RUSB2_PHYSET_CDPEN_Pos          (3UL)        /* CDPEN (Bit 3) */
+#define RUSB2_PHYSET_CDPEN_Msk          (0x8UL)      /* CDPEN (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSET_PLLRESET_Pos       (1UL)        /* PLLRESET (Bit 1) */
+#define RUSB2_PHYSET_PLLRESET_Msk       (0x2UL)      /* PLLRESET (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSET_DIRPD_Pos          (0UL)        /* DIRPD (Bit 0) */
+#define RUSB2_PHYSET_DIRPD_Msk          (0x1UL)      /* DIRPD (Bitfield-Mask: 0x01) */
+
+// INTSTS0
+#define RUSB2_INTSTS0_VBINT_Pos         (15UL)       /* VBINT (Bit 15) */
+#define RUSB2_INTSTS0_VBINT_Msk         (0x8000UL)   /* VBINT (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_RESM_Pos          (14UL)       /* RESM (Bit 14) */
+#define RUSB2_INTSTS0_RESM_Msk          (0x4000UL)   /* RESM (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_SOFR_Pos          (13UL)       /* SOFR (Bit 13) */
+#define RUSB2_INTSTS0_SOFR_Msk          (0x2000UL)   /* SOFR (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_DVST_Pos          (12UL)       /* DVST (Bit 12) */
+#define RUSB2_INTSTS0_DVST_Msk          (0x1000UL)   /* DVST (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_CTRT_Pos          (11UL)       /* CTRT (Bit 11) */
+#define RUSB2_INTSTS0_CTRT_Msk          (0x800UL)    /* CTRT (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_BEMP_Pos          (10UL)       /* BEMP (Bit 10) */
+#define RUSB2_INTSTS0_BEMP_Msk          (0x400UL)    /* BEMP (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_NRDY_Pos          (9UL)        /* NRDY (Bit 9) */
+#define RUSB2_INTSTS0_NRDY_Msk          (0x200UL)    /* NRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_BRDY_Pos          (8UL)        /* BRDY (Bit 8) */
+#define RUSB2_INTSTS0_BRDY_Msk          (0x100UL)    /* BRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_VBSTS_Pos         (7UL)        /* VBSTS (Bit 7) */
+#define RUSB2_INTSTS0_VBSTS_Msk         (0x80UL)     /* VBSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_DVSQ_Pos          (4UL)        /* DVSQ (Bit 4) */
+#define RUSB2_INTSTS0_DVSQ_Msk          (0x70UL)     /* DVSQ (Bitfield-Mask: 0x07) */
+#define RUSB2_INTSTS0_VALID_Pos         (3UL)        /* VALID (Bit 3) */
+#define RUSB2_INTSTS0_VALID_Msk         (0x8UL)      /* VALID (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_CTSQ_Pos          (0UL)        /* CTSQ (Bit 0) */
+#define RUSB2_INTSTS0_CTSQ_Msk          (0x7UL)      /* CTSQ (Bitfield-Mask: 0x07) */
+
+// INTSTS1
+#define RUSB2_INTSTS1_OVRCR_Pos         (15UL)       /* OVRCR (Bit 15) */
+#define RUSB2_INTSTS1_OVRCR_Msk         (0x8000UL)   /* OVRCR (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_BCHG_Pos          (14UL)       /* BCHG (Bit 14) */
+#define RUSB2_INTSTS1_BCHG_Msk          (0x4000UL)   /* BCHG (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_DTCH_Pos          (12UL)       /* DTCH (Bit 12) */
+#define RUSB2_INTSTS1_DTCH_Msk          (0x1000UL)   /* DTCH (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_ATTCH_Pos         (11UL)       /* ATTCH (Bit 11) */
+#define RUSB2_INTSTS1_ATTCH_Msk         (0x800UL)    /* ATTCH (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_L1RSMEND_Pos      (9UL)        /* L1RSMEND (Bit 9) */
+#define RUSB2_INTSTS1_L1RSMEND_Msk      (0x200UL)    /* L1RSMEND (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_LPMEND_Pos        (8UL)        /* LPMEND (Bit 8) */
+#define RUSB2_INTSTS1_LPMEND_Msk        (0x100UL)    /* LPMEND (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_EOFERR_Pos        (6UL)        /* EOFERR (Bit 6) */
+#define RUSB2_INTSTS1_EOFERR_Msk        (0x40UL)     /* EOFERR (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_SIGN_Pos          (5UL)        /* SIGN (Bit 5) */
+#define RUSB2_INTSTS1_SIGN_Msk          (0x20UL)     /* SIGN (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_SACK_Pos          (4UL)        /* SACK (Bit 4) */
+#define RUSB2_INTSTS1_SACK_Msk          (0x10UL)     /* SACK (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_PDDETINT0_Pos     (0UL)        /* PDDETINT0 (Bit 0) */
+#define RUSB2_INTSTS1_PDDETINT0_Msk     (0x1UL)      /* PDDETINT0 (Bitfield-Mask: 0x01) */
+
+// BRDYSTS
+#define RUSB2_BRDYSTS_PIPEBRDY_Pos      (0UL)        /* PIPEBRDY (Bit 0) */
+#define RUSB2_BRDYSTS_PIPEBRDY_Msk      (0x1UL)      /* PIPEBRDY (Bitfield-Mask: 0x01) */
+
+// NRDYSTS
+#define RUSB2_NRDYSTS_PIPENRDY_Pos      (0UL)        /* PIPENRDY (Bit 0) */
+#define RUSB2_NRDYSTS_PIPENRDY_Msk      (0x1UL)      /* PIPENRDY (Bitfield-Mask: 0x01) */
+
+// BEMPSTS
+#define RUSB2_BEMPSTS_PIPEBEMP_Pos      (0UL)        /* PIPEBEMP (Bit 0) */
+#define RUSB2_BEMPSTS_PIPEBEMP_Msk      (0x1UL)      /* PIPEBEMP (Bitfield-Mask: 0x01) */
+
+// FRMNUM
+#define RUSB2_FRMNUM_OVRN_Pos           (15UL)       /* OVRN (Bit 15) */
+#define RUSB2_FRMNUM_OVRN_Msk           (0x8000UL)   /* OVRN (Bitfield-Mask: 0x01) */
+#define RUSB2_FRMNUM_CRCE_Pos           (14UL)       /* CRCE (Bit 14) */
+#define RUSB2_FRMNUM_CRCE_Msk           (0x4000UL)   /* CRCE (Bitfield-Mask: 0x01) */
+#define RUSB2_FRMNUM_FRNM_Pos           (0UL)        /* FRNM (Bit 0) */
+#define RUSB2_FRMNUM_FRNM_Msk           (0x7ffUL)    /* FRNM (Bitfield-Mask: 0x7ff) */
+
+// UFRMNUM
+#define RUSB2_UFRMNUM_DVCHG_Pos         (15UL)       /* DVCHG (Bit 15) */
+#define RUSB2_UFRMNUM_DVCHG_Msk         (0x8000UL)   /* DVCHG (Bitfield-Mask: 0x01) */
+#define RUSB2_UFRMNUM_UFRNM_Pos         (0UL)        /* UFRNM (Bit 0) */
+#define RUSB2_UFRMNUM_UFRNM_Msk         (0x7UL)      /* UFRNM (Bitfield-Mask: 0x07) */
+
+// USBADDR
+#define RUSB2_USBADDR_STSRECOV0_Pos     (8UL)        /* STSRECOV0 (Bit 8) */
+#define RUSB2_USBADDR_STSRECOV0_Msk     (0x700UL)    /* STSRECOV0 (Bitfield-Mask: 0x07) */
+#define RUSB2_USBADDR_USBADDR_Pos       (0UL)        /* USBADDR (Bit 0) */
+#define RUSB2_USBADDR_USBADDR_Msk       (0x7fUL)     /* USBADDR (Bitfield-Mask: 0x7f) */
+
+// USBREQ
+#define RUSB2_USBREQ_BREQUEST_Pos       (8UL)        /* BREQUEST (Bit 8) */
+#define RUSB2_USBREQ_BREQUEST_Msk       (0xff00UL)   /* BREQUEST (Bitfield-Mask: 0xff) */
+#define RUSB2_USBREQ_BMREQUESTTYPE_Pos  (0UL)        /* BMREQUESTTYPE (Bit 0) */
+#define RUSB2_USBREQ_BMREQUESTTYPE_Msk  (0xffUL)     /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */
+
+// USBVAL
+#define RUSB2_USBVAL_WVALUE_Pos         (0UL)        /* WVALUE (Bit 0) */
+#define RUSB2_USBVAL_WVALUE_Msk         (0xffffUL)   /* WVALUE (Bitfield-Mask: 0xffff) */
+
+// USBINDX
+#define RUSB2_USBINDX_WINDEX_Pos        (0UL)        /* WINDEX (Bit 0) */
+#define RUSB2_USBINDX_WINDEX_Msk        (0xffffUL)   /* WINDEX (Bitfield-Mask: 0xffff) */
+
+// USBLENG
+#define RUSB2_USBLENG_WLENGTH_Pos       (0UL)        /* WLENGTH (Bit 0) */
+#define RUSB2_USBLENG_WLENGTH_Msk       (0xffffUL)   /* WLENGTH (Bitfield-Mask: 0xffff) */
+
+// DCPCFG
+#define RUSB2_DCPCFG_CNTMD_Pos          (8UL)        /* CNTMD (Bit 8) */
+#define RUSB2_DCPCFG_CNTMD_Msk          (0x100UL)    /* CNTMD (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCFG_SHTNAK_Pos         (7UL)        /* SHTNAK (Bit 7) */
+#define RUSB2_DCPCFG_SHTNAK_Msk         (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCFG_DIR_Pos            (4UL)        /* DIR (Bit 4) */
+#define RUSB2_DCPCFG_DIR_Msk            (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
+
+// DCPMAXP
+#define RUSB2_DCPMAXP_DEVSEL_Pos        (12UL)       /* DEVSEL (Bit 12) */
+#define RUSB2_DCPMAXP_DEVSEL_Msk        (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define RUSB2_DCPMAXP_MXPS_Pos          (0UL)        /* MXPS (Bit 0) */
+#define RUSB2_DCPMAXP_MXPS_Msk          (0x7fUL)     /* MXPS (Bitfield-Mask: 0x7f) */
+
+// DCPCTR
+#define RUSB2_DCPCTR_BSTS_Pos           (15UL)       /* BSTS (Bit 15) */
+#define RUSB2_DCPCTR_BSTS_Msk           (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_SUREQ_Pos          (14UL)       /* SUREQ (Bit 14) */
+#define RUSB2_DCPCTR_SUREQ_Msk          (0x4000UL)   /* SUREQ (Bitfield-Mask: 0x01) */
+#define R_USB_HS0_DCPCTR_CSCLR_Pos      (13UL)       /*!< CSCLR (Bit 13)                                        */
+#define RUSB2_DCPCTR_CSCLR_Msk          (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
+#define RUSB2_DCPCTR_CSSTS_Pos          (12UL)       /*!< CSSTS (Bit 12)                                        */
+#define RUSB2_DCPCTR_CSSTS_Msk          (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
+#define RUSB2_DCPCTR_SUREQCLR_Pos       (11UL)       /* SUREQCLR (Bit 11) */
+#define RUSB2_DCPCTR_SUREQCLR_Msk       (0x800UL)    /* SUREQCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_SQCLR_Pos          (8UL)        /* SQCLR (Bit 8) */
+#define RUSB2_DCPCTR_SQCLR_Msk          (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_SQSET_Pos          (7UL)        /* SQSET (Bit 7) */
+#define RUSB2_DCPCTR_SQSET_Msk          (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_SQMON_Pos          (6UL)        /* SQMON (Bit 6) */
+#define RUSB2_DCPCTR_SQMON_Msk          (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_PBUSY_Pos          (5UL)        /* PBUSY (Bit 5) */
+#define RUSB2_DCPCTR_PBUSY_Msk          (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_CCPL_Pos           (2UL)        /* CCPL (Bit 2) */
+#define RUSB2_DCPCTR_CCPL_Msk           (0x4UL)      /* CCPL (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_PID_Pos            (0UL)        /* PID (Bit 0) */
+#define RUSB2_DCPCTR_PID_Msk            (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
+
+// PIPESEL
+#define RUSB2_PIPESEL_PIPESEL_Pos       (0UL)        /* PIPESEL (Bit 0) */
+#define RUSB2_PIPESEL_PIPESEL_Msk       (0xfUL)      /* PIPESEL (Bitfield-Mask: 0x0f) */
+
+// PIPECFG
+#define RUSB2_PIPECFG_TYPE_Pos          (14UL)       /* TYPE (Bit 14) */
+#define RUSB2_PIPECFG_TYPE_Msk          (0xc000UL)   /* TYPE (Bitfield-Mask: 0x03) */
+#define RUSB2_PIPECFG_BFRE_Pos          (10UL)       /* BFRE (Bit 10) */
+#define RUSB2_PIPECFG_BFRE_Msk          (0x400UL)    /* BFRE (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_DBLB_Pos          (9UL)        /* DBLB (Bit 9) */
+#define RUSB2_PIPECFG_DBLB_Msk          (0x200UL)    /* DBLB (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_CNTMD_Pos         (8UL)        /*!< CNTMD (Bit 8)                                         */
+#define RUSB2_PIPECFG_CNTMD_Msk         (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+#define RUSB2_PIPECFG_SHTNAK_Pos        (7UL)        /* SHTNAK (Bit 7) */
+#define RUSB2_PIPECFG_SHTNAK_Msk        (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_DIR_Pos           (4UL)        /* DIR (Bit 4) */
+#define RUSB2_PIPECFG_DIR_Msk           (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_EPNUM_Pos         (0UL)        /* EPNUM (Bit 0) */
+#define RUSB2_PIPECFG_EPNUM_Msk         (0xfUL)      /* EPNUM (Bitfield-Mask: 0x0f) */
+
+// PIPEBUF
+#define RUSB2_PIPEBUF_BUFSIZE_Pos       (10UL)       /*!< BUFSIZE (Bit 10)                                      */
+#define RUSB2_PIPEBUF_BUFSIZE_Msk       (0x7c00UL)   /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
+#define RUSB2_PIPEBUF_BUFNMB_Pos        (0UL)        /*!< BUFNMB (Bit 0)                                        */
+#define RUSB2_PIPEBUF_BUFNMB_Msk        (0xffUL)     /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
+
+// PIPEMAXP
+#define RUSB2_PIPEMAXP_DEVSEL_Pos       (12UL)       /* DEVSEL (Bit 12) */
+#define RUSB2_PIPEMAXP_DEVSEL_Msk       (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define RUSB2_PIPEMAXP_MXPS_Pos         (0UL)        /* MXPS (Bit 0) */
+#define RUSB2_PIPEMAXP_MXPS_Msk         (0x1ffUL)    /* MXPS (Bitfield-Mask: 0x1ff) */
+
+// PIPEPERI
+#define RUSB2_PIPEPERI_IFIS_Pos         (12UL)       /* IFIS (Bit 12) */
+#define RUSB2_PIPEPERI_IFIS_Msk         (0x1000UL)   /* IFIS (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPEPERI_IITV_Pos         (0UL)        /* IITV (Bit 0) */
+#define RUSB2_PIPEPERI_IITV_Msk         (0x7UL)      /* IITV (Bitfield-Mask: 0x07) */
+
+// PIPE_CTR
+#define RUSB2_PIPE_CTR_BSTS_Pos         (15UL)       /* BSTS (Bit 15) */
+#define RUSB2_PIPE_CTR_BSTS_Msk         (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_INBUFM_Pos       (14UL)       /* INBUFM (Bit 14) */
+#define RUSB2_PIPE_CTR_INBUFM_Msk       (0x4000UL)   /* INBUFM (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_CSCLR_Pos        (13UL)       /* CSCLR (Bit 13) */
+#define RUSB2_PIPE_CTR_CSCLR_Msk        (0x2000UL)   /* CSCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_CSSTS_Pos        (12UL)       /* CSSTS (Bit 12) */
+#define RUSB2_PIPE_CTR_CSSTS_Msk        (0x1000UL)   /* CSSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_ATREPM_Pos       (10UL)       /* ATREPM (Bit 10) */
+#define RUSB2_PIPE_CTR_ATREPM_Msk       (0x400UL)    /* ATREPM (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_ACLRM_Pos        (9UL)        /* ACLRM (Bit 9) */
+#define RUSB2_PIPE_CTR_ACLRM_Msk        (0x200UL)    /* ACLRM (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_SQCLR_Pos        (8UL)        /* SQCLR (Bit 8) */
+#define RUSB2_PIPE_CTR_SQCLR_Msk        (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_SQSET_Pos        (7UL)        /* SQSET (Bit 7) */
+#define RUSB2_PIPE_CTR_SQSET_Msk        (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_SQMON_Pos        (6UL)        /* SQMON (Bit 6) */
+#define RUSB2_PIPE_CTR_SQMON_Msk        (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_PBUSY_Pos        (5UL)        /* PBUSY (Bit 5) */
+#define RUSB2_PIPE_CTR_PBUSY_Msk        (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_PID_Pos          (0UL)        /* PID (Bit 0) */
+#define RUSB2_PIPE_CTR_PID_Msk          (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
+
+// DEVADD
+#define RUSB2_DEVADD_UPPHUB_Pos         (11UL)       /* UPPHUB (Bit 11) */
+#define RUSB2_DEVADD_UPPHUB_Msk         (0x7800UL)   /* UPPHUB (Bitfield-Mask: 0x0f) */
+#define RUSB2_DEVADD_HUBPORT_Pos        (8UL)        /* HUBPORT (Bit 8) */
+#define RUSB2_DEVADD_HUBPORT_Msk        (0x700UL)    /* HUBPORT (Bitfield-Mask: 0x07) */
+#define RUSB2_DEVADD_USBSPD_Pos         (6UL)        /* USBSPD (Bit 6) */
+#define RUSB2_DEVADD_USBSPD_Msk         (0xc0UL)     /* USBSPD (Bitfield-Mask: 0x03) */
+
+// USBBCCTRL0
+#define RUSB2_USBBCCTRL0_PDDETSTS0_Pos  (9UL)        /* PDDETSTS0 (Bit 9) */
+#define RUSB2_USBBCCTRL0_PDDETSTS0_Msk  (0x200UL)    /* PDDETSTS0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_CHGDETSTS0_Pos (8UL)        /* CHGDETSTS0 (Bit 8) */
+#define RUSB2_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL)    /* CHGDETSTS0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_BATCHGE0_Pos   (7UL)        /* BATCHGE0 (Bit 7) */
+#define RUSB2_USBBCCTRL0_BATCHGE0_Msk   (0x80UL)     /* BATCHGE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_VDMSRCE0_Pos   (5UL)        /* VDMSRCE0 (Bit 5) */
+#define RUSB2_USBBCCTRL0_VDMSRCE0_Msk   (0x20UL)     /* VDMSRCE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_IDPSINKE0_Pos  (4UL)        /* IDPSINKE0 (Bit 4) */
+#define RUSB2_USBBCCTRL0_IDPSINKE0_Msk  (0x10UL)     /* IDPSINKE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_VDPSRCE0_Pos   (3UL)        /* VDPSRCE0 (Bit 3) */
+#define RUSB2_USBBCCTRL0_VDPSRCE0_Msk   (0x8UL)      /* VDPSRCE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_IDMSINKE0_Pos  (2UL)        /* IDMSINKE0 (Bit 2) */
+#define RUSB2_USBBCCTRL0_IDMSINKE0_Msk  (0x4UL)      /* IDMSINKE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_IDPSRCE0_Pos   (1UL)        /* IDPSRCE0 (Bit 1) */
+#define RUSB2_USBBCCTRL0_IDPSRCE0_Msk   (0x2UL)      /* IDPSRCE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_RPDME0_Pos     (0UL)        /* RPDME0 (Bit 0) */
+#define RUSB2_USBBCCTRL0_RPDME0_Msk     (0x1UL)      /* RPDME0 (Bitfield-Mask: 0x01) */
+
+// UCKSEL
+#define RUSB2_UCKSEL_UCKSELC_Pos        (0UL)        /* UCKSELC (Bit 0) */
+#define RUSB2_UCKSEL_UCKSELC_Msk        (0x1UL)      /* UCKSELC (Bitfield-Mask: 0x01) */
+
+// USBMC
+#define RUSB2_USBMC_VDCEN_Pos           (7UL)        /* VDCEN (Bit 7) */
+#define RUSB2_USBMC_VDCEN_Msk           (0x80UL)     /* VDCEN (Bitfield-Mask: 0x01) */
+#define RUSB2_USBMC_VDDUSBE_Pos         (0UL)        /* VDDUSBE (Bit 0) */
+#define RUSB2_USBMC_VDDUSBE_Msk         (0x1UL)      /* VDDUSBE (Bitfield-Mask: 0x01) */
+
+// PHYSLEW
+#define RUSB2_PHYSLEW_SLEWF01_Pos       (3UL)        /* SLEWF01 (Bit 3) */
+#define RUSB2_PHYSLEW_SLEWF01_Msk       (0x8UL)      /* SLEWF01 (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSLEW_SLEWF00_Pos       (2UL)        /* SLEWF00 (Bit 2) */
+#define RUSB2_PHYSLEW_SLEWF00_Msk       (0x4UL)      /* SLEWF00 (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSLEW_SLEWR01_Pos       (1UL)        /* SLEWR01 (Bit 1) */
+#define RUSB2_PHYSLEW_SLEWR01_Msk       (0x2UL)      /* SLEWR01 (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSLEW_SLEWR00_Pos       (0UL)        /* SLEWR00 (Bit 0) */
+#define RUSB2_PHYSLEW_SLEWR00_Msk       (0x1UL)      /* SLEWR00 (Bitfield-Mask: 0x01) */
+
+// LPCTRL
+#define RUSB2_LPCTRL_HWUPM_Pos          (7UL)        /* HWUPM (Bit 7) */
+#define RUSB2_LPCTRL_HWUPM_Msk          (0x80UL)     /* HWUPM (Bitfield-Mask: 0x01) */
+
+// LPSTS
+#define RUSB2_LPSTS_SUSPENDM_Pos        (14UL)       /* SUSPENDM (Bit 14) */
+#define RUSB2_LPSTS_SUSPENDM_Msk        (0x4000UL)   /* SUSPENDM (Bitfield-Mask: 0x01) */
+
+// BCCTRL
+#define RUSB2_BCCTRL_PDDETSTS_Pos       (9UL)        /* PDDETSTS (Bit 9) */
+#define RUSB2_BCCTRL_PDDETSTS_Msk       (0x200UL)    /* PDDETSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_CHGDETSTS_Pos      (8UL)        /* CHGDETSTS (Bit 8) */
+#define RUSB2_BCCTRL_CHGDETSTS_Msk      (0x100UL)    /* CHGDETSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_DCPMODE_Pos        (5UL)        /* DCPMODE (Bit 5) */
+#define RUSB2_BCCTRL_DCPMODE_Msk        (0x20UL)     /* DCPMODE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_VDMSRCE_Pos        (4UL)        /* VDMSRCE (Bit 4) */
+#define RUSB2_BCCTRL_VDMSRCE_Msk        (0x10UL)     /* VDMSRCE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_IDPSINKE_Pos       (3UL)        /* IDPSINKE (Bit 3) */
+#define RUSB2_BCCTRL_IDPSINKE_Msk       (0x8UL)      /* IDPSINKE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_VDPSRCE_Pos        (2UL)        /* VDPSRCE (Bit 2) */
+#define RUSB2_BCCTRL_VDPSRCE_Msk        (0x4UL)      /* VDPSRCE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_IDMSINKE_Pos       (1UL)        /* IDMSINKE (Bit 1) */
+#define RUSB2_BCCTRL_IDMSINKE_Msk       (0x2UL)      /* IDMSINKE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_IDPSRCE_Pos        (0UL)        /* IDPSRCE (Bit 0) */
+#define RUSB2_BCCTRL_IDPSRCE_Msk        (0x1UL)      /* IDPSRCE (Bitfield-Mask: 0x01) */
+
+// PL1CTRL1
+#define RUSB2_PL1CTRL1_L1EXTMD_Pos      (14UL)       /* L1EXTMD (Bit 14) */
+#define RUSB2_PL1CTRL1_L1EXTMD_Msk      (0x4000UL)   /* L1EXTMD (Bitfield-Mask: 0x01) */
+#define RUSB2_PL1CTRL1_HIRDTHR_Pos      (8UL)        /* HIRDTHR (Bit 8) */
+#define RUSB2_PL1CTRL1_HIRDTHR_Msk      (0xf00UL)    /* HIRDTHR (Bitfield-Mask: 0x0f) */
+#define RUSB2_PL1CTRL1_DVSQ_Pos         (4UL)        /* DVSQ (Bit 4) */
+#define RUSB2_PL1CTRL1_DVSQ_Msk         (0xf0UL)     /* DVSQ (Bitfield-Mask: 0x0f) */
+#define RUSB2_PL1CTRL1_L1NEGOMD_Pos     (3UL)        /* L1NEGOMD (Bit 3) */
+#define RUSB2_PL1CTRL1_L1NEGOMD_Msk     (0x8UL)      /* L1NEGOMD (Bitfield-Mask: 0x01) */
+#define RUSB2_PL1CTRL1_L1RESPMD_Pos     (1UL)        /* L1RESPMD (Bit 1) */
+#define RUSB2_PL1CTRL1_L1RESPMD_Msk     (0x6UL)      /* L1RESPMD (Bitfield-Mask: 0x03) */
+#define RUSB2_PL1CTRL1_L1RESPEN_Pos     (0UL)        /* L1RESPEN (Bit 0) */
+#define RUSB2_PL1CTRL1_L1RESPEN_Msk     (0x1UL)      /* L1RESPEN (Bitfield-Mask: 0x01) */
+
+// PL1CTRL2
+#define RUSB2_PL1CTRL2_RWEMON_Pos       (12UL)       /* RWEMON (Bit 12) */
+#define RUSB2_PL1CTRL2_RWEMON_Msk       (0x1000UL)   /* RWEMON (Bitfield-Mask: 0x01) */
+#define RUSB2_PL1CTRL2_HIRDMON_Pos      (8UL)        /* HIRDMON (Bit 8) */
+#define RUSB2_PL1CTRL2_HIRDMON_Msk      (0xf00UL)    /* HIRDMON (Bitfield-Mask: 0x0f) */
+
+// HL1CTRL1
+#define RUSB2_HL1CTRL1_L1STATUS_Pos     (1UL)        /* L1STATUS (Bit 1) */
+#define RUSB2_HL1CTRL1_L1STATUS_Msk     (0x6UL)      /* L1STATUS (Bitfield-Mask: 0x03) */
+#define RUSB2_HL1CTRL1_L1REQ_Pos        (0UL)        /* L1REQ (Bit 0) */
+#define RUSB2_HL1CTRL1_L1REQ_Msk        (0x1UL)      /* L1REQ (Bitfield-Mask: 0x01) */
+
+// HL1CTRL2
+#define RUSB2_HL1CTRL2_BESL_Pos         (15UL)       /* BESL (Bit 15) */
+#define RUSB2_HL1CTRL2_BESL_Msk         (0x8000UL)   /* BESL (Bitfield-Mask: 0x01) */
+#define RUSB2_HL1CTRL2_L1RWE_Pos        (12UL)       /* L1RWE (Bit 12) */
+#define RUSB2_HL1CTRL2_L1RWE_Msk        (0x1000UL)   /* L1RWE (Bitfield-Mask: 0x01) */
+#define RUSB2_HL1CTRL2_HIRD_Pos         (8UL)        /* HIRD (Bit 8) */
+#define RUSB2_HL1CTRL2_HIRD_Msk         (0xf00UL)    /* HIRD (Bitfield-Mask: 0x0f) */
+#define RUSB2_HL1CTRL2_L1ADDR_Pos       (0UL)        /* L1ADDR (Bit 0) */
+#define RUSB2_HL1CTRL2_L1ADDR_Msk       (0xfUL)      /* L1ADDR (Bitfield-Mask: 0x0f) */
+
+// PHYTRIM1
+#define RUSB2_PHYTRIM1_IMPOFFSET_Pos    (12UL)       /*!< IMPOFFSET (Bit 12)                                    */
+#define RUSB2_PHYTRIM1_IMPOFFSET_Msk    (0x7000UL)   /*!< IMPOFFSET (Bitfield-Mask: 0x07)                       */
+#define RUSB2_PHYTRIM1_HSIUP_Pos        (8UL)        /*!< HSIUP (Bit 8)                                         */
+#define RUSB2_PHYTRIM1_HSIUP_Msk        (0xf00UL)    /*!< HSIUP (Bitfield-Mask: 0x0f)                           */
+#define RUSB2_PHYTRIM1_PCOMPENB_Pos     (7UL)        /*!< PCOMPENB (Bit 7)                                      */
+#define RUSB2_PHYTRIM1_PCOMPENB_Msk     (0x80UL)     /*!< PCOMPENB (Bitfield-Mask: 0x01)                        */
+#define RUSB2_PHYTRIM1_DFALL_Pos        (2UL)        /*!< DFALL (Bit 2)                                         */
+#define RUSB2_PHYTRIM1_DFALL_Msk        (0xcUL)      /*!< DFALL (Bitfield-Mask: 0x03)                           */
+#define RUSB2_PHYTRIM1_DRISE_Pos        (0UL)        /*!< DRISE (Bit 0)                                         */
+#define RUSB2_PHYTRIM1_DRISE_Msk        (0x3UL)      /*!< DRISE (Bitfield-Mask: 0x03)                           */
+
+// PHYTRIM2
+#define RUSB2_PHYTRIM2_DIS_Pos          (12UL)       /*!< DIS (Bit 12)                                          */
+#define RUSB2_PHYTRIM2_DIS_Msk          (0x7000UL)   /*!< DIS (Bitfield-Mask: 0x07)                             */
+#define RUSB2_PHYTRIM2_PDR_Pos          (8UL)        /*!< PDR (Bit 8)                                           */
+#define RUSB2_PHYTRIM2_PDR_Msk          (0x300UL)    /*!< PDR (Bitfield-Mask: 0x03)                             */
+#define RUSB2_PHYTRIM2_HSRXENMO_Pos     (7UL)        /*!< HSRXENMO (Bit 7)                                      */
+#define RUSB2_PHYTRIM2_HSRXENMO_Msk     (0x80UL)     /*!< HSRXENMO (Bitfield-Mask: 0x01)                        */
+#define RUSB2_PHYTRIM2_SQU_Pos          (0UL)        /*!< SQU (Bit 0)                                           */
+#define RUSB2_PHYTRIM2_SQU_Msk          (0xfUL)      /*!< SQU (Bitfield-Mask: 0x0f)                             */
+
+// DPUSR0R
+#define RUSB2_DPUSR0R_DVBSTSHM_Pos      (23UL)       /* DVBSTSHM (Bit 23) */
+#define RUSB2_DPUSR0R_DVBSTSHM_Msk      (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_DOVCBHM_Pos       (21UL)       /* DOVCBHM (Bit 21) */
+#define RUSB2_DPUSR0R_DOVCBHM_Msk       (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_DOVCAHM_Pos       (20UL)       /* DOVCAHM (Bit 20) */
+#define RUSB2_DPUSR0R_DOVCAHM_Msk       (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */
+
+// DPUSR1R
+#define RUSB2_DPUSR1R_DVBSTSH_Pos       (23UL)       /* DVBSTSH (Bit 23) */
+#define RUSB2_DPUSR1R_DVBSTSH_Msk       (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DOVCBH_Pos        (21UL)       /* DOVCBH (Bit 21) */
+#define RUSB2_DPUSR1R_DOVCBH_Msk        (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DOVCAH_Pos        (20UL)       /* DOVCAH (Bit 20) */
+#define RUSB2_DPUSR1R_DOVCAH_Msk        (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DVBSTSHE_Pos      (7UL)        /* DVBSTSHE (Bit 7) */
+#define RUSB2_DPUSR1R_DVBSTSHE_Msk      (0x80UL)     /* DVBSTSHE (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DOVCBHE_Pos       (5UL)        /* DOVCBHE (Bit 5) */
+#define RUSB2_DPUSR1R_DOVCBHE_Msk       (0x20UL)     /* DOVCBHE (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DOVCAHE_Pos       (4UL)        /* DOVCAHE (Bit 4) */
+#define RUSB2_DPUSR1R_DOVCAHE_Msk       (0x10UL)     /* DOVCAHE (Bitfield-Mask: 0x01) */
+
+// DPUSR2R
+#define RUSB2_DPUSR2R_DMINTE_Pos        (9UL)        /* DMINTE (Bit 9) */
+#define RUSB2_DPUSR2R_DMINTE_Msk        (0x200UL)    /* DMINTE (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DPINTE_Pos        (8UL)        /* DPINTE (Bit 8) */
+#define RUSB2_DPUSR2R_DPINTE_Msk        (0x100UL)    /* DPINTE (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DMVAL_Pos         (5UL)        /* DMVAL (Bit 5) */
+#define RUSB2_DPUSR2R_DMVAL_Msk         (0x20UL)     /* DMVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DPVAL_Pos         (4UL)        /* DPVAL (Bit 4) */
+#define RUSB2_DPUSR2R_DPVAL_Msk         (0x10UL)     /* DPVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DMINT_Pos         (1UL)        /* DMINT (Bit 1) */
+#define RUSB2_DPUSR2R_DMINT_Msk         (0x2UL)      /* DMINT (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DPINT_Pos         (0UL)        /* DPINT (Bit 0) */
+#define RUSB2_DPUSR2R_DPINT_Msk         (0x1UL)      /* DPINT (Bitfield-Mask: 0x01) */
+
+// DPUSRCR
+#define RUSB2_DPUSRCR_FIXPHYPD_Pos      (1UL)        /* FIXPHYPD (Bit 1) */
+#define RUSB2_DPUSRCR_FIXPHYPD_Msk      (0x2UL)      /* FIXPHYPD (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSRCR_FIXPHY_Pos        (0UL)        /* FIXPHY (Bit 0) */
+#define RUSB2_DPUSRCR_FIXPHY_Msk        (0x1UL)      /* FIXPHY (Bitfield-Mask: 0x01) */
+
+// DPUSR0R_FS
+#define RUSB2_DPUSR0R_FS_DVBSTS0_Pos    (23UL)       /* DVBSTS0 (Bit 23) */
+#define RUSB2_DPUSR0R_FS_DVBSTS0_Msk    (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DOVCB0_Pos     (21UL)       /* DOVCB0 (Bit 21) */
+#define RUSB2_DPUSR0R_FS_DOVCB0_Msk     (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DOVCA0_Pos     (20UL)       /* DOVCA0 (Bit 20) */
+#define RUSB2_DPUSR0R_FS_DOVCA0_Msk     (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DM0_Pos        (17UL)       /* DM0 (Bit 17) */
+#define RUSB2_DPUSR0R_FS_DM0_Msk        (0x20000UL)  /* DM0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DP0_Pos        (16UL)       /* DP0 (Bit 16) */
+#define RUSB2_DPUSR0R_FS_DP0_Msk        (0x10000UL)  /* DP0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_FIXPHY0_Pos    (4UL)        /* FIXPHY0 (Bit 4) */
+#define RUSB2_DPUSR0R_FS_FIXPHY0_Msk    (0x10UL)     /* FIXPHY0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DRPD0_Pos      (3UL)        /* DRPD0 (Bit 3) */
+#define RUSB2_DPUSR0R_FS_DRPD0_Msk      (0x8UL)      /* DRPD0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_RPUE0_Pos      (1UL)        /* RPUE0 (Bit 1) */
+#define RUSB2_DPUSR0R_FS_RPUE0_Msk      (0x2UL)      /* RPUE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_SRPC0_Pos      (0UL)        /* SRPC0 (Bit 0) */
+#define RUSB2_DPUSR0R_FS_SRPC0_Msk      (0x1UL)      /* SRPC0 (Bitfield-Mask: 0x01) */
+
+// DPUSR1R_FS
+#define RUSB2_DPUSR1R_FS_DVBINT0_Pos    (23UL)       /* DVBINT0 (Bit 23) */
+#define RUSB2_DPUSR1R_FS_DVBINT0_Msk    (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DOVRCRB0_Pos   (21UL)       /* DOVRCRB0 (Bit 21) */
+#define RUSB2_DPUSR1R_FS_DOVRCRB0_Msk   (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DOVRCRA0_Pos   (20UL)       /* DOVRCRA0 (Bit 20) */
+#define RUSB2_DPUSR1R_FS_DOVRCRA0_Msk   (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DMINT0_Pos     (17UL)       /* DMINT0 (Bit 17) */
+#define RUSB2_DPUSR1R_FS_DMINT0_Msk     (0x20000UL)  /* DMINT0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DPINT0_Pos     (16UL)       /* DPINT0 (Bit 16) */
+#define RUSB2_DPUSR1R_FS_DPINT0_Msk     (0x10000UL)  /* DPINT0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DVBSE0_Pos     (7UL)        /* DVBSE0 (Bit 7) */
+#define RUSB2_DPUSR1R_FS_DVBSE0_Msk     (0x80UL)     /* DVBSE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DOVRCRBE0_Pos  (5UL)        /* DOVRCRBE0 (Bit 5) */
+#define RUSB2_DPUSR1R_FS_DOVRCRBE0_Msk  (0x20UL)     /* DOVRCRBE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DOVRCRAE0_Pos  (4UL)        /* DOVRCRAE0 (Bit 4) */
+#define RUSB2_DPUSR1R_FS_DOVRCRAE0_Msk  (0x10UL)     /* DOVRCRAE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DMINTE0_Pos    (1UL)        /* DMINTE0 (Bit 1) */
+#define RUSB2_DPUSR1R_FS_DMINTE0_Msk    (0x2UL)      /* DMINTE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DPINTE0_Pos    (0UL)        /* DPINTE0 (Bit 0) */
+#define RUSB2_DPUSR1R_FS_DPINTE0_Msk    (0x1UL)      /* DPINTE0 (Bitfield-Mask: 0x01) */
+
+/*--------------------------------------------------------------------*/
+/* Register Bit Utils                                           */
+/*--------------------------------------------------------------------*/
+#define RUSB2_PIPE_CTR_PID_NAK          (0U << RUSB2_PIPE_CTR_PID_Pos)    /* NAK response */
+#define RUSB2_PIPE_CTR_PID_BUF          (1U << RUSB2_PIPE_CTR_PID_Pos)    /* BUF response (depends buffer state) */
+#define RUSB2_PIPE_CTR_PID_STALL        (2U << RUSB2_PIPE_CTR_PID_Pos)    /* STALL response */
+#define RUSB2_PIPE_CTR_PID_STALL2       (3U << RUSB2_PIPE_CTR_PID_Pos)    /* Also STALL response */
+
+#define RUSB2_DVSTCTR0_RHST_LS          (1U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Low-speed connection */
+#define RUSB2_DVSTCTR0_RHST_FS          (2U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
+#define RUSB2_DVSTCTR0_RHST_HS          (3U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
+
+#define RUSB2_DEVADD_USBSPD_LS          (1U << RUSB2_DEVADD_USBSPD_Pos)   /* Target Device Low-speed */
+#define RUSB2_DEVADD_USBSPD_FS          (2U << RUSB2_DEVADD_USBSPD_Pos)   /* Target Device Full-speed */
+
+#define RUSB2_CFIFOSEL_ISEL_WRITE       (1U << RUSB2_CFIFOSEL_ISEL_Pos)   /* FIFO write AKA TX*/
+
+#define RUSB2_FIFOSEL_BIGEND            (1U << RUSB2_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
+#define RUSB2_FIFOSEL_MBW_8BIT          (0U << RUSB2_CFIFOSEL_MBW_Pos)    /* 8-bit width */
+#define RUSB2_FIFOSEL_MBW_16BIT         (1U << RUSB2_CFIFOSEL_MBW_Pos)    /* 16-bit width */
+#define RUSB2_FIFOSEL_MBW_32BIT         (2U << RUSB2_CFIFOSEL_MBW_Pos)    /* 32-bit width */
+
+#define RUSB2_INTSTS0_CTSQ_CTRL_RDATA   (1U << RUSB2_INTSTS0_CTSQ_Pos)
+
+#define RUSB2_INTSTS0_DVSQ_STATE_DEF    (1U << RUSB2_INTSTS0_DVSQ_Pos)    /* Default state */
+#define RUSB2_INTSTS0_DVSQ_STATE_ADDR   (2U << RUSB2_INTSTS0_DVSQ_Pos)    /* Address state */
+#define RUSB2_INTSTS0_DVSQ_STATE_SUSP0  (4U << RUSB2_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define RUSB2_INTSTS0_DVSQ_STATE_SUSP1  (5U << RUSB2_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define RUSB2_INTSTS0_DVSQ_STATE_SUSP2  (6U << RUSB2_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define RUSB2_INTSTS0_DVSQ_STATE_SUSP3  (7U << RUSB2_INTSTS0_DVSQ_Pos)    /* Suspend state */
+
+#define RUSB2_PIPECFG_TYPE_BULK         (1U << RUSB2_PIPECFG_TYPE_Pos)
+#define RUSB2_PIPECFG_TYPE_INT          (2U << RUSB2_PIPECFG_TYPE_Pos)
+#define RUSB2_PIPECFG_TYPE_ISO          (3U << RUSB2_PIPECFG_TYPE_Pos)
+
+//--------------------------------------------------------------------+
+// Static Assert
+//--------------------------------------------------------------------+
+
+TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size");
+TU_VERIFY_STATIC(sizeof(rusb2_reg_t) == 1032, "incorrect size");
+
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSCFG     ) == 0x0000, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BUSWAIT    ) == 0x0002, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSSTS0    ) == 0x0004, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PLLSTA     ) == 0x0006, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DVSTCTR0   ) == 0x0008, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, TESTMODE   ) == 0x000C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFO      ) == 0x0014, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFO     ) == 0x0018, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFO     ) == 0x001C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOSEL   ) == 0x0020, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOCTR   ) == 0x0022, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOSEL  ) == 0x0028, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOCTR  ) == 0x002A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOSEL  ) == 0x002C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOCTR  ) == 0x002E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB0    ) == 0x0030, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB1    ) == 0x0032, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYENB    ) == 0x0036, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYENB    ) == 0x0038, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPENB    ) == 0x003A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SOFCFG     ) == 0x003C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSET     ) == 0x003E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS0    ) == 0x0040, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS1    ) == 0x0042, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYSTS    ) == 0x0046, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYSTS    ) == 0x0048, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPSTS    ) == 0x004A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, FRMNUM     ) == 0x004C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UFRMNUM    ) == 0x004E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBADDR    ) == 0x0050, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBREQ     ) == 0x0054, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBVAL     ) == 0x0056, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBINDX    ) == 0x0058, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBLENG    ) == 0x005A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCFG     ) == 0x005C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPMAXP    ) == 0x005E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCTR     ) == 0x0060, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPESEL    ) == 0x0064, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPECFG    ) == 0x0068, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEBUF    ) == 0x006A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEMAXP   ) == 0x006C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEPERI   ) == 0x006E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_CTR   ) == 0x0070, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_TR    ) == 0x0090, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBBCCTRL0 ) == 0x00B0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UCKSEL     ) == 0x00C4, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBMC      ) == 0x00CC, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DEVADD     ) == 0x00D0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSLEW    ) == 0x00F0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPCTRL     ) == 0x0100, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPSTS      ) == 0x0102, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BCCTRL     ) == 0x0140, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL1   ) == 0x0144, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL2   ) == 0x0146, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL1   ) == 0x0148, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL2   ) == 0x014A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM1   ) == 0x0150, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM2   ) == 0x0152, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R    ) == 0x0160, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R    ) == 0x0164, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR2R    ) == 0x0168, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSRCR    ) == 0x016A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R_FS ) == 0x0400, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R_FS ) == 0x0404, "incorrect offset");
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_RUSB2_TYPE_H_ */
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
deleted file mode 100644
index fa87c9f4d..000000000
--- a/src/portable/renesas/usba/dcd_usba.c
+++ /dev/null
@@ -1,915 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Koji Kitayama
- * Portions copyrighted (c) 2021 Roland Winistoerfer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#define USE_SOF     0
-
-#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
-                                 CFG_TUSB_MCU == OPT_MCU_RX65X || \
-                                 CFG_TUSB_MCU == OPT_MCU_RX72N )
-#include "device/dcd.h"
-#include "iodefine.h"
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define SYSTEM_PRCR_PRC1     (1<<1)
-#define SYSTEM_PRCR_PRKEY    (0xA5u<<8)
-
-#define USB_FIFOSEL_TX       ((uint16_t)(1u<<5))
-#define USB_FIFOSEL_BIGEND   ((uint16_t)(1u<<8))
-#define USB_FIFOSEL_MBW_8    ((uint16_t)(0u<<10))
-#define USB_FIFOSEL_MBW_16   ((uint16_t)(1u<<10))
-#define USB_IS0_CTSQ         ((uint16_t)(7u))
-#define USB_IS0_DVSQ         ((uint16_t)(7u<<4))
-#define USB_IS0_VALID        ((uint16_t)(1u<<3))
-#define USB_IS0_BRDY         ((uint16_t)(1u<<8))
-#define USB_IS0_NRDY         ((uint16_t)(1u<<9))
-#define USB_IS0_BEMP         ((uint16_t)(1u<<10))
-#define USB_IS0_CTRT         ((uint16_t)(1u<<11))
-#define USB_IS0_DVST         ((uint16_t)(1u<<12))
-#define USB_IS0_SOFR         ((uint16_t)(1u<<13))
-#define USB_IS0_RESM         ((uint16_t)(1u<<14))
-#define USB_IS0_VBINT        ((uint16_t)(1u<<15))
-#define USB_IS1_SACK         ((uint16_t)(1u<<4))
-#define USB_IS1_SIGN         ((uint16_t)(1u<<5))
-#define USB_IS1_EOFERR       ((uint16_t)(1u<<6))
-#define USB_IS1_ATTCH        ((uint16_t)(1u<<11))
-#define USB_IS1_DTCH         ((uint16_t)(1u<<12))
-#define USB_IS1_BCHG         ((uint16_t)(1u<<14))
-#define USB_IS1_OVRCR        ((uint16_t)(1u<<15))
-
-#define USB_IS0_CTSQ_MSK     (7u)
-#define USB_IS0_CTSQ_SETUP   (1u)
-#define USB_IS0_DVSQ_DEF     (1u<<4)
-#define USB_IS0_DVSQ_ADDR    (2u<<4)
-#define USB_IS0_DVSQ_SUSP0   (4u<<4)
-#define USB_IS0_DVSQ_SUSP1   (5u<<4)
-#define USB_IS0_DVSQ_SUSP2   (6u<<4)
-#define USB_IS0_DVSQ_SUSP3   (7u<<4)
-
-#define USB_PIPECTR_PID_NAK   (0u)
-#define USB_PIPECTR_PID_BUF   (1u)
-#define USB_PIPECTR_PID_STALL (2u)
-#define USB_PIPECTR_CCPL      (1u<<2)
-#define USB_PIPECTR_SQMON     (1u<<6)
-#define USB_PIPECTR_SQCLR     (1u<<8)
-#define USB_PIPECTR_ACLRM     (1u<<9)
-#define USB_PIPECTR_INBUFM    (1u<<14)
-#define USB_PIPECTR_BSTS      (1u<<15)
-
-#define USB_FIFOCTR_DTLN     (0x1FF)
-#define USB_FIFOCTR_FRDY     (1u<<13)
-#define USB_FIFOCTR_BCLR     (1u<<14)
-#define USB_FIFOCTR_BVAL     (1u<<15)
-
-#define USB_PIPECFG_SHTNAK   (1u<<7)
-#define USB_PIPECFG_DBLB     (1u<<9)
-#define USB_PIPECFG_BULK     (1u<<14)
-#define USB_PIPECFG_ISO      (3u<<14)
-#define USB_PIPECFG_INT      (2u<<14)
-
-#define FIFO_REQ_CLR         (1u)
-#define FIFO_COMPLETE        (1u<<1)
-
-// Start of definition of packed structs (used by the CCRX toolchain)
-TU_ATTR_PACKED_BEGIN
-TU_ATTR_BIT_FIELD_ORDER_BEGIN
-
-typedef struct {
-  union {
-    struct {
-      uint16_t      : 8;
-      uint16_t TRCLR: 1;
-      uint16_t TRENB: 1;
-      uint16_t      : 0;
-    };
-    uint16_t TRE;
-  };
-  uint16_t TRN;
-} reg_pipetre_t;
-
-typedef union {
-  struct {
-    volatile uint16_t u8: 8;
-    volatile uint16_t   : 0;
-  };
-  volatile uint16_t u16;
-} hw_fifo_t;
-
-typedef struct TU_ATTR_PACKED
-{
-  void      *buf;      /* the start address of a transfer data buffer */
-  uint16_t  length;    /* the number of bytes in the buffer */
-  uint16_t  remaining; /* the number of bytes remaining in the buffer */
-  struct {
-    uint32_t ep  : 8;  /* an assigned endpoint address */
-    uint32_t ff  : 1;  /* `buf` is TU_FUFO or POD */
-    uint32_t     : 0;
-  };
-} pipe_state_t;
-
-TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
-TU_ATTR_BIT_FIELD_ORDER_END
-
-typedef struct
-{
-  pipe_state_t pipe[10];
-  uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
-} dcd_data_t;
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-static dcd_data_t _dcd;
-
-static uint32_t disable_interrupt(void)
-{
-  uint32_t pswi;
-#if defined(__CCRX__)
-  pswi = get_psw() & 0x010000;
-  clrpsw_i();
-#else
-  pswi = __builtin_rx_mvfc(0) & 0x010000;
-  __builtin_rx_clrpsw('I');
-#endif
-  return pswi;
-}
-
-static void enable_interrupt(uint32_t pswi)
-{
-#if defined(__CCRX__)
-  set_psw(get_psw() | pswi);
-#else
-  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
-#endif
-}
-
-static unsigned find_pipe(unsigned xfer)
-{
-  switch (xfer) {
-  case TUSB_XFER_ISOCHRONOUS:
-    for (int i = 1; i <= 2; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_BULK:
-    for (int i = 3; i <= 5; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    for (int i = 1; i <= 1; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_INTERRUPT:
-    for (int i = 6; i <= 9; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    break;
-  default:
-    /* No support for control transfer */
-    break;
-  }
-  return 0;
-}
-
-static volatile uint16_t* get_pipectr(unsigned num)
-{
-  volatile uint16_t *ctr = NULL;
-  if (num) {
-    ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-    ctr += num - 1;
-  } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
-  }
-  return ctr;
-}
-
-static volatile reg_pipetre_t* get_pipetre(unsigned num)
-{
-  volatile reg_pipetre_t* tre = NULL;
-  if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
-    tre += num - 1;
-  }
-  return tre;
-}
-
-static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
-{
-  (void)rhport;
-  volatile uint16_t *ctr = NULL;
-  const unsigned epn   = tu_edpt_number(ep_addr);
-  if (epn) {
-    const unsigned dir = tu_edpt_dir(ep_addr);
-    const unsigned num = _dcd.ep[dir][epn];
-    if (num) {
-      ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-      ctr += num - 1;
-    }
-  } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
-  }
-  return ctr;
-}
-
-static unsigned edpt0_max_packet_size(void)
-{
-  return USB0.DCPMAXP.BIT.MXPS;
-}
-
-static unsigned edpt_max_packet_size(unsigned num)
-{
-  USB0.PIPESEL.WORD = num;
-  return USB0.PIPEMAXP.WORD;
-}
-
-static inline void pipe_wait_for_ready(unsigned num)
-{
-  while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
-  while (!USB0.D0FIFOCTR.BIT.FRDY) ;
-}
-
-static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
-{
-  volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo;
-  uintptr_t addr = (uintptr_t)buf;
-  while (len >= 2) {
-    reg->u16 = *(const uint16_t *)addr;
-    addr += 2;
-    len  -= 2;
-  }
-  if (len) {
-    reg->u8 = *(const uint8_t *)addr;
-    ++addr;
-  }
-}
-
-static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
-{
-  uint8_t *p   = (uint8_t*)buf;
-  volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
-  while (len--) *p++ = *reg;
-}
-
-static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir)
-{
-  static const struct {
-    void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
-    void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n);
-    void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len);
-  } ops[] = {
-    /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
-    /* IN  */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
-  };
-  tu_fifo_buffer_info_t info;
-  ops[dir].tu_fifo_get_info(f, &info);
-  unsigned total_len = len;
-  len = TU_MIN(total_len, info.len_lin);
-  ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
-  unsigned rem = total_len - len;
-  if (rem) {
-    len = TU_MIN(rem, info.len_wrap);
-    ops[dir].pipe_read_write(info.ptr_wrap, fifo, len);
-    rem -= len;
-  }
-  ops[dir].tu_fifo_advance(f, total_len - rem);
-}
-
-static bool pipe0_xfer_in(void)
-{
-  pipe_state_t *pipe = &_dcd.pipe[0];
-  const unsigned rem = pipe->remaining;
-  if (!rem) {
-    pipe->buf = NULL;
-    return true;
-  }
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned len = TU_MIN(mps, rem);
-  void          *buf = pipe->buf;
-  if (len) {
-    if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_IN);
-    } else {
-      pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
-      pipe->buf = (uint8_t*)buf + len;
-    }
-  }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
-  pipe->remaining = rem - len;
-  return false;
-}
-
-static bool pipe0_xfer_out(void)
-{
-  pipe_state_t *pipe = &_dcd.pipe[0];
-  const unsigned rem = pipe->remaining;
-
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
-  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
-  void          *buf = pipe->buf;
-  if (len) {
-    if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_OUT);
-    } else {
-      pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
-      pipe->buf = (uint8_t*)buf + len;
-    }
-  }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  pipe->remaining = rem - len;
-  if ((len < mps) || (rem == len)) {
-    pipe->buf = NULL;
-    return true;
-  }
-  return false;
-}
-
-static bool pipe_xfer_in(unsigned num)
-{
-  pipe_state_t  *pipe = &_dcd.pipe[num];
-  const unsigned rem  = pipe->remaining;
-
-  if (!rem) {
-    pipe->buf = NULL;
-    return true;
-  }
-
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned len  = TU_MIN(rem, mps);
-  void          *buf  = pipe->buf;
-  if (len) {
-    if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_IN);
-    } else {
-      pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
-      pipe->buf = (uint8_t*)buf + len;
-    }
-  }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  pipe->remaining = rem - len;
-  return false;
-}
-
-static bool pipe_xfer_out(unsigned num)
-{
-  pipe_state_t  *pipe = &_dcd.pipe[num];
-  const unsigned rem  = pipe->remaining;
-
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned vld  = USB0.D0FIFOCTR.BIT.DTLN;
-  const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
-  void          *buf  = pipe->buf;
-  if (len) {
-    if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_OUT);
-    } else {
-      pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
-      pipe->buf = (uint8_t*)buf + len;
-    }
-  }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  pipe->remaining     = rem - len;
-  if ((len < mps) || (rem == len)) {
-    pipe->buf = NULL;
-    return NULL != buf;
-  }
-  return false;
-}
-
-static void process_setup_packet(uint8_t rhport)
-{
-  uint16_t setup_packet[4];
-  if (0 == (USB0.INTSTS0.WORD & USB_IS0_VALID)) return;
-  USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  setup_packet[0] = tu_le16toh(USB0.USBREQ.WORD);
-  setup_packet[1] = USB0.USBVAL;
-  setup_packet[2] = USB0.USBINDX;
-  setup_packet[3] = USB0.USBLENG;
-  USB0.INTSTS0.WORD = ~USB_IS0_VALID;
-  dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
-}
-
-static void process_status_completion(uint8_t rhport)
-{
-  uint8_t ep_addr;
-  /* Check the data stage direction */
-  if (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) {
-    /* IN transfer. */
-    ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
-  } else {
-    /* OUT transfer. */
-    ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT);
-  }
-  dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true);
-}
-
-static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
-{
-  /* configure fifo direction and access unit settings */
-  if (ep_addr) { /* IN, 2 bytes */
-    USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-    while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
-  } else {       /* OUT, a byte */
-    USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
-    while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
-  }
-
-  pipe_state_t *pipe = &_dcd.pipe[0];
-  pipe->ff        = buffer_type;
-  pipe->length    = total_bytes;
-  pipe->remaining = total_bytes;
-  if (total_bytes) {
-    pipe->buf     = buffer;
-    if (ep_addr) { /* IN */
-      TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
-      pipe0_xfer_in();
-    }
-    USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
-  } else {
-    /* ZLP */
-    pipe->buf        = NULL;
-    USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
-  }
-  return true;
-}
-
-static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
-{
-  const unsigned epn = tu_edpt_number(ep_addr);
-  const unsigned dir = tu_edpt_dir(ep_addr);
-  const unsigned num = _dcd.ep[dir][epn];
-
-  TU_ASSERT(num);
-
-  pipe_state_t *pipe  = &_dcd.pipe[num];
-  pipe->ff        = buffer_type;
-  pipe->buf       = buffer;
-  pipe->length    = total_bytes;
-  pipe->remaining = total_bytes;
-  if (dir) { /* IN */
-    if (total_bytes) {
-      pipe_xfer_in(num);
-    } else { /* ZLP */
-      USB0.D0FIFOSEL.WORD = num;
-      pipe_wait_for_ready(num);
-      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-      USB0.D0FIFOSEL.WORD = 0;
-      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-    }
-  } else {
-#if defined(__CCRX__)
-    __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num);
-#else
-    volatile reg_pipetre_t *pt = get_pipetre(num);
-#endif
-    if (pt) {
-      const unsigned     mps = edpt_max_packet_size(num);
-      volatile uint16_t *ctr = get_pipectr(num);
-      if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
-      pt->TRE   = TU_BIT(8);
-      pt->TRN   = (total_bytes + mps - 1) / mps;
-      pt->TRENB = 1;
-      *ctr = USB_PIPECTR_PID_BUF;
-    }
-  }
-  //  TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
-  return true;
-}
-
-static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
-{
-  const unsigned epn = tu_edpt_number(ep_addr);
-  if (0 == epn) {
-    return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes);
-  } else {
-    return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes);
-  }
-}
-
-static void process_pipe0_bemp(uint8_t rhport)
-{
-  bool completed = pipe0_xfer_in();
-  if (completed) {
-    pipe_state_t *pipe = &_dcd.pipe[0];
-    dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
-                            pipe->length, XFER_RESULT_SUCCESS, true);
-  }
-}
-
-static void process_pipe_brdy(uint8_t rhport, unsigned num)
-{
-  pipe_state_t  *pipe = &_dcd.pipe[num];
-  const unsigned dir  = tu_edpt_dir(pipe->ep);
-  bool completed;
-
-  if (dir) { /* IN */
-    completed = pipe_xfer_in(num);
-  } else {
-    if (num) {
-      completed = pipe_xfer_out(num);
-    } else {
-      completed = pipe0_xfer_out();
-    }
-  }
-  if (completed) {
-    dcd_event_xfer_complete(rhport, pipe->ep,
-                            pipe->length - pipe->remaining,
-                            XFER_RESULT_SUCCESS, true);
-    //  TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining);
-  }
-}
-
-static void process_bus_reset(uint8_t rhport)
-{
-  USB0.BEMPENB.WORD   = 1;
-  USB0.BRDYENB.WORD   = 1;
-  USB0.CFIFOCTR.WORD  = USB_FIFOCTR_BCLR;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  USB0.D1FIFOSEL.WORD = 0;
-  while (USB0.D1FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1CTR.WORD));
-  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1TRE.WORD));
-  for (int i = 1; i <= 5; ++i) {
-    USB0.PIPESEL.WORD  = i;
-    USB0.PIPECFG.WORD  = 0;
-    *ctr = USB_PIPECTR_ACLRM;
-    *ctr = 0;
-    ++ctr;
-    *tre = TU_BIT(8);
-    tre += 2;
-  }
-  for (int i = 6; i <= 9; ++i) {
-    USB0.PIPESEL.WORD  = i;
-    USB0.PIPECFG.WORD  = 0;
-    *ctr = USB_PIPECTR_ACLRM;
-    *ctr = 0;
-    ++ctr;
-  }
-  tu_varclr(&_dcd);
-  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
-}
-
-static void process_set_address(uint8_t rhport)
-{
-  const uint32_t addr = USB0.USBADDR.BIT.USBADDR;
-  if (!addr) return;
-  const tusb_control_request_t setup_packet = {
-#if defined(__CCRX__)
-      .bmRequestType = { 0 },  /* Note: CCRX needs the braces over this struct member */
-#else
-      .bmRequestType = 0,
-#endif
-      .bRequest      = TUSB_REQ_SET_ADDRESS,
-      .wValue        = addr,
-      .wIndex        = 0,
-      .wLength       = 0,
-    };
-  dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true);
-}
-
-/*------------------------------------------------------------------*/
-/* Device API
- *------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
-  (void)rhport;
-  /* Enable USB0 */
-  uint32_t pswi = disable_interrupt();
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(USB0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  enable_interrupt(pswi);
-  USB0.SYSCFG.BIT.SCKE = 1;
-  while (!USB0.SYSCFG.BIT.SCKE) ;
-  USB0.SYSCFG.BIT.DRPD = 0;
-  USB0.SYSCFG.BIT.DCFM = 0;
-  USB0.SYSCFG.BIT.USBE = 1;
-
-  USB.DPUSR0R.BIT.FIXPHY0 = 0u;    /* USB0 Transceiver Output fixed */
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  USB0.PHYSLEW.LONG = 0x5;
-  IR(PERIB, INTB185) = 0;
-#else
-  IR(USB0, USBI0)   = 0;
-#endif
-
-  /* Setup default control pipe */
-  USB0.DCPMAXP.BIT.MXPS  = 64;
-  USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP |
-    USB_IS0_DVST | USB_IS0_CTRT | (USE_SOF ? USB_IS0_SOFR: 0) | USB_IS0_RESM;
-  USB0.BEMPENB.WORD = 1;
-  USB0.BRDYENB.WORD = 1;
-
-  if (USB0.INTSTS0.BIT.VBSTS) {
-    dcd_connect(rhport);
-  }
-}
-
-void dcd_int_enable(uint8_t rhport)
-{
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 1;
-#else
-  IEN(USB0, USBI0) = 1;
-#endif
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 0;
-#else
-  IEN(USB0, USBI0) = 0;
-#endif
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void)rhport;
-  (void)dev_addr;
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void)rhport;
-  USB0.DVSTCTR0.BIT.WKUP = 1;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  (void)rhport;
-  USB0.SYSCFG.BIT.DPRPU = 1;
-}
-
-void dcd_disconnect(uint8_t rhport)
-{
-  (void)rhport;
-  USB0.SYSCFG.BIT.DPRPU = 0;
-}
-
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
-  (void) rhport;
-  (void) en;
-
-  // TODO implement later
-}
-
-//--------------------------------------------------------------------+
-// Endpoint API
-//--------------------------------------------------------------------+
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
-{
-  (void)rhport;
-
-  const unsigned ep_addr = ep_desc->bEndpointAddress;
-  const unsigned epn     = tu_edpt_number(ep_addr);
-  const unsigned dir     = tu_edpt_dir(ep_addr);
-  const unsigned xfer    = ep_desc->bmAttributes.xfer;
-
-  const unsigned mps = tu_edpt_packet_size(ep_desc);
-  if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
-    /* USBa supports up to 256 bytes */
-    return false;
-  }
-
-  const unsigned num = find_pipe(xfer);
-  if (!num) return false;
-  _dcd.pipe[num].ep = ep_addr;
-  _dcd.ep[dir][epn] = num;
-
-  /* setup pipe */
-  dcd_int_disable(rhport);
-  USB0.PIPESEL.WORD  = num;
-  USB0.PIPEMAXP.WORD = mps;
-  volatile uint16_t *ctr = get_pipectr(num);
-  *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
-  *ctr = 0;
-  unsigned cfg = (dir << 4) | epn;
-  if (xfer == TUSB_XFER_BULK) {
-    cfg |= (USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB);
-  } else if (xfer == TUSB_XFER_INTERRUPT) {
-    cfg |= USB_PIPECFG_INT;
-  } else {
-    cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB);
-  }
-  USB0.PIPECFG.WORD  = cfg;
-  USB0.BRDYSTS.WORD  = 0x1FFu ^ TU_BIT(num);
-  USB0.BRDYENB.WORD |= TU_BIT(num);
-  if (dir || (xfer != TUSB_XFER_BULK)) {
-    *ctr = USB_PIPECTR_PID_BUF;
-  }
-  // TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD);
-  dcd_int_enable(rhport);
-
-  return true;
-}
-
-void dcd_edpt_close_all(uint8_t rhport)
-{
-  unsigned i = TU_ARRAY_SIZE(_dcd.pipe);
-  dcd_int_disable(rhport);
-  while (--i) { /* Close all pipes except 0 */
-    const unsigned ep_addr = _dcd.pipe[i].ep;
-    if (!ep_addr) continue;
-    dcd_edpt_close(rhport, ep_addr);
-  }
-  dcd_int_enable(rhport);
-}
-
-void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
-{
-  (void)rhport;
-  const unsigned epn = tu_edpt_number(ep_addr);
-  const unsigned dir = tu_edpt_dir(ep_addr);
-  const unsigned num = _dcd.ep[dir][epn];
-
-  USB0.BRDYENB.WORD &= ~TU_BIT(num);
-  volatile uint16_t *ctr = get_pipectr(num);
-  *ctr = 0;
-  USB0.PIPESEL.WORD = num;
-  USB0.PIPECFG.WORD = 0;
-  _dcd.pipe[num].ep = 0;
-  _dcd.ep[dir][epn] = 0;
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
-{
-  bool r;
-  dcd_int_disable(rhport);
-  r = process_edpt_xfer(0, ep_addr, buffer, total_bytes);
-  dcd_int_enable(rhport);
-  return r;
-}
-
-bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
-  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
-  TU_ASSERT(ff->item_size == 1);
-  bool r;
-  dcd_int_disable(rhport);
-  r = process_edpt_xfer(1, ep_addr, ff, total_bytes);
-  dcd_int_enable(rhport);
-  return r;
-}
-
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
-  if (!ctr) return;
-  dcd_int_disable(rhport);
-  const uint32_t pid = *ctr & 0x3;
-  *ctr = pid | USB_PIPECTR_PID_STALL;
-  *ctr = USB_PIPECTR_PID_STALL;
-  dcd_int_enable(rhport);
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
-  if (!ctr) return;
-  dcd_int_disable(rhport);
-  *ctr = USB_PIPECTR_SQCLR;
-
-  if (tu_edpt_dir(ep_addr)) { /* IN */
-    *ctr = USB_PIPECTR_PID_BUF;
-  } else {
-    const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
-    USB0.PIPESEL.WORD  = num;
-    if (USB0.PIPECFG.BIT.TYPE != 1) {
-      *ctr = USB_PIPECTR_PID_BUF;
-    }
-  }
-  dcd_int_enable(rhport);
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-void dcd_int_handler(uint8_t rhport)
-{
-  (void)rhport;
-
-  unsigned is0 = USB0.INTSTS0.WORD;
-  /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  USB0.INTSTS0.WORD = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID;
-  if (is0 & USB_IS0_VBINT) {
-    if (USB0.INTSTS0.BIT.VBSTS) {
-      dcd_connect(rhport);
-    } else {
-      dcd_disconnect(rhport);
-    }
-  }
-  if (is0 & USB_IS0_RESM) {
-    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-#if (0==USE_SOF)
-    USB0.INTENB0.BIT.SOFE = 0;
-#endif
-  }
-  if ((is0 & USB_IS0_SOFR) && USB0.INTENB0.BIT.SOFE) {
-    // USBD will exit suspended mode when SOF event is received
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-#if (0==USE_SOF)
-    USB0.INTENB0.BIT.SOFE = 0;
-#endif
-  }
-  if (is0 & USB_IS0_DVST) {
-    switch (is0 & USB_IS0_DVSQ) {
-    case USB_IS0_DVSQ_DEF:
-      process_bus_reset(rhport);
-      break;
-    case USB_IS0_DVSQ_ADDR:
-      process_set_address(rhport);
-      break;
-    case USB_IS0_DVSQ_SUSP0:
-    case USB_IS0_DVSQ_SUSP1:
-    case USB_IS0_DVSQ_SUSP2:
-    case USB_IS0_DVSQ_SUSP3:
-       dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-#if (0==USE_SOF)
-       USB0.INTENB0.BIT.SOFE = 1;
-#endif
-    default:
-      break;
-    }
-  }
-  if (is0 & USB_IS0_CTRT) {
-    if (is0 & USB_IS0_CTSQ_SETUP) {
-      /* A setup packet has been received. */
-      process_setup_packet(rhport);
-    } else if (0 == (is0 & USB_IS0_CTSQ_MSK)) {
-      /* A ZLP has been sent/received. */
-      process_status_completion(rhport);
-    }
-  }
-  if (is0 & USB_IS0_BEMP) {
-    const unsigned s = USB0.BEMPSTS.WORD;
-    USB0.BEMPSTS.WORD = 0;
-    if (s & 1) {
-      process_pipe0_bemp(rhport);
-    }
-  }
-  if (is0 & USB_IS0_BRDY) {
-    const unsigned m = USB0.BRDYENB.WORD;
-    unsigned s       = USB0.BRDYSTS.WORD & m;
-    /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    USB0.BRDYSTS.WORD = ~s;
-    while (s) {
-#if defined(__CCRX__)
-      static const int Mod37BitPosition[] = {
-        -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4,
-        7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
-        20, 8, 19, 18
-      };
-
-      const unsigned num = Mod37BitPosition[(-s & s) % 37];
-#else
-      const unsigned num = __builtin_ctz(s);
-#endif
-      process_pipe_brdy(rhport, num);
-      s &= ~TU_BIT(num);
-    }
-  }
-}
-
-#endif
diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/usba/hcd_usba.c
deleted file mode 100644
index 5246ecb94..000000000
--- a/src/portable/renesas/usba/hcd_usba.c
+++ /dev/null
@@ -1,875 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021 Koji Kitayama
- * Portions copyrighted (c) 2021 Roland Winistoerfer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
-                               CFG_TUSB_MCU == OPT_MCU_RX65X || \
-                               CFG_TUSB_MCU == OPT_MCU_RX72N )
-#include "host/hcd.h"
-#include "iodefine.h"
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define SYSTEM_PRCR_PRC1     (1<<1)
-#define SYSTEM_PRCR_PRKEY    (0xA5u<<8)
-
-#define USB_DVSTCTR0_LOW     (1u)
-#define USB_DVSTCTR0_FULL    (2u)
-
-#define USB_FIFOSEL_TX       ((uint16_t)(1u<<5))
-#define USB_FIFOSEL_BIGEND   ((uint16_t)(1u<<8))
-#define USB_FIFOSEL_MBW_8    ((uint16_t)(0u<<10))
-#define USB_FIFOSEL_MBW_16   ((uint16_t)(1u<<10))
-#define USB_IS0_CTSQ         ((uint16_t)(7u))
-#define USB_IS0_DVSQ         ((uint16_t)(7u<<4))
-#define USB_IS0_VALID        ((uint16_t)(1u<<3))
-#define USB_IS0_BRDY         ((uint16_t)(1u<<8))
-#define USB_IS0_NRDY         ((uint16_t)(1u<<9))
-#define USB_IS0_BEMP         ((uint16_t)(1u<<10))
-#define USB_IS0_CTRT         ((uint16_t)(1u<<11))
-#define USB_IS0_DVST         ((uint16_t)(1u<<12))
-#define USB_IS0_SOFR         ((uint16_t)(1u<<13))
-#define USB_IS0_RESM         ((uint16_t)(1u<<14))
-#define USB_IS0_VBINT        ((uint16_t)(1u<<15))
-#define USB_IS1_SACK         ((uint16_t)(1u<<4))
-#define USB_IS1_SIGN         ((uint16_t)(1u<<5))
-#define USB_IS1_EOFERR       ((uint16_t)(1u<<6))
-#define USB_IS1_ATTCH        ((uint16_t)(1u<<11))
-#define USB_IS1_DTCH         ((uint16_t)(1u<<12))
-#define USB_IS1_BCHG         ((uint16_t)(1u<<14))
-#define USB_IS1_OVRCR        ((uint16_t)(1u<<15))
-
-#define USB_IS0_CTSQ_MSK     (7u)
-#define USB_IS0_CTSQ_SETUP   (1u)
-#define USB_IS0_DVSQ_DEF     (1u<<4)
-#define USB_IS0_DVSQ_ADDR    (2u<<4)
-#define USB_IS0_DVSQ_SUSP0   (4u<<4)
-#define USB_IS0_DVSQ_SUSP1   (5u<<4)
-#define USB_IS0_DVSQ_SUSP2   (6u<<4)
-#define USB_IS0_DVSQ_SUSP3   (7u<<4)
-
-#define USB_PIPECTR_PID_MSK   (3u)
-#define USB_PIPECTR_PID_NAK   (0u)
-#define USB_PIPECTR_PID_BUF   (1u)
-#define USB_PIPECTR_PID_STALL (2u)
-#define USB_PIPECTR_CCPL      (1u<<2)
-#define USB_PIPECTR_SQMON     (1u<<6)
-#define USB_PIPECTR_SQCLR     (1u<<8)
-#define USB_PIPECTR_ACLRM     (1u<<9)
-#define USB_PIPECTR_INBUFM    (1u<<14)
-#define USB_PIPECTR_BSTS      (1u<<15)
-
-#define USB_FIFOCTR_DTLN     (0x1FF)
-#define USB_FIFOCTR_FRDY     (1u<<13)
-#define USB_FIFOCTR_BCLR     (1u<<14)
-#define USB_FIFOCTR_BVAL     (1u<<15)
-
-#define USB_PIPECFG_SHTNAK   (1u<<7)
-#define USB_PIPECFG_DBLB     (1u<<9)
-#define USB_PIPECFG_BULK     (1u<<14)
-#define USB_PIPECFG_ISO      (3u<<14)
-#define USB_PIPECFG_INT      (2u<<14)
-
-#define USB_DEVADD_LOW       (1u<<6)
-#define USB_DEVADD_FULL      (2u<<6)
-
-#define FIFO_REQ_CLR         (1u)
-#define FIFO_COMPLETE        (1u<<1)
-
-// Start of definition of packed structs (used by the CCRX toolchain)
-TU_ATTR_PACKED_BEGIN
-TU_ATTR_BIT_FIELD_ORDER_BEGIN
-
-typedef struct {
-  union {
-    struct {
-      uint16_t      : 8;
-      uint16_t TRCLR: 1;
-      uint16_t TRENB: 1;
-      uint16_t      : 0;
-    };
-    uint16_t TRE;
-  };
-  uint16_t TRN;
-} reg_pipetre_t;
-
-typedef union {
-  struct {
-    volatile uint16_t u8: 8;
-    volatile uint16_t   : 0;
-  };
-  volatile uint16_t u16;
-} hw_fifo_t;
-
-typedef struct TU_ATTR_PACKED
-{
-  void      *buf;      /* the start address of a transfer data buffer */
-  uint16_t  length;    /* the number of bytes in the buffer */
-  uint16_t  remaining; /* the number of bytes remaining in the buffer */
-  struct {
-    uint32_t ep  : 8;  /* an assigned endpoint address */
-    uint32_t dev : 8;  /* an assigned device address */
-    uint32_t ff  : 1;  /* `buf` is TU_FUFO or POD */
-    uint32_t     : 0;
-  };
-} pipe_state_t;
-
-TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
-TU_ATTR_BIT_FIELD_ORDER_END
-
-typedef struct
-{
-  bool         need_reset; /* The device has not been reset after connection. */
-  pipe_state_t pipe[10];
-  uint8_t ep[4][2][15];   /* a lookup table for a pipe index from an endpoint address */
-  uint8_t      ctl_mps[5]; /* EP0 max packet size for each device */
-} hcd_data_t;
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-static hcd_data_t _hcd;
-
-static uint32_t disable_interrupt(void)
-{
-  uint32_t pswi;
-#if defined(__CCRX__)
-  pswi = get_psw() & 0x010000;
-  clrpsw_i();
-#else
-  pswi = __builtin_rx_mvfc(0) & 0x010000;
-  __builtin_rx_clrpsw('I');
-#endif
-  return pswi;
-}
-
-static void enable_interrupt(uint32_t pswi)
-{
-#if defined(__CCRX__)
-  set_psw(get_psw() | pswi);
-#else
-  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
-#endif
-}
-
-static unsigned find_pipe(unsigned xfer)
-{
-  switch (xfer) {
-  case TUSB_XFER_ISOCHRONOUS:
-    for (int i = 1; i <= 2; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_BULK:
-    for (int i = 3; i <= 5; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    for (int i = 1; i <= 1; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_INTERRUPT:
-    for (int i = 6; i <= 9; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    break;
-  default:
-    /* No support for control transfer */
-    break;
-  }
-  return 0;
-}
-
-static volatile uint16_t* get_pipectr(unsigned num)
-{
-  volatile uint16_t *ctr = NULL;
-  if (num) {
-    ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-    ctr += num - 1;
-  } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
-  }
-  return ctr;
-}
-
-static volatile reg_pipetre_t* get_pipetre(unsigned num)
-{
-  volatile reg_pipetre_t* tre = NULL;
-  if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
-    tre += num - 1;
-  }
-  return tre;
-}
-
-static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr)
-{
-  volatile uint16_t *ctr = NULL;
-  const unsigned epn   = tu_edpt_number(ep_addr);
-  if (epn) {
-    const unsigned dir_in = tu_edpt_dir(ep_addr);
-    const unsigned num    = _hcd.ep[dev_addr][dir_in][epn - 1];
-    if (num) {
-      ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-      ctr += num - 1;
-    }
-  } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
-  }
-  return ctr;
-}
-
-static unsigned edpt0_max_packet_size(void)
-{
-  return USB0.DCPMAXP.BIT.MXPS;
-}
-
-static unsigned edpt_max_packet_size(unsigned num)
-{
-  USB0.PIPESEL.WORD = num;
-  return USB0.PIPEMAXP.BIT.MXPS;
-}
-
-static inline void pipe_wait_for_ready(unsigned num)
-{
-  while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
-  while (!USB0.D0FIFOCTR.BIT.FRDY) ;
-}
-
-static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
-{
-  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
-  uintptr_t addr = (uintptr_t)buf;
-  while (len >= 2) {
-    reg->u16 = *(const uint16_t *)addr;
-    addr += 2;
-    len  -= 2;
-  }
-  if (len) {
-    reg->u8 = *(const uint8_t *)addr;
-    ++addr;
-  }
-}
-
-static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
-{
-  uint8_t *p   = (uint8_t*)buf;
-  volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
-  while (len--) *p++ = *reg;
-}
-
-static bool pipe0_xfer_in(void)
-{
-  pipe_state_t *pipe = &_hcd.pipe[0];
-  const unsigned rem = pipe->remaining;
-
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
-  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
-  void          *buf = pipe->buf;
-  if (len) {
-    USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
-    pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
-    pipe->buf = (uint8_t*)buf + len;
-  }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  pipe->remaining = rem - len;
-  if ((len < mps) || (rem == len)) {
-    pipe->buf = NULL;
-    return true;
-  }
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
-  return false;
-}
-
-static bool pipe0_xfer_out(void)
-{
-  pipe_state_t *pipe = &_hcd.pipe[0];
-  const unsigned rem = pipe->remaining;
-  if (!rem) {
-    pipe->buf = NULL;
-    return true;
-  }
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned len = TU_MIN(mps, rem);
-  void          *buf = pipe->buf;
-  if (len) {
-    pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
-    pipe->buf = (uint8_t*)buf + len;
-  }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
-  pipe->remaining = rem - len;
-  return false;
-}
-
-static bool pipe_xfer_in(unsigned num)
-{
-  pipe_state_t  *pipe = &_hcd.pipe[num];
-  const unsigned rem  = pipe->remaining;
-
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned vld  = USB0.D0FIFOCTR.BIT.DTLN;
-  const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
-  void          *buf  = pipe->buf;
-  if (len) {
-    pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
-    pipe->buf = (uint8_t*)buf + len;
-  }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  pipe->remaining     = rem - len;
-  if ((len < mps) || (rem == len)) {
-    pipe->buf = NULL;
-    return NULL != buf;
-  }
-  return false;
-}
-
-static bool pipe_xfer_out(unsigned num)
-{
-  pipe_state_t  *pipe = &_hcd.pipe[num];
-  const unsigned rem  = pipe->remaining;
-
-  if (!rem) {
-    pipe->buf = NULL;
-    return true;
-  }
-
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned len  = TU_MIN(rem, mps);
-  void          *buf  = pipe->buf;
-  if (len) {
-    pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
-    pipe->buf = (uint8_t*)buf + len;
-  }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  pipe->remaining = rem - len;
-  return false;
-}
-
-static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
-{
-  (void)dev_addr;
-  const unsigned dir_in = tu_edpt_dir(ep_addr);
-
-  /* configure fifo direction and access unit settings */
-  if (dir_in) { /* IN, a byte */
-    USB0.CFIFOSEL.WORD  = USB_FIFOSEL_MBW_8;
-    while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
-  } else {       /* OUT, 2 bytes */
-    USB0.CFIFOSEL.WORD  = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-    while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
-  }
-
-  pipe_state_t *pipe = &_hcd.pipe[0];
-  pipe->ep        = ep_addr;
-  pipe->length    = buflen;
-  pipe->remaining = buflen;
-  if (buflen) {
-    pipe->buf     = buffer;
-    if (!dir_in) { /* OUT */
-      TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
-      pipe0_xfer_out();
-    }
-  } else { /* ZLP */
-    pipe->buf        = NULL;
-    if (!dir_in) { /* OUT */
-      USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
-    }
-    if (dir_in == USB0.DCPCFG.BIT.DIR) {
-      TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID);
-      USB0.DCPCTR.BIT.SQSET = 1;
-      USB0.DCPCFG.BIT.DIR = dir_in ^ 1;
-    }
-  }
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
-  return true;
-}
-
-static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
-{
-  const unsigned epn    = tu_edpt_number(ep_addr);
-  const unsigned dir_in = tu_edpt_dir(ep_addr);
-  const unsigned num    = _hcd.ep[dev_addr - 1][dir_in][epn - 1];
-
-  TU_ASSERT(num);
-
-  pipe_state_t *pipe  = &_hcd.pipe[num];
-  pipe->buf       = buffer;
-  pipe->length    = buflen;
-  pipe->remaining = buflen;
-  if (!dir_in) { /* OUT */
-    if (buflen) {
-      pipe_xfer_out(num);
-    } else { /* ZLP */
-      USB0.D0FIFOSEL.WORD = num;
-      pipe_wait_for_ready(num);
-      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-      USB0.D0FIFOSEL.WORD = 0;
-      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-    }
-  } else {
-    volatile uint16_t     *ctr = get_pipectr(num);
-    volatile reg_pipetre_t *pt = get_pipetre(num);
-    if (pt) {
-      const unsigned     mps = edpt_max_packet_size(num);
-      if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
-      pt->TRE   = TU_BIT(8);
-      pt->TRN   = (buflen + mps - 1) / mps;
-      pt->TRENB = 1;
-    }
-    *ctr = USB_PIPECTR_PID_BUF;
-  }
-  return true;
-}
-
-static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
-{
-  const unsigned epn = tu_edpt_number(ep_addr);
-  if (0 == epn) {
-    return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen);
-  } else {
-    return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen);
-  }
-}
-
-static void process_pipe0_bemp(uint8_t rhport)
-{
-  (void)rhport;
-  bool completed = pipe0_xfer_out();
-  if (completed) {
-    pipe_state_t *pipe = &_hcd.pipe[0];
-    hcd_event_xfer_complete(pipe->dev,
-                            tu_edpt_addr(0, TUSB_DIR_OUT),
-                            pipe->length - pipe->remaining,
-                            XFER_RESULT_SUCCESS, true);
-  }
-}
-
-static void process_pipe_nrdy(uint8_t rhport, unsigned num)
-{
-  (void)rhport;
-  unsigned result;
-  uint16_t volatile *ctr = get_pipectr(num);
-  // TU_LOG1("NRDY %d %x\n", num, *ctr);
-  switch (*ctr & USB_PIPECTR_PID_MSK) {
-    default: return;
-    case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break;
-    case USB_PIPECTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
-  }
-  pipe_state_t *pipe = &_hcd.pipe[num];
-  hcd_event_xfer_complete(pipe->dev, pipe->ep,
-                          pipe->length - pipe->remaining,
-                          result, true);
-}
-
-static void process_pipe_brdy(uint8_t rhport, unsigned num)
-{
-  (void)rhport;
-  pipe_state_t  *pipe   = &_hcd.pipe[num];
-  const unsigned dir_in = tu_edpt_dir(pipe->ep);
-  bool completed;
-
-  if (dir_in) { /* IN */
-    if (num) {
-      completed = pipe_xfer_in(num);
-    } else {
-      completed = pipe0_xfer_in();
-    }
-  } else {
-    completed = pipe_xfer_out(num);
-  }
-  if (completed) {
-    hcd_event_xfer_complete(pipe->dev, pipe->ep,
-                            pipe->length - pipe->remaining,
-                            XFER_RESULT_SUCCESS, true);
-    //  TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining);
-  }
-}
-
-
-/*------------------------------------------------------------------*/
-/* Host API
- *------------------------------------------------------------------*/
-bool hcd_init(uint8_t rhport)
-{
-  (void)rhport;
-  /* Enable USB0 */
-  uint32_t pswi = disable_interrupt();
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(USB0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  enable_interrupt(pswi);
-  USB0.SYSCFG.BIT.SCKE = 1;
-  while (!USB0.SYSCFG.BIT.SCKE) ;
-  USB0.SYSCFG.BIT.DPRPU = 0;
-  USB0.SYSCFG.BIT.DRPD = 0;
-  USB0.SYSCFG.BIT.DCFM = 1;
-
-  USB0.DVSTCTR0.BIT.VBUSEN = 1;
-
-  USB0.SYSCFG.BIT.DRPD = 1;
-  for (volatile int i = 0; i < 30000; ++i) ;
-  USB0.SYSCFG.BIT.USBE = 1;
-
-  USB.DPUSR0R.BIT.FIXPHY0 = 0u;    /* USB0 Transceiver Output fixed */
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  USB0.PHYSLEW.LONG = 0x5;
-  IR(PERIB, INTB185) = 0;
-#else
-  IR(USB0, USBI0)   = 0;
-#endif
-
-  /* Setup default control pipe */
-  USB0.DCPCFG.WORD  = USB_PIPECFG_SHTNAK;
-  USB0.DCPMAXP.WORD = 64;
-  USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP;
-  USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN |
-    USB_IS1_ATTCH | USB_IS1_DTCH;
-  USB0.BEMPENB.WORD = 1;
-  USB0.NRDYENB.WORD = 1;
-  USB0.BRDYENB.WORD = 1;
-  return true;
-}
-
-void hcd_int_enable(uint8_t rhport)
-{
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 1;
-#else
-  IEN(USB0, USBI0) = 1;
-#endif
-}
-
-void hcd_int_disable(uint8_t rhport)
-{
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 0;
-#else
-  IEN(USB0, USBI0) = 0;
-#endif
-}
-
-uint32_t hcd_frame_number(uint8_t rhport)
-{
-  (void)rhport;
-  /* The device must be reset at least once after connection 
-   * in order to start the frame counter. */
-  if (_hcd.need_reset) hcd_port_reset(rhport);
-  return USB0.FRMNUM.BIT.FRNM;
-}
-
-/*--------------------------------------------------------------------+
- * Port API
- *--------------------------------------------------------------------+*/
-bool hcd_port_connect_status(uint8_t rhport)
-{
-  (void)rhport;
-  return USB0.INTSTS1.BIT.ATTCH ? true: false;
-}
-
-void hcd_port_reset(uint8_t rhport)
-{
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
-  while (USB0.DCPCTR.BIT.PBUSY) ;
-  hcd_int_disable(rhport);
-  USB0.DVSTCTR0.BIT.UACT   = 0;
-  if (USB0.DCPCTR.BIT.SUREQ)
-    USB0.DCPCTR.BIT.SUREQCLR = 1;
-  hcd_int_enable(rhport);
-  /* Reset should be asserted 10-20ms. */
-  USB0.DVSTCTR0.BIT.USBRST = 1;
-  for (volatile int i = 0; i < 2400000; ++i) ;
-  USB0.DVSTCTR0.BIT.USBRST = 0;
-  USB0.DVSTCTR0.BIT.UACT   = 1;
-  _hcd.need_reset = false;
-}
-
-void hcd_port_reset_end(uint8_t rhport)
-{
-  (void) rhport;
-}
-
-tusb_speed_t hcd_port_speed_get(uint8_t rhport)
-{
-  (void)rhport;
-  switch (USB0.DVSTCTR0.BIT.RHST) {
-    default: return TUSB_SPEED_INVALID;
-    case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL;
-    case USB_DVSTCTR0_LOW:  return TUSB_SPEED_LOW;
-  }
-}
-
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
-{
-  (void)rhport;
-  uint16_t volatile *ctr;
-  TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */
-  if (!dev_addr) return;
-  _hcd.ctl_mps[dev_addr] = 0;
-  uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0];
-  for (int i = 0; i < 2 * 15; ++i, ++ep) {
-    unsigned num = *ep;
-    if (!num || dev_addr != _hcd.pipe[num].dev) continue;
-
-    ctr  = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1;
-    *ctr = 0;
-    USB0.NRDYENB.WORD &= ~TU_BIT(num);
-    USB0.BRDYENB.WORD &= ~TU_BIT(num);
-    USB0.PIPESEL.WORD  = num;
-    USB0.PIPECFG.WORD  = 0;
-    USB0.PIPEMAXP.WORD = 0;
-
-    _hcd.pipe[num].ep  = 0;
-    _hcd.pipe[num].dev = 0;
-    *ep                = 0;
-  }
-}
-
-/*--------------------------------------------------------------------+
- * Endpoints API
- *--------------------------------------------------------------------+*/
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
-{
-  (void)rhport;
-  //  TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD);
-
-  TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
-  TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ);
-
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
-
-  _hcd.pipe[0].buf       = NULL;
-  _hcd.pipe[0].length    = 8;
-  _hcd.pipe[0].remaining = 0;
-  _hcd.pipe[0].dev       = dev_addr;
-
-  while (USB0.DCPCTR.BIT.PBUSY) ;
-  USB0.DCPMAXP.WORD      = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
-
-  /* Set direction in advance for DATA stage */
-  uint8_t const bmRequesttype = setup_packet[0];
-  USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
-
-  uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
-  USB0.USBREQ.WORD = tu_htole16(p[0]);
-  USB0.USBVAL      = p[1];
-  USB0.USBINDX     = p[2];
-  USB0.USBLENG     = p[3];
-
-  USB0.DCPCTR.BIT.SUREQ = 1;
-  return true;
-}
-
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
-{
-  (void)rhport;
-  TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
-
-  const unsigned ep_addr = ep_desc->bEndpointAddress;
-  const unsigned epn     = tu_edpt_number(ep_addr);
-  const unsigned mps     = tu_edpt_packet_size(ep_desc);
-  if (0 == epn) {
-    USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
-    hcd_devtree_info_t devtree;
-    hcd_devtree_get_info(dev_addr, &devtree);
-    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD;
-    devadd += dev_addr;
-    while (USB0.DCPCTR.BIT.PBUSY) ;
-    USB0.DCPMAXP.WORD = (dev_addr << 12) | mps;
-    *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW;
-    _hcd.ctl_mps[dev_addr] = mps;
-    return true;
-  }
-
-  const unsigned dir_in = tu_edpt_dir(ep_addr);
-  const unsigned xfer   = ep_desc->bmAttributes.xfer;
-  if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
-    /* USBa supports up to 256 bytes */
-    return false;
-  }
-  const unsigned num = find_pipe(xfer);
-  if (!num) return false;
-  _hcd.pipe[num].dev = dev_addr;
-  _hcd.pipe[num].ep  = ep_addr;
-  _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num;
-
-  /* setup pipe */
-  hcd_int_disable(rhport);
-  USB0.PIPESEL.WORD  = num;
-  USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps;
-  volatile uint16_t *ctr = get_pipectr(num);
-  *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
-  *ctr = 0;
-  unsigned cfg = ((1 ^ dir_in) << 4) | epn;
-  if (xfer == TUSB_XFER_BULK) {
-    cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB;
-  } else if (xfer == TUSB_XFER_INTERRUPT) {
-    cfg |= USB_PIPECFG_INT;
-  } else {
-    cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
-  }
-  USB0.PIPECFG.WORD  = cfg;
-  USB0.BRDYSTS.WORD  = 0x1FFu ^ TU_BIT(num);
-  USB0.NRDYENB.WORD |= TU_BIT(num);
-  USB0.BRDYENB.WORD |= TU_BIT(num);
-  if (!dir_in) {
-    *ctr = USB_PIPECTR_PID_BUF;
-  }
-  hcd_int_enable(rhport);
-
-  return true;
-}
-
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
-{
-  bool r;
-  hcd_int_disable(rhport);
-  // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen);
-  r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen);
-  hcd_int_enable(rhport);
-  return r;
-}
-
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
-  uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr);
-  TU_ASSERT(ctr);
-
-  const uint32_t pid = *ctr & 0x3;
-  if (pid & 2) {
-    *ctr = pid & 2;
-    *ctr = 0;
-  }
-  *ctr = USB_PIPECTR_SQCLR;
-  unsigned const epn = tu_edpt_number(ep_addr);
-  if (!epn) return true;
-
-  if (!tu_edpt_dir(ep_addr)) { /* OUT */
-    *ctr = USB_PIPECTR_PID_BUF;
-  }
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-void hcd_int_handler(uint8_t rhport)
-{
-  (void)rhport;
-#if defined(__CCRX__)
-  static const int Mod37BitPosition[] = {
-    -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4,
-    7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
-    20, 8, 19, 18};
-#endif
-
-  unsigned is1 = USB0.INTSTS1.WORD;
-  unsigned is0 = USB0.INTSTS0.WORD;
-  /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1);
-  USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0);
-  // TU_LOG1("IS %04x %04x\n", is0, is1);
-  is1 &= USB0.INTENB1.WORD;
-  is0 &= USB0.INTENB0.WORD;
-
-  if (is1 & USB_IS1_SACK) {
-    /* Set DATA1 in advance for the next transfer. */
-    USB0.DCPCTR.BIT.SQSET = 1;
-    hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
-                            tu_edpt_addr(0, TUSB_DIR_OUT),
-                            8, XFER_RESULT_SUCCESS, true);
-  }
-  if (is1 & USB_IS1_SIGN) {
-    hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
-                            tu_edpt_addr(0, TUSB_DIR_OUT),
-                            8, XFER_RESULT_FAILED, true);
-  }
-  if (is1 & USB_IS1_ATTCH) {
-    USB0.DVSTCTR0.BIT.UACT = 1;
-    _hcd.need_reset = true;
-    USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH;
-    hcd_event_device_attach(rhport, true);
-  }
-  if (is1 & USB_IS1_DTCH) {
-    USB0.DVSTCTR0.BIT.UACT = 0;
-    if (USB0.DCPCTR.BIT.SUREQ)
-      USB0.DCPCTR.BIT.SUREQCLR = 1;
-    USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH;
-    hcd_event_device_remove(rhport, true);
-  }
-
-  if (is0 & USB_IS0_BEMP) {
-    const unsigned s = USB0.BEMPSTS.WORD;
-    USB0.BEMPSTS.WORD = 0;
-    if (s & 1) {
-      process_pipe0_bemp(rhport);
-    }
-  }
-  if (is0 & USB_IS0_NRDY) {
-    const unsigned m = USB0.NRDYENB.WORD;
-    unsigned s       = USB0.NRDYSTS.WORD & m;
-    USB0.NRDYSTS.WORD = ~s;
-    while (s) {
-#if defined(__CCRX__)
-      const unsigned num = Mod37BitPosition[(-s & s) % 37];
-#else
-      const unsigned num = __builtin_ctz(s);
-#endif
-      process_pipe_nrdy(rhport, num);
-      s &= ~TU_BIT(num);
-    }
-  }
-  if (is0 & USB_IS0_BRDY) {
-    const unsigned m = USB0.BRDYENB.WORD;
-    unsigned s       = USB0.BRDYSTS.WORD & m;
-    /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    USB0.BRDYSTS.WORD = ~s;
-    while (s) {
-#if defined(__CCRX__)
-      const unsigned num = Mod37BitPosition[(-s & s) % 37];
-#else
-      const unsigned num = __builtin_ctz(s);
-#endif
-      process_pipe_brdy(rhport, num);
-      s &= ~TU_BIT(num);
-    }
-  }
-}
-
-#endif
diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index 6677891a5..b16509c6f 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -102,17 +102,25 @@ static int _dcd_bind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_
   usbdev = dev;
   usbdcd_driver.ep[0] = dev->ep0;
 
+  #ifdef EP_ALLOCREQ
+  // SDK v2
   usbdcd_driver.req[0] = EP_ALLOCREQ(usbdcd_driver.ep[0]);
-  if (usbdcd_driver.req[0] != NULL)
-  {
+  if (usbdcd_driver.req[0] != NULL) {
     usbdcd_driver.req[0]->len = 64;
     usbdcd_driver.req[0]->buf = EP_ALLOCBUFFER(usbdcd_driver.ep[0], 64);
-    if (!usbdcd_driver.req[0]->buf)
-    {
+    if (!usbdcd_driver.req[0]->buf) {
       EP_FREEREQ(usbdcd_driver.ep[0], usbdcd_driver.req[0]);
       usbdcd_driver.req[0] = NULL;
+      return ENOMEM;
     }
   }
+  #else
+  // SDK v3
+  usbdcd_driver.req[0] = usbdev_allocreq(usbdcd_driver.ep[0], 64);
+  if (usbdcd_driver.req[0] == NULL) {
+    return ENOMEM;
+  }
+  #endif
 
   usbdcd_driver.req[0]->callback = usbdcd_ep0incomplete;
 
@@ -193,9 +201,9 @@ static void _dcd_resume(FAR struct usbdevclass_driver_s *driver, FAR struct usbd
   dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
 }
 
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   usbdcd_driver.usbdevclass_driver.speed = USB_SPEED_HIGH;
   usbdcd_driver.usbdevclass_driver.ops = &g_driverops;
@@ -203,6 +211,8 @@ void dcd_init(uint8_t rhport)
   usbdcd_driver.setup_queue = osal_queue_create(&_setup_queue_def);
 
   usbdev_register(&usbdcd_driver.usbdevclass_driver);
+
+  return true;
 }
 
 // Enable device interrupt
@@ -295,13 +305,19 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
   }
 
   usbdcd_driver.req[epnum] = NULL;
+
+  #ifdef EP_ALLOCREQ
+  // sdk v2
   usbdcd_driver.req[epnum] = EP_ALLOCREQ(usbdcd_driver.ep[epnum]);
-  if (usbdcd_driver.req[epnum] != NULL)
-  {
+  if (usbdcd_driver.req[epnum] != NULL) {
     usbdcd_driver.req[epnum]->len = ep_mps;
   }
-  else
-  {
+  #else
+  // sdk v3
+  usbdcd_driver.req[epnum] = usbdev_allocreq(usbdcd_driver.ep[epnum], ep_mps);
+  #endif
+
+  if(usbdcd_driver.req[epnum] == NULL) {
     return false;
   }
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index c88a8a3a2..ef58957bb 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -1,11 +1,12 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Nathan Conrad
  *
  * Portions:
- * Copyright (c) 2016 STMicroelectronics
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2022 Simon KÃŧppers (skuep)
+ * Copyright (c) 2022 HiFiPhile
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -35,13 +36,21 @@
  * It also should work with minimal changes for any ST MCU with an "USB A"/"PCD"/"HCD" peripheral. This
  *  covers:
  *
- * F04x, F072, F078, 070x6/B      1024 byte buffer
+ * F04x, F072, F078, F070x6/B     1024 byte buffer
  * F102, F103                      512 byte buffer; no internal D+ pull-up (maybe many more changes?)
  * F302xB/C, F303xB/C, F373        512 byte buffer; no internal D+ pull-up
  * F302x6/8, F302xD/E2, F303xD/E  1024 byte buffer; no internal D+ pull-up
+ * C0                             2048 byte buffer; 32-bit bus; host mode
+ * G0                             2048 byte buffer; 32-bit bus; host mode
+ * G4                             1024 byte buffer
+ * H5                             2048 byte buffer; 32-bit bus; host mode
  * L0x2, L0x3                     1024 byte buffer
  * L1                              512 byte buffer
  * L4x2, L4x3                     1024 byte buffer
+ * L5                             1024 byte buffer
+ * U0                             1024 byte buffer; 32-bit bus
+ * U535, U545                     2048 byte buffer; 32-bit bus; host mode
+ * WB35, WB55                     1024 byte buffer
  *
  * To use this driver, you must:
  * - If you are using a device with crystal-less USB, set up the clock recovery system (CRS)
@@ -64,10 +73,6 @@
  * - STALL handled, but not tested.
  *   - Does it work? No clue.
  * - All EP BTABLE buffers are created based on max packet size of first EP opened with that address.
- * - No isochronous endpoints
- * - Endpoint index is the ID of the endpoint
- *   - This means that priority is given to endpoints with lower ID numbers
- *   - Code is mixing up EP IX with EP ID. Everywhere.
  * - Packet buffer memory is copied in the interrupt.
  *   - This is better for performance, but means interrupts are disabled for longer
  *   - DMA may be the best choice, but it could also be pushed to the USBD task.
@@ -103,569 +108,361 @@
 
 #include "tusb_option.h"
 
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
-    defined(STM32F103x6) || defined(STM32F103xB) || \
-    defined(STM32F103xE) || defined(STM32F103xG)
-#define STM32F1_FSDEV
-#endif
-
-#if defined(STM32L412xx) || defined(STM32L422xx) || \
-    defined(STM32L432xx) || defined(STM32L433xx) || \
-    defined(STM32L442xx) || defined(STM32L443xx) || \
-    defined(STM32L452xx) || defined(STM32L462xx)
-#define STM32L4_FSDEV
-#endif
-
-#if CFG_TUD_ENABLED && \
-      ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4, OPT_MCU_STM32WB) || \
-        (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) || \
-        (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) \
-      )
-
-// In order to reduce the dependance on HAL, we undefine this.
-// Some definitions are copied to our private include file.
-#undef USE_HAL_DRIVER
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_FSDEV) && \
+    !(defined(TUP_USBIP_FSDEV_CH32) && CFG_TUD_WCH_USBIP_FSDEV == 0)
 
 #include "device/dcd.h"
-#include "portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h"
 
-
-/*****************************************************
- * Configuration
- *****************************************************/
-
-// HW supports max of 8 bidirectional endpoints, but this can be reduced to save RAM
-// (8u here would mean 8 IN and 8 OUT)
-#ifndef MAX_EP_COUNT
-#  define MAX_EP_COUNT 8U
+#if defined(TUP_USBIP_FSDEV_STM32)
+  #include "fsdev_stm32.h"
+#elif defined(TUP_USBIP_FSDEV_CH32)
+  #include "fsdev_ch32.h"
+#else
+  #error "Unknown USB IP"
 #endif
 
-// If sharing with CAN, one can set this to be non-zero to give CAN space where it wants it
-// Both of these MUST be a multiple of 2, and are in byte units.
-#ifndef DCD_STM32_BTABLE_BASE
-#  define DCD_STM32_BTABLE_BASE 0U
-#endif
+#include "fsdev_type.h"
 
-#ifndef DCD_STM32_BTABLE_LENGTH
-#  define DCD_STM32_BTABLE_LENGTH (PMA_LENGTH - DCD_STM32_BTABLE_BASE)
-#endif
-
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#ifndef USE_SOF
-#  define USE_SOF     0
-#endif
-
-/***************************************************
- * Checks, structs, defines, function definitions, etc.
- */
-
-TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware");
-
-TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH),
-    "BTABLE does not fit in PMA RAM");
-
-TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes");
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
 
 // One of these for every EP IN & OUT, uses a bit of RAM....
-typedef struct
-{
-  uint8_t * buffer;
-  // tu_fifo_t * ff;  // TODO support dcd_edpt_xfer_fifo API
+typedef struct {
+  uint8_t *buffer;
+  tu_fifo_t *ff;
   uint16_t total_len;
   uint16_t queued_len;
-  uint16_t pma_ptr;
-  uint8_t max_packet_size;
-  uint8_t pma_alloc_size;
+  uint16_t max_packet_size;
+  uint8_t ep_idx;   // index for USB_EPnR register
+  bool iso_in_sending; // Workaround for ISO IN EP doesn't have interrupt mask
 } xfer_ctl_t;
 
-static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
+// EP allocator
+typedef struct {
+  uint8_t ep_num;
+  uint8_t ep_type;
+  bool allocated[2];
+} ep_alloc_t;
 
-static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t epnum, uint32_t dir)
-{
+static xfer_ctl_t xfer_status[CFG_TUD_ENDPPOINT_MAX][2];
+static ep_alloc_t ep_alloc_status[FSDEV_EP_COUNT];
+static uint8_t remoteWakeCountdown; // When wake is requested
+
+//--------------------------------------------------------------------+
+// Prototypes
+//--------------------------------------------------------------------+
+
+// into the stack.
+static void handle_bus_reset(uint8_t rhport);
+static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix);
+static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, tusb_dir_t dir);
+
+// PMA allocation/access
+static uint16_t ep_buf_ptr; ///< Points to first free memory location
+static uint32_t dcd_pma_alloc(uint16_t len, bool dbuf);
+static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t nbytes);
+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t nbytes);
+
+static bool dcd_write_packet_memory_ff(tu_fifo_t *ff, uint16_t dst, uint16_t wNBytes);
+static bool dcd_read_packet_memory_ff(tu_fifo_t *ff, uint16_t src, uint16_t wNBytes);
+
+static void edpt0_open(uint8_t rhport);
+
+TU_ATTR_ALWAYS_INLINE static inline void edpt0_prepare_setup(void) {
+   btable_set_rx_bufsize(0, BTABLE_BUF_RX, 8);
+}
+
+//--------------------------------------------------------------------+
+// Inline helper
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint8_t epnum, uint8_t dir) {
   return &xfer_status[epnum][dir];
 }
 
-static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
-
-static uint8_t remoteWakeCountdown; // When wake is requested
-
-// into the stack.
-static void dcd_handle_bus_reset(void);
-static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
-static void dcd_ep_ctr_handler(void);
-
-// PMA allocation/access 
-static uint8_t open_ep_count;
-static uint16_t ep_buf_ptr; ///< Points to first free memory location
-static void dcd_pma_alloc_reset(void);
-static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length);
-static void dcd_pma_free(uint8_t ep_addr);
-static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
-static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
-
-//static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes);
-//static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes);
-
-// Using a function due to better type checks
-// This seems better than having to do type casts everywhere else
-static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) {
-  *reg = (uint16_t)(*reg & ~mask);
-}
-
-// Bits in ISTR are cleared upon writing 0
-static inline void clear_istr_bits(uint16_t mask) {
-  USB->ISTR = ~mask;
-}
-
-void dcd_init (uint8_t rhport)
-{
-  /* Clocks should already be enabled */
-  /* Use __HAL_RCC_USB_CLK_ENABLE(); to enable the clocks before calling this function */
-
-  /* The RM mentions to use a special ordering of PDWN and FRES, but this isn't done in HAL.
-   * Here, the RM is followed. */
-
-  for(uint32_t i = 0; i<200; i++) // should be a few us
-  {
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+  // Follow the RM mentions to use a special ordering of PDWN and FRES
+  for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
     asm("NOP");
   }
-	// Perform USB peripheral reset
-  USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
-  for(uint32_t i = 0; i<200; i++) // should be a few us
-  {
+
+  // Perform USB peripheral reset
+  FSDEV_REG->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
+  for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
     asm("NOP");
   }
-  reg16_clear_bits(&USB->CNTR, USB_CNTR_PDWN);// Remove powerdown
+
+  FSDEV_REG->CNTR &= ~USB_CNTR_PDWN;
+
   // Wait startup time, for F042 and F070, this is <= 1 us.
-  for(uint32_t i = 0; i<200; i++) // should be a few us
-  {
+  for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
     asm("NOP");
   }
-  USB->CNTR = 0; // Enable USB
-  
-  USB->BTABLE = DCD_STM32_BTABLE_BASE;
+  FSDEV_REG->CNTR = 0; // Enable USB
 
-  USB->ISTR = 0; // Clear pending interrupts
+#if !defined(FSDEV_BUS_32BIT)
+  // BTABLE register does not exist any more on 32-bit bus devices
+  FSDEV_REG->BTABLE = FSDEV_BTABLE_BASE;
+#endif
+
+  FSDEV_REG->ISTR = 0; // Clear pending interrupts
 
   // Reset endpoints to disabled
-  for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
-  {
+  for (uint32_t i = 0; i < FSDEV_EP_COUNT; i++) {
     // This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED.
-    pcd_set_endpoint(USB,i,0u);
+    ep_write(i, 0u, false);
   }
 
-  USB->CNTR |= USB_CNTR_RESETM | (USE_SOF ? USB_CNTR_SOFM : 0) | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
-  dcd_handle_bus_reset();
-  
+  FSDEV_REG->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM |
+      USB_CNTR_SUSPM | USB_CNTR_WKUPM | USB_CNTR_PMAOVRM;
+  handle_bus_reset(rhport);
+
   // Enable pull-up if supported
-  if ( dcd_connect ) dcd_connect(rhport);
+  dcd_connect(rhport);
+
+  return true;
 }
 
-// Define only on MCU with internal pull-up. BSP can define on MCU without internal PU.
-#if defined(USB_BCDR_DPPU)
-
-// Disable internal D+ PU
-void dcd_disconnect(uint8_t rhport)
-{
-  (void) rhport;
-  USB->BCDR &= ~(USB_BCDR_DPPU);
-}
-
-// Enable internal D+ PU
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  USB->BCDR |= USB_BCDR_DPPU;
-}
-
-#elif defined(SYSCFG_PMC_USB_PU) // works e.g. on STM32L151
-// Disable internal D+ PU
-void dcd_disconnect(uint8_t rhport)
-{
-  (void) rhport;
-  SYSCFG->PMC &= ~(SYSCFG_PMC_USB_PU);
-}
-
-// Enable internal D+ PU
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  SYSCFG->PMC |= SYSCFG_PMC_USB_PU;
-}
-#endif
-
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
-  (void) rhport;
-  (void) en;
-
-  // TODO implement later
-}
-
-// Enable device interrupt
-void dcd_int_enable (uint8_t rhport)
-{
-  (void)rhport;
-  // Member here forces write to RAM before allowing ISR to execute
-  __DSB();
-  __ISB();
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \
-    CFG_TUSB_MCU == OPT_MCU_STM32L4
-  NVIC_EnableIRQ(USB_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
-  NVIC_EnableIRQ(USB_LP_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
-  // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
-  // shared USB/CAN IRQs to separate CAN and USB IRQs.
-  // This dynamically checks if this remap is active to enable the right IRQs.
-  #ifdef SYSCFG_CFGR1_USB_IT_RMP
-  if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP)
-  {
-    NVIC_EnableIRQ(USB_HP_IRQn);
-    NVIC_EnableIRQ(USB_LP_IRQn);
-    NVIC_EnableIRQ(USBWakeUp_RMP_IRQn);
-  }
-  else
-  #endif
-  {
-    NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn);
-    NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
-    NVIC_EnableIRQ(USBWakeUp_IRQn);
-  }
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
-  NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn);
-  NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
-  NVIC_EnableIRQ(USBWakeUp_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
-  NVIC_EnableIRQ(USB_HP_IRQn);
-  NVIC_EnableIRQ(USB_LP_IRQn);
-  NVIC_EnableIRQ(USBWakeUp_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
-  NVIC_EnableIRQ(USB_HP_IRQn);
-  NVIC_EnableIRQ(USB_LP_IRQn);
-
-#else
-  #error Unknown arch in USB driver
-#endif
-}
-
-// Disable device interrupt
-void dcd_int_disable(uint8_t rhport)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
   (void)rhport;
 
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \
-    CFG_TUSB_MCU == OPT_MCU_STM32L4
-  NVIC_DisableIRQ(USB_IRQn);
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
-  NVIC_DisableIRQ(USB_LP_IRQn);
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
-  // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
-  // shared USB/CAN IRQs to separate CAN and USB IRQs.
-  // This dynamically checks if this remap is active to disable the right IRQs.
-  #ifdef SYSCFG_CFGR1_USB_IT_RMP
-  if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP)
-  {
-    NVIC_DisableIRQ(USB_HP_IRQn);
-    NVIC_DisableIRQ(USB_LP_IRQn);
-    NVIC_DisableIRQ(USBWakeUp_RMP_IRQn);
+  if (en) {
+    FSDEV_REG->CNTR |= USB_CNTR_SOFM;
+  } else {
+    FSDEV_REG->CNTR &= ~USB_CNTR_SOFM;
   }
-  else
-  #endif
-  {
-    NVIC_DisableIRQ(USB_HP_CAN_TX_IRQn);
-    NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn);
-    NVIC_DisableIRQ(USBWakeUp_IRQn);
-  }
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
-  NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn);
-  NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
-  NVIC_DisableIRQ(USBWakeUp_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
-  NVIC_DisableIRQ(USB_HP_IRQn);
-  NVIC_DisableIRQ(USB_LP_IRQn);
-  NVIC_DisableIRQ(USBWakeUp_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
-  NVIC_DisableIRQ(USB_HP_IRQn);
-  NVIC_DisableIRQ(USB_LP_IRQn);
-
-#else
-  #error Unknown arch in USB driver
-#endif
-
-  // CMSIS has a membar after disabling interrupts
 }
 
 // Receive Set Address request, mcu port must also include status IN response
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void) rhport;
-  (void) dev_addr;
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  (void)dev_addr;
 
   // Respond with status
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  dcd_edpt_xfer(rhport, TUSB_DIR_IN_MASK | 0x00, NULL, 0);
 
   // DCD can only set address after status for this request is complete.
   // do it at dcd_edpt0_status_complete()
 }
 
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
+void dcd_remote_wakeup(uint8_t rhport) {
+  (void)rhport;
 
-  USB->CNTR |= (uint16_t) USB_CNTR_RESUME;
+  FSDEV_REG->CNTR |= USB_CNTR_RESUME;
   remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
 }
 
-static const tusb_desc_endpoint_t ep0OUT_desc =
-{
-  .bLength          = sizeof(tusb_desc_endpoint_t),
-  .bDescriptorType  = TUSB_DESC_ENDPOINT,
+static void handle_bus_reset(uint8_t rhport) {
+  FSDEV_REG->DADDR = 0u; // disable USB Function
 
-  .bEndpointAddress = 0x00,
-  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
-  .bInterval        = 0
-};
-
-static const tusb_desc_endpoint_t ep0IN_desc =
-{
-  .bLength          = sizeof(tusb_desc_endpoint_t),
-  .bDescriptorType  = TUSB_DESC_ENDPOINT,
-
-  .bEndpointAddress = 0x80,
-  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
-  .bInterval        = 0
-};
-
-static void dcd_handle_bus_reset(void)
-{
-  //__IO uint16_t * const epreg = &(EPREG(0));
-  USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
-
-  // Clear all EPREG (or maybe this is automatic? I'm not sure)
-  for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
-  {
-    pcd_set_endpoint(USB,i,0u);
+  for (uint32_t i = 0; i < FSDEV_EP_COUNT; i++) {
+    // Clear EP allocation status
+    ep_alloc_status[i].ep_num = 0xFF;
+    ep_alloc_status[i].ep_type = 0xFF;
+    ep_alloc_status[i].allocated[0] = false;
+    ep_alloc_status[i].allocated[1] = false;
   }
 
-  dcd_pma_alloc_reset();
-  dcd_edpt_open (0, &ep0OUT_desc);
-  dcd_edpt_open (0, &ep0IN_desc);
+  // Reset PMA allocation
+  ep_buf_ptr = FSDEV_BTABLE_BASE + 8 * FSDEV_EP_COUNT;
 
-  USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero.
+  edpt0_open(rhport); // open control endpoint (both IN & OUT)
+
+  FSDEV_REG->DADDR = USB_DADDR_EF; // Enable USB Function
 }
 
 // Handle CTR interrupt for the TX/IN direction
-//
-// Upon call, (wIstr & USB_ISTR_DIR) == 0U
-static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
-{
-  uint32_t EPindex = wIstr & USB_ISTR_EP_ID;
-  uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex);
+static void handle_ctr_tx(uint32_t ep_id) {
+  uint32_t ep_reg = ep_read(ep_id) | USB_EP_CTR_TX | USB_EP_CTR_RX;
 
-  // Verify the CTR_TX bit is set. This was in the ST Micro code,
-  // but I'm not sure it's actually necessary?
-  if((wEPRegVal & USB_EP_CTR_TX) == 0U)
-  {
-    return;
+  uint8_t const ep_num = ep_reg & USB_EPADDR_FIELD;
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, TUSB_DIR_IN);
+
+  if (ep_is_iso(ep_reg)) {
+    // Ignore spurious interrupts that we don't schedule
+    // host can send IN token while there is no data to send, since ISO does not have NAK
+    // this will result to zero length packet --> trigger interrupt (which cannot be masked)
+    if (!xfer->iso_in_sending) {
+      return;
+    }
+    xfer->iso_in_sending = false;
+    uint8_t buf_id = (ep_reg & USB_EP_DTOG_TX) ? 0 : 1;
+    btable_set_count(ep_id, buf_id, 0);
   }
 
-  /* clear int flag */
-  pcd_clear_tx_ep_ctr(USB, EPindex);
-
-  xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_IN);
-  if((xfer->total_len != xfer->queued_len)) /* TX not complete */
-  {
-      dcd_transmit_packet(xfer, EPindex);
+  if (xfer->total_len != xfer->queued_len) {
+    dcd_transmit_packet(xfer, ep_id);
+  } else {
+    dcd_event_xfer_complete(0, ep_num | TUSB_DIR_IN_MASK, xfer->queued_len, XFER_RESULT_SUCCESS, true);
   }
-  else /* TX Complete */
-  {
-    dcd_event_xfer_complete(0, (uint8_t)(0x80 + EPindex), xfer->total_len, XFER_RESULT_SUCCESS, true);
+}
+
+static void handle_ctr_setup(uint32_t ep_id) {
+  uint16_t rx_count = btable_get_count(ep_id, BTABLE_BUF_RX);
+  uint16_t rx_addr = btable_get_addr(ep_id, BTABLE_BUF_RX);
+  uint8_t setup_packet[8] TU_ATTR_ALIGNED(4);
+
+  dcd_read_packet_memory(setup_packet, rx_addr, rx_count);
+
+  // Clear CTR RX if another setup packet arrived before this, it will be discarded
+  ep_write_clear_ctr(ep_id, TUSB_DIR_OUT);
+
+  // Setup packet should always be 8 bytes. If not, we probably missed the packet
+  if (rx_count == 8) {
+    dcd_event_setup_received(0, (uint8_t*) setup_packet, true);
+    // Hardware should reset EP0 RX/TX to NAK and both toggle to 1
+  } else {
+    // Missed setup packet !!!
+    TU_BREAKPOINT();
+    edpt0_prepare_setup();
   }
 }
 
 // Handle CTR interrupt for the RX/OUT direction
-//
-// Upon call, (wIstr & USB_ISTR_DIR) == 0U
-static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
-{
-  uint32_t EPindex = wIstr & USB_ISTR_EP_ID;
-  uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex);
-  uint32_t count = pcd_get_ep_rx_cnt(USB,EPindex);
+static void handle_ctr_rx(uint32_t ep_id) {
+  uint32_t ep_reg = ep_read(ep_id) | USB_EP_CTR_TX | USB_EP_CTR_RX;
+  uint8_t const ep_num = ep_reg & USB_EPADDR_FIELD;
+  bool const is_iso = ep_is_iso(ep_reg);
+  xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, TUSB_DIR_OUT);
 
-  xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_OUT);
-
-  // Verify the CTR_RX bit is set. This was in the ST Micro code,
-  // but I'm not sure it's actually necessary?
-  if((wEPRegVal & USB_EP_CTR_RX) == 0U)
-  {
-    return;
+  uint8_t buf_id;
+  if (is_iso) {
+    buf_id = (ep_reg & USB_EP_DTOG_RX) ? 0 : 1; // ISO are double buffered
+  } else {
+    buf_id = BTABLE_BUF_RX;
   }
-  
-  if((EPindex == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */
-  {
-    // The setup_received function uses memcpy, so this must first copy the setup data into
-    // user memory, to allow for the 32-bit access that memcpy performs.
-    uint8_t userMemBuf[8];
-    /* Get SETUP Packet*/
-    if(count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again.
-    {
-      // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
-      pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK);
-      pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK);
-      dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB,EPindex), 8);
-      dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
-    }
+  uint16_t const rx_count = btable_get_count(ep_id, buf_id);
+  uint16_t pma_addr = (uint16_t) btable_get_addr(ep_id, buf_id);
+
+  if (xfer->ff) {
+    dcd_read_packet_memory_ff(xfer->ff, pma_addr, rx_count);
+  } else {
+    dcd_read_packet_memory(xfer->buffer + xfer->queued_len, pma_addr, rx_count);
   }
-  else
-  {
-    // Clear RX CTR interrupt flag
-    if(EPindex != 0u)
-    {
-      pcd_clear_rx_ep_ctr(USB, EPindex);
-    }
-
-    if (count != 0U)
-    {
-#if 0 // TODO support dcd_edpt_xfer_fifo API
-      if (xfer->ff)
-      {
-        dcd_read_packet_memory_ff(xfer->ff, *pcd_ep_rx_address_ptr(USB,EPindex), count);
-      }
-      else
-#endif
-      {
-        dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), *pcd_ep_rx_address_ptr(USB,EPindex), count);
-      }
-
-      xfer->queued_len = (uint16_t)(xfer->queued_len + count);
-    }
-
-    if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
-    {
-      /* RX COMPLETE */
-      dcd_event_xfer_complete(0, EPindex, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-      // Though the host could still send, we don't know.
-      // Does the bulk pipe need to be reset to valid to allow for a ZLP?
-    }
-    else
-    {
-      uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len;
-      if(remaining >= xfer->max_packet_size) {
-        pcd_set_ep_rx_cnt(USB, EPindex,xfer->max_packet_size);
-      } else {
-        pcd_set_ep_rx_cnt(USB, EPindex,remaining);
-      }
-      pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
-    }
-  }
-
-  // For EP0, prepare to receive another SETUP packet.
-  // Clear CTR last so that a new packet does not overwrite the packing being read.
-  // (Based on the docs, it seems SETUP will always be accepted after CTR is cleared)
-  if(EPindex == 0u)
-  {
-      // Always be prepared for a status packet...
-    pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
-    pcd_clear_rx_ep_ctr(USB, EPindex);
-  }
-}
-
-static void dcd_ep_ctr_handler(void)
-{
-  uint32_t wIstr;
-
-  /* stay in loop while pending interrupts */
-  while (((wIstr = USB->ISTR) & USB_ISTR_CTR) != 0U)
-  {
-
-    if ((wIstr & USB_ISTR_DIR) == 0U) /* TX/IN */
-    {
-      dcd_ep_ctr_tx_handler(wIstr);
-    }
-    else /* RX/OUT*/
-    {
-      dcd_ep_ctr_rx_handler(wIstr);
+  xfer->queued_len += rx_count;
+
+  if ((rx_count < xfer->max_packet_size) || (xfer->queued_len >= xfer->total_len)) {
+    // all bytes received or short packet
+
+    // For ch32v203: reset rx bufsize to mps to prevent race condition to cause PMAOVR (occurs with msc write10)
+    btable_set_rx_bufsize(ep_id, BTABLE_BUF_RX, xfer->max_packet_size);
+
+    dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+
+    // ch32 seems to unconditionally accept ZLP on EP0 OUT, which can incorrectly use queued_len of previous
+    // transfer. So reset total_len and queued_len to 0.
+    xfer->total_len = xfer->queued_len = 0;
+  } else {
+    // Set endpoint active again for receiving more data. Note that isochronous endpoints stay active always
+    if (!is_iso) {
+      uint16_t const cnt = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size);
+      btable_set_rx_bufsize(ep_id, BTABLE_BUF_RX, cnt);
     }
+    ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(TUSB_DIR_OUT); // will change RX Status, reserved other toggle bits
+    ep_change_status(&ep_reg, TUSB_DIR_OUT, EP_STAT_VALID);
+    ep_write(ep_id, ep_reg, false);
   }
 }
 
 void dcd_int_handler(uint8_t rhport) {
+  uint32_t int_status = FSDEV_REG->ISTR;
 
-  (void) rhport;
+  /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
+  if (int_status & USB_ISTR_SOF) {
+    FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_SOF;
+    dcd_event_sof(0, FSDEV_REG->FNR & USB_FNR_FN, true);
+  }
 
-  uint32_t int_status = USB->ISTR;
-  //const uint32_t handled_ints = USB_ISTR_CTR | USB_ISTR_RESET | USB_ISTR_WKUP
-  //    | USB_ISTR_SUSP | USB_ISTR_SOF | USB_ISTR_ESOF;
-  // unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_L1REQ )
-
-  // The ST driver loops here on the CTR bit, but that loop has been moved into the
-  // dcd_ep_ctr_handler(), so less need to loop here. The other interrupts shouldn't
-  // be triggered repeatedly.
-
-  if(int_status & USB_ISTR_RESET) {
+  if (int_status & USB_ISTR_RESET) {
     // USBRST is start of reset.
-    clear_istr_bits(USB_ISTR_RESET);
-    dcd_handle_bus_reset();
+    FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_RESET;
+    handle_bus_reset(rhport);
     dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
     return; // Don't do the rest of the things here; perhaps they've been cleared?
   }
 
-  if (int_status & USB_ISTR_CTR)
-  {
-    /* servicing of the endpoint correct transfer interrupt */
-    /* clear of the CTR flag into the sub */
-    dcd_ep_ctr_handler();
-  }
+  if (int_status & USB_ISTR_WKUP) {
+    FSDEV_REG->CNTR &= ~USB_CNTR_LPMODE;
+    FSDEV_REG->CNTR &= ~USB_CNTR_FSUSP;
 
-  if (int_status & USB_ISTR_WKUP)
-  {
-    reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE);
-    reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP);
-    clear_istr_bits(USB_ISTR_WKUP);
+    FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_WKUP;
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
 
-  if (int_status & USB_ISTR_SUSP)
-  {
+  if (int_status & USB_ISTR_SUSP) {
     /* Suspend is asserted for both suspend and unplug events. without Vbus monitoring,
      * these events cannot be differentiated, so we only trigger suspend. */
 
     /* Force low-power mode in the macrocell */
-    USB->CNTR |= USB_CNTR_FSUSP;
-    USB->CNTR |= USB_CNTR_LPMODE;
+    FSDEV_REG->CNTR |= USB_CNTR_FSUSP;
+    FSDEV_REG->CNTR |= USB_CNTR_LPMODE;
 
     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
-    clear_istr_bits(USB_ISTR_SUSP);
+    FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_SUSP;
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 
-#if USE_SOF
-  if(int_status & USB_ISTR_SOF) {
-    clear_istr_bits(USB_ISTR_SOF);
-    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
-  }
-#endif 
-
-  if(int_status & USB_ISTR_ESOF) {
-    if(remoteWakeCountdown == 1u)
-    {
-      USB->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
+  if (int_status & USB_ISTR_ESOF) {
+    if (remoteWakeCountdown == 1u) {
+      FSDEV_REG->CNTR &= ~USB_CNTR_RESUME;
     }
-    if(remoteWakeCountdown > 0u)
-    {
+    if (remoteWakeCountdown > 0u) {
       remoteWakeCountdown--;
     }
-    clear_istr_bits(USB_ISTR_ESOF);
+    FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_ESOF;
+  }
+
+  // loop to handle all pending CTR interrupts
+  while (FSDEV_REG->ISTR & USB_ISTR_CTR) {
+    // skip DIR bit, and use CTR TX/RX instead, since there is chance we have both TX/RX completed in one interrupt
+    uint32_t const ep_id = FSDEV_REG->ISTR & USB_ISTR_EP_ID;
+    uint32_t const ep_reg = ep_read(ep_id);
+
+    if (ep_reg & USB_EP_CTR_RX) {
+      #ifdef FSDEV_BUS_32BIT
+      /* https://www.st.com/resource/en/errata_sheet/es0561-stm32h503cbebkbrb-device-errata-stmicroelectronics.pdf
+       * https://www.st.com/resource/en/errata_sheet/es0587-stm32u535xx-and-stm32u545xx-device-errata-stmicroelectronics.pdf
+       * From H503/U535 errata: Buffer description table update completes after CTR interrupt triggers
+       * Description:
+       * - During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses
+       * have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.
+       * Workaround:
+       * - Software should ensure that a small delay is included before accessing the SRAM contents. This delay
+       * should be 800 ns in Full Speed mode and 6.4 Îŧs in Low Speed mode
+       * - Since H5 can run up to 250Mhz -> 1 cycle = 4ns. Per errata, we need to wait 200 cycles. Though executing code
+       * also takes time, so we'll wait 60 cycles (count = 20).
+       * - Since Low Speed mode is not supported/popular, we will ignore it for now.
+       *
+       * Note: this errata may also apply to G0, U5, H5 etc.
+       */
+      volatile uint32_t cycle_count = 20; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
+      while (cycle_count > 0U) {
+        cycle_count--; // each count take 3 cycles (1 for sub, jump, and compare)
+      }
+      #endif
+
+      if (ep_reg & USB_EP_SETUP) {
+        handle_ctr_setup(ep_id); // CTR will be clear after copied setup packet
+      } else {
+        ep_write_clear_ctr(ep_id, TUSB_DIR_OUT);
+        handle_ctr_rx(ep_id);
+      }
+    }
+
+    if (ep_reg & USB_EP_CTR_TX) {
+      ep_write_clear_ctr(ep_id, TUSB_DIR_IN);
+      handle_ctr_tx(ep_id);
+    }
+  }
+
+  if (int_status & USB_ISTR_PMAOVR) {
+    TU_BREAKPOINT();
+    FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_PMAOVR;
   }
 }
 
@@ -675,498 +472,508 @@ void dcd_int_handler(uint8_t rhport) {
 
 // Invoked when a control transfer's status stage is complete.
 // May help DCD to prepare for next control transfer, this API is optional.
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
-{
-  (void) rhport;
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
+  (void)rhport;
 
   if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
       request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
-      request->bRequest == TUSB_REQ_SET_ADDRESS )
-  {
-    uint8_t const dev_addr = (uint8_t) request->wValue;
-
-    // Setting new address after the whole request is complete
-    reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
-    USB->DADDR = (uint16_t)(USB->DADDR | dev_addr); // leave the enable bit set
+      request->bRequest == TUSB_REQ_SET_ADDRESS) {
+    uint8_t const dev_addr = (uint8_t)request->wValue;
+    FSDEV_REG->DADDR = (USB_DADDR_EF | dev_addr);
   }
-}
 
-static void dcd_pma_alloc_reset(void)
-{
-  ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
-  //TU_LOG2("dcd_pma_alloc_reset()\r\n");
-  for(uint32_t i=0; i<MAX_EP_COUNT; i++)
-  {
-    xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_alloc_size = 0U;
-    xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_alloc_size = 0U;
-    xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_ptr = 0U;
-    xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_ptr = 0U;
-  }
+  edpt0_prepare_setup();
 }
 
 /***
  * Allocate a section of PMA
- * 
- * If the EP number has already been allocated, and the new allocation
- * is larger than the old allocation, then this will fail with a TU_ASSERT.
- * (This is done to simplify the code. More complicated algorithms could be used)
- * 
+ * In case of double buffering, high 16bit is the address of 2nd buffer
  * During failure, TU_ASSERT is used. If this happens, rework/reallocate memory manually.
  */
-static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
+static uint32_t dcd_pma_alloc(uint16_t len, bool dbuf)
 {
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-  xfer_ctl_t* epXferCtl = xfer_ctl_ptr(epnum,dir);
+  uint8_t blsize, num_block;
+  uint16_t aligned_len = pma_align_buffer_size(len, &blsize, &num_block);
+  (void) blsize;
+  (void) num_block;
 
-  if(epXferCtl->pma_alloc_size != 0U)
-  {
-    //TU_LOG2("dcd_pma_alloc(%x,%x)=%x (cached)\r\n",ep_addr,length,epXferCtl->pma_ptr);
-    // Previously allocated
-    TU_ASSERT(length <= epXferCtl->pma_alloc_size, 0xFFFF);  // Verify no larger than previous alloc
-    return epXferCtl->pma_ptr;
+  uint32_t addr = ep_buf_ptr;
+  ep_buf_ptr = (uint16_t)(ep_buf_ptr + aligned_len); // increment buffer pointer
+
+  if (dbuf) {
+    addr |= ((uint32_t)ep_buf_ptr) << 16;
+    ep_buf_ptr = (uint16_t)(ep_buf_ptr + aligned_len); // increment buffer pointer
   }
-  
-  uint16_t addr = ep_buf_ptr; 
-  ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
-  
-  // Verify no overflow
-  TU_ASSERT(ep_buf_ptr <= PMA_LENGTH, 0xFFFF);
-  
-  epXferCtl->pma_ptr = addr;
-  epXferCtl->pma_alloc_size = length;
-  //TU_LOG2("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr);
+
+  // Verify packet buffer is not overflowed
+  TU_ASSERT(ep_buf_ptr <= FSDEV_PMA_SIZE, 0xFFFF);
 
   return addr;
 }
 
 /***
- * Free a block of PMA space
+ * Allocate hardware endpoint
  */
-static void dcd_pma_free(uint8_t ep_addr)
+static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
 {
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  // Presently, this should never be called for EP0 IN/OUT
-  TU_ASSERT(open_ep_count > 2, /**/);
-  TU_ASSERT(xfer_ctl_ptr(epnum,dir)->max_packet_size != 0, /**/);
-  open_ep_count--;
+  for (uint8_t i = 0; i < FSDEV_EP_COUNT; i++) {
+    // Check if already allocated
+    if (ep_alloc_status[i].allocated[dir] &&
+        ep_alloc_status[i].ep_type == ep_type &&
+        ep_alloc_status[i].ep_num == epnum) {
+      return i;
+    }
 
-  // If count is 2, only EP0 should be open, so allocations can be mostly reset.
+    // If EP of current direction is not allocated
+    // Except for ISO endpoint, both direction should be free
+    if (!ep_alloc_status[i].allocated[dir] &&
+        (ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1])) {
+      // Check if EP number is the same
+      if (ep_alloc_status[i].ep_num == 0xFF || ep_alloc_status[i].ep_num == epnum) {
+        // One EP pair has to be the same type
+        if (ep_alloc_status[i].ep_type == 0xFF || ep_alloc_status[i].ep_type == ep_type) {
+          ep_alloc_status[i].ep_num = epnum;
+          ep_alloc_status[i].ep_type = ep_type;
+          ep_alloc_status[i].allocated[dir] = true;
 
-  if(open_ep_count == 2)
-  {
-    ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT + 2*CFG_TUD_ENDPOINT0_SIZE; // 8 bytes per endpoint (two TX and two RX words, each), and EP0
-
-    // Skip EP0
-    for(uint32_t i=1; i<MAX_EP_COUNT; i++)
-    {
-      xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_alloc_size = 0U;
-      xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_alloc_size = 0U;
-      xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_ptr = 0U;
-      xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_ptr = 0U;
+          return i;
+        }
+      }
     }
   }
+
+  // Allocation failed
+  TU_ASSERT(0);
 }
 
-// The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
-// so I'm using the #define from HAL here, instead.
+void edpt0_open(uint8_t rhport) {
+  (void) rhport;
 
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
+  dcd_ep_alloc(0x0, TUSB_XFER_CONTROL);
+  dcd_ep_alloc(0x80, TUSB_XFER_CONTROL);
+
+  xfer_status[0][0].max_packet_size = CFG_TUD_ENDPOINT0_SIZE;
+  xfer_status[0][0].ep_idx = 0;
+
+  xfer_status[0][1].max_packet_size = CFG_TUD_ENDPOINT0_SIZE;
+  xfer_status[0][1].ep_idx = 0;
+
+  uint16_t pma_addr0 = dcd_pma_alloc(CFG_TUD_ENDPOINT0_SIZE, false);
+  uint16_t pma_addr1 = dcd_pma_alloc(CFG_TUD_ENDPOINT0_SIZE, false);
+
+  btable_set_addr(0, BTABLE_BUF_RX, pma_addr0);
+  btable_set_addr(0, BTABLE_BUF_TX, pma_addr1);
+
+  uint32_t ep_reg = ep_read(0) & ~USB_EPREG_MASK; // only get toggle bits
+  ep_reg |= USB_EP_CONTROL;
+  ep_change_status(&ep_reg, TUSB_DIR_IN, EP_STAT_NAK);
+  ep_change_status(&ep_reg, TUSB_DIR_OUT, EP_STAT_NAK);
+  // no need to explicitly set DTOG bits since we aren't masked DTOG bit
+
+  edpt0_prepare_setup(); // prepare for setup packet
+  ep_write(0, ep_reg, false);
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
   (void)rhport;
-  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc);
-  uint16_t pma_addr;
-  uint32_t wType;
-  
-  // Isochronous not supported (yet), and some other driver assumptions.
-  TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
-  TU_ASSERT(epnum < MAX_EP_COUNT);
+  uint8_t const ep_addr = desc_ep->bEndpointAddress;
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+  const uint16_t packet_size = tu_edpt_packet_size(desc_ep);
+  uint8_t const ep_idx = dcd_ep_alloc(ep_addr, desc_ep->bmAttributes.xfer);
+  TU_ASSERT(ep_idx < FSDEV_EP_COUNT);
+
+  uint32_t ep_reg = ep_read(ep_idx) & ~USB_EPREG_MASK;
+  ep_reg |= tu_edpt_number(ep_addr) | USB_EP_CTR_TX | USB_EP_CTR_RX;
 
   // Set type
-  switch(p_endpoint_desc->bmAttributes.xfer) {
-  case TUSB_XFER_CONTROL:
-    wType = USB_EP_CONTROL;
-    break;
-#if (0)
-  case TUSB_XFER_ISOCHRONOUS: // FIXME: Not yet supported
-    wType = USB_EP_ISOCHRONOUS;
-    break;
-#endif
+  switch (desc_ep->bmAttributes.xfer) {
+    case TUSB_XFER_BULK:
+      ep_reg |= USB_EP_BULK;
+      break;
+    case TUSB_XFER_INTERRUPT:
+      ep_reg |= USB_EP_INTERRUPT;
+      break;
 
-  case TUSB_XFER_BULK:
-    wType = USB_EP_CONTROL;
-    break;
-
-  case TUSB_XFER_INTERRUPT:
-    wType = USB_EP_INTERRUPT;
-    break;
-
-  default:
-    TU_ASSERT(false);
+    default:
+      // Note: ISO endpoint should use alloc / active functions
+      TU_ASSERT(false);
   }
 
-  pcd_set_eptype(USB, epnum, wType);
-  pcd_set_ep_address(USB, epnum, epnum);
-  // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
-  // or being double-buffered (bulk endpoints)
-  pcd_clear_ep_kind(USB,0);
+  /* Create a packet memory buffer area. */
+  uint16_t pma_addr = dcd_pma_alloc(packet_size, false);
+  btable_set_addr(ep_idx, dir == TUSB_DIR_IN ? BTABLE_BUF_TX : BTABLE_BUF_RX, pma_addr);
 
-  pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, epMaxPktSize);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
+  xfer->max_packet_size = packet_size;
+  xfer->ep_idx = ep_idx;
 
-  if(dir == TUSB_DIR_IN)
-  {
-    *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
-    pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize);
-    pcd_clear_tx_dtog(USB, epnum);
-    pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_NAK);
-  }
-  else
-  {
-    *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
-    pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize);
-    pcd_clear_rx_dtog(USB, epnum);
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
+  ep_change_status(&ep_reg, dir, EP_STAT_NAK);
+  ep_change_dtog(&ep_reg, dir, 0);
+
+  // reserve other direction toggle bits
+  if (dir == TUSB_DIR_IN) {
+    ep_reg &= ~(USB_EPRX_STAT | USB_EP_DTOG_RX);
+  } else {
+    ep_reg &= ~(USB_EPTX_STAT | USB_EP_DTOG_TX);
   }
 
-  xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize;
+  ep_write(ep_idx, ep_reg, true);
 
   return true;
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+void dcd_edpt_close_all(uint8_t rhport) {
+  dcd_int_disable(rhport);
+
+  for (uint32_t i = 1; i < FSDEV_EP_COUNT; i++) {
+    // Reset endpoint
+    ep_write(i, 0, false);
+    // Clear EP allocation status
+    ep_alloc_status[i].ep_num = 0xFF;
+    ep_alloc_status[i].ep_type = 0xFF;
+    ep_alloc_status[i].allocated[0] = false;
+    ep_alloc_status[i].allocated[1] = false;
+  }
+
+  dcd_int_enable(rhport);
+
+  // Reset PMA allocation
+  ep_buf_ptr = FSDEV_BTABLE_BASE + 8 * CFG_TUD_ENDPPOINT_MAX + 2 * CFG_TUD_ENDPOINT0_SIZE;
 }
 
-/**
- * Close an endpoint.
- * 
- * This function may be called with interrupts enabled or disabled.
- * 
- * This also clears transfers in progress, should there be any.
- */
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
   (void)rhport;
-  uint32_t const epnum = tu_edpt_number(ep_addr);
-  uint32_t const dir   = tu_edpt_dir(ep_addr);
-  
-  if(dir == TUSB_DIR_IN)
-  {
-    pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_DIS);
-  }
-  else
-  {
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
-  }
 
-  dcd_pma_free(ep_addr);
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+  uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
+
+  /* Create a packet memory buffer area. Enable double buffering for devices with 2048 bytes PMA,
+     for smaller devices double buffering occupy too much space. */
+#if FSDEV_PMA_SIZE > 1024u
+  uint32_t pma_addr = dcd_pma_alloc(largest_packet_size, true);
+  uint16_t pma_addr2 = pma_addr >> 16;
+#else
+  uint32_t pma_addr = dcd_pma_alloc(largest_packet_size, false);
+  uint16_t pma_addr2 = pma_addr;
+#endif
+
+  btable_set_addr(ep_idx, 0, pma_addr);
+  btable_set_addr(ep_idx, 1, pma_addr2);
+
+  xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, dir);
+  xfer->ep_idx = ep_idx;
+
+  return true;
+}
+
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
+  (void)rhport;
+  uint8_t const ep_addr = desc_ep->bEndpointAddress;
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+  xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, dir);
+
+  uint8_t const ep_idx = xfer->ep_idx;
+
+  xfer->max_packet_size = tu_edpt_packet_size(desc_ep);
+
+  uint32_t ep_reg = ep_read(ep_idx) & ~USB_EPREG_MASK;
+  ep_reg |= tu_edpt_number(ep_addr) | USB_EP_ISOCHRONOUS | USB_EP_CTR_TX | USB_EP_CTR_RX;
+  ep_change_status(&ep_reg, TUSB_DIR_IN, EP_STAT_DISABLED);
+  ep_change_status(&ep_reg, TUSB_DIR_OUT, EP_STAT_DISABLED);
+  ep_change_dtog(&ep_reg, dir, 0);
+  ep_change_dtog(&ep_reg, (tusb_dir_t)(1 - dir), 1);
+
+  ep_write(ep_idx, ep_reg, true);
+
+  return true;
 }
 
 // Currently, single-buffered, and only 64 bytes at a time (max)
+static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) {
+  uint16_t len = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size);
+  uint32_t ep_reg = ep_read(ep_ix) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR
 
-static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
-{
-  uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
+  bool const is_iso = ep_is_iso(ep_reg);
 
-  if(len > xfer->max_packet_size) // max packet size for FS transfer
-  {
-    len = xfer->max_packet_size;
+  uint8_t buf_id;
+  if (is_iso) {
+    buf_id = (ep_reg & USB_EP_DTOG_TX) ? 1 : 0;
+  } else {
+    buf_id = BTABLE_BUF_TX;
   }
-  uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB,ep_ix);
+  uint16_t addr_ptr = (uint16_t) btable_get_addr(ep_ix, buf_id);
 
-#if 0 // TODO support dcd_edpt_xfer_fifo API
-  if (xfer->ff)
-  {
-    dcd_write_packet_memory_ff(xfer->ff, oldAddr, len);
+  if (xfer->ff) {
+    dcd_write_packet_memory_ff(xfer->ff, addr_ptr, len);
+  } else {
+    dcd_write_packet_memory(addr_ptr, &(xfer->buffer[xfer->queued_len]), len);
   }
-  else
-#endif
-  {
-    dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len);
-  }
-  xfer->queued_len = (uint16_t)(xfer->queued_len + len);
+  xfer->queued_len += len;
 
-  pcd_set_ep_tx_cnt(USB,ep_ix,len);
-  pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
+  btable_set_count(ep_ix, buf_id, len);
+  ep_change_status(&ep_reg, TUSB_DIR_IN, EP_STAT_VALID);
+
+  if (is_iso) {
+    xfer->iso_in_sending = true;
+  }
+  ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(TUSB_DIR_IN); // only change TX Status, reserve other toggle bits
+  ep_write(ep_ix, ep_reg, true);
 }
 
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, tusb_dir_t dir) {
   (void) rhport;
 
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
+  uint8_t const ep_idx = xfer->ep_idx;
 
-  xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
+  if (dir == TUSB_DIR_IN) {
+    dcd_transmit_packet(xfer, ep_idx);
+  } else {
+    uint32_t ep_reg = ep_read(ep_idx) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR
+    ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir);
+
+    uint16_t cnt = tu_min16(xfer->total_len, xfer->max_packet_size);
+
+    if (ep_is_iso(ep_reg)) {
+      btable_set_rx_bufsize(ep_idx, 0, cnt);
+      btable_set_rx_bufsize(ep_idx, 1, cnt);
+    } else {
+      btable_set_rx_bufsize(ep_idx, BTABLE_BUF_RX, cnt);
+    }
+
+    ep_change_status(&ep_reg, dir, EP_STAT_VALID);
+    ep_write(ep_idx, ep_reg, true);
+  }
+
+  return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) {
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
 
   xfer->buffer = buffer;
-  // xfer->ff     = NULL; // TODO support dcd_edpt_xfer_fifo API
+  xfer->ff = NULL;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
 
-  if ( dir == TUSB_DIR_OUT )
-  {
-    // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
-    // buffer for the control endpoint.
-    if (epnum == 0 && buffer == NULL)
-    {
-        xfer->buffer = (uint8_t*)_setup_packet;
-    }
-    if(total_bytes > xfer->max_packet_size)
-    {
-      pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size);
-    } else {
-      pcd_set_ep_rx_cnt(USB,epnum,total_bytes);
-    }
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID);
-  }
-  else // IN
-  {
-    dcd_transmit_packet(xfer,epnum);
-  }
-  return true;
+  return edpt_xfer(rhport, ep_num, dir);
 }
 
-#if 0 // TODO support dcd_edpt_xfer_fifo API
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
-  (void) rhport;
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) {
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
 
   xfer->buffer = NULL;
-  // xfer->ff     = ff; // TODO support dcd_edpt_xfer_fifo API
+  xfer->ff = ff;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
 
-  if ( dir == TUSB_DIR_OUT )
-  {
-    if(total_bytes > xfer->max_packet_size)
-    {
-      pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size);
-    } else {
-      pcd_set_ep_rx_cnt(USB,epnum,total_bytes);
+  return edpt_xfer(rhport, ep_num, dir);
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+  (void)rhport;
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
+  uint8_t const ep_idx = xfer->ep_idx;
+
+  uint32_t ep_reg = ep_read(ep_idx) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR bits
+  ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir);
+  ep_change_status(&ep_reg, dir, EP_STAT_STALL);
+
+  ep_write(ep_idx, ep_reg, true);
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+  (void)rhport;
+
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
+  uint8_t const ep_idx = xfer->ep_idx;
+
+  uint32_t ep_reg = ep_read(ep_idx) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR bits
+  ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir) | EP_DTOG_MASK(dir);
+
+  if (!ep_is_iso(ep_reg)) {
+    ep_change_status(&ep_reg, dir, EP_STAT_NAK);
+  }
+  ep_change_dtog(&ep_reg, dir, 0); // Reset to DATA0
+  ep_write(ep_idx, ep_reg, true);
+}
+
+//--------------------------------------------------------------------+
+// PMA read/write
+//--------------------------------------------------------------------+
+
+// Write to packet memory area (PMA) from user memory
+// - Packet memory must be either strictly 16-bit or 32-bit depending on FSDEV_BUS_32BIT
+// - Uses unaligned for RAM (since M0 cannot access unaligned address)
+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t nbytes) {
+  if (nbytes == 0) return true;
+  uint32_t n_write = nbytes / FSDEV_BUS_SIZE;
+
+  fsdev_pma_buf_t* pma_buf = PMA_BUF_AT(dst);
+  const uint8_t *src8 = src;
+
+  while (n_write--) {
+    pma_buf->value = fsdevbus_unaligned_read(src8);
+    src8 += FSDEV_BUS_SIZE;
+    pma_buf++;
+  }
+
+  // odd bytes e.g 1 for 16-bit or 1-3 for 32-bit
+  uint16_t odd = nbytes & (FSDEV_BUS_SIZE - 1);
+  if (odd) {
+    fsdev_bus_t temp = 0;
+    for(uint16_t i = 0; i < odd; i++) {
+      temp |= *src8++ << (i * 8);
     }
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID);
+    pma_buf->value = temp;
   }
-  else // IN
-  {
-    dcd_transmit_packet(xfer,epnum);
-  }
-  return true;
-}
-#endif
 
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void)rhport;
-
-  if (ep_addr & 0x80)
-  { // IN
-    pcd_set_ep_tx_status(USB, ep_addr & 0x7F, USB_EP_TX_STALL);
-  }
-  else
-  { // OUT
-    pcd_set_ep_rx_status(USB, ep_addr, USB_EP_RX_STALL);
-  }
-}
-
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void)rhport;
-
-  if (ep_addr & 0x80)
-  { // IN
-    ep_addr &= 0x7F;
-
-    pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK);
-
-    /* Reset to DATA0 if clearing stall condition. */
-    pcd_clear_tx_dtog(USB,ep_addr);
-  }
-  else
-  { // OUT
-    /* Reset to DATA0 if clearing stall condition. */
-    pcd_clear_rx_dtog(USB,ep_addr);
-
-    pcd_set_ep_rx_status(USB,ep_addr, USB_EP_RX_NAK);
-  }
-}
-
-// Packet buffer access can only be 8- or 16-bit.
-/**
-  * @brief Copy a buffer from user memory area to packet memory area (PMA).
-  *        This uses byte-access for user memory (so support non-aligned buffers)
-  *        and 16-bit access for packet memory.
-  * @param   dst, byte address in PMA; must be 16-bit aligned
-  * @param   src pointer to user memory area.
-  * @param   wPMABufAddr address into PMA.
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
-static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
-{
-  uint32_t n =  ((uint32_t)wNBytes + 1U) >> 1U;
-  uint32_t i;
-  uint16_t temp1, temp2;
-  const uint8_t * srcVal;
-
-  // The GCC optimizer will combine access to 32-bit sizes if we let it. Force
-  // it volatile so that it won't do that.
-  __IO uint16_t *pdwVal;
-
-  srcVal = src;
-  pdwVal = &pma[PMA_STRIDE*(dst>>1)];
-
-  for (i = n; i != 0; i--)
-  {
-    temp1 = (uint16_t) *srcVal;
-    srcVal++;
-    temp2 = temp1 | ((uint16_t)((uint16_t) ((*srcVal) << 8U))) ;
-    *pdwVal = temp2;
-    pdwVal += PMA_STRIDE;
-    srcVal++;
-  }
   return true;
 }
 
-#if 0 // TODO support dcd_edpt_xfer_fifo API
-/**
-  * @brief Copy from FIFO to packet memory area (PMA).
-  *        Uses byte-access of system memory and 16-bit access of packet memory
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
+// Read from packet memory area (PMA) to user memory.
+// - Packet memory must be either strictly 16-bit or 32-bit depending on FSDEV_BUS_32BIT
+// - Uses unaligned for RAM (since M0 cannot access unaligned address)
+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t nbytes) {
+  if (nbytes == 0) return true;
+  uint32_t n_read = nbytes / FSDEV_BUS_SIZE;
 
-// THIS FUNCTION IS UNTESTED
+  fsdev_pma_buf_t* pma_buf = PMA_BUF_AT(src);
+  uint8_t *dst8 = (uint8_t *)dst;
+
+  while (n_read--) {
+    fsdevbus_unaligned_write(dst8, (fsdev_bus_t ) pma_buf->value);
+    dst8 += FSDEV_BUS_SIZE;
+    pma_buf++;
+  }
+
+  // odd bytes e.g 1 for 16-bit or 1-3 for 32-bit
+  uint16_t odd = nbytes & (FSDEV_BUS_SIZE - 1);
+  if (odd) {
+    fsdev_bus_t temp = pma_buf->value;
+    while (odd--) {
+      *dst8++ = (uint8_t) (temp & 0xfful);
+      temp >>= 8;
+    }
+  }
+
+  return true;
+}
+
+// Write to PMA from FIFO
+static bool dcd_write_packet_memory_ff(tu_fifo_t *ff, uint16_t dst, uint16_t wNBytes) {
+  if (wNBytes == 0) return true;
 
-static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes)
-{
   // Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
-  // Check for first linear part
-  void * src;
-  uint16_t len = tu_fifo_get_linear_read_info(ff, 0, &src, wNBytes);  // We want to read from the FIFO        - THIS FUNCTION CHANGED!!!
-  TU_VERIFY(len && dcd_write_packet_memory(dst, src, len));           // and write it into the PMA
-  tu_fifo_advance_read_pointer(ff, len);
+  tu_fifo_buffer_info_t info;
+  tu_fifo_get_read_info(ff, &info);
 
-  // Check for wrapped part
-  if (len < wNBytes)
-  {
-    // Get remaining wrapped length
-    uint16_t len2 = tu_fifo_get_linear_read_info(ff, 0, &src, wNBytes - len);
-    TU_VERIFY(len2);
+  uint16_t cnt_lin = tu_min16(wNBytes, info.len_lin);
+  uint16_t cnt_wrap = tu_min16(wNBytes - cnt_lin, info.len_wrap);
+  uint16_t const cnt_total = cnt_lin + cnt_wrap;
 
-    // Update destination pointer
-    dst += len;
+  // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
+  // last lin byte will be combined with wrapped part To ensure PMA is always access aligned
+  uint16_t lin_even = cnt_lin & ~(FSDEV_BUS_SIZE - 1);
+  uint16_t lin_odd = cnt_lin & (FSDEV_BUS_SIZE - 1);
+  uint8_t const *src8 = (uint8_t const*) info.ptr_lin;
 
-    // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split
-    if (len % 2)    // If len is uneven there is a byte left to copy
-    {
-      // Since PMA can accessed only 16 bit-wise we copy the last byte again
-      tu_fifo_backward_read_pointer(ff, 1);                 // Move one byte back and copy two bytes for the PMA
-      tu_fifo_read_n(ff, (void *) &pma[PMA_STRIDE*(dst>>1)], 2);     // Since EP FIFOs must be of item size 1 this is safe to do
-      dst++;
-      len2--;
+  // write even linear part
+  dcd_write_packet_memory(dst, src8, lin_even);
+  dst += lin_even;
+  src8 += lin_even;
+
+  if (lin_odd == 0) {
+    src8 = (uint8_t const*) info.ptr_wrap;
+  } else {
+    // Combine last linear bytes + first wrapped bytes to form fsdev bus width data
+    fsdev_bus_t temp = 0;
+    uint16_t i;
+    for(i = 0; i < lin_odd; i++) {
+      temp |= *src8++ << (i * 8);
     }
 
-    TU_VERIFY(dcd_write_packet_memory(dst, src, len2));
-    tu_fifo_advance_write_pointer(ff, len2);
+    src8 = (uint8_t const*) info.ptr_wrap;
+    for(; i < FSDEV_BUS_SIZE && cnt_wrap > 0; i++, cnt_wrap--) {
+      temp |= *src8++ << (i * 8);
+    }
+
+    dcd_write_packet_memory(dst, &temp, FSDEV_BUS_SIZE);
+    dst += FSDEV_BUS_SIZE;
   }
 
-  return true;
-}
-#endif
+  // write the rest of the wrapped part
+  dcd_write_packet_memory(dst, src8, cnt_wrap);
 
-/**
-  * @brief Copy a buffer from packet memory area (PMA) to user memory area.
-  *        Uses byte-access of system memory and 16-bit access of packet memory
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
-static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
-{
-  uint32_t n = (uint32_t)wNBytes >> 1U;
-  uint32_t i;
-  // The GCC optimizer will combine access to 32-bit sizes if we let it. Force
-  // it volatile so that it won't do that.
-  __IO const uint16_t *pdwVal;
-  uint32_t temp;
-
-  pdwVal = &pma[PMA_STRIDE*(src>>1)];
-  uint8_t *dstVal = (uint8_t*)dst;
-
-  for (i = n; i != 0U; i--)
-  {
-    temp = *pdwVal;
-    pdwVal += PMA_STRIDE;
-    *dstVal++ = ((temp >> 0) & 0xFF);
-    *dstVal++ = ((temp >> 8) & 0xFF);
-  }
-
-  if (wNBytes % 2)
-  {
-    temp = *pdwVal;
-    pdwVal += PMA_STRIDE;
-    *dstVal++ = ((temp >> 0) & 0xFF);
-  }
+  tu_fifo_advance_read_pointer(ff, cnt_total);
   return true;
 }
 
-#if 0 // TODO support dcd_edpt_xfer_fifo API
-/**
-  * @brief Copy a buffer from user packet memory area (PMA) to FIFO.
-  *        Uses byte-access of system memory and 16-bit access of packet memory
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
+// Read from PMA to FIFO
+static bool dcd_read_packet_memory_ff(tu_fifo_t *ff, uint16_t src, uint16_t wNBytes) {
+  if (wNBytes == 0) return true;
 
-// THIS FUNCTION IS UNTESTED
-
-static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes)
-{
   // Since we copy into a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
   // Check for first linear part
-  void * dst;
-  uint16_t len = tu_fifo_get_linear_write_info(ff, 0, &dst, wNBytes);           // THIS FUNCTION CHANGED!!!!
-  TU_VERIFY(len && dcd_read_packet_memory(dst, src, len));
-  tu_fifo_advance_write_pointer(ff, len);
+  tu_fifo_buffer_info_t info;
+  tu_fifo_get_write_info(ff, &info); // We want to read from the FIFO
 
-  // Check for wrapped part
-  if (len < wNBytes)
-  {
-    // Get remaining wrapped length
-    uint16_t len2 = tu_fifo_get_linear_write_info(ff, 0, &dst, wNBytes - len);
-    TU_VERIFY(len2);
+  uint16_t cnt_lin = tu_min16(wNBytes, info.len_lin);
+  uint16_t cnt_wrap = tu_min16(wNBytes - cnt_lin, info.len_wrap);
+  uint16_t cnt_total = cnt_lin + cnt_wrap;
 
-    // Update source pointer
-    src += len;
+  // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
+  // last lin byte will be combined with wrapped part To ensure PMA is always access aligned
 
-    // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split
-    if (len % 2)    // If len is uneven there is a byte left to copy
-    {
-      uint32_t temp = pma[PMA_STRIDE*(src>>1)];
-      *((uint8_t *)dst++) = ((temp >> 8) & 0xFF);
-      src++;
-      len2--;
+  uint16_t lin_even = cnt_lin & ~(FSDEV_BUS_SIZE - 1);
+  uint16_t lin_odd = cnt_lin & (FSDEV_BUS_SIZE - 1);
+  uint8_t *dst8 = (uint8_t *) info.ptr_lin;
+
+  // read even linear part
+  dcd_read_packet_memory(dst8, src, lin_even);
+  dst8 += lin_even;
+  src += lin_even;
+
+  if (lin_odd == 0) {
+    dst8 = (uint8_t *) info.ptr_wrap;
+  } else {
+    // Combine last linear bytes + first wrapped bytes to form fsdev bus width data
+    fsdev_bus_t temp;
+    dcd_read_packet_memory(&temp, src, FSDEV_BUS_SIZE);
+    src += FSDEV_BUS_SIZE;
+
+    uint16_t i;
+    for (i = 0; i < lin_odd; i++) {
+      *dst8++ = (uint8_t) (temp & 0xfful);
+      temp >>= 8;
     }
 
-    TU_VERIFY(dcd_read_packet_memory(dst, src, len2));
-    tu_fifo_advance_write_pointer(ff, len2);
+    dst8 = (uint8_t *) info.ptr_wrap;
+    for (; i < FSDEV_BUS_SIZE && cnt_wrap > 0; i++, cnt_wrap--) {
+      *dst8++ = (uint8_t) (temp & 0xfful);
+      temp >>= 8;
+    }
   }
 
+  // read the rest of the wrapped part
+  dcd_read_packet_memory(dst8, src, cnt_wrap);
+
+  tu_fifo_advance_write_pointer(ff, cnt_total);
   return true;
 }
 
 #endif
-
-#endif
-
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
deleted file mode 100644
index 920d12c1b..000000000
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ /dev/null
@@ -1,426 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    dcd_stm32f0_pvt_st.h
-  * @brief   DCD utilities from ST code
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  * <h2><center>&copy; parts COPYRIGHT(c) N Conrad</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  **********/
-
-// This file contains source copied from ST's HAL, and thus should have their copyright statement.
-
-// PMA_LENGTH is PMA buffer size in bytes.
-// On 512-byte devices, access with a stride of two words (use every other 16-bit address)
-// On 1024-byte devices, access with a stride of one word (use every 16-bit address)
-
-#ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
-#define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
-
-#if defined(STM32F042x6) || \
-    defined(STM32F070x6) || defined(STM32F070xB) || \
-    defined(STM32F072xB) || \
-    defined(STM32F078xx)
-  #include "stm32f0xx.h"
-  #define PMA_LENGTH (1024u)
-  // F0x2 models are crystal-less
-  // All have internal D+ pull-up
-  // 070RB:    2 x 16 bits/word memory     LPM Support, BCD Support
-  // PMA dedicated to USB (no sharing with CAN)
-
-#elif defined(STM32F1_FSDEV)
-  #include "stm32f1xx.h"
-  #define PMA_LENGTH (512u)
-  // NO internal Pull-ups
-  //         *B, and *C:    2 x 16 bits/word
-
-  // F1 names this differently from the rest
-  #define USB_CNTR_LPMODE   USB_CNTR_LP_MODE
-
-#elif defined(STM32F302xB) || defined(STM32F302xC) || \
-      defined(STM32F303xB) || defined(STM32F303xC) || \
-      defined(STM32F373xC)
-  #include "stm32f3xx.h"
-  #define PMA_LENGTH (512u)
-  // NO internal Pull-ups
-  //         *B, and *C:    1 x 16 bits/word
-  // PMA dedicated to USB (no sharing with CAN)
-
-#elif defined(STM32F302x6) || defined(STM32F302x8) || \
-      defined(STM32F302xD) || defined(STM32F302xE) || \
-      defined(STM32F303xD) || defined(STM32F303xE)
-  #include "stm32f3xx.h"
-  #define PMA_LENGTH (1024u)
-  // NO internal Pull-ups
-  // *6, *8, *D, and *E:    2 x 16 bits/word     LPM Support
-  // When CAN clock is enabled, USB can use first 768 bytes ONLY.
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
-  #include "stm32l0xx.h"
-  #define PMA_LENGTH (1024u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
-  #include "stm32l1xx.h"
-  #define PMA_LENGTH (512u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
-  #include "stm32g4xx.h"
-  #define PMA_LENGTH (1024u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
-  #include "stm32wbxx.h"
-  #define PMA_LENGTH (1024u)
-  /* ST provided header has incorrect value */
-  #undef USB_PMAADDR
-  #define USB_PMAADDR USB1_PMAADDR
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
-  #include "stm32l4xx.h"
-  #define PMA_LENGTH (1024u)
-
-#else
-  #error You are using an untested or unimplemented STM32 variant. Please update the driver.
-  // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
-#endif
-
-// For purposes of accessing the packet
-#if ((PMA_LENGTH) == 512u)
-  #define PMA_STRIDE  (2u)
-#elif ((PMA_LENGTH) == 1024u)
-  #define PMA_STRIDE  (1u)
-#endif
-
-// And for type-safety create a new macro for the volatile address of PMAADDR
-// The compiler should warn us if we cast it to a non-volatile type?
-// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
-static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
-
-// prototypes
-static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
-static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
-static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue);
-
-
-/* SetENDPOINT */
-static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue)
-{
-  __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpNum*2u);
-  *reg = (uint16_t)wRegValue;
-}
-
-/* GetENDPOINT */
-static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) {
-  __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpNum*2u);
-  return *reg;
-}
-
-static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= (uint32_t)USB_EP_T_MASK;
-  regVal |= wType;
-  regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high
-  pcd_set_endpoint(USBx, bEpNum, regVal);
-}
-
-static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= USB_EP_T_FIELD;
-  return regVal;
-}
-/**
-  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= USB_EPREG_MASK;
-  regVal &= ~USB_EP_CTR_RX;
-  regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0)
-  pcd_set_endpoint(USBx, bEpNum, regVal);
-}
-static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= USB_EPREG_MASK;
-  regVal &= ~USB_EP_CTR_TX;
-  regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0)
-  pcd_set_endpoint(USBx, bEpNum,regVal);
-}
-/**
-  * @brief  gets counter of the tx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval Counter value
-  */
-static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpNum);
-  return *regPtr & 0x3ffU;
-}
-
-static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpNum);
-  return *regPtr & 0x3ffU;
-}
-
-/**
-  * @brief  Sets counter of rx buffer with no. of blocks.
-  * @param  dwReg Register
-  * @param  wCount Counter.
-  * @param  wNBlocks no. of Blocks.
-  * @retval None
-  */
-
-static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount)  {
-  uint32_t wNBlocks;
-  if(wCount > 62u)
-  {
-    wNBlocks = wCount >> 5u;
-    if((wCount & 0x1fU) == 0u)
-    {
-      wNBlocks--;
-    }
-    wNBlocks = wNBlocks << 10u;
-    wNBlocks |= 0x8000u; // Mark block size as 32byte
-    *pdwReg = (uint16_t)wNBlocks;
-  }
-  else
-  {
-    wNBlocks = wCount >> 1u;
-    if((wCount & 0x1U) != 0u)
-    {
-      wNBlocks++;
-    }
-    *pdwReg = (uint16_t)((wNBlocks) << 10u);
-  }
-}
-
-
-/**
-  * @brief  Sets address in an endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  bAddr Address.
-  * @retval None
-  */
-static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t bAddr)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= USB_EPREG_MASK;
-  regVal |= bAddr;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum,regVal);
-}
-
-static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
-{
-  size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
-  total_word_offset *= PMA_STRIDE;
-  return &(pma[total_word_offset]);
-}
-
-// Pointers to the PMA table entries (using the ARM address space)
-static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 0u);
-}
-static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 1u);
-}
-
-static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  return  pcd_btable_word_ptr(USBx,(bEpNum)*4u + 2u);
-}
-
-static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 3u);
-}
-
-static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
-{
-  *pcd_ep_tx_cnt_ptr(USBx, bEpNum) = (uint16_t)wCount;
-}
-
-static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
-{
-  __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum));
-  pcd_set_ep_cnt_rx_reg(pdwReg, wCount);
-}
-
-/**
-  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wState new state
-  * @retval None
-  */
-static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wState)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= USB_EPTX_DTOGMASK;
-
-  /* toggle first bit ? */
-  if((USB_EPTX_DTOG1 & (wState))!= 0U)
-  {
-    regVal ^= USB_EPTX_DTOG1;
-  }
-  /* toggle second bit ?  */
-  if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)
-  {
-    regVal ^= USB_EPTX_DTOG2;
-  }
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
-} /* pcd_set_ep_tx_status */
-
-/**
-  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wState new state
-  * @retval None
-  */
-
-static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wState)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= USB_EPRX_DTOGMASK;
-
-  /* toggle first bit ? */
-  if((USB_EPRX_DTOG1 & wState)!= 0U)
-  {
-    regVal ^= USB_EPRX_DTOG1;
-  }
-  /* toggle second bit ? */
-  if((USB_EPRX_DTOG2 & wState)!= 0U)
-  {
-    regVal ^= USB_EPRX_DTOG2;
-  }
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
-} /* pcd_set_ep_rx_status */
-
-static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  return (regVal & USB_EPRX_STAT) >> (12u);
-} /* pcd_get_ep_rx_status */
-
-
-/**
-  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= USB_EPREG_MASK;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
-}
-
-static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= USB_EPREG_MASK;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
-}
-
-/**
-  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-
-static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  if((regVal & USB_EP_DTOG_RX) != 0)
-  {
-    pcd_rx_dtog(USBx,bEpNum);
-  }
-}
-
-static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  if((regVal & USB_EP_DTOG_TX) != 0)
-  {
-    pcd_tx_dtog(USBx,bEpNum);
-  }
-}
-
-/**
-  * @brief  set & clear EP_KIND bit.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-
-static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal |= USB_EP_KIND;
-  regVal &= USB_EPREG_MASK;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
-}
-static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum)
-{
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
-  regVal &= USB_EPKIND_MASK;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
-}
-
-// This checks if the device has "LPM"
-#if defined(USB_ISTR_L1REQ)
-#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ)
-#else
-#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U)
-#endif
-
-#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \
-     USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
-
-// Number of endpoints in hardware
-#define STFSDEV_EP_COUNT (8u)
-
-#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */
diff --git a/src/portable/st/stm32_fsdev/fsdev_ch32.h b/src/portable/st/stm32_fsdev/fsdev_ch32.h
new file mode 100644
index 000000000..518197c47
--- /dev/null
+++ b/src/portable/st/stm32_fsdev/fsdev_ch32.h
@@ -0,0 +1,206 @@
+/*
+* The MIT License (MIT)
+ *
+ * Copyright (c) 2024, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+/** <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  */
+
+#ifndef TUSB_FSDEV_CH32_H
+#define TUSB_FSDEV_CH32_H
+
+#include "common/tusb_compiler.h"
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_CH32F20X
+  #include <ch32f20x.h>
+#elif CFG_TUSB_MCU == OPT_MCU_CH32V20X
+  #include <ch32v20x.h>
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#define FSDEV_PMA_SIZE (512u)
+#define FSDEV_REG_BASE  (APB1PERIPH_BASE + 0x00005C00UL)
+#define FSDEV_PMA_BASE  (APB1PERIPH_BASE + 0x00006000UL)
+
+/****************************  ISTR interrupt events  *************************/
+#define USB_ISTR_CTR                         ((uint16_t)0x8000U)               /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR                      ((uint16_t)0x4000U)               /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR                         ((uint16_t)0x2000U)               /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP                        ((uint16_t)0x1000U)               /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP                        ((uint16_t)0x0800U)               /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET                       ((uint16_t)0x0400U)               /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF                         ((uint16_t)0x0200U)               /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF                        ((uint16_t)0x0100U)               /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_DIR                         ((uint16_t)0x0010U)               /*!< DIRection of transaction (read-only bit)  */
+#define USB_ISTR_EP_ID                       ((uint16_t)0x000FU)               /*!< EndPoint IDentifier (read-only bit)  */
+
+/* Legacy defines */
+#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
+
+#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
+#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
+#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
+#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
+
+/* Legacy defines */
+#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
+
+/*************************  CNTR control register bits definitions  ***********/
+#define USB_CNTR_CTRM                        ((uint16_t)0x8000U)               /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVR                      ((uint16_t)0x4000U)               /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM                        ((uint16_t)0x2000U)               /*!< ERRor Mask */
+#define USB_CNTR_WKUPM                       ((uint16_t)0x1000U)               /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM                       ((uint16_t)0x0800U)               /*!< SUSPend Mask */
+#define USB_CNTR_RESETM                      ((uint16_t)0x0400U)               /*!< RESET Mask   */
+#define USB_CNTR_SOFM                        ((uint16_t)0x0200U)               /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM                       ((uint16_t)0x0100U)               /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_RESUME                      ((uint16_t)0x0010U)               /*!< RESUME request */
+#define USB_CNTR_FSUSP                       ((uint16_t)0x0008U)               /*!< Force SUSPend */
+#define USB_CNTR_LPMODE                      ((uint16_t)0x0004U)               /*!< Low-power MODE */
+#define USB_CNTR_PDWN                        ((uint16_t)0x0002U)               /*!< Power DoWN */
+#define USB_CNTR_FRES                        ((uint16_t)0x0001U)               /*!< Force USB RESet */
+
+/* Legacy defines */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
+#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
+
+/********************  FNR Frame Number Register bit definitions   ************/
+#define USB_FNR_RXDP                         ((uint16_t)0x8000U)               /*!< status of D+ data line */
+#define USB_FNR_RXDM                         ((uint16_t)0x4000U)               /*!< status of D- data line */
+#define USB_FNR_LCK                          ((uint16_t)0x2000U)               /*!< LoCKed */
+#define USB_FNR_LSOF                         ((uint16_t)0x1800U)               /*!< Lost SOF */
+#define USB_FNR_FN                           ((uint16_t)0x07FFU)               /*!< Frame Number */
+
+/********************  DADDR Device ADDRess bit definitions    ****************/
+#define USB_DADDR_EF                         ((uint8_t)0x80U)                  /*!< USB device address Enable Function */
+#define USB_DADDR_ADD                        ((uint8_t)0x7FU)                  /*!< USB device address */
+
+/******************************  Endpoint register    *************************/
+#define USB_EP0R                             USB_BASE                    /*!< endpoint 0 register address */
+#define USB_EP1R                             (USB_BASE + 0x04U)           /*!< endpoint 1 register address */
+#define USB_EP2R                             (USB_BASE + 0x08U)           /*!< endpoint 2 register address */
+#define USB_EP3R                             (USB_BASE + 0x0CU)           /*!< endpoint 3 register address */
+#define USB_EP4R                             (USB_BASE + 0x10U)           /*!< endpoint 4 register address */
+#define USB_EP5R                             (USB_BASE + 0x14U)           /*!< endpoint 5 register address */
+#define USB_EP6R                             (USB_BASE + 0x18U)           /*!< endpoint 6 register address */
+#define USB_EP7R                             (USB_BASE + 0x1CU)           /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX                        ((uint16_t)0x8000U)               /*!<  EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX                       ((uint16_t)0x4000U)               /*!<  EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT                        ((uint16_t)0x3000U)               /*!<  EndPoint RX STATus bit field */
+#define USB_EP_SETUP                         ((uint16_t)0x0800U)               /*!<  EndPoint SETUP */
+#define USB_EP_T_FIELD                       ((uint16_t)0x0600U)               /*!<  EndPoint TYPE */
+#define USB_EP_KIND                          ((uint16_t)0x0100U)               /*!<  EndPoint KIND */
+#define USB_EP_CTR_TX                        ((uint16_t)0x0080U)               /*!<  EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX                       ((uint16_t)0x0040U)               /*!<  EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT                        ((uint16_t)0x0030U)               /*!<  EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD                     ((uint16_t)0x000FU)               /*!<  EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK                     ((uint16_t)0x0600U)               /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK                          ((uint16_t)0x0000U)               /*!< EndPoint BULK */
+#define USB_EP_CONTROL                       ((uint16_t)0x0200U)               /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS                   ((uint16_t)0x0400U)               /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT                     ((uint16_t)0x0600U)               /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK                      ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
+                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS                        ((uint16_t)0x0000U)               /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL                      ((uint16_t)0x0010U)               /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK                        ((uint16_t)0x0020U)               /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID                      ((uint16_t)0x0030U)               /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1                       ((uint16_t)0x0010U)               /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2                       ((uint16_t)0x0020U)               /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
+                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS                        ((uint16_t)0x0000U)               /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL                      ((uint16_t)0x1000U)               /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK                        ((uint16_t)0x2000U)               /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID                      ((uint16_t)0x3000U)               /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1                       ((uint16_t)0x1000U)               /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2                       ((uint16_t)0x2000U)               /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_MCU == OPT_MCU_CH32V20X
+static const IRQn_Type fsdev_irq[] = {
+  USB_HP_CAN1_TX_IRQn,
+  USB_LP_CAN1_RX0_IRQn,
+  USBWakeUp_IRQn
+};
+enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
+#else
+  #error "Unsupported MCU"
+#endif
+
+void dcd_int_enable(uint8_t rhport) {
+  (void)rhport;
+  for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
+    NVIC_EnableIRQ(fsdev_irq[i]);
+  }
+}
+
+void dcd_int_disable(uint8_t rhport) {
+  (void)rhport;
+  for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
+    NVIC_DisableIRQ(fsdev_irq[i]);
+  }
+}
+
+void dcd_disconnect(uint8_t rhport) {
+  (void) rhport;
+  EXTEN->EXTEN_CTR &= ~EXTEN_USBD_PU_EN;
+}
+
+void dcd_connect(uint8_t rhport) {
+  (void) rhport;
+  EXTEN->EXTEN_CTR |= EXTEN_USBD_PU_EN;
+}
+
+#endif
diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h
new file mode 100644
index 000000000..ccf31e035
--- /dev/null
+++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h
@@ -0,0 +1,372 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright(c) N Conrad
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_FSDEV_STM32_H
+#define TUSB_FSDEV_STM32_H
+
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0
+  #include "stm32f0xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+  #define FSDEV_REG_BASE USB_BASE
+  // F0x2 models are crystal-less
+  // All have internal D+ pull-up
+  // 070RB:    2 x 16 bits/word memory     LPM Support, BCD Support
+  // PMA dedicated to USB (no sharing with CAN)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
+  #include "stm32f1xx.h"
+  #define FSDEV_PMA_SIZE (512u)
+  // NO internal Pull-ups
+  //         *B, and *C:    2 x 16 bits/word
+
+  // F1 names this differently from the rest
+  #define USB_CNTR_LPMODE   USB_CNTR_LP_MODE
+
+#elif defined(STM32F302xB) || defined(STM32F302xC) || \
+      defined(STM32F303xB) || defined(STM32F303xC) || \
+      defined(STM32F373xC)
+  #include "stm32f3xx.h"
+  #define FSDEV_PMA_SIZE (512u)
+  // NO internal Pull-ups
+  //         *B, and *C:    1 x 16 bits/word
+  // PMA dedicated to USB (no sharing with CAN)
+
+#elif defined(STM32F302x6) || defined(STM32F302x8) || \
+      defined(STM32F302xD) || defined(STM32F302xE) || \
+      defined(STM32F303xD) || defined(STM32F303xE)
+  #include "stm32f3xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+  // NO internal Pull-ups
+  // *6, *8, *D, and *E:    2 x 16 bits/word     LPM Support
+  // When CAN clock is enabled, USB can use first 768 bytes ONLY.
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
+  #include "stm32l0xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
+  #include "stm32l1xx.h"
+  #define FSDEV_PMA_SIZE (512u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
+  #include "stm32g4xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+  #include "stm32g0xx.h"
+  #define FSDEV_PMA_SIZE (2048u)
+  #define USB USB_DRD_FS
+
+  #define USB_EP_CTR_RX USB_EP_VTRX
+  #define USB_EP_CTR_TX USB_EP_VTTX
+  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT USB_CH_RX_VALID
+  #define USB_EPKIND_MASK USB_EP_KIND_MASK
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32C0
+  #include "stm32c0xx.h"
+  #define FSDEV_PMA_SIZE (2048u)
+  #define USB USB_DRD_FS
+  #define USB_EP_CTR_RX USB_CHEP_VTRX
+  #define USB_EP_CTR_TX USB_CHEP_VTTX
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
+  #include "stm32h5xx.h"
+  #define FSDEV_PMA_SIZE (2048u)
+  #define USB USB_DRD_FS
+
+  #define USB_EP_CTR_RX USB_EP_VTRX
+  #define USB_EP_CTR_TX USB_EP_VTTX
+  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT USB_CH_RX_VALID
+  #define USB_EPKIND_MASK USB_EP_KIND_MASK
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+  #include "stm32wbxx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+  /* ST provided header has incorrect value of USB_PMAADDR */
+  #define FSDEV_PMA_BASE USB1_PMAADDR
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
+  #include "stm32l4xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
+  #include "stm32l5xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+
+  #ifndef USB_PMAADDR
+    #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
+  #endif
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
+  #include "stm32u5xx.h"
+  #define FSDEV_PMA_SIZE (2048u)
+  #define USB USB_DRD_FS
+
+  #define USB_EP_CTR_RX USB_EP_VTRX
+  #define USB_EP_CTR_TX USB_EP_VTTX
+  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT USB_CH_RX_VALID
+  #define USB_EPKIND_MASK USB_EP_KIND_MASK
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32U0
+  #include "stm32u0xx.h"
+  #define FSDEV_PMA_SIZE (2048u)
+  #define USB USB_DRD_FS
+
+  #define USB_EP_CTR_RX USB_EP_VTRX
+  #define USB_EP_CTR_TX USB_EP_VTTX
+  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT USB_CH_RX_VALID
+  #define USB_EPKIND_MASK USB_EP_KIND_MASK
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#else
+  #error You are using an untested or unimplemented STM32 variant. Please update the driver.
+  // This includes U0
+#endif
+
+//--------------------------------------------------------------------+
+// Register and PMA Base Address
+//--------------------------------------------------------------------+
+#ifndef FSDEV_REG_BASE
+#if defined(USB_BASE)
+  #define FSDEV_REG_BASE USB_BASE
+#elif defined(USB_DRD_BASE)
+  #define FSDEV_REG_BASE USB_DRD_BASE
+#elif defined(USB_DRD_FS_BASE)
+  #define FSDEV_REG_BASE USB_DRD_FS_BASE
+#else
+  #error "FSDEV_REG_BASE not defined"
+#endif
+#endif
+
+#ifndef FSDEV_PMA_BASE
+#if defined(USB_PMAADDR)
+  #define FSDEV_PMA_BASE USB_PMAADDR
+#elif defined(USB_DRD_PMAADDR)
+  #define FSDEV_PMA_BASE USB_DRD_PMAADDR
+#else
+  #error "FSDEV_PMA_BASE not defined"
+#endif
+#endif
+
+// This checks if the device has "LPM"
+#if defined(USB_ISTR_L1REQ)
+#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ)
+#else
+#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U)
+#endif
+
+#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \
+     USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+#if TU_CHECK_MCU(OPT_MCU_STM32L1) && !defined(USBWakeUp_IRQn)
+  #define USBWakeUp_IRQn USB_FS_WKUP_IRQn
+#endif
+
+static const IRQn_Type fsdev_irq[] = {
+  #if TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32L0, OPT_MCU_STM32L4)
+    USB_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32F1
+    USB_HP_CAN1_TX_IRQn,
+    USB_LP_CAN1_RX0_IRQn,
+    USBWakeUp_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32F3
+    // USB remap handles dcd functions
+    USB_HP_CAN_TX_IRQn,
+    USB_LP_CAN_RX0_IRQn,
+    USBWakeUp_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+    #ifdef STM32G0B0xx
+    USB_IRQn,
+    #else
+    USB_UCPD1_2_IRQn,
+    #endif
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32C0
+    USB_DRD_FS_IRQn,
+  #elif TU_CHECK_MCU(OPT_MCU_STM32G4, OPT_MCU_STM32L1)
+    USB_HP_IRQn,
+    USB_LP_IRQn,
+    USBWakeUp_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32H5
+    USB_DRD_FS_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32L5
+    USB_FS_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+    USB_HP_IRQn,
+    USB_LP_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
+    USB_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32U0
+    USB_DRD_FS_IRQn,
+  #else
+    #error Unknown arch in USB driver
+  #endif
+};
+enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
+
+void dcd_int_enable(uint8_t rhport) {
+  (void)rhport;
+
+  // forces write to RAM before allowing ISR to execute
+  __DSB(); __ISB();
+
+  #if CFG_TUSB_MCU == OPT_MCU_STM32F3 && defined(SYSCFG_CFGR1_USB_IT_RMP)
+  // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
+  // shared USB/CAN IRQs to separate CAN and USB IRQs.
+  // This dynamically checks if this remap is active to enable the right IRQs.
+  if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
+    NVIC_EnableIRQ(USB_HP_IRQn);
+    NVIC_EnableIRQ(USB_LP_IRQn);
+    NVIC_EnableIRQ(USBWakeUp_RMP_IRQn);
+  } else
+  #endif
+  {
+    for (uint8_t i = 0; i < FSDEV_IRQ_NUM; i++) {
+      NVIC_EnableIRQ(fsdev_irq[i]);
+    }
+  }
+}
+
+void dcd_int_disable(uint8_t rhport) {
+  (void)rhport;
+
+  #if CFG_TUSB_MCU == OPT_MCU_STM32F3 && defined(SYSCFG_CFGR1_USB_IT_RMP)
+  // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
+  // shared USB/CAN IRQs to separate CAN and USB IRQs.
+  // This dynamically checks if this remap is active to enable the right IRQs.
+  if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
+    NVIC_DisableIRQ(USB_HP_IRQn);
+    NVIC_DisableIRQ(USB_LP_IRQn);
+    NVIC_DisableIRQ(USBWakeUp_RMP_IRQn);
+  } else
+  #endif
+  {
+    for (uint8_t i = 0; i < FSDEV_IRQ_NUM; i++) {
+      NVIC_DisableIRQ(fsdev_irq[i]);
+    }
+  }
+
+  // CMSIS has a membar after disabling interrupts
+}
+
+// Define only on MCU with internal pull-up. BSP can define on MCU without internal PU.
+#if defined(USB_BCDR_DPPU)
+
+void dcd_disconnect(uint8_t rhport) {
+  (void)rhport;
+  USB->BCDR &= ~(USB_BCDR_DPPU);
+}
+
+void dcd_connect(uint8_t rhport) {
+  (void)rhport;
+  USB->BCDR |= USB_BCDR_DPPU;
+}
+
+#elif defined(SYSCFG_PMC_USB_PU) // works e.g. on STM32L151
+
+void dcd_disconnect(uint8_t rhport) {
+  (void)rhport;
+  SYSCFG->PMC &= ~(SYSCFG_PMC_USB_PU);
+}
+
+void dcd_connect(uint8_t rhport) {
+  (void)rhport;
+  SYSCFG->PMC |= SYSCFG_PMC_USB_PU;
+}
+#endif
+
+
+#endif /* TUSB_FSDEV_STM32_H */
diff --git a/src/portable/st/stm32_fsdev/fsdev_type.h b/src/portable/st/stm32_fsdev/fsdev_type.h
new file mode 100644
index 000000000..cf36576bb
--- /dev/null
+++ b/src/portable/st/stm32_fsdev/fsdev_type.h
@@ -0,0 +1,307 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright(c) N Conrad
+ * Copyright(c) 2024, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_FSDEV_TYPE_H
+#define TUSB_FSDEV_TYPE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stdint.h"
+
+// If sharing with CAN, one can set this to be non-zero to give CAN space where it wants it
+// Both of these MUST be a multiple of 2, and are in byte units.
+#ifndef FSDEV_BTABLE_BASE
+#define FSDEV_BTABLE_BASE 0U
+#endif
+
+TU_VERIFY_STATIC(FSDEV_BTABLE_BASE % 8 == 0, "BTABLE base must be aligned to 8 bytes");
+
+// FSDEV_PMA_SIZE is PMA buffer size in bytes.
+// - 512-byte devices, access with a stride of two words (use every other 16-bit address)
+// - 1024-byte devices, access with a stride of one word (use every 16-bit address)
+// - 2048-byte devices, access with 32-bit address
+
+// For purposes of accessing the packet
+#if FSDEV_PMA_SIZE == 512
+  // 1x16 bit / word access scheme
+  #define FSDEV_PMA_STRIDE  2
+  #define pma_access_scheme TU_ATTR_ALIGNED(4)
+#elif FSDEV_PMA_SIZE == 1024
+  // 2x16 bit / word access scheme
+  #define FSDEV_PMA_STRIDE  1
+  #define pma_access_scheme
+#elif FSDEV_PMA_SIZE == 2048
+  // 32 bit access scheme
+  #define FSDEV_BUS_32BIT
+  #define FSDEV_PMA_STRIDE  1
+  #define pma_access_scheme
+#endif
+
+// The fsdev_bus_t type can be used for both register and PMA access necessities
+#ifdef FSDEV_BUS_32BIT
+  typedef uint32_t fsdev_bus_t;
+  #define fsdevbus_unaligned_read(_addr)           tu_unaligned_read32(_addr)
+  #define fsdevbus_unaligned_write(_addr, _value)  tu_unaligned_write32(_addr, _value)
+#else
+  typedef uint16_t fsdev_bus_t;
+  #define fsdevbus_unaligned_read(_addr)           tu_unaligned_read16(_addr)
+  #define fsdevbus_unaligned_write(_addr, _value)  tu_unaligned_write16(_addr, _value)
+#endif
+
+enum {
+  FSDEV_BUS_SIZE = sizeof(fsdev_bus_t),
+};
+
+//--------------------------------------------------------------------+
+// BTable Typedef
+//--------------------------------------------------------------------+
+enum {
+  BTABLE_BUF_TX = 0,
+  BTABLE_BUF_RX = 1
+};
+
+// hardware limit endpoint
+#define FSDEV_EP_COUNT 8
+
+// Buffer Table is located in Packet Memory Area (PMA) and therefore its address access is forced to either
+// 16-bit or 32-bit depending on FSDEV_BUS_32BIT.
+// 0: TX (IN), 1: RX (OUT)
+typedef union {
+  // data is strictly 16-bit access (address could be 32-bit aligned)
+  struct {
+    volatile pma_access_scheme uint16_t addr;
+    volatile pma_access_scheme uint16_t count;
+  } ep16[FSDEV_EP_COUNT][2];
+
+  // strictly 32-bit access
+  struct {
+    volatile uint32_t count_addr;
+  } ep32[FSDEV_EP_COUNT][2];
+} fsdev_btable_t;
+
+TU_VERIFY_STATIC(sizeof(fsdev_btable_t) == FSDEV_EP_COUNT*8*FSDEV_PMA_STRIDE, "size is not correct");
+TU_VERIFY_STATIC(FSDEV_BTABLE_BASE + FSDEV_EP_COUNT*8 <= FSDEV_PMA_SIZE, "BTABLE does not fit in PMA RAM");
+
+#define FSDEV_BTABLE ((volatile fsdev_btable_t*) (FSDEV_PMA_BASE + FSDEV_PMA_STRIDE*(FSDEV_BTABLE_BASE)))
+
+typedef struct {
+  volatile pma_access_scheme fsdev_bus_t value;
+} fsdev_pma_buf_t;
+
+#define PMA_BUF_AT(_addr) ((fsdev_pma_buf_t*) (FSDEV_PMA_BASE + FSDEV_PMA_STRIDE*(_addr)))
+
+//--------------------------------------------------------------------+
+// Registers Typedef
+//--------------------------------------------------------------------+
+
+// volatile 32-bit aligned
+#define _va32     volatile TU_ATTR_ALIGNED(4)
+
+typedef struct {
+  struct {
+    _va32 fsdev_bus_t reg;
+  }ep[FSDEV_EP_COUNT];
+
+  _va32 uint32_t RESERVED7[8];       // Reserved
+  _va32 fsdev_bus_t CNTR;            // 40: Control register
+  _va32 fsdev_bus_t ISTR;            // 44: Interrupt status register
+  _va32 fsdev_bus_t FNR;             // 48: Frame number register
+  _va32 fsdev_bus_t DADDR;           // 4C: Device address register
+  _va32 fsdev_bus_t BTABLE;          // 50: Buffer Table address register (16-bit only)
+  _va32 fsdev_bus_t LPMCSR;          // 54: LPM Control and Status Register (32-bit only)
+  _va32 fsdev_bus_t BCDR;            // 58: Battery Charging Detector Register (32-bit only)
+} fsdev_regs_t;
+
+TU_VERIFY_STATIC(offsetof(fsdev_regs_t, CNTR) == 0x40, "Wrong offset");
+TU_VERIFY_STATIC(sizeof(fsdev_regs_t) == 0x5C, "Size is not correct");
+
+#define FSDEV_REG ((fsdev_regs_t*) FSDEV_REG_BASE)
+
+
+#ifndef USB_EPTX_STAT
+#define USB_EPTX_STAT 0x0030U
+#endif
+
+#ifndef USB_EPRX_STAT
+#define USB_EPRX_STAT 0x3000U
+#endif
+
+#ifndef USB_EPTX_STAT_Pos
+#define USB_EPTX_STAT_Pos    4u
+#endif
+
+#ifndef USB_EP_DTOG_TX_Pos
+#define USB_EP_DTOG_TX_Pos   6u
+#endif
+
+#ifndef USB_EP_CTR_TX_Pos
+#define USB_EP_CTR_TX_Pos    7u
+#endif
+
+typedef enum {
+  EP_STAT_DISABLED = 0,
+  EP_STAT_STALL = 1,
+  EP_STAT_NAK = 2,
+  EP_STAT_VALID = 3
+}ep_stat_t;
+
+#define EP_STAT_MASK(_dir)  (3u << (USB_EPTX_STAT_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
+#define EP_DTOG_MASK(_dir)  (1u << (USB_EP_DTOG_TX_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
+
+//--------------------------------------------------------------------+
+// Endpoint Helper
+// - CTR is write 0 to clear
+// - DTOG and STAT are write 1 to toggle
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_read(uint32_t ep_id) {
+  return FSDEV_REG->ep[ep_id].reg;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void ep_write(uint32_t ep_id, uint32_t value, bool need_exclusive) {
+  if (need_exclusive) {
+    dcd_int_disable(0);
+  }
+
+  FSDEV_REG->ep[ep_id].reg = (fsdev_bus_t) value;
+
+  if (need_exclusive) {
+    dcd_int_enable(0);
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void ep_write_clear_ctr(uint32_t ep_id, tusb_dir_t dir) {
+  uint32_t reg = FSDEV_REG->ep[ep_id].reg;
+  reg |= USB_EP_CTR_TX | USB_EP_CTR_RX;
+  reg &= USB_EPREG_MASK;
+  reg &= ~(1 << (USB_EP_CTR_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
+  ep_write(ep_id, reg, false);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void ep_change_status(uint32_t* reg, tusb_dir_t dir, ep_stat_t state) {
+  *reg ^= (state << (USB_EPTX_STAT_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void ep_change_dtog(uint32_t* reg, tusb_dir_t dir, uint8_t state) {
+  *reg ^= (state << (USB_EP_DTOG_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(uint32_t reg) {
+  return (reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS;
+}
+
+//--------------------------------------------------------------------+
+// BTable Helper
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t btable_get_addr(uint32_t ep_id, uint8_t buf_id) {
+#ifdef FSDEV_BUS_32BIT
+  return FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr & 0x0000FFFFu;
+#else
+  return FSDEV_BTABLE->ep16[ep_id][buf_id].addr;
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void btable_set_addr(uint32_t ep_id, uint8_t buf_id, uint16_t addr) {
+#ifdef FSDEV_BUS_32BIT
+  uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
+  count_addr = (count_addr & 0xFFFF0000u) | (addr & 0x0000FFFCu);
+  FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
+#else
+  FSDEV_BTABLE->ep16[ep_id][buf_id].addr = addr;
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t btable_get_count(uint32_t ep_id, uint8_t buf_id) {
+  uint16_t count;
+#ifdef FSDEV_BUS_32BIT
+  count = (FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr >> 16);
+#else
+  count = FSDEV_BTABLE->ep16[ep_id][buf_id].count;
+#endif
+  return count & 0x3FFU;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void btable_set_count(uint32_t ep_id, uint8_t buf_id, uint16_t byte_count) {
+#ifdef FSDEV_BUS_32BIT
+  uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
+  count_addr = (count_addr & ~0x03FF0000u) | ((byte_count & 0x3FFu) << 16);
+  FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
+#else
+  uint16_t cnt = FSDEV_BTABLE->ep16[ep_id][buf_id].count;
+  cnt = (cnt & ~0x3FFU) | (byte_count & 0x3FFU);
+  FSDEV_BTABLE->ep16[ep_id][buf_id].count = cnt;
+#endif
+}
+
+/* Aligned buffer size according to hardware */
+TU_ATTR_ALWAYS_INLINE static inline uint16_t pma_align_buffer_size(uint16_t size, uint8_t* blsize, uint8_t* num_block) {
+  /* The STM32 full speed USB peripheral supports only a limited set of
+   * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
+  uint16_t block_in_bytes;
+  if (size > 62) {
+    block_in_bytes = 32;
+    *blsize = 1;
+    *num_block = tu_div_ceil(size, 32);
+  } else {
+    block_in_bytes = 2;
+    *blsize = 0;
+    *num_block = tu_div_ceil(size, 2);
+  }
+
+  return (*num_block) * block_in_bytes;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void btable_set_rx_bufsize(uint32_t ep_id, uint8_t buf_id, uint16_t wCount) {
+  uint8_t blsize, num_block;
+  (void) pma_align_buffer_size(wCount, &blsize, &num_block);
+
+  /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
+  uint16_t bl_nb = (blsize << 15) | ((num_block - blsize) << 10);
+  if (bl_nb == 0) {
+    // zlp but 0 is invalid value, set blsize to 1 (32 bytes)
+    // Note: lower value can cause PMAOVR on setup with ch32v203
+    bl_nb = 1 << 15;
+  }
+
+#ifdef FSDEV_BUS_32BIT
+  uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
+  count_addr = (bl_nb << 16) | (count_addr & 0x0000FFFFu);
+  FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
+#else
+  FSDEV_BTABLE->ep16[ep_id][buf_id].count = bl_nb;
+#endif
+
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
deleted file mode 100644
index 2fc3adb4f..000000000
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ /dev/null
@@ -1,1240 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- * Copyright (c) 2020 Jan Duempelmann
- * Copyright (c) 2020 Reinhard Panhuber
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#define USE_SOF     0
-
-#if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
-    defined (STM32F107xB) || defined (STM32F107xC)
-#define STM32F1_SYNOPSYS
-#endif
-
-#if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
-    defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
-    defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define STM32L4_SYNOPSYS
-#endif
-
-#if CFG_TUD_ENABLED &&                                          \
-    ( (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \
-       CFG_TUSB_MCU == OPT_MCU_STM32F2                               || \
-       CFG_TUSB_MCU == OPT_MCU_STM32F4                               || \
-       CFG_TUSB_MCU == OPT_MCU_STM32F7                               || \
-       CFG_TUSB_MCU == OPT_MCU_STM32H7                               || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)  || \
-       CFG_TUSB_MCU == OPT_MCU_GD32VF103 )                           \
-    )
-
-// EP_MAX       : Max number of bi-directional endpoints including EP0
-// EP_FIFO_SIZE : Size of dedicated USB SRAM
-#if CFG_TUSB_MCU == OPT_MCU_STM32F1
-#include "stm32f1xx.h"
-#define EP_MAX_FS       4
-#define EP_FIFO_SIZE_FS 1280
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F2
-#include "stm32f2xx.h"
-#define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
-#define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F4
-#include "stm32f4xx.h"
-#define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
-#define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
-#define EP_MAX_HS       USB_OTG_HS_MAX_IN_ENDPOINTS
-#define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32H7
-#include "stm32h7xx.h"
-#define EP_MAX_FS       9
-#define EP_FIFO_SIZE_FS 4096
-#define EP_MAX_HS       9
-#define EP_FIFO_SIZE_HS 4096
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
-#include "stm32f7xx.h"
-#define EP_MAX_FS       6
-#define EP_FIFO_SIZE_FS 1280
-#define EP_MAX_HS       9
-#define EP_FIFO_SIZE_HS 4096
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
-#include "stm32l4xx.h"
-#define EP_MAX_FS       6
-#define EP_FIFO_SIZE_FS 1280
-
-#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
-#include "synopsys_common.h"
-
-// for remote wakeup delay
-#define __NOP()   __asm volatile ("nop")
-
-// These numbers are the same for the whole GD32VF103 family.
-#define OTG_FS_IRQn     86
-#define EP_MAX_FS       4
-#define EP_FIFO_SIZE_FS 1280
-
-// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
-// Interrupt Controller by Nuclei. It is nearly API compatible to the
-// NVIC used by ARM MCUs.
-#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
-
-#define NVIC_EnableIRQ __eclic_enable_interrupt
-#define NVIC_DisableIRQ __eclic_disable_interrupt
-
-static inline void __eclic_enable_interrupt (uint32_t irq) {
-  *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
-}
-
-static inline void __eclic_disable_interrupt (uint32_t irq){
-  *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
-}
-
-#else
-#error "Unsupported MCUs"
-#endif
-
-#include "device/dcd.h"
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
-#if TUD_OPT_RHPORT == 0
-#define EP_MAX            EP_MAX_FS
-#define EP_FIFO_SIZE      EP_FIFO_SIZE_FS
-#define RHPORT_REGS_BASE  USB_OTG_FS_PERIPH_BASE
-#define RHPORT_IRQn       OTG_FS_IRQn
-
-#else
-#define EP_MAX            EP_MAX_HS
-#define EP_FIFO_SIZE      EP_FIFO_SIZE_HS
-#define RHPORT_REGS_BASE  USB_OTG_HS_PERIPH_BASE
-#define RHPORT_IRQn       OTG_HS_IRQn
-
-#endif
-
-#define GLOBAL_BASE(_port)     ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE)
-#define DEVICE_BASE(_port)     (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE)
-#define OUT_EP_BASE(_port)     (USB_OTG_OUTEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE)
-#define IN_EP_BASE(_port)      (USB_OTG_INEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE)
-#define FIFO_BASE(_port, _x)   ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
-
-enum
-{
-  DCD_HIGH_SPEED        = 0, // Highspeed mode
-  DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY)
-  DCD_FULL_SPEED        = 3, // Full speed with internal PHY
-};
-
-static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
-
-typedef struct {
-  uint8_t * buffer;
-  tu_fifo_t * ff;
-  uint16_t total_len;
-  uint16_t max_size;
-  uint8_t interval;
-} xfer_ctl_t;
-
-typedef volatile uint32_t * usb_fifo_t;
-
-xfer_ctl_t xfer_status[EP_MAX][2];
-#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
-
-// EP0 transfers are limited to 1 packet - larger sizes has to be split
-static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
-
-// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
-static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
-static bool _out_ep_closed;                       // Flag to check if RX FIFO size needs an update (reduce its size)
-
-// Calculate the RX FIFO size according to recommendations from reference manual
-static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
-{
-  return 15 + 2*(ep_size/4) + 2*EP_MAX;
-}
-
-static void update_grxfsiz(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-
-  // Determine largest EP size for RX FIFO
-  uint16_t max_epsize = 0;
-  for (uint8_t epnum = 0; epnum < EP_MAX; epnum++)
-  {
-    max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
-  }
-
-  // Update size of RX FIFO
-  usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize);
-}
-
-// Setup the control endpoint 0.
-static void bus_reset(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  tu_memclr(xfer_status, sizeof(xfer_status));
-  _out_ep_closed = false;
-
-  // clear device address
-  dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
-
-  // 1. NAK for all OUT endpoints
-  for(uint8_t n = 0; n < EP_MAX; n++) {
-    out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
-  }
-
-  // 2. Un-mask interrupt bits
-  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
-  dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
-  dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
-
-  // "USB Data FIFOs" section in reference manual
-  // Peripheral FIFO architecture
-  //
-  // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
-  // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
-  // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
-  // configuration done below.
-  //
-  // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
-  // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
-  // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
-  // opened when the host sends an additional command: setInterface. At this point in time
-  // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
-  // an additional memory
-  //
-  // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-  // | IN FIFO 0   |
-  // --------------- (320 or 1024) - 16
-  // | IN FIFO 1   |
-  // --------------- (320 or 1024) - 16 - x
-  // |   . . . .   |
-  // --------------- (320 or 1024) - 16 - x - y - ... - z
-  // | IN FIFO MAX |
-  // ---------------
-  // |    FREE     |
-  // --------------- GRXFSIZ
-  // | OUT FIFO    |
-  // | ( Shared )  |
-  // --------------- 0
-  //
-  // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
-  // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
-  //
-  // - All EP OUT shared a unique OUT FIFO which uses
-  //   - 13 for setup packets + control words (up to 3 setup packets).
-  //   - 1 for global NAK (not required/used here).
-  //   - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is  "2 x (Largest-EPsize/4) + 1"
-  //   - 2 for each used OUT endpoint
-  //
-  //   Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
-  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x EP_MAX = 47  + 2 x EP_MAX
-  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX
-  //
-  //   NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
-  //   of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
-  //
-  //   For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
-  //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
-  //   overwrite this.
-
-  usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
-
-  _allocated_fifo_words_tx = 16;
-
-  // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
-
-  // Fixed control EP0 size to 64 bytes
-  in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
-  xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
-
-  out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
-
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
-}
-
-// Set turn-around timeout according to link speed
-extern uint32_t SystemCoreClock;
-static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed)
-{
-  usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-
-  if ( speed == TUSB_SPEED_HIGH )
-  {
-    // Use fixed 0x09 for Highspeed
-    usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos);
-  }
-  else
-  {
-    // Turnaround timeout depends on the MCU clock
-    uint32_t turnaround;
-
-    if ( SystemCoreClock >= 32000000U )
-      turnaround = 0x6U;
-    else if ( SystemCoreClock >= 27500000U )
-      turnaround = 0x7U;
-    else if ( SystemCoreClock >= 24000000U )
-      turnaround = 0x8U;
-    else if ( SystemCoreClock >= 21800000U )
-      turnaround = 0x9U;
-    else if ( SystemCoreClock >= 20000000U )
-      turnaround = 0xAU;
-    else if ( SystemCoreClock >= 18500000U )
-      turnaround = 0xBU;
-    else if ( SystemCoreClock >= 17200000U )
-      turnaround = 0xCU;
-    else if ( SystemCoreClock >= 16000000U )
-      turnaround = 0xDU;
-    else if ( SystemCoreClock >= 15000000U )
-      turnaround = 0xEU;
-    else
-      turnaround = 0xFU;
-
-    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos);
-  }
-}
-
-static tusb_speed_t get_speed(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
-  return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
-}
-
-static void set_speed(uint8_t rhport, tusb_speed_t speed)
-{
-  uint32_t bitvalue;
-
-  if ( rhport == 1 )
-  {
-    bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
-  }
-  else
-  {
-    bitvalue = DCD_FULL_SPEED;
-  }
-
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-
-  // Clear and set speed bits
-  dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
-  dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
-}
-
-#if defined(USB_HS_PHYC)
-static bool USB_HS_PHYCInit(void)
-{
-  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
-
-  // Enable LDO: Note STM32F72/3xx Reference Manual rev 3 June 2018 incorrectly defined this bit as Disabled !!
-  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
-
-  // Wait until LDO ready
-  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
-
-  uint32_t phyc_pll = 0;
-
-  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
-  switch ( HSE_VALUE )
-  {
-    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
-    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
-    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
-    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
-    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
-    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
-    default:
-      TU_ASSERT(0);
-  }
-  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
-
-  // Control the tuning interface of the High Speed PHY
-  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
-  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
-
-  // Enable PLL internal PHY
-  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
-
-  // Original ST code has 2 ms delay for PLL stabilization.
-  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
-
-  return true;
-}
-#endif
-
-static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
-{
-  (void) rhport;
-
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  // EP0 is limited to one packet each xfer
-  // We use multiple transaction of xfer->max_size length to get a whole transfer done
-  if(epnum == 0) {
-    xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir);
-    total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
-    ep0_pending[dir] -= total_bytes;
-  }
-
-  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
-  if(dir == TUSB_DIR_IN) {
-    // A full IN transfer (multiple packets, possibly) triggers XFRC.
-    in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk);
-
-    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
-    // For ISO endpoint set correct odd/even bit for next frame.
-    if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
-    {
-      // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
-      in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk);
-    }
-    // Enable fifo empty interrupt only if there are something to put in the fifo.
-    if(total_bytes != 0) {
-      dev->DIEPEMPMSK |= (1 << epnum);
-    }
-  } else {
-    // A full OUT transfer (multiple packets, possibly) triggers XFRC.
-    out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ);
-    out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk);
-
-    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
-    if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
-    {
-      // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
-      out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk);
-    }
-  }
-}
-
-/*------------------------------------------------------------------*/
-/* Controller API
- *------------------------------------------------------------------*/
-void dcd_init (uint8_t rhport)
-{
-  // Programming model begins in the last section of the chapter on the USB
-  // peripheral in each Reference Manual.
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-
-  // No HNP/SRP (no OTG support), program timeout later.
-  if ( rhport == 1 )
-  {
-    // On selected MCUs HS port1 can be used with external PHY via ULPI interface
-#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
-    // deactivate internal PHY
-    usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
-
-    // Init The UTMI Interface
-    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
-
-    // Select default internal VBUS Indicator and Drive for ULPI
-    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
-#else
-    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-#endif
-
-#if defined(USB_HS_PHYC)
-    // Highspeed with embedded UTMI PHYC
-
-    // Select UTMI Interface
-    usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
-    usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
-
-    // Enables control of a High Speed USB PHY
-    USB_HS_PHYCInit();
-#endif
-  } else
-  {
-    // Enable internal PHY
-    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-  }
-
-  // Reset core after selecting PHY
-  // Wait AHB IDLE, reset then wait until it is cleared
-  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
-  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
-
-  // Restart PHY clock
-  *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
-
-  // Clear all interrupts
-  usb_otg->GINTSTS |= usb_otg->GINTSTS;
-
-  // Required as part of core initialization.
-  // TODO: How should mode mismatch be handled? It will cause
-  // the core to stop working/require reset.
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM;
-
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-
-  // If USB host misbehaves during status portion of control xfer
-  // (non zero-length packet), send STALL back and discard.
-  dev->DCFG |=  USB_OTG_DCFG_NZLSOHSK;
-
-  set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
-
-  // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
-
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST   | USB_OTG_GINTMSK_ENUMDNEM |
-      USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM     |
-      USB_OTG_GINTMSK_RXFLVLM  | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0);
-
-  // Enable global interrupt
-  usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
-
-  dcd_connect(rhport);
-}
-
-void dcd_int_enable (uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ(RHPORT_IRQn);
-}
-
-void dcd_int_disable (uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(RHPORT_IRQn);
-}
-
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos);
-
-  // Response with status after changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-}
-
-static void remote_wakeup_delay(void)
-{
-  // try to delay for 1 ms
-  uint32_t count = SystemCoreClock / 1000;
-  while ( count-- )
-  {
-    __NOP();
-  }
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-
-  // set remote wakeup
-  dev->DCTL |= USB_OTG_DCTL_RWUSIG;
-
-  // enable SOF to detect bus resume
-  usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM;
-
-  // Per specs: remote wakeup signal bit must be clear within 1-15ms
-  remote_wakeup_delay();
-
-  dev->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCTL &= ~USB_OTG_DCTL_SDIS;
-}
-
-void dcd_disconnect(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCTL |= USB_OTG_DCTL_SDIS;
-}
-
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
-  (void) rhport;
-  (void) en;
-
-  // TODO implement later
-}
-
-/*------------------------------------------------------------------*/
-/* DCD Endpoint port
- *------------------------------------------------------------------*/
-
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
-
-  TU_ASSERT(epnum < EP_MAX);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = tu_edpt_packet_size(desc_edpt);
-  xfer->interval = desc_edpt->bInterval;
-
-  uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word
-
-  if(dir == TUSB_DIR_OUT)
-  {
-    // Calculate required size of RX FIFO
-    uint16_t const sz = calc_rx_ff_size(4*fifo_size);
-
-    // If size_rx needs to be extended check if possible and if so enlarge it
-    if (usb_otg->GRXFSIZ < sz)
-    {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
-
-      // Enlarge RX FIFO
-      usb_otg->GRXFSIZ = sz;
-    }
-
-    out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos)        |
-        (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos)   |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos);
-
-    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
-  }
-  else
-  {
-    // "USB Data FIFOs" section in reference manual
-    // Peripheral FIFO architecture
-    //
-    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-    // | IN FIFO 0   |
-    // --------------- (320 or 1024) - 16
-    // | IN FIFO 1   |
-    // --------------- (320 or 1024) - 16 - x
-    // |   . . . .   |
-    // --------------- (320 or 1024) - 16 - x - y - ... - z
-    // | IN FIFO MAX |
-    // ---------------
-    // |    FREE     |
-    // --------------- GRXFSIZ
-    // | OUT FIFO    |
-    // | ( Shared )  |
-    // --------------- 0
-    //
-    // In FIFO is allocated by following rules:
-    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
-
-    // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
-
-    _allocated_fifo_words_tx += fifo_size;
-
-    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
-
-    // DIEPTXF starts at FIFO #1.
-    // Both TXFD and TXSA are in unit of 32-bit words.
-    usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
-
-    in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
-        (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
-        (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos);
-
-    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
-  }
-
-  return true;
-}
-
-// Close all non-control endpoints, cancel all pending transfers if any.
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  (void) rhport;
-
-//  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  // Disable non-control interrupt
-  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
-
-  for(uint8_t n = 1; n < EP_MAX; n++)
-  {
-    // disable OUT endpoint
-    out_ep[n].DOEPCTL = 0;
-    xfer_status[n][TUSB_DIR_OUT].max_size = 0;
-
-    // disable IN endpoint
-    in_ep[n].DIEPCTL = 0;
-    xfer_status[n][TUSB_DIR_IN].max_size = 0;
-  }
-
-  // reset allocated fifo IN
-  _allocated_fifo_words_tx = 16;
-}
-
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = buffer;
-  xfer->ff          = NULL;
-  xfer->total_len   = total_bytes;
-
-  // EP0 can only handle one packet
-  if(epnum == 0) {
-    ep0_pending[dir] = total_bytes;
-    // Schedule the first transaction for EP0 transfer
-    edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
-    return true;
-  }
-
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint16_t const short_packet_size = total_bytes % xfer->max_size;
-
-  // Zero-size packet is special case.
-  if(short_packet_size > 0 || (total_bytes == 0)) {
-    num_packets++;
-  }
-
-  // Schedule packets to be sent within interrupt
-  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
-
-  return true;
-}
-
-// The number of bytes has to be given explicitly to allow more flexible control of how many
-// bytes should be written and second to keep the return value free to give back a boolean
-// success message. If total_bytes is too big, the FIFO will copy only what is available
-// into the USB buffer!
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
-  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
-  TU_ASSERT(ff->item_size == 1);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = NULL;
-  xfer->ff          = ff;
-  xfer->total_len   = total_bytes;
-
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint16_t const short_packet_size = total_bytes % xfer->max_size;
-
-  // Zero-size packet is special case.
-  if(short_packet_size > 0 || (total_bytes == 0)) num_packets++;
-
-  // Schedule packets to be sent within interrupt
-  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
-
-  return true;
-}
-
-static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  if(dir == TUSB_DIR_IN) {
-    // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0);
-    } else {
-      // Stop transmitting packets and NAK IN xfers.
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
-      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0);
-
-      // Disable the endpoint.
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0);
-      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0);
-      in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD;
-    }
-
-    // Flush the FIFO, and wait until we have confirmed it cleared.
-    usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos);
-    usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
-    while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
-  } else {
-    // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
-      out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0;
-    } else {
-      // Asserting GONAK is required to STALL an OUT endpoint.
-      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
-      // anyway, and it can't be cleared by user code. If this while loop never
-      // finishes, we have bigger problems than just the stack.
-      dev->DCTL |= USB_OTG_DCTL_SGONAK;
-      while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
-
-      // Ditto here- disable the endpoint.
-      out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0);
-      while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0);
-      out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD;
-
-      // Allow other OUT endpoints to keep receiving.
-      dev->DCTL |= USB_OTG_DCTL_CGONAK;
-    }
-  }
-}
-
-/**
- * Close an endpoint.
- */
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  dcd_edpt_disable(rhport, ep_addr, false);
-
-  // Update max_size
-  xfer_status[epnum][dir].max_size = 0;  // max_size = 0 marks a disabled EP - required for changing FIFO allocation
-
-  if (dir == TUSB_DIR_IN)
-  {
-    uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
-    uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
-    // For now only the last opened endpoint can be closed without fuss.
-    TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
-    _allocated_fifo_words_tx -= fifo_size;
-  }
-  else
-  {
-    _out_ep_closed = true;     // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
-  }
-}
-
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  dcd_edpt_disable(rhport, ep_addr, true);
-}
-
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  // Clear stall and reset data toggle
-  if(dir == TUSB_DIR_IN) {
-    in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
-  } else {
-    out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
-  }
-}
-
-/*------------------------------------------------------------------*/
-
-// Read a single data packet from receive FIFO
-static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
-{
-  (void) rhport;
-
-  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
-
-  // Reading full available 32 bit words from fifo
-  uint16_t full_words = len >> 2;
-  for(uint16_t i = 0; i < full_words; i++) {
-    uint32_t tmp = *rx_fifo;
-    dst[0] = tmp & 0x000000FF;
-    dst[1] = (tmp & 0x0000FF00) >> 8;
-    dst[2] = (tmp & 0x00FF0000) >> 16;
-    dst[3] = (tmp & 0xFF000000) >> 24;
-    dst += 4;
-  }
-
-  // Read the remaining 1-3 bytes from fifo
-  uint8_t bytes_rem = len & 0x03;
-  if(bytes_rem != 0) {
-    uint32_t tmp = *rx_fifo;
-    dst[0] = tmp & 0x000000FF;
-    if(bytes_rem > 1) {
-      dst[1] = (tmp & 0x0000FF00) >> 8;
-    }
-    if(bytes_rem > 2) {
-      dst[2] = (tmp & 0x00FF0000) >> 16;
-    }
-  }
-}
-
-// Write a single data packet to EPIN FIFO
-static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len)
-{
-  (void) rhport;
-
-  usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num);
-
-  // Pushing full available 32 bit words to fifo
-  uint16_t full_words = len >> 2;
-  for(uint16_t i = 0; i < full_words; i++){
-    *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0];
-    src += 4;
-  }
-
-  // Write the remaining 1-3 bytes into fifo
-  uint8_t bytes_rem = len & 0x03;
-  if(bytes_rem){
-    uint32_t tmp_word = 0;
-    tmp_word |= src[0];
-    if(bytes_rem > 1){
-      tmp_word |= src[1] << 8;
-    }
-    if(bytes_rem > 2){
-      tmp_word |= src[2] << 16;
-    }
-    *tx_fifo = tmp_word;
-  }
-}
-
-static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_ep) {
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
-
-  // Pop control word off FIFO
-  uint32_t ctl_word = usb_otg->GRXSTSP;
-  uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
-  uint8_t epnum = (ctl_word &  USB_OTG_GRXSTSP_EPNUM_Msk) >>  USB_OTG_GRXSTSP_EPNUM_Pos;
-  uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
-
-  switch(pktsts) {
-    case 0x01: // Global OUT NAK (Interrupt)
-      break;
-
-    case 0x02: // Out packet recvd
-    {
-      xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
-
-      // Read packet off RxFIFO
-      if (xfer->ff)
-      {
-        // Ring buffer
-        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt);
-      }
-      else
-      {
-        // Linear buffer
-        read_fifo_packet(rhport, xfer->buffer, bcnt);
-
-        // Increment pointer to xfer data
-        xfer->buffer += bcnt;
-      }
-
-      // Truncate transfer length in case of short packet
-      if(bcnt < xfer->max_size) {
-        xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
-        if(epnum == 0) {
-          xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
-          ep0_pending[TUSB_DIR_OUT] = 0;
-        }
-      }
-    }
-    break;
-
-    case 0x03: // Out packet done (Interrupt)
-      break;
-
-    case 0x04: // Setup packet done (Interrupt)
-      out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
-      break;
-
-    case 0x06: // Setup packet recvd
-      // We can receive up to three setup packets in succession, but
-      // only the last one is valid.
-      _setup_packet[0] = (* rx_fifo);
-      _setup_packet[1] = (* rx_fifo);
-      break;
-
-    default: // Invalid
-      TU_BREAKPOINT();
-      break;
-  }
-}
-
-static void handle_epout_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
-  // DAINT for a given EP clears when DOEPINTx is cleared.
-  // OEPINT will be cleared when DAINT's out bits are cleared.
-  for(uint8_t n = 0; n < EP_MAX; n++) {
-    xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
-    if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
-      // SETUP packet Setup Phase done.
-      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
-        out_ep[n].DOEPINT =  USB_OTG_DOEPINT_STUP;
-        dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
-      }
-
-      // OUT XFER complete
-      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) {
-        out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC;
-
-        // EP0 can only handle one packet
-        if((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
-          // Schedule another packet to be received.
-          edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
-        } else {
-          dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
-      }
-    }
-  }
-}
-
-static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) {
-  // DAINT for a given EP clears when DIEPINTx is cleared.
-  // IEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < EP_MAX; n++ )
-  {
-    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
-
-    if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) )
-    {
-      // IN XFER complete (entire xfer).
-      if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC )
-      {
-        in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC;
-
-        // EP0 can only handle one packet
-        if((n == 0) && ep0_pending[TUSB_DIR_IN]) {
-          // Schedule another packet to be transmitted.
-          edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
-        } else {
-          dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
-      }
-
-      // XFER FIFO empty
-      if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
-      {
-        // DIEPINT's TXFE bit is read-only, software cannot clear it.
-        // It will only be cleared by hardware when written bytes is more than
-        // - 64 bytes or
-        // - Half of TX FIFO size (configured by DIEPTXF)
-
-        uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos;
-
-        // Process every single packet (only whole packets can be written to fifo)
-        for(uint16_t i = 0; i < remaining_packets; i++)
-        {
-          uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
-
-          // Packet can not be larger than ep max size
-          uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
-
-          // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
-          // EP has to be checked if the buffer can take another WHOLE packet
-          if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break;
-
-          // Push packet to Tx-FIFO
-          if (xfer->ff)
-          {
-            usb_fifo_t tx_fifo = FIFO_BASE(rhport, n);
-            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
-          }
-          else
-          {
-            write_fifo_packet(rhport, n, xfer->buffer, packet_size);
-
-            // Increment pointer to xfer data
-            xfer->buffer += packet_size;
-          }
-        }
-
-        // Turn off TXFE if all bytes are written.
-        if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0)
-        {
-          dev->DIEPEMPMSK &= ~(1 << n);
-        }
-      }
-    }
-  }
-}
-
-void dcd_int_handler(uint8_t rhport)
-{
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
-
-  if(int_status & USB_OTG_GINTSTS_USBRST)
-  {
-    // USBRST is start of reset.
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST;
-    bus_reset(rhport);
-  }
-
-  if(int_status & USB_OTG_GINTSTS_ENUMDNE)
-  {
-    // ENUMDNE is the end of reset where speed of the link is detected
-
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
-
-    tusb_speed_t const speed = get_speed(rhport);
-
-    set_turnaround(usb_otg, speed);
-    dcd_event_bus_reset(rhport, speed, true);
-  }
-
-  if(int_status & USB_OTG_GINTSTS_USBSUSP)
-  {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP;
-    dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-  }
-
-  if(int_status & USB_OTG_GINTSTS_WKUINT)
-  {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT;
-    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-  }
-
-  // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection
-  // if(int_status & USB_OTG_GINTSTS_DISCINT)
-
-  if(int_status & USB_OTG_GINTSTS_OTGINT)
-  {
-    // OTG INT bit is read-only
-    uint32_t const otg_int = usb_otg->GOTGINT;
-
-    if (otg_int & USB_OTG_GOTGINT_SEDET)
-    {
-      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-    }
-
-    usb_otg->GOTGINT = otg_int;
-  }
-
-  if(int_status & USB_OTG_GINTSTS_SOF)
-  {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
-
-    // Disable SOF interrupt since currently only used for remote wakeup detection
-    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM;
-
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-  }
-
-  // RxFIFO non-empty interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_RXFLVL)
-  {
-    // RXFLVL bit is read-only
-
-    // Mask out RXFLVL while reading data from FIFO
-    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
-
-    // Loop until all available packets were handled
-    do
-    {
-      handle_rxflvl_ints(rhport, out_ep);
-    } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL);
-
-    // Manage RX FIFO size
-    if (_out_ep_closed)
-    {
-      update_grxfsiz(rhport);
-
-      // Disable flag
-      _out_ep_closed = false;
-    }
-
-    usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
-  }
-
-  // OUT endpoint interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_OEPINT)
-  {
-    // OEPINT is read-only
-    handle_epout_ints(rhport, dev, out_ep);
-  }
-
-  // IN endpoint interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_IEPINT)
-  {
-    // IEPINT bit read-only
-    handle_epin_ints(rhport, dev, in_ep);
-  }
-
-  //  // Check for Incomplete isochronous IN transfer
-  //  if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
-  //    printf("      IISOIXFR!\r\n");
-  ////    TU_LOG2("      IISOIXFR!\r\n");
-  //  }
-}
-
-#endif
diff --git a/src/portable/st/synopsys/synopsys_common.h b/src/portable/st/synopsys/synopsys_common.h
deleted file mode 100644
index 6f0602fe9..000000000
--- a/src/portable/st/synopsys/synopsys_common.h
+++ /dev/null
@@ -1,1465 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    synopsys_common.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device USB OTG peripheral Header File. 
-  *          This file contains the USB OTG peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32F1xx devices.
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for the USB OTG peripheral
-  *           - The Peripheral's registers declarations and bits definition
-  *           - Macros to access the peripheral's registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-#include "stdint.h"
-
-#pragma once
-
-#ifdef __cplusplus
-  #define   __I   volatile
-#else
-  #define   __I   volatile const
-#endif
-#define     __O   volatile
-#define     __IO  volatile
-#define     __IM  volatile const
-#define     __OM  volatile
-#define     __IOM volatile
-
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register       Address offset: 000h */
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                Address offset: 004h */
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register           Address offset: 008h */
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register           Address offset: 00Ch */
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                       Address offset: 010h */
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                   Address offset: 014h */
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register              Address offset: 018h */
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register               Address offset: 01Ch */
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register         Address offset: 020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                 Address offset: 024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register  Address offset: 028h */
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg        Address offset: 02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved 030h*/
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                Address offset: 038h */
-  __IO uint32_t CID;                  /*!< User ID Register                           Address offset: 03Ch */
-  uint32_t  Reserved40[48];           /*!< Reserved 040h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg             Address offset: 100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                 Address offset: 0x104 */
-} USB_OTG_GlobalTypeDef;
-
-/** 
-  * @brief __device_Registers
-  */
-
-typedef struct 
-{
-  __IO uint32_t DCFG;                 /*!< dev Configuration Register                 Address offset: 800h*/
-  __IO uint32_t DCTL;                 /*!< dev Control Register                       Address offset: 804h*/
-  __IO uint32_t DSTS;                 /*!< dev Status Register (RO)                   Address offset: 808h*/
-  uint32_t Reserved0C;                /*!< Reserved 80Ch*/
-  __IO uint32_t DIEPMSK;              /*!< dev IN Endpoint Mask                       Address offset: 810h*/
-  __IO uint32_t DOEPMSK;              /*!< dev OUT Endpoint Mask                      Address offset: 814h*/
-  __IO uint32_t DAINT;                /*!< dev All Endpoints Itr Reg                  Address offset: 818h*/
-  __IO uint32_t DAINTMSK;             /*!< dev All Endpoints Itr Mask                 Address offset: 81Ch*/
-  uint32_t  Reserved20;               /*!< Reserved 820h*/
-  uint32_t Reserved9;                 /*!< Reserved 824h*/
-  __IO uint32_t DVBUSDIS;             /*!< dev VBUS discharge Register                Address offset: 828h*/
-  __IO uint32_t DVBUSPULSE;           /*!< dev VBUS Pulse Register                    Address offset: 82Ch*/
-  __IO uint32_t DTHRCTL;              /*!< dev thr                                    Address offset: 830h*/
-  __IO uint32_t DIEPEMPMSK;           /*!< dev empty msk                              Address offset: 834h*/
-  __IO uint32_t DEACHINT;             /*!< dedicated EP interrupt                     Address offset: 838h*/
-  __IO uint32_t DEACHMSK;             /*!< dedicated EP msk                           Address offset: 83Ch*/  
-  uint32_t Reserved40;                /*!< dedicated EP mask                          Address offset: 840h*/
-  __IO uint32_t DINEP1MSK;            /*!< dedicated EP mask                          Address offset: 844h*/
-  uint32_t  Reserved44[15];           /*!< Reserved 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK;           /*!< dedicated EP msk                           Address offset: 884h*/
-} USB_OTG_DeviceTypeDef;
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;              /*!< dev IN Endpoint Control Reg                900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;                /*!< Reserved                                   900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT;              /*!< dev IN Endpoint Itr Reg                    900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;                /*!< Reserved                                   900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ;             /*!< IN Endpoint Txfer Size                     900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA;              /*!< IN Endpoint DMA Address Reg                900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;              /*!< IN Endpoint Tx FIFO Status Reg             900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;                /*!< Reserved                                   900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-} USB_OTG_INEndpointTypeDef;
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;              /*!< dev OUT Endpoint Control Reg               B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;                /*!< Reserved                                   B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;              /*!< dev OUT Endpoint Itr Reg                   B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;                /*!< Reserved                                   B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;             /*!< dev OUT Endpoint Txfer Size                B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;              /*!< dev OUT Endpoint DMA Address               B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];             /*!< Reserved                                   B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-} USB_OTG_OUTEndpointTypeDef;
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-
-typedef struct 
-{
-  __IO uint32_t HCFG;                 /*!< Host Configuration Register    400h*/
-  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;               /*!< Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask 418h*/
-} USB_OTG_HostTypeDef;
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-} USB_OTG_HostChannelTypeDef;
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
-
-#define USB_OTG_GLOBAL_BASE                  0x00000000UL
-#define USB_OTG_DEVICE_BASE                  0x00000800UL
-#define USB_OTG_IN_ENDPOINT_BASE             0x00000900UL
-#define USB_OTG_OUT_ENDPOINT_BASE            0x00000B00UL
-#define USB_OTG_EP_REG_SIZE                  0x00000020UL
-#define USB_OTG_HOST_BASE                    0x00000400UL
-#define USB_OTG_HOST_PORT_BASE               0x00000440UL
-#define USB_OTG_HOST_CHANNEL_BASE            0x00000500UL
-#define USB_OTG_HOST_CHANNEL_SIZE            0x00000020UL
-#define USB_OTG_PCGCCTL_BASE                 0x00000E00UL
-#define USB_OTG_FIFO_BASE                    0x00001000UL
-#define USB_OTG_FIFO_SIZE                    0x00001000UL
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 USB_OTG                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS_Pos              (0U)                           
-#define USB_OTG_GOTGCTL_SRQSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_GOTGCTL_SRQSCS                  USB_OTG_GOTGCTL_SRQSCS_Msk     /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ_Pos                 (1U)                           
-#define USB_OTG_GOTGCTL_SRQ_Msk                 (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
-#define USB_OTG_GOTGCTL_SRQ                     USB_OTG_GOTGCTL_SRQ_Msk        /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS_Pos              (8U)                           
-#define USB_OTG_GOTGCTL_HNGSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ_Pos               (9U)                           
-#define USB_OTG_GOTGCTL_HNPRQ_Msk               (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGCTL_HNPRQ                   USB_OTG_GOTGCTL_HNPRQ_Msk      /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN_Pos             (10U)                          
-#define USB_OTG_GOTGCTL_HSHNPEN_Msk             (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_GOTGCTL_HSHNPEN                 USB_OTG_GOTGCTL_HSHNPEN_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN_Pos              (11U)                          
-#define USB_OTG_GOTGCTL_DHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
-#define USB_OTG_GOTGCTL_DHNPEN                  USB_OTG_GOTGCTL_DHNPEN_Msk     /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS_Pos              (16U)                          
-#define USB_OTG_GOTGCTL_CIDSTS_Msk              (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
-#define USB_OTG_GOTGCTL_CIDSTS                  USB_OTG_GOTGCTL_CIDSTS_Msk     /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT_Pos                (17U)                          
-#define USB_OTG_GOTGCTL_DBCT_Msk                (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGCTL_DBCT                    USB_OTG_GOTGCTL_DBCT_Msk       /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD_Pos               (18U)                          
-#define USB_OTG_GOTGCTL_ASVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGCTL_ASVLD                   USB_OTG_GOTGCTL_ASVLD_Msk      /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD_Pos               (19U)                          
-#define USB_OTG_GOTGCTL_BSVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGCTL_BSVLD                   USB_OTG_GOTGCTL_BSVLD_Msk      /*!< B-session valid */
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS_Pos                (0U)                           
-#define USB_OTG_HCFG_FSLSPCS_Msk                (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
-#define USB_OTG_HCFG_FSLSPCS                    USB_OTG_HCFG_FSLSPCS_Msk       /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0                  (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCFG_FSLSPCS_1                  (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCFG_FSLSS_Pos                  (2U)                           
-#define USB_OTG_HCFG_FSLSS_Msk                  (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCFG_FSLSS                      USB_OTG_HCFG_FSLSS_Msk         /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD_Pos                   (0U)                           
-#define USB_OTG_DCFG_DSPD_Msk                   (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
-#define USB_OTG_DCFG_DSPD                       USB_OTG_DCFG_DSPD_Msk          /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                     (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCFG_DSPD_1                     (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCFG_NZLSOHSK_Pos               (2U)                           
-#define USB_OTG_DCFG_NZLSOHSK_Msk               (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCFG_NZLSOHSK                   USB_OTG_DCFG_NZLSOHSK_Msk      /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD_Pos                    (4U)                           
-#define USB_OTG_DCFG_DAD_Msk                    (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                        USB_OTG_DCFG_DAD_Msk           /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                      (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCFG_DAD_1                      (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCFG_DAD_2                      (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCFG_DAD_3                      (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCFG_DAD_4                      (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCFG_DAD_5                      (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCFG_DAD_6                      (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
-
-#define USB_OTG_DCFG_PFIVL_Pos                  (11U)                          
-#define USB_OTG_DCFG_PFIVL_Msk                  (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                      USB_OTG_DCFG_PFIVL_Msk         /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                    (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCFG_PFIVL_1                    (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
-
-#define USB_OTG_DCFG_PERSCHIVL_Pos              (24U)                          
-#define USB_OTG_DCFG_PERSCHIVL_Msk              (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                  USB_OTG_DCFG_PERSCHIVL_Msk     /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0                (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
-#define USB_OTG_DCFG_PERSCHIVL_1                (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK_Pos               (0U)                           
-#define USB_OTG_PCGCR_STPPCLK_Msk               (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCR_STPPCLK                   USB_OTG_PCGCR_STPPCLK_Msk      /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK_Pos              (1U)                           
-#define USB_OTG_PCGCR_GATEHCLK_Msk              (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCR_GATEHCLK                  USB_OTG_PCGCR_GATEHCLK_Msk     /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP_Pos               (4U)                           
-#define USB_OTG_PCGCR_PHYSUSP_Msk               (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCR_PHYSUSP                   USB_OTG_PCGCR_PHYSUSP_Msk      /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET_Pos               (2U)                           
-#define USB_OTG_GOTGINT_SEDET_Msk               (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
-#define USB_OTG_GOTGINT_SEDET                   USB_OTG_GOTGINT_SEDET_Msk      /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG_Pos             (8U)                           
-#define USB_OTG_GOTGINT_SRSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGINT_SRSSCHG                 USB_OTG_GOTGINT_SRSSCHG_Msk    /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG_Pos             (9U)                           
-#define USB_OTG_GOTGINT_HNSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGINT_HNSSCHG                 USB_OTG_GOTGINT_HNSSCHG_Msk    /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET_Pos              (17U)                          
-#define USB_OTG_GOTGINT_HNGDET_Msk              (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGINT_HNGDET                  USB_OTG_GOTGINT_HNGDET_Msk     /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG_Pos             (18U)                          
-#define USB_OTG_GOTGINT_ADTOCHG_Msk             (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGINT_ADTOCHG                 USB_OTG_GOTGINT_ADTOCHG_Msk    /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE_Pos              (19U)                          
-#define USB_OTG_GOTGINT_DBCDNE_Msk              (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGINT_DBCDNE                  USB_OTG_GOTGINT_DBCDNE_Msk     /*!< Debounce done */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG_Pos                 (0U)                           
-#define USB_OTG_DCTL_RWUSIG_Msk                 (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCTL_RWUSIG                     USB_OTG_DCTL_RWUSIG_Msk        /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS_Pos                   (1U)                           
-#define USB_OTG_DCTL_SDIS_Msk                   (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCTL_SDIS                       USB_OTG_DCTL_SDIS_Msk          /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS_Pos                 (2U)                           
-#define USB_OTG_DCTL_GINSTS_Msk                 (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCTL_GINSTS                     USB_OTG_DCTL_GINSTS_Msk        /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS_Pos                 (3U)                           
-#define USB_OTG_DCTL_GONSTS_Msk                 (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
-#define USB_OTG_DCTL_GONSTS                     USB_OTG_DCTL_GONSTS_Msk        /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL_Pos                   (4U)                           
-#define USB_OTG_DCTL_TCTL_Msk                   (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
-#define USB_OTG_DCTL_TCTL                       USB_OTG_DCTL_TCTL_Msk          /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                     (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCTL_TCTL_1                     (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCTL_TCTL_2                     (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCTL_SGINAK_Pos                 (7U)                           
-#define USB_OTG_DCTL_SGINAK_Msk                 (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCTL_SGINAK                     USB_OTG_DCTL_SGINAK_Msk        /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK_Pos                 (8U)                           
-#define USB_OTG_DCTL_CGINAK_Msk                 (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCTL_CGINAK                     USB_OTG_DCTL_CGINAK_Msk        /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK_Pos                 (9U)                           
-#define USB_OTG_DCTL_SGONAK_Msk                 (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCTL_SGONAK                     USB_OTG_DCTL_SGONAK_Msk        /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK_Pos                 (10U)                          
-#define USB_OTG_DCTL_CGONAK_Msk                 (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
-#define USB_OTG_DCTL_CGONAK                     USB_OTG_DCTL_CGONAK_Msk        /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE_Pos               (11U)                          
-#define USB_OTG_DCTL_POPRGDNE_Msk               (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCTL_POPRGDNE                   USB_OTG_DCTL_POPRGDNE_Msk      /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL_Pos                  (0U)                           
-#define USB_OTG_HFIR_FRIVL_Msk                  (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFIR_FRIVL                      USB_OTG_HFIR_FRIVL_Msk         /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM_Pos                 (0U)                           
-#define USB_OTG_HFNUM_FRNUM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFNUM_FRNUM                     USB_OTG_HFNUM_FRNUM_Msk        /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM_Pos                 (16U)                          
-#define USB_OTG_HFNUM_FTREM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HFNUM_FTREM                     USB_OTG_HFNUM_FTREM_Msk        /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS_Pos                (0U)                           
-#define USB_OTG_DSTS_SUSPSTS_Msk                (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_DSTS_SUSPSTS                    USB_OTG_DSTS_SUSPSTS_Msk       /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD_Pos                (1U)                           
-#define USB_OTG_DSTS_ENUMSPD_Msk                (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
-#define USB_OTG_DSTS_ENUMSPD                    USB_OTG_DSTS_ENUMSPD_Msk       /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0                  (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DSTS_ENUMSPD_1                  (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
-#define USB_OTG_DSTS_EERR_Pos                   (3U)                           
-#define USB_OTG_DSTS_EERR_Msk                   (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
-#define USB_OTG_DSTS_EERR                       USB_OTG_DSTS_EERR_Msk          /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF_Pos                  (8U)                           
-#define USB_OTG_DSTS_FNSOF_Msk                  (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
-#define USB_OTG_DSTS_FNSOF                      USB_OTG_DSTS_FNSOF_Msk         /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT_Pos                (0U)                           
-#define USB_OTG_GAHBCFG_GINT_Msk                (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
-#define USB_OTG_GAHBCFG_GINT                    USB_OTG_GAHBCFG_GINT_Msk       /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)                           
-#define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
-#define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
-#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
-#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
-#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
-#define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)                           
-#define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL_Pos             (7U)                           
-#define USB_OTG_GAHBCFG_TXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
-#define USB_OTG_GAHBCFG_TXFELVL                 USB_OTG_GAHBCFG_TXFELVL_Msk    /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL_Pos            (8U)                           
-#define USB_OTG_GAHBCFG_PTXFELVL_Msk            (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
-#define USB_OTG_GAHBCFG_PTXFELVL                USB_OTG_GAHBCFG_PTXFELVL_Msk   /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL_Pos               (0U)                           
-#define USB_OTG_GUSBCFG_TOCAL_Msk               (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
-#define USB_OTG_GUSBCFG_TOCAL                   USB_OTG_GUSBCFG_TOCAL_Msk      /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
-#define USB_OTG_GUSBCFG_PHYSEL_Pos              (6U)                           
-#define USB_OTG_GUSBCFG_PHYSEL_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
-#define USB_OTG_GUSBCFG_PHYSEL                  USB_OTG_GUSBCFG_PHYSEL_Msk     /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP_Pos              (8U)                           
-#define USB_OTG_GUSBCFG_SRPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
-#define USB_OTG_GUSBCFG_SRPCAP                  USB_OTG_GUSBCFG_SRPCAP_Msk     /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP_Pos              (9U)                           
-#define USB_OTG_GUSBCFG_HNPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
-#define USB_OTG_GUSBCFG_HNPCAP                  USB_OTG_GUSBCFG_HNPCAP_Msk     /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT_Pos                (10U)                          
-#define USB_OTG_GUSBCFG_TRDT_Msk                (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
-#define USB_OTG_GUSBCFG_TRDT                    USB_OTG_GUSBCFG_TRDT_Msk       /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
-#define USB_OTG_GUSBCFG_TRDT_1                  (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
-#define USB_OTG_GUSBCFG_TRDT_2                  (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
-#define USB_OTG_GUSBCFG_TRDT_3                  (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
-#define USB_OTG_GUSBCFG_PHYLPCS_Pos             (15U)                          
-#define USB_OTG_GUSBCFG_PHYLPCS_Msk             (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 USB_OTG_GUSBCFG_PHYLPCS_Msk    /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS_Pos            (17U)                          
-#define USB_OTG_GUSBCFG_ULPIFSLS_Msk            (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
-#define USB_OTG_GUSBCFG_ULPIFSLS                USB_OTG_GUSBCFG_ULPIFSLS_Msk   /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR_Pos              (18U)                          
-#define USB_OTG_GUSBCFG_ULPIAR_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
-#define USB_OTG_GUSBCFG_ULPIAR                  USB_OTG_GUSBCFG_ULPIAR_Msk     /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM_Pos             (19U)                          
-#define USB_OTG_GUSBCFG_ULPICSM_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
-#define USB_OTG_GUSBCFG_ULPICSM                 USB_OTG_GUSBCFG_ULPICSM_Msk    /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos          (20U)                          
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos          (21U)                          
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS_Pos               (22U)                          
-#define USB_OTG_GUSBCFG_TSDPS_Msk               (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
-#define USB_OTG_GUSBCFG_TSDPS                   USB_OTG_GUSBCFG_TSDPS_Msk      /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI_Pos                (23U)                          
-#define USB_OTG_GUSBCFG_PCCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
-#define USB_OTG_GUSBCFG_PCCI                    USB_OTG_GUSBCFG_PCCI_Msk       /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI_Pos                (24U)                          
-#define USB_OTG_GUSBCFG_PTCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
-#define USB_OTG_GUSBCFG_PTCI                    USB_OTG_GUSBCFG_PTCI_Msk       /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD_Pos             (25U)                          
-#define USB_OTG_GUSBCFG_ULPIIPD_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
-#define USB_OTG_GUSBCFG_ULPIIPD                 USB_OTG_GUSBCFG_ULPIIPD_Msk    /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD_Pos               (29U)                          
-#define USB_OTG_GUSBCFG_FHMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
-#define USB_OTG_GUSBCFG_FHMOD                   USB_OTG_GUSBCFG_FHMOD_Msk      /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD_Pos               (30U)                          
-#define USB_OTG_GUSBCFG_FDMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
-#define USB_OTG_GUSBCFG_FDMOD                   USB_OTG_GUSBCFG_FDMOD_Msk      /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT_Pos              (31U)                          
-#define USB_OTG_GUSBCFG_CTXPKT_Msk              (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                  USB_OTG_GUSBCFG_CTXPKT_Msk     /*!< Corrupt Tx packet */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST_Pos               (0U)                           
-#define USB_OTG_GRSTCTL_CSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
-#define USB_OTG_GRSTCTL_CSRST                   USB_OTG_GRSTCTL_CSRST_Msk      /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST_Pos               (1U)                           
-#define USB_OTG_GRSTCTL_HSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
-#define USB_OTG_GRSTCTL_HSRST                   USB_OTG_GRSTCTL_HSRST_Msk      /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST_Pos               (2U)                           
-#define USB_OTG_GRSTCTL_FCRST_Msk               (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
-#define USB_OTG_GRSTCTL_FCRST                   USB_OTG_GRSTCTL_FCRST_Msk      /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH_Pos             (4U)                           
-#define USB_OTG_GRSTCTL_RXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
-#define USB_OTG_GRSTCTL_RXFFLSH                 USB_OTG_GRSTCTL_RXFFLSH_Msk    /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH_Pos             (5U)                           
-#define USB_OTG_GRSTCTL_TXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
-#define USB_OTG_GRSTCTL_TXFFLSH                 USB_OTG_GRSTCTL_TXFFLSH_Msk    /*!< TxFIFO flush */
-
-
-#define USB_OTG_GRSTCTL_TXFNUM_Pos              (6U)                           
-#define USB_OTG_GRSTCTL_TXFNUM_Msk              (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
-#define USB_OTG_GRSTCTL_TXFNUM                  USB_OTG_GRSTCTL_TXFNUM_Msk     /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GRSTCTL_DMAREQ_Pos              (30U)                          
-#define USB_OTG_GRSTCTL_DMAREQ_Msk              (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
-#define USB_OTG_GRSTCTL_DMAREQ                  USB_OTG_GRSTCTL_DMAREQ_Msk     /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL_Pos              (31U)                          
-#define USB_OTG_GRSTCTL_AHBIDL_Msk              (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
-#define USB_OTG_GRSTCTL_AHBIDL                  USB_OTG_GRSTCTL_AHBIDL_Msk     /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM_Pos               (0U)                           
-#define USB_OTG_DIEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPMSK_XFRCM                   USB_OTG_DIEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM_Pos                (1U)                           
-#define USB_OTG_DIEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPMSK_EPDM                    USB_OTG_DIEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM_Pos                 (3U)                           
-#define USB_OTG_DIEPMSK_TOM_Msk                 (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPMSK_TOM                     USB_OTG_DIEPMSK_TOM_Msk        /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos           (4U)                           
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk           (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               USB_OTG_DIEPMSK_ITTXFEMSK_Msk  /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM_Pos             (5U)                           
-#define USB_OTG_DIEPMSK_INEPNMM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPMSK_INEPNMM                 USB_OTG_DIEPMSK_INEPNMM_Msk    /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM_Pos             (6U)                           
-#define USB_OTG_DIEPMSK_INEPNEM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPMSK_INEPNEM                 USB_OTG_DIEPMSK_INEPNEM_Msk    /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM_Pos              (8U)                           
-#define USB_OTG_DIEPMSK_TXFURM_Msk              (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPMSK_TXFURM                  USB_OTG_DIEPMSK_TXFURM_Msk     /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM_Pos                 (9U)                           
-#define USB_OTG_DIEPMSK_BIM_Msk                 (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPMSK_BIM                     USB_OTG_DIEPMSK_BIM_Msk        /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL_Pos            (0U)                           
-#define USB_OTG_HPTXSTS_PTXFSAVL_Msk            (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXSTS_PTXFSAVL                USB_OTG_HPTXSTS_PTXFSAVL_Msk   /*!< Periodic transmit data FIFO space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_Pos             (16U)                          
-#define USB_OTG_HPTXSTS_PTXQSAV_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_HPTXSTS_PTXQSAV                 USB_OTG_HPTXSTS_PTXQSAV_Msk    /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP_Pos             (24U)                          
-#define USB_OTG_HPTXSTS_PTXQTOP_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP                 USB_OTG_HPTXSTS_PTXQTOP_Msk    /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT_Pos                 (0U)                           
-#define USB_OTG_HAINT_HAINT_Msk                 (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINT_HAINT                     USB_OTG_HAINT_HAINT_Msk        /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM_Pos               (0U)                           
-#define USB_OTG_DOEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPMSK_XFRCM                   USB_OTG_DOEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM_Pos                (1U)                           
-#define USB_OTG_DOEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPMSK_EPDM                    USB_OTG_DOEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
-#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
-#define USB_OTG_DOEPMSK_STUPM_Pos               (3U)                           
-#define USB_OTG_DOEPMSK_STUPM_Msk               (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPMSK_STUPM                   USB_OTG_DOEPMSK_STUPM_Msk      /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM_Pos              (4U)                           
-#define USB_OTG_DOEPMSK_OTEPDM_Msk              (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPMSK_OTEPDM                  USB_OTG_DOEPMSK_OTEPDM_Msk     /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
-#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP_Pos             (6U)                           
-#define USB_OTG_DOEPMSK_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPMSK_B2BSTUP                 USB_OTG_DOEPMSK_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM_Pos                (8U)                           
-#define USB_OTG_DOEPMSK_OPEM_Msk                (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPMSK_OPEM                    USB_OTG_DOEPMSK_OPEM_Msk       /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM_Pos                (9U)                           
-#define USB_OTG_DOEPMSK_BOIM_Msk                (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPMSK_BOIM                    USB_OTG_DOEPMSK_BOIM_Msk       /*!< BNA interrupt mask */
-#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
-#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
-#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
-#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
-#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
-#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD_Pos                (0U)                           
-#define USB_OTG_GINTSTS_CMOD_Msk                (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
-#define USB_OTG_GINTSTS_CMOD                    USB_OTG_GINTSTS_CMOD_Msk       /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS_Pos                (1U)                           
-#define USB_OTG_GINTSTS_MMIS_Msk                (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTSTS_MMIS                    USB_OTG_GINTSTS_MMIS_Msk       /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT_Pos              (2U)                           
-#define USB_OTG_GINTSTS_OTGINT_Msk              (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTSTS_OTGINT                  USB_OTG_GINTSTS_OTGINT_Msk     /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF_Pos                 (3U)                           
-#define USB_OTG_GINTSTS_SOF_Msk                 (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTSTS_SOF                     USB_OTG_GINTSTS_SOF_Msk        /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL_Pos              (4U)                           
-#define USB_OTG_GINTSTS_RXFLVL_Msk              (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTSTS_RXFLVL                  USB_OTG_GINTSTS_RXFLVL_Msk     /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE_Pos              (5U)                           
-#define USB_OTG_GINTSTS_NPTXFE_Msk              (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTSTS_NPTXFE                  USB_OTG_GINTSTS_NPTXFE_Msk     /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF_Pos            (6U)                           
-#define USB_OTG_GINTSTS_GINAKEFF_Msk            (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTSTS_GINAKEFF                USB_OTG_GINTSTS_GINAKEFF_Msk   /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos          (7U)                           
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk          (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP_Pos               (10U)                          
-#define USB_OTG_GINTSTS_ESUSP_Msk               (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTSTS_ESUSP                   USB_OTG_GINTSTS_ESUSP_Msk      /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP_Pos             (11U)                          
-#define USB_OTG_GINTSTS_USBSUSP_Msk             (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTSTS_USBSUSP                 USB_OTG_GINTSTS_USBSUSP_Msk    /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST_Pos              (12U)                          
-#define USB_OTG_GINTSTS_USBRST_Msk              (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTSTS_USBRST                  USB_OTG_GINTSTS_USBRST_Msk     /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE_Pos             (13U)                          
-#define USB_OTG_GINTSTS_ENUMDNE_Msk             (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTSTS_ENUMDNE                 USB_OTG_GINTSTS_ENUMDNE_Msk    /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP_Pos             (14U)                          
-#define USB_OTG_GINTSTS_ISOODRP_Msk             (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTSTS_ISOODRP                 USB_OTG_GINTSTS_ISOODRP_Msk    /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF_Pos                (15U)                          
-#define USB_OTG_GINTSTS_EOPF_Msk                (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTSTS_EOPF                    USB_OTG_GINTSTS_EOPF_Msk       /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT_Pos              (18U)                          
-#define USB_OTG_GINTSTS_IEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTSTS_IEPINT                  USB_OTG_GINTSTS_IEPINT_Msk     /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT_Pos              (19U)                          
-#define USB_OTG_GINTSTS_OEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTSTS_OEPINT                  USB_OTG_GINTSTS_OEPINT_Msk     /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR_Pos            (20U)                          
-#define USB_OTG_GINTSTS_IISOIXFR_Msk            (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTSTS_IISOIXFR                USB_OTG_GINTSTS_IISOIXFR_Msk   /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)                          
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP_Pos           (22U)                          
-#define USB_OTG_GINTSTS_DATAFSUSP_Msk           (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTSTS_DATAFSUSP               USB_OTG_GINTSTS_DATAFSUSP_Msk  /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT_Pos             (24U)                          
-#define USB_OTG_GINTSTS_HPRTINT_Msk             (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTSTS_HPRTINT                 USB_OTG_GINTSTS_HPRTINT_Msk    /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT_Pos               (25U)                          
-#define USB_OTG_GINTSTS_HCINT_Msk               (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTSTS_HCINT                   USB_OTG_GINTSTS_HCINT_Msk      /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE_Pos               (26U)                          
-#define USB_OTG_GINTSTS_PTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTSTS_PTXFE                   USB_OTG_GINTSTS_PTXFE_Msk      /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG_Pos             (28U)                          
-#define USB_OTG_GINTSTS_CIDSCHG_Msk             (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTSTS_CIDSCHG                 USB_OTG_GINTSTS_CIDSCHG_Msk    /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT_Pos             (29U)                          
-#define USB_OTG_GINTSTS_DISCINT_Msk             (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTSTS_DISCINT                 USB_OTG_GINTSTS_DISCINT_Msk    /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT_Pos              (30U)                          
-#define USB_OTG_GINTSTS_SRQINT_Msk              (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTSTS_SRQINT                  USB_OTG_GINTSTS_SRQINT_Msk     /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT_Pos              (31U)                          
-#define USB_OTG_GINTSTS_WKUINT_Msk              (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTSTS_WKUINT                  USB_OTG_GINTSTS_WKUINT_Msk     /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM_Pos               (1U)                           
-#define USB_OTG_GINTMSK_MMISM_Msk               (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTMSK_MMISM                   USB_OTG_GINTMSK_MMISM_Msk      /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT_Pos              (2U)                           
-#define USB_OTG_GINTMSK_OTGINT_Msk              (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTMSK_OTGINT                  USB_OTG_GINTMSK_OTGINT_Msk     /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM_Pos                (3U)                           
-#define USB_OTG_GINTMSK_SOFM_Msk                (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTMSK_SOFM                    USB_OTG_GINTMSK_SOFM_Msk       /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM_Pos             (4U)                           
-#define USB_OTG_GINTMSK_RXFLVLM_Msk             (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTMSK_RXFLVLM                 USB_OTG_GINTMSK_RXFLVLM_Msk    /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM_Pos             (5U)                           
-#define USB_OTG_GINTMSK_NPTXFEM_Msk             (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTMSK_NPTXFEM                 USB_OTG_GINTMSK_NPTXFEM_Msk    /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM_Pos           (6U)                           
-#define USB_OTG_GINTMSK_GINAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTMSK_GINAKEFFM               USB_OTG_GINTMSK_GINAKEFFM_Msk  /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM_Pos           (7U)                           
-#define USB_OTG_GINTMSK_GONAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTMSK_GONAKEFFM               USB_OTG_GINTMSK_GONAKEFFM_Msk  /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM_Pos              (10U)                          
-#define USB_OTG_GINTMSK_ESUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTMSK_ESUSPM                  USB_OTG_GINTMSK_ESUSPM_Msk     /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM_Pos            (11U)                          
-#define USB_OTG_GINTMSK_USBSUSPM_Msk            (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTMSK_USBSUSPM                USB_OTG_GINTMSK_USBSUSPM_Msk   /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST_Pos              (12U)                          
-#define USB_OTG_GINTMSK_USBRST_Msk              (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTMSK_USBRST                  USB_OTG_GINTMSK_USBRST_Msk     /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM_Pos            (13U)                          
-#define USB_OTG_GINTMSK_ENUMDNEM_Msk            (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTMSK_ENUMDNEM                USB_OTG_GINTMSK_ENUMDNEM_Msk   /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM_Pos            (14U)                          
-#define USB_OTG_GINTMSK_ISOODRPM_Msk            (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTMSK_ISOODRPM                USB_OTG_GINTMSK_ISOODRPM_Msk   /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM_Pos               (15U)                          
-#define USB_OTG_GINTMSK_EOPFM_Msk               (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTMSK_EOPFM                   USB_OTG_GINTMSK_EOPFM_Msk      /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM_Pos              (17U)                          
-#define USB_OTG_GINTMSK_EPMISM_Msk              (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
-#define USB_OTG_GINTMSK_EPMISM                  USB_OTG_GINTMSK_EPMISM_Msk     /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT_Pos              (18U)                          
-#define USB_OTG_GINTMSK_IEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTMSK_IEPINT                  USB_OTG_GINTMSK_IEPINT_Msk     /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT_Pos              (19U)                          
-#define USB_OTG_GINTMSK_OEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTMSK_OEPINT                  USB_OTG_GINTMSK_OEPINT_Msk     /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM_Pos           (20U)                          
-#define USB_OTG_GINTMSK_IISOIXFRM_Msk           (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTMSK_IISOIXFRM               USB_OTG_GINTMSK_IISOIXFRM_Msk  /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos     (21U)                          
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk     (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM_Pos              (22U)                          
-#define USB_OTG_GINTMSK_FSUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTMSK_FSUSPM                  USB_OTG_GINTMSK_FSUSPM_Msk     /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM_Pos               (24U)                          
-#define USB_OTG_GINTMSK_PRTIM_Msk               (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTMSK_PRTIM                   USB_OTG_GINTMSK_PRTIM_Msk      /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM_Pos                (25U)                          
-#define USB_OTG_GINTMSK_HCIM_Msk                (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTMSK_HCIM                    USB_OTG_GINTMSK_HCIM_Msk       /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM_Pos              (26U)                          
-#define USB_OTG_GINTMSK_PTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTMSK_PTXFEM                  USB_OTG_GINTMSK_PTXFEM_Msk     /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM_Pos            (28U)                          
-#define USB_OTG_GINTMSK_CIDSCHGM_Msk            (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTMSK_CIDSCHGM                USB_OTG_GINTMSK_CIDSCHGM_Msk   /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT_Pos             (29U)                          
-#define USB_OTG_GINTMSK_DISCINT_Msk             (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTMSK_DISCINT                 USB_OTG_GINTMSK_DISCINT_Msk    /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM_Pos               (30U)                          
-#define USB_OTG_GINTMSK_SRQIM_Msk               (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTMSK_SRQIM                   USB_OTG_GINTMSK_SRQIM_Msk      /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM_Pos                (31U)                          
-#define USB_OTG_GINTMSK_WUIM_Msk                (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTMSK_WUIM                    USB_OTG_GINTMSK_WUIM_Msk       /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT_Pos                (0U)                           
-#define USB_OTG_DAINT_IEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINT_IEPINT                    USB_OTG_DAINT_IEPINT_Msk       /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT_Pos                (16U)                          
-#define USB_OTG_DAINT_OEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINT_OEPINT                    USB_OTG_DAINT_OEPINT_Msk       /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM_Pos             (0U)                           
-#define USB_OTG_HAINTMSK_HAINTM_Msk             (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINTMSK_HAINTM                 USB_OTG_HAINTMSK_HAINTM_Msk    /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM_Pos               (0U)                           
-#define USB_OTG_GRXSTSP_EPNUM_Msk               (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
-#define USB_OTG_GRXSTSP_EPNUM                   USB_OTG_GRXSTSP_EPNUM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT_Pos                (4U)                           
-#define USB_OTG_GRXSTSP_BCNT_Msk                (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
-#define USB_OTG_GRXSTSP_BCNT                    USB_OTG_GRXSTSP_BCNT_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID_Pos                (15U)                          
-#define USB_OTG_GRXSTSP_DPID_Msk                (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
-#define USB_OTG_GRXSTSP_DPID                    USB_OTG_GRXSTSP_DPID_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS_Pos              (17U)                          
-#define USB_OTG_GRXSTSP_PKTSTS_Msk              (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
-#define USB_OTG_GRXSTSP_PKTSTS                  USB_OTG_GRXSTSP_PKTSTS_Msk     /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM_Pos               (0U)                           
-#define USB_OTG_DAINTMSK_IEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINTMSK_IEPM                   USB_OTG_DAINTMSK_IEPM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM_Pos               (16U)                          
-#define USB_OTG_DAINTMSK_OEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINTMSK_OEPM                   USB_OTG_DAINTMSK_OEPM_Msk      /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD_Pos                (0U)                           
-#define USB_OTG_GRXFSIZ_RXFD_Msk                (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GRXFSIZ_RXFD                    USB_OTG_GRXFSIZ_RXFD_Msk       /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT_Pos             (0U)                           
-#define USB_OTG_DVBUSDIS_VBUSDT_Msk             (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DVBUSDIS_VBUSDT                 USB_OTG_DVBUSDIS_VBUSDT_Msk    /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA_Pos                     (0U)                           
-#define USB_OTG_NPTXFSA_Msk                     (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_NPTXFSA                         USB_OTG_NPTXFSA_Msk            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD_Pos                      (16U)                          
-#define USB_OTG_NPTXFD_Msk                      (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_NPTXFD                          USB_OTG_NPTXFD_Msk             /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA_Pos                      (0U)                           
-#define USB_OTG_TX0FSA_Msk                      (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_TX0FSA                          USB_OTG_TX0FSA_Msk             /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD_Pos                       (16U)                          
-#define USB_OTG_TX0FD_Msk                       (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_TX0FD                           USB_OTG_TX0FD_Msk              /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP_Pos           (0U)                           
-#define USB_OTG_DVBUSPULSE_DVBUSP_Msk           (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
-#define USB_OTG_DVBUSPULSE_DVBUSP               USB_OTG_DVBUSPULSE_DVBUSP_Msk  /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos           (0U)                           
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk           (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GNPTXSTS_NPTXFSAV               USB_OTG_GNPTXSTS_NPTXFSAV_Msk  /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos           (16U)                          
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk           (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV               USB_OTG_GNPTXSTS_NPTQXSAV_Msk  /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0             (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1             (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2             (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3             (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4             (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5             (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6             (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7             (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos           (24U)                          
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk           (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP               USB_OTG_GNPTXSTS_NPTXQTOP_Msk  /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0             (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1             (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2             (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3             (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4             (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5             (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6             (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN_Pos         (0U)                           
-#define USB_OTG_DTHRCTL_NONISOTHREN_Msk         (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
-#define USB_OTG_DTHRCTL_NONISOTHREN             USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN_Pos            (1U)                           
-#define USB_OTG_DTHRCTL_ISOTHREN_Msk            (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
-#define USB_OTG_DTHRCTL_ISOTHREN                USB_OTG_DTHRCTL_ISOTHREN_Msk   /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN_Pos            (2U)                           
-#define USB_OTG_DTHRCTL_TXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
-#define USB_OTG_DTHRCTL_TXTHRLEN                USB_OTG_DTHRCTL_TXTHRLEN_Msk   /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_DTHRCTL_RXTHREN_Pos             (16U)                          
-#define USB_OTG_DTHRCTL_RXTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
-#define USB_OTG_DTHRCTL_RXTHREN                 USB_OTG_DTHRCTL_RXTHREN_Msk    /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN_Pos            (17U)                          
-#define USB_OTG_DTHRCTL_RXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN                USB_OTG_DTHRCTL_RXTHRLEN_Msk   /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
-#define USB_OTG_DTHRCTL_ARPEN_Pos               (27U)                          
-#define USB_OTG_DTHRCTL_ARPEN_Msk               (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
-#define USB_OTG_DTHRCTL_ARPEN                   USB_OTG_DTHRCTL_ARPEN_Msk      /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos        (0U)                           
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk        (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM            USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT_Pos            (1U)                           
-#define USB_OTG_DEACHINT_IEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINT_IEP1INT                USB_OTG_DEACHINT_IEP1INT_Msk   /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT_Pos            (17U)                          
-#define USB_OTG_DEACHINT_OEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINT_OEP1INT                USB_OTG_DEACHINT_OEP1INT_Msk   /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN_Pos                (16U)                          
-#define USB_OTG_GCCFG_PWRDWN_Msk                (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
-#define USB_OTG_GCCFG_PWRDWN                    USB_OTG_GCCFG_PWRDWN_Msk       /*!< Power down */
-#define USB_OTG_GCCFG_VBUSASEN_Pos              (18U)                          
-#define USB_OTG_GCCFG_VBUSASEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_GCCFG_VBUSASEN                  USB_OTG_GCCFG_VBUSASEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN_Pos              (19U)                          
-#define USB_OTG_GCCFG_VBUSBSEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_GCCFG_VBUSBSEN                  USB_OTG_GCCFG_VBUSBSEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN_Pos              (20U)                          
-#define USB_OTG_GCCFG_SOFOUTEN_Msk              (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_GCCFG_SOFOUTEN                  USB_OTG_GCCFG_SOFOUTEN_Msk     /*!< SOF output enable */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos        (1U)                           
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINTMSK_IEP1INTM            USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos        (17U)                          
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINTMSK_OEP1INTM            USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID_Pos              (0U)                           
-#define USB_OTG_CID_PRODUCT_ID_Msk              (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_CID_PRODUCT_ID                  USB_OTG_CID_PRODUCT_ID_Msk     /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos          (0U)                           
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPEACHMSK1_XFRCM              USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM_Pos           (1U)                           
-#define USB_OTG_DIEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPEACHMSK1_EPDM               USB_OTG_DIEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM_Pos            (3U)                           
-#define USB_OTG_DIEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPEACHMSK1_TOM                USB_OTG_DIEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK          USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos        (5U)                           
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM            USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos        (6U)                           
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM            USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos         (8U)                           
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPEACHMSK1_TXFURM             USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM_Pos            (9U)                           
-#define USB_OTG_DIEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPEACHMSK1_BIM                USB_OTG_DIEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM_Pos           (13U)                          
-#define USB_OTG_DIEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPEACHMSK1_NAKM               USB_OTG_DIEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS_Pos                  (0U)                           
-#define USB_OTG_HPRT_PCSTS_Msk                  (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HPRT_PCSTS                      USB_OTG_HPRT_PCSTS_Msk         /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET_Pos                  (1U)                           
-#define USB_OTG_HPRT_PCDET_Msk                  (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
-#define USB_OTG_HPRT_PCDET                      USB_OTG_HPRT_PCDET_Msk         /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA_Pos                   (2U)                           
-#define USB_OTG_HPRT_PENA_Msk                   (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
-#define USB_OTG_HPRT_PENA                       USB_OTG_HPRT_PENA_Msk          /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG_Pos                (3U)                           
-#define USB_OTG_HPRT_PENCHNG_Msk                (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
-#define USB_OTG_HPRT_PENCHNG                    USB_OTG_HPRT_PENCHNG_Msk       /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA_Pos                   (4U)                           
-#define USB_OTG_HPRT_POCA_Msk                   (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
-#define USB_OTG_HPRT_POCA                       USB_OTG_HPRT_POCA_Msk          /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG_Pos                (5U)                           
-#define USB_OTG_HPRT_POCCHNG_Msk                (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
-#define USB_OTG_HPRT_POCCHNG                    USB_OTG_HPRT_POCCHNG_Msk       /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES_Pos                   (6U)                           
-#define USB_OTG_HPRT_PRES_Msk                   (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
-#define USB_OTG_HPRT_PRES                       USB_OTG_HPRT_PRES_Msk          /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP_Pos                  (7U)                           
-#define USB_OTG_HPRT_PSUSP_Msk                  (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
-#define USB_OTG_HPRT_PSUSP                      USB_OTG_HPRT_PSUSP_Msk         /*!< Port suspend */
-#define USB_OTG_HPRT_PRST_Pos                   (8U)                           
-#define USB_OTG_HPRT_PRST_Msk                   (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
-#define USB_OTG_HPRT_PRST                       USB_OTG_HPRT_PRST_Msk          /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS_Pos                  (10U)                          
-#define USB_OTG_HPRT_PLSTS_Msk                  (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
-#define USB_OTG_HPRT_PLSTS                      USB_OTG_HPRT_PLSTS_Msk         /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                    (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
-#define USB_OTG_HPRT_PLSTS_1                    (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_HPRT_PPWR_Pos                   (12U)                          
-#define USB_OTG_HPRT_PPWR_Msk                   (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HPRT_PPWR                       USB_OTG_HPRT_PPWR_Msk          /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL_Pos                  (13U)                          
-#define USB_OTG_HPRT_PTCTL_Msk                  (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
-#define USB_OTG_HPRT_PTCTL                      USB_OTG_HPRT_PTCTL_Msk         /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                    (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
-#define USB_OTG_HPRT_PTCTL_1                    (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
-#define USB_OTG_HPRT_PTCTL_2                    (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
-#define USB_OTG_HPRT_PTCTL_3                    (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
-
-#define USB_OTG_HPRT_PSPD_Pos                   (17U)                          
-#define USB_OTG_HPRT_PSPD_Msk                   (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
-#define USB_OTG_HPRT_PSPD                       USB_OTG_HPRT_PSPD_Msk          /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                     (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPRT_PSPD_1                     (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos          (0U)                           
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPEACHMSK1_XFRCM              USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM_Pos           (1U)                           
-#define USB_OTG_DOEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPEACHMSK1_EPDM               USB_OTG_DOEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM_Pos            (3U)                           
-#define USB_OTG_DOEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPEACHMSK1_TOM                USB_OTG_DOEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK          USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos        (5U)                           
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM            USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos        (6U)                           
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM            USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos         (8U)                           
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPEACHMSK1_TXFURM             USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM_Pos            (9U)                           
-#define USB_OTG_DOEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPEACHMSK1_BIM                USB_OTG_DOEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM_Pos          (12U)                          
-#define USB_OTG_DOEPEACHMSK1_BERRM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPEACHMSK1_BERRM              USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM_Pos           (13U)                          
-#define USB_OTG_DOEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPEACHMSK1_NAKM               USB_OTG_DOEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM_Pos          (14U)                          
-#define USB_OTG_DOEPEACHMSK1_NYETM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPEACHMSK1_NYETM              USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA_Pos              (0U)                           
-#define USB_OTG_HPTXFSIZ_PTXSA_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXFSIZ_PTXSA                  USB_OTG_HPTXFSIZ_PTXSA_Msk     /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD_Pos              (16U)                          
-#define USB_OTG_HPTXFSIZ_PTXFD_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HPTXFSIZ_PTXFD                  USB_OTG_HPTXFSIZ_PTXFD_Msk     /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ_Pos               (0U)                           
-#define USB_OTG_DIEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DIEPCTL_MPSIZ                   USB_OTG_DIEPCTL_MPSIZ_Msk      /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP_Pos              (15U)                          
-#define USB_OTG_DIEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DIEPCTL_USBAEP                  USB_OTG_DIEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID_Pos          (16U)                          
-#define USB_OTG_DIEPCTL_EONUM_DPID_Msk          (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
-#define USB_OTG_DIEPCTL_EONUM_DPID              USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS_Pos              (17U)                          
-#define USB_OTG_DIEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DIEPCTL_NAKSTS                  USB_OTG_DIEPCTL_NAKSTS_Msk     /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP_Pos               (18U)                          
-#define USB_OTG_DIEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DIEPCTL_EPTYP                   USB_OTG_DIEPCTL_EPTYP_Msk      /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DIEPCTL_STALL_Pos               (21U)                          
-#define USB_OTG_DIEPCTL_STALL_Msk               (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DIEPCTL_STALL                   USB_OTG_DIEPCTL_STALL_Msk      /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM_Pos              (22U)                          
-#define USB_OTG_DIEPCTL_TXFNUM_Msk              (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
-#define USB_OTG_DIEPCTL_TXFNUM                  USB_OTG_DIEPCTL_TXFNUM_Msk     /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
-#define USB_OTG_DIEPCTL_CNAK_Pos                (26U)                          
-#define USB_OTG_DIEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DIEPCTL_CNAK                    USB_OTG_DIEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK_Pos                (27U)                          
-#define USB_OTG_DIEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DIEPCTL_SNAK                    USB_OTG_DIEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM_Pos             (29U)                          
-#define USB_OTG_DIEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DIEPCTL_SODDFRM                 USB_OTG_DIEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS_Pos               (30U)                          
-#define USB_OTG_DIEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DIEPCTL_EPDIS                   USB_OTG_DIEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA_Pos               (31U)                          
-#define USB_OTG_DIEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DIEPCTL_EPENA                   USB_OTG_DIEPCTL_EPENA_Msk      /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ_Pos                (0U)                           
-#define USB_OTG_HCCHAR_MPSIZ_Msk                (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_HCCHAR_MPSIZ                    USB_OTG_HCCHAR_MPSIZ_Msk       /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM_Pos                (11U)                          
-#define USB_OTG_HCCHAR_EPNUM_Msk                (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
-#define USB_OTG_HCCHAR_EPNUM                    USB_OTG_HCCHAR_EPNUM_Msk       /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                  (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCCHAR_EPNUM_1                  (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCCHAR_EPNUM_2                  (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
-#define USB_OTG_HCCHAR_EPNUM_3                  (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCCHAR_EPDIR_Pos                (15U)                          
-#define USB_OTG_HCCHAR_EPDIR_Msk                (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCCHAR_EPDIR                    USB_OTG_HCCHAR_EPDIR_Msk       /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV_Pos                (17U)                          
-#define USB_OTG_HCCHAR_LSDEV_Msk                (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HCCHAR_LSDEV                    USB_OTG_HCCHAR_LSDEV_Msk       /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP_Pos                (18U)                          
-#define USB_OTG_HCCHAR_EPTYP_Msk                (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_HCCHAR_EPTYP                    USB_OTG_HCCHAR_EPTYP_Msk       /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                  (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_HCCHAR_EPTYP_1                  (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
-                                      
-#define USB_OTG_HCCHAR_MC_Pos                   (20U)                          
-#define USB_OTG_HCCHAR_MC_Msk                   (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
-#define USB_OTG_HCCHAR_MC                       USB_OTG_HCCHAR_MC_Msk          /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                     (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
-#define USB_OTG_HCCHAR_MC_1                     (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
-
-#define USB_OTG_HCCHAR_DAD_Pos                  (22U)                          
-#define USB_OTG_HCCHAR_DAD_Msk                  (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
-#define USB_OTG_HCCHAR_DAD                      USB_OTG_HCCHAR_DAD_Msk         /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                    (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
-#define USB_OTG_HCCHAR_DAD_1                    (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
-#define USB_OTG_HCCHAR_DAD_2                    (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
-#define USB_OTG_HCCHAR_DAD_3                    (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
-#define USB_OTG_HCCHAR_DAD_4                    (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
-#define USB_OTG_HCCHAR_DAD_5                    (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
-#define USB_OTG_HCCHAR_DAD_6                    (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
-#define USB_OTG_HCCHAR_ODDFRM_Pos               (29U)                          
-#define USB_OTG_HCCHAR_ODDFRM_Msk               (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCCHAR_ODDFRM                   USB_OTG_HCCHAR_ODDFRM_Msk      /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS_Pos                (30U)                          
-#define USB_OTG_HCCHAR_CHDIS_Msk                (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_HCCHAR_CHDIS                    USB_OTG_HCCHAR_CHDIS_Msk       /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA_Pos                (31U)                          
-#define USB_OTG_HCCHAR_CHENA_Msk                (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCCHAR_CHENA                    USB_OTG_HCCHAR_CHENA_Msk       /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR_Pos              (0U)                           
-#define USB_OTG_HCSPLT_PRTADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
-#define USB_OTG_HCSPLT_PRTADDR                  USB_OTG_HCSPLT_PRTADDR_Msk     /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0                (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCSPLT_PRTADDR_1                (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCSPLT_PRTADDR_2                (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCSPLT_PRTADDR_3                (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCSPLT_PRTADDR_4                (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCSPLT_PRTADDR_5                (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCSPLT_PRTADDR_6                (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
-
-#define USB_OTG_HCSPLT_HUBADDR_Pos              (7U)                           
-#define USB_OTG_HCSPLT_HUBADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
-#define USB_OTG_HCSPLT_HUBADDR                  USB_OTG_HCSPLT_HUBADDR_Msk     /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0                (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCSPLT_HUBADDR_1                (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCSPLT_HUBADDR_2                (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCSPLT_HUBADDR_3                (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCSPLT_HUBADDR_4                (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCSPLT_HUBADDR_5                (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCSPLT_HUBADDR_6                (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
-
-#define USB_OTG_HCSPLT_XACTPOS_Pos              (14U)                          
-#define USB_OTG_HCSPLT_XACTPOS_Msk              (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
-#define USB_OTG_HCSPLT_XACTPOS                  USB_OTG_HCSPLT_XACTPOS_Msk     /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0                (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCSPLT_XACTPOS_1                (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCSPLT_COMPLSPLT_Pos            (16U)                          
-#define USB_OTG_HCSPLT_COMPLSPLT_Msk            (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
-#define USB_OTG_HCSPLT_COMPLSPLT                USB_OTG_HCSPLT_COMPLSPLT_Msk   /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN_Pos              (31U)                          
-#define USB_OTG_HCSPLT_SPLITEN_Msk              (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCSPLT_SPLITEN                  USB_OTG_HCSPLT_SPLITEN_Msk     /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC_Pos                  (0U)                           
-#define USB_OTG_HCINT_XFRC_Msk                  (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINT_XFRC                      USB_OTG_HCINT_XFRC_Msk         /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH_Pos                   (1U)                           
-#define USB_OTG_HCINT_CHH_Msk                   (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINT_CHH                       USB_OTG_HCINT_CHH_Msk          /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR_Pos                (2U)                           
-#define USB_OTG_HCINT_AHBERR_Msk                (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINT_AHBERR                    USB_OTG_HCINT_AHBERR_Msk       /*!< AHB error */
-#define USB_OTG_HCINT_STALL_Pos                 (3U)                           
-#define USB_OTG_HCINT_STALL_Msk                 (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINT_STALL                     USB_OTG_HCINT_STALL_Msk        /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK_Pos                   (4U)                           
-#define USB_OTG_HCINT_NAK_Msk                   (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINT_NAK                       USB_OTG_HCINT_NAK_Msk          /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK_Pos                   (5U)                           
-#define USB_OTG_HCINT_ACK_Msk                   (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINT_ACK                       USB_OTG_HCINT_ACK_Msk          /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET_Pos                  (6U)                           
-#define USB_OTG_HCINT_NYET_Msk                  (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINT_NYET                      USB_OTG_HCINT_NYET_Msk         /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR_Pos                 (7U)                           
-#define USB_OTG_HCINT_TXERR_Msk                 (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINT_TXERR                     USB_OTG_HCINT_TXERR_Msk        /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR_Pos                 (8U)                           
-#define USB_OTG_HCINT_BBERR_Msk                 (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINT_BBERR                     USB_OTG_HCINT_BBERR_Msk        /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR_Pos                 (9U)                           
-#define USB_OTG_HCINT_FRMOR_Msk                 (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINT_FRMOR                     USB_OTG_HCINT_FRMOR_Msk        /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR_Pos                 (10U)                          
-#define USB_OTG_HCINT_DTERR_Msk                 (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINT_DTERR                     USB_OTG_HCINT_DTERR_Msk        /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC_Pos                (0U)                           
-#define USB_OTG_DIEPINT_XFRC_Msk                (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPINT_XFRC                    USB_OTG_DIEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD_Pos              (1U)                           
-#define USB_OTG_DIEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPINT_EPDISD                  USB_OTG_DIEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
-#define USB_OTG_DIEPINT_TOC_Pos                 (3U)                           
-#define USB_OTG_DIEPINT_TOC_Msk                 (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPINT_TOC                     USB_OTG_DIEPINT_TOC_Msk        /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE_Pos              (4U)                           
-#define USB_OTG_DIEPINT_ITTXFE_Msk              (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPINT_ITTXFE                  USB_OTG_DIEPINT_ITTXFE_Msk     /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
-#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
-#define USB_OTG_DIEPINT_INEPNE_Pos              (6U)                           
-#define USB_OTG_DIEPINT_INEPNE_Msk              (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPINT_INEPNE                  USB_OTG_DIEPINT_INEPNE_Msk     /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE_Pos                (7U)                           
-#define USB_OTG_DIEPINT_TXFE_Msk                (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
-#define USB_OTG_DIEPINT_TXFE                    USB_OTG_DIEPINT_TXFE_Msk       /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos          (8U)                           
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk          (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA_Pos                 (9U)                           
-#define USB_OTG_DIEPINT_BNA_Msk                 (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPINT_BNA                     USB_OTG_DIEPINT_BNA_Msk        /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS_Pos           (11U)                          
-#define USB_OTG_DIEPINT_PKTDRPSTS_Msk           (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_DIEPINT_PKTDRPSTS               USB_OTG_DIEPINT_PKTDRPSTS_Msk  /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR_Pos                (12U)                          
-#define USB_OTG_DIEPINT_BERR_Msk                (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
-#define USB_OTG_DIEPINT_BERR                    USB_OTG_DIEPINT_BERR_Msk       /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK_Pos                 (13U)                          
-#define USB_OTG_DIEPINT_NAK_Msk                 (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPINT_NAK                     USB_OTG_DIEPINT_NAK_Msk        /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM_Pos              (0U)                           
-#define USB_OTG_HCINTMSK_XFRCM_Msk              (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINTMSK_XFRCM                  USB_OTG_HCINTMSK_XFRCM_Msk     /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM_Pos               (1U)                           
-#define USB_OTG_HCINTMSK_CHHM_Msk               (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINTMSK_CHHM                   USB_OTG_HCINTMSK_CHHM_Msk      /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR_Pos             (2U)                           
-#define USB_OTG_HCINTMSK_AHBERR_Msk             (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINTMSK_AHBERR                 USB_OTG_HCINTMSK_AHBERR_Msk    /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM_Pos             (3U)                           
-#define USB_OTG_HCINTMSK_STALLM_Msk             (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINTMSK_STALLM                 USB_OTG_HCINTMSK_STALLM_Msk    /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM_Pos               (4U)                           
-#define USB_OTG_HCINTMSK_NAKM_Msk               (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINTMSK_NAKM                   USB_OTG_HCINTMSK_NAKM_Msk      /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM_Pos               (5U)                           
-#define USB_OTG_HCINTMSK_ACKM_Msk               (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINTMSK_ACKM                   USB_OTG_HCINTMSK_ACKM_Msk      /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET_Pos               (6U)                           
-#define USB_OTG_HCINTMSK_NYET_Msk               (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINTMSK_NYET                   USB_OTG_HCINTMSK_NYET_Msk      /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM_Pos             (7U)                           
-#define USB_OTG_HCINTMSK_TXERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINTMSK_TXERRM                 USB_OTG_HCINTMSK_TXERRM_Msk    /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM_Pos             (8U)                           
-#define USB_OTG_HCINTMSK_BBERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINTMSK_BBERRM                 USB_OTG_HCINTMSK_BBERRM_Msk    /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM_Pos             (9U)                           
-#define USB_OTG_HCINTMSK_FRMORM_Msk             (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINTMSK_FRMORM                 USB_OTG_HCINTMSK_FRMORM_Msk    /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM_Pos             (10U)                          
-#define USB_OTG_HCINTMSK_DTERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINTMSK_DTERRM                 USB_OTG_HCINTMSK_DTERRM_Msk    /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos             (0U)                           
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DIEPTSIZ_XFRSIZ                 USB_OTG_DIEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT_Pos             (19U)                          
-#define USB_OTG_DIEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DIEPTSIZ_PKTCNT                 USB_OTG_DIEPTSIZ_PKTCNT_Msk    /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT_Pos             (29U)                          
-#define USB_OTG_DIEPTSIZ_MULCNT_Msk             (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DIEPTSIZ_MULCNT                 USB_OTG_DIEPTSIZ_MULCNT_Msk    /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ_Pos               (0U)                           
-#define USB_OTG_HCTSIZ_XFRSIZ_Msk               (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_HCTSIZ_XFRSIZ                   USB_OTG_HCTSIZ_XFRSIZ_Msk      /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT_Pos               (19U)                          
-#define USB_OTG_HCTSIZ_PKTCNT_Msk               (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_HCTSIZ_PKTCNT                   USB_OTG_HCTSIZ_PKTCNT_Msk      /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING_Pos               (31U)                          
-#define USB_OTG_HCTSIZ_DOPING_Msk               (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCTSIZ_DOPING                   USB_OTG_HCTSIZ_DOPING_Msk      /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID_Pos                 (29U)                          
-#define USB_OTG_HCTSIZ_DPID_Msk                 (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
-#define USB_OTG_HCTSIZ_DPID                     USB_OTG_HCTSIZ_DPID_Msk        /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCTSIZ_DPID_1                   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR_Pos             (0U)                           
-#define USB_OTG_DIEPDMA_DMAADDR_Msk             (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_DIEPDMA_DMAADDR                 USB_OTG_DIEPDMA_DMAADDR_Msk    /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR_Pos               (0U)                           
-#define USB_OTG_HCDMA_DMAADDR_Msk               (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_HCDMA_DMAADDR                   USB_OTG_HCDMA_DMAADDR_Msk      /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV_Pos           (0U)                           
-#define USB_OTG_DTXFSTS_INEPTFSAV_Msk           (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA_Pos            (0U)                           
-#define USB_OTG_DIEPTXF_INEPTXSA_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPTXF_INEPTXSA                USB_OTG_DIEPTXF_INEPTXSA_Msk   /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD_Pos            (16U)                          
-#define USB_OTG_DIEPTXF_INEPTXFD_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DIEPTXF_INEPTXFD                USB_OTG_DIEPTXF_INEPTXFD_Msk   /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ_Pos               (0U)                           
-#define USB_OTG_DOEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP_Pos              (15U)                          
-#define USB_OTG_DOEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPCTL_USBAEP                  USB_OTG_DOEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS_Pos              (17U)                          
-#define USB_OTG_DOEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DOEPCTL_NAKSTS                  USB_OTG_DOEPCTL_NAKSTS_Msk     /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM          USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM_Pos             (29U)                          
-#define USB_OTG_DOEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPCTL_SODDFRM                 USB_OTG_DOEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP_Pos               (18U)                          
-#define USB_OTG_DOEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DOEPCTL_EPTYP                   USB_OTG_DOEPCTL_EPTYP_Msk      /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DOEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DOEPCTL_SNPM_Pos                (20U)                          
-#define USB_OTG_DOEPCTL_SNPM_Msk                (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
-#define USB_OTG_DOEPCTL_SNPM                    USB_OTG_DOEPCTL_SNPM_Msk       /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL_Pos               (21U)                          
-#define USB_OTG_DOEPCTL_STALL_Msk               (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DOEPCTL_STALL                   USB_OTG_DOEPCTL_STALL_Msk      /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK_Pos                (26U)                          
-#define USB_OTG_DOEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DOEPCTL_CNAK                    USB_OTG_DOEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK_Pos                (27U)                          
-#define USB_OTG_DOEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DOEPCTL_SNAK                    USB_OTG_DOEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS_Pos               (30U)                          
-#define USB_OTG_DOEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DOEPCTL_EPDIS                   USB_OTG_DOEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA_Pos               (31U)                          
-#define USB_OTG_DOEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DOEPCTL_EPENA                   USB_OTG_DOEPCTL_EPENA_Msk      /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC_Pos                (0U)                           
-#define USB_OTG_DOEPINT_XFRC_Msk                (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPINT_XFRC                    USB_OTG_DOEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD_Pos              (1U)                           
-#define USB_OTG_DOEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPINT_EPDISD                  USB_OTG_DOEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
-#define USB_OTG_DOEPINT_STUP_Pos                (3U)                           
-#define USB_OTG_DOEPINT_STUP_Msk                (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPINT_STUP                    USB_OTG_DOEPINT_STUP_Msk       /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS_Pos             (4U)                           
-#define USB_OTG_DOEPINT_OTEPDIS_Msk             (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPINT_OTEPDIS                 USB_OTG_DOEPINT_OTEPDIS_Msk    /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
-#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP_Pos             (6U)                           
-#define USB_OTG_DOEPINT_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPINT_B2BSTUP                 USB_OTG_DOEPINT_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
-#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
-#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
-#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
-#define USB_OTG_DOEPINT_NYET_Pos                (14U)                          
-#define USB_OTG_DOEPINT_NYET_Msk                (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPINT_NYET                    USB_OTG_DOEPINT_NYET_Msk       /*!< NYET interrupt */
-#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
-#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos             (0U)                           
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DOEPTSIZ_XFRSIZ                 USB_OTG_DOEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT_Pos             (19U)                          
-#define USB_OTG_DOEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DOEPTSIZ_PKTCNT                 USB_OTG_DOEPTSIZ_PKTCNT_Msk    /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT_Pos            (29U)                          
-#define USB_OTG_DOEPTSIZ_STUPCNT_Msk            (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT                USB_OTG_DOEPTSIZ_STUPCNT_Msk   /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0              (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1              (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK_Pos             (0U)                           
-#define USB_OTG_PCGCCTL_STOPCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCCTL_STOPCLK                 USB_OTG_PCGCCTL_STOPCLK_Msk    /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK_Pos             (1U)                           
-#define USB_OTG_PCGCCTL_GATECLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCCTL_GATECLK                 USB_OTG_PCGCCTL_GATECLK_Msk    /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP_Pos             (4U)                           
-#define USB_OTG_PCGCCTL_PHYSUSP_Msk             (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 USB_OTG_PCGCCTL_PHYSUSP_Msk    /*!<Bit 1 */
-
-/* Legacy define */
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_CHNUM_Pos                       (0U)                           
-#define USB_OTG_CHNUM_Msk                       (0xFUL << USB_OTG_CHNUM_Pos)    /*!< 0x0000000F */
-#define USB_OTG_CHNUM                           USB_OTG_CHNUM_Msk              /*!< Channel number */
-#define USB_OTG_CHNUM_0                         (0x1UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000001 */
-#define USB_OTG_CHNUM_1                         (0x2UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000002 */
-#define USB_OTG_CHNUM_2                         (0x4UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000004 */
-#define USB_OTG_CHNUM_3                         (0x8UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000008 */
-#define USB_OTG_BCNT_Pos                        (4U)                           
-#define USB_OTG_BCNT_Msk                        (0x7FFUL << USB_OTG_BCNT_Pos)   /*!< 0x00007FF0 */
-#define USB_OTG_BCNT                            USB_OTG_BCNT_Msk               /*!< Byte count */
-
-#define USB_OTG_DPID_Pos                        (15U)                          
-#define USB_OTG_DPID_Msk                        (0x3UL << USB_OTG_DPID_Pos)     /*!< 0x00018000 */
-#define USB_OTG_DPID                            USB_OTG_DPID_Msk               /*!< Data PID */
-#define USB_OTG_DPID_0                          (0x1UL << USB_OTG_DPID_Pos)     /*!< 0x00008000 */
-#define USB_OTG_DPID_1                          (0x2UL << USB_OTG_DPID_Pos)     /*!< 0x00010000 */
-
-#define USB_OTG_PKTSTS_Pos                      (17U)                          
-#define USB_OTG_PKTSTS_Msk                      (0xFUL << USB_OTG_PKTSTS_Pos)   /*!< 0x001E0000 */
-#define USB_OTG_PKTSTS                          USB_OTG_PKTSTS_Msk             /*!< Packet status */
-#define USB_OTG_PKTSTS_0                        (0x1UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00020000 */
-#define USB_OTG_PKTSTS_1                        (0x2UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00040000 */
-#define USB_OTG_PKTSTS_2                        (0x4UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00080000 */
-#define USB_OTG_PKTSTS_3                        (0x8UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00100000 */
-
-#define USB_OTG_EPNUM_Pos                       (0U)                           
-#define USB_OTG_EPNUM_Msk                       (0xFUL << USB_OTG_EPNUM_Pos)    /*!< 0x0000000F */
-#define USB_OTG_EPNUM                           USB_OTG_EPNUM_Msk              /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                         (0x1UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000001 */
-#define USB_OTG_EPNUM_1                         (0x2UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000002 */
-#define USB_OTG_EPNUM_2                         (0x4UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000004 */
-#define USB_OTG_EPNUM_3                         (0x8UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000008 */
-
-#define USB_OTG_FRMNUM_Pos                      (21U)                          
-#define USB_OTG_FRMNUM_Msk                      (0xFUL << USB_OTG_FRMNUM_Pos)   /*!< 0x01E00000 */
-#define USB_OTG_FRMNUM                          USB_OTG_FRMNUM_Msk             /*!< Frame number */
-#define USB_OTG_FRMNUM_0                        (0x1UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00200000 */
-#define USB_OTG_FRMNUM_1                        (0x2UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00400000 */
-#define USB_OTG_FRMNUM_2                        (0x4UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00800000 */
-#define USB_OTG_FRMNUM_3                        (0x8UL << USB_OTG_FRMNUM_Pos)   /*!< 0x01000000 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
new file mode 100644
index 000000000..8da2e39ba
--- /dev/null
+++ b/src/portable/st/typec/typec_stm32.c
@@ -0,0 +1,372 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "tusb_option.h"
+#include "typec/tcd.h"
+
+#if CFG_TUC_ENABLED && defined(TUP_USBIP_TYPEC_STM32)
+
+#include "common/tusb_common.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_STM32G4
+  #include "stm32g4xx.h"
+  #include "stm32g4xx_ll_dma.h" // for UCPD REQID
+#else
+  #error "Unsupported STM32 family"
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+enum {
+  IMR_ATTACHED = UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
+                 UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
+                 UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE
+};
+
+#define PHY_SYNC1 0x18u
+#define PHY_SYNC2 0x11u
+#define PHY_SYNC3 0x06u
+#define PHY_RST1  0x07u
+#define PHY_RST2  0x19u
+#define PHY_EOP   0x0Du
+
+#define PHY_ORDERED_SET_SOP          (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC2<<15u)) // SOP Ordered set coding
+#define PHY_ORDERED_SET_SOP_P        (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC3<<15u)) // SOP' Ordered set coding
+#define PHY_ORDERED_SET_SOP_PP       (PHY_SYNC1 | (PHY_SYNC3<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC3<<15u)) // SOP'' Ordered set coding
+#define PHY_ORDERED_SET_HARD_RESET   (PHY_RST1  | (PHY_RST1<<5u)  | (PHY_RST1<<10u)  | (PHY_RST2<<15u )) // Hard Reset Ordered set coding
+#define PHY_ORDERED_SET_CABLE_RESET  (PHY_RST1  | (PHY_SYNC1<<5u) | (PHY_RST1<<10u)  | (PHY_SYNC3<<15u)) // Cable Reset Ordered set coding
+#define PHY_ORDERED_SET_SOP_P_DEBUG  (PHY_SYNC1 | (PHY_RST2<<5u)  | (PHY_RST2<<10u)  | (PHY_SYNC3<<15u)) // SOP' Debug Ordered set coding
+#define PHY_ORDERED_SET_SOP_PP_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u)  | (PHY_SYNC3<<10u) | (PHY_SYNC2<<15u)) // SOP'' Debug Ordered set coding
+
+
+static uint8_t const* _rx_buf;
+static uint8_t const* _tx_pending_buf;
+static uint16_t _tx_pending_bytes;
+static uint16_t _tx_xferring_bytes;
+
+static pd_header_t _good_crc = {
+    .msg_type   = PD_CTRL_GOOD_CRC,
+    .data_role  = 0, // UFP
+    .specs_rev  = PD_REV_20,
+    .power_role = 0, // Sink
+    .msg_id     = 0,
+    .n_data_obj = 0,
+    .extended   = 0
+};
+
+// address of DMA channel rx, tx for each port
+#define CFG_TUC_STM32_DMA  { { DMA1_Channel1_BASE, DMA1_Channel2_BASE } }
+
+//--------------------------------------------------------------------+
+// DMA
+//--------------------------------------------------------------------+
+
+static const uint32_t _dma_addr_arr[TUP_TYPEC_RHPORTS_NUM][2] = CFG_TUC_STM32_DMA;
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t dma_get_addr(uint8_t rhport, bool is_rx) {
+  return _dma_addr_arr[rhport][is_rx ? 0 : 1];
+}
+
+static void dma_init(uint8_t rhport, bool is_rx) {
+  uint32_t dma_addr = dma_get_addr(rhport, is_rx);
+  DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_addr;
+  uint32_t req_id;
+
+  if (is_rx) {
+    // Peripheral -> Memory, Memory inc, 8-bit, High priority
+    dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
+    dma_ch->CPAR = (uint32_t) &UCPD1->RXDR;
+
+    req_id = LL_DMAMUX_REQ_UCPD1_RX;
+  } else {
+    // Memory -> Peripheral, Memory inc, 8-bit, High priority
+    dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_DIR;
+    dma_ch->CPAR = (uint32_t) &UCPD1->TXDR;
+
+    req_id = LL_DMAMUX_REQ_UCPD1_TX;
+  }
+
+  // find and set up mux channel TODO support mcu with multiple DMAMUXs
+  enum {
+    CH_DIFF = DMA1_Channel2_BASE - DMA1_Channel1_BASE
+  };
+  uint32_t mux_ch_num;
+
+  #ifdef DMA2_BASE
+  if (dma_addr > DMA2_BASE) {
+    mux_ch_num = 8 * ((dma_addr - DMA2_Channel1_BASE) / CH_DIFF);
+  } else
+  #endif
+  {
+    mux_ch_num = (dma_addr - DMA1_Channel1_BASE) / CH_DIFF;
+  }
+
+  DMAMUX_Channel_TypeDef* mux_ch = DMAMUX1_Channel0 + mux_ch_num;
+
+  uint32_t mux_ccr = mux_ch->CCR & ~(DMAMUX_CxCR_DMAREQ_ID);
+  mux_ccr |= req_id;
+  mux_ch->CCR = mux_ccr;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dma_start(uint8_t rhport, bool is_rx, void const* buf, uint16_t len) {
+  DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
+
+  dma_ch->CMAR = (uint32_t) buf;
+  dma_ch->CNDTR = len;
+  dma_ch->CCR |= DMA_CCR_EN;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dma_stop(uint8_t rhport, bool is_rx) {
+  DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
+  dma_ch->CCR &= ~DMA_CCR_EN;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(uint8_t rhport, bool is_rx) {
+  DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
+  return dma_ch->CCR & DMA_CCR_EN;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) {
+  UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
+  UCPD1->TX_PAYSZ = len;
+  dma_start(rhport, false, buf, len);
+  UCPD1->CR |= UCPD_CR_TXSEND;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dma_tx_stop(uint8_t rhport) {
+  dma_stop(rhport, false);
+}
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tcd_init(uint8_t rhport, uint32_t port_type) {
+  (void) rhport;
+
+  // Init DMA for RX, TX
+  dma_init(rhport, true);
+  dma_init(rhport, false);
+
+  // Initialization phase: CFG1, detect all SOPs
+  UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
+                (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos);
+  UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
+
+  // General programming sequence (with UCPD configured then enabled)
+  if (port_type == TUSB_TYPEC_PORT_SNK) {
+    // Set analog mode enable both CC Phy
+    UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1);
+
+    // Read Voltage State on CC1 & CC2 fore initial state
+    uint32_t v_cc[2];
+    (void) v_cc;
+    v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
+    v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
+    TU_LOG1("Initial VState CC1 = %lu, CC2 = %lu\r\n", v_cc[0], v_cc[1]);
+
+    // Enable CC1 & CC2 Interrupt
+    UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
+  }
+
+  // Disable dead battery in PWR's CR3
+  PWR->CR3 |= PWR_CR3_UCPD_DBDIS;
+
+  return true;
+}
+
+// Enable interrupt
+void tcd_int_enable (uint8_t rhport) {
+  (void) rhport;
+  NVIC_EnableIRQ(UCPD1_IRQn);
+}
+
+// Disable interrupt
+void tcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_DisableIRQ(UCPD1_IRQn);
+}
+
+bool tcd_msg_receive(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
+  _rx_buf = buffer;
+  dma_start(rhport, true, buffer, total_bytes);
+  return true;
+}
+
+bool tcd_msg_send(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) {
+  (void) rhport;
+
+  if (dma_enabled(rhport, false)) {
+    // DMA is busy, probably sending GoodCRC, save as pending TX
+    _tx_pending_buf = buffer;
+    _tx_pending_bytes = total_bytes;
+  }else {
+    // DMA is free, start sending
+    _tx_pending_buf = NULL;
+    _tx_pending_bytes = 0;
+
+    _tx_xferring_bytes = total_bytes;
+    dma_tx_start(rhport, buffer, total_bytes);
+  }
+
+  return true;
+}
+
+void tcd_int_handler(uint8_t rhport) {
+  (void) rhport;
+
+  uint32_t sr = UCPD1->SR;
+  sr &= UCPD1->IMR;
+
+  if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
+    uint32_t v_cc[2];
+    v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
+    v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
+
+    TU_LOG3("VState CC1 = %lu, CC2 = %lu\r\n", v_cc[0], v_cc[1]);
+
+    uint32_t cr = UCPD1->CR;
+
+    // TODO only support SNK for now, required highest voltage for now
+    // Enable PHY on active CC and disable Rd on other CC
+    // FIXME somehow CC2 is vstate is not correct, always 1 even not attached.
+    // on DPOW1 board, it is connected to PA10 (USBPD_DBCC2), we probably miss something.
+    if ((sr & UCPD_SR_TYPECEVT1) && (v_cc[0] == 3)) {
+      TU_LOG3("Attach CC1\r\n");
+      cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE);
+      cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0;
+    } else if ((sr & UCPD_SR_TYPECEVT2) && (v_cc[1] == 3)) {
+      TU_LOG3("Attach CC2\r\n");
+      cr &= ~UCPD_CR_CCENABLE;
+      cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1);
+    } else {
+      TU_LOG3("Detach\r\n");
+      cr &= ~UCPD_CR_PHYRXEN;
+      cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
+    }
+
+    if (cr & UCPD_CR_PHYRXEN) {
+      // Attached
+      UCPD1->IMR |= IMR_ATTACHED;
+      UCPD1->CFG1 |= UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN;
+    }else {
+      // Detached
+      UCPD1->CFG1 &= ~(UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN);
+      UCPD1->IMR &= ~IMR_ATTACHED;
+    }
+
+    // notify stack
+    tcd_event_cc_changed(rhport, v_cc[0], v_cc[1], true);
+
+    UCPD1->CR = cr;
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
+  }
+
+  //------------- RX -------------//
+  if (sr & UCPD_SR_RXORDDET) {
+    // SOP: Start of Packet.
+    TU_LOG3("SOP\r\n");
+    // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_RXORDDETCF;
+  }
+
+  // Received full message
+  if (sr & UCPD_SR_RXMSGEND) {
+    TU_LOG3("RX MSG END\r\n");
+
+    // stop TX
+    dma_stop(rhport, true);
+
+    uint8_t result;
+
+    if (!(sr & UCPD_SR_RXERR)) {
+      // response with good crc
+      // TODO move this to usbc stack
+      if (_rx_buf) {
+        _good_crc.msg_id = ((pd_header_t const *) _rx_buf)->msg_id;
+        dma_tx_start(rhport, &_good_crc, 2);
+      }
+
+      result = XFER_RESULT_SUCCESS;
+    }else {
+      // CRC failed
+      result = XFER_RESULT_FAILED;
+    }
+
+    // notify stack
+    tcd_event_rx_complete(rhport, UCPD1->RX_PAYSZ, result, true);
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
+  }
+
+  if (sr & UCPD_SR_RXOVR) {
+    TU_LOG3("RXOVR\r\n");
+    // ack
+    UCPD1->ICR = UCPD_ICR_RXOVRCF;
+  }
+
+  //------------- TX -------------//
+  // All tx events: complete and error
+  if (sr & (UCPD_SR_TXMSGSENT | (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND))) {
+    // force TX stop
+    dma_tx_stop(rhport);
+
+    uint16_t const xferred_bytes = _tx_xferring_bytes - UCPD1->TX_PAYSZ;
+    uint8_t result;
+
+    if ( sr & UCPD_SR_TXMSGSENT ) {
+      TU_LOG3("TX MSG SENT\r\n");
+      result = XFER_RESULT_SUCCESS;
+      // ack
+      UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
+    }else {
+      TU_LOG3("TX Error\r\n");
+      result = XFER_RESULT_FAILED;
+      // ack
+      UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND;
+    }
+
+    // start pending TX if any
+    if (_tx_pending_buf && _tx_pending_bytes ) {
+      // Start the pending TX
+      dma_tx_start(rhport, _tx_pending_buf, _tx_pending_bytes);
+
+      // clear pending
+      _tx_pending_buf = NULL;
+      _tx_pending_bytes = 0;
+    }
+
+    // notify stack
+    tcd_event_tx_complete(rhport, xferred_bytes, result, true);
+  }
+}
+
+#endif
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index a0be846a5..21f13b279 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -35,7 +35,9 @@
 #include <f1c100s-irq.h>
 #include <device/dcd.h>
 #include "musb_def.h"
-#include "bsp/board.h"
+
+//#include "bsp/board_api.h"
+extern uint32_t board_millis(void); // TODO remove
 
 typedef uint32_t u32;
 typedef uint16_t u16;
@@ -58,7 +60,7 @@ typedef struct TU_ATTR_PACKED
 
 typedef struct
 {
-  tusb_control_request_t setup_packet;
+  CFG_TUD_MEM_ALIGN tusb_control_request_t setup_packet;
   uint16_t     remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
   int8_t       status_out;
   pipe_state_t pipe0;
@@ -243,7 +245,7 @@ static void USBC_Dev_SetAddress(u8 address)
 
 static void __USBC_Dev_Tx_SendStall(void)
 {
-	//send stall, and fifo is flushed automaticly
+	//send stall, and fifo is flushed automatically
 	USBC_REG_set_bit_w(USBC_BP_TXCSR_D_SEND_STALL, USBC_REG_TXCSR(USBC0_BASE));
 }
 static u32 __USBC_Dev_Tx_IsEpStall(void)
@@ -350,7 +352,7 @@ static void USBC_INT_DisableRxEp(u8 ep_index)
  * INTERNAL FUNCTION DECLARATION
  *------------------------------------------------------------------*/
 
-static dcd_data_t _dcd;
+CFG_TUD_MEM_ALIGN static dcd_data_t _dcd;
 
 static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
 {
@@ -408,9 +410,9 @@ static inline unsigned free_block_size(free_block_t const *blk)
 #if 0
 static inline void print_block_list(free_block_t const *blk, unsigned num)
 {
-  TU_LOG1("*************\n");
+  TU_LOG1("*************\r\n");
   for (unsigned i = 0; i < num; ++i) {
-    TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end);
+    TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end);
     ++blk;
   }
 }
@@ -560,7 +562,7 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
 
 static void process_setup_packet(uint8_t rhport)
 {
-  uint32_t *p = (uint32_t*)&_dcd.setup_packet;
+  uint32_t *p = (uint32_t*)(uintptr_t) &_dcd.setup_packet;
   p[0]        = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
   p[1]        = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
 
@@ -590,11 +592,11 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
   const unsigned mps = USBC_Readw(USBC_REG_TXMAXP(USBC0_BASE));
   const unsigned len = TU_MIN(mps, rem);
   uint8_t          *buf = pipe->buf;
-  // TU_LOG1("   %p mps %d len %d rem %d\n", buf, mps, len, rem);
+  // TU_LOG1("   %p mps %d len %d rem %d\r\n", buf, mps, len, rem);
   if (len) {
     volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
-      pipe_read_write_packet_ff((tu_fifo_t *)buf, addr, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t *)(uintptr_t) buf, addr, len, TUSB_DIR_IN);
     } else {
       pipe_write_packet(buf, addr, len);
       pipe->buf       = buf + len;
@@ -602,7 +604,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
     pipe->remaining = rem - len;
   }
   __USBC_Dev_Tx_WriteDataComplete();
-  // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
+  // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
   return false;
 }
 
@@ -610,7 +612,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
 {
   unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
   pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
-  // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL);
+  // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL);
 
   TU_ASSERT(__USBC_Dev_Rx_IsReadDataReady());
 
@@ -622,7 +624,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
   if (len) {
     volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) {
-      pipe_read_write_packet_ff((tu_fifo_t *)buf, addr, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t *)(uintptr_t )buf, addr, len, TUSB_DIR_OUT);
     } else {
       pipe_read_packet(buf, addr, len);
       pipe->buf       = buf + len;
@@ -677,14 +679,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
      * may have already finished and received the next setup packet
      * without calling this function, so we have no choice but to
      * invoke the callback function of status packet here. */
-    // TU_LOG1(" STATUS OUT CSRL0 = %x\n", CSRL0);
+    // TU_LOG1(" STATUS OUT CSRL0 = %x\r\n", CSRL0);
     _dcd.status_out = 0;
     if (req == REQUEST_TYPE_INVALID) {
       dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
     } else {
       /* The next setup packet has already been received, it aborts
        * invoking callback function to avoid confusing TUSB stack. */
-      TU_LOG1("Drop CONTROL_STAGE_ACK\n");
+      TU_LOG1("Drop CONTROL_STAGE_ACK\r\n");
     }
     return true;
   }
@@ -709,16 +711,16 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
       } else {
         __USBC_Dev_ep0_WriteDataHalf();
       }
-      // TU_LOG1(" IN CSRL0 = %x\n", CSRL0);
+      // TU_LOG1(" IN CSRL0 = %x\r\n", CSRL0);
     } else {
-      // TU_LOG1(" OUT CSRL0 = %x\n", CSRL0);
+      // TU_LOG1(" OUT CSRL0 = %x\r\n", CSRL0);
       _dcd.pipe0.buf       = buffer;
       _dcd.pipe0.length    = len;
       _dcd.pipe0.remaining = len;
       __USBC_Dev_ep0_ReadDataHalf();
     }
   } else if (dir_in) {
-    // TU_LOG1(" STATUS IN CSRL0 = %x\n", CSRL0);
+    // TU_LOG1(" STATUS IN CSRL0 = %x\r\n", CSRL0);
     _dcd.pipe0.buf = NULL;
     _dcd.pipe0.length    = 0;
     _dcd.pipe0.remaining = 0;
@@ -733,7 +735,7 @@ static void process_ep0(uint8_t rhport)
   USBC_SelectActiveEp(0);
   uint_fast8_t csrl = USBC_Readw(USBC_REG_CSR0(USBC0_BASE));
 
-  // TU_LOG1(" EP0 CSRL0 = %x\n", csrl);
+  // TU_LOG1(" EP0 CSRL0 = %x\r\n", csrl);
 
   if (csrl & USB_CSRL0_STALLED) {
     /* Returned STALL packet to HOST. */
@@ -743,7 +745,7 @@ static void process_ep0(uint8_t rhport)
 
   unsigned req = _dcd.setup_packet.bmRequestType;
   if (csrl & USB_CSRL0_SETEND) {
-    // TU_LOG1("   ABORT by the next packets\n");
+    // TU_LOG1("   ABORT by the next packets\r\n");
     USBC_Dev_Ctrl_ClearSetupEnd();
     if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
       /* DATA stage was aborted by receiving STATUS or SETUP packet. */
@@ -819,14 +821,14 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
   USBC_SelectActiveEp(epn);
 
   if (dir_in) {
-    // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL);
+    // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL);
     if (__USBC_Dev_Tx_IsEpStall()) {
 	  __USBC_Dev_Tx_ClearStall();
       return;
     }
     completed = handle_xfer_in(ep_addr);
   } else {
-    // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL);
+    // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL);
     if (__USBC_Dev_Rx_IsEpStall()) {
 	    __USBC_Dev_Rx_ClearStall();
       return;
@@ -865,8 +867,9 @@ static void usb_isr_handler(void) {
 	dcd_int_handler(0);
 }
 
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+
   dcd_disconnect(rhport);
   USBC_HardwareReset();
   USBC_PhyConfig();
@@ -893,6 +896,8 @@ void dcd_init(uint8_t rhport)
   f1c100s_intc_set_isr(F1C100S_IRQ_USBOTG, usb_isr_handler);
 
   dcd_connect(rhport);
+
+  return true;
 }
 
 // Connect by enabling internal pull-up resistor on D+/D-
@@ -996,7 +1001,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   if (dir_in) {
     USBC_Writew(mps, USBC_REG_TXMAXP(USBC0_BASE));
 
-    reg_val = (1 << USBC_BP_TXCSR_D_MODE) 
+    reg_val = (1 << USBC_BP_TXCSR_D_MODE)
       | (1 << USBC_BP_TXCSR_D_FLUSH_FIFO)
       | (1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE);
     if  (xfer == TUSB_XFER_ISOCHRONOUS)
@@ -1048,7 +1053,7 @@ void dcd_edpt_close_all(uint8_t rhport)
       USBC_REG_TXCSR(USBC0_BASE));
 
     USBC_Writew(0, USBC_REG_RXMAXP(USBC0_BASE));
-	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO), 
+	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
       USBC_REG_RXCSR(USBC0_BASE));
 
     USBC_Writew(0, USBC_REG_TXFIFOAD(USBC0_BASE));
@@ -1078,7 +1083,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   } else {
     USBC_INT_DisableRxEp(epn);
     USBC_Writew(0, USBC_REG_RXMAXP(USBC0_BASE));
-	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO), 
+	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
       USBC_REG_RXCSR(USBC0_BASE));
 
     USBC_Writew(0, USBC_REG_RXFIFOAD(USBC0_BASE));
@@ -1092,7 +1097,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   musb_int_mask();
 
@@ -1111,7 +1116,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   TU_ASSERT(epnum);
 
diff --git a/src/portable/sunxi/musb_def.h b/src/portable/sunxi/musb_def.h
index 602b4f113..53da5ded2 100644
--- a/src/portable/sunxi/musb_def.h
+++ b/src/portable/sunxi/musb_def.h
@@ -93,7 +93,7 @@
 #define  USBC1_BASE                 0x01c14000
 #define  USBC2_BASE                 0x01c1E000
 
-//Some reg whithin musb
+//Some reg within musb
 #define USBPHY_CLK_REG 		0x01c200CC
 #define USBPHY_CLK_RST_BIT 0
 #define USBPHY_CLK_GAT_BIT 1
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index f5ecdfe4f..c461d9a79 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -31,59 +31,28 @@
 
 #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
 
+#if !(CFG_TUD_DWC2_SLAVE_ENABLE || CFG_TUD_DWC2_DMA_ENABLE)
+#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUD_DWC2_DMA_ENABLE to be enabled
+#endif
+
+// Debug level for DWC2
+#define DWC2_DEBUG    2
+
 #include "device/dcd.h"
-#include "dwc2_type.h"
+#include "dwc2_common.h"
 
-// Following symbols must be defined by port header
-// - _dwc2_controller[]: array of controllers
-// - DWC2_EP_MAX: largest EP counts of all controllers
-// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
-// - dwc2_dcd_int_enable/dwc2_dcd_int_disable
-// - dwc2_remote_wakeup_delay
-
-#if defined(TUP_USBIP_DWC2_STM32)
-  #include "dwc2_stm32.h"
-#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-  #include "dwc2_esp32.h"
-#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
-  #include "dwc2_gd32.h"
-#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
-  #include "dwc2_bcm.h"
-#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
-  #include "dwc2_efm32.h"
-#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
-  #include "dwc2_xmc.h"
+#if TU_CHECK_MCU(OPT_MCU_GD32VF103)
+  #define DWC2_EP_COUNT(_dwc2)   DWC2_EP_MAX
 #else
-  #error "Unsupported MCUs"
+  #define DWC2_EP_COUNT(_dwc2)  ((_dwc2)->ghwcfg2_bm.num_dev_ep + 1)
 #endif
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
-
-// DWC2 registers
-#define DWC2_REG(_port)       ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
-
-// Debug level for DWC2
-#define DWC2_DEBUG    2
-
-#ifndef dcache_clean
-#define dcache_clean(_addr, _size)
-#endif
-
-#ifndef dcache_invalidate
-#define dcache_invalidate(_addr, _size)
-#endif
-
-#ifndef dcache_clean_invalidate
-#define dcache_clean_invalidate(_addr, _size)
-#endif
-
-static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
-
 typedef struct {
-  uint8_t * buffer;
-  tu_fifo_t * ff;
+  uint8_t* buffer;
+  tu_fifo_t* ff;
   uint16_t total_len;
   uint16_t max_size;
   uint8_t interval;
@@ -92,431 +61,366 @@ typedef struct {
 static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
 #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
 
-// EP0 transfers are limited to 1 packet - larger sizes has to be split
-static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
+typedef struct {
+  // EP0 transfers are limited to 1 packet - larger sizes has to be split
+  uint16_t ep0_pending[2];  // Index determines direction as tusb_dir_t type
+  uint16_t dfifo_top;      // top free location in DFIFO in words
 
-// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
-static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
-static bool     _out_ep_closed;                   // Flag to check if RX FIFO size needs an update (reduce its size)
+  // Number of IN endpoints active
+  uint8_t allocated_epin_count;
 
-// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
-static bool _sof_en;
+  // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
+  bool sof_en;
+} dcd_data_t;
 
-// Calculate the RX FIFO size according to recommendations from reference manual
-static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count)
-{
-  return 15 + 2*(max_ep_size/4) + 2*ep_count;
+static dcd_data_t _dcd_data;
+
+CFG_TUD_MEM_SECTION static struct {
+  TUD_EPBUF_DEF(setup_packet, 8);
+} _dcd_usbbuf;
+
+//--------------------------------------------------------------------
+// DMA
+//--------------------------------------------------------------------
+#if CFG_TUD_MEM_DCACHE_ENABLE
+bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
+  TU_VERIFY(addr && data_size);
+  return dwc2_dcache_clean(addr, data_size);
 }
 
-static void update_grxfsiz(uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
-  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
-
-  // Determine largest EP size for RX FIFO
-  uint16_t max_epsize = 0;
-  for (uint8_t epnum = 0; epnum < ep_count; epnum++)
-  {
-    max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
-  }
-
-  // Update size of RX FIFO
-  dwc2->grxfsiz = calc_grxfsiz(max_epsize, ep_count);
+bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
+  TU_VERIFY(addr && data_size);
+  return dwc2_dcache_invalidate(addr, data_size);
 }
 
-// Start of Bus Reset
-static void bus_reset(uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
-  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
-
-  tu_memclr(xfer_status, sizeof(xfer_status));
-  _out_ep_closed = false;
-
-  _sof_en = false;
-
-  // clear device address
-  dwc2->dcfg &= ~DCFG_DAD_Msk;
-
-  // 1. NAK for all OUT endpoints
-  for ( uint8_t n = 0; n < ep_count; n++ )
-  {
-    dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
-  }
-
-  // 2. Set up interrupt mask
-  dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
-  dwc2->doepmsk  = DOEPMSK_STUPM | DOEPMSK_XFRCM;
-  dwc2->diepmsk  = DIEPMSK_TOM   | DIEPMSK_XFRCM;
-
-  // "USB Data FIFOs" section in reference manual
-  // Peripheral FIFO architecture
-  //
-  // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
-  // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
-  // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
-  // configuration done below.
-  //
-  // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
-  // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
-  // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
-  // opened when the host sends an additional command: setInterface. At this point in time
-  // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
-  // an additional memory
-  //
-  // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-  // | IN FIFO 0   |
-  // --------------- (320 or 1024) - 16
-  // | IN FIFO 1   |
-  // --------------- (320 or 1024) - 16 - x
-  // |   . . . .   |
-  // --------------- (320 or 1024) - 16 - x - y - ... - z
-  // | IN FIFO MAX |
-  // ---------------
-  // |    FREE     |
-  // --------------- GRXFSIZ
-  // | OUT FIFO    |
-  // | ( Shared )  |
-  // --------------- 0
-  //
-  // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
-  // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
-  //
-  // - All EP OUT shared a unique OUT FIFO which uses
-  //   - 13 for setup packets + control words (up to 3 setup packets).
-  //   - 1 for global NAK (not required/used here).
-  //   - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is  "2 x (Largest-EPsize/4) + 1"
-  //   - 2 for each used OUT endpoint
-  //
-  //   Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
-  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x ep_count = 47  + 2 x ep_count
-  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x ep_count = 271 + 2 x ep_count
-  //
-  //   NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
-  //   of the overall picture yet. We will use the worst scenario: largest possible + ep_count
-  //
-  //   For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
-  //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
-  //   overwrite this.
-
-  // EP0 out max is 64
-  dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
-
-  // Setup the control endpoint 0
-  _allocated_fifo_words_tx = 16;
-
-  // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx);
-
-  // Fixed control EP0 size to 64 bytes
-  dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
-  xfer_status[0][TUSB_DIR_OUT].max_size = 64;
-  xfer_status[0][TUSB_DIR_IN ].max_size = 64;
-
-  dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
-
-  dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
-}
-
-static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
-{
-  (void) rhport;
-
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-
-  // EP0 is limited to one packet each xfer
-  // We use multiple transaction of xfer->max_size length to get a whole transfer done
-  if ( epnum == 0 )
-  {
-    xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, dir);
-    total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
-    ep0_pending[dir] -= total_bytes;
-  }
-
-  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
-  if ( dir == TUSB_DIR_IN )
-  {
-    dwc2_epin_t* epin = dwc2->epin;
-
-    // A full IN transfer (multiple packets, possibly) triggers XFRC.
-    epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
-                           ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
-
-    epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
-
-    // For ISO endpoint set correct odd/even bit for next frame.
-    if ( (epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
-    {
-      // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
-      epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
-    }
-    // Enable fifo empty interrupt only if there are something to put in the fifo.
-    if ( total_bytes != 0 )
-    {
-      dwc2->diepempmsk |= (1 << epnum);
-    }
-  }
-  else
-  {
-    dwc2_epout_t* epout = dwc2->epout;
-
-    // A full OUT transfer (multiple packets, possibly) triggers XFRC.
-    epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
-    epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
-                             ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
-
-    epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
-    if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
-         XFER_CTL_BASE(epnum, dir)->interval == 1 )
-    {
-      // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
-      epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
-    }
-  }
-}
-
-/*------------------------------------------------------------------*/
-/* Controller API
- *------------------------------------------------------------------*/
-#if CFG_TUSB_DEBUG >= DWC2_DEBUG
-void print_dwc2_info(dwc2_regs_t * dwc2)
-{
-  dwc2_ghwcfg2_t const * hw_cfg2 = &dwc2->ghwcfg2_bm;
-  dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm;
-  dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm;
-
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->guid);
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid);
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1);
-
-  // HW configure 2
-  TU_LOG(DWC2_DEBUG, "\r\n");
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg2);
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->op_mode                );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->arch                   );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->point2point            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->hs_phy_type            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->fs_phy_type            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_dev_ep             );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_host_ch            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->period_channel_support );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->enable_dynamic_fifo    );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->mul_cpu_int            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->nperiod_tx_q_depth     );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->host_period_tx_q_depth );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->dev_token_q_depth      );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->otg_enable_ic_usb      );
-
-  // HW configure 3
-  TU_LOG(DWC2_DEBUG, "\r\n");
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg3);
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->xfer_size_width          );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->packet_size_width        );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable               );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->i2c_enable               );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->vendor_ctrl_itf          );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->optional_feature_removed );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->synch_reset              );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_adp_support          );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable_hsic          );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->battery_charger_support  );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->lpm_mode                 );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->total_fifo_size          );
-
-  // HW configure 4
-  TU_LOG(DWC2_DEBUG, "\r\n");
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg4);
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_period_in_ep      );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->power_optimized           );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ahb_freq_min              );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->hibernation               );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->service_interval_mode     );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ipg_isoc_en               );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->acg_enable                );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->utmi_phy_data_width       );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dev_ctrl_ep_num           );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->iddg_filter_enabled       );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->vbus_valid_filter_enabled );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->a_valid_filter_enabled    );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->b_valid_filter_enabled    );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dedicated_fifos           );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_in_eps            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_desc_enable           );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_dynamic               );
+bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
+  TU_VERIFY(addr && data_size);
+  return dwc2_dcache_clean_invalidate(addr, data_size);
 }
 #endif
 
-static void reset_core(dwc2_regs_t * dwc2)
-{
-  // reset core
-  dwc2->grstctl |= GRSTCTL_CSRST;
-
-  // wait for reset bit is cleared
-  // TODO version 4.20a should wait for RESET DONE mask
-  while (dwc2->grstctl & GRSTCTL_CSRST) { }
-
-  // wait for AHB master IDLE
-  while ( !(dwc2->grstctl & GRSTCTL_AHBIDL) ) { }
-
-  // wait for device mode ?
-}
-
-static bool phy_hs_supported(dwc2_regs_t * dwc2)
-{
-  // note: esp32 incorrect report its hs_phy_type as utmi
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-  return false;
-#else
-  return TUD_OPT_HIGH_SPEED && dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
-#endif
-}
-
-static void phy_fs_init(dwc2_regs_t * dwc2)
-{
-  TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n");
-
-  // Select FS PHY
-  dwc2->gusbcfg |= GUSBCFG_PHYSEL;
-
-  // MCU specific PHY init before reset
-  dwc2_phy_init(dwc2, HS_PHY_TYPE_NONE);
-
-  // Reset core after selecting PHY
-  reset_core(dwc2);
-
-  // USB turnaround time is critical for certification where long cables and 5-Hubs are used.
-  // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
-  // these bits can be programmed to a larger value. Default is 5
-  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
-
-  // MCU specific PHY update post reset
-  dwc2_phy_update(dwc2, HS_PHY_TYPE_NONE);
-
-  // set max speed
-  dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
-}
-
-static void phy_hs_init(dwc2_regs_t * dwc2)
-{
-  uint32_t gusbcfg = dwc2->gusbcfg;
-
-  // De-select FS PHY
-  gusbcfg &= ~GUSBCFG_PHYSEL;
-
-  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI)
-  {
-    TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
-
-    // Select ULPI
-    gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
-
-    // ULPI 8-bit interface, single data rate
-    gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
-
-    // default internal VBUS Indicator and Drive
-    gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
-
-    // Disable FS/LS ULPI
-    gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
-  }else
-  {
-    TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n");
-
-    // Select UTMI+ with 8-bit interface
-    gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
-
-    // Set 16-bit interface if supported
-    if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
-  }
-
-  // Apply config
-  dwc2->gusbcfg = gusbcfg;
-
-  // mcu specific phy init
-  dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
-
-  // Reset core after selecting PHY
-  reset_core(dwc2);
-
-  // Set turn-around, must after core reset otherwise it will be clear
-  // - 9 if using 8-bit PHY interface
-  // - 5 if using 16-bit PHY interface
-  gusbcfg &= ~GUSBCFG_TRDT_Msk;
-  gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
-  dwc2->gusbcfg = gusbcfg;
-
-  // MCU specific PHY update post reset
-  dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
-
-  // Set max speed
-  uint32_t dcfg = dwc2->dcfg;
-  dcfg &= ~DCFG_DSPD_Msk;
-  dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
-
-  // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
-  // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
-  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY;
-
-  dwc2->dcfg = dcfg;
-}
-
-static bool check_dwc2(dwc2_regs_t * dwc2)
-{
-#if CFG_TUSB_DEBUG >= DWC2_DEBUG
-  print_dwc2_info(dwc2);
-#endif
-
-  // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
+TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) {
   (void) dwc2;
-#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
-  uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
-  TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
-#endif
+  // Internal DMA only
+  return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
+}
+
+static void dma_setup_prepare(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) {
+    if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) {
+      return;
+    }
+  }
+
+  // Receive only 1 packet
+  dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos);
+  dwc2->epout[0].doepdma = (uintptr_t) _dcd_usbbuf.setup_packet;
+  dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP;
+}
+
+//--------------------------------------------------------------------+
+// Data FIFO
+//--------------------------------------------------------------------+
+
+
+/* Device Data FIFO scheme
+
+  The FIFO is split up into
+  - EPInfo: for storing DMA metadata, only required when use DMA. Maximum size is called
+    EP_LOC_CNT = ep_fifo_size - ghwcfg3.dfifo_depth. For value less than EP_LOC_CNT, gdfifocfg must be configured before
+    gahbcfg.dmaen is set
+      - Buffer mode: 1 word per endpoint direction
+      - Scatter/Gather DMA: 4 words per endpoint direction
+  - TX FIFO: one fifo for each IN endpoint. Size is dynamic depending on packet size, starting from top with EP0 IN.
+  - Shared RX FIFO: a shared fifo for all OUT endpoints. Typically, can hold up to 2 packets of the largest EP size.
+
+  We allocated TX FIFO from top to bottom (using top pointer), this to allow the RX FIFO to grow dynamically which is
+  possible since the free space is located between the RX and TX FIFOs.
+
+   ---------------- ep_fifo_size
+  |  DxEPIDMAn  |
+  |-------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth)
+  | IN FIFO 0   |       control EP
+  |-------------|
+  | IN FIFO 1   |
+  |-------------|
+  |   . . . .   |
+  |-------------|
+  | IN FIFO n   |
+  |-------------|
+  |    FREE     |
+  |-------------|-- GRXFSIZ (expandable)
+  |  OUT FIFO   |
+  | ( Shared )  |
+  --------------- 0
+
+  According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
+  - Each EP IN needs at least max packet size
+  - All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula):
+    - 13 for setup packets + control words (up to 3 setup packets).
+    - 1 for global NAK (not required/used here).
+    - Largest-EPsize/4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is  "2 x (Largest-EPsize/4 + 1)"
+    - 2 for each used OUT endpoint
+
+    Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum
+*/
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_device_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) {
+  return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count;
+}
+
+static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+  const uint8_t ep_count = dwc2_controller->ep_count;
+  const uint8_t epnum = tu_edpt_number(ep_addr);
+  const uint8_t dir = tu_edpt_dir(ep_addr);
+
+  TU_ASSERT(epnum < ep_count);
+
+  uint16_t fifo_size = tu_div_ceil(packet_size, 4);
+  if (dir == TUSB_DIR_OUT) {
+    // Calculate required size of RX FIFO
+    const uint16_t new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count);
+
+    // If size_rx needs to be extended check if there is enough free space
+    if (dwc2->grxfsiz < new_sz) {
+      TU_ASSERT(new_sz <= _dcd_data.dfifo_top);
+      dwc2->grxfsiz = new_sz; // Enlarge RX FIFO
+    }
+  } else {
+    // Check IN endpoints concurrently active limit
+    if(dwc2_controller->ep_in_count) {
+      TU_ASSERT(_dcd_data.allocated_epin_count < dwc2_controller->ep_in_count);
+      _dcd_data.allocated_epin_count++;
+    }
+
+    // If The TXFELVL is configured as half empty, the fifo must be twice the max_size.
+    if ((dwc2->gahbcfg & GAHBCFG_TX_FIFO_EPMTY_LVL) == 0) {
+      fifo_size *= 2;
+    }
+
+    // Check if free space is available
+    TU_ASSERT(_dcd_data.dfifo_top >= fifo_size + dwc2->grxfsiz);
+    _dcd_data.dfifo_top -= fifo_size;
+    // TU_LOG(DWC2_DEBUG, "    TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, dfifo_top);
+
+    // Both TXFD and TXSA are in unit of 32-bit words.
+    if (epnum == 0) {
+      dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dcd_data.dfifo_top;
+    } else {
+      // DIEPTXF starts at FIFO #1.
+      dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dcd_data.dfifo_top;
+    }
+  }
 
   return true;
 }
 
-void dcd_init (uint8_t rhport)
-{
-  // Programming model begins in the last section of the chapter on the USB
-  // peripheral in each Reference Manual.
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+static void dfifo_device_init(uint8_t rhport) {
+  const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  dwc2->grxfsiz = calc_device_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count);
 
-  // Check Synopsys ID register, failed if controller clock/power is not enabled
-  TU_VERIFY(check_dwc2(dwc2), );
+  // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction
+  const bool is_dma = dma_device_enabled(dwc2);
+  _dcd_data.dfifo_top = dwc2_controller->ep_fifo_size/4;
+  if (is_dma) {
+    _dcd_data.dfifo_top -= 2 * dwc2_controller->ep_count;
+  }
+  dwc2->gdfifocfg = (_dcd_data.dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dcd_data.dfifo_top;
 
-  dcd_disconnect(rhport);
+  // Allocate FIFO for EP0 IN
+  dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
+}
 
-  // max number of endpoints & total_fifo_size are:
-  // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size
 
-  if( phy_hs_supported(dwc2) )
-  {
-    // Highspeed
-    phy_hs_init(dwc2);
-  }else
-  {
-    // core does not support highspeed or hs-phy is not present
-    phy_fs_init(dwc2);
+//--------------------------------------------------------------------
+// Endpoint
+//--------------------------------------------------------------------
+static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint_desc) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  const uint8_t dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
+  xfer->interval = p_endpoint_desc->bInterval;
+
+  // Endpoint control
+  union {
+    uint32_t value;
+    dwc2_depctl_t bm;
+  } depctl;
+  depctl.value = 0;
+
+  depctl.bm.mps = xfer->max_size;
+  depctl.bm.active = 1;
+  depctl.bm.type = p_endpoint_desc->bmAttributes.xfer;
+  if (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) {
+    depctl.bm.set_data0_iso_even = 1;
+  }
+  if (dir == TUSB_DIR_IN) {
+    depctl.bm.tx_fifo_num = epnum;
   }
 
-  // Restart PHY clock
-  dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
+  dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
+  dep->ctl = depctl.value;
+  dwc2->daintmsk |= TU_BIT(epnum + DAINT_SHIFT(dir));
+}
 
-	/* Set HS/FS Timeout Calibration to 7 (max available value).
-	 * The number of PHY clocks that the application programs in
-	 * this field is added to the high/full speed interpacket timeout
-	 * duration in the core to account for any additional delays
-	 * introduced by the PHY. This can be required, because the delay
-	 * introduced by the PHY in generating the linestate condition
-	 * can vary from one PHY to another.
-	 */
-  dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
+static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
+  (void) rhport;
+
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const uint8_t epnum = tu_edpt_number(ep_addr);
+  const uint8_t dir = tu_edpt_dir(ep_addr);
+  dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
+
+  if (dir == TUSB_DIR_IN) {
+    // Only disable currently enabled non-control endpoint
+    if ((epnum == 0) || !(dep->diepctl & DIEPCTL_EPENA)) {
+      dep->diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+    } else {
+      // Stop transmitting packets and NAK IN xfers.
+      dep->diepctl |= DIEPCTL_SNAK;
+      while ((dep->diepint & DIEPINT_INEPNE) == 0) {}
+
+      // Disable the endpoint.
+      dep->diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+      while ((dep->diepint & DIEPINT_EPDISD_Msk) == 0) {}
+
+      dep->diepint = DIEPINT_EPDISD;
+    }
+
+    // Flush the FIFO, and wait until we have confirmed it cleared.
+    dfifo_flush_tx(dwc2, epnum);
+  } else {
+    // Only disable currently enabled non-control endpoint
+    if ((epnum == 0) || !(dep->doepctl & DOEPCTL_EPENA)) {
+      dep->doepctl |= stall ? DOEPCTL_STALL : 0;
+    } else {
+      // Asserting GONAK is required to STALL an OUT endpoint.
+      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
+      // anyway, and it can't be cleared by user code. If this while loop never
+      // finishes, we have bigger problems than just the stack.
+      dwc2->dctl |= DCTL_SGONAK;
+      while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {}
+
+      // Ditto here disable the endpoint.
+      dep->doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+      while ((dep->doepint & DOEPINT_EPDISD_Msk) == 0) {}
+
+      dep->doepint = DOEPINT_EPDISD;
+
+      // Allow other OUT endpoints to keep receiving.
+      dwc2->dctl |= DCTL_CGONAK;
+    }
+  }
+}
+
+static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uint8_t dir) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
+  dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
+
+  uint16_t num_packets;
+  uint16_t total_bytes;
+
+  // EP0 is limited to one packet per xfer
+  if (epnum == 0) {
+    total_bytes = tu_min16(_dcd_data.ep0_pending[dir], xfer->max_size);
+    _dcd_data.ep0_pending[dir] -= total_bytes;
+    num_packets = 1;
+  } else {
+    total_bytes = xfer->total_len;
+    num_packets = tu_div_ceil(total_bytes, xfer->max_size);
+    if (num_packets == 0) {
+      num_packets = 1; // zero length packet still count as 1
+    }
+  }
+
+  // transfer size: A full OUT transfer (multiple packets, possibly) triggers XFRC.
+  union {
+    uint32_t value;
+    dwc2_ep_tsize_t bm;
+  } deptsiz;
+  deptsiz.value = 0;
+  deptsiz.bm.xfer_size =  total_bytes;
+  deptsiz.bm.packet_count = num_packets;
+
+  dep->tsiz = deptsiz.value;
+
+  // control
+  union {
+    dwc2_depctl_t bm;
+    uint32_t value;
+  } depctl;
+  depctl.value = dep->ctl;
+
+  depctl.bm.clear_nak = 1;
+  depctl.bm.enable = 1;
+  if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) {
+    const uint32_t odd_now = (dwc2->dsts_bm.frame_number & 1u);
+    if (odd_now) {
+      depctl.bm.set_data0_iso_even = 1;
+    } else {
+      depctl.bm.set_data1_iso_odd = 1;
+    }
+  }
+
+  const bool is_dma = dma_device_enabled(dwc2);
+  if(is_dma) {
+    if (dir == TUSB_DIR_IN && total_bytes != 0) {
+      dcd_dcache_clean(xfer->buffer, total_bytes);
+    }
+    dep->diepdma = (uintptr_t) xfer->buffer;
+    dep->diepctl = depctl.value; // enable endpoint
+  } else {
+    dep->diepctl = depctl.value; // enable endpoint
+
+    // Enable tx fifo empty interrupt only if there is data. Note must after depctl enable
+    if (dir == TUSB_DIR_IN && total_bytes != 0) {
+      dwc2->diepempmsk |= (1 << epnum);
+    }
+  }
+}
+
+//--------------------------------------------------------------------
+// Controller API
+//--------------------------------------------------------------------
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  tu_memclr(&_dcd_data, sizeof(_dcd_data));
+
+  // Core Initialization
+  const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
+  const bool is_dma = dma_device_enabled(dwc2);
+  TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma));
+
+  //------------- 7.1 Device Initialization -------------//
+  // Set device max speed
+  uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk;
+  if (is_highspeed) {
+    dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
+
+    // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
+    // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
+    if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
+      dcfg |= DCFG_XCVRDLY;
+    }
+  } else {
+    dcfg |= DCFG_DSPD_FS << DCFG_DSPD_Pos;
+  }
+
+  dcfg |= DCFG_NZLSOHSK; // send STALL back and discard if host send non-zlp during control status
+  dwc2->dcfg = dcfg;
+
+  dcd_disconnect(rhport);
 
   // Force device mode
   dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
@@ -524,58 +428,39 @@ void dcd_init (uint8_t rhport)
   // Clear A override, force B Valid
   dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
 
-  // If USB host misbehaves during status portion of control xfer
-  // (non zero-length packet), send STALL back and discard.
-  dwc2->dcfg |= DCFG_NZLSOHSK;
+  // Enable required interrupts
+  dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
 
-  // Clear all interrupts
-  dwc2->gintsts |= dwc2->gintsts;
-  dwc2->gotgint |= dwc2->gotgint;
-
-  // Required as part of core initialization.
-  // TODO: How should mode mismatch be handled? It will cause
-  // the core to stop working/require reset.
-  dwc2->gintmsk = GINTMSK_OTGINT   | GINTMSK_MMISM  | GINTMSK_RXFLVLM  |
-                  GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
-
-  // Enable global interrupt
-  dwc2->gahbcfg |= GAHBCFG_GINT;
-
-  // make sure we are in device mode
-//  TU_ASSERT(!(dwc2->gintsts & GINTSTS_CMOD), );
-
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gahbcfg);
+  // TX FIFO empty level for interrupt is complete empty
+  uint32_t gahbcfg = dwc2->gahbcfg;
+  gahbcfg |= GAHBCFG_TX_FIFO_EPMTY_LVL;
+  gahbcfg |= GAHBCFG_GINT; // Enable global interrupt
+  dwc2->gahbcfg = gahbcfg;
 
   dcd_connect(rhport);
+  return true;
 }
 
-void dcd_int_enable (uint8_t rhport)
-{
+void dcd_int_enable(uint8_t rhport) {
   dwc2_dcd_int_enable(rhport);
 }
 
-void dcd_int_disable (uint8_t rhport)
-{
+void dcd_int_disable(uint8_t rhport) {
   dwc2_dcd_int_disable(rhport);
 }
 
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   dwc2->dcfg = (dwc2->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
 
   // Response with status after changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
 
-void dcd_remote_wakeup(uint8_t rhport)
-{
+void dcd_remote_wakeup(uint8_t rhport) {
   (void) rhport;
 
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   // set remote wakeup
   dwc2->dctl |= DCTL_RWUSIG;
@@ -590,35 +475,51 @@ void dcd_remote_wakeup(uint8_t rhport)
   dwc2->dctl &= ~DCTL_RWUSIG;
 }
 
-void dcd_connect(uint8_t rhport)
-{
+void dcd_connect(uint8_t rhport) {
   (void) rhport;
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+#ifdef TUP_USBIP_DWC2_ESP32
+  usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+  conf.pad_pull_override = 0;
+  conf.dp_pullup = 0;
+  conf.dp_pulldown = 0;
+  conf.dm_pullup = 0;
+  conf.dm_pulldown = 0;
+  USB_WRAP.otg_conf = conf;
+#endif
+
   dwc2->dctl &= ~DCTL_SDIS;
 }
 
-void dcd_disconnect(uint8_t rhport)
-{
+void dcd_disconnect(uint8_t rhport) {
   (void) rhport;
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+#ifdef TUP_USBIP_DWC2_ESP32
+  usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+  conf.pad_pull_override = 1;
+  conf.dp_pullup = 0;
+  conf.dp_pulldown = 1;
+  conf.dm_pullup = 0;
+  conf.dm_pulldown = 1;
+  USB_WRAP.otg_conf = conf;
+#endif
+
   dwc2->dctl |= DCTL_SDIS;
 }
 
 // Be advised: audio, video and possibly other iso-ep classes use dcd_sof_enable() to enable/disable its corresponding ISR on purpose!
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
   (void) rhport;
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
-  _sof_en = en;
+  _dcd_data.sof_en = en;
 
-  if (en)
-  {
+  if (en) {
     dwc2->gintsts = GINTSTS_SOF;
     dwc2->gintmsk |= GINTMSK_SOFM;
-  }
-  else
-  {
+  } else {
     dwc2->gintmsk &= ~GINTMSK_SOFM;
   }
 }
@@ -627,144 +528,66 @@ void dcd_sof_enable(uint8_t rhport, bool en)
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
 
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
-  (void) rhport;
-
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
-  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
-
-  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
-
-  TU_ASSERT(epnum < ep_count);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = tu_edpt_packet_size(desc_edpt);
-  xfer->interval = desc_edpt->bInterval;
-
-  uint16_t const fifo_size = tu_div_ceil(xfer->max_size, 4);
-
-  if(dir == TUSB_DIR_OUT)
-  {
-    // Calculate required size of RX FIFO
-    uint16_t const sz = calc_grxfsiz(4*fifo_size, ep_count);
-
-    // If size_rx needs to be extended check if possible and if so enlarge it
-    if (dwc2->grxfsiz < sz)
-    {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size/4);
-
-      // Enlarge RX FIFO
-      dwc2->grxfsiz = sz;
-    }
-
-    dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) |
-                                  (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
-                                  (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
-                                  (xfer->max_size << DOEPCTL_MPSIZ_Pos);
-
-    dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
-  }
-  else
-  {
-    // "USB Data FIFOs" section in reference manual
-    // Peripheral FIFO architecture
-    //
-    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-    // | IN FIFO 0   |
-    // --------------- (320 or 1024) - 16
-    // | IN FIFO 1   |
-    // --------------- (320 or 1024) - 16 - x
-    // |   . . . .   |
-    // --------------- (320 or 1024) - 16 - x - y - ... - z
-    // | IN FIFO MAX |
-    // ---------------
-    // |    FREE     |
-    // --------------- GRXFSIZ
-    // | OUT FIFO    |
-    // | ( Shared )  |
-    // --------------- 0
-    //
-    // In FIFO is allocated by following rules:
-    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
-
-    // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size/4);
-
-    _allocated_fifo_words_tx += fifo_size;
-
-    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size*4, _dwc2_controller[rhport].ep_fifo_size-_allocated_fifo_words_tx*4);
-
-    // DIEPTXF starts at FIFO #1.
-    // Both TXFD and TXSA are in unit of 32-bit words.
-    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (_dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx);
-
-    dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
-                                 (epnum << DIEPCTL_TXFNUM_Pos) |
-                                 (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
-                                 (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
-                                 (xfer->max_size << DIEPCTL_MPSIZ_Pos);
-
-    dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
-  }
-
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
+  TU_ASSERT(dfifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt)));
+  edpt_activate(rhport, desc_edpt);
   return true;
 }
 
 // Close all non-control endpoints, cancel all pending transfers if any.
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+void dcd_edpt_close_all(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
+  _dcd_data.allocated_epin_count = 0;
+
   // Disable non-control interrupt
   dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
 
-  for(uint8_t n = 1; n < ep_count; n++)
-  {
-    // disable OUT endpoint
-    dwc2->epout[n].doepctl = 0;
-    xfer_status[n][TUSB_DIR_OUT].max_size = 0;
-
-    // disable IN endpoint
-    dwc2->epin[n].diepctl = 0;
-    xfer_status[n][TUSB_DIR_IN].max_size = 0;
+  for (uint8_t n = 1; n < ep_count; n++) {
+    for (uint8_t d = 0; d < 2; d++) {
+      dwc2_dep_t* dep = &dwc2->ep[d][n];
+      if (dep->ctl & EPCTL_EPENA) {
+        dep->ctl |= EPCTL_SNAK | EPCTL_EPDIS;
+      }
+      xfer_status[n][1-d].max_size = 0;
+    }
   }
 
-  // reset allocated fifo IN
-  _allocated_fifo_words_tx = 16;
+  dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+  dfifo_flush_rx(dwc2);
+
+  dfifo_device_init(rhport); // re-init dfifo
 }
 
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
+  TU_ASSERT(dfifo_alloc(rhport, ep_addr, largest_packet_size));
+  return true;
+}
 
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = buffer;
-  xfer->ff          = NULL;
-  xfer->total_len   = total_bytes;
+bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc) {
+  // Disable EP to clear potential incomplete transfers
+  edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false);
+  edpt_activate(rhport, p_endpoint_desc);
+  return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer = buffer;
+  xfer->ff = NULL;
+  xfer->total_len = total_bytes;
 
   // EP0 can only handle one packet
-  if(epnum == 0)
-  {
-    ep0_pending[dir] = total_bytes;
-
-    // Schedule the first transaction for EP0 transfer
-    edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
+  if (epnum == 0) {
+    _dcd_data.ep0_pending[dir] = total_bytes;
   }
-  else
-  {
-    uint16_t num_packets = (total_bytes / xfer->max_size);
-    uint16_t const short_packet_size = total_bytes % xfer->max_size;
 
-    // Zero-size packet is special case.
-    if ( (short_packet_size > 0) || (total_bytes == 0) ) num_packets++;
-
-    // Schedule packets to be sent within interrupt
-    edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
-  }
+  // Schedule packets to be sent within interrupt
+  edpt_schedule_packets(rhport, epnum, dir);
 
   return true;
 }
@@ -773,496 +596,415 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 // bytes should be written and second to keep the return value free to give back a boolean
 // success message. If total_bytes is too big, the FIFO will copy only what is available
 // into the USB buffer!
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes) {
   // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
   TU_ASSERT(ff->item_size == 1);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = NULL;
-  xfer->ff          = ff;
-  xfer->total_len   = total_bytes;
-
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint16_t const short_packet_size = total_bytes % xfer->max_size;
-
-  // Zero-size packet is special case.
-  if ( short_packet_size > 0 || (total_bytes == 0) ) num_packets++;
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer = NULL;
+  xfer->ff = ff;
+  xfer->total_len = total_bytes;
 
   // Schedule packets to be sent within interrupt
-  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+  // TODO xfer fifo may only available for slave mode
+  edpt_schedule_packets(rhport, epnum, dir);
 
   return true;
 }
 
-static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
-{
-  (void) rhport;
-
-  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  if ( dir == TUSB_DIR_IN )
-  {
-    dwc2_epin_t* epin = dwc2->epin;
-
-    // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA) )
-    {
-      epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
-    }
-    else
-    {
-      // Stop transmitting packets and NAK IN xfers.
-      epin[epnum].diepctl |= DIEPCTL_SNAK;
-      while ( (epin[epnum].diepint & DIEPINT_INEPNE) == 0 ) {}
-
-      // Disable the endpoint.
-      epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
-      while ( (epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {}
-
-      epin[epnum].diepint = DIEPINT_EPDISD;
-    }
-
-    // Flush the FIFO, and wait until we have confirmed it cleared.
-    dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH);
-    while ( (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
-  }
-  else
-  {
-    dwc2_epout_t* epout = dwc2->epout;
-
-    // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA) )
-    {
-      epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
-    }
-    else
-    {
-      // Asserting GONAK is required to STALL an OUT endpoint.
-      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
-      // anyway, and it can't be cleared by user code. If this while loop never
-      // finishes, we have bigger problems than just the stack.
-      dwc2->dctl |= DCTL_SGONAK;
-      while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
-
-      // Ditto here- disable the endpoint.
-      epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
-      while ( (epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {}
-
-      epout[epnum].doepint = DOEPINT_EPDISD;
-
-      // Allow other OUT endpoints to keep receiving.
-      dwc2->dctl |= DCTL_CGONAK;
-    }
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  edpt_disable(rhport, ep_addr, true);
+  if((tu_edpt_number(ep_addr) == 0) && dma_device_enabled(dwc2)) {
+    dma_setup_prepare(rhport);
   }
 }
 
-/**
- * Close an endpoint.
- */
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  dcd_edpt_disable(rhport, ep_addr, false);
-
-  // Update max_size
-  xfer_status[epnum][dir].max_size = 0;  // max_size = 0 marks a disabled EP - required for changing FIFO allocation
-
-  if (dir == TUSB_DIR_IN)
-  {
-    uint16_t const fifo_size = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
-    uint16_t const fifo_start = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
-
-    // For now only the last opened endpoint can be closed without fuss.
-    TU_ASSERT(fifo_start == _dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx,);
-    _allocated_fifo_words_tx -= fifo_size;
-  }
-  else
-  {
-    _out_ep_closed = true;     // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
-  }
-}
-
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  dcd_edpt_disable(rhport, ep_addr, true);
-}
-
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+  dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
 
   // Clear stall and reset data toggle
-  if ( dir == TUSB_DIR_IN )
-  {
-    dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL;
-    dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM;
-  }
-  else
-  {
-    dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL;
-    dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM;
-  }
+  dep->ctl &= ~EPCTL_STALL;;
+  dep->ctl |= EPCTL_SD0PID_SEVNFRM;
 }
 
-/*------------------------------------------------------------------*/
+//--------------------------------------------------------------------
+// Interrupt Handler
+//--------------------------------------------------------------------
 
-// Read a single data packet from receive FIFO
-static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
-{
-  (void) rhport;
+// 7.4.1 Initialization on USB Reset
+static void handle_bus_reset(uint8_t rhport) {
+  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
+  const uint8_t ep_count =  DWC2_EP_COUNT(dwc2);
 
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  volatile const uint32_t * rx_fifo = dwc2->fifo[0];
+  tu_memclr(xfer_status, sizeof(xfer_status));
 
-  // Reading full available 32 bit words from fifo
-  uint16_t full_words = len >> 2;
-  while(full_words--)
-  {
-    tu_unaligned_write32(dst, *rx_fifo);
-    dst += 4;
+  _dcd_data.sof_en = false;
+  _dcd_data.allocated_epin_count = 0;
+
+  // 1. NAK for all OUT endpoints
+  for (uint8_t n = 0; n < ep_count; n++) {
+    dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
 
-  // Read the remaining 1-3 bytes from fifo
-  uint8_t const bytes_rem = len & 0x03;
-  if ( bytes_rem != 0 )
-  {
-    uint32_t const tmp = *rx_fifo;
-    dst[0] = tu_u32_byte0(tmp);
-    if ( bytes_rem > 1 ) dst[1] = tu_u32_byte1(tmp);
-    if ( bytes_rem > 2 ) dst[2] = tu_u32_byte2(tmp);
+  // Disable all IN endpoints
+  for (uint8_t n = 0; n < ep_count; n++) {
+    if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
+      dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+    }
   }
+
+  // 2. Set up interrupt mask for EP0
+  dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
+  dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
+  dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
+
+  // 4. Set up DFIFO
+  dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+  dfifo_flush_rx(dwc2);
+  dfifo_device_init(rhport);
+
+  // 5. Reset device address
+  dwc2->dcfg_bm.address = 0;
+
+  // Fixed both control EP0 size to 64 bytes
+  dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
+  dwc2->epout[0].ctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos);
+
+  xfer_status[0][TUSB_DIR_OUT].max_size = 64;
+  xfer_status[0][TUSB_DIR_IN].max_size = 64;
+
+  if(dma_device_enabled(dwc2)) {
+    dma_setup_prepare(rhport);
+  } else {
+    dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+  }
+
+  dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
-// Write a single data packet to EPIN FIFO
-static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const * src, uint16_t len)
-{
-  (void) rhport;
+static void handle_enum_done(uint8_t rhport) {
+  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
+  tusb_speed_t speed;
+  switch (dwc2->dsts_bm.enum_speed) {
+    case DCFG_SPEED_HIGH:
+      speed = TUSB_SPEED_HIGH;
+    break;
 
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  volatile uint32_t * tx_fifo = dwc2->fifo[fifo_num];
+    case DCFG_SPEED_LOW:
+      speed = TUSB_SPEED_LOW;
+    break;
 
-  // Pushing full available 32 bit words to fifo
-  uint16_t full_words = len >> 2;
-  while(full_words--)
-  {
-    *tx_fifo = tu_unaligned_read32(src);
-    src += 4;
+    case DCFG_SPEED_FULL_30_60MHZ:
+    case DCFG_SPEED_FULL_48MHZ:
+    default:
+      speed = TUSB_SPEED_FULL;
+    break;
   }
 
-  // Write the remaining 1-3 bytes into fifo
-  uint8_t const bytes_rem = len & 0x03;
-  if ( bytes_rem )
-  {
-    uint32_t tmp_word = src[0];
-    if ( bytes_rem > 1 ) tmp_word |= (src[1] << 8);
-    if ( bytes_rem > 2 ) tmp_word |= (src[2] << 16);
-
-    *tx_fifo = tmp_word;
-  }
+  // TODO must update GUSBCFG_TRDT according to link speed
+  dcd_event_bus_reset(rhport, speed, true);
 }
 
-static void handle_rxflvl_irq(uint8_t rhport)
-{
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  volatile uint32_t const * rx_fifo = dwc2->fifo[0];
+#if 0
+TU_ATTR_ALWAYS_INLINE static inline void print_doepint(uint32_t doepint) {
+  const char* str[] = {
+    "XFRC", "DIS", "AHBERR", "SETUP_DONE",
+    "ORXED", "STATUS_RX", "SETUP_B2B", "RSV7",
+    "OPERR", "BNA", "RSV10", "ISODROP",
+    "BBLERR", "NAK", "NYET", "SETUP_RX"
+  };
+
+  for(uint32_t i=0; i<TU_ARRAY_SIZE(str); i++) {
+    if (doepint & TU_BIT(i)) {
+      TU_LOG1("%s ", str[i]);
+    }
+  }
+  TU_LOG1("\r\n");
+}
+#endif
+
+#if CFG_TUD_DWC2_SLAVE_ENABLE
+// Process shared receive FIFO, this interrupt is only used in Slave mode
+static void handle_rxflvl_irq(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const volatile uint32_t* rx_fifo = dwc2->fifo[0];
 
   // Pop control word off FIFO
-  uint32_t const ctl_word = dwc2->grxstsp;
-  uint8_t  const pktsts   = (ctl_word & GRXSTSP_PKTSTS_Msk ) >> GRXSTSP_PKTSTS_Pos;
-  uint8_t  const epnum    = (ctl_word & GRXSTSP_EPNUM_Msk  ) >> GRXSTSP_EPNUM_Pos;
-  uint16_t const bcnt     = (ctl_word & GRXSTSP_BCNT_Msk   ) >> GRXSTSP_BCNT_Pos;
+  const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm;
+  const uint8_t epnum = grxstsp_bm.ep_ch_num;
 
-  dwc2_epout_t* epout = &dwc2->epout[epnum];
+  dwc2_dep_t* epout = &dwc2->epout[epnum];
 
-//#if CFG_TUSB_DEBUG >= DWC2_DEBUG
-//  const char * pktsts_str[] =
-//  {
-//    "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)",
-//    "Setup Complete (ISR)", "ASSERT", "Setup Data Received"
-//  };
-//  TU_LOG_LOCATION();
-//  TU_LOG(DWC2_DEBUG, "  EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]);
-//  TU_LOG(DWC2_DEBUG, "  daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint);
-//#endif
+  switch (grxstsp_bm.packet_status) {
+    case GRXSTS_PKTSTS_GLOBAL_OUT_NAK:
+      // Global OUT NAK: do nothing
+      break;
 
-  switch ( pktsts )
-  {
-    // Global OUT NAK: do nothign
-    case GRXSTS_PKTSTS_GLOBALOUTNAK: break;
-
-    case GRXSTS_PKTSTS_SETUPRX:
+    case GRXSTS_PKTSTS_SETUP_RX: {
       // Setup packet received
+      uint32_t* setup = (uint32_t*)(uintptr_t) _dcd_usbbuf.setup_packet;
+      // We can receive up to three setup packets in succession, but only the last one is valid.
+      setup[0] = (*rx_fifo);
+      setup[1] = (*rx_fifo);
+      break;
+    }
 
-      // We can receive up to three setup packets in succession, but
-      // only the last one is valid.
-      _setup_packet[0] = (*rx_fifo);
-      _setup_packet[1] = (*rx_fifo);
-    break;
-
-    case GRXSTS_PKTSTS_SETUPDONE:
-      // Setup packet done (Interrupt)
+    case GRXSTS_PKTSTS_SETUP_DONE:
+      // Setup packet done:
+      // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq()
       epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
-    break;
+      break;
 
-    case GRXSTS_PKTSTS_OUTRX:
-    {
+    case GRXSTS_PKTSTS_RX_DATA: {
       // Out packet received
-      xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+      const uint16_t byte_count = grxstsp_bm.byte_count;
+      xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
-      // Read packet off RxFIFO
-      if ( xfer->ff )
-      {
-        // Ring buffer
-        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
-      }
-      else
-      {
-        // Linear buffer
-        read_fifo_packet(rhport, xfer->buffer, bcnt);
-
-        // Increment pointer to xfer data
-        xfer->buffer += bcnt;
-      }
-
-      // Truncate transfer length in case of short packet
-      if ( bcnt < xfer->max_size )
-      {
-        xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
-        if ( epnum == 0 )
-        {
-          xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
-          ep0_pending[TUSB_DIR_OUT] = 0;
+      if (byte_count) {
+        // Read packet off RxFIFO
+        if (xfer->ff) {
+          tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count);
+        } else {
+          dfifo_read_packet(dwc2, xfer->buffer, byte_count);
+          xfer->buffer += byte_count;
         }
-      }
-    }
-    break;
 
-    // Out packet done (Interrupt)
-    case GRXSTS_PKTSTS_OUTDONE:
-        // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a
-        // May (or not) be 3.10a specific feature/bug or depending on MCU configuration
-        // XFRC complete is additionally generated when
-        // - setup packet is received
-        // - complete the data stage of control write is complete
-        if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a))
-        {
-          uint32_t doepint = epout->doepint;
-
-          if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR))
-          {
-            // skip this "no-data" transfer complete event
-            // Note: STPKTRX will be clear later by setup received handler
-            uint32_t clear_flags = DOEPINT_XFRC;
-
-            if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR;
-
-            epout->doepint = clear_flags;
-
-            // TU_LOG(DWC2_DEBUG, "  FIX extra transfer complete on setup/data compete\r\n");
+        // short packet, minus remaining bytes (xfer_size)
+        if (byte_count < xfer->max_size) {
+          xfer->total_len -= epout->tsiz_bm.xfer_size;
+          if (epnum == 0) {
+            xfer->total_len -= _dcd_data.ep0_pending[TUSB_DIR_OUT];
+            _dcd_data.ep0_pending[TUSB_DIR_OUT] = 0;
           }
         }
-    break;
+      }
+      break;
+    }
 
-    default:    // Invalid
-      TU_BREAKPOINT();
-    break;
+    case GRXSTS_PKTSTS_RX_COMPLETE:
+      // Out packet done
+      // After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on
+      // the specified OUT endpoint which will be handled by handle_epout_irq()
+      break;
+
+    default: break;
   }
 }
 
-static void handle_epout_irq (uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
-  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) {
+  if (doepint_bm.setup_phase_done) {
+    dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true);
+    return;
+  }
 
-  // DAINT for a given EP clears when DOEPINTx is cleared.
-  // OEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < ep_count; n++ )
-  {
-    if ( dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n) )
-    {
-      dwc2_epout_t* epout = &dwc2->epout[n];
+  // Normal OUT transfer complete
+  if (doepint_bm.xfer_complete) {
+    // only handle data skip if it is setup or status related
+    // Note: even though (xfer_complete + status_phase_rx) is for buffered DMA only, for STM32L47x (dwc2 v3.00a) they
+    // can is set when GRXSTS_PKTSTS_SETUP_RX is popped therefore they can bet set before/together with setup_phase_done
+    if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
+      xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
-      uint32_t const doepint = epout->doepint;
-
-      // SETUP packet Setup Phase done.
-      if ( doepint & DOEPINT_STUP )
-      {
-        uint32_t clear_flag = DOEPINT_STUP;
-
-        // STPKTRX is only available for version from 3_00a
-        if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a))
-        {
-          clear_flag |= DOEPINT_STPKTRX;
-        }
-
-        epout->doepint = clear_flag;
-        dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
-      }
-
-      // OUT XFER complete
-      if ( epout->doepint & DOEPINT_XFRC )
-      {
-        epout->doepint = DOEPINT_XFRC;
-
-        xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
-        // EP0 can only handle one packet
-        if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] )
-        {
-          // Schedule another packet to be received.
-          edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
-        }
-        else
-        {
-          dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
+      if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) {
+        // EP0 can only handle one packet, Schedule another packet to be received.
+        edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
+      } else {
+        dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
       }
     }
   }
 }
 
-static void handle_epin_irq (uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
-  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
-  dwc2_epin_t* epin      = dwc2->epin;
+static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  dwc2_dep_t* epin = &dwc2->epin[epnum];
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
 
-  // DAINT for a given EP clears when DIEPINTx is cleared.
-  // IEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < ep_count; n++ )
-  {
-    if ( dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n) )
-    {
-      // IN XFER complete (entire xfer).
-      xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
+  if (diepint_bm.xfer_complete) {
+    if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) {
+      // EP0 can only handle one packet. Schedule another packet to be transmitted.
+      edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
+    } else {
+      dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+    }
+  }
 
-      if ( epin[n].diepint & DIEPINT_XFRC )
-      {
-        epin[n].diepint = DIEPINT_XFRC;
+  // TX FIFO empty bit is read-only. It will only be cleared by hardware when written bytes is more than
+  // - 64 bytes or
+  // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL)
+  if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) {
+    const uint16_t remain_packets = epin->tsiz_bm.packet_count;
 
-        // EP0 can only handle one packet
-        if ( (n == 0) && ep0_pending[TUSB_DIR_IN] )
-        {
-          // Schedule another packet to be transmitted.
-          edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
-        }
-        else
-        {
-          dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
+    // Process every single packet (only whole packets can be written to fifo)
+    for (uint16_t i = 0; i < remain_packets; i++) {
+      const uint16_t remain_bytes = (uint16_t) epin->tsiz_bm.xfer_size;
+      const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size);
+
+      // Check if dtxfsts has enough space available
+      if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) {
+        break;
       }
 
-      // XFER FIFO empty
-      if ( (epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
-      {
-        // diepint's TXFE bit is read-only, software cannot clear it.
-        // It will only be cleared by hardware when written bytes is more than
-        // - 64 bytes or
-        // - Half of TX FIFO size (configured by DIEPTXF)
+      // Push packet to Tx-FIFO
+      if (xfer->ff) {
+        volatile uint32_t* tx_fifo = dwc2->fifo[epnum];
+        tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*)(uintptr_t)tx_fifo, xact_bytes);
+      } else {
+        dfifo_write_packet(dwc2, epnum, xfer->buffer, xact_bytes);
+        xfer->buffer += xact_bytes;
+      }
+    }
 
-        uint16_t remaining_packets = (epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
+    // Turn off TXFE if all bytes are written.
+    if (epin->tsiz_bm.xfer_size == 0) {
+      dwc2->diepempmsk &= ~(1 << epnum);
+    }
+  }
+}
+#endif
 
-        // Process every single packet (only whole packets can be written to fifo)
-        for ( uint16_t i = 0; i < remaining_packets; i++ )
-        {
-          uint16_t const remaining_bytes = (epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
+#if CFG_TUD_DWC2_DMA_ENABLE
+static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
-          // Packet can not be larger than ep max size
-          uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
+  if (doepint_bm.setup_phase_done) {
+    dma_setup_prepare(rhport);
+    dcd_dcache_invalidate(_dcd_usbbuf.setup_packet, 8);
+    dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true);
+    return;
+  }
 
-          // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
-          // EP has to be checked if the buffer can take another WHOLE packet
-          if ( packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2) ) break;
+  // OUT XFER complete
+  if (doepint_bm.xfer_complete) {
+    // only handle data skip if it is setup or status related
+    // Normal OUT transfer complete
+    if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
+      if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) {
+        // EP0 can only handle one packet Schedule another packet to be received.
+        edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
+      } else {
+        dwc2_dep_t* epout = &dwc2->epout[epnum];
+        xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
-          // Push packet to Tx-FIFO
-          if ( xfer->ff )
-          {
-            volatile uint32_t *tx_fifo = dwc2->fifo[n];
-            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size);
-          }
-          else
-          {
-            write_fifo_packet(rhport, n, xfer->buffer, packet_size);
+        // determine actual received bytes
+        const uint16_t remain = epout->tsiz_bm.xfer_size;
+        xfer->total_len -= remain;
 
-            // Increment pointer to xfer data
-            xfer->buffer += packet_size;
-          }
+        // this is ZLP, so prepare EP0 for next setup
+        // TODO use status phase rx
+        if(epnum == 0 && xfer->total_len == 0) {
+          dma_setup_prepare(rhport);
         }
 
-        // Turn off TXFE if all bytes are written.
-        if ( ((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 )
-        {
-          dwc2->diepempmsk &= ~(1 << n);
-        }
+        dcd_dcache_invalidate(xfer->buffer, xfer->total_len);
+        dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
       }
     }
   }
 }
 
-void dcd_int_handler(uint8_t rhport)
-{
-  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
+static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) {
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
 
-  uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk;
+  if (diepint_bm.xfer_complete) {
+    if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) {
+      // EP0 can only handle one packet. Schedule another packet to be transmitted.
+      edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
+    } else {
+      if(epnum == 0) {
+        dma_setup_prepare(rhport);
+      }
+      dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+    }
+  }
+}
+#endif
 
-  if(int_status & GINTSTS_USBRST)
-  {
+static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const bool is_dma = dma_device_enabled(dwc2);
+  const uint8_t ep_count = DWC2_EP_COUNT(dwc2);
+  const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos;
+  dwc2_dep_t* ep_base = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][0];
+
+  // DAINT for a given EP clears when DEPINTx is cleared.
+  // EPINT will be cleared when DAINT bits are cleared.
+  for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
+    if (dwc2->daint & TU_BIT(daint_offset + epnum)) {
+      dwc2_dep_t* epout = &ep_base[epnum];
+      union {
+        uint32_t value;
+        dwc2_diepint_t diepint_bm;
+        dwc2_doepint_t doepint_bm;
+      } intr;
+      intr.value = epout->intr;
+
+      epout->intr = intr.value; // Clear interrupt
+
+      if (is_dma) {
+        #if CFG_TUD_DWC2_DMA_ENABLE
+        if (dir == TUSB_DIR_IN) {
+          handle_epin_dma(rhport, epnum, intr.diepint_bm);
+        } else {
+          handle_epout_dma(rhport, epnum, intr.doepint_bm);
+        }
+        #endif
+      } else {
+        #if CFG_TUD_DWC2_SLAVE_ENABLE
+        if (dir == TUSB_DIR_IN) {
+          handle_epin_slave(rhport, epnum, intr.diepint_bm);
+        } else {
+          handle_epout_slave(rhport, epnum, intr.doepint_bm);
+        }
+        #endif
+      }
+    }
+  }
+}
+
+/* Interrupt Hierarchy
+                 DIEPINT  DIEPINT
+                    \       /
+                     \     /
+                      DAINT
+                     /     \
+                    /       \
+     GINTSTS:    OEPInt    IEPInt | USBReset | EnumDone | USBSusp | WkUpInt | OTGInt | SOF | RXFLVL
+
+  Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk
+  are combined to generate dedicated interrupt line for each endpoint.
+ */
+void dcd_int_handler(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  const uint32_t gintmask = dwc2->gintmsk;
+  const uint32_t gintsts = dwc2->gintsts & gintmask;
+
+  if (gintsts & GINTSTS_USBRST) {
     // USBRST is start of reset.
     dwc2->gintsts = GINTSTS_USBRST;
-    bus_reset(rhport);
+    handle_bus_reset(rhport);
   }
 
-  if(int_status & GINTSTS_ENUMDNE)
-  {
+  if (gintsts & GINTSTS_ENUMDNE) {
     // ENUMDNE is the end of reset where speed of the link is detected
-
     dwc2->gintsts = GINTSTS_ENUMDNE;
-
-    tusb_speed_t speed;
-    switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos)
-    {
-      case DSTS_ENUMSPD_HS:
-        speed = TUSB_SPEED_HIGH;
-      break;
-
-      case DSTS_ENUMSPD_LS:
-        speed = TUSB_SPEED_LOW;
-      break;
-
-      case DSTS_ENUMSPD_FS_HSPHY:
-      case DSTS_ENUMSPD_FS:
-      default:
-        speed = TUSB_SPEED_FULL;
-      break;
-    }
-
-    dcd_event_bus_reset(rhport, speed, true);
+    handle_enum_done(rhport);
   }
 
-  if(int_status & GINTSTS_USBSUSP)
-  {
+  if (gintsts & GINTSTS_USBSUSP) {
     dwc2->gintsts = GINTSTS_USBSUSP;
     dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
   }
 
-  if(int_status & GINTSTS_WKUINT)
-  {
+  if (gintsts & GINTSTS_WKUINT) {
     dwc2->gintsts = GINTSTS_WKUINT;
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
   }
@@ -1270,82 +1012,63 @@ void dcd_int_handler(uint8_t rhport)
   // TODO check GINTSTS_DISCINT for disconnect detection
   // if(int_status & GINTSTS_DISCINT)
 
-  if(int_status & GINTSTS_OTGINT)
-  {
+  if (gintsts & GINTSTS_OTGINT) {
     // OTG INT bit is read-only
-    uint32_t const otg_int = dwc2->gotgint;
+    const uint32_t otg_int = dwc2->gotgint;
 
-    if (otg_int & GOTGINT_SEDET)
-    {
+    if (otg_int & GOTGINT_SEDET) {
       dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
     }
 
     dwc2->gotgint = otg_int;
   }
 
-  if(int_status & GINTSTS_SOF)
-  {
-    dwc2->gotgint = GINTSTS_SOF;
+  if(gintsts & GINTSTS_SOF) {
+    dwc2->gintsts = GINTSTS_SOF;
+    const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos;
 
-    if (_sof_en)
-    {
-      uint32_t frame = (dwc2->dsts & (DSTS_FNSOF)) >> 8;
-      dcd_event_sof(rhport, frame, true);
-    }
-    else
-    {
-      // Disable SOF interrupt if SOF was not explicitly enabled. SOF was used for remote wakeup detection
+    // Disable SOF interrupt if SOF was not explicitly enabled since SOF was used for remote wakeup detection
+    if (!_dcd_data.sof_en) {
       dwc2->gintmsk &= ~GINTMSK_SOFM;
     }
 
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+    dcd_event_sof(rhport, frame, true);
   }
 
+#if CFG_TUD_DWC2_SLAVE_ENABLE
   // RxFIFO non-empty interrupt handling.
-  if(int_status & GINTSTS_RXFLVL)
-  {
+  if (gintsts & GINTSTS_RXFLVL) {
     // RXFLVL bit is read-only
+    dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading
 
-    // Mask out RXFLVL while reading data from FIFO
-    dwc2->gintmsk &= ~GINTMSK_RXFLVLM;
-
-    // Loop until all available packets were handled
-    do
-    {
-      handle_rxflvl_irq(rhport);
-    } while(dwc2->gotgint & GINTSTS_RXFLVL);
-
-    // Manage RX FIFO size
-    if (_out_ep_closed)
-    {
-      update_grxfsiz(rhport);
-
-      // Disable flag
-      _out_ep_closed = false;
-    }
+    do {
+      handle_rxflvl_irq(rhport); // read all packets
+    } while(dwc2->gintsts & GINTSTS_RXFLVL);
 
     dwc2->gintmsk |= GINTMSK_RXFLVLM;
   }
+#endif
 
   // OUT endpoint interrupt handling.
-  if(int_status & GINTSTS_OEPINT)
-  {
+  if (gintsts & GINTSTS_OEPINT) {
     // OEPINT is read-only, clear using DOEPINTn
-    handle_epout_irq(rhport);
+    handle_ep_irq(rhport, TUSB_DIR_OUT);
   }
 
   // IN endpoint interrupt handling.
-  if(int_status & GINTSTS_IEPINT)
-  {
+  if (gintsts & GINTSTS_IEPINT) {
     // IEPINT bit read-only, clear using DIEPINTn
-    handle_epin_irq(rhport);
+    handle_ep_irq(rhport, TUSB_DIR_IN);
   }
-
-  //  // Check for Incomplete isochronous IN transfer
-  //  if(int_status & GINTSTS_IISOIXFR) {
-  //    printf("      IISOIXFR!\r\n");
-  ////    TU_LOG(DWC2_DEBUG, "      IISOIXFR!\r\n");
-  //  }
 }
 
+#if CFG_TUD_TEST_MODE
+void dcd_enter_test_mode(uint8_t rhport, tusb_feature_test_mode_t test_selector) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  // Enable the test mode
+  dwc2->dctl = (dwc2->dctl & ~DCTL_TCTL_Msk) | (((uint8_t) test_selector) << DCTL_TCTL_Pos);
+}
+#endif
+
 #endif
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index 732d96ae0..e5824606a 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -39,7 +39,7 @@
 
 static const dwc2_controller_t _dwc2_controller[] =
 {
-  { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 4096 }
+  { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 16384 }
 };
 
 #define dcache_clean(_addr, _size)              data_clean(_addr, _size)
diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c
new file mode 100644
index 000000000..f80ae9acb
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_common.c
@@ -0,0 +1,311 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#define DWC2_COMMON_DEBUG   2
+
+#if defined(TUP_USBIP_DWC2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED)
+
+#if CFG_TUD_ENABLED
+#include "device/dcd.h"
+#endif
+
+#if CFG_TUH_ENABLED
+#include "host/hcd.h"
+#endif
+
+#include "dwc2_common.h"
+
+//--------------------------------------------------------------------
+//
+//--------------------------------------------------------------------
+static void reset_core(dwc2_regs_t* dwc2) {
+  // reset core
+  dwc2->grstctl |= GRSTCTL_CSRST;
+
+  if ((dwc2->gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
+    // prior v42.0 CSRST is self-clearing
+    while (dwc2->grstctl & GRSTCTL_CSRST) {}
+  } else {
+    // From v4.20a CSRST bit is write only, CSRT_DONE (w1c) is introduced for checking.
+    // CSRST must also be explicitly cleared
+    while (!(dwc2->grstctl & GRSTCTL_CSRST_DONE)) {}
+    dwc2->grstctl =  (dwc2->grstctl & ~GRSTCTL_CSRST) | GRSTCTL_CSRST_DONE;
+  }
+
+  while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for AHB master IDLE
+}
+
+static void phy_fs_init(dwc2_regs_t* dwc2) {
+  TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n");
+
+  uint32_t gusbcfg = dwc2->gusbcfg;
+
+  // Select FS PHY
+  gusbcfg |= GUSBCFG_PHYSEL;
+  dwc2->gusbcfg = gusbcfg;
+
+  // MCU specific PHY init before reset
+  dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
+
+  // Reset core after selecting PHY
+  reset_core(dwc2);
+
+  // USB turnaround time is critical for certification where long cables and 5-Hubs are used.
+  // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
+  // these bits can be programmed to a larger value. Default is 5
+  gusbcfg &= ~GUSBCFG_TRDT_Msk;
+  gusbcfg |= 5u << GUSBCFG_TRDT_Pos;
+  dwc2->gusbcfg = gusbcfg;
+
+  // MCU specific PHY update post reset
+  dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
+}
+
+static void phy_hs_init(dwc2_regs_t* dwc2) {
+  uint32_t gusbcfg = dwc2->gusbcfg;
+
+  // De-select FS PHY
+  gusbcfg &= ~GUSBCFG_PHYSEL;
+
+  if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
+    TU_LOG(DWC2_COMMON_DEBUG, "Highspeed ULPI PHY init\r\n");
+
+    // Select ULPI PHY (external)
+    gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
+
+    // ULPI is always 8-bit interface
+    gusbcfg &= ~GUSBCFG_PHYIF16;
+
+    // ULPI select single data rate
+    gusbcfg &= ~GUSBCFG_DDRSEL;
+
+    // default internal VBUS Indicator and Drive
+    gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
+
+    // Disable FS/LS ULPI
+    gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
+  } else {
+    TU_LOG(DWC2_COMMON_DEBUG, "Highspeed UTMI+ PHY init\r\n");
+
+    // Select UTMI+ PHY (internal)
+    gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
+
+    // Set 16-bit interface if supported
+    if (dwc2->ghwcfg4_bm.phy_data_width) {
+      gusbcfg |= GUSBCFG_PHYIF16; // 16 bit
+    } else {
+      gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
+    }
+  }
+
+  // Apply config
+  dwc2->gusbcfg = gusbcfg;
+
+  // mcu specific phy init
+  dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
+
+  // Reset core after selecting PHY
+  reset_core(dwc2);
+
+  // Set turn-around, must after core reset otherwise it will be clear
+  // - 9 if using 8-bit PHY interface
+  // - 5 if using 16-bit PHY interface
+  gusbcfg &= ~GUSBCFG_TRDT_Msk;
+  gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
+  dwc2->gusbcfg = gusbcfg;
+
+  // MCU specific PHY update post reset
+  dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
+}
+
+static bool check_dwc2(dwc2_regs_t* dwc2) {
+#if CFG_TUSB_DEBUG >= DWC2_COMMON_DEBUG
+  // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
+  // Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports
+  volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
+  TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
+  for (size_t i = 0; i < 5; i++) {
+    TU_LOG1("0x%08" PRIX32 ", ", p[i]);
+  }
+  TU_LOG1("0x%08" PRIX32 "\r\n", p[5]);
+#endif
+
+  // For some reason: GD32VF103 gsnpsid and all hwcfg register are always zero (skip it)
+  (void)dwc2;
+#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
+  enum { GSNPSID_ID_MASK = TU_GENMASK(31, 16) };
+  const uint32_t gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
+  TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
+#endif
+
+  return true;
+}
+
+//--------------------------------------------------------------------
+//
+//--------------------------------------------------------------------
+bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) {
+  (void)dwc2;
+
+#if CFG_TUD_ENABLED
+  if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) {
+    return false;
+  }
+#endif
+#if CFG_TUH_ENABLED
+  if (role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) {
+    return false;
+  }
+#endif
+
+  return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
+}
+
+/* dwc2 has several PHYs option
+ * - UTMI+ is internal highspeed PHY, clock can be 30 Mhz (8-bit) or 60 Mhz (16-bit)
+ * - ULPI is external highspeed PHY, clock is 60Mhz with only 8-bit interface
+ * - Dedicated FS PHY is internal with clock 48Mhz.
+ *
+ * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz
+ *
+*/
+bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  // Check Synopsys ID register, failed if controller clock/power is not enabled
+  TU_ASSERT(check_dwc2(dwc2));
+
+  // disable global interrupt
+  dwc2->gahbcfg &= ~GAHBCFG_GINT;
+
+  if (is_highspeed) {
+    phy_hs_init(dwc2);
+  } else {
+    phy_fs_init(dwc2);
+  }
+
+  /* Set HS/FS Timeout Calibration to 7 (max available value).
+   * The number of PHY clocks that the application programs in
+   * this field is added to the high/full speed interpacket timeout
+   * duration in the core to account for any additional delays
+   * introduced by the PHY. This can be required, because the delay
+   * introduced by the PHY in generating the linestate condition
+   * can vary from one PHY to another. */
+  dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
+
+  // Enable PHY clock TODO stop/gate clock when suspended mode
+  dwc2->pcgcctl &= ~(PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK | PCGCCTL_PWRCLMP | PCGCCTL_RSTPDWNMODULE);
+
+  dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+  dfifo_flush_rx(dwc2);
+
+  // Clear pending and disable all interrupts
+  dwc2->gintsts = 0xFFFFFFFFU;
+  dwc2->gotgint = 0xFFFFFFFFU;
+  dwc2->gintmsk = 0;
+
+  TU_LOG(DWC2_COMMON_DEBUG, "DMA = %u\r\n", is_dma);
+
+  if (is_dma) {
+    // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly
+    dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2;
+  } else {
+    dwc2->gintmsk |= GINTSTS_RXFLVL;
+  }
+
+  return true;
+}
+
+// void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr) {
+//   (void) in_isr;
+//   dwc2_regs_t * const dwc2 = DWC2_REG(rhport);
+//   const uint32_t int_mask = dwc2->gintmsk;
+//   const uint32_t int_status = dwc2->gintsts & int_mask;
+//
+//   // Device disconnect
+//   if (int_status & GINTSTS_DISCINT) {
+//     dwc2->gintsts = GINTSTS_DISCINT;
+//   }
+//
+// }
+
+//--------------------------------------------------------------------
+// DFIFO
+//--------------------------------------------------------------------
+// Read a single data packet from receive DFIFO
+void dfifo_read_packet(dwc2_regs_t* dwc2, uint8_t* dst, uint16_t len) {
+  const volatile uint32_t* rx_fifo = dwc2->fifo[0];
+
+  // Reading full available 32 bit words from fifo
+  uint16_t word_count = len >> 2;
+  while (word_count--) {
+    tu_unaligned_write32(dst, *rx_fifo);
+    dst += 4;
+  }
+
+  // Read the remaining 1-3 bytes from fifo
+  const uint8_t bytes_rem = len & 0x03;
+  if (bytes_rem != 0) {
+    const uint32_t tmp = *rx_fifo;
+    dst[0] = tu_u32_byte0(tmp);
+    if (bytes_rem > 1) {
+      dst[1] = tu_u32_byte1(tmp);
+    }
+    if (bytes_rem > 2) {
+      dst[2] = tu_u32_byte2(tmp);
+    }
+  }
+}
+
+// Write a single data packet to DFIFO
+void dfifo_write_packet(dwc2_regs_t* dwc2, uint8_t fifo_num, const uint8_t* src, uint16_t len) {
+  volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
+
+  // Pushing full available 32 bit words to fifo
+  uint16_t word_count = len >> 2;
+  while (word_count--) {
+    *tx_fifo = tu_unaligned_read32(src);
+    src += 4;
+  }
+
+  // Write the remaining 1-3 bytes into fifo
+  const uint8_t bytes_rem = len & 0x03;
+  if (bytes_rem) {
+    uint32_t tmp_word = src[0];
+    if (bytes_rem > 1) {
+      tmp_word |= (src[1] << 8);
+    }
+    if (bytes_rem > 2) {
+      tmp_word |= (src[2] << 16);
+    }
+
+    *tx_fifo = tmp_word;
+  }
+}
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h
new file mode 100644
index 000000000..18b93894f
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_common.h
@@ -0,0 +1,101 @@
+/*
+* The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_DWC2_COMMON_H
+#define TUSB_DWC2_COMMON_H
+
+#include "common/tusb_common.h"
+#include "dwc2_type.h"
+
+// Following symbols must be defined by port header
+// - _dwc2_controller[]: array of controllers
+// - DWC2_EP_MAX: largest EP counts of all controllers
+// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
+// - dwc2_dcd_int_enable/dwc2_dcd_int_disable
+// - dwc2_remote_wakeup_delay
+
+#if defined(TUP_USBIP_DWC2_STM32)
+  #include "dwc2_stm32.h"
+#elif defined(TUP_USBIP_DWC2_ESP32)
+  #include "dwc2_esp32.h"
+#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
+  #include "dwc2_gd32.h"
+#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
+  #include "dwc2_bcm.h"
+#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
+  #include "dwc2_efm32.h"
+#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
+  #include "dwc2_xmc.h"
+#else
+  #error "Unsupported MCUs"
+#endif
+
+enum {
+  DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
+};
+
+enum {
+  OTG_INT_COMMON = 0 // GINTSTS_DISCINT | GINTSTS_CONIDSTSCHNG
+};
+
+//--------------------------------------------------------------------+
+// Core/Controller
+//--------------------------------------------------------------------+
+TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
+  if (rhport >= DWC2_CONTROLLER_COUNT) {
+    // user mis-configured, ignore and use first controller
+    rhport = 0;
+  }
+  return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base;
+}
+
+bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role);
+bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma);
+void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr);
+
+//--------------------------------------------------------------------+
+// DFIFO
+//--------------------------------------------------------------------+
+TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t fnum) {
+  // flush TX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_TXFFLSH | (fnum << GRSTCTL_TXFNUM_Pos);
+  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) {
+  // flush RX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_RXFFLSH;
+  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+}
+
+void dfifo_read_packet(dwc2_regs_t* dwc2, uint8_t* dst, uint16_t len);
+void dfifo_write_packet(dwc2_regs_t* dwc2, uint8_t fifo_num, uint8_t const* src, uint16_t len);
+
+//--------------------------------------------------------------------+
+// DMA
+//--------------------------------------------------------------------+
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index c50dd66b8..3309760ff 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -25,72 +25,134 @@
  */
 
 
-#ifndef _DWC2_ESP32_H_
-#define _DWC2_ESP32_H_
+#ifndef TUSB_DWC2_ESP32_H_
+#define TUSB_DWC2_ESP32_H_
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+
 #include "esp_intr_alloc.h"
 #include "soc/periph_defs.h"
-//#include "soc/usb_periph.h"
+#include "soc/usb_wrap_struct.h"
 
-#define DWC2_REG_BASE       0x60080000UL
-#define DWC2_EP_MAX         6             // USB_OUT_EP_NUM. TODO ESP32Sx only has 5 tx fifo (5 endpoint IN)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#define DWC2_FS_REG_BASE   0x60080000UL
+#define DWC2_EP_MAX        7
 
-static const dwc2_controller_t _dwc2_controller[] =
-{
-  { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1024 }
+static const dwc2_controller_t _dwc2_controller[] = {
+  { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }
 };
 
-static intr_handle_t usb_ih;
+#elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
+#define DWC2_FS_REG_BASE   0x50040000UL
+#define DWC2_HS_REG_BASE   0x50000000UL
+#define DWC2_EP_MAX        16
 
-static void dcd_int_handler_wrap(void* arg)
-{
-  (void) arg;
-  dcd_int_handler(0);
+// On ESP32 for consistency we associate
+// - Port0 to OTG_FS, and Port1 to OTG_HS
+static const dwc2_controller_t _dwc2_controller[] = {
+{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
+{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
+};
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+static intr_handle_t usb_ih[TU_ARRAY_SIZE(_dwc2_controller)];
+
+static void dwc2_int_handler_wrap(void* arg) {
+  const uint8_t rhport = tu_u16_low((uint16_t)(uintptr_t)arg);
+  const tusb_role_t role = (tusb_role_t) tu_u16_high((uint16_t)(uintptr_t)arg);
+#if CFG_TUD_ENABLED
+  if (role == TUSB_ROLE_DEVICE) {
+    dcd_int_handler(rhport);
+  }
+#endif
+#if CFG_TUH_ENABLED && !CFG_TUH_MAX3421
+  if (role == TUSB_ROLE_HOST) {
+    hcd_int_handler(rhport, true);
+  }
+#endif
 }
 
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_enable (uint8_t rhport)
-{
-  (void) rhport;
-  esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih);
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
+  if (enabled) {
+    esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED,
+                   dwc2_int_handler_wrap, (void*)(uintptr_t)tu_u16(role, rhport), &usb_ih[rhport]);
+  } else {
+    esp_intr_free(usb_ih[rhport]);
+  }
 }
 
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_disable (uint8_t rhport)
-{
-  (void) rhport;
-  esp_intr_free(usb_ih);
-}
+#define dwc2_dcd_int_enable(_rhport)  dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, true)
+#define dwc2_dcd_int_disable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, false)
 
-static inline void dwc2_remote_wakeup_delay(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
   vTaskDelay(pdMS_TO_TICKS(1));
 }
 
 // MCU specific PHY init, called BEFORE core reset
-static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
-{
-  (void) dwc2;
-  (void) hs_phy_type;
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  (void)dwc2;
+  (void)hs_phy_type;
+  // maybe usb_utmi_hal_init()
 
-  // nothing to do
 }
 
 // MCU specific PHY update, it is called AFTER init() and core reset
-static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
-{
-  (void) dwc2;
-  (void) hs_phy_type;
-
-  // nothing to do
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  (void)dwc2;
+  (void)hs_phy_type;
+  // maybe usb_utmi_hal_disable()
 }
 
+//--------------------------------------------------------------------+
+// Data Cache
+//--------------------------------------------------------------------+
+#if CFG_TUD_DWC2_DMA_ENABLE || CFG_TUH_DWC2_DMA_ENABLE
+#if defined(SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+#include "esp_cache.h"
+
+#if CFG_TUD_MEM_DCACHE_LINE_SIZE != CONFIG_CACHE_L1_CACHE_LINE_SIZE || \
+    CFG_TUH_MEM_DCACHE_LINE_SIZE != CONFIG_CACHE_L1_CACHE_LINE_SIZE
+#error "CFG_TUD/TUH_MEM_DCACHE_LINE_SIZE must match CONFIG_CACHE_L1_CACHE_LINE_SIZE"
+#endif
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
+  if (size & (CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) {
+    size = (size & ~(CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) + CONFIG_CACHE_L1_CACHE_LINE_SIZE;
+  }
+  return size;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(const void* addr, uint32_t data_size) {
+  const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M;
+  data_size = round_up_to_cache_line_size(data_size);
+  return ESP_OK == esp_cache_msync((void*)addr, data_size, flag);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(const void* addr, uint32_t data_size) {
+  const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
+  data_size = round_up_to_cache_line_size(data_size);
+  return ESP_OK == esp_cache_msync((void*)addr, data_size, flag);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
+  const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
+  data_size = round_up_to_cache_line_size(data_size);
+  return ESP_OK == esp_cache_msync((void*)addr, data_size, flag);
+}
+
+#endif
+#endif
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* _DWC2_ESP32_H_ */
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md
new file mode 100644
index 000000000..dec021f59
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_info.md
@@ -0,0 +1,58 @@
+|                            | BCM2711 (Pi4)   | EFM32GG      | ESP32-S2/S3   | ESP32-P4     | ST F207/F407/411/429 FS   | ST F407/429 HS   | ST F412/76x FS   | ST F723/L4P5 FS   | ST F723 HS   | ST F76x HS   | ST H743/H750   | ST L476 FS   | ST U5A5 HS   | XMC4500      | GD32VF103   |
+|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:-------------|:------------|
+| GUID                       | 0x2708A000      | 0x00000000   | 0x00000000    | 0x00000000   | 0x00001200                | 0x00001100       | 0x00002000       | 0x00003000        | 0x00003100   | 0x00002100   | 0x00002300     | 0x00002000   | 0x00005000   | 0x00AEC000   | 0x00001000  |
+| GSNPSID                    | 0x4F54280A      | 0x4F54330A   | 0x4F54400A    | 0x4F54400A   | 0x4F54281A                | 0x4F54281A       | 0x4F54320A       | 0x4F54330A        | 0x4F54330A   | 0x4F54320A   | 0x4F54330A     | 0x4F54310A   | 0x4F54411A   | 0x4F54292A   | 0x00000000  |
+| - specs version            | 2.80a           | 3.30a        | 4.00a         | 4.00a        | 2.81a                     | 2.81a            | 3.20a            | 3.30a             | 3.30a        | 3.20a        | 3.30a          | 3.10a        | 4.11a        | 2.92a        | 0.00W       |
+| GHWCFG1                    | 0x00000000      | 0x00000000   | 0x00000000    | 0x00000000   | 0x00000000                | 0x00000000       | 0x00000000       | 0x00000000        | 0x00000000   | 0x00000000   | 0x00000000     | 0x00000000   | 0x00000000   | 0x00000000   | 0x00000000  |
+| GHWCFG2                    | 0x228DDD50      | 0x228F5910   | 0x224DD930    | 0x215FFFD0   | 0x229DCD20                | 0x229ED590       | 0x229ED520       | 0x229ED520        | 0x229FE1D0   | 0x229FE190   | 0x229FE190     | 0x229ED520   | 0x228FE052   | 0x228F5930   | 0x00000000  |
+| - op_mode                  | HNP SRP         | HNP SRP      | HNP SRP       | HNP SRP      | HNP SRP                   | HNP SRP          | HNP SRP          | HNP SRP           | HNP SRP      | HNP SRP      | HNP SRP        | HNP SRP      | noHNP noSRP  | HNP SRP      | HNP SRP     |
+| - arch                     | DMA internal    | DMA internal | DMA internal  | DMA internal | Slave only                | DMA internal     | Slave only       | Slave only        | DMA internal | DMA internal | DMA internal   | Slave only   | DMA internal | DMA internal | Slave only  |
+| - single_point             | hub             | hub          | n/a           | hub          | n/a                       | hub              | n/a              | n/a               | hub          | hub          | hub            | n/a          | hub          | n/a          | hub         |
+| - hs_phy_type              | UTMI+           | n/a          | n/a           | UTMI+/ULPI   | n/a                       | ULPI             | n/a              | n/a               | UTMI+/ULPI   | ULPI         | ULPI           | n/a          | UTMI+        | n/a          | n/a         |
+| - fs_phy_type              | Dedicated       | Dedicated    | Dedicated     | Shared ULPI  | Dedicated                 | Dedicated        | Dedicated        | Dedicated         | Dedicated    | Dedicated    | Dedicated      | Dedicated    | n/a          | Dedicated    | n/a         |
+| - num_dev_ep               | 7               | 6            | 6             | 15           | 3                         | 5                | 5                | 5                 | 8            | 8            | 8              | 5            | 8            | 6            | 0           |
+| - num_host_ch              | 7               | 13           | 7             | 15           | 7                         | 11               | 11               | 11                | 15           | 15           | 15             | 11           | 15           | 13           | 0           |
+| - period_channel_support   | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1            | 1            | 0           |
+| - enable_dynamic_fifo      | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1            | 1            | 0           |
+| - mul_proc_intrpt          | 0               | 0            | 0             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0            | 0            | 0           |
+| - reserved21               | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| - nptx_q_depth             | 8               | 8            | 4             | 4            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8            | 8            | 2           |
+| - ptx_q_depth              | 8               | 8            | 8             | 4            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8            | 8            | 2           |
+| - token_q_depth            | 8               | 8            | 8             | 8            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8            | 8            | 0           |
+| - otg_enable_ic_usb        | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| GHWCFG3                    | 0x0FF000E8      | 0x01F204E8   | 0x00C804B5    | 0x03805EB5   | 0x020001E8                | 0x03F403E8       | 0x0200D1E8       | 0x0200D1E8        | 0x03EED2E8   | 0x03EED2E8   | 0x03B8D2E8     | 0x0200D1E8   | 0x03B882E8   | 0x027A01E5   | 0x00000000  |
+| - xfer_size_width          | 8               | 8            | 5             | 5            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8            | 5            | 0           |
+| - packet_size_width        | 6               | 6            | 3             | 3            | 6                         | 6                | 6                | 6                 | 6            | 6            | 6              | 6            | 6            | 6            | 0           |
+| - otg_enable               | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1            | 1            | 0           |
+| - i2c_enable               | 0               | 0            | 0             | 0            | 1                         | 1                | 1                | 1                 | 0            | 0            | 0              | 1            | 0            | 1            | 0           |
+| - vendor_ctrl_itf          | 0               | 0            | 0             | 1            | 0                         | 1                | 0                | 0                 | 1            | 1            | 1              | 0            | 1            | 0            | 0           |
+| - optional_feature_removed | 0               | 1            | 1             | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| - synch_reset              | 0               | 0            | 0             | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| - otg_adp_support          | 0               | 0            | 0             | 1            | 0                         | 0                | 1                | 1                 | 1            | 1            | 1              | 1            | 0            | 0            | 0           |
+| - otg_enable_hsic          | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| - battery_charger_support  | 0               | 0            | 0             | 1            | 0                         | 0                | 1                | 1                 | 1            | 1            | 1              | 1            | 0            | 0            | 0           |
+| - lpm_mode                 | 0               | 0            | 0             | 0            | 0                         | 0                | 1                | 1                 | 1            | 1            | 1              | 1            | 1            | 0            | 0           |
+| - dfifo_depth              | 4080            | 498          | 200           | 896          | 512                       | 1012             | 512              | 512               | 1006         | 1006         | 952            | 512          | 952          | 634          | 0           |
+| GHWCFG4                    | 0x1FF00020      | 0x1BF08030   | 0xD3F0A030    | 0xDFF1A030   | 0x0FF08030                | 0x17F00030       | 0x17F08030       | 0x17F08030        | 0x23F00030   | 0x23F00030   | 0xE3F00030     | 0x17F08030   | 0xE2103E30   | 0xDBF08030   | 0x00000000  |
+| - num_dev_period_in_ep     | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| - partial_powerdown        | 0               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1            | 1            | 0           |
+| - ahb_freq_min             | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1            | 1            | 0           |
+| - hibernation              | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| - extended_hibernation     | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| - reserved8                | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| - enhanced_lpm_support1    | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1            | 0            | 0           |
+| - service_interval_flow    | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1            | 0            | 0           |
+| - ipg_isoc_support         | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1            | 0            | 0           |
+| - acg_support              | 0               | 0            | 0             | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1            | 0            | 0           |
+| - enhanced_lpm_support     | 0               | 0            | 1             | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1            | 0            | 0           |
+| - phy_data_width           | 8 bit           | 8/16 bit     | 8/16 bit      | 8/16 bit     | 8/16 bit                  | 8 bit            | 8/16 bit         | 8/16 bit          | 8 bit        | 8 bit        | 8 bit          | 8/16 bit     | 8 bit        | 8/16 bit     | 8 bit       |
+| - ctrl_ep_num              | 0               | 0            | 0             | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0            | 0            | 0           |
+| - iddg_filter              | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1            | 1            | 0           |
+| - vbus_valid_filter        | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0            | 1            | 0           |
+| - a_valid_filter           | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0            | 1            | 0           |
+| - b_valid_filter           | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0            | 1            | 0           |
+| - session_end_filter       | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0            | 1            | 0           |
+| - dedicated_fifos          | 1               | 1            | 1             | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1            | 1            | 0           |
+| - num_dev_in_eps           | 7               | 6            | 4             | 7            | 3                         | 5                | 5                | 5                 | 8            | 8            | 8              | 5            | 8            | 6            | 0           |
+| - dma_desc_enable          | 0               | 0            | 1             | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 1              | 0            | 1            | 1            | 0           |
+| - dma_desc_dynamic         | 0               | 0            | 1             | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 1              | 0            | 1            | 1            | 0           |
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
new file mode 100755
index 000000000..25edcf22d
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -0,0 +1,210 @@
+#!/usr/bin/env python3
+
+import ctypes
+import argparse
+import click
+import pandas as pd
+
+# hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
+# Note: FS is FullSpeed, HS is HighSpeed
+dwc2_reg_list = ['GUID', 'GSNPSID', 'GHWCFG1', 'GHWCFG2', 'GHWCFG3', 'GHWCFG4']
+dwc2_reg_value = {
+    'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020],
+    'EFM32GG': [0, 0x4F54330A, 0, 0x228F5910, 0x01F204E8, 0x1BF08030],
+    'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030],
+    'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030],
+    'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
+    'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030],
+    'ST F412/76x FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+    'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+    'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
+    'ST F76x HS': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030],
+    'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030],
+    'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+    'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
+    'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030],
+    'GD32VF103': [0x1000, 0, 0, 0, 0, 0],
+}
+
+# Combine dwc2_info with dwc2_reg_list
+# dwc2_info = {
+#     'BCM2711 (Pi4)': {
+#         'GUID': 0x2708A000,
+#         'GSNPSID': 0x4F54280A,
+#         'GHWCFG1': 0,
+#         'GHWCFG2': 0x228DDD50,
+#         'GHWCFG3': 0xFF000E8,
+#         'GHWCFG4': 0x1FF00020
+#     },
+dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()}
+
+
+class GHWCFG2(ctypes.LittleEndianStructure):
+    _fields_ = [
+        ("op_mode", ctypes.c_uint32, 3),
+        ("arch", ctypes.c_uint32, 2),
+        ("single_point", ctypes.c_uint32, 1),
+        ("hs_phy_type", ctypes.c_uint32, 2),
+        ("fs_phy_type", ctypes.c_uint32, 2),
+        ("num_dev_ep", ctypes.c_uint32, 4),
+        ("num_host_ch", ctypes.c_uint32, 4),
+        ("period_channel_support", ctypes.c_uint32, 1),
+        ("enable_dynamic_fifo", ctypes.c_uint32, 1),
+        ("mul_proc_intrpt", ctypes.c_uint32, 1),
+        ("reserved21", ctypes.c_uint32, 1),
+        ("nptx_q_depth", ctypes.c_uint32, 2),
+        ("ptx_q_depth", ctypes.c_uint32, 2),
+        ("token_q_depth", ctypes.c_uint32, 5),
+        ("otg_enable_ic_usb", ctypes.c_uint32, 1)
+    ]
+
+
+class GHWCFG3(ctypes.LittleEndianStructure):
+    _fields_ = [
+        ("xfer_size_width", ctypes.c_uint32, 4),
+        ("packet_size_width", ctypes.c_uint32, 3),
+        ("otg_enable", ctypes.c_uint32, 1),
+        ("i2c_enable", ctypes.c_uint32, 1),
+        ("vendor_ctrl_itf", ctypes.c_uint32, 1),
+        ("optional_feature_removed", ctypes.c_uint32, 1),
+        ("synch_reset", ctypes.c_uint32, 1),
+        ("otg_adp_support", ctypes.c_uint32, 1),
+        ("otg_enable_hsic", ctypes.c_uint32, 1),
+        ("battery_charger_support", ctypes.c_uint32, 1),
+        ("lpm_mode", ctypes.c_uint32, 1),
+        ("dfifo_depth", ctypes.c_uint32, 16)
+    ]
+
+
+class GHWCFG4(ctypes.LittleEndianStructure):
+    _fields_ = [
+        ("num_dev_period_in_ep", ctypes.c_uint32, 4),
+        ("partial_powerdown", ctypes.c_uint32, 1),
+        ("ahb_freq_min", ctypes.c_uint32, 1),
+        ("hibernation", ctypes.c_uint32, 1),
+        ("extended_hibernation", ctypes.c_uint32, 1),
+        ("reserved8", ctypes.c_uint32, 1),
+        ("enhanced_lpm_support1", ctypes.c_uint32, 1),
+        ("service_interval_flow", ctypes.c_uint32, 1),
+        ("ipg_isoc_support", ctypes.c_uint32, 1),
+        ("acg_support", ctypes.c_uint32, 1),
+        ("enhanced_lpm_support", ctypes.c_uint32, 1),
+        ("phy_data_width", ctypes.c_uint32, 2),
+        ("ctrl_ep_num", ctypes.c_uint32, 4),
+        ("iddg_filter", ctypes.c_uint32, 1),
+        ("vbus_valid_filter", ctypes.c_uint32, 1),
+        ("a_valid_filter", ctypes.c_uint32, 1),
+        ("b_valid_filter", ctypes.c_uint32, 1),
+        ("session_end_filter", ctypes.c_uint32, 1),
+        ("dedicated_fifos", ctypes.c_uint32, 1),
+        ("num_dev_in_eps", ctypes.c_uint32, 4),
+        ("dma_desc_enable", ctypes.c_uint32, 1),
+        ("dma_desc_dynamic", ctypes.c_uint32, 1)
+    ]
+
+# mapping for specific fields in GHWCFG2
+GHWCFG2_field = {
+    'op_mode': {
+        0: "HNP SRP",
+        1: "SRP",
+        2: "noHNP noSRP",
+        3: "SRP Device",
+        4: "noOTG Device",
+        5: "SRP Host",
+        6: "noOTG Host"
+    },
+    'arch': {
+        0: "Slave only",
+        1: "DMA external",
+        2: "DMA internal"
+    },
+    'single_point': {
+        0: "hub",
+        1: "n/a"
+    },
+    'hs_phy_type': {
+        0: "n/a",
+        1: "UTMI+",
+        2: "ULPI",
+        3: "UTMI+/ULPI"
+    },
+    'fs_phy_type': {
+        0: "n/a",
+        1: "Dedicated",
+        2: "Shared UTMI+",
+        3: "Shared ULPI"
+    },
+    'nptx_q_depth': {
+        0: "2",
+        1: "4",
+        2: "8",
+    },
+    'ptx_q_depth': {
+        0: "2",
+        1: "4",
+        2: "8",
+        3: "16"
+    },
+}
+
+# mapping for specific fields in GHWCFG4
+GHWCFG4_field = {
+    'phy_data_width': {
+        0: "8 bit",
+        1: "16 bit",
+        2: "8/16 bit",
+        3: "Reserved"
+    },
+    }
+
+def main():
+    """Render dwc2_info to Markdown table"""
+
+    parser = argparse.ArgumentParser()
+    args = parser.parse_args()
+
+    # Create an empty list to hold the dictionaries
+    md_table = []
+
+    # Iterate over the dwc2_info dictionary and extract fields
+    for device, reg_values in dwc2_info.items():
+        md_item = {"Device": device}
+        for r_name, r_value in reg_values.items():
+            md_item[r_name] = f"0x{r_value:08X}"
+
+            if r_name == 'GSNPSID':
+                # Get dwc2 specs version
+                major = ((r_value >> 8) >> 4) & 0x0F
+                minor = (r_value >> 4) & 0xFF
+                patch = chr((r_value & 0x0F) + ord('a') - 0xA)
+                md_item[f' - specs version'] = f"{major:X}.{minor:02X}{patch}"
+            elif r_name in globals():
+                # Get bit-field values which exist as ctypes structures
+                class_hdl = globals()[r_name]
+                ghwcfg = class_hdl.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
+                for field_name, field_type, _ in class_hdl._fields_:
+                    field_value = getattr(ghwcfg, field_name)
+                    if class_hdl == GHWCFG2 and field_name in GHWCFG2_field:
+                        field_value = GHWCFG2_field[field_name].get(field_value, f"Unknown ({field_value})")
+                    if class_hdl == GHWCFG4 and field_name in GHWCFG4_field:
+                        field_value = GHWCFG4_field[field_name].get(field_value, f"Unknown ({field_value})")
+
+                    md_item[f' - {field_name}'] = field_value
+
+        md_table.append(md_item)
+
+    # Create a Pandas DataFrame from the list of dictionaries
+    df = pd.DataFrame(md_table).set_index('Device')
+
+    # Transpose the DataFrame to switch rows and columns
+    df = df.T
+    #print(df)
+
+    # Write the Markdown table to a file
+    with open('dwc2_info.md', 'w') as md_file:
+        md_file.write(df.to_markdown())
+        md_file.write('\n')
+
+
+if __name__ == '__main__':
+    main()
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index ea786362e..c11c1eb05 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -24,11 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _DWC2_STM32_H_
-#define _DWC2_STM32_H_
+#ifndef DWC2_STM32_H_
+#define DWC2_STM32_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 // EP_MAX       : Max number of bi-directional endpoints including EP0
@@ -69,6 +69,14 @@
     #define OTG_FS_IRQn             OTG_HS_IRQn
   #endif
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H7RS
+  #include "stm32h7rsxx.h"
+  #define EP_MAX_FS       6
+  #define EP_FIFO_SIZE_FS 1280
+
+  #define EP_MAX_HS       9
+  #define EP_FIFO_SIZE_HS 4096
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
   #include "stm32f7xx.h"
   #define EP_MAX_FS       6
@@ -84,10 +92,16 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
   #include "stm32u5xx.h"
-  #define USB_OTG_FS_PERIPH_BASE       USB_OTG_FS_BASE
-  #define EP_MAX_FS       6
-  #define EP_FIFO_SIZE_FS 1280
-
+  // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
+  #ifdef USB_OTG_FS
+    #define USB_OTG_FS_PERIPH_BASE    USB_OTG_FS_BASE
+    #define EP_MAX_FS                 6
+    #define EP_FIFO_SIZE_FS           1280
+  #else
+    #define USB_OTG_HS_PERIPH_BASE    USB_OTG_HS_BASE
+    #define EP_MAX_HS                 9
+    #define EP_FIFO_SIZE_HS           4096
+  #endif
 #else
   #error "Unsupported MCUs"
 #endif
@@ -101,60 +115,82 @@
 
 // On STM32 for consistency we associate
 // - Port0 to OTG_FS, and Port1 to OTG_HS
-static const dwc2_controller_t _dwc2_controller[] =
-{
-#ifdef USB_OTG_FS_PERIPH_BASE
-  { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
-#endif
+static const dwc2_controller_t _dwc2_controller[] = {
+    #ifdef USB_OTG_FS_PERIPH_BASE
+    { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
+    #endif
 
-#ifdef USB_OTG_HS_PERIPH_BASE
-  { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
-#endif
+    #ifdef USB_OTG_HS_PERIPH_BASE
+    { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
+    #endif
 };
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
-// SystemCoreClock is alrady included by family header
+// SystemCoreClock is already included by family header
 // extern uint32_t SystemCoreClock;
 
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
+  (void) role;
+  const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
+  if (enabled) {
+    NVIC_EnableIRQ(irqn);
+  } else {
+    NVIC_DisableIRQ(irqn);
+  }
 }
 
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_disable (uint8_t rhport)
-{
-  NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
-}
+#define dwc2_dcd_int_enable(_rhport)  dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, true)
+#define dwc2_dcd_int_disable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, false)
 
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_remote_wakeup_delay(void)
-{
+
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
   // try to delay for 1 ms
   uint32_t count = SystemCoreClock / 1000;
-  while ( count-- ) __NOP();
+  while (count--) __NOP();
 }
 
 // MCU specific PHY init, called BEFORE core reset
-static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
-{
-  if ( hs_phy_type == HS_PHY_TYPE_NONE )
-  {
+// - dwc2 3.30a (H5) use USB_HS_PHYC
+// - dwc2 4.11a (U5) use femtoPHY
+static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
     // Enable on-chip FS PHY
     dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
-  }else
-  {
-    // Disable FS PHY
+
+    // https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867
+    // H7 running on full-speed phy need to disable ULPI clock in sleep mode.
+    // Otherwise, USB won't work when mcu executing WFI/WFE instruction i.e tick-less RTOS.
+    // Note: there may be other family that is affected by this, but only H7 and F7 is tested so far
+    #if defined(USB_OTG_FS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB2OTGFSULPILPEN)
+    if ( USB_OTG_FS_PERIPH_BASE == (uint32_t) dwc2 ) {
+      RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB2OTGFSULPILPEN;
+    }
+    #endif
+
+    #if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB1OTGHSULPILPEN)
+    if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) {
+      RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB1OTGHSULPILPEN;
+    }
+    #endif
+
+    #if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_OTGHSULPILPEN)
+    if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) {
+      RCC->AHB1LPENR &= ~RCC_AHB1LPENR_OTGHSULPILPEN;
+    }
+    #endif
+
+  } else {
+#if CFG_TUSB_MCU != OPT_MCU_STM32U5
+    // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
     dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+#endif
 
     // Enable on-chip HS PHY
-    if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI)
-    {
-#ifdef USB_HS_PHYC
+    if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
+      #ifdef USB_HS_PHYC
       // Enable UTMI HS PHY
       dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
 
@@ -186,40 +222,47 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 
       // Enable PLL internal PHY
       USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
-#endif
+      #else
+
+      #endif
     }
   }
 }
 
 // MCU specific PHY update, it is called AFTER init() and core reset
-static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
-{
+static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   // used to set turnaround time for fullspeed, nothing to do in highspeed mode
-  if ( hs_phy_type == HS_PHY_TYPE_NONE )
-  {
+  if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
     // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
     uint32_t turnaround;
 
-    if ( SystemCoreClock >= 32000000u )
+    if (SystemCoreClock >= 32000000u) {
       turnaround = 0x6u;
-    else if ( SystemCoreClock >= 27500000u )
+    } else if (SystemCoreClock >= 27500000u) {
       turnaround = 0x7u;
-    else if ( SystemCoreClock >= 24000000u )
+    } else if (SystemCoreClock >= 24000000u) {
       turnaround = 0x8u;
-    else if ( SystemCoreClock >= 21800000u )
+    } else if (SystemCoreClock >= 21800000u) {
       turnaround = 0x9u;
-    else if ( SystemCoreClock >= 20000000u )
+    }
+    else if (SystemCoreClock >= 20000000u) {
       turnaround = 0xAu;
-    else if ( SystemCoreClock >= 18500000u )
+    }
+    else if (SystemCoreClock >= 18500000u) {
       turnaround = 0xBu;
-    else if ( SystemCoreClock >= 17200000u )
+    }
+    else if (SystemCoreClock >= 17200000u) {
       turnaround = 0xCu;
-    else if ( SystemCoreClock >= 16000000u )
+    }
+    else if (SystemCoreClock >= 16000000u) {
       turnaround = 0xDu;
-    else if ( SystemCoreClock >= 15000000u )
+    }
+    else if (SystemCoreClock >= 15000000u) {
       turnaround = 0xEu;
-    else
+    }
+    else {
       turnaround = 0xFu;
+    }
 
     dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos);
   }
@@ -229,4 +272,4 @@ static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 }
 #endif
 
-#endif /* _DWC2_STM32_H_ */
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 3fc979337..812096759 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -1,21 +1,38 @@
-/**
-  * @author  MCD Application Team
-  *          Ha Thach (tinyusb.org)
-  *
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+/** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
   *                        opensource.org/licenses/BSD-3-Clause
-  *
   */
 
-#ifndef _TUSB_DWC2_TYPES_H_
-#define _TUSB_DWC2_TYPES_H_
+#ifndef TUSB_DWC2_TYPES_H_
+#define TUSB_DWC2_TYPES_H_
 
 #include "stdint.h"
 
@@ -29,10 +46,11 @@ typedef struct
   uintptr_t reg_base;
   uint32_t  irqnum;
   uint8_t   ep_count;
+  uint8_t   ep_in_count;
   uint32_t  ep_fifo_size;
 }dwc2_controller_t;
 
-/* DWC OTG HW Release versions */
+// DWC OTG HW Release versions
 #define DWC2_CORE_REV_2_71a   0x4f54271a
 #define DWC2_CORE_REV_2_72a   0x4f54272a
 #define DWC2_CORE_REV_2_80a   0x4f54280a
@@ -43,12 +61,13 @@ typedef struct
 #define DWC2_CORE_REV_3_00a   0x4f54300a
 #define DWC2_CORE_REV_3_10a   0x4f54310a
 #define DWC2_CORE_REV_4_00a   0x4f54400a
+#define DWC2_CORE_REV_4_11a   0x4f54411a
 #define DWC2_CORE_REV_4_20a   0x4f54420a
 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
 #define DWC2_CORE_REV_MASK    0x0000ffff
 
-/* DWC OTG HW Core ID */
+// DWC OTG HW Core ID
 #define DWC2_OTG_ID           0x4f540000
 #define DWC2_FS_IOT_ID        0x55310000
 #define DWC2_HS_IOT_ID        0x55320000
@@ -57,231 +76,717 @@ typedef struct
 // HS PHY
 typedef struct
 {
-  volatile uint32_t HS_PHYC_PLL;         // This register is used to control the PLL of the HS PHY.                       000h */
-  volatile uint32_t Reserved04;          // Reserved                                                                      004h */
-  volatile uint32_t Reserved08;          // Reserved                                                                      008h */
-  volatile uint32_t HS_PHYC_TUNE;        // This register is used to control the tuning interface of the High Speed PHY.  00Ch */
-  volatile uint32_t Reserved10;          // Reserved                                                                      010h */
-  volatile uint32_t Reserved14;          // Reserved                                                                      014h */
-  volatile uint32_t HS_PHYC_LDO;         // This register is used to control the regulator (LDO).                         018h */
+  volatile uint32_t HS_PHYC_PLL;         // 000h This register is used to control the PLL of the HS PHY.
+  volatile uint32_t Reserved04;          // 004h Reserved
+  volatile uint32_t Reserved08;          // 008h Reserved
+  volatile uint32_t HS_PHYC_TUNE;        // 00Ch This register is used to control the tuning interface of the High Speed PHY.
+  volatile uint32_t Reserved10;          // 010h Reserved
+  volatile uint32_t Reserved14;          // 014h Reserved
+  volatile uint32_t HS_PHYC_LDO;         // 018h This register is used to control the regulator (LDO).
 } HS_PHYC_GlobalTypeDef;
 #endif
 
 enum {
-  HS_PHY_TYPE_NONE = 0  , // not supported
-  HS_PHY_TYPE_UTMI      , // internal PHY (mostly)
-  HS_PHY_TYPE_ULPI      , // external PHY
-  HS_PHY_TYPE_UTMI_ULPI ,
+  GOTGCTL_OTG_VERSION_1_3 = 0,
+  GOTGCTL_OTG_VERSION_2_0 = 1,
 };
 
 enum {
-  FS_PHY_TYPE_NONE = 0,  // not supported
-  FS_PHY_TYPE_DEDICATED,
-  FS_PHY_TYPE_UTMI,
-  FS_PHY_TYPE_ULPI,
+  GHWCFG2_OPMODE_HNP_SRP         = 0,
+  GHWCFG2_OPMODE_SRP             = 1,
+  GHWCFG2_OPMODE_NON_HNP_NON_SRP = 2,
+  GHWCFG2_OPMODE_SRP_DEVICE      = 3,
+  GHWCFFG2_OPMODE_NON_OTG_DEVICE = 4,
+  GHWCFG2_OPMODE_SRP_HOST        = 5,
+  GHWCFG2_OPMODE_NON_OTG_HOST    = 6,
+};
+enum {
+  GHWCFG2_ARCH_SLAVE_ONLY   = 0,
+  GHWCFG2_ARCH_EXTERNAL_DMA = 1,
+  GHWCFG2_ARCH_INTERNAL_DMA = 2,
 };
 
-typedef struct TU_ATTR_PACKED
-{
-  uint32_t op_mode                  : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
-  uint32_t arch                     : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others
-  uint32_t point2point              : 1; // 0: support hub and split | 1: no hub, no split
-  uint32_t hs_phy_type              : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
-  uint32_t fs_phy_type              : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
-  uint32_t num_dev_ep               : 4; // Number of device endpoints (not including EP0)
-  uint32_t num_host_ch              : 4; // Number of host channel
-  uint32_t period_channel_support   : 1; // Support Periodic OUT Host Channel
-  uint32_t enable_dynamic_fifo      : 1; // Dynamic FIFO Sizing Enabled
-  uint32_t mul_cpu_int              : 1; // Multi-Processor Interrupt Enabled
-  uint32_t reserved21               : 1;
-  uint32_t nperiod_tx_q_depth       : 2; // Non-periodic request queue depth: 0 = 2.  1 = 4, 2 = 8
-  uint32_t host_period_tx_q_depth   : 2; // Host periodic request queue depth: 0 = 2.  1 = 4, 2 = 8
-  uint32_t dev_token_q_depth        : 5; // Device IN token sequence learning queue depth: 0-30
-  uint32_t otg_enable_ic_usb        : 1; // IC_USB mode specified for mode of operation
-} dwc2_ghwcfg2_t;
+enum {
+  GHWCFG2_HSPHY_NOT_SUPPORTED = 0,
+  GHWCFG2_HSPHY_UTMI          = 1, // internal PHY (mostly)
+  GHWCFG2_HSPHY_ULPI          = 2, // external PHY (mostly)
+  GHWCFG2_HSPHY_UTMI_ULPI     = 3, // both
 
+};
+
+enum {
+  GHWCFG2_FSPHY_NOT_SUPPORTED = 0,
+  GHWCFG2_FSPHY_DEDICATED     = 1, // have dedicated FS PHY
+  GHWCFG2_FSPHY_UTMI          = 2, // shared with UTMI+
+  GHWCFG2_FSPHY_ULPI          = 3, // shared with ULPI
+};
+
+enum {
+  GHWCFFG4_PHY_DATA_WIDTH_8    = 0,
+  GHWCFFG4_PHY_DATA_WIDTH_16   = 1,
+  GHWCFFG4_PHY_DATA_WIDTH_8_16 = 2, // software selectable
+};
+
+enum {
+  HPRT_SPEED_HIGH = 0,
+  HPRT_SPEED_FULL = 1,
+  HPRT_SPEED_LOW  = 2
+};
+
+enum {
+  GINTSTS_CMODE_DEVICE = 0,
+  GINTSTS_CMODE_HOST   = 1,
+};
+
+enum {
+  HCTSIZ_PID_DATA0 = 0, // 00b
+  HCTSIZ_PID_DATA2 = 1, // 01b
+  HCTSIZ_PID_DATA1 = 2, // 10b
+  HCTSIZ_PID_SETUP = 3, // 11b
+};
+enum {
+  HCTSIZ_PID_MDATA = 3,
+};
+
+enum {
+  GRXSTS_PKTSTS_GLOBAL_OUT_NAK      = 1,
+  GRXSTS_PKTSTS_RX_DATA             = 2,
+  GRXSTS_PKTSTS_RX_COMPLETE         = 3,
+  GRXSTS_PKTSTS_SETUP_DONE          = 4,
+  GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR = 5,
+  GRXSTS_PKTSTS_SETUP_RX            = 6,
+  GRXSTS_PKTSTS_HOST_CHANNEL_HALTED = 7
+};
+
+// Same as TUSB_XFER_*
+enum {
+  HCCHAR_EPTYPE_CONTROL     = 0,
+  HCCHAR_EPTYPE_ISOCHRONOUS = 1,
+  HCCHAR_EPTYPE_BULK        = 2,
+  HCCHAR_EPTYPE_INTERRUPT   = 3
+};
+
+enum {
+  DCFG_SPEED_HIGH          = 0, // Highspeed with 30/60 Mhz
+  DCFG_SPEED_FULL_30_60MHZ = 1, // Fullspeed with UTMI+/ULPI 30/60 Mhz
+  DCFG_SPEED_LOW           = 2, // Lowspeed with FS PHY at 6 Mhz
+  DCFG_SPEED_FULL_48MHZ    = 3, // Fullspeed with dedicated FS PHY at 48 Mhz
+};
+
+// Same as TUSB_XFER_*
+enum {
+  DEPCTL_EPTYPE_CONTROL     = 0,
+  DEPCTL_EPTYPE_ISOCHRONOUS = 1,
+  DEPCTL_EPTYPE_BULK        = 2,
+  DEPCTL_EPTYPE_INTERRUPT   = 3
+};
+
+//--------------------------------------------------------------------
+// Common Register Bitfield
+//--------------------------------------------------------------------
+typedef struct TU_ATTR_PACKED {
+  uint32_t ses_req_scs           : 1; //  0 Session request success
+  uint32_t ses_req               : 1; //  1 Session request
+  uint32_t vbval_ov_en           : 1; //  2 VBUS valid override enable
+  uint32_t vbval_ov_val          : 1; //  3 VBUS valid override value
+  uint32_t aval_ov_en            : 1; //  4 A-peripheral session valid override enable
+  uint32_t aval_ov_al            : 1; //  5 A-peripheral session valid override value
+  uint32_t bval_ov_en            : 1; //  6 B-peripheral session valid override enable
+  uint32_t bval_ov_val           : 1; //  7 B-peripheral session valid override value
+  uint32_t hng_scs               : 1; //  8 Host negotiation success
+  uint32_t hnp_rq                : 1; //  9 HNP (host negotiation protocol) request
+  uint32_t host_set_hnp_en       : 1; // 10 Host set HNP enable
+  uint32_t dev_hnp_en            : 1; // 11 Device HNP enabled
+  uint32_t embedded_host_en      : 1; // 12 Embedded host enable
+  uint32_t rsv13_14              : 2; // 13.14 Reserved
+  uint32_t dbnc_filter_bypass    : 1; // 15 Debounce filter bypass
+  uint32_t cid_status            : 1; // 16 Connector ID status
+  uint32_t dbnc_done             : 1; // 17 Debounce done
+  uint32_t ases_valid            : 1; // 18 A-session valid
+  uint32_t bses_valid            : 1; // 19 B-session valid
+  uint32_t otg_ver               : 1; // 20 OTG version 0: v1.3, 1: v2.0
+  uint32_t current_mode          : 1; // 21 Current mode of operation. Only from v3.00a
+  uint32_t mult_val_id_bc        : 5; // 22..26 Multi-valued input pin ID battery charger
+  uint32_t chirp_en              : 1; // 27 Chirp detection enable
+  uint32_t rsv28_30              : 3; // 28.30: Reserved
+  uint32_t test_mode_corr_eusb2  : 1; // 31 Test mode control for eUSB2 PHY
+} dwc2_gotgctl_t;
+TU_VERIFY_STATIC(sizeof(dwc2_gotgctl_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t rsv0_1                : 2; //  0..1  Reserved
+  uint32_t ses_end_det           : 1; //  2     Session end detected
+  uint32_t rsv3_7                : 5; //  3..7  Reserved
+  uint32_t srs_status_change     : 1; //  8     Session request success status change
+  uint32_t hns_status_change     : 1; //  9     Host negotiation success status change
+  uint32_t rsv10_16              : 7; // 10..16 Reserved
+  uint32_t hng_det               : 1; // 17     Host negotiation detected
+  uint32_t adev_timeout_change   : 1; // 18     A-device timeout change
+  uint32_t dbnc_done             : 1; // 19     Debounce done
+  uint32_t mult_val_lp_change    : 1; // 20     Multi-valued input pin change
+  uint32_t rsv21_31              :11; // 21..31 Reserved
+} dwc2_gotgint_t;
+TU_VERIFY_STATIC(sizeof(dwc2_gotgint_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t gintmask              :  1; //  0 Global interrupt mask
+  uint32_t hbst_len              :  4; //  1..4 Burst length/type
+  uint32_t dma_en                :  1; //  5 DMA enable
+  uint32_t rsv6                  :  1; //  6 Reserved
+  uint32_t nptxf_empty_lvl       :  1; //  7 Non-periodic Tx FIFO empty level
+  uint32_t ptxf_empty_lvl        :  1; //  8 Periodic Tx FIFO empty level
+  uint32_t rsv9_20               : 12; //  9.20: Reserved
+  uint32_t remote_mem_support    :  1; // 21 Remote memory support
+  uint32_t notify_all_dma_write  :  1; // 22 Notify all DMA writes
+  uint32_t ahb_single            :  1; // 23 AHB single
+  uint32_t inv_desc_endian       :  1; // 24 Inverse descriptor endian
+  uint32_t rsv25_31              :  7; // 25..31 Reserved
+} dwc2_gahbcfg_t;
+TU_VERIFY_STATIC(sizeof(dwc2_gahbcfg_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t timeout_cal             :  3; /* 0..2 Timeout calibration.
+    The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard
+    timeout value for full- speed operation is 16 to 18 (inclusive) bit times. The application must program this field
+    based on the speed of enumeration. The number of bit times added per PHY clock are as follows:
+    - High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times
+    - Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */
+  uint32_t phy_if16                : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits
+  uint32_t ulpi_utmi_sel           : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI
+  uint32_t fs_intf_sel             : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin
+  uint32_t phy_sel                 : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver
+  uint32_t ddr_sel                 : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit
+  uint32_t srp_capable             : 1; // 8 SRP-capable
+  uint32_t hnp_capable             : 1; // 9 HNP-capable
+  uint32_t turnaround_time         : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+
+  uint32_t rsv14                   : 1; // 14 Reserved
+  uint32_t phy_low_power_clk_sel   : 1; /* 15 PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode.
+    In FS/LS modes, the PHY can usually operate on a 48-MHz clock to save power. This bit is valid only for UTMI+ PHYs.
+    - 0: 480 Mhz internal PLL: the UTMI interface operates at either 60 MHz (8 bit) or 30 MHz (16-bit)
+    - 1 48 Mhz external clock: the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode */
+  uint32_t otg_i2c_sel             : 1; // 16 OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals
+  uint32_t ulpi_fsls               : 1; /* 17 ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS.
+                                             valid only when the FS serial transceiver is selected on the ULPI PHY. */
+  uint32_t ulpi_auto_resume        : 1; // 18 ULPI Auto-resume
+  uint32_t ulpi_clk_sus_m          : 1; // 19 ULPI Clock SuspendM
+  uint32_t ulpi_ext_vbus_drv       : 1; // 20 ULPI External VBUS Drive
+  uint32_t ulpi_int_vbus_indicator : 1; // 21 ULPI Internal VBUS Indicator
+  uint32_t term_sel_dl_pulse       : 1; // 22 TermSel DLine pulsing
+  uint32_t indicator_complement    : 1; // 23 Indicator complement
+  uint32_t indicator_pass_through  : 1; // 24 Indicator pass through
+  uint32_t ulpi_if_protect_disable : 1; // 25 ULPI interface protect disable
+  uint32_t ic_usb_capable          : 1; // 26 IC_USB Capable
+  uint32_t ic_usb_traf_ctl         : 1; // 27 IC_USB Traffic Control
+  uint32_t tx_end_delay            : 1; // 28 TX end delay
+  uint32_t force_host_mode         : 1; // 29 Force host mode
+  uint32_t force_dev_mode          : 1; // 30 Force device mode
+  uint32_t corrupt_tx_pkt          : 1; // 31 Corrupt Tx packet. 0: normal, 1: debug
+} dwc2_gusbcfg_t;
+TU_VERIFY_STATIC(sizeof(dwc2_gusbcfg_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t core_soft_rst          : 1; // 0 Core Soft Reset
+  uint32_t piufs_soft_rst         : 1; // 1 PIU FS Dedicated Controller Soft Reset
+  uint32_t frame_counter_rst      : 1; // 2 Frame Counter Reset (host)
+  uint32_t intoken_q_flush        : 1; // 3 IN Token Queue Flush
+  uint32_t rx_fifo_flush          : 1; // 4 RX FIFO Flush
+  uint32_t tx_fifo_flush          : 1; // 5 TX FIFO Flush
+  uint32_t tx_fifo_num            : 5; // 6..10 TX FIFO Number
+  uint32_t rsv11_28               :18; // 11..28 Reserved
+  uint32_t core_soft_rst_done     : 1; // 29 Core Soft Reset Done, from v4.20a
+  uint32_t dma_req                : 1; // 30 DMA Request
+  uint32_t ahb_idle               : 1; // 31 AHB Idle
+} dwc2_grstctl_t;
+TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t ep_ch_num             : 4; // 0..3 Endpoint/Channel Number
+  uint32_t byte_count            :11; // 4..14 Byte Count
+  uint32_t dpid                  : 2; // 15..16 Data PID
+  uint32_t packet_status         : 4; // 17..20 Packet Status
+  uint32_t frame_number          : 4; // 21..24 Frame Number
+  uint32_t rsv25_31              : 7; // 25..31 Reserved
+} dwc2_grxstsp_t;
+TU_VERIFY_STATIC(sizeof(dwc2_grxstsp_t) == 4, "incorrect size");
+
+// Hardware Configuration
+typedef struct TU_ATTR_PACKED {
+  uint32_t op_mode                : 3; // 0..2 HNP/SRP Host/Device/OTG mode
+  uint32_t arch                   : 2; // 3..4 Slave/External/Internal DMA
+  uint32_t single_point           : 1; // 5 0: support hub and split | 1: no hub, no split
+  uint32_t hs_phy_type            : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
+  uint32_t fs_phy_type            : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
+  uint32_t num_dev_ep             : 4; // 10..13 Number of device endpoints (excluding EP0)
+  uint32_t num_host_ch            : 4; // 14..17 Number of host channel (excluding control)
+  uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel
+  uint32_t enable_dynamic_fifo    : 1; // 19 Dynamic FIFO Sizing Enabled
+  uint32_t mul_proc_intrpt        : 1; // 20 Multi-Processor Interrupt enabled (OTG_MULTI_PROC_INTRPT)
+  uint32_t reserved21             : 1; // 21 reserved
+  uint32_t nptx_q_depth           : 2; // 22..23 Non-periodic request queue depth: 0 = 2.  1 = 4, 2 = 8
+  uint32_t ptx_q_depth            : 2; // 24..25 Host periodic request queue depth: 0 = 2.  1 = 4, 2 = 8
+  uint32_t token_q_depth          : 5; // 26..30 Device IN token sequence learning queue depth: 0-30
+  uint32_t otg_enable_ic_usb      : 1; // 31 IC_USB mode specified for mode of operation
+} dwc2_ghwcfg2_t;
 TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
 
-typedef struct TU_ATTR_PACKED
-{
-  uint32_t xfer_size_width          : 4;  // Transfer size counter in bits = 11 + n (max 19 bits)
-  uint32_t packet_size_width        : 3;  // Packet size counter in bits = 4 + n (max 10 bits)
-  uint32_t otg_enable               : 1;  // 1 is OTG capable
-  uint32_t i2c_enable               : 1;  // I2C interface is available
-  uint32_t vendor_ctrl_itf          : 1;  // Vendor control interface is available
-  uint32_t optional_feature_removed : 1;  // remove User ID, GPIO, SOF toggle & counter
-  uint32_t synch_reset              : 1;  // 0: async reset | 1: synch reset
-  uint32_t otg_adp_support          : 1;  // ADP logic is present along with HSOTG controller
-  uint32_t otg_enable_hsic          : 1;  // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
-  uint32_t battery_charger_support  : 1;  // support battery charger
-  uint32_t lpm_mode                 : 1;  // LPC mode
-  uint32_t total_fifo_size          : 16; // DFIFO depth value in terms of 32-bit words
+typedef struct TU_ATTR_PACKED {
+  uint32_t xfer_size_width          : 4;  // 0..3 Transfer size counter in bits = 11 + n (max 19 bits)
+  uint32_t packet_size_width        : 3;  // 4..6 Packet size counter in bits = 4 + n (max 10 bits)
+  uint32_t otg_enable               : 1;  // 7 OTG capable
+  uint32_t i2c_enable               : 1;  // 8 I2C interface is available
+  uint32_t vendor_ctrl_itf          : 1;  // 9 Vendor control interface is available
+  uint32_t optional_feature_removed : 1;  // 10 remove User ID, GPIO, SOF toggle & counter to save gate count
+  uint32_t synch_reset              : 1;  // 11 0: async reset | 1: synch reset
+  uint32_t otg_adp_support          : 1;  // 12 ADP logic is present along with HSOTG controller
+  uint32_t otg_enable_hsic          : 1;  // 13 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
+  uint32_t battery_charger_support  : 1;  // s14 upport battery charger
+  uint32_t lpm_mode                 : 1;  // 15 LPM mode
+  uint32_t dfifo_depth              : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words
 }dwc2_ghwcfg3_t;
-
 TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
 
-typedef struct TU_ATTR_PACKED
-{
-  uint32_t num_dev_period_in_ep       : 4; // Number of Device Periodic IN Endpoints
-  uint32_t power_optimized            : 1; // Partial Power Down Enabled
-  uint32_t ahb_freq_min               : 1; // 1: minimum of AHB frequency is less than 60 MHz
-  uint32_t hibernation                : 1; // Hibernation feature is enabled
-  uint32_t reserved7                  : 3;
-  uint32_t service_interval_mode      : 1; // Service Interval supported
-  uint32_t ipg_isoc_en                : 1; // IPG ISOC supported
-  uint32_t acg_enable                 : 1; // ACG enabled
-  uint32_t reserved13                 : 1;
-  uint32_t utmi_phy_data_width        : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
-  uint32_t dev_ctrl_ep_num            : 4; // Number of Device control endpoints in addition to EP0
-  uint32_t iddg_filter_enabled        : 1;
-  uint32_t vbus_valid_filter_enabled  : 1;
-  uint32_t a_valid_filter_enabled     : 1;
-  uint32_t b_valid_filter_enabled     : 1;
-  uint32_t dedicated_fifos            : 1; // Dedicated tx fifo for device IN Endpoint is enabled
-  uint32_t num_dev_in_eps             : 4; // Number of Device IN Endpoints including EP0
-  uint32_t dma_desc_enable            : 1; // scatter/gather DMA configuration
-  uint32_t dma_dynamic                : 1; // Dynamic scatter/gather DMA
+typedef struct TU_ATTR_PACKED {
+  uint32_t num_dev_period_in_ep     : 4; // 0..3 Number of Device Periodic IN Endpoints
+  uint32_t partial_powerdown        : 1; // 4 Partial Power Down Enabled
+  uint32_t ahb_freq_min             : 1; // 5 1: minimum of AHB frequency is less than 60 MHz
+  uint32_t hibernation              : 1; // 6 Hibernation feature is enabled
+  uint32_t extended_hibernation     : 1; // 7 Extended Hibernation feature is enabled
+  uint32_t reserved8                : 1; // 8 Reserved
+  uint32_t enhanced_lpm_support1    : 1; // 9 Enhanced LPM Support1
+  uint32_t service_interval_flow    : 1; // 10 Service Interval flow is supported
+  uint32_t ipg_isoc_support         : 1; // 11 Interpacket GAP ISO OUT worst-case is supported
+  uint32_t acg_support              : 1; // 12 Active clock gating is supported
+  uint32_t enhanced_lpm_support     : 1; // 13 Enhanced LPM Support
+  uint32_t phy_data_width           : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
+  uint32_t ctrl_ep_num              : 4; // 16..19 Number of Device control endpoints in addition to EP0
+  uint32_t iddg_filter              : 1; // 20 IDDG Filter Enabled
+  uint32_t vbus_valid_filter        : 1; // 21 VBUS Valid Filter Enabled
+  uint32_t a_valid_filter           : 1; // 22 A Valid Filter Enabled
+  uint32_t b_valid_filter           : 1; // 23 B Valid Filter Enabled
+  uint32_t session_end_filter       : 1; // 24 Session End Filter Enabled
+  uint32_t dedicated_fifos          : 1; // 25 Dedicated tx fifo for device IN Endpoint
+  uint32_t num_dev_in_eps           : 4; // 26..29 Number of Device IN Endpoints including EP0
+  uint32_t dma_desc_enabled         : 1; // scatter/gather DMA configuration enabled
+  uint32_t dma_desc_dynamic         : 1; // Dynamic scatter/gather DMA
 }dwc2_ghwcfg4_t;
-
 TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
 
+//--------------------------------------------------------------------
+// Host Register Bitfield
+//--------------------------------------------------------------------
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t fifo_available      : 16; // 0..15 Number of words available in the Tx FIFO
+  uint32_t req_queue_available :  8; // 16..23 Number of spaces available in the NPT transmit request queue for both IN and OU
+  // 24..31 is top entry in the request queue that is currently being processed by the MAC
+  uint32_t qtop_terminate      :  1; // 24 Last entry for selected channel
+  uint32_t qtop_type           :  2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command
+  uint32_t qtop_ch_num         :  4; // 27..30 Channel number
+} dwc2_hnptxsts_t;
+TU_VERIFY_STATIC(sizeof(dwc2_hnptxsts_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t fifo_available      : 16; // 0..15 Number of words available in the Tx FIFO
+  uint32_t req_queue_available : 7; // 16..22 Number of spaces available in the PTX transmit request queue
+  uint32_t qtop_terminate      : 1; // 23 Last entry for selected channel
+  uint32_t qtop_last_period    : 1; // 24 Last entry for selected channel is a periodic entry
+  uint32_t qtop_type           : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command
+  uint32_t qtop_ch_num         : 4; // 27..30 Channel number
+  uint32_t qtop_odd_frame      : 1; // 31 Send in odd frame
+} dwc2_hptxsts_t;
+TU_VERIFY_STATIC(sizeof(dwc2_hptxsts_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t conn_status         : 1; // 0 Port connect status
+  uint32_t conn_detected       : 1; // 1 Port connect detected
+  uint32_t enable              : 1; // 2 Port enable status
+  uint32_t enable_change       : 1; // 3 Port enable change
+  uint32_t over_current_active : 1; // 4 Port Over-current active
+  uint32_t over_current_change : 1; // 5 Port Over-current change
+  uint32_t resume              : 1; // 6 Port resume
+  uint32_t suspend             : 1; // 7 Port suspend
+  uint32_t reset               : 1; // 8 Port reset
+  uint32_t rsv9                : 1; // 9 Reserved
+  uint32_t line_status         : 2; // 10..11 Line status
+  uint32_t power               : 1; // 12 Port power
+  uint32_t test_control        : 4; // 13..16 Port Test control
+  uint32_t speed               : 2; // 17..18 Port speed
+  uint32_t rsv19_31            :13; // 19..31 Reserved
+}dwc2_hprt_t;
+TU_VERIFY_STATIC(sizeof(dwc2_hprt_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t ep_size         : 11; // 0..10 Maximum packet size
+  uint32_t ep_num          :  4; // 11..14 Endpoint number
+  uint32_t ep_dir          :  1; // 15 Endpoint direction
+  uint32_t rsv16           :  1; // 16 Reserved
+  uint32_t low_speed_dev   :  1; // 17 Low-speed device
+  uint32_t ep_type         :  2; // 18..19 Endpoint type
+  uint32_t err_multi_count :  2; // 20..21 Error (splitEn = 1) / Multi (SplitEn = 0)  count
+  uint32_t dev_addr        :  7; // 22..28 Device address
+  uint32_t odd_frame       :  1; // 29 Odd frame
+  uint32_t disable         :  1; // 30 Channel disable
+  uint32_t enable          :  1; // 31 Channel enable
+} dwc2_channel_char_t;
+TU_VERIFY_STATIC(sizeof(dwc2_channel_char_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t hub_port        :  7; // 0..6 Hub port number
+  uint32_t hub_addr        :  7; // 7..13 Hub address
+  uint32_t xact_pos        :  2; // 14..15 Transaction position
+  uint32_t split_compl     :  1; // 16 Split completion
+  uint32_t rsv17_30        : 14; // 17..30 Reserved
+  uint32_t split_en        :  1; // 31 Split enable
+} dwc2_channel_split_t;
+TU_VERIFY_STATIC(sizeof(dwc2_channel_split_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t xfer_size      : 19; // 0..18 Transfer size in bytes
+  uint32_t packet_count   : 10; // 19..28 Number of packets
+  uint32_t pid            :  2; // 29..30 Packet ID
+  uint32_t do_ping        :  1; // 31 Do PING
+} dwc2_channel_tsize_t;
+TU_VERIFY_STATIC(sizeof(dwc2_channel_tsize_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t num        : 16; // 0..15 Frame number
+  uint32_t remainning : 16; // 16..31 Frame remaining
+} dwc2_hfnum_t;
+TU_VERIFY_STATIC(sizeof(dwc2_hfnum_t) == 4, "incorrect size");
+
 // Host Channel
-typedef struct
-{
-  volatile uint32_t hcchar;           // 500 + 20*ch Host Channel Characteristics
-  volatile uint32_t hcsplt;           // 504 + 20*ch Host Channel Split Control
-  volatile uint32_t hcint;            // 508 + 20*ch Host Channel Interrupt
-  volatile uint32_t hcintmsk;         // 50C + 20*ch Host Channel Interrupt Mask
-  volatile uint32_t hctsiz;           // 510 + 20*ch Host Channel Transfer Size
-  volatile uint32_t hcdma;            // 514 + 20*ch Host Channel DMA Address
-           uint32_t reserved518;      // 518 + 20*ch
-  volatile uint32_t hcdmab;           // 51C + 20*ch Host Channel DMA Address
+typedef struct {
+  union {
+    volatile uint32_t hcchar;           // 500 + 20*ch Host Channel Characteristics
+    volatile dwc2_channel_char_t hcchar_bm;
+  };
+  union {
+    volatile uint32_t hcsplt;           // 504 + 20*ch Host Channel Split Control
+    volatile dwc2_channel_split_t hcsplt_bm;
+  };
+    volatile uint32_t hcint;            // 508 + 20*ch Host Channel Interrupt
+    volatile uint32_t hcintmsk;         // 50C + 20*ch Host Channel Interrupt Mask
+  union {
+    volatile uint32_t hctsiz;           // 510 + 20*ch Host Channel Transfer Size
+    volatile dwc2_channel_tsize_t hctsiz_bm;
+  };
+    volatile uint32_t hcdma;            // 514 + 20*ch Host Channel DMA Address
+             uint32_t reserved518;      // 518 + 20*ch
+    volatile uint32_t hcdmab;           // 51C + 20*ch Host Channel DMA Address
 } dwc2_channel_t;
 
-// Endpoint IN
-typedef struct
-{
-  volatile uint32_t diepctl;          // 900 + 20*ep Device IN Endpoint Control
-           uint32_t reserved04;       // 904
-  volatile uint32_t diepint;          // 908 + 20*ep Device IN Endpoint Interrupt
-           uint32_t reserved0c;       // 90C
-  volatile uint32_t dieptsiz;         // 910 + 20*ep Device IN Endpoint Transfer Size
-  volatile uint32_t diepdma;          // 914 + 20*ep Device IN Endpoint DMA Address
-  volatile uint32_t dtxfsts;          // 918 + 20*ep Device IN Endpoint Tx FIFO Status
-           uint32_t reserved1c;       // 91C
-} dwc2_epin_t;
+//--------------------------------------------------------------------
+// Device Register Bitfield
+//--------------------------------------------------------------------
+typedef struct TU_ATTR_PACKED {
+  uint32_t speed                    : 2; // 0..1 Speed
+  uint32_t nzsts_out_handshake      : 1; // 2 Non-zero-length status OUT handshake
+  uint32_t en_32khz_suspsend        : 1; // 3 Enable 32-kHz SUSPEND mode
+  uint32_t address                  : 7; // 4..10 Device address
+  uint32_t period_frame_interval    : 2; // 11..12 Periodic frame interval
+  uint32_t en_out_nak               : 1; // 13 Enable Device OUT NAK
+  uint32_t xcvr_delay               : 1; // 14 Transceiver delay
+  uint32_t erratic_int_mask         : 1; // 15 Erratic interrupt mask
+  uint32_t rsv16                    : 1; // 16 Reserved
+  uint32_t ipg_iso_support          : 1; // 17 Interpacket gap ISO support
+  uint32_t epin_mismatch_count      : 5; // 18..22 EP IN mismatch count
+  uint32_t dma_desc                 : 1; // 23 Enable scatter/gatter DMA descriptor
+  uint32_t period_schedule_interval : 2; // 24..25 Periodic schedule interval for scatter/gatter DMA
+  uint32_t resume_valid             : 6; // 26..31 Resume valid period
+} dwc2_dcfg_t;
+TU_VERIFY_STATIC(sizeof(dwc2_dcfg_t) == 4, "incorrect size");
 
-// Endpoint OUT
-typedef struct
-{
-  volatile uint32_t doepctl;          // B00 + 20*ep Device OUT Endpoint Control
-           uint32_t reserved04;       // B04
-  volatile uint32_t doepint;          // B08 + 20*ep Device OUT Endpoint Interrupt
-           uint32_t reserved0c;       // B0C
-  volatile uint32_t doeptsiz;         // B10 + 20*ep Device OUT Endpoint Transfer Size
-  volatile uint32_t doepdma;          // B14 + 20*ep Device OUT Endpoint DMA Address
-           uint32_t reserved18[2];    // B18..B1C
-} dwc2_epout_t;
+typedef struct TU_ATTR_PACKED {
+  uint32_t remote_wakeup_signal   : 1; // 0 Remote wakeup signal
+  uint32_t soft_disconnet         : 1; // 1 Soft disconnect
+  uint32_t gnp_in_nak_status      : 1; // 2 Global non-periodic NAK IN status
+  uint32_t gout_nak_status        : 1; // 3 Global OUT NAK status
+  uint32_t test_control           : 3; // 4..6 Test control
+  uint32_t set_gnp_in_nak         : 1; // 7 Set global non-periodic IN NAK
+  uint32_t clear_gnp_in_nak       : 1; // 8 Clear global non-periodic IN NAK
+  uint32_t set_gout_nak           : 1; // 9 Set global OUT NAK
+  uint32_t clear_gout_nak         : 1; // 10 Clear global OUT NAK
+  uint32_t poweron_prog_done      : 1; // 11 Power-on programming done
+  uint32_t rsv12                  : 1; // 12 Reserved
+  uint32_t global_multi_count     : 2; // 13..14 Global multi-count
+  uint32_t ignore_frame_number    : 1; // 15 Ignore frame number
+  uint32_t nak_on_babble          : 1; // 16 NAK on babble
+  uint32_t en_cont_on_bna         : 1; // 17 Enable continue on BNA
+  uint32_t deep_sleep_besl_reject : 1; // 18 Deep sleep BESL reject
+  uint32_t service_interval       : 1; // 19 Service interval for ISO IN endpoint
+  uint32_t rsv20_31               :12; // 20..31 Reserved
+} dwc2_dctl_t;
+TU_VERIFY_STATIC(sizeof(dwc2_dctl_t) == 4, "incorrect size");
 
-typedef struct
-{
-  //------------- Core Global -------------//
-  volatile uint32_t gotgctl;          // 000 OTG Control and Status
-  volatile uint32_t gotgint;          // 004 OTG Interrupt
-  volatile uint32_t gahbcfg;          // 008 AHB Configuration
-  volatile uint32_t gusbcfg;          // 00c USB Configuration
-  volatile uint32_t grstctl;          // 010 Reset
-  volatile uint32_t gintsts;          // 014 Interrupt
-  volatile uint32_t gintmsk;          // 018 Interrupt Mask
-  volatile uint32_t grxstsr;          // 01c Receive Status Debug Read
-  volatile uint32_t grxstsp;          // 020 Receive Status Read/Pop
-  volatile uint32_t grxfsiz;          // 024 Receive FIFO Size
-union {
-  volatile uint32_t dieptxf0;         // 028 EP0 Tx FIFO Size
-  volatile uint32_t gnptxfsiz;        // 028 Non-periodic Transmit FIFO Size
-};
-  volatile uint32_t gnptxsts;         // 02c Non-periodic Transmit FIFO/Queue Status
-  volatile uint32_t gi2cctl;          // 030 I2C Address
-  volatile uint32_t gpvndctl;         // 034 PHY Vendor Control
-union {
-  volatile uint32_t ggpio;            // 038 General Purpose IO
-  volatile uint32_t stm32_gccfg;      // 038 STM32 General Core Configuration
-};
-  volatile uint32_t guid;             // 03C User (Application programmable) ID
-  volatile uint32_t gsnpsid;          // 040 Synopsys ID + Release version
-  volatile uint32_t ghwcfg1;          // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
-union {
-  volatile uint32_t ghwcfg2;          // 048 User Hardware Configuration2
-  dwc2_ghwcfg2_t    ghwcfg2_bm;
-};
-union {
-  volatile uint32_t ghwcfg3;          // 04C User Hardware Configuration3
-  dwc2_ghwcfg3_t    ghwcfg3_bm;
-};
-union {
-  volatile uint32_t ghwcfg4;          // 050 User Hardware Configuration4
-  dwc2_ghwcfg4_t    ghwcfg4_bm;
-};
-  volatile uint32_t glpmcfg;          // 054 Core LPM Configuration
-  volatile uint32_t gpwrdn;           // 058 Power Down
-  volatile uint32_t gdfifocfg;        // 05C DFIFO Software Configuration
-  volatile uint32_t gadpctl;          // 060 ADP Timer, Control and Status
-           uint32_t reserved64[39];   // 064..0FF
-  volatile uint32_t hptxfsiz;         // 100 Host Periodic Tx FIFO Size
-  volatile uint32_t dieptxf[15];      // 104..13C Device Periodic Transmit FIFO Size
-           uint32_t reserved140[176]; // 140..3FF
+typedef struct TU_ATTR_PACKED {
+  uint32_t suspend_status : 1; // 0 Suspend status
+  uint32_t enum_speed     : 2; // 1..2 Enumerated speed
+  uint32_t erratic_err    : 1; // 3 Erratic error
+  uint32_t rsv4_7         : 4; // 4..7 Reserved
+  uint32_t frame_number   : 14; // 8..21  Frame/MicroFrame number
+  uint32_t line_status    : 2; // 22..23 Line status
+  uint32_t rsv24_31       : 8; // 24..31 Reserved
+} dwc2_dsts_t;
+TU_VERIFY_STATIC(sizeof(dwc2_dsts_t) == 4, "incorrect size");
 
-  //------------- Host -------------//
-  volatile uint32_t hcfg;             // 400 Host Configuration
-  volatile uint32_t hfir;             // 404 Host Frame Interval
-  volatile uint32_t hfnum;            // 408 Host Frame Number / Frame Remaining
-           uint32_t reserved40c;      // 40C
-  volatile uint32_t hptxsts;          // 410 Host Periodic TX FIFO / Queue Status
-  volatile uint32_t haint;            // 414 Host All Channels Interrupt
-  volatile uint32_t haintmsk;         // 418 Host All Channels Interrupt Mask
-  volatile uint32_t hflbaddr;         // 41C Host Frame List Base Address
-           uint32_t reserved420[8];   // 420..43F
-  volatile uint32_t hprt;             // 440 Host Port Control and Status
-           uint32_t reserved444[47];  // 444..4FF
+typedef struct TU_ATTR_PACKED {
+  uint32_t xfer_complete       : 1; // 0 Transfer complete
+  uint32_t disabled            : 1; // 1 Endpoint disabled
+  uint32_t ahb_err             : 1; // 2 AHB error
+  uint32_t timeout             : 1; // 3 Timeout
+  uint32_t in_rx_txfe          : 1; // 4 IN token received when TxFIFO is empty
+  uint32_t in_rx_ep_mismatch   : 1; // 5 IN token received with EP mismatch
+  uint32_t in_ep_nak_effective : 1; // 6 IN endpoint NAK effective
+  uint32_t txfifo_empty        : 1; // 7 TX FIFO empty
+  uint32_t txfifo_underrun     : 1; // 8 Tx FIFO under run
+  uint32_t bna                 : 1; // 9 Buffer not available
+  uint32_t rsv10               : 1; // 10 Reserved
+  uint32_t iso_packet_drop     : 1; // 11 Isochronous OUT packet drop status
+  uint32_t babble_err          : 1; // 12 Babble error
+  uint32_t nak                 : 1; // 13 NAK
+  uint32_t nyet                : 1; // 14 NYET
+  uint32_t rsv14_31            :17; // 15..31 Reserved
+} dwc2_diepint_t;
+TU_VERIFY_STATIC(sizeof(dwc2_diepint_t) == 4, "incorrect size");
 
-  //------------- Host Channel -------------//
-  dwc2_channel_t    channel[16];      // 500..6FF Host Channels 0-15
-           uint32_t reserved700[64];  // 700..7FF
+typedef struct TU_ATTR_PACKED {
+        uint32_t mps                : 11; // 0..10 Maximum packet size, EP0 only use 2 bit
+        uint32_t next_ep            : 4; // 11..14 Next endpoint number
+        uint32_t active             : 1; // 15 Active
+  const uint32_t dpid_iso_odd       : 1; // 16 DATA0/DATA1 for bulk/interrupt, odd frame for isochronous
+  const uint32_t nak_status         : 1; // 17 NAK status
+        uint32_t type               : 2; // 18..19 Endpoint type
+        uint32_t rsv20              : 1; // 20 Reserved
+        uint32_t stall              : 1; // 21 Stall
+        uint32_t tx_fifo_num        : 4; // 22..25 Tx FIFO number (IN)
+        uint32_t clear_nak          : 1; // 26 Clear NAK
+        uint32_t set_nak            : 1; // 27 Set NAK
+        uint32_t set_data0_iso_even : 1; // 28 Set DATA0 if bulk/interrupt, even frame for isochronous
+        uint32_t set_data1_iso_odd  : 1; // 29 Set DATA1 if bulk/interrupt, odd frame for isochronous
+        uint32_t disable            : 1; // 30 Disable
+        uint32_t enable             : 1; // 31 Enable
+} dwc2_depctl_t;
+TU_VERIFY_STATIC(sizeof(dwc2_depctl_t) == 4, "incorrect size");
 
- //------------- Device -------------//
-  volatile uint32_t dcfg;             // 800 Device Configuration
-  volatile uint32_t dctl;             // 804 Device Control
-  volatile uint32_t dsts;             // 808 Device Status (RO)
-           uint32_t reserved80c;      // 80C
-  volatile uint32_t diepmsk;          // 810 Device IN Endpoint Interrupt Mask
-  volatile uint32_t doepmsk;          // 814 Device OUT Endpoint Interrupt Mask
-  volatile uint32_t daint;            // 818 Device All Endpoints Interrupt
-  volatile uint32_t daintmsk;         // 81C Device All Endpoints Interrupt Mask
-  volatile uint32_t dtknqr1;          // 820 Device IN token sequence learning queue read1
-  volatile uint32_t dtknqr2;          // 824 Device IN token sequence learning queue read2
-  volatile uint32_t dvbusdis;         // 828 Device VBUS Discharge Time
-  volatile uint32_t dvbuspulse;       // 82C Device VBUS Pulsing Time
-  volatile uint32_t dthrctl;          // 830 Device threshold Control
-  volatile uint32_t diepempmsk;       // 834 Device IN Endpoint FIFO Empty Interrupt Mask
-  volatile uint32_t deachint;         // 838 Device Each Endpoint Interrupt
-  volatile uint32_t deachmsk;         // 83C Device Each Endpoint Interrupt msk
-  volatile uint32_t diepeachmsk[16];  // 840..87C Device Each IN Endpoint mask
-  volatile uint32_t doepeachmsk[16];  // 880..8BF Device Each OUT Endpoint mask
-           uint32_t reserved8c0[16];  // 8C0..8FF
+typedef struct TU_ATTR_PACKED {
+  uint32_t xfer_complete      : 1; // 0 Transfer complete
+  uint32_t disabled           : 1; // 1 Endpoint disabled
+  uint32_t ahb_err            : 1; // 2 AHB error
+  uint32_t setup_phase_done   : 1; // 3 Setup phase done
+  uint32_t out_rx_ep_disabled : 1; // 4 OUT token received when endpoint disabled
+  uint32_t status_phase_rx    : 1; // 5 Status phase received
+  uint32_t setup_b2b          : 1; // 6 Setup packet back-to-back
+  uint32_t rsv7               : 1; // 7 Reserved
+  uint32_t out_packet_err     : 1; // 8 OUT packet error
+  uint32_t bna                : 1; // 9 Buffer not available
+  uint32_t rsv10              : 1; // 10 Reserved
+  uint32_t iso_packet_drop    : 1; // 11 Isochronous OUT packet drop status
+  uint32_t babble_err         : 1; // 12 Babble error
+  uint32_t nak                : 1; // 13 NAK
+  uint32_t nyet               : 1; // 14 NYET
+  uint32_t setup_packet_rx    : 1; // 15 Setup packet received (Buffer DMA Mode only)
+  uint32_t rsv16_31           :16; // 16..31 Reserved
+} dwc2_doepint_t;
+TU_VERIFY_STATIC(sizeof(dwc2_doepint_t) == 4, "incorrect size");
 
-  //------------- Device Endpoint -------------//
-  dwc2_epin_t       epin[16];         // 900..AFF  IN Endpoints
-  dwc2_epout_t      epout[16];        // B00..CFF  OUT Endpoints
-           uint32_t reservedd00[64];  // D00..DFF
+typedef struct TU_ATTR_PACKED {
+  uint32_t xfer_size    : 19; // 0..18 Transfer size in bytes
+  uint32_t packet_count : 10; // 19..28 Number of packets
+  uint32_t mc_pid       :  2; // 29..30 IN: Multi Count, OUT: PID
+} dwc2_ep_tsize_t;
+TU_VERIFY_STATIC(sizeof(dwc2_ep_tsize_t) == 4, "incorrect size");
 
-  //------------- Power Clock -------------//
-  volatile uint32_t pcgctl;           // E00 Power and Clock Gating Control
-  volatile uint32_t pcgctl1;          // E04
-           uint32_t reservede08[126]; // E08..FFF
+// Device IN/OUT Endpoint
+typedef struct {
+  union {
+    volatile uint32_t diepctl;
+    volatile uint32_t doepctl;
 
-  //------------- FIFOs -------------//
-  // Word-accessed only using first pointer since it auto shift
-  volatile uint32_t fifo[16][0x400];  // 1000..FFFF Endpoint FIFO
+    volatile uint32_t ctl;
+    volatile dwc2_depctl_t ctl_bm;
+  };
+  uint32_t rsv04;
+  union {
+    volatile uint32_t intr;
+
+    volatile uint32_t diepint;
+    volatile dwc2_diepint_t diepint_bm;
+
+    volatile uint32_t doepint;
+    volatile dwc2_doepint_t doepint_bm;
+  };
+  uint32_t rsv0c;
+  union {
+    volatile uint32_t dieptsiz;
+    volatile uint32_t doeptsiz;
+    volatile uint32_t tsiz;
+    volatile dwc2_ep_tsize_t tsiz_bm;
+  };
+  union {
+    volatile uint32_t diepdma;
+    volatile uint32_t doepdma;
+  };
+  volatile uint32_t dtxfsts;
+  uint32_t rsv1c;
+}dwc2_dep_t;
+
+TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size");
+
+//--------------------------------------------------------------------
+// CSR Register Map
+//--------------------------------------------------------------------
+typedef struct {
+    //------------- Core Global -------------//
+  union {
+    volatile uint32_t gotgctl;          // 000 OTG Control and Status
+    volatile dwc2_gotgctl_t gotgctl_bm;
+  };
+  union {
+    volatile uint32_t gotgint;          // 004 OTG Interrupt
+    volatile dwc2_gotgint_t gotgint_bm;
+  };
+  union {
+    volatile uint32_t gahbcfg;          // 008 AHB Configuration
+    volatile dwc2_gahbcfg_t gahbcfg_bm;
+  };
+  union {
+    volatile uint32_t gusbcfg;          // 00c USB Configuration
+    volatile dwc2_gusbcfg_t gusbcfg_bm;
+  };
+  union {
+    volatile uint32_t grstctl;          // 010 Reset
+    volatile dwc2_grstctl_t grstctl_bm;
+  };
+    volatile uint32_t gintsts;          // 014 Interrupt
+    volatile uint32_t gintmsk;          // 018 Interrupt Mask
+    volatile uint32_t grxstsr;          // 01c Receive Status Debug Read
+  union {
+    volatile uint32_t grxstsp;          // 020 Receive Status Read/Pop
+    volatile dwc2_grxstsp_t grxstsp_bm;
+  };
+    volatile uint32_t grxfsiz;          // 024 Receive FIFO Size
+  union {
+    volatile uint32_t dieptxf0;         // 028 EP0 Tx FIFO Size
+    volatile uint32_t gnptxfsiz;        // 028 Non-periodic Transmit FIFO Size
+  };
+  union {
+    volatile uint32_t hnptxsts;         // 02c Non-periodic Transmit FIFO/Queue Status
+    volatile dwc2_hnptxsts_t hnptxsts_bm;
+    volatile uint32_t gnptxsts;
+  };
+    volatile uint32_t gi2cctl;          // 030 I2C Address
+    volatile uint32_t gpvndctl;         // 034 PHY Vendor Control
+  union {
+    volatile uint32_t ggpio;            // 038 General Purpose IO
+    volatile uint32_t stm32_gccfg;      // 038 STM32 General Core Configuration
+  };
+    volatile uint32_t guid;             // 03C User (Application programmable) ID
+    volatile uint32_t gsnpsid;          // 040 Synopsys ID + Release version
+    volatile uint32_t ghwcfg1;          // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
+  union {
+    volatile uint32_t ghwcfg2;          // 048 User Hardware Configuration2
+    volatile dwc2_ghwcfg2_t ghwcfg2_bm;
+  };
+  union {
+    volatile uint32_t ghwcfg3;          // 04C User Hardware Configuration3
+    volatile dwc2_ghwcfg3_t ghwcfg3_bm;
+  };
+  union {
+    volatile uint32_t ghwcfg4;          // 050 User Hardware Configuration4
+    volatile dwc2_ghwcfg4_t ghwcfg4_bm;
+  };
+    volatile uint32_t glpmcfg;          // 054 Core LPM Configuration
+    volatile uint32_t gpwrdn;           // 058 Power Down
+    volatile uint32_t gdfifocfg;        // 05C DFIFO Software Configuration
+    volatile uint32_t gadpctl;          // 060 ADP Timer, Control and Status
+             uint32_t reserved64[39];   // 064..0FF
+    volatile uint32_t hptxfsiz;         // 100 Host Periodic Tx FIFO Size
+    volatile uint32_t dieptxf[15];      // 104..13C Device Periodic Transmit FIFO Size
+             uint32_t reserved140[176]; // 140..3FF
+
+    //------------ Host -------------//
+    volatile uint32_t hcfg;             // 400 Host Configuration
+    volatile uint32_t hfir;             // 404 Host Frame Interval
+  union {
+    volatile uint32_t hfnum;            // 408 Host Frame Number / Frame Remaining
+    volatile dwc2_hfnum_t hfnum_bm;
+  };
+             uint32_t reserved40c;      // 40C
+  union {
+    volatile uint32_t hptxsts;          // 410 Host Periodic TX FIFO / Queue Status
+    volatile dwc2_hptxsts_t hptxsts_bm;
+  };
+    volatile uint32_t haint;            // 414 Host All Channels Interrupt
+    volatile uint32_t haintmsk;         // 418 Host All Channels Interrupt Mask
+    volatile uint32_t hflbaddr;         // 41C Host Frame List Base Address
+             uint32_t reserved420[8];   // 420..43F
+  union {
+    volatile uint32_t hprt;             // 440 Host Port Control and Status
+    volatile dwc2_hprt_t hprt_bm;
+  };
+             uint32_t reserved444[47];  // 444..4FF
+
+    //------------- Host Channel -------------//
+    dwc2_channel_t    channel[16];      // 500..6FF Host Channels 0-15
+             uint32_t reserved700[64];  // 700..7FF
+
+    //------------- Device -----------//
+  union {
+    volatile uint32_t dcfg;             // 800 Device Configuration
+    volatile dwc2_dcfg_t dcfg_bm;
+  };
+  union {
+    volatile uint32_t dctl;             // 804 Device Control
+    volatile dwc2_dctl_t dctl_bm;
+  };
+  union {
+    volatile uint32_t dsts;             // 808 Device Status (RO)
+    volatile dwc2_dsts_t dsts_bm;
+  };
+             uint32_t reserved80c;      // 80C
+  union {
+    volatile uint32_t diepmsk;          // 810 Device IN Endpoint Interrupt Mask
+    volatile dwc2_diepint_t diepmsk_bm;
+  };
+  union {
+    volatile uint32_t doepmsk;          // 814 Device OUT Endpoint Interrupt Mask
+    volatile dwc2_doepint_t doepmsk_bm;
+  };
+    volatile uint32_t daint;            // 818 Device All Endpoints Interrupt
+    volatile uint32_t daintmsk;         // 81C Device All Endpoints Interrupt Mask
+    volatile uint32_t dtknqr1;          // 820 Device IN token sequence learning queue read1
+    volatile uint32_t dtknqr2;          // 824 Device IN token sequence learning queue read2
+    volatile uint32_t dvbusdis;         // 828 Device VBUS Discharge Time
+    volatile uint32_t dvbuspulse;       // 82C Device VBUS Pulsing Time
+    volatile uint32_t dthrctl;          // 830 Device threshold Control
+    volatile uint32_t diepempmsk;       // 834 Device IN Endpoint FIFO Empty Interrupt Mask
+
+    // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line
+    // require OTG_MULTI_PROC_INTRPT=1
+    volatile uint32_t deachint;         // 838 Device Each Endpoint Interrupt
+    volatile uint32_t deachmsk;         // 83C Device Each Endpoint Interrupt mask
+    volatile uint32_t diepeachmsk[16];  // 840..87C Device Each IN Endpoint mask
+    volatile uint32_t doepeachmsk[16];  // 880..8BF Device Each OUT Endpoint mask
+             uint32_t reserved8c0[16];  // 8C0..8FF
+
+    //------------- Device Endpoint -------------//
+    union {
+      dwc2_dep_t ep[2][16];            // 0: IN, 1 OUT
+      struct {
+        dwc2_dep_t  epin[16];         // 900..AFF  IN Endpoints
+        dwc2_dep_t epout[16];        // B00..CFF  OUT Endpoints
+      };
+    };
+    uint32_t reservedd00[64];  // D00..DFF
+
+    //------------- Power Clock -------------//
+    volatile uint32_t pcgcctl;          // E00 Power and Clock Gating Characteristic Control
+    volatile uint32_t pcgcctl1;         // E04 Power and Clock Gating Characteristic Control 1
+             uint32_t reservede08[126]; // E08..FFF
+
+    //------------- FIFOs -------------//
+    // Word-accessed only using first pointer since it auto shift
+    volatile uint32_t fifo[16][0x400];  // 1000..FFFF Endpoint FIFO
 } dwc2_regs_t;
 
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg   ) == 0x0400, "incorrect size");
@@ -289,7 +794,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg   ) == 0x0800, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin   ) == 0x0900, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout  ) == 0x0B00, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctl ) == 0x0E00, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgcctl) == 0x0E00, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 //--------------------------------------------------------------------+
@@ -298,103 +803,105 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 /********************  Bit definition for GOTGCTL register  ********************/
 #define GOTGCTL_SRQSCS_Pos               (0U)
-#define GOTGCTL_SRQSCS_Msk               (0x1UL << GOTGCTL_SRQSCS_Pos)            // 0x00000001 */
-#define GOTGCTL_SRQSCS                   GOTGCTL_SRQSCS_Msk                       // Session request success */
+#define GOTGCTL_SRQSCS_Msk               (0x1UL << GOTGCTL_SRQSCS_Pos)            // 0x00000001
+#define GOTGCTL_SRQSCS                   GOTGCTL_SRQSCS_Msk                       // Session request success
 #define GOTGCTL_SRQ_Pos                  (1U)
-#define GOTGCTL_SRQ_Msk                  (0x1UL << GOTGCTL_SRQ_Pos)               // 0x00000002 */
-#define GOTGCTL_SRQ                      GOTGCTL_SRQ_Msk                          // Session request */
+#define GOTGCTL_SRQ_Msk                  (0x1UL << GOTGCTL_SRQ_Pos)               // 0x00000002
+#define GOTGCTL_SRQ                      GOTGCTL_SRQ_Msk                          // Session request
 #define GOTGCTL_VBVALOEN_Pos             (2U)
-#define GOTGCTL_VBVALOEN_Msk             (0x1UL << GOTGCTL_VBVALOEN_Pos)          // 0x00000004 */
-#define GOTGCTL_VBVALOEN                 GOTGCTL_VBVALOEN_Msk                     // VBUS valid override enable */
+#define GOTGCTL_VBVALOEN_Msk             (0x1UL << GOTGCTL_VBVALOEN_Pos)          // 0x00000004
+#define GOTGCTL_VBVALOEN                 GOTGCTL_VBVALOEN_Msk                     // VBUS valid override enable
 #define GOTGCTL_VBVALOVAL_Pos            (3U)
-#define GOTGCTL_VBVALOVAL_Msk            (0x1UL << GOTGCTL_VBVALOVAL_Pos)         // 0x00000008 */
-#define GOTGCTL_VBVALOVAL                GOTGCTL_VBVALOVAL_Msk                    // VBUS valid override value */
+#define GOTGCTL_VBVALOVAL_Msk            (0x1UL << GOTGCTL_VBVALOVAL_Pos)         // 0x00000008
+#define GOTGCTL_VBVALOVAL                GOTGCTL_VBVALOVAL_Msk                    // VBUS valid override value
 #define GOTGCTL_AVALOEN_Pos              (4U)
-#define GOTGCTL_AVALOEN_Msk              (0x1UL << GOTGCTL_AVALOEN_Pos)           // 0x00000010 */
-#define GOTGCTL_AVALOEN                  GOTGCTL_AVALOEN_Msk                      // A-peripheral session valid override enable */
+#define GOTGCTL_AVALOEN_Msk              (0x1UL << GOTGCTL_AVALOEN_Pos)           // 0x00000010
+#define GOTGCTL_AVALOEN                  GOTGCTL_AVALOEN_Msk                      // A-peripheral session valid override enable
 #define GOTGCTL_AVALOVAL_Pos             (5U)
-#define GOTGCTL_AVALOVAL_Msk             (0x1UL << GOTGCTL_AVALOVAL_Pos)          // 0x00000020 */
-#define GOTGCTL_AVALOVAL                 GOTGCTL_AVALOVAL_Msk                     // A-peripheral session valid override value */
+#define GOTGCTL_AVALOVAL_Msk             (0x1UL << GOTGCTL_AVALOVAL_Pos)          // 0x00000020
+#define GOTGCTL_AVALOVAL                 GOTGCTL_AVALOVAL_Msk                     // A-peripheral session valid override value
 #define GOTGCTL_BVALOEN_Pos              (6U)
-#define GOTGCTL_BVALOEN_Msk              (0x1UL << GOTGCTL_BVALOEN_Pos)           // 0x00000040 */
-#define GOTGCTL_BVALOEN                  GOTGCTL_BVALOEN_Msk                      // B-peripheral session valid override enable */
+#define GOTGCTL_BVALOEN_Msk              (0x1UL << GOTGCTL_BVALOEN_Pos)           // 0x00000040
+#define GOTGCTL_BVALOEN                  GOTGCTL_BVALOEN_Msk                      // B-peripheral session valid override enable
 #define GOTGCTL_BVALOVAL_Pos             (7U)
-#define GOTGCTL_BVALOVAL_Msk             (0x1UL << GOTGCTL_BVALOVAL_Pos)          // 0x00000080 */
-#define GOTGCTL_BVALOVAL                 GOTGCTL_BVALOVAL_Msk                     // B-peripheral session valid override value  */
+#define GOTGCTL_BVALOVAL_Msk             (0x1UL << GOTGCTL_BVALOVAL_Pos)          // 0x00000080
+#define GOTGCTL_BVALOVAL                 GOTGCTL_BVALOVAL_Msk                     // B-peripheral session valid override value
 #define GOTGCTL_HNGSCS_Pos               (8U)
-#define GOTGCTL_HNGSCS_Msk               (0x1UL << GOTGCTL_HNGSCS_Pos)            // 0x00000100 */
-#define GOTGCTL_HNGSCS                   GOTGCTL_HNGSCS_Msk                       // Host set HNP enable */
+#define GOTGCTL_HNGSCS_Msk               (0x1UL << GOTGCTL_HNGSCS_Pos)            // 0x00000100
+#define GOTGCTL_HNGSCS                   GOTGCTL_HNGSCS_Msk                       // Host set HNP enable
 #define GOTGCTL_HNPRQ_Pos                (9U)
-#define GOTGCTL_HNPRQ_Msk                (0x1UL << GOTGCTL_HNPRQ_Pos)             // 0x00000200 */
-#define GOTGCTL_HNPRQ                    GOTGCTL_HNPRQ_Msk                        // HNP request */
+#define GOTGCTL_HNPRQ_Msk                (0x1UL << GOTGCTL_HNPRQ_Pos)             // 0x00000200
+#define GOTGCTL_HNPRQ                    GOTGCTL_HNPRQ_Msk                        // HNP request
 #define GOTGCTL_HSHNPEN_Pos              (10U)
-#define GOTGCTL_HSHNPEN_Msk              (0x1UL << GOTGCTL_HSHNPEN_Pos)           // 0x00000400 */
-#define GOTGCTL_HSHNPEN                  GOTGCTL_HSHNPEN_Msk                      // Host set HNP enable */
+#define GOTGCTL_HSHNPEN_Msk              (0x1UL << GOTGCTL_HSHNPEN_Pos)           // 0x00000400
+#define GOTGCTL_HSHNPEN                  GOTGCTL_HSHNPEN_Msk                      // Host set HNP enable
 #define GOTGCTL_DHNPEN_Pos               (11U)
-#define GOTGCTL_DHNPEN_Msk               (0x1UL << GOTGCTL_DHNPEN_Pos)            // 0x00000800 */
-#define GOTGCTL_DHNPEN                   GOTGCTL_DHNPEN_Msk                       // Device HNP enabled */
+#define GOTGCTL_DHNPEN_Msk               (0x1UL << GOTGCTL_DHNPEN_Pos)            // 0x00000800
+#define GOTGCTL_DHNPEN                   GOTGCTL_DHNPEN_Msk                       // Device HNP enabled
 #define GOTGCTL_EHEN_Pos                 (12U)
-#define GOTGCTL_EHEN_Msk                 (0x1UL << GOTGCTL_EHEN_Pos)              // 0x00001000 */
-#define GOTGCTL_EHEN                     GOTGCTL_EHEN_Msk                         // Embedded host enable */
+#define GOTGCTL_EHEN_Msk                 (0x1UL << GOTGCTL_EHEN_Pos)              // 0x00001000
+#define GOTGCTL_EHEN                     GOTGCTL_EHEN_Msk                         // Embedded host enable
 #define GOTGCTL_CIDSTS_Pos               (16U)
-#define GOTGCTL_CIDSTS_Msk               (0x1UL << GOTGCTL_CIDSTS_Pos)            // 0x00010000 */
-#define GOTGCTL_CIDSTS                   GOTGCTL_CIDSTS_Msk                       // Connector ID status */
+#define GOTGCTL_CIDSTS_Msk               (0x1UL << GOTGCTL_CIDSTS_Pos)            // 0x00010000
+#define GOTGCTL_CIDSTS                   GOTGCTL_CIDSTS_Msk                       // Connector ID status
 #define GOTGCTL_DBCT_Pos                 (17U)
-#define GOTGCTL_DBCT_Msk                 (0x1UL << GOTGCTL_DBCT_Pos)              // 0x00020000 */
-#define GOTGCTL_DBCT                     GOTGCTL_DBCT_Msk                         // Long/short debounce time */
+#define GOTGCTL_DBCT_Msk                 (0x1UL << GOTGCTL_DBCT_Pos)              // 0x00020000
+#define GOTGCTL_DBCT                     GOTGCTL_DBCT_Msk                         // Long/short debounce time
 #define GOTGCTL_ASVLD_Pos                (18U)
-#define GOTGCTL_ASVLD_Msk                (0x1UL << GOTGCTL_ASVLD_Pos)             // 0x00040000 */
-#define GOTGCTL_ASVLD                    GOTGCTL_ASVLD_Msk                        // A-session valid  */
+#define GOTGCTL_ASVLD_Msk                (0x1UL << GOTGCTL_ASVLD_Pos)             // 0x00040000
+#define GOTGCTL_ASVLD                    GOTGCTL_ASVLD_Msk                        // A-session valid
 #define GOTGCTL_BSESVLD_Pos              (19U)
-#define GOTGCTL_BSESVLD_Msk              (0x1UL << GOTGCTL_BSESVLD_Pos)           // 0x00080000 */
-#define GOTGCTL_BSESVLD                  GOTGCTL_BSESVLD_Msk                      // B-session valid */
+#define GOTGCTL_BSESVLD_Msk              (0x1UL << GOTGCTL_BSESVLD_Pos)           // 0x00080000
+#define GOTGCTL_BSESVLD                  GOTGCTL_BSESVLD_Msk                      // B-session valid
 #define GOTGCTL_OTGVER_Pos               (20U)
-#define GOTGCTL_OTGVER_Msk               (0x1UL << GOTGCTL_OTGVER_Pos)            // 0x00100000 */
-#define GOTGCTL_OTGVER                   GOTGCTL_OTGVER_Msk                       // OTG version  */
+#define GOTGCTL_OTGVER_Msk               (0x1UL << GOTGCTL_OTGVER_Pos)            // 0x00100000
+#define GOTGCTL_OTGVER                   GOTGCTL_OTGVER_Msk                       // OTG version
 
 /********************  Bit definition for HCFG register  ********************/
-#define HCFG_FSLSPCS_Pos                 (0U)
-#define HCFG_FSLSPCS_Msk                 (0x3UL << HCFG_FSLSPCS_Pos)              // 0x00000003 */
-#define HCFG_FSLSPCS                     HCFG_FSLSPCS_Msk                         // FS/LS PHY clock select  */
-#define HCFG_FSLSPCS_0                   (0x1UL << HCFG_FSLSPCS_Pos)              // 0x00000001 */
-#define HCFG_FSLSPCS_1                   (0x2UL << HCFG_FSLSPCS_Pos)              // 0x00000002 */
-#define HCFG_FSLSS_Pos                   (2U)
-#define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos)                // 0x00000004 */
-#define HCFG_FSLSS                       HCFG_FSLSS_Msk                           // FS- and LS-only support */
+#define HCFG_FSLS_PHYCLK_SEL_Pos         (0U)
+#define HCFG_FSLS_PHYCLK_SEL_Msk         (0x3UL << HCFG_FSLS_PHYCLK_SEL_Pos)      // 0x00000003
+#define HCFG_FSLS_PHYCLK_SEL             HCFG_FSLS_PHYCLK_SEL_Msk                 // FS/LS PHY clock select
+#define HCFG_FSLS_PHYCLK_SEL_30_60MHZ    (0x0UL << HCFG_FSLS_PHYCLK_SEL_Pos)      // 0x00000000
+#define HCFG_FSLS_PHYCLK_SEL_48MHZ       (0x1UL << HCFG_FSLS_PHYCLK_SEL_Pos)      // 0x00000001
+#define HCFG_FSLS_PHYCLK_SEL_6MHZ        (0x2UL << HCFG_FSLS_PHYCLK_SEL_Pos)      // 0x00000002
+
+#define HCFG_FSLS_ONLY_Pos               (2U)
+#define HCFG_FSLS_ONLY_Msk               (0x1UL << HCFG_FSLS_ONLY_Pos)            // 0x00000004
+#define HCFG_FSLS_ONLY                   HCFG_FSLS_ONLY_Msk                       // FS- and LS-only support
 
 /********************  Bit definition for PCGCR register  ********************/
 #define PCGCR_STPPCLK_Pos                (0U)
-#define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos)             // 0x00000001 */
-#define PCGCR_STPPCLK                    PCGCR_STPPCLK_Msk                        // Stop PHY clock */
+#define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos)             // 0x00000001
+#define PCGCR_STPPCLK                    PCGCR_STPPCLK_Msk                        // Stop PHY clock
 #define PCGCR_GATEHCLK_Pos               (1U)
-#define PCGCR_GATEHCLK_Msk               (0x1UL << PCGCR_GATEHCLK_Pos)            // 0x00000002 */
-#define PCGCR_GATEHCLK                   PCGCR_GATEHCLK_Msk                       // Gate HCLK */
+#define PCGCR_GATEHCLK_Msk               (0x1UL << PCGCR_GATEHCLK_Pos)            // 0x00000002
+#define PCGCR_GATEHCLK                   PCGCR_GATEHCLK_Msk                       // Gate HCLK
 #define PCGCR_PHYSUSP_Pos                (4U)
-#define PCGCR_PHYSUSP_Msk                (0x1UL << PCGCR_PHYSUSP_Pos)             // 0x00000010 */
-#define PCGCR_PHYSUSP                    PCGCR_PHYSUSP_Msk                        // PHY suspended */
+#define PCGCR_PHYSUSP_Msk                (0x1UL << PCGCR_PHYSUSP_Pos)             // 0x00000010
+#define PCGCR_PHYSUSP                    PCGCR_PHYSUSP_Msk                        // PHY suspended
 
 /********************  Bit definition for GOTGINT register  ********************/
 #define GOTGINT_SEDET_Pos                (2U)
-#define GOTGINT_SEDET_Msk                (0x1UL << GOTGINT_SEDET_Pos)             // 0x00000004 */
-#define GOTGINT_SEDET                    GOTGINT_SEDET_Msk                        // Session end detected                   */
+#define GOTGINT_SEDET_Msk                (0x1UL << GOTGINT_SEDET_Pos)             // 0x00000004
+#define GOTGINT_SEDET                    GOTGINT_SEDET_Msk                        // Session end detected
 #define GOTGINT_SRSSCHG_Pos              (8U)
-#define GOTGINT_SRSSCHG_Msk              (0x1UL << GOTGINT_SRSSCHG_Pos)           // 0x00000100 */
-#define GOTGINT_SRSSCHG                  GOTGINT_SRSSCHG_Msk                      // Session request success status change  */
+#define GOTGINT_SRSSCHG_Msk              (0x1UL << GOTGINT_SRSSCHG_Pos)           // 0x00000100
+#define GOTGINT_SRSSCHG                  GOTGINT_SRSSCHG_Msk                      // Session request success status change
 #define GOTGINT_HNSSCHG_Pos              (9U)
-#define GOTGINT_HNSSCHG_Msk              (0x1UL << GOTGINT_HNSSCHG_Pos)           // 0x00000200 */
-#define GOTGINT_HNSSCHG                  GOTGINT_HNSSCHG_Msk                      // Host negotiation success status change */
+#define GOTGINT_HNSSCHG_Msk              (0x1UL << GOTGINT_HNSSCHG_Pos)           // 0x00000200
+#define GOTGINT_HNSSCHG                  GOTGINT_HNSSCHG_Msk                      // Host negotiation success status change
 #define GOTGINT_HNGDET_Pos               (17U)
-#define GOTGINT_HNGDET_Msk               (0x1UL << GOTGINT_HNGDET_Pos)            // 0x00020000 */
-#define GOTGINT_HNGDET                   GOTGINT_HNGDET_Msk                       // Host negotiation detected              */
+#define GOTGINT_HNGDET_Msk               (0x1UL << GOTGINT_HNGDET_Pos)            // 0x00020000
+#define GOTGINT_HNGDET                   GOTGINT_HNGDET_Msk                       // Host negotiation detected
 #define GOTGINT_ADTOCHG_Pos              (18U)
-#define GOTGINT_ADTOCHG_Msk              (0x1UL << GOTGINT_ADTOCHG_Pos)           // 0x00040000 */
-#define GOTGINT_ADTOCHG                  GOTGINT_ADTOCHG_Msk                      // A-device timeout change                */
+#define GOTGINT_ADTOCHG_Msk              (0x1UL << GOTGINT_ADTOCHG_Pos)           // 0x00040000
+#define GOTGINT_ADTOCHG                  GOTGINT_ADTOCHG_Msk                      // A-device timeout change
 #define GOTGINT_DBCDNE_Pos               (19U)
-#define GOTGINT_DBCDNE_Msk               (0x1UL << GOTGINT_DBCDNE_Pos)            // 0x00080000 */
-#define GOTGINT_DBCDNE                   GOTGINT_DBCDNE_Msk                       // Debounce done                          */
+#define GOTGINT_DBCDNE_Msk               (0x1UL << GOTGINT_DBCDNE_Pos)            // 0x00080000
+#define GOTGINT_DBCDNE                   GOTGINT_DBCDNE_Msk                       // Debounce done
 #define GOTGINT_IDCHNG_Pos               (20U)
-#define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos)            // 0x00100000 */
-#define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk                       // Change in ID pin input value           */
+#define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos)            // 0x00100000
+#define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk                       // Change in ID pin input value
 
 /********************  Bit definition for DCFG register  ********************/
 #define DCFG_DSPD_Pos                    (0U)
@@ -405,92 +912,95 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DCFG_DSPD_FS                     3    // Fullspeed on FS PHY
 
 #define DCFG_NZLSOHSK_Pos                (2U)
-#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             // 0x00000004 */
-#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        // Nonzero-length status OUT handshake */
+#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             // 0x00000004
+#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        // Nonzero-length status OUT handshake
 
 #define DCFG_DAD_Pos                     (4U)
-#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 // 0x000007F0 */
-#define DCFG_DAD                         DCFG_DAD_Msk                             // Device address */
-#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 // 0x00000010 */
-#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 // 0x00000020 */
-#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 // 0x00000040 */
-#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 // 0x00000080 */
-#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 // 0x00000100 */
-#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 // 0x00000200 */
-#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 // 0x00000400 */
+#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 // 0x000007F0
+#define DCFG_DAD                         DCFG_DAD_Msk                             // Device address
+#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 // 0x00000010
+#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 // 0x00000020
+#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 // 0x00000040
+#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 // 0x00000080
+#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 // 0x00000100
+#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 // 0x00000200
+#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 // 0x00000400
 
 #define DCFG_PFIVL_Pos                   (11U)
-#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                // 0x00001800 */
-#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           // Periodic (micro)frame interval */
-#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800 */
-#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000 */
+#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                // 0x00001800
+#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           // Periodic (micro)frame interval
+#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800
+#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000
 
 #define DCFG_XCVRDLY_Pos                 (14U)
-#define DCFG_XCVRDLY_Msk                 (0x1UL << DCFG_XCVRDLY_Pos)             /*!< 0x00004000 */
+#define DCFG_XCVRDLY_Msk                 (0x1UL << DCFG_XCVRDLY_Pos)             // 0x00004000
 #define DCFG_XCVRDLY                     DCFG_XCVRDLY_Msk                        // Enables delay between xcvr_sel and txvalid during device chirp
 
 #define DCFG_PERSCHIVL_Pos               (24U)
-#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000 */
-#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval */
-#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            // 0x01000000 */
-#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            // 0x02000000 */
+#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000
+#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval
+#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            // 0x01000000
+#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            // 0x02000000
 
 /********************  Bit definition for DCTL register  ********************/
 #define DCTL_RWUSIG_Pos                  (0U)
-#define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos)               // 0x00000001 */
-#define DCTL_RWUSIG                      DCTL_RWUSIG_Msk                          // Remote wakeup signaling */
+#define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos)               // 0x00000001
+#define DCTL_RWUSIG                      DCTL_RWUSIG_Msk                          // Remote wakeup signaling
 #define DCTL_SDIS_Pos                    (1U)
-#define DCTL_SDIS_Msk                    (0x1UL << DCTL_SDIS_Pos)                 // 0x00000002 */
-#define DCTL_SDIS                        DCTL_SDIS_Msk                            // Soft disconnect         */
+#define DCTL_SDIS_Msk                    (0x1UL << DCTL_SDIS_Pos)                 // 0x00000002
+#define DCTL_SDIS                        DCTL_SDIS_Msk                            // Soft disconnect
 #define DCTL_GINSTS_Pos                  (2U)
-#define DCTL_GINSTS_Msk                  (0x1UL << DCTL_GINSTS_Pos)               // 0x00000004 */
-#define DCTL_GINSTS                      DCTL_GINSTS_Msk                          // Global IN NAK status    */
+#define DCTL_GINSTS_Msk                  (0x1UL << DCTL_GINSTS_Pos)               // 0x00000004
+#define DCTL_GINSTS                      DCTL_GINSTS_Msk                          // Global IN NAK status
 #define DCTL_GONSTS_Pos                  (3U)
-#define DCTL_GONSTS_Msk                  (0x1UL << DCTL_GONSTS_Pos)               // 0x00000008 */
-#define DCTL_GONSTS                      DCTL_GONSTS_Msk                          // Global OUT NAK status   */
+#define DCTL_GONSTS_Msk                  (0x1UL << DCTL_GONSTS_Pos)               // 0x00000008
+#define DCTL_GONSTS                      DCTL_GONSTS_Msk                          // Global OUT NAK status
 
 #define DCTL_TCTL_Pos                    (4U)
-#define DCTL_TCTL_Msk                    (0x7UL << DCTL_TCTL_Pos)                 // 0x00000070 */
-#define DCTL_TCTL                        DCTL_TCTL_Msk                            // Test control */
-#define DCTL_TCTL_0                      (0x1UL << DCTL_TCTL_Pos)                 // 0x00000010 */
-#define DCTL_TCTL_1                      (0x2UL << DCTL_TCTL_Pos)                 // 0x00000020 */
-#define DCTL_TCTL_2                      (0x4UL << DCTL_TCTL_Pos)                 // 0x00000040 */
+#define DCTL_TCTL_Msk                    (0x7UL << DCTL_TCTL_Pos)                 // 0x00000070
+#define DCTL_TCTL                        DCTL_TCTL_Msk                            // Test control
+#define DCTL_TCTL_0                      (0x1UL << DCTL_TCTL_Pos)                 // 0x00000010
+#define DCTL_TCTL_1                      (0x2UL << DCTL_TCTL_Pos)                 // 0x00000020
+#define DCTL_TCTL_2                      (0x4UL << DCTL_TCTL_Pos)                 // 0x00000040
 #define DCTL_SGINAK_Pos                  (7U)
-#define DCTL_SGINAK_Msk                  (0x1UL << DCTL_SGINAK_Pos)               // 0x00000080 */
-#define DCTL_SGINAK                      DCTL_SGINAK_Msk                          // Set global IN NAK         */
+#define DCTL_SGINAK_Msk                  (0x1UL << DCTL_SGINAK_Pos)               // 0x00000080
+#define DCTL_SGINAK                      DCTL_SGINAK_Msk                          // Set global IN NAK
 #define DCTL_CGINAK_Pos                  (8U)
-#define DCTL_CGINAK_Msk                  (0x1UL << DCTL_CGINAK_Pos)               // 0x00000100 */
-#define DCTL_CGINAK                      DCTL_CGINAK_Msk                          // Clear global IN NAK       */
+#define DCTL_CGINAK_Msk                  (0x1UL << DCTL_CGINAK_Pos)               // 0x00000100
+#define DCTL_CGINAK                      DCTL_CGINAK_Msk                          // Clear global IN NAK
 #define DCTL_SGONAK_Pos                  (9U)
-#define DCTL_SGONAK_Msk                  (0x1UL << DCTL_SGONAK_Pos)               // 0x00000200 */
-#define DCTL_SGONAK                      DCTL_SGONAK_Msk                          // Set global OUT NAK        */
+#define DCTL_SGONAK_Msk                  (0x1UL << DCTL_SGONAK_Pos)               // 0x00000200
+#define DCTL_SGONAK                      DCTL_SGONAK_Msk                          // Set global OUT NAK
 #define DCTL_CGONAK_Pos                  (10U)
-#define DCTL_CGONAK_Msk                  (0x1UL << DCTL_CGONAK_Pos)               // 0x00000400 */
-#define DCTL_CGONAK                      DCTL_CGONAK_Msk                          // Clear global OUT NAK      */
+#define DCTL_CGONAK_Msk                  (0x1UL << DCTL_CGONAK_Pos)               // 0x00000400
+#define DCTL_CGONAK                      DCTL_CGONAK_Msk                          // Clear global OUT NAK
 #define DCTL_POPRGDNE_Pos                (11U)
-#define DCTL_POPRGDNE_Msk                (0x1UL << DCTL_POPRGDNE_Pos)             // 0x00000800 */
-#define DCTL_POPRGDNE                    DCTL_POPRGDNE_Msk                        // Power-on programming done */
+#define DCTL_POPRGDNE_Msk                (0x1UL << DCTL_POPRGDNE_Pos)             // 0x00000800
+#define DCTL_POPRGDNE                    DCTL_POPRGDNE_Msk                        // Power-on programming done
 
 /********************  Bit definition for HFIR register  ********************/
 #define HFIR_FRIVL_Pos                   (0U)
-#define HFIR_FRIVL_Msk                   (0xFFFFUL << HFIR_FRIVL_Pos)             // 0x0000FFFF */
-#define HFIR_FRIVL                       HFIR_FRIVL_Msk                           // Frame interval */
+#define HFIR_FRIVL_Msk                   (0xFFFFUL << HFIR_FRIVL_Pos)             // 0x0000FFFF
+#define HFIR_FRIVL                       HFIR_FRIVL_Msk                           // Frame interval
+#define HFIR_RELOAD_CTRL_Pos             (16U)                                    // available since v2.92a
+#define HFIR_RELOAD_CTRL_Msk             (0x1UL << HFIR_RELOAD_CTRL_Pos)
+#define HFIR_RELOAD_CTRL                  HFIR_RELOAD_CTRL_Msk
 
 /********************  Bit definition for HFNUM register  ********************/
 #define HFNUM_FRNUM_Pos                  (0U)
-#define HFNUM_FRNUM_Msk                  (0xFFFFUL << HFNUM_FRNUM_Pos)            // 0x0000FFFF */
-#define HFNUM_FRNUM                      HFNUM_FRNUM_Msk                          // Frame number         */
+#define HFNUM_FRNUM_Msk                  (0xFFFFUL << HFNUM_FRNUM_Pos)            // 0x0000FFFF
+#define HFNUM_FRNUM                      HFNUM_FRNUM_Msk                          // Frame number
 #define HFNUM_FTREM_Pos                  (16U)
-#define HFNUM_FTREM_Msk                  (0xFFFFUL << HFNUM_FTREM_Pos)            // 0xFFFF0000 */
-#define HFNUM_FTREM                      HFNUM_FTREM_Msk                          // Frame time remaining */
+#define HFNUM_FTREM_Msk                  (0xFFFFUL << HFNUM_FTREM_Pos)            // 0xFFFF0000
+#define HFNUM_FTREM                      HFNUM_FTREM_Msk                          // Frame time remaining
 
 /********************  Bit definition for DSTS register  ********************/
 #define DSTS_SUSPSTS_Pos                 (0U)
-#define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos)              // 0x00000001 */
-#define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk                         // Suspend status   */
+#define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos)              // 0x00000001
+#define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk                         // Suspend status
 #define DSTS_ENUMSPD_Pos                 (1U)
-#define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos)              // 0x00000006 */
-#define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk                         // Enumerated speed */
+#define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos)              // 0x00000006
+#define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk                         // Enumerated speed
 #define DSTS_ENUMSPD_HS                  0    // Highspeed
 #define DSTS_ENUMSPD_FS_HSPHY            1    // Fullspeed on HS PHY
 #define DSTS_ENUMSPD_LS                  2    // Lowspeed
@@ -498,1236 +1008,1274 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 
 #define DSTS_EERR_Pos                    (3U)
-#define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos)                 // 0x00000008 */
-#define DSTS_EERR                        DSTS_EERR_Msk                            // Erratic error     */
+#define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos)                 // 0x00000008
+#define DSTS_EERR                        DSTS_EERR_Msk                            // Erratic error
 #define DSTS_FNSOF_Pos                   (8U)
-#define DSTS_FNSOF_Msk                   (0x3FFFUL << DSTS_FNSOF_Pos)             // 0x003FFF00 */
-#define DSTS_FNSOF                       DSTS_FNSOF_Msk                           // Frame number of the received SOF */
+#define DSTS_FNSOF_Msk                   (0x3FFFUL << DSTS_FNSOF_Pos)             // 0x003FFF00
+#define DSTS_FNSOF                       DSTS_FNSOF_Msk                           // Frame number of the received SOF
 
 /********************  Bit definition for GAHBCFG register  ********************/
 #define GAHBCFG_GINT_Pos                 (0U)
-#define GAHBCFG_GINT_Msk                 (0x1UL << GAHBCFG_GINT_Pos)              // 0x00000001 */
-#define GAHBCFG_GINT                     GAHBCFG_GINT_Msk                         // Global interrupt mask */
+#define GAHBCFG_GINT_Msk                 (0x1UL << GAHBCFG_GINT_Pos)              // 0x00000001
+#define GAHBCFG_GINT                     GAHBCFG_GINT_Msk                         // Global interrupt mask
 #define GAHBCFG_HBSTLEN_Pos              (1U)
-#define GAHBCFG_HBSTLEN_Msk              (0xFUL << GAHBCFG_HBSTLEN_Pos)           // 0x0000001E */
-#define GAHBCFG_HBSTLEN                  GAHBCFG_HBSTLEN_Msk                      // Burst length/type */
-#define GAHBCFG_HBSTLEN_0                (0x0UL << GAHBCFG_HBSTLEN_Pos)           // Single */
-#define GAHBCFG_HBSTLEN_1                (0x1UL << GAHBCFG_HBSTLEN_Pos)           // INCR */
-#define GAHBCFG_HBSTLEN_2                (0x3UL << GAHBCFG_HBSTLEN_Pos)           // INCR4 */
-#define GAHBCFG_HBSTLEN_3                (0x5UL << GAHBCFG_HBSTLEN_Pos)           // INCR8 */
-#define GAHBCFG_HBSTLEN_4                (0x7UL << GAHBCFG_HBSTLEN_Pos)           // INCR16 */
+#define GAHBCFG_HBSTLEN_Msk              (0xFUL << GAHBCFG_HBSTLEN_Pos)           // 0x0000001E
+#define GAHBCFG_HBSTLEN                  GAHBCFG_HBSTLEN_Msk                      // Burst length/type
+#define GAHBCFG_HBSTLEN_0                (0x0UL << GAHBCFG_HBSTLEN_Pos)           // Single
+#define GAHBCFG_HBSTLEN_1                (0x1UL << GAHBCFG_HBSTLEN_Pos)           // INCR
+#define GAHBCFG_HBSTLEN_2                (0x3UL << GAHBCFG_HBSTLEN_Pos)           // INCR4
+#define GAHBCFG_HBSTLEN_3                (0x5UL << GAHBCFG_HBSTLEN_Pos)           // INCR8
+#define GAHBCFG_HBSTLEN_4                (0x7UL << GAHBCFG_HBSTLEN_Pos)           // INCR16
 #define GAHBCFG_DMAEN_Pos                (5U)
-#define GAHBCFG_DMAEN_Msk                (0x1UL << GAHBCFG_DMAEN_Pos)             // 0x00000020 */
-#define GAHBCFG_DMAEN                    GAHBCFG_DMAEN_Msk                        // DMA enable */
-#define GAHBCFG_TXFELVL_Pos              (7U)
-#define GAHBCFG_TXFELVL_Msk              (0x1UL << GAHBCFG_TXFELVL_Pos)           // 0x00000080 */
-#define GAHBCFG_TXFELVL                  GAHBCFG_TXFELVL_Msk                      // TxFIFO empty level */
-#define GAHBCFG_PTXFELVL_Pos             (8U)
-#define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          // 0x00000100 */
-#define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     // Periodic TxFIFO empty level */
-
-#define GSNPSID_ID_MASK                 TU_GENMASK(31, 16)
+#define GAHBCFG_DMAEN_Msk                (0x1UL << GAHBCFG_DMAEN_Pos)             // 0x00000020
+#define GAHBCFG_DMAEN                    GAHBCFG_DMAEN_Msk                        // DMA enable
+#define GAHBCFG_TX_FIFO_EPMTY_LVL_Pos    (7U)
+#define GAHBCFG_TX_FIFO_EPMTY_LVL_Msk    (0x1UL << GAHBCFG_TX_FIFO_EPMTY_LVL_Pos) // 0x00000080
+#define GAHBCFG_TX_FIFO_EPMTY_LVL        GAHBCFG_TX_FIFO_EPMTY_LVL_Msk            // TxFIFO empty level
+#define GAHBCFG_PTX_FIFO_EPMTY_LVL_Pos   (8U)
+#define GAHBCFG_PTX_FIFO_EPMTY_LVL_Msk   (0x1UL << GAHBCFG_PTX_FIFO_EPMTY_LVL_Pos) // 0x00000100
+#define GAHBCFG_PTX_FIFO_EPMTY_LVL       GAHBCFG_PTX_FIFO_EPMTY_LVL_Msk            // Periodic TxFIFO empty level
 
 /********************  Bit definition for GUSBCFG register  ********************/
 #define GUSBCFG_TOCAL_Pos                (0U)
-#define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             // 0x00000007 */
-#define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk                        // FS timeout calibration */
+#define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             // 0x00000007
+#define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk                        // HS/FS timeout calibration
 #define GUSBCFG_PHYIF16_Pos              (3U)
-#define GUSBCFG_PHYIF16_Msk              (0x1UL << GUSBCFG_PHYIF16_Pos)             // 0x00000008 */
-#define GUSBCFG_PHYIF16                  GUSBCFG_PHYIF16_Msk                        // PHY Interface (PHYIf) */
+#define GUSBCFG_PHYIF16_Msk              (0x1UL << GUSBCFG_PHYIF16_Pos)           // 0x00000008
+#define GUSBCFG_PHYIF16                  GUSBCFG_PHYIF16_Msk                      // PHY Interface (PHYIf)
 #define GUSBCFG_ULPI_UTMI_SEL_Pos        (4U)
-#define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos)     // 0x00000010 */
-#define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk                // ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
+#define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos)     // 0x00000010
+#define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk                // ULPI or UTMI+ Select (ULPI_UTMI_Sel)
 #define GUSBCFG_PHYSEL_Pos               (6U)
-#define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040 */
-#define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040
+#define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
 #define GUSBCFG_DDRSEL                   TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
 #define GUSBCFG_SRPCAP_Pos               (8U)
-#define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100 */
-#define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable */
+#define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100
+#define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable
 #define GUSBCFG_HNPCAP_Pos               (9U)
-#define GUSBCFG_HNPCAP_Msk               (0x1UL << GUSBCFG_HNPCAP_Pos)            // 0x00000200 */
-#define GUSBCFG_HNPCAP                   GUSBCFG_HNPCAP_Msk                       // HNP-capable */
+#define GUSBCFG_HNPCAP_Msk               (0x1UL << GUSBCFG_HNPCAP_Pos)            // 0x00000200
+#define GUSBCFG_HNPCAP                   GUSBCFG_HNPCAP_Msk                       // HNP-capable
 #define GUSBCFG_TRDT_Pos                 (10U)
-#define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos)              // 0x00003C00 */
-#define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk                         // USB turnaround time */
+#define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos)              // 0x00003C00
+#define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk                         // USB turnaround time
 #define GUSBCFG_PHYLPCS_Pos              (15U)
-#define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos)           // 0x00008000 */
-#define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk                      // PHY Low-power clock select */
+#define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos)           // 0x00008000
+#define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk                      // PHY Low-power clock select
 #define GUSBCFG_ULPIFSLS_Pos             (17U)
-#define GUSBCFG_ULPIFSLS_Msk             (0x1UL << GUSBCFG_ULPIFSLS_Pos)          // 0x00020000 */
-#define GUSBCFG_ULPIFSLS                 GUSBCFG_ULPIFSLS_Msk                     // ULPI FS/LS select               */
+#define GUSBCFG_ULPIFSLS_Msk             (0x1UL << GUSBCFG_ULPIFSLS_Pos)          // 0x00020000
+#define GUSBCFG_ULPIFSLS                 GUSBCFG_ULPIFSLS_Msk                     // ULPI FS/LS select
 #define GUSBCFG_ULPIAR_Pos               (18U)
-#define GUSBCFG_ULPIAR_Msk               (0x1UL << GUSBCFG_ULPIAR_Pos)            // 0x00040000 */
-#define GUSBCFG_ULPIAR                   GUSBCFG_ULPIAR_Msk                       // ULPI Auto-resume                */
+#define GUSBCFG_ULPIAR_Msk               (0x1UL << GUSBCFG_ULPIAR_Pos)            // 0x00040000
+#define GUSBCFG_ULPIAR                   GUSBCFG_ULPIAR_Msk                       // ULPI Auto-resume
 #define GUSBCFG_ULPICSM_Pos              (19U)
-#define GUSBCFG_ULPICSM_Msk              (0x1UL << GUSBCFG_ULPICSM_Pos)           // 0x00080000 */
-#define GUSBCFG_ULPICSM                  GUSBCFG_ULPICSM_Msk                      // ULPI Clock SuspendM             */
+#define GUSBCFG_ULPICSM_Msk              (0x1UL << GUSBCFG_ULPICSM_Pos)           // 0x00080000
+#define GUSBCFG_ULPICSM                  GUSBCFG_ULPICSM_Msk                      // ULPI Clock SuspendM
 #define GUSBCFG_ULPIEVBUSD_Pos           (20U)
-#define GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << GUSBCFG_ULPIEVBUSD_Pos)        // 0x00100000 */
-#define GUSBCFG_ULPIEVBUSD               GUSBCFG_ULPIEVBUSD_Msk                   // ULPI External VBUS Drive        */
+#define GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << GUSBCFG_ULPIEVBUSD_Pos)        // 0x00100000
+#define GUSBCFG_ULPIEVBUSD               GUSBCFG_ULPIEVBUSD_Msk                   // ULPI External VBUS Drive
 #define GUSBCFG_ULPIEVBUSI_Pos           (21U)
-#define GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << GUSBCFG_ULPIEVBUSI_Pos)        // 0x00200000 */
-#define GUSBCFG_ULPIEVBUSI               GUSBCFG_ULPIEVBUSI_Msk                   // ULPI external VBUS indicator    */
+#define GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << GUSBCFG_ULPIEVBUSI_Pos)        // 0x00200000
+#define GUSBCFG_ULPIEVBUSI               GUSBCFG_ULPIEVBUSI_Msk                   // ULPI external VBUS indicator
 #define GUSBCFG_TSDPS_Pos                (22U)
-#define GUSBCFG_TSDPS_Msk                (0x1UL << GUSBCFG_TSDPS_Pos)             // 0x00400000 */
-#define GUSBCFG_TSDPS                    GUSBCFG_TSDPS_Msk                        // TermSel DLine pulsing selection */
+#define GUSBCFG_TSDPS_Msk                (0x1UL << GUSBCFG_TSDPS_Pos)             // 0x00400000
+#define GUSBCFG_TSDPS                    GUSBCFG_TSDPS_Msk                        // TermSel DLine pulsing selection
 #define GUSBCFG_PCCI_Pos                 (23U)
-#define GUSBCFG_PCCI_Msk                 (0x1UL << GUSBCFG_PCCI_Pos)              // 0x00800000 */
-#define GUSBCFG_PCCI                     GUSBCFG_PCCI_Msk                         // Indicator complement            */
+#define GUSBCFG_PCCI_Msk                 (0x1UL << GUSBCFG_PCCI_Pos)              // 0x00800000
+#define GUSBCFG_PCCI                     GUSBCFG_PCCI_Msk                         // Indicator complement
 #define GUSBCFG_PTCI_Pos                 (24U)
-#define GUSBCFG_PTCI_Msk                 (0x1UL << GUSBCFG_PTCI_Pos)              // 0x01000000 */
-#define GUSBCFG_PTCI                     GUSBCFG_PTCI_Msk                         // Indicator pass through          */
+#define GUSBCFG_PTCI_Msk                 (0x1UL << GUSBCFG_PTCI_Pos)              // 0x01000000
+#define GUSBCFG_PTCI                     GUSBCFG_PTCI_Msk                         // Indicator pass through
 #define GUSBCFG_ULPIIPD_Pos              (25U)
-#define GUSBCFG_ULPIIPD_Msk              (0x1UL << GUSBCFG_ULPIIPD_Pos)           // 0x02000000 */
-#define GUSBCFG_ULPIIPD                  GUSBCFG_ULPIIPD_Msk                      // ULPI interface protect disable  */
+#define GUSBCFG_ULPIIPD_Msk              (0x1UL << GUSBCFG_ULPIIPD_Pos)           // 0x02000000
+#define GUSBCFG_ULPIIPD                  GUSBCFG_ULPIIPD_Msk                      // ULPI interface protect disable
 #define GUSBCFG_FHMOD_Pos                (29U)
-#define GUSBCFG_FHMOD_Msk                (0x1UL << GUSBCFG_FHMOD_Pos)             // 0x20000000 */
-#define GUSBCFG_FHMOD                    GUSBCFG_FHMOD_Msk                        // Forced host mode                */
+#define GUSBCFG_FHMOD_Msk                (0x1UL << GUSBCFG_FHMOD_Pos)             // 0x20000000
+#define GUSBCFG_FHMOD                    GUSBCFG_FHMOD_Msk                        // Forced host mode
 #define GUSBCFG_FDMOD_Pos                (30U)
-#define GUSBCFG_FDMOD_Msk                (0x1UL << GUSBCFG_FDMOD_Pos)             // 0x40000000 */
-#define GUSBCFG_FDMOD                    GUSBCFG_FDMOD_Msk                        // Forced peripheral mode          */
+#define GUSBCFG_FDMOD_Msk                (0x1UL << GUSBCFG_FDMOD_Pos)             // 0x40000000
+#define GUSBCFG_FDMOD                    GUSBCFG_FDMOD_Msk                        // Forced peripheral mode
 #define GUSBCFG_CTXPKT_Pos               (31U)
-#define GUSBCFG_CTXPKT_Msk               (0x1UL << GUSBCFG_CTXPKT_Pos)            // 0x80000000 */
-#define GUSBCFG_CTXPKT                   GUSBCFG_CTXPKT_Msk                       // Corrupt Tx packet               */
+#define GUSBCFG_CTXPKT_Msk               (0x1UL << GUSBCFG_CTXPKT_Pos)            // 0x80000000
+#define GUSBCFG_CTXPKT                   GUSBCFG_CTXPKT_Msk                       // Corrupt Tx packet
 
 /********************  Bit definition for GRSTCTL register  ********************/
 #define GRSTCTL_CSRST_Pos                (0U)
-#define GRSTCTL_CSRST_Msk                (0x1UL << GRSTCTL_CSRST_Pos)             // 0x00000001 */
-#define GRSTCTL_CSRST                    GRSTCTL_CSRST_Msk                        // Core soft reset          */
+#define GRSTCTL_CSRST_Msk                (0x1UL << GRSTCTL_CSRST_Pos)             // 0x00000001
+#define GRSTCTL_CSRST                    GRSTCTL_CSRST_Msk                        // Core soft reset
 #define GRSTCTL_HSRST_Pos                (1U)
-#define GRSTCTL_HSRST_Msk                (0x1UL << GRSTCTL_HSRST_Pos)             // 0x00000002 */
-#define GRSTCTL_HSRST                    GRSTCTL_HSRST_Msk                        // HCLK soft reset          */
+#define GRSTCTL_HSRST_Msk                (0x1UL << GRSTCTL_HSRST_Pos)             // 0x00000002
+#define GRSTCTL_HSRST                    GRSTCTL_HSRST_Msk                        // HCLK soft reset
 #define GRSTCTL_FCRST_Pos                (2U)
-#define GRSTCTL_FCRST_Msk                (0x1UL << GRSTCTL_FCRST_Pos)             // 0x00000004 */
-#define GRSTCTL_FCRST                    GRSTCTL_FCRST_Msk                        // Host frame counter reset */
+#define GRSTCTL_FCRST_Msk                (0x1UL << GRSTCTL_FCRST_Pos)             // 0x00000004
+#define GRSTCTL_FCRST                    GRSTCTL_FCRST_Msk                        // Host frame counter reset
 #define GRSTCTL_RXFFLSH_Pos              (4U)
-#define GRSTCTL_RXFFLSH_Msk              (0x1UL << GRSTCTL_RXFFLSH_Pos)           // 0x00000010 */
-#define GRSTCTL_RXFFLSH                  GRSTCTL_RXFFLSH_Msk                      // RxFIFO flush             */
+#define GRSTCTL_RXFFLSH_Msk              (0x1UL << GRSTCTL_RXFFLSH_Pos)           // 0x00000010
+#define GRSTCTL_RXFFLSH                  GRSTCTL_RXFFLSH_Msk                      // RxFIFO flush
 #define GRSTCTL_TXFFLSH_Pos              (5U)
-#define GRSTCTL_TXFFLSH_Msk              (0x1UL << GRSTCTL_TXFFLSH_Pos)           // 0x00000020 */
-#define GRSTCTL_TXFFLSH                  GRSTCTL_TXFFLSH_Msk                      // TxFIFO flush             */
+#define GRSTCTL_TXFFLSH_Msk              (0x1UL << GRSTCTL_TXFFLSH_Pos)           // 0x00000020
+#define GRSTCTL_TXFFLSH                  GRSTCTL_TXFFLSH_Msk                      // TxFIFO flush
 #define GRSTCTL_TXFNUM_Pos               (6U)
-#define GRSTCTL_TXFNUM_Msk               (0x1FUL << GRSTCTL_TXFNUM_Pos)           // 0x000007C0 */
-#define GRSTCTL_TXFNUM                   GRSTCTL_TXFNUM_Msk                       // TxFIFO number */
-#define GRSTCTL_TXFNUM_0                 (0x01UL << GRSTCTL_TXFNUM_Pos)           // 0x00000040 */
-#define GRSTCTL_TXFNUM_1                 (0x02UL << GRSTCTL_TXFNUM_Pos)           // 0x00000080 */
-#define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           // 0x00000100 */
-#define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           // 0x00000200 */
-#define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           // 0x00000400 */
-#define GRSTCTL_CSFTRST_DONE_Pos       (29)
-#define GRSTCTL_CSFTRST_DONE           (1u << GRSTCTL_CSFTRST_DONE_Pos)         // Reset Done, only available from v4.20a
+#define GRSTCTL_TXFNUM_Msk               (0x1FUL << GRSTCTL_TXFNUM_Pos)           // 0x000007C0
+#define GRSTCTL_TXFNUM                   GRSTCTL_TXFNUM_Msk                       // TxFIFO number
+#define GRSTCTL_TXFNUM_0                 (0x01UL << GRSTCTL_TXFNUM_Pos)           // 0x00000040
+#define GRSTCTL_TXFNUM_1                 (0x02UL << GRSTCTL_TXFNUM_Pos)           // 0x00000080
+#define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           // 0x00000100
+#define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           // 0x00000200
+#define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           // 0x00000400
+#define GRSTCTL_CSRST_DONE_Pos           (29)
+#define GRSTCTL_CSRST_DONE               (1u << GRSTCTL_CSRST_DONE_Pos)         // Reset Done, only available from v4.20a
 #define GRSTCTL_DMAREQ_Pos               (30U)
-#define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            // 0x40000000 */
-#define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       // DMA request signal */
+#define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            // 0x40000000
+#define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       // DMA request signal
 #define GRSTCTL_AHBIDL_Pos               (31U)
-#define GRSTCTL_AHBIDL_Msk               (0x1UL << GRSTCTL_AHBIDL_Pos)            // 0x80000000 */
-#define GRSTCTL_AHBIDL                   GRSTCTL_AHBIDL_Msk                       // AHB master idle */
+#define GRSTCTL_AHBIDL_Msk               (0x1UL << GRSTCTL_AHBIDL_Pos)            // 0x80000000
+#define GRSTCTL_AHBIDL                   GRSTCTL_AHBIDL_Msk                       // AHB master idle
 
 /********************  Bit definition for DIEPMSK register  ********************/
 #define DIEPMSK_XFRCM_Pos                (0U)
-#define DIEPMSK_XFRCM_Msk                (0x1UL << DIEPMSK_XFRCM_Pos)             // 0x00000001 */
-#define DIEPMSK_XFRCM                    DIEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask                 */
+#define DIEPMSK_XFRCM_Msk                (0x1UL << DIEPMSK_XFRCM_Pos)             // 0x00000001
+#define DIEPMSK_XFRCM                    DIEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask
 #define DIEPMSK_EPDM_Pos                 (1U)
-#define DIEPMSK_EPDM_Msk                 (0x1UL << DIEPMSK_EPDM_Pos)              // 0x00000002 */
-#define DIEPMSK_EPDM                     DIEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask                  */
+#define DIEPMSK_EPDM_Msk                 (0x1UL << DIEPMSK_EPDM_Pos)              // 0x00000002
+#define DIEPMSK_EPDM                     DIEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask
 #define DIEPMSK_TOM_Pos                  (3U)
-#define DIEPMSK_TOM_Msk                  (0x1UL << DIEPMSK_TOM_Pos)               // 0x00000008 */
-#define DIEPMSK_TOM                      DIEPMSK_TOM_Msk                          // Timeout condition mask (nonisochronous endpoints) */
+#define DIEPMSK_TOM_Msk                  (0x1UL << DIEPMSK_TOM_Pos)               // 0x00000008
+#define DIEPMSK_TOM                      DIEPMSK_TOM_Msk                          // Timeout condition mask (nonisochronous endpoints)
 #define DIEPMSK_ITTXFEMSK_Pos            (4U)
-#define DIEPMSK_ITTXFEMSK_Msk            (0x1UL << DIEPMSK_ITTXFEMSK_Pos)         // 0x00000010 */
-#define DIEPMSK_ITTXFEMSK                DIEPMSK_ITTXFEMSK_Msk                    // IN token received when TxFIFO empty mask          */
+#define DIEPMSK_ITTXFEMSK_Msk            (0x1UL << DIEPMSK_ITTXFEMSK_Pos)         // 0x00000010
+#define DIEPMSK_ITTXFEMSK                DIEPMSK_ITTXFEMSK_Msk                    // IN token received when TxFIFO empty mask
 #define DIEPMSK_INEPNMM_Pos              (5U)
-#define DIEPMSK_INEPNMM_Msk              (0x1UL << DIEPMSK_INEPNMM_Pos)           // 0x00000020 */
-#define DIEPMSK_INEPNMM                  DIEPMSK_INEPNMM_Msk                      // IN token received with EP mismatch mask           */
+#define DIEPMSK_INEPNMM_Msk              (0x1UL << DIEPMSK_INEPNMM_Pos)           // 0x00000020
+#define DIEPMSK_INEPNMM                  DIEPMSK_INEPNMM_Msk                      // IN token received with EP mismatch mask
 #define DIEPMSK_INEPNEM_Pos              (6U)
-#define DIEPMSK_INEPNEM_Msk              (0x1UL << DIEPMSK_INEPNEM_Pos)           // 0x00000040 */
-#define DIEPMSK_INEPNEM                  DIEPMSK_INEPNEM_Msk                      // IN endpoint NAK effective mask                    */
+#define DIEPMSK_INEPNEM_Msk              (0x1UL << DIEPMSK_INEPNEM_Pos)           // 0x00000040
+#define DIEPMSK_INEPNEM                  DIEPMSK_INEPNEM_Msk                      // IN endpoint NAK effective mask
 #define DIEPMSK_TXFURM_Pos               (8U)
-#define DIEPMSK_TXFURM_Msk               (0x1UL << DIEPMSK_TXFURM_Pos)            // 0x00000100 */
-#define DIEPMSK_TXFURM                   DIEPMSK_TXFURM_Msk                       // FIFO underrun mask                                */
+#define DIEPMSK_TXFURM_Msk               (0x1UL << DIEPMSK_TXFURM_Pos)            // 0x00000100
+#define DIEPMSK_TXFURM                   DIEPMSK_TXFURM_Msk                       // FIFO underrun mask
 #define DIEPMSK_BIM_Pos                  (9U)
-#define DIEPMSK_BIM_Msk                  (0x1UL << DIEPMSK_BIM_Pos)               // 0x00000200 */
-#define DIEPMSK_BIM                      DIEPMSK_BIM_Msk                          // BNA interrupt mask                                */
+#define DIEPMSK_BIM_Msk                  (0x1UL << DIEPMSK_BIM_Pos)               // 0x00000200
+#define DIEPMSK_BIM                      DIEPMSK_BIM_Msk                          // BNA interrupt mask
 
 /********************  Bit definition for HPTXSTS register  ********************/
 #define HPTXSTS_PTXFSAVL_Pos             (0U)
-#define HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos)       // 0x0000FFFF */
-#define HPTXSTS_PTXFSAVL                 HPTXSTS_PTXFSAVL_Msk                     // Periodic transmit data FIFO space available     */
+#define HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos)       // 0x0000FFFF
+#define HPTXSTS_PTXFSAVL                 HPTXSTS_PTXFSAVL_Msk                     // Periodic transmit data FIFO space available
 #define HPTXSTS_PTXQSAV_Pos              (16U)
-#define HPTXSTS_PTXQSAV_Msk              (0xFFUL << HPTXSTS_PTXQSAV_Pos)          // 0x00FF0000 */
-#define HPTXSTS_PTXQSAV                  HPTXSTS_PTXQSAV_Msk                      // Periodic transmit request queue space available */
-#define HPTXSTS_PTXQSAV_0                (0x01UL << HPTXSTS_PTXQSAV_Pos)          // 0x00010000 */
-#define HPTXSTS_PTXQSAV_1                (0x02UL << HPTXSTS_PTXQSAV_Pos)          // 0x00020000 */
-#define HPTXSTS_PTXQSAV_2                (0x04UL << HPTXSTS_PTXQSAV_Pos)          // 0x00040000 */
-#define HPTXSTS_PTXQSAV_3                (0x08UL << HPTXSTS_PTXQSAV_Pos)          // 0x00080000 */
-#define HPTXSTS_PTXQSAV_4                (0x10UL << HPTXSTS_PTXQSAV_Pos)          // 0x00100000 */
-#define HPTXSTS_PTXQSAV_5                (0x20UL << HPTXSTS_PTXQSAV_Pos)          // 0x00200000 */
-#define HPTXSTS_PTXQSAV_6                (0x40UL << HPTXSTS_PTXQSAV_Pos)          // 0x00400000 */
-#define HPTXSTS_PTXQSAV_7                (0x80UL << HPTXSTS_PTXQSAV_Pos)          // 0x00800000 */
+#define HPTXSTS_PTXQSAV_Msk              (0xFFUL << HPTXSTS_PTXQSAV_Pos)          // 0x00FF0000
+#define HPTXSTS_PTXQSAV                  HPTXSTS_PTXQSAV_Msk                      // Periodic transmit request queue space available
+#define HPTXSTS_PTXQSAV_0                (0x01UL << HPTXSTS_PTXQSAV_Pos)          // 0x00010000
+#define HPTXSTS_PTXQSAV_1                (0x02UL << HPTXSTS_PTXQSAV_Pos)          // 0x00020000
+#define HPTXSTS_PTXQSAV_2                (0x04UL << HPTXSTS_PTXQSAV_Pos)          // 0x00040000
+#define HPTXSTS_PTXQSAV_3                (0x08UL << HPTXSTS_PTXQSAV_Pos)          // 0x00080000
+#define HPTXSTS_PTXQSAV_4                (0x10UL << HPTXSTS_PTXQSAV_Pos)          // 0x00100000
+#define HPTXSTS_PTXQSAV_5                (0x20UL << HPTXSTS_PTXQSAV_Pos)          // 0x00200000
+#define HPTXSTS_PTXQSAV_6                (0x40UL << HPTXSTS_PTXQSAV_Pos)          // 0x00400000
+#define HPTXSTS_PTXQSAV_7                (0x80UL << HPTXSTS_PTXQSAV_Pos)          // 0x00800000
 
 #define HPTXSTS_PTXQTOP_Pos              (24U)
-#define HPTXSTS_PTXQTOP_Msk              (0xFFUL << HPTXSTS_PTXQTOP_Pos)          // 0xFF000000 */
-#define HPTXSTS_PTXQTOP                  HPTXSTS_PTXQTOP_Msk                      // Top of the periodic transmit request queue */
-#define HPTXSTS_PTXQTOP_0                (0x01UL << HPTXSTS_PTXQTOP_Pos)          // 0x01000000 */
-#define HPTXSTS_PTXQTOP_1                (0x02UL << HPTXSTS_PTXQTOP_Pos)          // 0x02000000 */
-#define HPTXSTS_PTXQTOP_2                (0x04UL << HPTXSTS_PTXQTOP_Pos)          // 0x04000000 */
-#define HPTXSTS_PTXQTOP_3                (0x08UL << HPTXSTS_PTXQTOP_Pos)          // 0x08000000 */
-#define HPTXSTS_PTXQTOP_4                (0x10UL << HPTXSTS_PTXQTOP_Pos)          // 0x10000000 */
-#define HPTXSTS_PTXQTOP_5                (0x20UL << HPTXSTS_PTXQTOP_Pos)          // 0x20000000 */
-#define HPTXSTS_PTXQTOP_6                (0x40UL << HPTXSTS_PTXQTOP_Pos)          // 0x40000000 */
-#define HPTXSTS_PTXQTOP_7                (0x80UL << HPTXSTS_PTXQTOP_Pos)          // 0x80000000 */
+#define HPTXSTS_PTXQTOP_Msk              (0xFFUL << HPTXSTS_PTXQTOP_Pos)          // 0xFF000000
+#define HPTXSTS_PTXQTOP                  HPTXSTS_PTXQTOP_Msk                      // Top of the periodic transmit request queue
+#define HPTXSTS_PTXQTOP_0                (0x01UL << HPTXSTS_PTXQTOP_Pos)          // 0x01000000
+#define HPTXSTS_PTXQTOP_1                (0x02UL << HPTXSTS_PTXQTOP_Pos)          // 0x02000000
+#define HPTXSTS_PTXQTOP_2                (0x04UL << HPTXSTS_PTXQTOP_Pos)          // 0x04000000
+#define HPTXSTS_PTXQTOP_3                (0x08UL << HPTXSTS_PTXQTOP_Pos)          // 0x08000000
+#define HPTXSTS_PTXQTOP_4                (0x10UL << HPTXSTS_PTXQTOP_Pos)          // 0x10000000
+#define HPTXSTS_PTXQTOP_5                (0x20UL << HPTXSTS_PTXQTOP_Pos)          // 0x20000000
+#define HPTXSTS_PTXQTOP_6                (0x40UL << HPTXSTS_PTXQTOP_Pos)          // 0x40000000
+#define HPTXSTS_PTXQTOP_7                (0x80UL << HPTXSTS_PTXQTOP_Pos)          // 0x80000000
 
 /********************  Bit definition for HAINT register  ********************/
 #define HAINT_HAINT_Pos                  (0U)
-#define HAINT_HAINT_Msk                  (0xFFFFUL << HAINT_HAINT_Pos)            // 0x0000FFFF */
-#define HAINT_HAINT                      HAINT_HAINT_Msk                          // Channel interrupts */
+#define HAINT_HAINT_Msk                  (0xFFFFUL << HAINT_HAINT_Pos)            // 0x0000FFFF
+#define HAINT_HAINT                      HAINT_HAINT_Msk                          // Channel interrupts
 
 /********************  Bit definition for DOEPMSK register  ********************/
 #define DOEPMSK_XFRCM_Pos                (0U)
-#define DOEPMSK_XFRCM_Msk                (0x1UL << DOEPMSK_XFRCM_Pos)             // 0x00000001 */
-#define DOEPMSK_XFRCM                    DOEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask */
+#define DOEPMSK_XFRCM_Msk                (0x1UL << DOEPMSK_XFRCM_Pos)             // 0x00000001
+#define DOEPMSK_XFRCM                    DOEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask
 #define DOEPMSK_EPDM_Pos                 (1U)
-#define DOEPMSK_EPDM_Msk                 (0x1UL << DOEPMSK_EPDM_Pos)              // 0x00000002 */
-#define DOEPMSK_EPDM                     DOEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask               */
+#define DOEPMSK_EPDM_Msk                 (0x1UL << DOEPMSK_EPDM_Pos)              // 0x00000002
+#define DOEPMSK_EPDM                     DOEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask
 #define DOEPMSK_AHBERRM_Pos              (2U)
-#define DOEPMSK_AHBERRM_Msk              (0x1UL << DOEPMSK_AHBERRM_Pos)           // 0x00000004 */
-#define DOEPMSK_AHBERRM                  DOEPMSK_AHBERRM_Msk                      // OUT transaction AHB Error interrupt mask    */
+#define DOEPMSK_AHBERRM_Msk              (0x1UL << DOEPMSK_AHBERRM_Pos)           // 0x00000004
+#define DOEPMSK_AHBERRM                  DOEPMSK_AHBERRM_Msk                      // OUT transaction AHB Error interrupt mask
 #define DOEPMSK_STUPM_Pos                (3U)
-#define DOEPMSK_STUPM_Msk                (0x1UL << DOEPMSK_STUPM_Pos)             // 0x00000008 */
-#define DOEPMSK_STUPM                    DOEPMSK_STUPM_Msk                        // SETUP phase done mask                          */
+#define DOEPMSK_STUPM_Msk                (0x1UL << DOEPMSK_STUPM_Pos)             // 0x00000008
+#define DOEPMSK_STUPM                    DOEPMSK_STUPM_Msk                        // SETUP phase done mask
 #define DOEPMSK_OTEPDM_Pos               (4U)
-#define DOEPMSK_OTEPDM_Msk               (0x1UL << DOEPMSK_OTEPDM_Pos)            // 0x00000010 */
-#define DOEPMSK_OTEPDM                   DOEPMSK_OTEPDM_Msk                       // OUT token received when endpoint disabled mask */
+#define DOEPMSK_OTEPDM_Msk               (0x1UL << DOEPMSK_OTEPDM_Pos)            // 0x00000010
+#define DOEPMSK_OTEPDM                   DOEPMSK_OTEPDM_Msk                       // OUT token received when endpoint disabled mask
 #define DOEPMSK_OTEPSPRM_Pos             (5U)
-#define DOEPMSK_OTEPSPRM_Msk             (0x1UL << DOEPMSK_OTEPSPRM_Pos)          // 0x00000020 */
-#define DOEPMSK_OTEPSPRM                 DOEPMSK_OTEPSPRM_Msk                     // Status Phase Received mask                     */
+#define DOEPMSK_OTEPSPRM_Msk             (0x1UL << DOEPMSK_OTEPSPRM_Pos)          // 0x00000020
+#define DOEPMSK_OTEPSPRM                 DOEPMSK_OTEPSPRM_Msk                     // Status Phase Received mask
 #define DOEPMSK_B2BSTUP_Pos              (6U)
-#define DOEPMSK_B2BSTUP_Msk              (0x1UL << DOEPMSK_B2BSTUP_Pos)           // 0x00000040 */
-#define DOEPMSK_B2BSTUP                  DOEPMSK_B2BSTUP_Msk                      // Back-to-back SETUP packets received mask       */
+#define DOEPMSK_B2BSTUP_Msk              (0x1UL << DOEPMSK_B2BSTUP_Pos)           // 0x00000040
+#define DOEPMSK_B2BSTUP                  DOEPMSK_B2BSTUP_Msk                      // Back-to-back SETUP packets received mask
 #define DOEPMSK_OPEM_Pos                 (8U)
-#define DOEPMSK_OPEM_Msk                 (0x1UL << DOEPMSK_OPEM_Pos)              // 0x00000100 */
-#define DOEPMSK_OPEM                     DOEPMSK_OPEM_Msk                         // OUT packet error mask                          */
+#define DOEPMSK_OPEM_Msk                 (0x1UL << DOEPMSK_OPEM_Pos)              // 0x00000100
+#define DOEPMSK_OPEM                     DOEPMSK_OPEM_Msk                         // OUT packet error mask
 #define DOEPMSK_BOIM_Pos                 (9U)
-#define DOEPMSK_BOIM_Msk                 (0x1UL << DOEPMSK_BOIM_Pos)              // 0x00000200 */
-#define DOEPMSK_BOIM                     DOEPMSK_BOIM_Msk                         // BNA interrupt mask                             */
+#define DOEPMSK_BOIM_Msk                 (0x1UL << DOEPMSK_BOIM_Pos)              // 0x00000200
+#define DOEPMSK_BOIM                     DOEPMSK_BOIM_Msk                         // BNA interrupt mask
 #define DOEPMSK_BERRM_Pos                (12U)
-#define DOEPMSK_BERRM_Msk                (0x1UL << DOEPMSK_BERRM_Pos)             // 0x00001000 */
-#define DOEPMSK_BERRM                    DOEPMSK_BERRM_Msk                        // Babble error interrupt mask                   */
+#define DOEPMSK_BERRM_Msk                (0x1UL << DOEPMSK_BERRM_Pos)             // 0x00001000
+#define DOEPMSK_BERRM                    DOEPMSK_BERRM_Msk                        // Babble error interrupt mask
 #define DOEPMSK_NAKM_Pos                 (13U)
-#define DOEPMSK_NAKM_Msk                 (0x1UL << DOEPMSK_NAKM_Pos)              // 0x00002000 */
-#define DOEPMSK_NAKM                     DOEPMSK_NAKM_Msk                         // OUT Packet NAK interrupt mask                  */
+#define DOEPMSK_NAKM_Msk                 (0x1UL << DOEPMSK_NAKM_Pos)              // 0x00002000
+#define DOEPMSK_NAKM                     DOEPMSK_NAKM_Msk                         // OUT Packet NAK interrupt mask
 #define DOEPMSK_NYETM_Pos                (14U)
-#define DOEPMSK_NYETM_Msk                (0x1UL << DOEPMSK_NYETM_Pos)             // 0x00004000 */
-#define DOEPMSK_NYETM                    DOEPMSK_NYETM_Msk                        // NYET interrupt mask                           */
+#define DOEPMSK_NYETM_Msk                (0x1UL << DOEPMSK_NYETM_Pos)             // 0x00004000
+#define DOEPMSK_NYETM                    DOEPMSK_NYETM_Msk                        // NYET interrupt mask
 
 /********************  Bit definition for GINTSTS register  ********************/
 #define GINTSTS_CMOD_Pos                 (0U)
-#define GINTSTS_CMOD_Msk                 (0x1UL << GINTSTS_CMOD_Pos)              // 0x00000001 */
-#define GINTSTS_CMOD                     GINTSTS_CMOD_Msk                         // Current mode of operation                      */
+#define GINTSTS_CMOD_Msk                 (0x1UL << GINTSTS_CMOD_Pos)              // 0x00000001
+#define GINTSTS_CMOD                     GINTSTS_CMOD_Msk                         // Current mode of operation
 #define GINTSTS_MMIS_Pos                 (1U)
-#define GINTSTS_MMIS_Msk                 (0x1UL << GINTSTS_MMIS_Pos)              // 0x00000002 */
-#define GINTSTS_MMIS                     GINTSTS_MMIS_Msk                         // Mode mismatch interrupt                        */
+#define GINTSTS_MMIS_Msk                 (0x1UL << GINTSTS_MMIS_Pos)              // 0x00000002
+#define GINTSTS_MMIS                     GINTSTS_MMIS_Msk                         // Mode mismatch interrupt
 #define GINTSTS_OTGINT_Pos               (2U)
-#define GINTSTS_OTGINT_Msk               (0x1UL << GINTSTS_OTGINT_Pos)            // 0x00000004 */
-#define GINTSTS_OTGINT                   GINTSTS_OTGINT_Msk                       // OTG interrupt                                  */
+#define GINTSTS_OTGINT_Msk               (0x1UL << GINTSTS_OTGINT_Pos)            // 0x00000004
+#define GINTSTS_OTGINT                   GINTSTS_OTGINT_Msk                       // OTG interrupt
 #define GINTSTS_SOF_Pos                  (3U)
-#define GINTSTS_SOF_Msk                  (0x1UL << GINTSTS_SOF_Pos)               // 0x00000008 */
-#define GINTSTS_SOF                      GINTSTS_SOF_Msk                          // Start of frame                                 */
+#define GINTSTS_SOF_Msk                  (0x1UL << GINTSTS_SOF_Pos)               // 0x00000008
+#define GINTSTS_SOF                      GINTSTS_SOF_Msk                          // Start of frame
 #define GINTSTS_RXFLVL_Pos               (4U)
-#define GINTSTS_RXFLVL_Msk               (0x1UL << GINTSTS_RXFLVL_Pos)            // 0x00000010 */
-#define GINTSTS_RXFLVL                   GINTSTS_RXFLVL_Msk                       // RxFIFO nonempty                                */
-#define GINTSTS_NPTXFE_Pos               (5U)
-#define GINTSTS_NPTXFE_Msk               (0x1UL << GINTSTS_NPTXFE_Pos)            // 0x00000020 */
-#define GINTSTS_NPTXFE                   GINTSTS_NPTXFE_Msk                       // Nonperiodic TxFIFO empty                       */
+#define GINTSTS_RXFLVL_Msk               (0x1UL << GINTSTS_RXFLVL_Pos)            // 0x00000010
+#define GINTSTS_RXFLVL                   GINTSTS_RXFLVL_Msk                       // RxFIFO nonempty
+#define GINTSTS_NPTX_FIFO_EMPTY_Pos      (5U)
+#define GINTSTS_NPTX_FIFO_EMPTY_Msk      (0x1UL << GINTSTS_NPTX_FIFO_EMPTY_Pos)   // 0x00000020
+#define GINTSTS_NPTX_FIFO_EMPTY          GINTSTS_NPTX_FIFO_EMPTY_Msk              // Nonperiodic TxFIFO empty
 #define GINTSTS_GINAKEFF_Pos             (6U)
-#define GINTSTS_GINAKEFF_Msk             (0x1UL << GINTSTS_GINAKEFF_Pos)          // 0x00000040 */
-#define GINTSTS_GINAKEFF                 GINTSTS_GINAKEFF_Msk                     // Global IN nonperiodic NAK effective            */
+#define GINTSTS_GINAKEFF_Msk             (0x1UL << GINTSTS_GINAKEFF_Pos)          // 0x00000040
+#define GINTSTS_GINAKEFF                 GINTSTS_GINAKEFF_Msk                     // Global IN nonperiodic NAK effective
 #define GINTSTS_BOUTNAKEFF_Pos           (7U)
-#define GINTSTS_BOUTNAKEFF_Msk           (0x1UL << GINTSTS_BOUTNAKEFF_Pos)        // 0x00000080 */
-#define GINTSTS_BOUTNAKEFF               GINTSTS_BOUTNAKEFF_Msk                   // Global OUT NAK effective                       */
+#define GINTSTS_BOUTNAKEFF_Msk           (0x1UL << GINTSTS_BOUTNAKEFF_Pos)        // 0x00000080
+#define GINTSTS_BOUTNAKEFF               GINTSTS_BOUTNAKEFF_Msk                   // Global OUT NAK effective
 #define GINTSTS_ESUSP_Pos                (10U)
-#define GINTSTS_ESUSP_Msk                (0x1UL << GINTSTS_ESUSP_Pos)             // 0x00000400 */
-#define GINTSTS_ESUSP                    GINTSTS_ESUSP_Msk                        // Early suspend                                  */
+#define GINTSTS_ESUSP_Msk                (0x1UL << GINTSTS_ESUSP_Pos)             // 0x00000400
+#define GINTSTS_ESUSP                    GINTSTS_ESUSP_Msk                        // Early suspend
 #define GINTSTS_USBSUSP_Pos              (11U)
-#define GINTSTS_USBSUSP_Msk              (0x1UL << GINTSTS_USBSUSP_Pos)           // 0x00000800 */
-#define GINTSTS_USBSUSP                  GINTSTS_USBSUSP_Msk                      // USB suspend                                    */
+#define GINTSTS_USBSUSP_Msk              (0x1UL << GINTSTS_USBSUSP_Pos)           // 0x00000800
+#define GINTSTS_USBSUSP                  GINTSTS_USBSUSP_Msk                      // USB suspend
 #define GINTSTS_USBRST_Pos               (12U)
-#define GINTSTS_USBRST_Msk               (0x1UL << GINTSTS_USBRST_Pos)            // 0x00001000 */
-#define GINTSTS_USBRST                   GINTSTS_USBRST_Msk                       // USB reset                                      */
+#define GINTSTS_USBRST_Msk               (0x1UL << GINTSTS_USBRST_Pos)            // 0x00001000
+#define GINTSTS_USBRST                   GINTSTS_USBRST_Msk                       // USB reset
 #define GINTSTS_ENUMDNE_Pos              (13U)
-#define GINTSTS_ENUMDNE_Msk              (0x1UL << GINTSTS_ENUMDNE_Pos)           // 0x00002000 */
-#define GINTSTS_ENUMDNE                  GINTSTS_ENUMDNE_Msk                      // Enumeration done                               */
+#define GINTSTS_ENUMDNE_Msk              (0x1UL << GINTSTS_ENUMDNE_Pos)           // 0x00002000
+#define GINTSTS_ENUMDNE                  GINTSTS_ENUMDNE_Msk                      // Enumeration done
 #define GINTSTS_ISOODRP_Pos              (14U)
-#define GINTSTS_ISOODRP_Msk              (0x1UL << GINTSTS_ISOODRP_Pos)           // 0x00004000 */
-#define GINTSTS_ISOODRP                  GINTSTS_ISOODRP_Msk                      // Isochronous OUT packet dropped interrupt       */
+#define GINTSTS_ISOODRP_Msk              (0x1UL << GINTSTS_ISOODRP_Pos)           // 0x00004000
+#define GINTSTS_ISOODRP                  GINTSTS_ISOODRP_Msk                      // Isochronous OUT packet dropped interrupt
 #define GINTSTS_EOPF_Pos                 (15U)
-#define GINTSTS_EOPF_Msk                 (0x1UL << GINTSTS_EOPF_Pos)              // 0x00008000 */
-#define GINTSTS_EOPF                     GINTSTS_EOPF_Msk                         // End of periodic frame interrupt                */
+#define GINTSTS_EOPF_Msk                 (0x1UL << GINTSTS_EOPF_Pos)              // 0x00008000
+#define GINTSTS_EOPF                     GINTSTS_EOPF_Msk                         // End of periodic frame interrupt
 #define GINTSTS_IEPINT_Pos               (18U)
-#define GINTSTS_IEPINT_Msk               (0x1UL << GINTSTS_IEPINT_Pos)            // 0x00040000 */
-#define GINTSTS_IEPINT                   GINTSTS_IEPINT_Msk                       // IN endpoint interrupt                          */
+#define GINTSTS_IEPINT_Msk               (0x1UL << GINTSTS_IEPINT_Pos)            // 0x00040000
+#define GINTSTS_IEPINT                   GINTSTS_IEPINT_Msk                       // IN endpoint interrupt
 #define GINTSTS_OEPINT_Pos               (19U)
-#define GINTSTS_OEPINT_Msk               (0x1UL << GINTSTS_OEPINT_Pos)            // 0x00080000 */
-#define GINTSTS_OEPINT                   GINTSTS_OEPINT_Msk                       // OUT endpoint interrupt                         */
+#define GINTSTS_OEPINT_Msk               (0x1UL << GINTSTS_OEPINT_Pos)            // 0x00080000
+#define GINTSTS_OEPINT                   GINTSTS_OEPINT_Msk                       // OUT endpoint interrupt
 #define GINTSTS_IISOIXFR_Pos             (20U)
-#define GINTSTS_IISOIXFR_Msk             (0x1UL << GINTSTS_IISOIXFR_Pos)          // 0x00100000 */
-#define GINTSTS_IISOIXFR                 GINTSTS_IISOIXFR_Msk                     // Incomplete isochronous IN transfer             */
+#define GINTSTS_IISOIXFR_Msk             (0x1UL << GINTSTS_IISOIXFR_Pos)          // 0x00100000
+#define GINTSTS_IISOIXFR                 GINTSTS_IISOIXFR_Msk                     // Incomplete isochronous IN transfer
 #define GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
-#define GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000 */
-#define GINTSTS_PXFR_INCOMPISOOUT        GINTSTS_PXFR_INCOMPISOOUT_Msk            // Incomplete periodic transfer                   */
+#define GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000
+#define GINTSTS_PXFR_INCOMPISOOUT        GINTSTS_PXFR_INCOMPISOOUT_Msk            // Incomplete periodic transfer
 #define GINTSTS_DATAFSUSP_Pos            (22U)
-#define GINTSTS_DATAFSUSP_Msk            (0x1UL << GINTSTS_DATAFSUSP_Pos)         // 0x00400000 */
-#define GINTSTS_DATAFSUSP                GINTSTS_DATAFSUSP_Msk                    // Data fetch suspended                           */
+#define GINTSTS_DATAFSUSP_Msk            (0x1UL << GINTSTS_DATAFSUSP_Pos)         // 0x00400000
+#define GINTSTS_DATAFSUSP                GINTSTS_DATAFSUSP_Msk                    // Data fetch suspended
 #define GINTSTS_RSTDET_Pos               (23U)
-#define GINTSTS_RSTDET_Msk               (0x1UL << GINTSTS_RSTDET_Pos)            // 0x00800000 */
-#define GINTSTS_RSTDET                   GINTSTS_RSTDET_Msk                       // Reset detected interrupt                       */
+#define GINTSTS_RSTDET_Msk               (0x1UL << GINTSTS_RSTDET_Pos)            // 0x00800000
+#define GINTSTS_RSTDET                   GINTSTS_RSTDET_Msk                       // Reset detected interrupt
 #define GINTSTS_HPRTINT_Pos              (24U)
-#define GINTSTS_HPRTINT_Msk              (0x1UL << GINTSTS_HPRTINT_Pos)           // 0x01000000 */
-#define GINTSTS_HPRTINT                  GINTSTS_HPRTINT_Msk                      // Host port interrupt                            */
+#define GINTSTS_HPRTINT_Msk              (0x1UL << GINTSTS_HPRTINT_Pos)           // 0x01000000
+#define GINTSTS_HPRTINT                  GINTSTS_HPRTINT_Msk                      // Host port interrupt
 #define GINTSTS_HCINT_Pos                (25U)
-#define GINTSTS_HCINT_Msk                (0x1UL << GINTSTS_HCINT_Pos)             // 0x02000000 */
-#define GINTSTS_HCINT                    GINTSTS_HCINT_Msk                        // Host channels interrupt                        */
-#define GINTSTS_PTXFE_Pos                (26U)
-#define GINTSTS_PTXFE_Msk                (0x1UL << GINTSTS_PTXFE_Pos)             // 0x04000000 */
-#define GINTSTS_PTXFE                    GINTSTS_PTXFE_Msk                        // Periodic TxFIFO empty                          */
+#define GINTSTS_HCINT_Msk                (0x1UL << GINTSTS_HCINT_Pos)             // 0x02000000
+#define GINTSTS_HCINT                    GINTSTS_HCINT_Msk                        // Host channels interrupt
+#define GINTSTS_PTX_FIFO_EMPTY_Pos       (26U)
+#define GINTSTS_PTX_FIFO_EMPTY_Msk       (0x1UL << GINTSTS_PTX_FIFO_EMPTY_Pos)    // 0x04000000
+#define GINTSTS_PTX_FIFO_EMPTY           GINTSTS_PTX_FIFO_EMPTY_Msk               // Periodic TxFIFO empty
 #define GINTSTS_LPMINT_Pos               (27U)
-#define GINTSTS_LPMINT_Msk               (0x1UL << GINTSTS_LPMINT_Pos)            // 0x08000000 */
-#define GINTSTS_LPMINT                   GINTSTS_LPMINT_Msk                       // LPM interrupt                                  */
-#define GINTSTS_CIDSCHG_Pos              (28U)
-#define GINTSTS_CIDSCHG_Msk              (0x1UL << GINTSTS_CIDSCHG_Pos)           // 0x10000000 */
-#define GINTSTS_CIDSCHG                  GINTSTS_CIDSCHG_Msk                      // Connector ID status change                     */
+#define GINTSTS_LPMINT_Msk               (0x1UL << GINTSTS_LPMINT_Pos)            // 0x08000000
+#define GINTSTS_LPMINT                   GINTSTS_LPMINT_Msk                       // LPM interrupt
+#define GINTSTS_CONIDSTSCHNG_Pos         (28U)
+#define GINTSTS_CONIDSTSCHNG_Msk         (0x1UL << GINTSTS_CONIDSTSCHNG_Pos)      // 0x10000000
+#define GINTSTS_CONIDSTSCHNG             GINTSTS_CONIDSTSCHNG_Msk                 // Connector ID status change
 #define GINTSTS_DISCINT_Pos              (29U)
-#define GINTSTS_DISCINT_Msk              (0x1UL << GINTSTS_DISCINT_Pos)           // 0x20000000 */
-#define GINTSTS_DISCINT                  GINTSTS_DISCINT_Msk                      // Disconnect detected interrupt                  */
+#define GINTSTS_DISCINT_Msk              (0x1UL << GINTSTS_DISCINT_Pos)           // 0x20000000
+#define GINTSTS_DISCINT                  GINTSTS_DISCINT_Msk                      // Disconnect detected interrupt
 #define GINTSTS_SRQINT_Pos               (30U)
-#define GINTSTS_SRQINT_Msk               (0x1UL << GINTSTS_SRQINT_Pos)            // 0x40000000 */
-#define GINTSTS_SRQINT                   GINTSTS_SRQINT_Msk                       // Session request/new session detected interrupt */
+#define GINTSTS_SRQINT_Msk               (0x1UL << GINTSTS_SRQINT_Pos)            // 0x40000000
+#define GINTSTS_SRQINT                   GINTSTS_SRQINT_Msk                       // Session request/new session detected interrupt
 #define GINTSTS_WKUINT_Pos               (31U)
-#define GINTSTS_WKUINT_Msk               (0x1UL << GINTSTS_WKUINT_Pos)            // 0x80000000 */
-#define GINTSTS_WKUINT                   GINTSTS_WKUINT_Msk                       // Resume/remote wakeup detected interrupt        */
+#define GINTSTS_WKUINT_Msk               (0x1UL << GINTSTS_WKUINT_Pos)            // 0x80000000
+#define GINTSTS_WKUINT                   GINTSTS_WKUINT_Msk                       // Resume/remote wakeup detected interrupt
 
 /********************  Bit definition for GINTMSK register  ********************/
 #define GINTMSK_MMISM_Pos                (1U)
-#define GINTMSK_MMISM_Msk                (0x1UL << GINTMSK_MMISM_Pos)             // 0x00000002 */
-#define GINTMSK_MMISM                    GINTMSK_MMISM_Msk                        // Mode mismatch interrupt mask                        */
+#define GINTMSK_MMISM_Msk                (0x1UL << GINTMSK_MMISM_Pos)             // 0x00000002
+#define GINTMSK_MMISM                    GINTMSK_MMISM_Msk                        // Mode mismatch interrupt mask
 #define GINTMSK_OTGINT_Pos               (2U)
-#define GINTMSK_OTGINT_Msk               (0x1UL << GINTMSK_OTGINT_Pos)            // 0x00000004 */
-#define GINTMSK_OTGINT                   GINTMSK_OTGINT_Msk                       // OTG interrupt mask                                  */
+#define GINTMSK_OTGINT_Msk               (0x1UL << GINTMSK_OTGINT_Pos)            // 0x00000004
+#define GINTMSK_OTGINT                   GINTMSK_OTGINT_Msk                       // OTG interrupt mask
 #define GINTMSK_SOFM_Pos                 (3U)
-#define GINTMSK_SOFM_Msk                 (0x1UL << GINTMSK_SOFM_Pos)              // 0x00000008 */
-#define GINTMSK_SOFM                     GINTMSK_SOFM_Msk                         // Start of frame mask                                 */
+#define GINTMSK_SOFM_Msk                 (0x1UL << GINTMSK_SOFM_Pos)              // 0x00000008
+#define GINTMSK_SOFM                     GINTMSK_SOFM_Msk                         // Start of frame mask
 #define GINTMSK_RXFLVLM_Pos              (4U)
-#define GINTMSK_RXFLVLM_Msk              (0x1UL << GINTMSK_RXFLVLM_Pos)           // 0x00000010 */
-#define GINTMSK_RXFLVLM                  GINTMSK_RXFLVLM_Msk                      // Receive FIFO nonempty mask                          */
+#define GINTMSK_RXFLVLM_Msk              (0x1UL << GINTMSK_RXFLVLM_Pos)           // 0x00000010
+#define GINTMSK_RXFLVLM                  GINTMSK_RXFLVLM_Msk                      // Receive FIFO nonempty mask
 #define GINTMSK_NPTXFEM_Pos              (5U)
-#define GINTMSK_NPTXFEM_Msk              (0x1UL << GINTMSK_NPTXFEM_Pos)           // 0x00000020 */
-#define GINTMSK_NPTXFEM                  GINTMSK_NPTXFEM_Msk                      // Nonperiodic TxFIFO empty mask                       */
+#define GINTMSK_NPTXFEM_Msk              (0x1UL << GINTMSK_NPTXFEM_Pos)           // 0x00000020
+#define GINTMSK_NPTXFEM                  GINTMSK_NPTXFEM_Msk                      // Nonperiodic TxFIFO empty mask
 #define GINTMSK_GINAKEFFM_Pos            (6U)
-#define GINTMSK_GINAKEFFM_Msk            (0x1UL << GINTMSK_GINAKEFFM_Pos)         // 0x00000040 */
-#define GINTMSK_GINAKEFFM                GINTMSK_GINAKEFFM_Msk                    // Global nonperiodic IN NAK effective mask            */
+#define GINTMSK_GINAKEFFM_Msk            (0x1UL << GINTMSK_GINAKEFFM_Pos)         // 0x00000040
+#define GINTMSK_GINAKEFFM                GINTMSK_GINAKEFFM_Msk                    // Global nonperiodic IN NAK effective mask
 #define GINTMSK_GONAKEFFM_Pos            (7U)
-#define GINTMSK_GONAKEFFM_Msk            (0x1UL << GINTMSK_GONAKEFFM_Pos)         // 0x00000080 */
-#define GINTMSK_GONAKEFFM                GINTMSK_GONAKEFFM_Msk                    // Global OUT NAK effective mask                       */
+#define GINTMSK_GONAKEFFM_Msk            (0x1UL << GINTMSK_GONAKEFFM_Pos)         // 0x00000080
+#define GINTMSK_GONAKEFFM                GINTMSK_GONAKEFFM_Msk                    // Global OUT NAK effective mask
 #define GINTMSK_ESUSPM_Pos               (10U)
-#define GINTMSK_ESUSPM_Msk               (0x1UL << GINTMSK_ESUSPM_Pos)            // 0x00000400 */
-#define GINTMSK_ESUSPM                   GINTMSK_ESUSPM_Msk                       // Early suspend mask                                  */
+#define GINTMSK_ESUSPM_Msk               (0x1UL << GINTMSK_ESUSPM_Pos)            // 0x00000400
+#define GINTMSK_ESUSPM                   GINTMSK_ESUSPM_Msk                       // Early suspend mask
 #define GINTMSK_USBSUSPM_Pos             (11U)
-#define GINTMSK_USBSUSPM_Msk             (0x1UL << GINTMSK_USBSUSPM_Pos)          // 0x00000800 */
-#define GINTMSK_USBSUSPM                 GINTMSK_USBSUSPM_Msk                     // USB suspend mask                                    */
+#define GINTMSK_USBSUSPM_Msk             (0x1UL << GINTMSK_USBSUSPM_Pos)          // 0x00000800
+#define GINTMSK_USBSUSPM                 GINTMSK_USBSUSPM_Msk                     // USB suspend mask
 #define GINTMSK_USBRST_Pos               (12U)
-#define GINTMSK_USBRST_Msk               (0x1UL << GINTMSK_USBRST_Pos)            // 0x00001000 */
-#define GINTMSK_USBRST                   GINTMSK_USBRST_Msk                       // USB reset mask                                      */
+#define GINTMSK_USBRST_Msk               (0x1UL << GINTMSK_USBRST_Pos)            // 0x00001000
+#define GINTMSK_USBRST                   GINTMSK_USBRST_Msk                       // USB reset mask
 #define GINTMSK_ENUMDNEM_Pos             (13U)
-#define GINTMSK_ENUMDNEM_Msk             (0x1UL << GINTMSK_ENUMDNEM_Pos)          // 0x00002000 */
-#define GINTMSK_ENUMDNEM                 GINTMSK_ENUMDNEM_Msk                     // Enumeration done mask                               */
+#define GINTMSK_ENUMDNEM_Msk             (0x1UL << GINTMSK_ENUMDNEM_Pos)          // 0x00002000
+#define GINTMSK_ENUMDNEM                 GINTMSK_ENUMDNEM_Msk                     // Enumeration done mask
 #define GINTMSK_ISOODRPM_Pos             (14U)
-#define GINTMSK_ISOODRPM_Msk             (0x1UL << GINTMSK_ISOODRPM_Pos)          // 0x00004000 */
-#define GINTMSK_ISOODRPM                 GINTMSK_ISOODRPM_Msk                     // Isochronous OUT packet dropped interrupt mask       */
+#define GINTMSK_ISOODRPM_Msk             (0x1UL << GINTMSK_ISOODRPM_Pos)          // 0x00004000
+#define GINTMSK_ISOODRPM                 GINTMSK_ISOODRPM_Msk                     // Isochronous OUT packet dropped interrupt mask
 #define GINTMSK_EOPFM_Pos                (15U)
-#define GINTMSK_EOPFM_Msk                (0x1UL << GINTMSK_EOPFM_Pos)             // 0x00008000 */
-#define GINTMSK_EOPFM                    GINTMSK_EOPFM_Msk                        // End of periodic frame interrupt mask                */
+#define GINTMSK_EOPFM_Msk                (0x1UL << GINTMSK_EOPFM_Pos)             // 0x00008000
+#define GINTMSK_EOPFM                    GINTMSK_EOPFM_Msk                        // End of periodic frame interrupt mask
 #define GINTMSK_EPMISM_Pos               (17U)
-#define GINTMSK_EPMISM_Msk               (0x1UL << GINTMSK_EPMISM_Pos)            // 0x00020000 */
-#define GINTMSK_EPMISM                   GINTMSK_EPMISM_Msk                       // Endpoint mismatch interrupt mask                    */
+#define GINTMSK_EPMISM_Msk               (0x1UL << GINTMSK_EPMISM_Pos)            // 0x00020000
+#define GINTMSK_EPMISM                   GINTMSK_EPMISM_Msk                       // Endpoint mismatch interrupt mask
 #define GINTMSK_IEPINT_Pos               (18U)
-#define GINTMSK_IEPINT_Msk               (0x1UL << GINTMSK_IEPINT_Pos)            // 0x00040000 */
-#define GINTMSK_IEPINT                   GINTMSK_IEPINT_Msk                       // IN endpoints interrupt mask                         */
+#define GINTMSK_IEPINT_Msk               (0x1UL << GINTMSK_IEPINT_Pos)            // 0x00040000
+#define GINTMSK_IEPINT                   GINTMSK_IEPINT_Msk                       // IN endpoints interrupt mask
 #define GINTMSK_OEPINT_Pos               (19U)
-#define GINTMSK_OEPINT_Msk               (0x1UL << GINTMSK_OEPINT_Pos)            // 0x00080000 */
-#define GINTMSK_OEPINT                   GINTMSK_OEPINT_Msk                       // OUT endpoints interrupt mask                        */
+#define GINTMSK_OEPINT_Msk               (0x1UL << GINTMSK_OEPINT_Pos)            // 0x00080000
+#define GINTMSK_OEPINT                   GINTMSK_OEPINT_Msk                       // OUT endpoints interrupt mask
 #define GINTMSK_IISOIXFRM_Pos            (20U)
-#define GINTMSK_IISOIXFRM_Msk            (0x1UL << GINTMSK_IISOIXFRM_Pos)         // 0x00100000 */
-#define GINTMSK_IISOIXFRM                GINTMSK_IISOIXFRM_Msk                    // Incomplete isochronous IN transfer mask             */
+#define GINTMSK_IISOIXFRM_Msk            (0x1UL << GINTMSK_IISOIXFRM_Pos)         // 0x00100000
+#define GINTMSK_IISOIXFRM                GINTMSK_IISOIXFRM_Msk                    // Incomplete isochronous IN transfer mask
 #define GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
-#define GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos)   // 0x00200000 */
-#define GINTMSK_PXFRM_IISOOXFRM          GINTMSK_PXFRM_IISOOXFRM_Msk              // Incomplete periodic transfer mask                   */
+#define GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos)   // 0x00200000
+#define GINTMSK_PXFRM_IISOOXFRM          GINTMSK_PXFRM_IISOOXFRM_Msk              // Incomplete periodic transfer mask
 #define GINTMSK_FSUSPM_Pos               (22U)
-#define GINTMSK_FSUSPM_Msk               (0x1UL << GINTMSK_FSUSPM_Pos)            // 0x00400000 */
-#define GINTMSK_FSUSPM                   GINTMSK_FSUSPM_Msk                       // Data fetch suspended mask                           */
+#define GINTMSK_FSUSPM_Msk               (0x1UL << GINTMSK_FSUSPM_Pos)            // 0x00400000
+#define GINTMSK_FSUSPM                   GINTMSK_FSUSPM_Msk                       // Data fetch suspended mask
 #define GINTMSK_RSTDEM_Pos               (23U)
-#define GINTMSK_RSTDEM_Msk               (0x1UL << GINTMSK_RSTDEM_Pos)            // 0x00800000 */
-#define GINTMSK_RSTDEM                   GINTMSK_RSTDEM_Msk                       // Reset detected interrupt mask                       */
+#define GINTMSK_RSTDEM_Msk               (0x1UL << GINTMSK_RSTDEM_Pos)            // 0x00800000
+#define GINTMSK_RSTDEM                   GINTMSK_RSTDEM_Msk                       // Reset detected interrupt mask
 #define GINTMSK_PRTIM_Pos                (24U)
-#define GINTMSK_PRTIM_Msk                (0x1UL << GINTMSK_PRTIM_Pos)             // 0x01000000 */
-#define GINTMSK_PRTIM                    GINTMSK_PRTIM_Msk                        // Host port interrupt mask                            */
+#define GINTMSK_PRTIM_Msk                (0x1UL << GINTMSK_PRTIM_Pos)             // 0x01000000
+#define GINTMSK_PRTIM                    GINTMSK_PRTIM_Msk                        // Host port interrupt mask
 #define GINTMSK_HCIM_Pos                 (25U)
-#define GINTMSK_HCIM_Msk                 (0x1UL << GINTMSK_HCIM_Pos)              // 0x02000000 */
-#define GINTMSK_HCIM                     GINTMSK_HCIM_Msk                         // Host channels interrupt mask                        */
+#define GINTMSK_HCIM_Msk                 (0x1UL << GINTMSK_HCIM_Pos)              // 0x02000000
+#define GINTMSK_HCIM                     GINTMSK_HCIM_Msk                         // Host channels interrupt mask
 #define GINTMSK_PTXFEM_Pos               (26U)
-#define GINTMSK_PTXFEM_Msk               (0x1UL << GINTMSK_PTXFEM_Pos)            // 0x04000000 */
-#define GINTMSK_PTXFEM                   GINTMSK_PTXFEM_Msk                       // Periodic TxFIFO empty mask                          */
+#define GINTMSK_PTXFEM_Msk               (0x1UL << GINTMSK_PTXFEM_Pos)            // 0x04000000
+#define GINTMSK_PTXFEM                   GINTMSK_PTXFEM_Msk                       // Periodic TxFIFO empty mask
 #define GINTMSK_LPMINTM_Pos              (27U)
-#define GINTMSK_LPMINTM_Msk              (0x1UL << GINTMSK_LPMINTM_Pos)           // 0x08000000 */
-#define GINTMSK_LPMINTM                  GINTMSK_LPMINTM_Msk                      // LPM interrupt Mask                                  */
-#define GINTMSK_CIDSCHGM_Pos             (28U)
-#define GINTMSK_CIDSCHGM_Msk             (0x1UL << GINTMSK_CIDSCHGM_Pos)          // 0x10000000 */
-#define GINTMSK_CIDSCHGM                 GINTMSK_CIDSCHGM_Msk                     // Connector ID status change mask                     */
+#define GINTMSK_LPMINTM_Msk              (0x1UL << GINTMSK_LPMINTM_Pos)           // 0x08000000
+#define GINTMSK_LPMINTM                  GINTMSK_LPMINTM_Msk                      // LPM interrupt Mask
+#define GINTMSK_CONIDSTSCHNGM_Pos        (28U)
+#define GINTMSK_CONIDSTSCHNGM_Msk        (0x1UL << GINTMSK_CONIDSTSCHNGM_Pos)     // 0x10000000
+#define GINTMSK_CONIDSTSCHNGM            GINTMSK_CONIDSTSCHNGM_Msk                // Connector ID status change mask
 #define GINTMSK_DISCINT_Pos              (29U)
-#define GINTMSK_DISCINT_Msk              (0x1UL << GINTMSK_DISCINT_Pos)           // 0x20000000 */
-#define GINTMSK_DISCINT                  GINTMSK_DISCINT_Msk                      // Disconnect detected interrupt mask                  */
+#define GINTMSK_DISCINT_Msk              (0x1UL << GINTMSK_DISCINT_Pos)           // 0x20000000
+#define GINTMSK_DISCINT                  GINTMSK_DISCINT_Msk                      // Disconnect detected interrupt mask
 #define GINTMSK_SRQIM_Pos                (30U)
-#define GINTMSK_SRQIM_Msk                (0x1UL << GINTMSK_SRQIM_Pos)             // 0x40000000 */
-#define GINTMSK_SRQIM                    GINTMSK_SRQIM_Msk                        // Session request/new session detected interrupt mask */
+#define GINTMSK_SRQIM_Msk                (0x1UL << GINTMSK_SRQIM_Pos)             // 0x40000000
+#define GINTMSK_SRQIM                    GINTMSK_SRQIM_Msk                        // Session request/new session detected interrupt mask
 #define GINTMSK_WUIM_Pos                 (31U)
-#define GINTMSK_WUIM_Msk                 (0x1UL << GINTMSK_WUIM_Pos)              // 0x80000000 */
-#define GINTMSK_WUIM                     GINTMSK_WUIM_Msk                         // Resume/remote wakeup detected interrupt mask        */
+#define GINTMSK_WUIM_Msk                 (0x1UL << GINTMSK_WUIM_Pos)              // 0x80000000
+#define GINTMSK_WUIM                     GINTMSK_WUIM_Msk                         // Resume/remote wakeup detected interrupt mask
 
 /********************  Bit definition for DAINT register  ********************/
 #define DAINT_IEPINT_Pos                 (0U)
-#define DAINT_IEPINT_Msk                 (0xFFFFUL << DAINT_IEPINT_Pos)           // 0x0000FFFF */
-#define DAINT_IEPINT                     DAINT_IEPINT_Msk                         // IN endpoint interrupt bits  */
+#define DAINT_IEPINT_Msk                 (0xFFFFUL << DAINT_IEPINT_Pos)           // 0x0000FFFF
+#define DAINT_IEPINT                     DAINT_IEPINT_Msk                         // IN endpoint interrupt bits
 #define DAINT_OEPINT_Pos                 (16U)
-#define DAINT_OEPINT_Msk                 (0xFFFFUL << DAINT_OEPINT_Pos)           // 0xFFFF0000 */
-#define DAINT_OEPINT                     DAINT_OEPINT_Msk                         // OUT endpoint interrupt bits */
+#define DAINT_OEPINT_Msk                 (0xFFFFUL << DAINT_OEPINT_Pos)           // 0xFFFF0000
+#define DAINT_OEPINT                     DAINT_OEPINT_Msk                         // OUT endpoint interrupt bits
 
 /********************  Bit definition for HAINTMSK register  ********************/
 #define HAINTMSK_HAINTM_Pos              (0U)
-#define HAINTMSK_HAINTM_Msk              (0xFFFFUL << HAINTMSK_HAINTM_Pos)        // 0x0000FFFF */
-#define HAINTMSK_HAINTM                  HAINTMSK_HAINTM_Msk                      // Channel interrupt mask */
+#define HAINTMSK_HAINTM_Msk              (0xFFFFUL << HAINTMSK_HAINTM_Pos)        // 0x0000FFFF
+#define HAINTMSK_HAINTM                  HAINTMSK_HAINTM_Msk                      // Channel interrupt mask
 
 /********************  Bit definition for GRXSTSP register  ********************/
 #define GRXSTSP_EPNUM_Pos                (0U)
-#define GRXSTSP_EPNUM_Msk                (0xFUL << GRXSTSP_EPNUM_Pos)             // 0x0000000F */
-#define GRXSTSP_EPNUM                    GRXSTSP_EPNUM_Msk                        // IN EP interrupt mask bits  */
+#define GRXSTSP_EPNUM_Msk                (0xFUL << GRXSTSP_EPNUM_Pos)             // 0x0000000F
+#define GRXSTSP_EPNUM                    GRXSTSP_EPNUM_Msk                        // IN EP interrupt mask bits
 #define GRXSTSP_BCNT_Pos                 (4U)
-#define GRXSTSP_BCNT_Msk                 (0x7FFUL << GRXSTSP_BCNT_Pos)            // 0x00007FF0 */
-#define GRXSTSP_BCNT                     GRXSTSP_BCNT_Msk                         // OUT EP interrupt mask bits */
+#define GRXSTSP_BCNT_Msk                 (0x7FFUL << GRXSTSP_BCNT_Pos)            // 0x00007FF0
+#define GRXSTSP_BCNT                     GRXSTSP_BCNT_Msk                         // OUT EP interrupt mask bits
 #define GRXSTSP_DPID_Pos                 (15U)
-#define GRXSTSP_DPID_Msk                 (0x3UL << GRXSTSP_DPID_Pos)              // 0x00018000 */
-#define GRXSTSP_DPID                     GRXSTSP_DPID_Msk                         // OUT EP interrupt mask bits */
+#define GRXSTSP_DPID_Msk                 (0x3UL << GRXSTSP_DPID_Pos)              // 0x00018000
+#define GRXSTSP_DPID                     GRXSTSP_DPID_Msk                         // OUT EP interrupt mask bits
 #define GRXSTSP_PKTSTS_Pos               (17U)
-#define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos)            // 0x001E0000 */
-#define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk                       // OUT EP interrupt mask bits */
-
-#define GRXSTS_PKTSTS_GLOBALOUTNAK       1
-#define GRXSTS_PKTSTS_OUTRX              2
-#define GRXSTS_PKTSTS_HCHIN              2
-#define GRXSTS_PKTSTS_OUTDONE            3
-#define GRXSTS_PKTSTS_HCHIN_XFER_COMP    3
-#define GRXSTS_PKTSTS_SETUPDONE          4
-#define GRXSTS_PKTSTS_DATATOGGLEERR      5
-#define GRXSTS_PKTSTS_SETUPRX            6
-#define GRXSTS_PKTSTS_HCHHALTED          7
-
+#define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos)            // 0x001E0000
+#define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk                       // OUT EP interrupt mask bits
 
 /********************  Bit definition for DAINTMSK register  ********************/
 #define DAINTMSK_IEPM_Pos                (0U)
-#define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos)          // 0x0000FFFF */
-#define DAINTMSK_IEPM                    DAINTMSK_IEPM_Msk                        // IN EP interrupt mask bits */
+#define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos)          // 0x0000FFFF
+#define DAINTMSK_IEPM                    DAINTMSK_IEPM_Msk                        // IN EP interrupt mask bits
 #define DAINTMSK_OEPM_Pos                (16U)
-#define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          // 0xFFFF0000 */
-#define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        // OUT EP interrupt mask bits */
+#define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          // 0xFFFF0000
+#define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        // OUT EP interrupt mask bits
+
+#define DAINT_SHIFT(_dir)            ((_dir == TUSB_DIR_IN) ? 0 : 16)
 
 #if 0
 /********************  Bit definition for OTG register  ********************/
 #define CHNUM_Pos                        (0U)
-#define CHNUM_Msk                        (0xFUL << CHNUM_Pos)                     // 0x0000000F */
-#define CHNUM                            CHNUM_Msk                                // Channel number */
-#define CHNUM_0                          (0x1UL << CHNUM_Pos)                     // 0x00000001 */
-#define CHNUM_1                          (0x2UL << CHNUM_Pos)                     // 0x00000002 */
-#define CHNUM_2                          (0x4UL << CHNUM_Pos)                     // 0x00000004 */
-#define CHNUM_3                          (0x8UL << CHNUM_Pos)                     // 0x00000008 */
+#define CHNUM_Msk                        (0xFUL << CHNUM_Pos)                     // 0x0000000F
+#define CHNUM                            CHNUM_Msk                                // Channel number
+#define CHNUM_0                          (0x1UL << CHNUM_Pos)                     // 0x00000001
+#define CHNUM_1                          (0x2UL << CHNUM_Pos)                     // 0x00000002
+#define CHNUM_2                          (0x4UL << CHNUM_Pos)                     // 0x00000004
+#define CHNUM_3                          (0x8UL << CHNUM_Pos)                     // 0x00000008
 #define BCNT_Pos                         (4U)
-#define BCNT_Msk                         (0x7FFUL << BCNT_Pos)                    // 0x00007FF0 */
-#define BCNT                             BCNT_Msk                                 // Byte count */
+#define BCNT_Msk                         (0x7FFUL << BCNT_Pos)                    // 0x00007FF0
+#define BCNT                             BCNT_Msk                                 // Byte count
 
 #define DPID_Pos                         (15U)
-#define DPID_Msk                         (0x3UL << DPID_Pos)                      // 0x00018000 */
-#define DPID                             DPID_Msk                                 // Data PID */
-#define DPID_0                           (0x1UL << DPID_Pos)                      // 0x00008000 */
-#define DPID_1                           (0x2UL << DPID_Pos)                      // 0x00010000 */
+#define DPID_Msk                         (0x3UL << DPID_Pos)                      // 0x00018000
+#define DPID                             DPID_Msk                                 // Data PID
+#define DPID_0                           (0x1UL << DPID_Pos)                      // 0x00008000
+#define DPID_1                           (0x2UL << DPID_Pos)                      // 0x00010000
 
 #define PKTSTS_Pos                       (17U)
-#define PKTSTS_Msk                       (0xFUL << PKTSTS_Pos)                    // 0x001E0000 */
-#define PKTSTS                           PKTSTS_Msk                               // Packet status */
-#define PKTSTS_0                         (0x1UL << PKTSTS_Pos)                    // 0x00020000 */
-#define PKTSTS_1                         (0x2UL << PKTSTS_Pos)                    // 0x00040000 */
-#define PKTSTS_2                         (0x4UL << PKTSTS_Pos)                    // 0x00080000 */
-#define PKTSTS_3                         (0x8UL << PKTSTS_Pos)                    // 0x00100000 */
+#define PKTSTS_Msk                       (0xFUL << PKTSTS_Pos)                    // 0x001E0000
+#define PKTSTS                           PKTSTS_Msk                               // Packet status
+#define PKTSTS_0                         (0x1UL << PKTSTS_Pos)                    // 0x00020000
+#define PKTSTS_1                         (0x2UL << PKTSTS_Pos)                    // 0x00040000
+#define PKTSTS_2                         (0x4UL << PKTSTS_Pos)                    // 0x00080000
+#define PKTSTS_3                         (0x8UL << PKTSTS_Pos)                    // 0x00100000
 
 #define EPNUM_Pos                        (0U)
-#define EPNUM_Msk                        (0xFUL << EPNUM_Pos)                     // 0x0000000F */
-#define EPNUM                            EPNUM_Msk                                // Endpoint number */
-#define EPNUM_0                          (0x1UL << EPNUM_Pos)                     // 0x00000001 */
-#define EPNUM_1                          (0x2UL << EPNUM_Pos)                     // 0x00000002 */
-#define EPNUM_2                          (0x4UL << EPNUM_Pos)                     // 0x00000004 */
-#define EPNUM_3                          (0x8UL << EPNUM_Pos)                     // 0x00000008 */
+#define EPNUM_Msk                        (0xFUL << EPNUM_Pos)                     // 0x0000000F
+#define EPNUM                            EPNUM_Msk                                // Endpoint number
+#define EPNUM_0                          (0x1UL << EPNUM_Pos)                     // 0x00000001
+#define EPNUM_1                          (0x2UL << EPNUM_Pos)                     // 0x00000002
+#define EPNUM_2                          (0x4UL << EPNUM_Pos)                     // 0x00000004
+#define EPNUM_3                          (0x8UL << EPNUM_Pos)                     // 0x00000008
 
 #define FRMNUM_Pos                       (21U)
-#define FRMNUM_Msk                       (0xFUL << FRMNUM_Pos)                    // 0x01E00000 */
-#define FRMNUM                           FRMNUM_Msk                               // Frame number */
-#define FRMNUM_0                         (0x1UL << FRMNUM_Pos)                    // 0x00200000 */
-#define FRMNUM_1                         (0x2UL << FRMNUM_Pos)                    // 0x00400000 */
-#define FRMNUM_2                         (0x4UL << FRMNUM_Pos)                    // 0x00800000 */
-#define FRMNUM_3                         (0x8UL << FRMNUM_Pos)                    // 0x01000000 */
+#define FRMNUM_Msk                       (0xFUL << FRMNUM_Pos)                    // 0x01E00000
+#define FRMNUM                           FRMNUM_Msk                               // Frame number
+#define FRMNUM_0                         (0x1UL << FRMNUM_Pos)                    // 0x00200000
+#define FRMNUM_1                         (0x2UL << FRMNUM_Pos)                    // 0x00400000
+#define FRMNUM_2                         (0x4UL << FRMNUM_Pos)                    // 0x00800000
+#define FRMNUM_3                         (0x8UL << FRMNUM_Pos)                    // 0x01000000
 #endif
 
 /********************  Bit definition for GRXFSIZ register  ********************/
 #define GRXFSIZ_RXFD_Pos                 (0U)
-#define GRXFSIZ_RXFD_Msk                 (0xFFFFUL << GRXFSIZ_RXFD_Pos)           // 0x0000FFFF */
-#define GRXFSIZ_RXFD                     GRXFSIZ_RXFD_Msk                         // RxFIFO depth */
+#define GRXFSIZ_RXFD_Msk                 (0xFFFFUL << GRXFSIZ_RXFD_Pos)           // 0x0000FFFF
+#define GRXFSIZ_RXFD                     GRXFSIZ_RXFD_Msk                         // RxFIFO depth
 
 /********************  Bit definition for DVBUSDIS register  ********************/
 #define DVBUSDIS_VBUSDT_Pos              (0U)
-#define DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << DVBUSDIS_VBUSDT_Pos)        // 0x0000FFFF */
-#define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk                      // Device VBUS discharge time */
+#define DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << DVBUSDIS_VBUSDT_Pos)        // 0x0000FFFF
+#define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk                      // Device VBUS discharge time
 
 /********************  Bit definition for OTG register  ********************/
 #define GNPTXFSIZ_NPTXFSA_Pos            (0U)
-#define GNPTXFSIZ_NPTXFSA_Msk            (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos)                // 0x0000FFFF */
-#define GNPTXFSIZ_NPTXFSA                GNPTXFSIZ_NPTXFSA_Msk                    // Nonperiodic transmit RAM start address */
+#define GNPTXFSIZ_NPTXFSA_Msk            (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos)                // 0x0000FFFF
+#define GNPTXFSIZ_NPTXFSA                GNPTXFSIZ_NPTXFSA_Msk                    // Nonperiodic transmit RAM start address
 #define GNPTXFSIZ_NPTXFD_Pos             (16U)
-#define GNPTXFSIZ_NPTXFD_Msk             (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos)                 // 0xFFFF0000 */
-#define GNPTXFSIZ_NPTXFD                 GNPTXFSIZ_NPTXFD_Msk                     // Nonperiodic TxFIFO depth               */
+#define GNPTXFSIZ_NPTXFD_Msk             (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos)                 // 0xFFFF0000
+#define GNPTXFSIZ_NPTXFD                 GNPTXFSIZ_NPTXFD_Msk                     // Nonperiodic TxFIFO depth
 #define DIEPTXF0_TX0FSA_Pos              (0U)
-#define DIEPTXF0_TX0FSA_Msk              (0xFFFFUL << DIEPTXF0_TX0FSA_Pos)                 // 0x0000FFFF */
-#define DIEPTXF0_TX0FSA                  DIEPTXF0_TX0FSA_Msk                      // Endpoint 0 transmit RAM start address  */
+#define DIEPTXF0_TX0FSA_Msk              (0xFFFFUL << DIEPTXF0_TX0FSA_Pos)                 // 0x0000FFFF
+#define DIEPTXF0_TX0FSA                  DIEPTXF0_TX0FSA_Msk                      // Endpoint 0 transmit RAM start address
 #define DIEPTXF0_TX0FD_Pos               (16U)
-#define DIEPTXF0_TX0FD_Msk               (0xFFFFUL << DIEPTXF0_TX0FD_Pos)                  // 0xFFFF0000 */
-#define DIEPTXF0_TX0FD                   DIEPTXF0_TX0FD_Msk                       // Endpoint 0 TxFIFO depth                */
+#define DIEPTXF0_TX0FD_Msk               (0xFFFFUL << DIEPTXF0_TX0FD_Pos)                  // 0xFFFF0000
+#define DIEPTXF0_TX0FD                   DIEPTXF0_TX0FD_Msk                       // Endpoint 0 TxFIFO depth
 
 /********************  Bit definition for DVBUSPULSE register  ********************/
 #define DVBUSPULSE_DVBUSP_Pos            (0U)
-#define DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << DVBUSPULSE_DVBUSP_Pos)       // 0x00000FFF */
-#define DVBUSPULSE_DVBUSP                DVBUSPULSE_DVBUSP_Msk                    // Device VBUS pulsing time */
+#define DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << DVBUSPULSE_DVBUSP_Pos)       // 0x00000FFF
+#define DVBUSPULSE_DVBUSP                DVBUSPULSE_DVBUSP_Msk                    // Device VBUS pulsing time
 
 /********************  Bit definition for GNPTXSTS register  ********************/
 #define GNPTXSTS_NPTXFSAV_Pos            (0U)
-#define GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos)      // 0x0000FFFF */
-#define GNPTXSTS_NPTXFSAV                GNPTXSTS_NPTXFSAV_Msk                    // Nonperiodic TxFIFO space available */
+#define GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos)      // 0x0000FFFF
+#define GNPTXSTS_NPTXFSAV                GNPTXSTS_NPTXFSAV_Msk                    // Nonperiodic TxFIFO space available
 
 #define GNPTXSTS_NPTQXSAV_Pos            (16U)
-#define GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00FF0000 */
-#define GNPTXSTS_NPTQXSAV                GNPTXSTS_NPTQXSAV_Msk                    // Nonperiodic transmit request queue space available */
-#define GNPTXSTS_NPTQXSAV_0              (0x01UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00010000 */
-#define GNPTXSTS_NPTQXSAV_1              (0x02UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00020000 */
-#define GNPTXSTS_NPTQXSAV_2              (0x04UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00040000 */
-#define GNPTXSTS_NPTQXSAV_3              (0x08UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00080000 */
-#define GNPTXSTS_NPTQXSAV_4              (0x10UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00100000 */
-#define GNPTXSTS_NPTQXSAV_5              (0x20UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00200000 */
-#define GNPTXSTS_NPTQXSAV_6              (0x40UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00400000 */
-#define GNPTXSTS_NPTQXSAV_7              (0x80UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00800000 */
+#define GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00FF0000
+#define GNPTXSTS_NPTQXSAV                GNPTXSTS_NPTQXSAV_Msk                    // Nonperiodic transmit request queue space available
+#define GNPTXSTS_NPTQXSAV_0              (0x01UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00010000
+#define GNPTXSTS_NPTQXSAV_1              (0x02UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00020000
+#define GNPTXSTS_NPTQXSAV_2              (0x04UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00040000
+#define GNPTXSTS_NPTQXSAV_3              (0x08UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00080000
+#define GNPTXSTS_NPTQXSAV_4              (0x10UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00100000
+#define GNPTXSTS_NPTQXSAV_5              (0x20UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00200000
+#define GNPTXSTS_NPTQXSAV_6              (0x40UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00400000
+#define GNPTXSTS_NPTQXSAV_7              (0x80UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00800000
 
 #define GNPTXSTS_NPTXQTOP_Pos            (24U)
-#define GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << GNPTXSTS_NPTXQTOP_Pos)        // 0x7F000000 */
-#define GNPTXSTS_NPTXQTOP                GNPTXSTS_NPTXQTOP_Msk                    // Top of the nonperiodic transmit request queue */
-#define GNPTXSTS_NPTXQTOP_0              (0x01UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x01000000 */
-#define GNPTXSTS_NPTXQTOP_1              (0x02UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x02000000 */
-#define GNPTXSTS_NPTXQTOP_2              (0x04UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x04000000 */
-#define GNPTXSTS_NPTXQTOP_3              (0x08UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x08000000 */
-#define GNPTXSTS_NPTXQTOP_4              (0x10UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x10000000 */
-#define GNPTXSTS_NPTXQTOP_5              (0x20UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x20000000 */
-#define GNPTXSTS_NPTXQTOP_6              (0x40UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x40000000 */
+#define GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << GNPTXSTS_NPTXQTOP_Pos)        // 0x7F000000
+#define GNPTXSTS_NPTXQTOP                GNPTXSTS_NPTXQTOP_Msk                    // Top of the nonperiodic transmit request queue
+#define GNPTXSTS_NPTXQTOP_0              (0x01UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x01000000
+#define GNPTXSTS_NPTXQTOP_1              (0x02UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x02000000
+#define GNPTXSTS_NPTXQTOP_2              (0x04UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x04000000
+#define GNPTXSTS_NPTXQTOP_3              (0x08UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x08000000
+#define GNPTXSTS_NPTXQTOP_4              (0x10UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x10000000
+#define GNPTXSTS_NPTXQTOP_5              (0x20UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x20000000
+#define GNPTXSTS_NPTXQTOP_6              (0x40UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x40000000
 
 /********************  Bit definition for DTHRCTL register  ********************/
 #define DTHRCTL_NONISOTHREN_Pos          (0U)
-#define DTHRCTL_NONISOTHREN_Msk          (0x1UL << DTHRCTL_NONISOTHREN_Pos)       // 0x00000001 */
-#define DTHRCTL_NONISOTHREN              DTHRCTL_NONISOTHREN_Msk                  // Nonisochronous IN endpoints threshold enable */
+#define DTHRCTL_NONISOTHREN_Msk          (0x1UL << DTHRCTL_NONISOTHREN_Pos)       // 0x00000001
+#define DTHRCTL_NONISOTHREN              DTHRCTL_NONISOTHREN_Msk                  // Nonisochronous IN endpoints threshold enable
 #define DTHRCTL_ISOTHREN_Pos             (1U)
-#define DTHRCTL_ISOTHREN_Msk             (0x1UL << DTHRCTL_ISOTHREN_Pos)          // 0x00000002 */
-#define DTHRCTL_ISOTHREN                 DTHRCTL_ISOTHREN_Msk                     // ISO IN endpoint threshold enable */
+#define DTHRCTL_ISOTHREN_Msk             (0x1UL << DTHRCTL_ISOTHREN_Pos)          // 0x00000002
+#define DTHRCTL_ISOTHREN                 DTHRCTL_ISOTHREN_Msk                     // ISO IN endpoint threshold enable
 
 #define DTHRCTL_TXTHRLEN_Pos             (2U)
-#define DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << DTHRCTL_TXTHRLEN_Pos)        // 0x000007FC */
-#define DTHRCTL_TXTHRLEN                 DTHRCTL_TXTHRLEN_Msk                     // Transmit threshold length */
-#define DTHRCTL_TXTHRLEN_0               (0x001UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000004 */
-#define DTHRCTL_TXTHRLEN_1               (0x002UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000008 */
-#define DTHRCTL_TXTHRLEN_2               (0x004UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000010 */
-#define DTHRCTL_TXTHRLEN_3               (0x008UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000020 */
-#define DTHRCTL_TXTHRLEN_4               (0x010UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000040 */
-#define DTHRCTL_TXTHRLEN_5               (0x020UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000080 */
-#define DTHRCTL_TXTHRLEN_6               (0x040UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000100 */
-#define DTHRCTL_TXTHRLEN_7               (0x080UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000200 */
-#define DTHRCTL_TXTHRLEN_8               (0x100UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000400 */
+#define DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << DTHRCTL_TXTHRLEN_Pos)        // 0x000007FC
+#define DTHRCTL_TXTHRLEN                 DTHRCTL_TXTHRLEN_Msk                     // Transmit threshold length
+#define DTHRCTL_TXTHRLEN_0               (0x001UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000004
+#define DTHRCTL_TXTHRLEN_1               (0x002UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000008
+#define DTHRCTL_TXTHRLEN_2               (0x004UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000010
+#define DTHRCTL_TXTHRLEN_3               (0x008UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000020
+#define DTHRCTL_TXTHRLEN_4               (0x010UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000040
+#define DTHRCTL_TXTHRLEN_5               (0x020UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000080
+#define DTHRCTL_TXTHRLEN_6               (0x040UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000100
+#define DTHRCTL_TXTHRLEN_7               (0x080UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000200
+#define DTHRCTL_TXTHRLEN_8               (0x100UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000400
 #define DTHRCTL_RXTHREN_Pos              (16U)
-#define DTHRCTL_RXTHREN_Msk              (0x1UL << DTHRCTL_RXTHREN_Pos)           // 0x00010000 */
-#define DTHRCTL_RXTHREN                  DTHRCTL_RXTHREN_Msk                      // Receive threshold enable */
+#define DTHRCTL_RXTHREN_Msk              (0x1UL << DTHRCTL_RXTHREN_Pos)           // 0x00010000
+#define DTHRCTL_RXTHREN                  DTHRCTL_RXTHREN_Msk                      // Receive threshold enable
 
 #define DTHRCTL_RXTHRLEN_Pos             (17U)
-#define DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << DTHRCTL_RXTHRLEN_Pos)        // 0x03FE0000 */
-#define DTHRCTL_RXTHRLEN                 DTHRCTL_RXTHRLEN_Msk                     // Receive threshold length */
-#define DTHRCTL_RXTHRLEN_0               (0x001UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00020000 */
-#define DTHRCTL_RXTHRLEN_1               (0x002UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00040000 */
-#define DTHRCTL_RXTHRLEN_2               (0x004UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00080000 */
-#define DTHRCTL_RXTHRLEN_3               (0x008UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00100000 */
-#define DTHRCTL_RXTHRLEN_4               (0x010UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00200000 */
-#define DTHRCTL_RXTHRLEN_5               (0x020UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00400000 */
-#define DTHRCTL_RXTHRLEN_6               (0x040UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00800000 */
-#define DTHRCTL_RXTHRLEN_7               (0x080UL << DTHRCTL_RXTHRLEN_Pos)        // 0x01000000 */
-#define DTHRCTL_RXTHRLEN_8               (0x100UL << DTHRCTL_RXTHRLEN_Pos)        // 0x02000000 */
+#define DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << DTHRCTL_RXTHRLEN_Pos)        // 0x03FE0000
+#define DTHRCTL_RXTHRLEN                 DTHRCTL_RXTHRLEN_Msk                     // Receive threshold length
+#define DTHRCTL_RXTHRLEN_0               (0x001UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00020000
+#define DTHRCTL_RXTHRLEN_1               (0x002UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00040000
+#define DTHRCTL_RXTHRLEN_2               (0x004UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00080000
+#define DTHRCTL_RXTHRLEN_3               (0x008UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00100000
+#define DTHRCTL_RXTHRLEN_4               (0x010UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00200000
+#define DTHRCTL_RXTHRLEN_5               (0x020UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00400000
+#define DTHRCTL_RXTHRLEN_6               (0x040UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00800000
+#define DTHRCTL_RXTHRLEN_7               (0x080UL << DTHRCTL_RXTHRLEN_Pos)        // 0x01000000
+#define DTHRCTL_RXTHRLEN_8               (0x100UL << DTHRCTL_RXTHRLEN_Pos)        // 0x02000000
 #define DTHRCTL_ARPEN_Pos                (27U)
-#define DTHRCTL_ARPEN_Msk                (0x1UL << DTHRCTL_ARPEN_Pos)             // 0x08000000 */
-#define DTHRCTL_ARPEN                    DTHRCTL_ARPEN_Msk                        // Arbiter parking enable */
+#define DTHRCTL_ARPEN_Msk                (0x1UL << DTHRCTL_ARPEN_Pos)             // 0x08000000
+#define DTHRCTL_ARPEN                    DTHRCTL_ARPEN_Msk                        // Arbiter parking enable
 
 /********************  Bit definition for DIEPEMPMSK register  ********************/
 #define DIEPEMPMSK_INEPTXFEM_Pos         (0U)
-#define DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos)   // 0x0000FFFF */
-#define DIEPEMPMSK_INEPTXFEM             DIEPEMPMSK_INEPTXFEM_Msk                 // IN EP Tx FIFO empty interrupt mask bits */
+#define DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos)   // 0x0000FFFF
+#define DIEPEMPMSK_INEPTXFEM             DIEPEMPMSK_INEPTXFEM_Msk                 // IN EP Tx FIFO empty interrupt mask bits
 
 /********************  Bit definition for DEACHINT register  ********************/
 #define DEACHINT_IEP1INT_Pos             (1U)
-#define DEACHINT_IEP1INT_Msk             (0x1UL << DEACHINT_IEP1INT_Pos)          // 0x00000002 */
-#define DEACHINT_IEP1INT                 DEACHINT_IEP1INT_Msk                     // IN endpoint 1interrupt bit   */
+#define DEACHINT_IEP1INT_Msk             (0x1UL << DEACHINT_IEP1INT_Pos)          // 0x00000002
+#define DEACHINT_IEP1INT                 DEACHINT_IEP1INT_Msk                     // IN endpoint 1interrupt bit
 #define DEACHINT_OEP1INT_Pos             (17U)
-#define DEACHINT_OEP1INT_Msk             (0x1UL << DEACHINT_OEP1INT_Pos)          // 0x00020000 */
-#define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk                     // OUT endpoint 1 interrupt bit */
+#define DEACHINT_OEP1INT_Msk             (0x1UL << DEACHINT_OEP1INT_Pos)          // 0x00020000
+#define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk                     // OUT endpoint 1 interrupt bit
 
 /********************  Bit definition for GCCFG register  ********************/
 #define STM32_GCCFG_DCDET_Pos            (0U)
-#define STM32_GCCFG_DCDET_Msk            (0x1UL << STM32_GCCFG_DCDET_Pos)         // 0x00000001 */
-#define STM32_GCCFG_DCDET                STM32_GCCFG_DCDET_Msk                    // Data contact detection (DCD) status */
+#define STM32_GCCFG_DCDET_Msk            (0x1UL << STM32_GCCFG_DCDET_Pos)         // 0x00000001
+#define STM32_GCCFG_DCDET                STM32_GCCFG_DCDET_Msk                    // Data contact detection (DCD) status
+
 #define STM32_GCCFG_PDET_Pos             (1U)
-#define STM32_GCCFG_PDET_Msk             (0x1UL << STM32_GCCFG_PDET_Pos)          // 0x00000002 */
-#define STM32_GCCFG_PDET                 STM32_GCCFG_PDET_Msk                     // Primary detection (PD) status */
+#define STM32_GCCFG_PDET_Msk             (0x1UL << STM32_GCCFG_PDET_Pos)          // 0x00000002
+#define STM32_GCCFG_PDET                 STM32_GCCFG_PDET_Msk                     // Primary detection (PD) status
+
 #define STM32_GCCFG_SDET_Pos             (2U)
-#define STM32_GCCFG_SDET_Msk             (0x1UL << STM32_GCCFG_SDET_Pos)          // 0x00000004 */
-#define STM32_GCCFG_SDET                 STM32_GCCFG_SDET_Msk                     // Secondary detection (SD) status */
+#define STM32_GCCFG_SDET_Msk             (0x1UL << STM32_GCCFG_SDET_Pos)          // 0x00000004
+#define STM32_GCCFG_SDET                 STM32_GCCFG_SDET_Msk                     // Secondary detection (SD) status
+
 #define STM32_GCCFG_PS2DET_Pos           (3U)
-#define STM32_GCCFG_PS2DET_Msk           (0x1UL << STM32_GCCFG_PS2DET_Pos)        // 0x00000008 */
-#define STM32_GCCFG_PS2DET               STM32_GCCFG_PS2DET_Msk                   // DM pull-up detection status */
+#define STM32_GCCFG_PS2DET_Msk           (0x1UL << STM32_GCCFG_PS2DET_Pos)        // 0x00000008
+#define STM32_GCCFG_PS2DET               STM32_GCCFG_PS2DET_Msk                   // DM pull-up detection status
+
 #define STM32_GCCFG_PWRDWN_Pos           (16U)
-#define STM32_GCCFG_PWRDWN_Msk           (0x1UL << STM32_GCCFG_PWRDWN_Pos)        // 0x00010000 */
-#define STM32_GCCFG_PWRDWN               STM32_GCCFG_PWRDWN_Msk                   // Power down */
+#define STM32_GCCFG_PWRDWN_Msk           (0x1UL << STM32_GCCFG_PWRDWN_Pos)        // 0x00010000
+#define STM32_GCCFG_PWRDWN               STM32_GCCFG_PWRDWN_Msk                   // Power down
+
 #define STM32_GCCFG_BCDEN_Pos            (17U)
-#define STM32_GCCFG_BCDEN_Msk            (0x1UL << STM32_GCCFG_BCDEN_Pos)         // 0x00020000 */
-#define STM32_GCCFG_BCDEN                STM32_GCCFG_BCDEN_Msk                    // Battery charging detector (BCD) enable */
+#define STM32_GCCFG_BCDEN_Msk            (0x1UL << STM32_GCCFG_BCDEN_Pos)         // 0x00020000
+#define STM32_GCCFG_BCDEN                STM32_GCCFG_BCDEN_Msk                    // Battery charging detector (BCD) enable
+
 #define STM32_GCCFG_DCDEN_Pos            (18U)
-#define STM32_GCCFG_DCDEN_Msk            (0x1UL << STM32_GCCFG_DCDEN_Pos)         // 0x00040000 */
+#define STM32_GCCFG_DCDEN_Msk            (0x1UL << STM32_GCCFG_DCDEN_Pos)         // 0x00040000
 #define STM32_GCCFG_DCDEN                STM32_GCCFG_DCDEN_Msk                    // Data contact detection (DCD) mode enable*/
+
 #define STM32_GCCFG_PDEN_Pos             (19U)
-#define STM32_GCCFG_PDEN_Msk             (0x1UL << STM32_GCCFG_PDEN_Pos)          // 0x00080000 */
+#define STM32_GCCFG_PDEN_Msk             (0x1UL << STM32_GCCFG_PDEN_Pos)          // 0x00080000
 #define STM32_GCCFG_PDEN                 STM32_GCCFG_PDEN_Msk                     // Primary detection (PD) mode enable*/
+
 #define STM32_GCCFG_SDEN_Pos             (20U)
-#define STM32_GCCFG_SDEN_Msk             (0x1UL << STM32_GCCFG_SDEN_Pos)          // 0x00100000 */
-#define STM32_GCCFG_SDEN                 STM32_GCCFG_SDEN_Msk                     // Secondary detection (SD) mode enable */
+#define STM32_GCCFG_SDEN_Msk             (0x1UL << STM32_GCCFG_SDEN_Pos)          // 0x00100000
+#define STM32_GCCFG_SDEN                 STM32_GCCFG_SDEN_Msk                     // Secondary detection (SD) mode enable
+
 #define STM32_GCCFG_VBDEN_Pos            (21U)
-#define STM32_GCCFG_VBDEN_Msk            (0x1UL << STM32_GCCFG_VBDEN_Pos)         // 0x00200000 */
-#define STM32_GCCFG_VBDEN                STM32_GCCFG_VBDEN_Msk                    // VBUS mode enable */
+#define STM32_GCCFG_VBDEN_Msk            (0x1UL << STM32_GCCFG_VBDEN_Pos)         // 0x00200000
+#define STM32_GCCFG_VBDEN                STM32_GCCFG_VBDEN_Msk                    // VBUS mode enable
+
 #define STM32_GCCFG_OTGIDEN_Pos          (22U)
-#define STM32_GCCFG_OTGIDEN_Msk          (0x1UL << STM32_GCCFG_OTGIDEN_Pos)       // 0x00400000 */
-#define STM32_GCCFG_OTGIDEN              STM32_GCCFG_OTGIDEN_Msk                  // OTG Id enable */
+#define STM32_GCCFG_OTGIDEN_Msk          (0x1UL << STM32_GCCFG_OTGIDEN_Pos)       // 0x00400000
+#define STM32_GCCFG_OTGIDEN              STM32_GCCFG_OTGIDEN_Msk                  // OTG Id enable
+
 #define STM32_GCCFG_PHYHSEN_Pos          (23U)
-#define STM32_GCCFG_PHYHSEN_Msk          (0x1UL << STM32_GCCFG_PHYHSEN_Pos)       // 0x00800000 */
-#define STM32_GCCFG_PHYHSEN              STM32_GCCFG_PHYHSEN_Msk                  // HS PHY enable */
+#define STM32_GCCFG_PHYHSEN_Msk          (0x1UL << STM32_GCCFG_PHYHSEN_Pos)       // 0x00800000
+#define STM32_GCCFG_PHYHSEN              STM32_GCCFG_PHYHSEN_Msk                  // HS PHY enable
+
+// TODO stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
+//#define STM32_GCCFG_SDEN_Pos                   (22U)
+//#define STM32_GCCFG_SDEN_Msk                   (0x1U << STM32_GCCFG_SDEN_Pos)             // 0x00400000
+//#define STM32_GCCFG_SDEN                       STM32_GCCFG_SDEN_Msk                       // Secondary detection (PD) mode enable
+
+// TODO stm32u5a5 VBVALOVA is 23rd bit, conflict with PHYHSEN bit above
+#define STM32_GCCFG_VBVALOVAL_Pos              (23U)
+#define STM32_GCCFG_VBVALOVAL_Msk              (0x1U << STM32_GCCFG_VBVALOVAL_Pos)        // 0x00800000
+#define STM32_GCCFG_VBVALOVAL                  STM32_GCCFG_VBVALOVAL_Msk                  // Value of VBUSVLDEXT0 femtoPHY input
+
+#define STM32_GCCFG_VBVALEXTOEN_Pos            (24U)
+#define STM32_GCCFG_VBVALEXTOEN_Msk            (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos)      // 0x01000000
+#define STM32_GCCFG_VBVALEXTOEN                STM32_GCCFG_VBVALEXTOEN_Msk                // Enables of VBUSVLDEXT0 femtoPHY input override
+
+#define STM32_GCCFG_PULLDOWNEN_Pos             (25U)
+#define STM32_GCCFG_PULLDOWNEN_Msk             (0x1U << STM32_GCCFG_PULLDOWNEN_Pos)       // 0x02000000
+#define STM32_GCCFG_PULLDOWNEN                 STM32_GCCFG_PULLDOWNEN_Msk                 // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
+
 
 /********************  Bit definition for DEACHINTMSK register  ********************/
 #define DEACHINTMSK_IEP1INTM_Pos         (1U)
-#define DEACHINTMSK_IEP1INTM_Msk         (0x1UL << DEACHINTMSK_IEP1INTM_Pos)      // 0x00000002 */
-#define DEACHINTMSK_IEP1INTM             DEACHINTMSK_IEP1INTM_Msk                 // IN Endpoint 1 interrupt mask bit  */
+#define DEACHINTMSK_IEP1INTM_Msk         (0x1UL << DEACHINTMSK_IEP1INTM_Pos)      // 0x00000002
+#define DEACHINTMSK_IEP1INTM             DEACHINTMSK_IEP1INTM_Msk                 // IN Endpoint 1 interrupt mask bit
 #define DEACHINTMSK_OEP1INTM_Pos         (17U)
-#define DEACHINTMSK_OEP1INTM_Msk         (0x1UL << DEACHINTMSK_OEP1INTM_Pos)      // 0x00020000 */
-#define DEACHINTMSK_OEP1INTM             DEACHINTMSK_OEP1INTM_Msk                 // OUT Endpoint 1 interrupt mask bit */
+#define DEACHINTMSK_OEP1INTM_Msk         (0x1UL << DEACHINTMSK_OEP1INTM_Pos)      // 0x00020000
+#define DEACHINTMSK_OEP1INTM             DEACHINTMSK_OEP1INTM_Msk                 // OUT Endpoint 1 interrupt mask bit
 
 /********************  Bit definition for CID register  ********************/
 #define CID_PRODUCT_ID_Pos               (0U)
-#define CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos)     // 0xFFFFFFFF */
-#define CID_PRODUCT_ID                   CID_PRODUCT_ID_Msk                       // Product ID field */
+#define CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos)     // 0xFFFFFFFF
+#define CID_PRODUCT_ID                   CID_PRODUCT_ID_Msk                       // Product ID field
 
 /********************  Bit definition for GLPMCFG register  ********************/
 #define GLPMCFG_LPMEN_Pos                (0U)
-#define GLPMCFG_LPMEN_Msk                (0x1UL << GLPMCFG_LPMEN_Pos)             // 0x00000001 */
-#define GLPMCFG_LPMEN                    GLPMCFG_LPMEN_Msk                        // LPM support enable                                     */
+#define GLPMCFG_LPMEN_Msk                (0x1UL << GLPMCFG_LPMEN_Pos)             // 0x00000001
+#define GLPMCFG_LPMEN                    GLPMCFG_LPMEN_Msk                        // LPM support enable
 #define GLPMCFG_LPMACK_Pos               (1U)
-#define GLPMCFG_LPMACK_Msk               (0x1UL << GLPMCFG_LPMACK_Pos)            // 0x00000002 */
-#define GLPMCFG_LPMACK                   GLPMCFG_LPMACK_Msk                       // LPM Token acknowledge enable                           */
+#define GLPMCFG_LPMACK_Msk               (0x1UL << GLPMCFG_LPMACK_Pos)            // 0x00000002
+#define GLPMCFG_LPMACK                   GLPMCFG_LPMACK_Msk                       // LPM Token acknowledge enable
 #define GLPMCFG_BESL_Pos                 (2U)
-#define GLPMCFG_BESL_Msk                 (0xFUL << GLPMCFG_BESL_Pos)              // 0x0000003C */
-#define GLPMCFG_BESL                     GLPMCFG_BESL_Msk                         // BESL value received with last ACKed LPM Token          */
+#define GLPMCFG_BESL_Msk                 (0xFUL << GLPMCFG_BESL_Pos)              // 0x0000003C
+#define GLPMCFG_BESL                     GLPMCFG_BESL_Msk                         // BESL value received with last ACKed LPM Token
 #define GLPMCFG_REMWAKE_Pos              (6U)
-#define GLPMCFG_REMWAKE_Msk              (0x1UL << GLPMCFG_REMWAKE_Pos)           // 0x00000040 */
-#define GLPMCFG_REMWAKE                  GLPMCFG_REMWAKE_Msk                      // bRemoteWake value received with last ACKed LPM Token   */
+#define GLPMCFG_REMWAKE_Msk              (0x1UL << GLPMCFG_REMWAKE_Pos)           // 0x00000040
+#define GLPMCFG_REMWAKE                  GLPMCFG_REMWAKE_Msk                      // bRemoteWake value received with last ACKed LPM Token
 #define GLPMCFG_L1SSEN_Pos               (7U)
-#define GLPMCFG_L1SSEN_Msk               (0x1UL << GLPMCFG_L1SSEN_Pos)            // 0x00000080 */
-#define GLPMCFG_L1SSEN                   GLPMCFG_L1SSEN_Msk                       // L1 shallow sleep enable                                */
+#define GLPMCFG_L1SSEN_Msk               (0x1UL << GLPMCFG_L1SSEN_Pos)            // 0x00000080
+#define GLPMCFG_L1SSEN                   GLPMCFG_L1SSEN_Msk                       // L1 shallow sleep enable
 #define GLPMCFG_BESLTHRS_Pos             (8U)
-#define GLPMCFG_BESLTHRS_Msk             (0xFUL << GLPMCFG_BESLTHRS_Pos)          // 0x00000F00 */
-#define GLPMCFG_BESLTHRS                 GLPMCFG_BESLTHRS_Msk                     // BESL threshold                                         */
+#define GLPMCFG_BESLTHRS_Msk             (0xFUL << GLPMCFG_BESLTHRS_Pos)          // 0x00000F00
+#define GLPMCFG_BESLTHRS                 GLPMCFG_BESLTHRS_Msk                     // BESL threshold
 #define GLPMCFG_L1DSEN_Pos               (12U)
-#define GLPMCFG_L1DSEN_Msk               (0x1UL << GLPMCFG_L1DSEN_Pos)            // 0x00001000 */
-#define GLPMCFG_L1DSEN                   GLPMCFG_L1DSEN_Msk                       // L1 deep sleep enable                                   */
+#define GLPMCFG_L1DSEN_Msk               (0x1UL << GLPMCFG_L1DSEN_Pos)            // 0x00001000
+#define GLPMCFG_L1DSEN                   GLPMCFG_L1DSEN_Msk                       // L1 deep sleep enable
 #define GLPMCFG_LPMRSP_Pos               (13U)
-#define GLPMCFG_LPMRSP_Msk               (0x3UL << GLPMCFG_LPMRSP_Pos)            // 0x00006000 */
-#define GLPMCFG_LPMRSP                   GLPMCFG_LPMRSP_Msk                       // LPM response                                           */
+#define GLPMCFG_LPMRSP_Msk               (0x3UL << GLPMCFG_LPMRSP_Pos)            // 0x00006000
+#define GLPMCFG_LPMRSP                   GLPMCFG_LPMRSP_Msk                       // LPM response
 #define GLPMCFG_SLPSTS_Pos               (15U)
-#define GLPMCFG_SLPSTS_Msk               (0x1UL << GLPMCFG_SLPSTS_Pos)            // 0x00008000 */
-#define GLPMCFG_SLPSTS                   GLPMCFG_SLPSTS_Msk                       // Port sleep status                                      */
+#define GLPMCFG_SLPSTS_Msk               (0x1UL << GLPMCFG_SLPSTS_Pos)            // 0x00008000
+#define GLPMCFG_SLPSTS                   GLPMCFG_SLPSTS_Msk                       // Port sleep status
 #define GLPMCFG_L1RSMOK_Pos              (16U)
-#define GLPMCFG_L1RSMOK_Msk              (0x1UL << GLPMCFG_L1RSMOK_Pos)           // 0x00010000 */
-#define GLPMCFG_L1RSMOK                  GLPMCFG_L1RSMOK_Msk                      // Sleep State Resume OK                                  */
+#define GLPMCFG_L1RSMOK_Msk              (0x1UL << GLPMCFG_L1RSMOK_Pos)           // 0x00010000
+#define GLPMCFG_L1RSMOK                  GLPMCFG_L1RSMOK_Msk                      // Sleep State Resume OK
 #define GLPMCFG_LPMCHIDX_Pos             (17U)
-#define GLPMCFG_LPMCHIDX_Msk             (0xFUL << GLPMCFG_LPMCHIDX_Pos)          // 0x001E0000 */
-#define GLPMCFG_LPMCHIDX                 GLPMCFG_LPMCHIDX_Msk                     // LPM Channel Index                                      */
+#define GLPMCFG_LPMCHIDX_Msk             (0xFUL << GLPMCFG_LPMCHIDX_Pos)          // 0x001E0000
+#define GLPMCFG_LPMCHIDX                 GLPMCFG_LPMCHIDX_Msk                     // LPM Channel Index
 #define GLPMCFG_LPMRCNT_Pos              (21U)
-#define GLPMCFG_LPMRCNT_Msk              (0x7UL << GLPMCFG_LPMRCNT_Pos)           // 0x00E00000 */
-#define GLPMCFG_LPMRCNT                  GLPMCFG_LPMRCNT_Msk                      // LPM retry count                                        */
+#define GLPMCFG_LPMRCNT_Msk              (0x7UL << GLPMCFG_LPMRCNT_Pos)           // 0x00E00000
+#define GLPMCFG_LPMRCNT                  GLPMCFG_LPMRCNT_Msk                      // LPM retry count
 #define GLPMCFG_SNDLPM_Pos               (24U)
-#define GLPMCFG_SNDLPM_Msk               (0x1UL << GLPMCFG_SNDLPM_Pos)            // 0x01000000 */
-#define GLPMCFG_SNDLPM                   GLPMCFG_SNDLPM_Msk                       // Send LPM transaction                                   */
+#define GLPMCFG_SNDLPM_Msk               (0x1UL << GLPMCFG_SNDLPM_Pos)            // 0x01000000
+#define GLPMCFG_SNDLPM                   GLPMCFG_SNDLPM_Msk                       // Send LPM transaction
 #define GLPMCFG_LPMRCNTSTS_Pos           (25U)
-#define GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << GLPMCFG_LPMRCNTSTS_Pos)        // 0x0E000000 */
-#define GLPMCFG_LPMRCNTSTS               GLPMCFG_LPMRCNTSTS_Msk                   // LPM retry count status                                 */
+#define GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << GLPMCFG_LPMRCNTSTS_Pos)        // 0x0E000000
+#define GLPMCFG_LPMRCNTSTS               GLPMCFG_LPMRCNTSTS_Msk                   // LPM retry count status
 #define GLPMCFG_ENBESL_Pos               (28U)
-#define GLPMCFG_ENBESL_Msk               (0x1UL << GLPMCFG_ENBESL_Pos)            // 0x10000000 */
-#define GLPMCFG_ENBESL                   GLPMCFG_ENBESL_Msk                       // Enable best effort service latency                     */
+#define GLPMCFG_ENBESL_Msk               (0x1UL << GLPMCFG_ENBESL_Pos)            // 0x10000000
+#define GLPMCFG_ENBESL                   GLPMCFG_ENBESL_Msk                       // Enable best effort service latency
+
+// GDFIFOCFG
+#define GDFIFOCFG_EPINFOBASE_MASK   (0xffff << 16)
+#define GDFIFOCFG_EPINFOBASE_SHIFT  16
+#define GDFIFOCFG_GDFIFOCFG_MASK    (0xffff << 0)
+#define GDFIFOCFG_GDFIFOCFG_SHIFT   0
 
 /********************  Bit definition for DIEPEACHMSK1 register  ********************/
 #define DIEPEACHMSK1_XFRCM_Pos           (0U)
-#define DIEPEACHMSK1_XFRCM_Msk           (0x1UL << DIEPEACHMSK1_XFRCM_Pos)        // 0x00000001 */
-#define DIEPEACHMSK1_XFRCM               DIEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask                 */
+#define DIEPEACHMSK1_XFRCM_Msk           (0x1UL << DIEPEACHMSK1_XFRCM_Pos)        // 0x00000001
+#define DIEPEACHMSK1_XFRCM               DIEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask
 #define DIEPEACHMSK1_EPDM_Pos            (1U)
-#define DIEPEACHMSK1_EPDM_Msk            (0x1UL << DIEPEACHMSK1_EPDM_Pos)         // 0x00000002 */
-#define DIEPEACHMSK1_EPDM                DIEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask                  */
+#define DIEPEACHMSK1_EPDM_Msk            (0x1UL << DIEPEACHMSK1_EPDM_Pos)         // 0x00000002
+#define DIEPEACHMSK1_EPDM                DIEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask
 #define DIEPEACHMSK1_TOM_Pos             (3U)
-#define DIEPEACHMSK1_TOM_Msk             (0x1UL << DIEPEACHMSK1_TOM_Pos)          // 0x00000008 */
-#define DIEPEACHMSK1_TOM                 DIEPEACHMSK1_TOM_Msk                     // Timeout condition mask (nonisochronous endpoints) */
+#define DIEPEACHMSK1_TOM_Msk             (0x1UL << DIEPEACHMSK1_TOM_Pos)          // 0x00000008
+#define DIEPEACHMSK1_TOM                 DIEPEACHMSK1_TOM_Msk                     // Timeout condition mask (nonisochronous endpoints)
 #define DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
-#define DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010 */
-#define DIEPEACHMSK1_ITTXFEMSK           DIEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask          */
+#define DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010
+#define DIEPEACHMSK1_ITTXFEMSK           DIEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask
 #define DIEPEACHMSK1_INEPNMM_Pos         (5U)
-#define DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << DIEPEACHMSK1_INEPNMM_Pos)      // 0x00000020 */
-#define DIEPEACHMSK1_INEPNMM             DIEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask           */
+#define DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << DIEPEACHMSK1_INEPNMM_Pos)      // 0x00000020
+#define DIEPEACHMSK1_INEPNMM             DIEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask
 #define DIEPEACHMSK1_INEPNEM_Pos         (6U)
-#define DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << DIEPEACHMSK1_INEPNEM_Pos)      // 0x00000040 */
-#define DIEPEACHMSK1_INEPNEM             DIEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask                    */
+#define DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << DIEPEACHMSK1_INEPNEM_Pos)      // 0x00000040
+#define DIEPEACHMSK1_INEPNEM             DIEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask
 #define DIEPEACHMSK1_TXFURM_Pos          (8U)
-#define DIEPEACHMSK1_TXFURM_Msk          (0x1UL << DIEPEACHMSK1_TXFURM_Pos)       // 0x00000100 */
-#define DIEPEACHMSK1_TXFURM              DIEPEACHMSK1_TXFURM_Msk                  // FIFO underrun mask                                */
+#define DIEPEACHMSK1_TXFURM_Msk          (0x1UL << DIEPEACHMSK1_TXFURM_Pos)       // 0x00000100
+#define DIEPEACHMSK1_TXFURM              DIEPEACHMSK1_TXFURM_Msk                  // FIFO underrun mask
 #define DIEPEACHMSK1_BIM_Pos             (9U)
-#define DIEPEACHMSK1_BIM_Msk             (0x1UL << DIEPEACHMSK1_BIM_Pos)          // 0x00000200 */
-#define DIEPEACHMSK1_BIM                 DIEPEACHMSK1_BIM_Msk                     // BNA interrupt mask                                */
+#define DIEPEACHMSK1_BIM_Msk             (0x1UL << DIEPEACHMSK1_BIM_Pos)          // 0x00000200
+#define DIEPEACHMSK1_BIM                 DIEPEACHMSK1_BIM_Msk                     // BNA interrupt mask
 #define DIEPEACHMSK1_NAKM_Pos            (13U)
-#define DIEPEACHMSK1_NAKM_Msk            (0x1UL << DIEPEACHMSK1_NAKM_Pos)         // 0x00002000 */
-#define DIEPEACHMSK1_NAKM                DIEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask                                */
+#define DIEPEACHMSK1_NAKM_Msk            (0x1UL << DIEPEACHMSK1_NAKM_Pos)         // 0x00002000
+#define DIEPEACHMSK1_NAKM                DIEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask
 
 /********************  Bit definition for HPRT register  ********************/
-#define HPRT_PCSTS_Pos                   (0U)
-#define HPRT_PCSTS_Msk                   (0x1UL << HPRT_PCSTS_Pos)                // 0x00000001 */
-#define HPRT_PCSTS                       HPRT_PCSTS_Msk                           // Port connect status        */
-#define HPRT_PCDET_Pos                   (1U)
-#define HPRT_PCDET_Msk                   (0x1UL << HPRT_PCDET_Pos)                // 0x00000002 */
-#define HPRT_PCDET                       HPRT_PCDET_Msk                           // Port connect detected      */
-#define HPRT_PENA_Pos                    (2U)
-#define HPRT_PENA_Msk                    (0x1UL << HPRT_PENA_Pos)                 // 0x00000004 */
-#define HPRT_PENA                        HPRT_PENA_Msk                            // Port enable                */
-#define HPRT_PENCHNG_Pos                 (3U)
-#define HPRT_PENCHNG_Msk                 (0x1UL << HPRT_PENCHNG_Pos)              // 0x00000008 */
-#define HPRT_PENCHNG                     HPRT_PENCHNG_Msk                         // Port enable/disable change */
-#define HPRT_POCA_Pos                    (4U)
-#define HPRT_POCA_Msk                    (0x1UL << HPRT_POCA_Pos)                 // 0x00000010 */
-#define HPRT_POCA                        HPRT_POCA_Msk                            // Port overcurrent active    */
-#define HPRT_POCCHNG_Pos                 (5U)
-#define HPRT_POCCHNG_Msk                 (0x1UL << HPRT_POCCHNG_Pos)              // 0x00000020 */
-#define HPRT_POCCHNG                     HPRT_POCCHNG_Msk                         // Port overcurrent change    */
-#define HPRT_PRES_Pos                    (6U)
-#define HPRT_PRES_Msk                    (0x1UL << HPRT_PRES_Pos)                 // 0x00000040 */
-#define HPRT_PRES                        HPRT_PRES_Msk                            // Port resume                */
-#define HPRT_PSUSP_Pos                   (7U)
-#define HPRT_PSUSP_Msk                   (0x1UL << HPRT_PSUSP_Pos)                // 0x00000080 */
-#define HPRT_PSUSP                       HPRT_PSUSP_Msk                           // Port suspend               */
-#define HPRT_PRST_Pos                    (8U)
-#define HPRT_PRST_Msk                    (0x1UL << HPRT_PRST_Pos)                 // 0x00000100 */
-#define HPRT_PRST                        HPRT_PRST_Msk                            // Port reset                 */
-
-#define HPRT_PLSTS_Pos                   (10U)
-#define HPRT_PLSTS_Msk                   (0x3UL << HPRT_PLSTS_Pos)                // 0x00000C00 */
-#define HPRT_PLSTS                       HPRT_PLSTS_Msk                           // Port line status           */
-#define HPRT_PLSTS_0                     (0x1UL << HPRT_PLSTS_Pos)                // 0x00000400 */
-#define HPRT_PLSTS_1                     (0x2UL << HPRT_PLSTS_Pos)                // 0x00000800 */
-#define HPRT_PPWR_Pos                    (12U)
-#define HPRT_PPWR_Msk                    (0x1UL << HPRT_PPWR_Pos)                 // 0x00001000 */
-#define HPRT_PPWR                        HPRT_PPWR_Msk                            // Port power                 */
-
-#define HPRT_PTCTL_Pos                   (13U)
-#define HPRT_PTCTL_Msk                   (0xFUL << HPRT_PTCTL_Pos)                // 0x0001E000 */
-#define HPRT_PTCTL                       HPRT_PTCTL_Msk                           // Port test control          */
-#define HPRT_PTCTL_0                     (0x1UL << HPRT_PTCTL_Pos)                // 0x00002000 */
-#define HPRT_PTCTL_1                     (0x2UL << HPRT_PTCTL_Pos)                // 0x00004000 */
-#define HPRT_PTCTL_2                     (0x4UL << HPRT_PTCTL_Pos)                // 0x00008000 */
-#define HPRT_PTCTL_3                     (0x8UL << HPRT_PTCTL_Pos)                // 0x00010000 */
-
-#define HPRT_PSPD_Pos                    (17U)
-#define HPRT_PSPD_Msk                    (0x3UL << HPRT_PSPD_Pos)                 // 0x00060000 */
-#define HPRT_PSPD                        HPRT_PSPD_Msk                            // Port speed                 */
-#define HPRT_PSPD_0                      (0x1UL << HPRT_PSPD_Pos)                 // 0x00020000 */
-#define HPRT_PSPD_1                      (0x2UL << HPRT_PSPD_Pos)                 // 0x00040000 */
+#define HPRT_CONN_STATUS_Pos           (0U)
+#define HPRT_CONN_STATUS_Msk           (0x1UL << HPRT_CONN_STATUS_Pos)         // 0x00000001
+#define HPRT_CONN_STATUS               HPRT_CONN_STATUS_Msk                    // Port connect status
+#define HPRT_CONN_DETECT_Pos           (1U)
+#define HPRT_CONN_DETECT_Msk           (0x1UL << HPRT_CONN_DETECT_Pos)         // 0x00000002
+#define HPRT_CONN_DETECT               HPRT_CONN_DETECT_Msk                    // Port connect detected
+#define HPRT_ENABLE_Pos                (2U)
+#define HPRT_ENABLE_Msk                (0x1UL << HPRT_ENABLE_Pos)              // 0x00000004
+#define HPRT_ENABLE                    HPRT_ENABLE_Msk                         // Port enable
+#define HPRT_ENABLE_CHANGE_Pos         (3U)
+#define HPRT_ENABLE_CHANGE_Msk         (0x1UL << HPRT_ENABLE_CHANGE_Pos)       // 0x00000008
+#define HPRT_ENABLE_CHANGE             HPRT_ENABLE_CHANGE_Msk                  // Port enable/disable change
+#define HPRT_OVER_CURRENT_ACTIVE_Pos   (4U)
+#define HPRT_OVER_CURRENT_ACTIVE_Msk   (0x1UL << HPRT_OVER_CURRENT_ACTIVE_Pos) // 0x00000010
+#define HPRT_OVER_CURRENT_ACTIVE       HPRT_OVER_CURRENT_ACTIVE_Msk            // Port overcurrent active
+#define HPRT_OVER_CURRENT_CHANGE_Pos   (5U)
+#define HPRT_OVER_CURRENT_CHANGE_Msk   (0x1UL << HPRT_OVER_CURRENT_CHANGE_Pos) // 0x00000020
+#define HPRT_OVER_CURRENT_CHANGE       HPRT_OVER_CURRENT_CHANGE_Msk            // Port overcurrent change
+#define HPRT_RESUME_Pos                (6U)
+#define HPRT_RESUME_Msk                (0x1UL << HPRT_RESUME_Pos)              // 0x00000040
+#define HPRT_RESUME                    HPRT_RESUME_Msk                         // Port resume
+#define HPRT_SUSPEND_Pos               (7U)
+#define HPRT_SUSPEND_Msk               (0x1UL << HPRT_SUSPEND_Pos)             // 0x00000080
+#define HPRT_SUSPEND                   HPRT_SUSPEND_Msk                        // Port suspend
+#define HPRT_RESET_Pos                 (8U)
+#define HPRT_RESET_Msk                 (0x1UL << HPRT_RESET_Pos)               // 0x00000100
+#define HPRT_RESET                     HPRT_RESET_Msk                          // Port reset
+#define HPRT_LINE_STATUS_Pos           (10U)
+#define HPRT_LINE_STATUS_Msk           (0x3UL << HPRT_LINE_STATUS_Pos)         // 0x00000C00
+#define HPRT_LINE_STATUS               HPRT_LINE_STATUS_Msk                    // Port line status
+#define HPRT_LINE_STATUS_0             (0x1UL << HPRT_LINE_STATUS_Pos)         // 0x00000400
+#define HPRT_LINE_STATUS_1             (0x2UL << HPRT_LINE_STATUS_Pos)         // 0x00000800
+#define HPRT_POWER_Pos                 (12U)
+#define HPRT_POWER_Msk                 (0x1UL << HPRT_POWER_Pos)               // 0x00001000
+#define HPRT_POWER                     HPRT_POWER_Msk                          // Port power
+#define HPRT_TEST_CONTROL_Pos          (13U)
+#define HPRT_TEST_CONTROL_Msk          (0xFUL << HPRT_TEST_CONTROL_Pos)        // 0x0001E000
+#define HPRT_TEST_CONTROL              HPRT_TEST_CONTROL_Msk                   // Port test control
+#define HPRT_TEST_CONTROL_0            (0x1UL << HPRT_TEST_CONTROL_Pos)        // 0x00002000
+#define HPRT_TEST_CONTROL_1            (0x2UL << HPRT_TEST_CONTROL_Pos)        // 0x00004000
+#define HPRT_TEST_CONTROL_2            (0x4UL << HPRT_TEST_CONTROL_Pos)        // 0x00008000
+#define HPRT_TEST_CONTROL_3            (0x8UL << HPRT_TEST_CONTROL_Pos)        // 0x00010000
+#define HPRT_SPEED_Pos                 (17U)
+#define HPRT_SPEED_Msk                 (0x3UL << HPRT_SPEED_Pos)               // 0x00060000
+#define HPRT_SPEED                     HPRT_SPEED_Msk                          // Port speed
+#define HPRT_SPEED_0                   (0x1UL << HPRT_SPEED_Pos)               // 0x00020000
+#define HPRT_SPEED_1                   (0x2UL << HPRT_SPEED_Pos)               // 0x00040000
 
 /********************  Bit definition for DOEPEACHMSK1 register  ********************/
 #define DOEPEACHMSK1_XFRCM_Pos           (0U)
-#define DOEPEACHMSK1_XFRCM_Msk           (0x1UL << DOEPEACHMSK1_XFRCM_Pos)        // 0x00000001 */
-#define DOEPEACHMSK1_XFRCM               DOEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask         */
+#define DOEPEACHMSK1_XFRCM_Msk           (0x1UL << DOEPEACHMSK1_XFRCM_Pos)        // 0x00000001
+#define DOEPEACHMSK1_XFRCM               DOEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask
 #define DOEPEACHMSK1_EPDM_Pos            (1U)
-#define DOEPEACHMSK1_EPDM_Msk            (0x1UL << DOEPEACHMSK1_EPDM_Pos)         // 0x00000002 */
-#define DOEPEACHMSK1_EPDM                DOEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask          */
+#define DOEPEACHMSK1_EPDM_Msk            (0x1UL << DOEPEACHMSK1_EPDM_Pos)         // 0x00000002
+#define DOEPEACHMSK1_EPDM                DOEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask
 #define DOEPEACHMSK1_TOM_Pos             (3U)
-#define DOEPEACHMSK1_TOM_Msk             (0x1UL << DOEPEACHMSK1_TOM_Pos)          // 0x00000008 */
-#define DOEPEACHMSK1_TOM                 DOEPEACHMSK1_TOM_Msk                     // Timeout condition mask                    */
+#define DOEPEACHMSK1_TOM_Msk             (0x1UL << DOEPEACHMSK1_TOM_Pos)          // 0x00000008
+#define DOEPEACHMSK1_TOM                 DOEPEACHMSK1_TOM_Msk                     // Timeout condition mask
 #define DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
-#define DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010 */
-#define DOEPEACHMSK1_ITTXFEMSK           DOEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask  */
+#define DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010
+#define DOEPEACHMSK1_ITTXFEMSK           DOEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask
 #define DOEPEACHMSK1_INEPNMM_Pos         (5U)
-#define DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << DOEPEACHMSK1_INEPNMM_Pos)      // 0x00000020 */
-#define DOEPEACHMSK1_INEPNMM             DOEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask   */
+#define DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << DOEPEACHMSK1_INEPNMM_Pos)      // 0x00000020
+#define DOEPEACHMSK1_INEPNMM             DOEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask
 #define DOEPEACHMSK1_INEPNEM_Pos         (6U)
-#define DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << DOEPEACHMSK1_INEPNEM_Pos)      // 0x00000040 */
-#define DOEPEACHMSK1_INEPNEM             DOEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask            */
+#define DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << DOEPEACHMSK1_INEPNEM_Pos)      // 0x00000040
+#define DOEPEACHMSK1_INEPNEM             DOEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask
 #define DOEPEACHMSK1_TXFURM_Pos          (8U)
-#define DOEPEACHMSK1_TXFURM_Msk          (0x1UL << DOEPEACHMSK1_TXFURM_Pos)       // 0x00000100 */
-#define DOEPEACHMSK1_TXFURM              DOEPEACHMSK1_TXFURM_Msk                  // OUT packet error mask                     */
+#define DOEPEACHMSK1_TXFURM_Msk          (0x1UL << DOEPEACHMSK1_TXFURM_Pos)       // 0x00000100
+#define DOEPEACHMSK1_TXFURM              DOEPEACHMSK1_TXFURM_Msk                  // OUT packet error mask
 #define DOEPEACHMSK1_BIM_Pos             (9U)
-#define DOEPEACHMSK1_BIM_Msk             (0x1UL << DOEPEACHMSK1_BIM_Pos)          // 0x00000200 */
-#define DOEPEACHMSK1_BIM                 DOEPEACHMSK1_BIM_Msk                     // BNA interrupt mask                        */
+#define DOEPEACHMSK1_BIM_Msk             (0x1UL << DOEPEACHMSK1_BIM_Pos)          // 0x00000200
+#define DOEPEACHMSK1_BIM                 DOEPEACHMSK1_BIM_Msk                     // BNA interrupt mask
 #define DOEPEACHMSK1_BERRM_Pos           (12U)
-#define DOEPEACHMSK1_BERRM_Msk           (0x1UL << DOEPEACHMSK1_BERRM_Pos)        // 0x00001000 */
-#define DOEPEACHMSK1_BERRM               DOEPEACHMSK1_BERRM_Msk                   // Bubble error interrupt mask               */
+#define DOEPEACHMSK1_BERRM_Msk           (0x1UL << DOEPEACHMSK1_BERRM_Pos)        // 0x00001000
+#define DOEPEACHMSK1_BERRM               DOEPEACHMSK1_BERRM_Msk                   // Bubble error interrupt mask
 #define DOEPEACHMSK1_NAKM_Pos            (13U)
-#define DOEPEACHMSK1_NAKM_Msk            (0x1UL << DOEPEACHMSK1_NAKM_Pos)         // 0x00002000 */
-#define DOEPEACHMSK1_NAKM                DOEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask                        */
+#define DOEPEACHMSK1_NAKM_Msk            (0x1UL << DOEPEACHMSK1_NAKM_Pos)         // 0x00002000
+#define DOEPEACHMSK1_NAKM                DOEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask
 #define DOEPEACHMSK1_NYETM_Pos           (14U)
-#define DOEPEACHMSK1_NYETM_Msk           (0x1UL << DOEPEACHMSK1_NYETM_Pos)        // 0x00004000 */
-#define DOEPEACHMSK1_NYETM               DOEPEACHMSK1_NYETM_Msk                   // NYET interrupt mask                       */
+#define DOEPEACHMSK1_NYETM_Msk           (0x1UL << DOEPEACHMSK1_NYETM_Pos)        // 0x00004000
+#define DOEPEACHMSK1_NYETM               DOEPEACHMSK1_NYETM_Msk                   // NYET interrupt mask
 
 /********************  Bit definition for HPTXFSIZ register  ********************/
 #define HPTXFSIZ_PTXSA_Pos               (0U)
-#define HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << HPTXFSIZ_PTXSA_Pos)         // 0x0000FFFF */
-#define HPTXFSIZ_PTXSA                   HPTXFSIZ_PTXSA_Msk                       // Host periodic TxFIFO start address            */
+#define HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << HPTXFSIZ_PTXSA_Pos)         // 0x0000FFFF
+#define HPTXFSIZ_PTXSA                   HPTXFSIZ_PTXSA_Msk                       // Host periodic TxFIFO start address
 #define HPTXFSIZ_PTXFD_Pos               (16U)
-#define HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << HPTXFSIZ_PTXFD_Pos)         // 0xFFFF0000 */
-#define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk                       // Host periodic TxFIFO depth                    */
+#define HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << HPTXFSIZ_PTXFD_Pos)         // 0xFFFF0000
+#define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk                       // Host periodic TxFIFO depth
 
 /********************  Bit definition for DIEPCTL register  ********************/
 #define DIEPCTL_MPSIZ_Pos                (0U)
-#define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos)           // 0x000007FF */
-#define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk                        // Maximum packet size              */
+#define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos)           // 0x000007FF
+#define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk                        // Maximum packet size
 #define DIEPCTL_USBAEP_Pos               (15U)
-#define DIEPCTL_USBAEP_Msk               (0x1UL << DIEPCTL_USBAEP_Pos)            // 0x00008000 */
-#define DIEPCTL_USBAEP                   DIEPCTL_USBAEP_Msk                       // USB active endpoint              */
+#define DIEPCTL_USBAEP_Msk               (0x1UL << DIEPCTL_USBAEP_Pos)            // 0x00008000
+#define DIEPCTL_USBAEP                   DIEPCTL_USBAEP_Msk                       // USB active endpoint
 #define DIEPCTL_EONUM_DPID_Pos           (16U)
-#define DIEPCTL_EONUM_DPID_Msk           (0x1UL << DIEPCTL_EONUM_DPID_Pos)        // 0x00010000 */
-#define DIEPCTL_EONUM_DPID               DIEPCTL_EONUM_DPID_Msk                   // Even/odd frame                   */
+#define DIEPCTL_EONUM_DPID_Msk           (0x1UL << DIEPCTL_EONUM_DPID_Pos)        // 0x00010000
+#define DIEPCTL_EONUM_DPID               DIEPCTL_EONUM_DPID_Msk                   // Even/odd frame
 #define DIEPCTL_NAKSTS_Pos               (17U)
-#define DIEPCTL_NAKSTS_Msk               (0x1UL << DIEPCTL_NAKSTS_Pos)            // 0x00020000 */
-#define DIEPCTL_NAKSTS                   DIEPCTL_NAKSTS_Msk                       // NAK status                       */
+#define DIEPCTL_NAKSTS_Msk               (0x1UL << DIEPCTL_NAKSTS_Pos)            // 0x00020000
+#define DIEPCTL_NAKSTS                   DIEPCTL_NAKSTS_Msk                       // NAK status
 
 #define DIEPCTL_EPTYP_Pos                (18U)
-#define DIEPCTL_EPTYP_Msk                (0x3UL << DIEPCTL_EPTYP_Pos)             // 0x000C0000 */
-#define DIEPCTL_EPTYP                    DIEPCTL_EPTYP_Msk                        // Endpoint type                    */
-#define DIEPCTL_EPTYP_0                  (0x1UL << DIEPCTL_EPTYP_Pos)             // 0x00040000 */
-#define DIEPCTL_EPTYP_1                  (0x2UL << DIEPCTL_EPTYP_Pos)             // 0x00080000 */
+#define DIEPCTL_EPTYP_Msk                (0x3UL << DIEPCTL_EPTYP_Pos)             // 0x000C0000
+#define DIEPCTL_EPTYP                    DIEPCTL_EPTYP_Msk                        // Endpoint type
+#define DIEPCTL_EPTYP_0                  (0x1UL << DIEPCTL_EPTYP_Pos)             // 0x00040000
+#define DIEPCTL_EPTYP_1                  (0x2UL << DIEPCTL_EPTYP_Pos)             // 0x00080000
 #define DIEPCTL_STALL_Pos                (21U)
-#define DIEPCTL_STALL_Msk                (0x1UL << DIEPCTL_STALL_Pos)             // 0x00200000 */
-#define DIEPCTL_STALL                    DIEPCTL_STALL_Msk                        // STALL handshake                  */
+#define DIEPCTL_STALL_Msk                (0x1UL << DIEPCTL_STALL_Pos)             // 0x00200000
+#define DIEPCTL_STALL                    DIEPCTL_STALL_Msk                        // STALL handshake
 
 #define DIEPCTL_TXFNUM_Pos               (22U)
-#define DIEPCTL_TXFNUM_Msk               (0xFUL << DIEPCTL_TXFNUM_Pos)            // 0x03C00000 */
-#define DIEPCTL_TXFNUM                   DIEPCTL_TXFNUM_Msk                       // TxFIFO number                    */
-#define DIEPCTL_TXFNUM_0                 (0x1UL << DIEPCTL_TXFNUM_Pos)            // 0x00400000 */
-#define DIEPCTL_TXFNUM_1                 (0x2UL << DIEPCTL_TXFNUM_Pos)            // 0x00800000 */
-#define DIEPCTL_TXFNUM_2                 (0x4UL << DIEPCTL_TXFNUM_Pos)            // 0x01000000 */
-#define DIEPCTL_TXFNUM_3                 (0x8UL << DIEPCTL_TXFNUM_Pos)            // 0x02000000 */
+#define DIEPCTL_TXFNUM_Msk               (0xFUL << DIEPCTL_TXFNUM_Pos)            // 0x03C00000
+#define DIEPCTL_TXFNUM                   DIEPCTL_TXFNUM_Msk                       // TxFIFO number
+#define DIEPCTL_TXFNUM_0                 (0x1UL << DIEPCTL_TXFNUM_Pos)            // 0x00400000
+#define DIEPCTL_TXFNUM_1                 (0x2UL << DIEPCTL_TXFNUM_Pos)            // 0x00800000
+#define DIEPCTL_TXFNUM_2                 (0x4UL << DIEPCTL_TXFNUM_Pos)            // 0x01000000
+#define DIEPCTL_TXFNUM_3                 (0x8UL << DIEPCTL_TXFNUM_Pos)            // 0x02000000
 #define DIEPCTL_CNAK_Pos                 (26U)
-#define DIEPCTL_CNAK_Msk                 (0x1UL << DIEPCTL_CNAK_Pos)              // 0x04000000 */
-#define DIEPCTL_CNAK                     DIEPCTL_CNAK_Msk                         // Clear NAK                        */
+#define DIEPCTL_CNAK_Msk                 (0x1UL << DIEPCTL_CNAK_Pos)              // 0x04000000
+#define DIEPCTL_CNAK                     DIEPCTL_CNAK_Msk                         // Clear NAK
 #define DIEPCTL_SNAK_Pos                 (27U)
-#define DIEPCTL_SNAK_Msk                 (0x1UL << DIEPCTL_SNAK_Pos)              // 0x08000000 */
-#define DIEPCTL_SNAK                     DIEPCTL_SNAK_Msk                         // Set NAK */
+#define DIEPCTL_SNAK_Msk                 (0x1UL << DIEPCTL_SNAK_Pos)              // 0x08000000
+#define DIEPCTL_SNAK                     DIEPCTL_SNAK_Msk                         // Set NAK
 #define DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
-#define DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000 */
-#define DIEPCTL_SD0PID_SEVNFRM           DIEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID                    */
+#define DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000
+#define DIEPCTL_SD0PID_SEVNFRM           DIEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID
 #define DIEPCTL_SODDFRM_Pos              (29U)
-#define DIEPCTL_SODDFRM_Msk              (0x1UL << DIEPCTL_SODDFRM_Pos)           // 0x20000000 */
-#define DIEPCTL_SODDFRM                  DIEPCTL_SODDFRM_Msk                      // Set odd frame                    */
+#define DIEPCTL_SODDFRM_Msk              (0x1UL << DIEPCTL_SODDFRM_Pos)           // 0x20000000
+#define DIEPCTL_SODDFRM                  DIEPCTL_SODDFRM_Msk                      // Set odd frame
 #define DIEPCTL_EPDIS_Pos                (30U)
-#define DIEPCTL_EPDIS_Msk                (0x1UL << DIEPCTL_EPDIS_Pos)             // 0x40000000 */
-#define DIEPCTL_EPDIS                    DIEPCTL_EPDIS_Msk                        // Endpoint disable                 */
+#define DIEPCTL_EPDIS_Msk                (0x1UL << DIEPCTL_EPDIS_Pos)             // 0x40000000
+#define DIEPCTL_EPDIS                    DIEPCTL_EPDIS_Msk                        // Endpoint disable
 #define DIEPCTL_EPENA_Pos                (31U)
-#define DIEPCTL_EPENA_Msk                (0x1UL << DIEPCTL_EPENA_Pos)             // 0x80000000 */
-#define DIEPCTL_EPENA                    DIEPCTL_EPENA_Msk                        // Endpoint enable                  */
+#define DIEPCTL_EPENA_Msk                (0x1UL << DIEPCTL_EPENA_Pos)             // 0x80000000
+#define DIEPCTL_EPENA                    DIEPCTL_EPENA_Msk                        // Endpoint enable
 
 /********************  Bit definition for HCCHAR register  ********************/
 #define HCCHAR_MPSIZ_Pos                 (0U)
-#define HCCHAR_MPSIZ_Msk                 (0x7FFUL << HCCHAR_MPSIZ_Pos)            // 0x000007FF */
-#define HCCHAR_MPSIZ                     HCCHAR_MPSIZ_Msk                         // Maximum packet size */
+#define HCCHAR_MPSIZ_Msk                 (0x7FFUL << HCCHAR_MPSIZ_Pos)            // 0x000007FF
+#define HCCHAR_MPSIZ                     HCCHAR_MPSIZ_Msk                         // Maximum packet size
 
 #define HCCHAR_EPNUM_Pos                 (11U)
-#define HCCHAR_EPNUM_Msk                 (0xFUL << HCCHAR_EPNUM_Pos)              // 0x00007800 */
-#define HCCHAR_EPNUM                     HCCHAR_EPNUM_Msk                         // Endpoint number */
-#define HCCHAR_EPNUM_0                   (0x1UL << HCCHAR_EPNUM_Pos)              // 0x00000800 */
-#define HCCHAR_EPNUM_1                   (0x2UL << HCCHAR_EPNUM_Pos)              // 0x00001000 */
-#define HCCHAR_EPNUM_2                   (0x4UL << HCCHAR_EPNUM_Pos)              // 0x00002000 */
-#define HCCHAR_EPNUM_3                   (0x8UL << HCCHAR_EPNUM_Pos)              // 0x00004000 */
+#define HCCHAR_EPNUM_Msk                 (0xFUL << HCCHAR_EPNUM_Pos)              // 0x00007800
+#define HCCHAR_EPNUM                     HCCHAR_EPNUM_Msk                         // Endpoint number
+#define HCCHAR_EPNUM_0                   (0x1UL << HCCHAR_EPNUM_Pos)              // 0x00000800
+#define HCCHAR_EPNUM_1                   (0x2UL << HCCHAR_EPNUM_Pos)              // 0x00001000
+#define HCCHAR_EPNUM_2                   (0x4UL << HCCHAR_EPNUM_Pos)              // 0x00002000
+#define HCCHAR_EPNUM_3                   (0x8UL << HCCHAR_EPNUM_Pos)              // 0x00004000
 #define HCCHAR_EPDIR_Pos                 (15U)
-#define HCCHAR_EPDIR_Msk                 (0x1UL << HCCHAR_EPDIR_Pos)              // 0x00008000 */
-#define HCCHAR_EPDIR                     HCCHAR_EPDIR_Msk                         // Endpoint direction */
+#define HCCHAR_EPDIR_Msk                 (0x1UL << HCCHAR_EPDIR_Pos)              // 0x00008000
+#define HCCHAR_EPDIR                     HCCHAR_EPDIR_Msk                         // Endpoint direction
 #define HCCHAR_LSDEV_Pos                 (17U)
-#define HCCHAR_LSDEV_Msk                 (0x1UL << HCCHAR_LSDEV_Pos)              // 0x00020000 */
-#define HCCHAR_LSDEV                     HCCHAR_LSDEV_Msk                         // Low-speed device */
+#define HCCHAR_LSDEV_Msk                 (0x1UL << HCCHAR_LSDEV_Pos)              // 0x00020000
+#define HCCHAR_LSDEV                     HCCHAR_LSDEV_Msk                         // Low-speed device
 
 #define HCCHAR_EPTYP_Pos                 (18U)
-#define HCCHAR_EPTYP_Msk                 (0x3UL << HCCHAR_EPTYP_Pos)              // 0x000C0000 */
-#define HCCHAR_EPTYP                     HCCHAR_EPTYP_Msk                         // Endpoint type */
-#define HCCHAR_EPTYP_0                   (0x1UL << HCCHAR_EPTYP_Pos)              // 0x00040000 */
-#define HCCHAR_EPTYP_1                   (0x2UL << HCCHAR_EPTYP_Pos)              // 0x00080000 */
+#define HCCHAR_EPTYP_Msk                 (0x3UL << HCCHAR_EPTYP_Pos)              // 0x000C0000
+#define HCCHAR_EPTYP                     HCCHAR_EPTYP_Msk                         // Endpoint type
+#define HCCHAR_EPTYP_0                   (0x1UL << HCCHAR_EPTYP_Pos)              // 0x00040000
+#define HCCHAR_EPTYP_1                   (0x2UL << HCCHAR_EPTYP_Pos)              // 0x00080000
 
 #define HCCHAR_MC_Pos                    (20U)
-#define HCCHAR_MC_Msk                    (0x3UL << HCCHAR_MC_Pos)                 // 0x00300000 */
-#define HCCHAR_MC                        HCCHAR_MC_Msk                            // Multi Count (MC) / Error Count (EC) */
-#define HCCHAR_MC_0                      (0x1UL << HCCHAR_MC_Pos)                 // 0x00100000 */
-#define HCCHAR_MC_1                      (0x2UL << HCCHAR_MC_Pos)                 // 0x00200000 */
+#define HCCHAR_MC_Msk                    (0x3UL << HCCHAR_MC_Pos)                 // 0x00300000
+#define HCCHAR_MC                        HCCHAR_MC_Msk                            // Multi Count (MC) / Error Count (EC)
+#define HCCHAR_MC_0                      (0x1UL << HCCHAR_MC_Pos)                 // 0x00100000
+#define HCCHAR_MC_1                      (0x2UL << HCCHAR_MC_Pos)                 // 0x00200000
 
 #define HCCHAR_DAD_Pos                   (22U)
-#define HCCHAR_DAD_Msk                   (0x7FUL << HCCHAR_DAD_Pos)               // 0x1FC00000 */
-#define HCCHAR_DAD                       HCCHAR_DAD_Msk                           // Device address */
-#define HCCHAR_DAD_0                     (0x01UL << HCCHAR_DAD_Pos)               // 0x00400000 */
-#define HCCHAR_DAD_1                     (0x02UL << HCCHAR_DAD_Pos)               // 0x00800000 */
-#define HCCHAR_DAD_2                     (0x04UL << HCCHAR_DAD_Pos)               // 0x01000000 */
-#define HCCHAR_DAD_3                     (0x08UL << HCCHAR_DAD_Pos)               // 0x02000000 */
-#define HCCHAR_DAD_4                     (0x10UL << HCCHAR_DAD_Pos)               // 0x04000000 */
-#define HCCHAR_DAD_5                     (0x20UL << HCCHAR_DAD_Pos)               // 0x08000000 */
-#define HCCHAR_DAD_6                     (0x40UL << HCCHAR_DAD_Pos)               // 0x10000000 */
+#define HCCHAR_DAD_Msk                   (0x7FUL << HCCHAR_DAD_Pos)               // 0x1FC00000
+#define HCCHAR_DAD                       HCCHAR_DAD_Msk                           // Device address
+#define HCCHAR_DAD_0                     (0x01UL << HCCHAR_DAD_Pos)               // 0x00400000
+#define HCCHAR_DAD_1                     (0x02UL << HCCHAR_DAD_Pos)               // 0x00800000
+#define HCCHAR_DAD_2                     (0x04UL << HCCHAR_DAD_Pos)               // 0x01000000
+#define HCCHAR_DAD_3                     (0x08UL << HCCHAR_DAD_Pos)               // 0x02000000
+#define HCCHAR_DAD_4                     (0x10UL << HCCHAR_DAD_Pos)               // 0x04000000
+#define HCCHAR_DAD_5                     (0x20UL << HCCHAR_DAD_Pos)               // 0x08000000
+#define HCCHAR_DAD_6                     (0x40UL << HCCHAR_DAD_Pos)               // 0x10000000
 #define HCCHAR_ODDFRM_Pos                (29U)
-#define HCCHAR_ODDFRM_Msk                (0x1UL << HCCHAR_ODDFRM_Pos)             // 0x20000000 */
-#define HCCHAR_ODDFRM                    HCCHAR_ODDFRM_Msk                        // Odd frame */
+#define HCCHAR_ODDFRM_Msk                (0x1UL << HCCHAR_ODDFRM_Pos)             // 0x20000000
+#define HCCHAR_ODDFRM                    HCCHAR_ODDFRM_Msk                        // Odd frame
 #define HCCHAR_CHDIS_Pos                 (30U)
-#define HCCHAR_CHDIS_Msk                 (0x1UL << HCCHAR_CHDIS_Pos)              // 0x40000000 */
-#define HCCHAR_CHDIS                     HCCHAR_CHDIS_Msk                         // Channel disable */
+#define HCCHAR_CHDIS_Msk                 (0x1UL << HCCHAR_CHDIS_Pos)              // 0x40000000
+#define HCCHAR_CHDIS                     HCCHAR_CHDIS_Msk                         // Channel disable
 #define HCCHAR_CHENA_Pos                 (31U)
-#define HCCHAR_CHENA_Msk                 (0x1UL << HCCHAR_CHENA_Pos)              // 0x80000000 */
-#define HCCHAR_CHENA                     HCCHAR_CHENA_Msk                         // Channel enable */
+#define HCCHAR_CHENA_Msk                 (0x1UL << HCCHAR_CHENA_Pos)              // 0x80000000
+#define HCCHAR_CHENA                     HCCHAR_CHENA_Msk                         // Channel enable
 
 /********************  Bit definition for HCSPLT register  ********************/
 
 #define HCSPLT_PRTADDR_Pos               (0U)
-#define HCSPLT_PRTADDR_Msk               (0x7FUL << HCSPLT_PRTADDR_Pos)           // 0x0000007F */
-#define HCSPLT_PRTADDR                   HCSPLT_PRTADDR_Msk                       // Port address */
-#define HCSPLT_PRTADDR_0                 (0x01UL << HCSPLT_PRTADDR_Pos)           // 0x00000001 */
-#define HCSPLT_PRTADDR_1                 (0x02UL << HCSPLT_PRTADDR_Pos)           // 0x00000002 */
-#define HCSPLT_PRTADDR_2                 (0x04UL << HCSPLT_PRTADDR_Pos)           // 0x00000004 */
-#define HCSPLT_PRTADDR_3                 (0x08UL << HCSPLT_PRTADDR_Pos)           // 0x00000008 */
-#define HCSPLT_PRTADDR_4                 (0x10UL << HCSPLT_PRTADDR_Pos)           // 0x00000010 */
-#define HCSPLT_PRTADDR_5                 (0x20UL << HCSPLT_PRTADDR_Pos)           // 0x00000020 */
-#define HCSPLT_PRTADDR_6                 (0x40UL << HCSPLT_PRTADDR_Pos)           // 0x00000040 */
+#define HCSPLT_PRTADDR_Msk               (0x7FUL << HCSPLT_PRTADDR_Pos)           // 0x0000007F
+#define HCSPLT_PRTADDR                   HCSPLT_PRTADDR_Msk                       // Port address
+#define HCSPLT_PRTADDR_0                 (0x01UL << HCSPLT_PRTADDR_Pos)           // 0x00000001
+#define HCSPLT_PRTADDR_1                 (0x02UL << HCSPLT_PRTADDR_Pos)           // 0x00000002
+#define HCSPLT_PRTADDR_2                 (0x04UL << HCSPLT_PRTADDR_Pos)           // 0x00000004
+#define HCSPLT_PRTADDR_3                 (0x08UL << HCSPLT_PRTADDR_Pos)           // 0x00000008
+#define HCSPLT_PRTADDR_4                 (0x10UL << HCSPLT_PRTADDR_Pos)           // 0x00000010
+#define HCSPLT_PRTADDR_5                 (0x20UL << HCSPLT_PRTADDR_Pos)           // 0x00000020
+#define HCSPLT_PRTADDR_6                 (0x40UL << HCSPLT_PRTADDR_Pos)           // 0x00000040
 
 #define HCSPLT_HUBADDR_Pos               (7U)
-#define HCSPLT_HUBADDR_Msk               (0x7FUL << HCSPLT_HUBADDR_Pos)           // 0x00003F80 */
-#define HCSPLT_HUBADDR                   HCSPLT_HUBADDR_Msk                       // Hub address */
-#define HCSPLT_HUBADDR_0                 (0x01UL << HCSPLT_HUBADDR_Pos)           // 0x00000080 */
-#define HCSPLT_HUBADDR_1                 (0x02UL << HCSPLT_HUBADDR_Pos)           // 0x00000100 */
-#define HCSPLT_HUBADDR_2                 (0x04UL << HCSPLT_HUBADDR_Pos)           // 0x00000200 */
-#define HCSPLT_HUBADDR_3                 (0x08UL << HCSPLT_HUBADDR_Pos)           // 0x00000400 */
-#define HCSPLT_HUBADDR_4                 (0x10UL << HCSPLT_HUBADDR_Pos)           // 0x00000800 */
-#define HCSPLT_HUBADDR_5                 (0x20UL << HCSPLT_HUBADDR_Pos)           // 0x00001000 */
-#define HCSPLT_HUBADDR_6                 (0x40UL << HCSPLT_HUBADDR_Pos)           // 0x00002000 */
+#define HCSPLT_HUBADDR_Msk               (0x7FUL << HCSPLT_HUBADDR_Pos)           // 0x00003F80
+#define HCSPLT_HUBADDR                   HCSPLT_HUBADDR_Msk                       // Hub address
+#define HCSPLT_HUBADDR_0                 (0x01UL << HCSPLT_HUBADDR_Pos)           // 0x00000080
+#define HCSPLT_HUBADDR_1                 (0x02UL << HCSPLT_HUBADDR_Pos)           // 0x00000100
+#define HCSPLT_HUBADDR_2                 (0x04UL << HCSPLT_HUBADDR_Pos)           // 0x00000200
+#define HCSPLT_HUBADDR_3                 (0x08UL << HCSPLT_HUBADDR_Pos)           // 0x00000400
+#define HCSPLT_HUBADDR_4                 (0x10UL << HCSPLT_HUBADDR_Pos)           // 0x00000800
+#define HCSPLT_HUBADDR_5                 (0x20UL << HCSPLT_HUBADDR_Pos)           // 0x00001000
+#define HCSPLT_HUBADDR_6                 (0x40UL << HCSPLT_HUBADDR_Pos)           // 0x00002000
 
 #define HCSPLT_XACTPOS_Pos               (14U)
-#define HCSPLT_XACTPOS_Msk               (0x3UL << HCSPLT_XACTPOS_Pos)            // 0x0000C000 */
-#define HCSPLT_XACTPOS                   HCSPLT_XACTPOS_Msk                       // XACTPOS */
-#define HCSPLT_XACTPOS_0                 (0x1UL << HCSPLT_XACTPOS_Pos)            // 0x00004000 */
-#define HCSPLT_XACTPOS_1                 (0x2UL << HCSPLT_XACTPOS_Pos)            // 0x00008000 */
+#define HCSPLT_XACTPOS_Msk               (0x3UL << HCSPLT_XACTPOS_Pos)            // 0x0000C000
+#define HCSPLT_XACTPOS                   HCSPLT_XACTPOS_Msk                       // XACTPOS
+#define HCSPLT_XACTPOS_0                 (0x1UL << HCSPLT_XACTPOS_Pos)            // 0x00004000
+#define HCSPLT_XACTPOS_1                 (0x2UL << HCSPLT_XACTPOS_Pos)            // 0x00008000
 #define HCSPLT_COMPLSPLT_Pos             (16U)
-#define HCSPLT_COMPLSPLT_Msk             (0x1UL << HCSPLT_COMPLSPLT_Pos)          // 0x00010000 */
-#define HCSPLT_COMPLSPLT                 HCSPLT_COMPLSPLT_Msk                     // Do complete split */
+#define HCSPLT_COMPLSPLT_Msk             (0x1UL << HCSPLT_COMPLSPLT_Pos)          // 0x00010000
+#define HCSPLT_COMPLSPLT                 HCSPLT_COMPLSPLT_Msk                     // Do complete split
 #define HCSPLT_SPLITEN_Pos               (31U)
-#define HCSPLT_SPLITEN_Msk               (0x1UL << HCSPLT_SPLITEN_Pos)            // 0x80000000 */
-#define HCSPLT_SPLITEN                   HCSPLT_SPLITEN_Msk                       // Split enable */
+#define HCSPLT_SPLITEN_Msk               (0x1UL << HCSPLT_SPLITEN_Pos)            // 0x80000000
+#define HCSPLT_SPLITEN                   HCSPLT_SPLITEN_Msk                       // Split enable
 
 /********************  Bit definition for HCINT register  ********************/
-#define HCINT_XFRC_Pos                   (0U)
-#define HCINT_XFRC_Msk                   (0x1UL << HCINT_XFRC_Pos)                // 0x00000001 */
-#define HCINT_XFRC                       HCINT_XFRC_Msk                           // Transfer completed */
-#define HCINT_CHH_Pos                    (1U)
-#define HCINT_CHH_Msk                    (0x1UL << HCINT_CHH_Pos)                 // 0x00000002 */
-#define HCINT_CHH                        HCINT_CHH_Msk                            // Channel halted */
-#define HCINT_AHBERR_Pos                 (2U)
-#define HCINT_AHBERR_Msk                 (0x1UL << HCINT_AHBERR_Pos)              // 0x00000004 */
-#define HCINT_AHBERR                     HCINT_AHBERR_Msk                         // AHB error */
+#define HCINT_XFER_COMPLETE_Pos          (0U)
+#define HCINT_XFER_COMPLETE_Msk          (0x1UL << HCINT_XFER_COMPLETE_Pos)       // 0x00000001
+#define HCINT_XFER_COMPLETE              HCINT_XFER_COMPLETE_Msk                  // Transfer completed
+#define HCINT_HALTED_Pos                 (1U)
+#define HCINT_HALTED_Msk                 (0x1UL << HCINT_HALTED_Pos)              // 0x00000002
+#define HCINT_HALTED                     HCINT_HALTED_Msk                         // Channel halted
+#define HCINT_AHB_ERR_Pos                (2U)
+#define HCINT_AHB_ERR_Msk                (0x1UL << HCINT_AHB_ERR_Pos)              // 0x00000004
+#define HCINT_AHB_ERR                     HCINT_AHB_ERR_Msk                         // AHB error
 #define HCINT_STALL_Pos                  (3U)
-#define HCINT_STALL_Msk                  (0x1UL << HCINT_STALL_Pos)               // 0x00000008 */
-#define HCINT_STALL                      HCINT_STALL_Msk                          // STALL response received interrupt */
+#define HCINT_STALL_Msk                  (0x1UL << HCINT_STALL_Pos)               // 0x00000008
+#define HCINT_STALL                      HCINT_STALL_Msk                          // STALL response received interrupt
 #define HCINT_NAK_Pos                    (4U)
-#define HCINT_NAK_Msk                    (0x1UL << HCINT_NAK_Pos)                 // 0x00000010 */
-#define HCINT_NAK                        HCINT_NAK_Msk                            // NAK response received interrupt */
+#define HCINT_NAK_Msk                    (0x1UL << HCINT_NAK_Pos)                 // 0x00000010
+#define HCINT_NAK                        HCINT_NAK_Msk                            // NAK response received interrupt
 #define HCINT_ACK_Pos                    (5U)
-#define HCINT_ACK_Msk                    (0x1UL << HCINT_ACK_Pos)                 // 0x00000020 */
-#define HCINT_ACK                        HCINT_ACK_Msk                            // ACK response received/transmitted interrupt */
+#define HCINT_ACK_Msk                    (0x1UL << HCINT_ACK_Pos)                 // 0x00000020
+#define HCINT_ACK                        HCINT_ACK_Msk                            // ACK response received/transmitted interrupt
 #define HCINT_NYET_Pos                   (6U)
-#define HCINT_NYET_Msk                   (0x1UL << HCINT_NYET_Pos)                // 0x00000040 */
-#define HCINT_NYET                       HCINT_NYET_Msk                           // Response received interrupt */
-#define HCINT_TXERR_Pos                  (7U)
-#define HCINT_TXERR_Msk                  (0x1UL << HCINT_TXERR_Pos)               // 0x00000080 */
-#define HCINT_TXERR                      HCINT_TXERR_Msk                          // Transaction error */
-#define HCINT_BBERR_Pos                  (8U)
-#define HCINT_BBERR_Msk                  (0x1UL << HCINT_BBERR_Pos)               // 0x00000100 */
-#define HCINT_BBERR                      HCINT_BBERR_Msk                          // Babble error */
-#define HCINT_FRMOR_Pos                  (9U)
-#define HCINT_FRMOR_Msk                  (0x1UL << HCINT_FRMOR_Pos)               // 0x00000200 */
-#define HCINT_FRMOR                      HCINT_FRMOR_Msk                          // Frame overrun */
-#define HCINT_DTERR_Pos                  (10U)
-#define HCINT_DTERR_Msk                  (0x1UL << HCINT_DTERR_Pos)               // 0x00000400 */
-#define HCINT_DTERR                      HCINT_DTERR_Msk                          // Data toggle error */
+#define HCINT_NYET_Msk                   (0x1UL << HCINT_NYET_Pos)                // 0x00000040
+#define HCINT_NYET                       HCINT_NYET_Msk                           // Response received interrupt
+#define HCINT_XACT_ERR_Pos               (7U)
+#define HCINT_XACT_ERR_Msk               (0x1UL << HCINT_XACT_ERR_Pos)            // 0x00000080
+#define HCINT_XACT_ERR                   HCINT_XACT_ERR_Msk                       // Transaction error
+#define HCINT_BABBLE_ERR_Pos             (8U)
+#define HCINT_BABBLE_ERR_Msk             (0x1UL << HCINT_BABBLE_ERR_Pos)          // 0x00000100
+#define HCINT_BABBLE_ERR                 HCINT_BABBLE_ERR_Msk                     // Babble error
+#define HCINT_FARME_OVERRUN_Pos          (9U)
+#define HCINT_FARME_OVERRUN_Msk          (0x1UL << HCINT_FARME_OVERRUN_Pos)       // 0x00000200
+#define HCINT_FARME_OVERRUN              HCINT_FARME_OVERRUN_Msk                  // Frame overrun
+#define HCINT_DATATOGGLE_ERR_Pos         (10U)
+#define HCINT_DATATOGGLE_ERR_Msk         (0x1UL << HCINT_DATATOGGLE_ERR_Pos)      // 0x00000400
+#define HCINT_DATATOGGLE_ERR             HCINT_DATATOGGLE_ERR_Msk                 // Data toggle error
+#define HCINT_BUFFER_NA_Pos             (11U)
+#define HCINT_BUFFER_NA_Msk             (0x1UL << HCINT_BUFFER_NA_Pos)          // 0x00000800
+#define HCINT_BUFFER_NA                 HCINT_BUFFER_NA_Msk                     // Buffer not available interrupt
+#define HCINT_XCS_XACT_ERR_Pos           (12U)
+#define HCINT_XCS_XACT_ERR_Msk           (0x1UL << HCINT_XCS_XACT_ERR_Pos)        // 0x00001000
+#define HCINT_XCS_XACT_ERR               HCINT_XCS_XACT_ERR_Msk                   // Excessive transaction error
+#define HCINT_DESC_ROLLOVER_Pos          (13U)
+#define HCINT_DESC_ROLLOVER_Msk          (0x1UL << HCINT_DESC_ROLLOVER_Pos)       // 0x00002000
+#define HCINT_DESC_ROLLOVER              HCINT_DESC_ROLLOVER_Msk                  // Descriptor rollover
 
 /********************  Bit definition for DIEPINT register  ********************/
 #define DIEPINT_XFRC_Pos                 (0U)
-#define DIEPINT_XFRC_Msk                 (0x1UL << DIEPINT_XFRC_Pos)              // 0x00000001 */
-#define DIEPINT_XFRC                     DIEPINT_XFRC_Msk                         // Transfer completed interrupt */
+#define DIEPINT_XFRC_Msk                 (0x1UL << DIEPINT_XFRC_Pos)              // 0x00000001
+#define DIEPINT_XFRC                     DIEPINT_XFRC_Msk                         // Transfer completed interrupt
 #define DIEPINT_EPDISD_Pos               (1U)
-#define DIEPINT_EPDISD_Msk               (0x1UL << DIEPINT_EPDISD_Pos)            // 0x00000002 */
-#define DIEPINT_EPDISD                   DIEPINT_EPDISD_Msk                       // Endpoint disabled interrupt */
+#define DIEPINT_EPDISD_Msk               (0x1UL << DIEPINT_EPDISD_Pos)            // 0x00000002
+#define DIEPINT_EPDISD                   DIEPINT_EPDISD_Msk                       // Endpoint disabled interrupt
 #define DIEPINT_AHBERR_Pos               (2U)
-#define DIEPINT_AHBERR_Msk               (0x1UL << DIEPINT_AHBERR_Pos)            // 0x00000004 */
-#define DIEPINT_AHBERR                   DIEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an IN transaction */
+#define DIEPINT_AHBERR_Msk               (0x1UL << DIEPINT_AHBERR_Pos)            // 0x00000004
+#define DIEPINT_AHBERR                   DIEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an IN transaction
 #define DIEPINT_TOC_Pos                  (3U)
-#define DIEPINT_TOC_Msk                  (0x1UL << DIEPINT_TOC_Pos)               // 0x00000008 */
-#define DIEPINT_TOC                      DIEPINT_TOC_Msk                          // Timeout condition */
+#define DIEPINT_TOC_Msk                  (0x1UL << DIEPINT_TOC_Pos)               // 0x00000008
+#define DIEPINT_TOC                      DIEPINT_TOC_Msk                          // Timeout condition
 #define DIEPINT_ITTXFE_Pos               (4U)
-#define DIEPINT_ITTXFE_Msk               (0x1UL << DIEPINT_ITTXFE_Pos)            // 0x00000010 */
-#define DIEPINT_ITTXFE                   DIEPINT_ITTXFE_Msk                       // IN token received when TxFIFO is empty */
+#define DIEPINT_ITTXFE_Msk               (0x1UL << DIEPINT_ITTXFE_Pos)            // 0x00000010
+#define DIEPINT_ITTXFE                   DIEPINT_ITTXFE_Msk                       // IN token received when TxFIFO is empty
 #define DIEPINT_INEPNM_Pos               (5U)
-#define DIEPINT_INEPNM_Msk               (0x1UL << DIEPINT_INEPNM_Pos)            // 0x00000020 */
-#define DIEPINT_INEPNM                   DIEPINT_INEPNM_Msk                       // IN token received with EP mismatch */
+#define DIEPINT_INEPNM_Msk               (0x1UL << DIEPINT_INEPNM_Pos)            // 0x00000020
+#define DIEPINT_INEPNM                   DIEPINT_INEPNM_Msk                       // IN token received with EP mismatch
 #define DIEPINT_INEPNE_Pos               (6U)
-#define DIEPINT_INEPNE_Msk               (0x1UL << DIEPINT_INEPNE_Pos)            // 0x00000040 */
-#define DIEPINT_INEPNE                   DIEPINT_INEPNE_Msk                       // IN endpoint NAK effective */
+#define DIEPINT_INEPNE_Msk               (0x1UL << DIEPINT_INEPNE_Pos)            // 0x00000040
+#define DIEPINT_INEPNE                   DIEPINT_INEPNE_Msk                       // IN endpoint NAK effective
 #define DIEPINT_TXFE_Pos                 (7U)
-#define DIEPINT_TXFE_Msk                 (0x1UL << DIEPINT_TXFE_Pos)              // 0x00000080 */
-#define DIEPINT_TXFE                     DIEPINT_TXFE_Msk                         // Transmit FIFO empty */
+#define DIEPINT_TXFE_Msk                 (0x1UL << DIEPINT_TXFE_Pos)              // 0x00000080
+#define DIEPINT_TXFE                     DIEPINT_TXFE_Msk                         // Transmit FIFO empty
 #define DIEPINT_TXFIFOUDRN_Pos           (8U)
-#define DIEPINT_TXFIFOUDRN_Msk           (0x1UL << DIEPINT_TXFIFOUDRN_Pos)        // 0x00000100 */
-#define DIEPINT_TXFIFOUDRN               DIEPINT_TXFIFOUDRN_Msk                   // Transmit Fifo Underrun */
+#define DIEPINT_TXFIFOUDRN_Msk           (0x1UL << DIEPINT_TXFIFOUDRN_Pos)        // 0x00000100
+#define DIEPINT_TXFIFOUDRN               DIEPINT_TXFIFOUDRN_Msk                   // Transmit Fifo Underrun
 #define DIEPINT_BNA_Pos                  (9U)
-#define DIEPINT_BNA_Msk                  (0x1UL << DIEPINT_BNA_Pos)               // 0x00000200 */
-#define DIEPINT_BNA                      DIEPINT_BNA_Msk                          // Buffer not available interrupt */
+#define DIEPINT_BNA_Msk                  (0x1UL << DIEPINT_BNA_Pos)               // 0x00000200
+#define DIEPINT_BNA                      DIEPINT_BNA_Msk                          // Buffer not available interrupt
 #define DIEPINT_PKTDRPSTS_Pos            (11U)
-#define DIEPINT_PKTDRPSTS_Msk            (0x1UL << DIEPINT_PKTDRPSTS_Pos)         // 0x00000800 */
-#define DIEPINT_PKTDRPSTS                DIEPINT_PKTDRPSTS_Msk                    // Packet dropped status */
+#define DIEPINT_PKTDRPSTS_Msk            (0x1UL << DIEPINT_PKTDRPSTS_Pos)         // 0x00000800
+#define DIEPINT_PKTDRPSTS                DIEPINT_PKTDRPSTS_Msk                    // Packet dropped status
 #define DIEPINT_BERR_Pos                 (12U)
-#define DIEPINT_BERR_Msk                 (0x1UL << DIEPINT_BERR_Pos)              // 0x00001000 */
-#define DIEPINT_BERR                     DIEPINT_BERR_Msk                         // Babble error interrupt */
+#define DIEPINT_BERR_Msk                 (0x1UL << DIEPINT_BERR_Pos)              // 0x00001000
+#define DIEPINT_BERR                     DIEPINT_BERR_Msk                         // Babble error interrupt
 #define DIEPINT_NAK_Pos                  (13U)
-#define DIEPINT_NAK_Msk                  (0x1UL << DIEPINT_NAK_Pos)               // 0x00002000 */
-#define DIEPINT_NAK                      DIEPINT_NAK_Msk                          // NAK interrupt */
-
-/********************  Bit definition for HCINTMSK register  ********************/
-#define HCINTMSK_XFRCM_Pos               (0U)
-#define HCINTMSK_XFRCM_Msk               (0x1UL << HCINTMSK_XFRCM_Pos)            // 0x00000001 */
-#define HCINTMSK_XFRCM                   HCINTMSK_XFRCM_Msk                       // Transfer completed mask */
-#define HCINTMSK_CHHM_Pos                (1U)
-#define HCINTMSK_CHHM_Msk                (0x1UL << HCINTMSK_CHHM_Pos)             // 0x00000002 */
-#define HCINTMSK_CHHM                    HCINTMSK_CHHM_Msk                        // Channel halted mask */
-#define HCINTMSK_AHBERR_Pos              (2U)
-#define HCINTMSK_AHBERR_Msk              (0x1UL << HCINTMSK_AHBERR_Pos)           // 0x00000004 */
-#define HCINTMSK_AHBERR                  HCINTMSK_AHBERR_Msk                      // AHB error */
-#define HCINTMSK_STALLM_Pos              (3U)
-#define HCINTMSK_STALLM_Msk              (0x1UL << HCINTMSK_STALLM_Pos)           // 0x00000008 */
-#define HCINTMSK_STALLM                  HCINTMSK_STALLM_Msk                      // STALL response received interrupt mask */
-#define HCINTMSK_NAKM_Pos                (4U)
-#define HCINTMSK_NAKM_Msk                (0x1UL << HCINTMSK_NAKM_Pos)             // 0x00000010 */
-#define HCINTMSK_NAKM                    HCINTMSK_NAKM_Msk                        // NAK response received interrupt mask */
-#define HCINTMSK_ACKM_Pos                (5U)
-#define HCINTMSK_ACKM_Msk                (0x1UL << HCINTMSK_ACKM_Pos)             // 0x00000020 */
-#define HCINTMSK_ACKM                    HCINTMSK_ACKM_Msk                        // ACK response received/transmitted interrupt mask */
-#define HCINTMSK_NYET_Pos                (6U)
-#define HCINTMSK_NYET_Msk                (0x1UL << HCINTMSK_NYET_Pos)             // 0x00000040 */
-#define HCINTMSK_NYET                    HCINTMSK_NYET_Msk                        // response received interrupt mask */
-#define HCINTMSK_TXERRM_Pos              (7U)
-#define HCINTMSK_TXERRM_Msk              (0x1UL << HCINTMSK_TXERRM_Pos)           // 0x00000080 */
-#define HCINTMSK_TXERRM                  HCINTMSK_TXERRM_Msk                      // Transaction error mask */
-#define HCINTMSK_BBERRM_Pos              (8U)
-#define HCINTMSK_BBERRM_Msk              (0x1UL << HCINTMSK_BBERRM_Pos)           // 0x00000100 */
-#define HCINTMSK_BBERRM                  HCINTMSK_BBERRM_Msk                      // Babble error mask */
-#define HCINTMSK_FRMORM_Pos              (9U)
-#define HCINTMSK_FRMORM_Msk              (0x1UL << HCINTMSK_FRMORM_Pos)           // 0x00000200 */
-#define HCINTMSK_FRMORM                  HCINTMSK_FRMORM_Msk                      // Frame overrun mask */
-#define HCINTMSK_DTERRM_Pos              (10U)
-#define HCINTMSK_DTERRM_Msk              (0x1UL << HCINTMSK_DTERRM_Pos)           // 0x00000400 */
-#define HCINTMSK_DTERRM                  HCINTMSK_DTERRM_Msk                      // Data toggle error mask */
+#define DIEPINT_NAK_Msk                  (0x1UL << DIEPINT_NAK_Pos)               // 0x00002000
+#define DIEPINT_NAK                      DIEPINT_NAK_Msk                          // NAK interrupt
 
 /********************  Bit definition for DIEPTSIZ register  ********************/
 
 #define DIEPTSIZ_XFRSIZ_Pos              (0U)
-#define DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF */
-#define DIEPTSIZ_XFRSIZ                  DIEPTSIZ_XFRSIZ_Msk                      // Transfer size */
+#define DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF
+#define DIEPTSIZ_XFRSIZ                  DIEPTSIZ_XFRSIZ_Msk                      // Transfer size
 #define DIEPTSIZ_PKTCNT_Pos              (19U)
-#define DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << DIEPTSIZ_PKTCNT_Pos)         // 0x1FF80000 */
-#define DIEPTSIZ_PKTCNT                  DIEPTSIZ_PKTCNT_Msk                      // Packet count */
+#define DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << DIEPTSIZ_PKTCNT_Pos)         // 0x1FF80000
+#define DIEPTSIZ_PKTCNT                  DIEPTSIZ_PKTCNT_Msk                      // Packet count
 #define DIEPTSIZ_MULCNT_Pos              (29U)
-#define DIEPTSIZ_MULCNT_Msk              (0x3UL << DIEPTSIZ_MULCNT_Pos)           // 0x60000000 */
-#define DIEPTSIZ_MULCNT                  DIEPTSIZ_MULCNT_Msk                      // Packet count */
+#define DIEPTSIZ_MULCNT_Msk              (0x3UL << DIEPTSIZ_MULCNT_Pos)           // 0x60000000
+#define DIEPTSIZ_MULCNT                  DIEPTSIZ_MULCNT_Msk                      // Packet count
                                                                                   /********************  Bit definition for HCTSIZ register  ********************/
 #define HCTSIZ_XFRSIZ_Pos                (0U)
-#define HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos)         // 0x0007FFFF */
-#define HCTSIZ_XFRSIZ                    HCTSIZ_XFRSIZ_Msk                        // Transfer size */
+#define HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos)         // 0x0007FFFF
+#define HCTSIZ_XFRSIZ                    HCTSIZ_XFRSIZ_Msk                        // Transfer size
 #define HCTSIZ_PKTCNT_Pos                (19U)
-#define HCTSIZ_PKTCNT_Msk                (0x3FFUL << HCTSIZ_PKTCNT_Pos)           // 0x1FF80000 */
-#define HCTSIZ_PKTCNT                    HCTSIZ_PKTCNT_Msk                        // Packet count */
+#define HCTSIZ_PKTCNT_Msk                (0x3FFUL << HCTSIZ_PKTCNT_Pos)           // 0x1FF80000
+#define HCTSIZ_PKTCNT                    HCTSIZ_PKTCNT_Msk                        // Packet count
 #define HCTSIZ_DOPING_Pos                (31U)
-#define HCTSIZ_DOPING_Msk                (0x1UL << HCTSIZ_DOPING_Pos)             // 0x80000000 */
-#define HCTSIZ_DOPING                    HCTSIZ_DOPING_Msk                        // Do PING */
-#define HCTSIZ_DPID_Pos                  (29U)
-#define HCTSIZ_DPID_Msk                  (0x3UL << HCTSIZ_DPID_Pos)               // 0x60000000 */
-#define HCTSIZ_DPID                      HCTSIZ_DPID_Msk                          // Data PID */
-#define HCTSIZ_DPID_0                    (0x1UL << HCTSIZ_DPID_Pos)               // 0x20000000 */
-#define HCTSIZ_DPID_1                    (0x2UL << HCTSIZ_DPID_Pos)               // 0x40000000 */
+#define HCTSIZ_DOPING_Msk                (0x1UL << HCTSIZ_DOPING_Pos)             // 0x80000000
+#define HCTSIZ_DOPING                    HCTSIZ_DOPING_Msk                        // Do PING
+#define HCTSIZ_PID_Pos                  (29U)
+#define HCTSIZ_PID_Msk                  (0x3UL << HCTSIZ_PID_Pos)               // 0x60000000
+#define HCTSIZ_PID                      HCTSIZ_PID_Msk                          // Data PID
 
 /********************  Bit definition for DIEPDMA register  ********************/
 #define DIEPDMA_DMAADDR_Pos              (0U)
-#define DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos)    // 0xFFFFFFFF */
-#define DIEPDMA_DMAADDR                  DIEPDMA_DMAADDR_Msk                      // DMA address */
+#define DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos)    // 0xFFFFFFFF
+#define DIEPDMA_DMAADDR                  DIEPDMA_DMAADDR_Msk                      // DMA address
 
 /********************  Bit definition for HCDMA register  ********************/
 #define HCDMA_DMAADDR_Pos                (0U)
-#define HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos)      // 0xFFFFFFFF */
-#define HCDMA_DMAADDR                    HCDMA_DMAADDR_Msk                        // DMA address */
+#define HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos)      // 0xFFFFFFFF
+#define HCDMA_DMAADDR                    HCDMA_DMAADDR_Msk                        // DMA address
 
                                                                                   /********************  Bit definition for DTXFSTS register  ********************/
 #define DTXFSTS_INEPTFSAV_Pos            (0U)
-#define DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos)      // 0x0000FFFF */
-#define DTXFSTS_INEPTFSAV                DTXFSTS_INEPTFSAV_Msk                    // IN endpoint TxFIFO space available */
+#define DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos)      // 0x0000FFFF
+#define DTXFSTS_INEPTFSAV                DTXFSTS_INEPTFSAV_Msk                    // IN endpoint TxFIFO space available
 
                                                                                   /********************  Bit definition for DIEPTXF register  ********************/
 #define DIEPTXF_INEPTXSA_Pos             (0U)
-#define DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << DIEPTXF_INEPTXSA_Pos)       // 0x0000FFFF */
-#define DIEPTXF_INEPTXSA                 DIEPTXF_INEPTXSA_Msk                     // IN endpoint FIFOx transmit RAM start address */
+#define DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << DIEPTXF_INEPTXSA_Pos)       // 0x0000FFFF
+#define DIEPTXF_INEPTXSA                 DIEPTXF_INEPTXSA_Msk                     // IN endpoint FIFOx transmit RAM start address
 #define DIEPTXF_INEPTXFD_Pos             (16U)
-#define DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << DIEPTXF_INEPTXFD_Pos)       // 0xFFFF0000 */
-#define DIEPTXF_INEPTXFD                 DIEPTXF_INEPTXFD_Msk                     // IN endpoint TxFIFO depth */
+#define DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << DIEPTXF_INEPTXFD_Pos)       // 0xFFFF0000
+#define DIEPTXF_INEPTXFD                 DIEPTXF_INEPTXFD_Msk                     // IN endpoint TxFIFO depth
+
+
+/********************  Bit definition for Common EPCTL register  ********************/
+#define EPCTL_MPSIZ_Pos                (0U)
+#define EPCTL_MPSIZ_Msk                (0x7FFUL << EPCTL_MPSIZ_Pos)           // 0x000007FF
+#define EPCTL_MPSIZ                    EPCTL_MPSIZ_Msk                        // Maximum packet size          //Bit 1
+#define EPCTL_USBAEP_Pos               (15U)
+#define EPCTL_USBAEP_Msk               (0x1UL << EPCTL_USBAEP_Pos)            // 0x00008000
+#define EPCTL_USBAEP                   EPCTL_USBAEP_Msk                       // USB active endpoint
+#define EPCTL_NAKSTS_Pos               (17U)
+#define EPCTL_NAKSTS_Msk               (0x1UL << EPCTL_NAKSTS_Pos)            // 0x00020000
+#define EPCTL_NAKSTS                   EPCTL_NAKSTS_Msk                       // NAK status
+#define EPCTL_EPTYP_Pos                (18U)
+#define EPCTL_EPTYP_Msk                (0x3UL << EPCTL_EPTYP_Pos)             // 0x000C0000
+#define EPCTL_EPTYP                    EPCTL_EPTYP_Msk                        // Endpoint type
+#define EPCTL_EPTYP_0                  (0x1UL << EPCTL_EPTYP_Pos)             // 0x00040000
+#define EPCTL_EPTYP_1                  (0x2UL << EPCTL_EPTYP_Pos)             // 0x00080000
+#define EPCTL_SNPM                     EPCTL_SNPM_Msk                         // Snoop mode
+#define EPCTL_STALL_Pos                (21U)
+#define EPCTL_STALL_Msk                (0x1UL << EPCTL_STALL_Pos)             // 0x00200000
+#define EPCTL_STALL                    EPCTL_STALL_Msk                        // STALL handshake
+#define EPCTL_CNAK_Pos                 (26U)
+#define EPCTL_CNAK_Msk                 (0x1UL << EPCTL_CNAK_Pos)              // 0x04000000
+#define EPCTL_CNAK                     EPCTL_CNAK_Msk                         // Clear NAK
+#define EPCTL_SNAK_Pos                 (27U)
+#define EPCTL_SNAK_Msk                 (0x1UL << EPCTL_SNAK_Pos)              // 0x08000000
+#define EPCTL_SNAK                     EPCTL_SNAK_Msk                         // Set NAK
+#define EPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define EPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << EPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000
+#define EPCTL_SD0PID_SEVNFRM           EPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID
+#define EPCTL_SODDFRM_Pos              (29U)
+#define EPCTL_SODDFRM_Msk              (0x1UL << EPCTL_SODDFRM_Pos)           // 0x20000000
+#define EPCTL_SODDFRM                  EPCTL_SODDFRM_Msk                      // Set odd frame
+#define EPCTL_EPDIS_Pos                (30U)
+#define EPCTL_EPDIS_Msk                (0x1UL << EPCTL_EPDIS_Pos)             // 0x40000000
+#define EPCTL_EPDIS                    EPCTL_EPDIS_Msk                        // Endpoint disable
+#define EPCTL_EPENA_Pos                (31U)
+#define EPCTL_EPENA_Msk                (0x1UL << EPCTL_EPENA_Pos)             // 0x80000000
+#define EPCTL_EPENA                    EPCTL_EPENA_Msk                        // Endpoint enable
 
 /********************  Bit definition for DOEPCTL register  ********************/
 #define DOEPCTL_MPSIZ_Pos                (0U)
-#define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos)           // 0x000007FF */
-#define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk                        // Maximum packet size */          //Bit 1 */
+#define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos)           // 0x000007FF
+#define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk                        // Maximum packet size          //Bit 1
 #define DOEPCTL_USBAEP_Pos               (15U)
-#define DOEPCTL_USBAEP_Msk               (0x1UL << DOEPCTL_USBAEP_Pos)            // 0x00008000 */
-#define DOEPCTL_USBAEP                   DOEPCTL_USBAEP_Msk                       // USB active endpoint */
+#define DOEPCTL_USBAEP_Msk               (0x1UL << DOEPCTL_USBAEP_Pos)            // 0x00008000
+#define DOEPCTL_USBAEP                   DOEPCTL_USBAEP_Msk                       // USB active endpoint
 #define DOEPCTL_NAKSTS_Pos               (17U)
-#define DOEPCTL_NAKSTS_Msk               (0x1UL << DOEPCTL_NAKSTS_Pos)            // 0x00020000 */
-#define DOEPCTL_NAKSTS                   DOEPCTL_NAKSTS_Msk                       // NAK status */
+#define DOEPCTL_NAKSTS_Msk               (0x1UL << DOEPCTL_NAKSTS_Pos)            // 0x00020000
+#define DOEPCTL_NAKSTS                   DOEPCTL_NAKSTS_Msk                       // NAK status
 #define DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
-#define DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000 */
-#define DOEPCTL_SD0PID_SEVNFRM           DOEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID */
+#define DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000
+#define DOEPCTL_SD0PID_SEVNFRM           DOEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID
 #define DOEPCTL_SODDFRM_Pos              (29U)
-#define DOEPCTL_SODDFRM_Msk              (0x1UL << DOEPCTL_SODDFRM_Pos)           // 0x20000000 */
-#define DOEPCTL_SODDFRM                  DOEPCTL_SODDFRM_Msk                      // Set odd frame */
+#define DOEPCTL_SODDFRM_Msk              (0x1UL << DOEPCTL_SODDFRM_Pos)           // 0x20000000
+#define DOEPCTL_SODDFRM                  DOEPCTL_SODDFRM_Msk                      // Set odd frame
 #define DOEPCTL_EPTYP_Pos                (18U)
-#define DOEPCTL_EPTYP_Msk                (0x3UL << DOEPCTL_EPTYP_Pos)             // 0x000C0000 */
-#define DOEPCTL_EPTYP                    DOEPCTL_EPTYP_Msk                        // Endpoint type */
-#define DOEPCTL_EPTYP_0                  (0x1UL << DOEPCTL_EPTYP_Pos)             // 0x00040000 */
-#define DOEPCTL_EPTYP_1                  (0x2UL << DOEPCTL_EPTYP_Pos)             // 0x00080000 */
+#define DOEPCTL_EPTYP_Msk                (0x3UL << DOEPCTL_EPTYP_Pos)             // 0x000C0000
+#define DOEPCTL_EPTYP                    DOEPCTL_EPTYP_Msk                        // Endpoint type
+#define DOEPCTL_EPTYP_0                  (0x1UL << DOEPCTL_EPTYP_Pos)             // 0x00040000
+#define DOEPCTL_EPTYP_1                  (0x2UL << DOEPCTL_EPTYP_Pos)             // 0x00080000
 #define DOEPCTL_SNPM_Pos                 (20U)
-#define DOEPCTL_SNPM_Msk                 (0x1UL << DOEPCTL_SNPM_Pos)              // 0x00100000 */
-#define DOEPCTL_SNPM                     DOEPCTL_SNPM_Msk                         // Snoop mode */
+#define DOEPCTL_SNPM_Msk                 (0x1UL << DOEPCTL_SNPM_Pos)              // 0x00100000
+#define DOEPCTL_SNPM                     DOEPCTL_SNPM_Msk                         // Snoop mode
 #define DOEPCTL_STALL_Pos                (21U)
-#define DOEPCTL_STALL_Msk                (0x1UL << DOEPCTL_STALL_Pos)             // 0x00200000 */
-#define DOEPCTL_STALL                    DOEPCTL_STALL_Msk                        // STALL handshake */
+#define DOEPCTL_STALL_Msk                (0x1UL << DOEPCTL_STALL_Pos)             // 0x00200000
+#define DOEPCTL_STALL                    DOEPCTL_STALL_Msk                        // STALL handshake
 #define DOEPCTL_CNAK_Pos                 (26U)
-#define DOEPCTL_CNAK_Msk                 (0x1UL << DOEPCTL_CNAK_Pos)              // 0x04000000 */
-#define DOEPCTL_CNAK                     DOEPCTL_CNAK_Msk                         // Clear NAK */
+#define DOEPCTL_CNAK_Msk                 (0x1UL << DOEPCTL_CNAK_Pos)              // 0x04000000
+#define DOEPCTL_CNAK                     DOEPCTL_CNAK_Msk                         // Clear NAK
 #define DOEPCTL_SNAK_Pos                 (27U)
-#define DOEPCTL_SNAK_Msk                 (0x1UL << DOEPCTL_SNAK_Pos)              // 0x08000000 */
-#define DOEPCTL_SNAK                     DOEPCTL_SNAK_Msk                         // Set NAK */
+#define DOEPCTL_SNAK_Msk                 (0x1UL << DOEPCTL_SNAK_Pos)              // 0x08000000
+#define DOEPCTL_SNAK                     DOEPCTL_SNAK_Msk                         // Set NAK
 #define DOEPCTL_EPDIS_Pos                (30U)
-#define DOEPCTL_EPDIS_Msk                (0x1UL << DOEPCTL_EPDIS_Pos)             // 0x40000000 */
-#define DOEPCTL_EPDIS                    DOEPCTL_EPDIS_Msk                        // Endpoint disable */
+#define DOEPCTL_EPDIS_Msk                (0x1UL << DOEPCTL_EPDIS_Pos)             // 0x40000000
+#define DOEPCTL_EPDIS                    DOEPCTL_EPDIS_Msk                        // Endpoint disable
 #define DOEPCTL_EPENA_Pos                (31U)
-#define DOEPCTL_EPENA_Msk                (0x1UL << DOEPCTL_EPENA_Pos)             // 0x80000000 */
-#define DOEPCTL_EPENA                    DOEPCTL_EPENA_Msk                        // Endpoint enable */
+#define DOEPCTL_EPENA_Msk                (0x1UL << DOEPCTL_EPENA_Pos)             // 0x80000000
+#define DOEPCTL_EPENA                    DOEPCTL_EPENA_Msk                        // Endpoint enable
 
 /********************  Bit definition for DOEPINT register  ********************/
 #define DOEPINT_XFRC_Pos                 (0U)
-#define DOEPINT_XFRC_Msk                 (0x1UL << DOEPINT_XFRC_Pos)              // 0x00000001 */
-#define DOEPINT_XFRC                     DOEPINT_XFRC_Msk                         // Transfer completed interrupt */
+#define DOEPINT_XFRC_Msk                 (0x1UL << DOEPINT_XFRC_Pos)              // 0x00000001
+#define DOEPINT_XFRC                     DOEPINT_XFRC_Msk                         // Transfer completed interrupt
 #define DOEPINT_EPDISD_Pos               (1U)
-#define DOEPINT_EPDISD_Msk               (0x1UL << DOEPINT_EPDISD_Pos)            // 0x00000002 */
-#define DOEPINT_EPDISD                   DOEPINT_EPDISD_Msk                       // Endpoint disabled interrupt */
+#define DOEPINT_EPDISD_Msk               (0x1UL << DOEPINT_EPDISD_Pos)            // 0x00000002
+#define DOEPINT_EPDISD                   DOEPINT_EPDISD_Msk                       // Endpoint disabled interrupt
 #define DOEPINT_AHBERR_Pos               (2U)
-#define DOEPINT_AHBERR_Msk               (0x1UL << DOEPINT_AHBERR_Pos)            // 0x00000004 */
-#define DOEPINT_AHBERR                   DOEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an OUT transaction */
-#define DOEPINT_STUP_Pos                 (3U)
-#define DOEPINT_STUP_Msk                 (0x1UL << DOEPINT_STUP_Pos)              // 0x00000008 */
-#define DOEPINT_STUP                     DOEPINT_STUP_Msk                         // SETUP phase done */
+#define DOEPINT_AHBERR_Msk               (0x1UL << DOEPINT_AHBERR_Pos)            // 0x00000004
+#define DOEPINT_AHBERR                   DOEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an OUT transaction
+
+#define DOEPINT_SETUP_Pos                (3U)
+#define DOEPINT_SETUP_Msk                (0x1UL << DOEPINT_SETUP_Pos)             // 0x00000008
+#define DOEPINT_SETUP                    DOEPINT_SETUP_Msk                        // SETUP phase done
+
 #define DOEPINT_OTEPDIS_Pos              (4U)
-#define DOEPINT_OTEPDIS_Msk              (0x1UL << DOEPINT_OTEPDIS_Pos)           // 0x00000010 */
-#define DOEPINT_OTEPDIS                  DOEPINT_OTEPDIS_Msk                      // OUT token received when endpoint disabled */
-#define DOEPINT_OTEPSPR_Pos              (5U)
-#define DOEPINT_OTEPSPR_Msk              (0x1UL << DOEPINT_OTEPSPR_Pos)           // 0x00000020 */
-#define DOEPINT_OTEPSPR                  DOEPINT_OTEPSPR_Msk                      // Status Phase Received For Control Write */
+#define DOEPINT_OTEPDIS_Msk              (0x1UL << DOEPINT_OTEPDIS_Pos)           // 0x00000010
+#define DOEPINT_OTEPDIS                  DOEPINT_OTEPDIS_Msk                      // OUT token received when endpoint disabled
+
+#define DOEPINT_STSPHSRX_Pos             (5U)
+#define DOEPINT_STSPHSRX_Msk             (0x1UL << DOEPINT_STSPHSRX_Pos)          // 0x00000020
+#define DOEPINT_STSPHSRX                  DOEPINT_STSPHSRX_Msk                    // Status Phase Received For Control Write
+
 #define DOEPINT_B2BSTUP_Pos              (6U)
-#define DOEPINT_B2BSTUP_Msk              (0x1UL << DOEPINT_B2BSTUP_Pos)           // 0x00000040 */
-#define DOEPINT_B2BSTUP                  DOEPINT_B2BSTUP_Msk                      // Back-to-back SETUP packets received */
+#define DOEPINT_B2BSTUP_Msk              (0x1UL << DOEPINT_B2BSTUP_Pos)           // 0x00000040
+#define DOEPINT_B2BSTUP                  DOEPINT_B2BSTUP_Msk                      // Back-to-back SETUP packets received
 #define DOEPINT_OUTPKTERR_Pos            (8U)
-#define DOEPINT_OUTPKTERR_Msk            (0x1UL << DOEPINT_OUTPKTERR_Pos)         // 0x00000100 */
-#define DOEPINT_OUTPKTERR                DOEPINT_OUTPKTERR_Msk                    // OUT packet error */
+#define DOEPINT_OUTPKTERR_Msk            (0x1UL << DOEPINT_OUTPKTERR_Pos)         // 0x00000100
+#define DOEPINT_OUTPKTERR                DOEPINT_OUTPKTERR_Msk                    // OUT packet error
 #define DOEPINT_NAK_Pos                  (13U)
-#define DOEPINT_NAK_Msk                  (0x1UL << DOEPINT_NAK_Pos)               // 0x00002000 */
-#define DOEPINT_NAK                      DOEPINT_NAK_Msk                          // NAK Packet is transmitted by the device */
+#define DOEPINT_NAK_Msk                  (0x1UL << DOEPINT_NAK_Pos)               // 0x00002000
+#define DOEPINT_NAK                      DOEPINT_NAK_Msk                          // NAK Packet is transmitted by the device
 #define DOEPINT_NYET_Pos                 (14U)
-#define DOEPINT_NYET_Msk                 (0x1UL << DOEPINT_NYET_Pos)              // 0x00004000 */
-#define DOEPINT_NYET                     DOEPINT_NYET_Msk                         // NYET interrupt */
+#define DOEPINT_NYET_Msk                 (0x1UL << DOEPINT_NYET_Pos)              // 0x00004000
+#define DOEPINT_NYET                     DOEPINT_NYET_Msk                         // NYET interrupt
+
 #define DOEPINT_STPKTRX_Pos              (15U)
-#define DOEPINT_STPKTRX_Msk              (0x1UL << DOEPINT_STPKTRX_Pos)           // 0x00008000 */
-#define DOEPINT_STPKTRX                  DOEPINT_STPKTRX_Msk                      // Setup Packet Received */
+#define DOEPINT_STPKTRX_Msk              (0x1UL << DOEPINT_STPKTRX_Pos)           // 0x00008000
+#define DOEPINT_STPKTRX                  DOEPINT_STPKTRX_Msk                      // Setup Packet Received
 
 /********************  Bit definition for DOEPTSIZ register  ********************/
 #define DOEPTSIZ_XFRSIZ_Pos              (0U)
-#define DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF */
-#define DOEPTSIZ_XFRSIZ                  DOEPTSIZ_XFRSIZ_Msk                      // Transfer size */
+#define DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF
+#define DOEPTSIZ_XFRSIZ                  DOEPTSIZ_XFRSIZ_Msk                      // Transfer size
 #define DOEPTSIZ_PKTCNT_Pos              (19U)
-#define DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << DOEPTSIZ_PKTCNT_Pos)         // 0x1FF80000 */
-#define DOEPTSIZ_PKTCNT                  DOEPTSIZ_PKTCNT_Msk                      // Packet count */
+#define DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << DOEPTSIZ_PKTCNT_Pos)         // 0x1FF80000
+#define DOEPTSIZ_PKTCNT                  DOEPTSIZ_PKTCNT_Msk                      // Packet count
 
 #define DOEPTSIZ_STUPCNT_Pos             (29U)
-#define DOEPTSIZ_STUPCNT_Msk             (0x3UL << DOEPTSIZ_STUPCNT_Pos)          // 0x60000000 */
-#define DOEPTSIZ_STUPCNT                 DOEPTSIZ_STUPCNT_Msk                     // SETUP packet count */
-#define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos)          // 0x20000000 */
-#define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos)          // 0x40000000 */
+#define DOEPTSIZ_STUPCNT_Msk             (0x3UL << DOEPTSIZ_STUPCNT_Pos)          // 0x60000000
+#define DOEPTSIZ_STUPCNT                 DOEPTSIZ_STUPCNT_Msk                     // SETUP packet count
+#define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos)          // 0x20000000
+#define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos)          // 0x40000000
 
 /********************  Bit definition for PCGCTL register  ********************/
-#define PCGCTL_IF_DEV_MODE              TU_BIT(31)
-#define PCGCTL_P2HD_PRT_SPD_MASK        (0x3ul << 29)
-#define PCGCTL_P2HD_PRT_SPD_SHIFT       29
-#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK   (0x3ul << 27)
-#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT  27
-#define PCGCTL_MAC_DEV_ADDR_MASK        (0x7ful << 20)
-#define PCGCTL_MAC_DEV_ADDR_SHIFT       20
-#define PCGCTL_MAX_TERMSEL              TU_BIT(19)
-#define PCGCTL_MAX_XCVRSELECT_MASK      (0x3ul << 17)
-#define PCGCTL_MAX_XCVRSELECT_SHIFT     17
-#define PCGCTL_PORT_POWER               TU_BIT(16)
-#define PCGCTL_PRT_CLK_SEL_MASK         (0x3ul << 14)
-#define PCGCTL_PRT_CLK_SEL_SHIFT        14
-#define PCGCTL_ESS_REG_RESTORED         TU_BIT(13)
-#define PCGCTL_EXTND_HIBER_SWITCH       TU_BIT(12)
-#define PCGCTL_EXTND_HIBER_PWRCLMP      TU_BIT(11)
-#define PCGCTL_ENBL_EXTND_HIBER         TU_BIT(10)
-#define PCGCTL_RESTOREMODE              TU_BIT(9)
-#define PCGCTL_RESETAFTSUSP             TU_BIT(8)
-#define PCGCTL_DEEP_SLEEP               TU_BIT(7)
-#define PCGCTL_PHY_IN_SLEEP             TU_BIT(6)
-#define PCGCTL_ENBL_SLEEP_GATING        TU_BIT(5)
-#define PCGCTL_RSTPDWNMODULE            TU_BIT(3)
-#define PCGCTL_PWRCLMP                  TU_BIT(2)
-#define PCGCTL_GATEHCLK                 TU_BIT(1)
-#define PCGCTL_STOPPCLK                 TU_BIT(0)
+#define PCGCCTL_IF_DEV_MODE              TU_BIT(31)
+#define PCGCCTL_P2HD_PRT_SPD_MASK        (0x3ul << 29)
+#define PCGCCTL_P2HD_PRT_SPD_SHIFT       29
+#define PCGCCTL_P2HD_DEV_ENUM_SPD_MASK   (0x3ul << 27)
+#define PCGCCTL_P2HD_DEV_ENUM_SPD_SHIFT  27
+#define PCGCCTL_MAC_DEV_ADDR_MASK        (0x7ful << 20)
+#define PCGCCTL_MAC_DEV_ADDR_SHIFT       20
+#define PCGCCTL_MAX_TERMSEL              TU_BIT(19)
+#define PCGCCTL_MAX_XCVRSELECT_MASK      (0x3ul << 17)
+#define PCGCCTL_MAX_XCVRSELECT_SHIFT     17
+#define PCGCCTL_PORT_POWER               TU_BIT(16)
+#define PCGCCTL_PRT_CLK_SEL_MASK         (0x3ul << 14)
+#define PCGCCTL_PRT_CLK_SEL_SHIFT        14
+#define PCGCCTL_ESS_REG_RESTORED         TU_BIT(13)
+#define PCGCCTL_EXTND_HIBER_SWITCH       TU_BIT(12)
+#define PCGCCTL_EXTND_HIBER_PWRCLMP      TU_BIT(11)
+#define PCGCCTL_ENBL_EXTND_HIBER         TU_BIT(10)
+#define PCGCCTL_RESTOREMODE              TU_BIT(9)
+#define PCGCCTL_RESETAFTSUSP             TU_BIT(8)
+#define PCGCCTL_DEEP_SLEEP               TU_BIT(7)
+#define PCGCCTL_PHY_IN_SLEEP             TU_BIT(6)
+#define PCGCCTL_ENBL_SLEEP_GATING        TU_BIT(5)
+#define PCGCCTL_RSTPDWNMODULE            TU_BIT(3)
+#define PCGCCTL_PWRCLMP                  TU_BIT(2)
+#define PCGCCTL_GATEHCLK                 TU_BIT(1)
+#define PCGCCTL_STOPPCLK                 TU_BIT(0)
 
 #define PCGCTL1_TIMER                   (0x3ul << 1)
 #define PCGCTL1_GATEEN                  TU_BIT(0)
diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c
new file mode 100644
index 000000000..ebbb6200a
--- /dev/null
+++ b/src/portable/synopsys/dwc2/hcd_dwc2.c
@@ -0,0 +1,1360 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2)
+
+#if !(CFG_TUH_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE)
+#error DWC2 require either CFG_TUH_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled
+#endif
+
+// Debug level for DWC2
+#define DWC2_DEBUG    2
+
+#include "host/hcd.h"
+#include "dwc2_common.h"
+
+// Max number of endpoints application can open, can be larger than DWC2_CHANNEL_COUNT_MAX
+#ifndef CFG_TUH_DWC2_ENDPOINT_MAX
+#define CFG_TUH_DWC2_ENDPOINT_MAX 16
+#endif
+
+#define DWC2_CHANNEL_COUNT_MAX    16 // absolute max channel count
+#define DWC2_CHANNEL_COUNT(_dwc2) tu_min8((_dwc2)->ghwcfg2_bm.num_host_ch + 1, DWC2_CHANNEL_COUNT_MAX)
+
+TU_VERIFY_STATIC(CFG_TUH_DWC2_ENDPOINT_MAX <= 255, "currently only use 8-bit for index");
+
+enum {
+  HPRT_W1_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE | HPRT_SUSPEND
+};
+
+enum {
+  HCD_XFER_ERROR_MAX = 3
+};
+
+enum {
+  HCD_XFER_PERIOD_SPLIT_NYET_MAX = 3
+};
+
+//--------------------------------------------------------------------
+//
+//--------------------------------------------------------------------
+
+// Host driver struct for each opened endpoint
+typedef struct {
+  union {
+    uint32_t hcchar;
+    dwc2_channel_char_t hcchar_bm;
+  };
+  union {
+    uint32_t hcsplt;
+    dwc2_channel_split_t hcsplt_bm;
+  };
+
+  struct TU_ATTR_PACKED {
+    uint32_t uframe_interval : 18; // micro-frame interval
+    uint32_t speed    : 2;
+    uint32_t next_pid : 2;
+    uint32_t do_ping  : 1;
+    // uint32_t : 9;
+  };
+
+  uint32_t uframe_countdown; // micro-frame count down to transfer for periodic, only need 18-bit
+
+  uint8_t* buffer;
+  uint16_t buflen;
+} hcd_endpoint_t;
+
+// Additional info for each channel when it is active
+typedef struct {
+  volatile bool allocated;
+  uint8_t ep_id;
+  struct TU_ATTR_PACKED {
+    uint8_t err_count : 3;
+    uint8_t period_split_nyet_count : 3;
+    uint8_t halted_nyet : 1;
+    uint8_t halted_sof_schedule : 1;
+  };
+  uint8_t result;
+
+  uint16_t xferred_bytes;  // bytes that accumulate transferred though USB bus for the whole hcd_edpt_xfer(), which can
+                           // be composed of multiple channel_xfer_start() (retry with NAK/NYET)
+  uint16_t fifo_bytes;     // bytes written/read from/to FIFO (may not be transferred on USB bus).
+} hcd_xfer_t;
+
+typedef struct {
+  hcd_xfer_t xfer[DWC2_CHANNEL_COUNT_MAX];
+  hcd_endpoint_t edpt[CFG_TUH_DWC2_ENDPOINT_MAX];
+} hcd_data_t;
+
+hcd_data_t _hcd_data;
+
+//--------------------------------------------------------------------
+//
+//--------------------------------------------------------------------
+TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t hprt_speed_get(dwc2_regs_t* dwc2) {
+  tusb_speed_t speed;
+  switch(dwc2->hprt_bm.speed) {
+    case HPRT_SPEED_HIGH: speed = TUSB_SPEED_HIGH; break;
+    case HPRT_SPEED_FULL: speed = TUSB_SPEED_FULL; break;
+    case HPRT_SPEED_LOW : speed = TUSB_SPEED_LOW ; break;
+    default:
+      speed = TUSB_SPEED_INVALID;
+      TU_BREAKPOINT();
+    break;
+  }
+  return speed;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc2) {
+  (void) dwc2;
+  // Internal DMA only
+  return CFG_TUH_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
+}
+
+#if CFG_TUH_MEM_DCACHE_ENABLE
+bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
+  TU_VERIFY(addr && data_size);
+  return dwc2_dcache_clean(addr, data_size);
+}
+
+bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) {
+  TU_VERIFY(addr && data_size);
+  return dwc2_dcache_invalidate(addr, data_size);
+}
+
+bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
+  TU_VERIFY(addr && data_size);
+  return dwc2_dcache_clean_invalidate(addr, data_size);
+}
+#endif
+
+// Allocate a channel for new transfer
+TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) {
+  const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
+  for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
+    hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+    if (!xfer->allocated) {
+      tu_memclr(xfer, sizeof(hcd_xfer_t));
+      xfer->allocated = true;
+      return ch_id;
+    }
+  }
+  return TUSB_INDEX_INVALID_8;
+}
+
+// Check if is periodic (interrupt/isochronous)
+TU_ATTR_ALWAYS_INLINE static inline bool edpt_is_periodic(uint8_t ep_type) {
+  return ep_type == HCCHAR_EPTYPE_INTERRUPT || ep_type == HCCHAR_EPTYPE_ISOCHRONOUS;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t req_queue_avail(const dwc2_regs_t* dwc2, bool is_period) {
+  if (is_period) {
+    return dwc2->hptxsts_bm.req_queue_available;
+  } else {
+    return dwc2->hnptxsts_bm.req_queue_available;
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint8_t ch_id) {
+  hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+  xfer->allocated = false;
+  dwc2->haintmsk &= ~TU_BIT(ch_id);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool channel_disable(const dwc2_regs_t* dwc2, dwc2_channel_t* channel) {
+  // disable also require request queue
+  TU_ASSERT(req_queue_avail(dwc2, edpt_is_periodic(channel->hcchar_bm.ep_type)));
+  channel->hcintmsk |= HCINT_HALTED;
+  channel->hcchar |= HCCHAR_CHDIS | HCCHAR_CHENA; // must set both CHDIS and CHENA
+  return true;
+}
+
+// attempt to send IN token to receive data
+TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t* dwc2, dwc2_channel_t* channel) {
+  TU_ASSERT(req_queue_avail(dwc2, edpt_is_periodic(channel->hcchar_bm.ep_type)));
+  channel->hcchar |= HCCHAR_CHENA;
+  return true;
+}
+
+// Find currently enabled channel. Note: EP0 is bidirectional
+TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dwc2, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) {
+  const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
+  for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
+    if (_hcd_data.xfer[ch_id].allocated) {
+      const dwc2_channel_char_t hcchar_bm = dwc2->channel[ch_id].hcchar_bm;
+      if (hcchar_bm.dev_addr == dev_addr && hcchar_bm.ep_num == ep_num && (ep_num == 0 || hcchar_bm.ep_dir == ep_dir)) {
+        return ch_id;
+      }
+    }
+  }
+  return TUSB_INDEX_INVALID_8;
+}
+
+
+// Allocate a new endpoint
+TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_alloc(void) {
+  for (uint32_t i = 0; i < CFG_TUH_DWC2_ENDPOINT_MAX; i++) {
+    hcd_endpoint_t* edpt = &_hcd_data.edpt[i];
+    if (edpt->hcchar_bm.enable == 0) {
+      tu_memclr(edpt, sizeof(hcd_endpoint_t));
+      edpt->hcchar_bm.enable = 1;
+      return i;
+    }
+  }
+  return TUSB_INDEX_INVALID_8;
+}
+
+// Find a endpoint that is opened previously with hcd_edpt_open()
+// Note: EP0 is bidirectional
+TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_find_opened(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) {
+  for (uint8_t i = 0; i < (uint8_t)CFG_TUH_DWC2_ENDPOINT_MAX; i++) {
+    const dwc2_channel_char_t* hcchar_bm = &_hcd_data.edpt[i].hcchar_bm;
+    if (hcchar_bm->enable && hcchar_bm->dev_addr == dev_addr &&
+        hcchar_bm->ep_num == ep_num && (ep_num == 0 || hcchar_bm->ep_dir == ep_dir)) {
+      return i;
+    }
+  }
+  return TUSB_INDEX_INVALID_8;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t cal_packet_count(uint16_t len, uint16_t ep_size) {
+  if (len == 0) {
+    return 1;
+  } else {
+    return tu_div_ceil(len, ep_size);
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t cal_next_pid(uint8_t pid, uint8_t packet_count) {
+  if (packet_count & 0x01) {
+    return pid ^ 0x02; // toggle DATA0 and DATA1
+  } else {
+    return pid;
+  }
+}
+
+//--------------------------------------------------------------------
+//
+//--------------------------------------------------------------------
+
+/* USB Data FIFO Layout
+
+  The FIFO is split up into
+  - EPInfo: for storing DMA metadata (check dcd_dwc2.c for more details)
+  - 1 RX FIFO: for receiving data
+  - 1 TX FIFO for non-periodic (NPTX)
+  - 1 TX FIFO for periodic (PTX)
+
+  We allocated TX FIFO from top to bottom (using top pointer), this to allow the RX FIFO to grow dynamically which is
+  possible since the free space is located between the RX and TX FIFOs.
+
+   ----------------- ep_fifo_size
+  |    HCDMAn    |
+  |--------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth)
+  | Non-Periodic |
+  |   TX FIFO    |
+  |--------------|--- GNPTXFSIZ.addr (fixed size)
+  |   Periodic   |
+  |   TX FIFO    |
+  |--------------|--- HPTXFSIZ.addr (expandable downward)
+  |    FREE      |
+  |              |
+  |--------------|-- GRXFSIZ (expandable upward)
+  |  RX FIFO     |
+  ---------------- 0
+*/
+
+/* Programming Guide 2.1.2 FIFO RAM allocation
+ * RX
+ * - Largest-EPsize/4 + 2 (status info). recommended x2 if high bandwidth or multiple ISO are used.
+ * - 2 for transfer complete and channel halted status
+ * - 1 for each Control/Bulk out endpoint to Handle NAK/NYET (i.e max is number of host channel)
+ *
+ * TX non-periodic (NPTX)
+ * - At least largest-EPsize/4, recommended x2
+ *
+ * TX periodic (PTX)
+ * - At least largest-EPsize*MulCount/4 (MulCount up to 3 for high-bandwidth ISO/interrupt)
+*/
+static void dfifo_host_init(uint8_t rhport) {
+  const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per channel
+  const bool is_dma = dma_host_enabled(dwc2);
+  uint16_t dfifo_top = dwc2_controller->ep_fifo_size/4;
+  if (is_dma) {
+    dfifo_top -= dwc2->ghwcfg2_bm.num_host_ch;
+  }
+
+  // fixed allocation for now, improve later:
+    // - ptx_largest is limited to 256 for FS since most FS core only has 1024 bytes total
+  bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST);
+  uint32_t nptx_largest = is_highspeed ? TUSB_EPSIZE_BULK_HS/4 : TUSB_EPSIZE_BULK_FS/4;
+  uint32_t ptx_largest = is_highspeed ? TUSB_EPSIZE_ISO_HS_MAX/4 : 256/4;
+
+  uint16_t nptxfsiz = 2 * nptx_largest;
+  uint16_t rxfsiz = 2 * (ptx_largest + 2) + dwc2->ghwcfg2_bm.num_host_ch;
+  TU_ASSERT(dfifo_top >= (nptxfsiz + rxfsiz),);
+  uint16_t ptxfsiz = dfifo_top - (nptxfsiz + rxfsiz);
+
+  dwc2->gdfifocfg = (dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | dfifo_top;
+
+  dfifo_top -= rxfsiz;
+  dwc2->grxfsiz = rxfsiz;
+
+  dfifo_top -= nptxfsiz;
+  dwc2->gnptxfsiz = tu_u32_from_u16(nptxfsiz, dfifo_top);
+
+  dfifo_top -= ptxfsiz;
+  dwc2->hptxfsiz = tu_u32_from_u16(ptxfsiz, dfifo_top);
+}
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// optional hcd configuration, called by tuh_configure()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  (void) cfg_id;
+  (void) cfg_param;
+
+  return true;
+}
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  tu_memclr(&_hcd_data, sizeof(_hcd_data));
+
+  // Core Initialization
+  const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST);
+  const bool is_dma = dma_host_enabled(dwc2);
+  TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma));
+
+  //------------- 3.1 Host Initialization -------------//
+
+  // work at max supported speed
+  dwc2->hcfg &= ~HCFG_FSLS_ONLY;
+
+  // Enable HFIR reload
+  if (dwc2->gsnpsid >= DWC2_CORE_REV_2_92a) {
+    dwc2->hfir |= HFIR_RELOAD_CTRL;
+  }
+
+  // force host mode and wait for mode switch
+  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD;
+  while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {}
+
+  // configure fixed-allocated fifo scheme
+  dfifo_host_init(rhport);
+
+  dwc2->hprt = HPRT_W1_MASK; // clear all write-1-clear bits
+  dwc2->hprt = HPRT_POWER; // turn on VBUS
+
+  // Enable required interrupts
+  dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_CONIDSTSCHNG | GINTSTS_HPRTINT | GINTSTS_HCINT;
+
+  // NPTX can hold at least 2 packet, change interrupt level to half-empty
+  uint32_t gahbcfg = dwc2->gahbcfg & ~GAHBCFG_TX_FIFO_EPMTY_LVL;
+  gahbcfg |= GAHBCFG_GINT;   // Enable global interrupt
+  dwc2->gahbcfg = gahbcfg;
+
+  return true;
+}
+
+// Enable USB interrupt
+void hcd_int_enable (uint8_t rhport) {
+  dwc2_int_set(rhport, TUSB_ROLE_HOST, true);
+}
+
+// Disable USB interrupt
+void hcd_int_disable(uint8_t rhport) {
+  dwc2_int_set(rhport, TUSB_ROLE_HOST, false);
+}
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  return dwc2->hfnum & HFNUM_FRNUM_Msk;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  return dwc2->hprt & HPRT_CONN_STATUS;
+}
+
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
+void hcd_port_reset(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  uint32_t hprt = dwc2->hprt & ~HPRT_W1_MASK;
+  hprt |= HPRT_RESET;
+  dwc2->hprt = hprt;
+}
+
+// Complete bus reset sequence, may be required by some controllers
+void hcd_port_reset_end(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  uint32_t hprt = dwc2->hprt & ~HPRT_W1_MASK; // skip w1c bits
+  hprt &= ~HPRT_RESET;
+  dwc2->hprt = hprt;
+}
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const tusb_speed_t speed = hprt_speed_get(dwc2);
+  return speed;
+}
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  for (uint8_t i = 0; i < (uint8_t) CFG_TUH_DWC2_ENDPOINT_MAX; i++) {
+    hcd_endpoint_t* edpt = &_hcd_data.edpt[i];
+    if (edpt->hcchar_bm.enable && edpt->hcchar_bm.dev_addr == dev_addr) {
+      tu_memclr(edpt, sizeof(hcd_endpoint_t));
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* desc_ep) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const tusb_speed_t rh_speed = hprt_speed_get(dwc2);
+
+  hcd_devtree_info_t devtree_info;
+  hcd_devtree_get_info(dev_addr, &devtree_info);
+
+  // find a free endpoint
+  const uint8_t ep_id = edpt_alloc();
+  TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
+
+  dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm;
+  hcchar_bm->ep_size         = tu_edpt_packet_size(desc_ep);
+  hcchar_bm->ep_num          = tu_edpt_number(desc_ep->bEndpointAddress);
+  hcchar_bm->ep_dir          = tu_edpt_dir(desc_ep->bEndpointAddress);
+  hcchar_bm->low_speed_dev   = (devtree_info.speed == TUSB_SPEED_LOW) ? 1 : 0;
+  hcchar_bm->ep_type         = desc_ep->bmAttributes.xfer; // ep_type matches TUSB_XFER_*
+  hcchar_bm->err_multi_count = 0;
+  hcchar_bm->dev_addr        = dev_addr;
+  hcchar_bm->odd_frame       = 0;
+  hcchar_bm->disable         = 0;
+  hcchar_bm->enable          = 1;
+
+  dwc2_channel_split_t* hcsplt_bm = &edpt->hcsplt_bm;
+  hcsplt_bm->hub_port        = devtree_info.hub_port;
+  hcsplt_bm->hub_addr        = devtree_info.hub_addr;
+  hcsplt_bm->xact_pos        = 0;
+  hcsplt_bm->split_compl     = 0;
+  hcsplt_bm->split_en        = (rh_speed == TUSB_SPEED_HIGH && devtree_info.speed != TUSB_SPEED_HIGH) ? 1 : 0;
+
+  edpt->speed = devtree_info.speed;
+  edpt->next_pid = HCTSIZ_PID_DATA0;
+  if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
+    edpt->uframe_interval = 1 << (desc_ep->bInterval - 1);
+    if (devtree_info.speed == TUSB_SPEED_FULL) {
+      edpt->uframe_interval <<= 3;
+    }
+  } else if (desc_ep->bmAttributes.xfer == TUSB_XFER_INTERRUPT) {
+    if (devtree_info.speed == TUSB_SPEED_HIGH) {
+      edpt->uframe_interval = 1 << (desc_ep->bInterval - 1);
+    } else {
+      edpt->uframe_interval = desc_ep->bInterval << 3;
+    }
+  }
+
+  return true;
+}
+
+// clean up channel after part of transfer is done but the whole urb is not complete
+static void channel_xfer_out_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) {
+  hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+  dwc2_channel_t* channel = &dwc2->channel[ch_id];
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
+
+  edpt->next_pid = channel->hctsiz_bm.pid; // save PID
+
+  /* Since hctsiz.xfersize field reflects the number of bytes transferred via the AHB, not the USB)
+   * For IN: we can use hctsiz.xfersize as remaining bytes.
+   * For OUT: Must use the hctsiz.pktcnt field to determine how much data has been transferred. This field reflects the
+   * number of packets that have been transferred via the USB. This is always an integral number of packets if the
+   * transfer was halted before its normal completion.
+   */
+  const uint16_t remain_packets = channel->hctsiz_bm.packet_count;
+  const uint16_t total_packets = cal_packet_count(edpt->buflen, channel->hcchar_bm.ep_size);
+  const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size;
+
+  xfer->fifo_bytes = 0;
+  xfer->xferred_bytes += actual_bytes;
+  edpt->buffer += actual_bytes;
+  edpt->buflen -= actual_bytes;
+}
+
+static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) {
+  hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
+  dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm;
+  dwc2_channel_t* channel = &dwc2->channel[ch_id];
+  bool const is_period = edpt_is_periodic(hcchar_bm->ep_type);
+
+  // clear previous state
+  xfer->fifo_bytes = 0;
+
+  // hchar: restore but don't enable yet
+  if (is_period) {
+    hcchar_bm->odd_frame = 1 - (dwc2->hfnum & 1);   // transfer on next frame
+  }
+  channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA);
+
+  // hctsiz: zero length packet still count as 1
+  const uint16_t packet_count = cal_packet_count(edpt->buflen, hcchar_bm->ep_size);
+  uint32_t hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | edpt->buflen;
+  if (edpt->do_ping && edpt->speed == TUSB_SPEED_HIGH &&
+     edpt->next_pid != HCTSIZ_PID_SETUP && hcchar_bm->ep_dir == TUSB_DIR_OUT) {
+    hctsiz |= HCTSIZ_DOPING;
+  }
+  channel->hctsiz = hctsiz;
+  edpt->do_ping = 0;
+
+  // pre-calculate next PID based on packet count, adjusted in transfer complete interrupt if short packet
+  if (hcchar_bm->ep_num == 0) {
+    edpt->next_pid = HCTSIZ_PID_DATA1; // control data and status stage always start with DATA1
+  } else {
+    edpt->next_pid = cal_next_pid(edpt->next_pid, packet_count);
+  }
+
+  channel->hcsplt = edpt->hcsplt;
+  channel->hcint = 0xFFFFFFFFU; // clear all channel interrupts
+
+  if (dma_host_enabled(dwc2)) {
+    uint32_t hcintmsk = HCINT_HALTED;
+    channel->hcintmsk = hcintmsk;
+    dwc2->haintmsk |= TU_BIT(ch_id);
+
+    channel->hcdma = (uint32_t) edpt->buffer;
+
+    if (hcchar_bm->ep_dir == TUSB_DIR_IN) {
+      channel_send_in_token(dwc2, channel);
+    } else {
+      hcd_dcache_clean(edpt->buffer, edpt->buflen);
+      channel->hcchar |= HCCHAR_CHENA;
+    }
+  } else {
+    uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR;
+    if (hcchar_bm->ep_dir == TUSB_DIR_IN) {
+      hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR | HCINT_ACK;
+    } else {
+      hcintmsk |= HCINT_NYET;
+      if (edpt->hcsplt_bm.split_en) {
+        hcintmsk |= HCINT_ACK;
+      }
+    }
+    channel->hcintmsk = hcintmsk;
+    dwc2->haintmsk |= TU_BIT(ch_id);
+
+    // enable channel for slave mode:
+    // - OUT: it will enable corresponding FIFO channel
+    // - IN : it will write an IN request to the Non-periodic Request Queue, this will have dwc2 trying to send
+    // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only
+    // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically.
+    if (hcchar_bm->ep_dir == TUSB_DIR_IN) {
+      channel_send_in_token(dwc2, channel);
+    } else {
+      channel->hcchar |= HCCHAR_CHENA;
+      if (edpt->buflen > 0) {
+        // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly
+        // And write packet in the interrupt handler
+        dwc2->gintmsk |= (is_period ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY);
+      }
+    }
+  }
+
+  return true;
+}
+
+// kick-off transfer with an endpoint
+static bool edpt_xfer_kickoff(dwc2_regs_t* dwc2, uint8_t ep_id) {
+  uint8_t ch_id = channel_alloc(dwc2);
+  TU_ASSERT(ch_id < 16); // all channel are in used
+  hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+  xfer->ep_id = ep_id;
+  xfer->result = XFER_RESULT_INVALID;
+
+  return channel_xfer_start(dwc2, ch_id);
+}
+
+// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const uint8_t ep_num = tu_edpt_number(ep_addr);
+  const uint8_t ep_dir = tu_edpt_dir(ep_addr);
+
+  uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir);
+  TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
+
+  edpt->buffer = buffer;
+  edpt->buflen = buflen;
+
+  if (ep_num == 0) {
+    // update ep_dir since control endpoint can switch direction
+    edpt->hcchar_bm.ep_dir = ep_dir;
+  }
+
+  return edpt_xfer_kickoff(dwc2, ep_id);
+}
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const uint8_t ep_num = tu_edpt_number(ep_addr);
+  const uint8_t ep_dir = tu_edpt_dir(ep_addr);
+  const uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir);
+  TU_VERIFY(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
+
+  // hcd_int_disable(rhport);
+
+  // Find enabled channeled and disable it, channel will be de-allocated in the interrupt handler
+  const uint8_t ch_id = channel_find_enabled(dwc2, dev_addr, ep_num, ep_dir);
+  if (ch_id < 16) {
+    dwc2_channel_t* channel = &dwc2->channel[ch_id];
+    channel_disable(dwc2, channel);
+  }
+
+  // hcd_int_enable(rhport);
+
+  return true;
+}
+
+// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet[8]) {
+  uint8_t ep_id = edpt_find_opened(dev_addr, 0, TUSB_DIR_OUT);
+  TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened endpoint
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
+  edpt->next_pid = HCTSIZ_PID_SETUP;
+
+  return hcd_edpt_xfer(rhport, dev_addr, 0, (uint8_t*)(uintptr_t) setup_packet, 8);
+}
+
+// clear stall, data toggle is also reset to DATA0
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  const uint8_t ep_num = tu_edpt_number(ep_addr);
+  const uint8_t ep_dir = tu_edpt_dir(ep_addr);
+  const uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir);
+  TU_VERIFY(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
+
+  edpt->next_pid = HCTSIZ_PID_DATA0;
+
+  return true;
+}
+
+//--------------------------------------------------------------------
+// HCD Event Handler
+//--------------------------------------------------------------------
+static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) {
+  hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+  dwc2_channel_t* channel = &dwc2->channel[ch_id];
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
+
+  if (edpt_is_periodic(channel->hcchar_bm.ep_type)){
+    // retry immediately for periodic split NYET if we haven't reach max retry
+    if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl && (hcint & HCINT_NYET || xfer->halted_nyet)) {
+      xfer->period_split_nyet_count++;
+      xfer->halted_nyet = 0;
+      if (xfer->period_split_nyet_count < HCD_XFER_PERIOD_SPLIT_NYET_MAX) {
+        channel->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame
+        channel_send_in_token(dwc2, channel);
+        return;
+      } else {
+        // too many NYET, de-allocate channel with below code
+        xfer->period_split_nyet_count = 0;
+      }
+    }
+
+    // for periodic, de-allocate channel, enable SOF set frame counter for later transfer
+    edpt->next_pid = channel->hctsiz_bm.pid; // save PID
+    edpt->uframe_countdown = edpt->uframe_interval;
+    dwc2->gintmsk |= GINTSTS_SOF;
+
+    if (hcint & HCINT_HALTED) {
+      // already halted, de-allocate channel (called from DMA isr)
+      channel_dealloc(dwc2, ch_id);
+    } else {
+      // disable channel first if not halted (called slave isr)
+      xfer->halted_sof_schedule = 1;
+      channel_disable(dwc2, channel);
+    }
+  } else {
+    // for control/bulk: retry immediately
+    channel_send_in_token(dwc2, channel);
+  }
+}
+
+#if CFG_TUSB_DEBUG
+TU_ATTR_ALWAYS_INLINE static inline void print_hcint(uint32_t hcint) {
+  const char* str[] = {
+    "XFRC", "HALTED", "AHBERR", "STALL",
+    "NAK", "ACK", "NYET", "XERR",
+    "BBLERR", "FRMOR", "DTERR", "BNA",
+    "XCSERR", "DESC_LST"
+  };
+
+  for(uint32_t i=0; i<14; i++) {
+    if (hcint & TU_BIT(i)) {
+      TU_LOG1("%s ", str[i]);
+    }
+  }
+  TU_LOG1("\r\n");
+}
+#endif
+
+#if CFG_TUH_DWC2_SLAVE_ENABLE
+static void handle_rxflvl_irq(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  // Pop control word off FIFO
+  const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm;
+  const uint8_t ch_id = grxstsp_bm.ep_ch_num;
+
+  switch (grxstsp_bm.packet_status) {
+    case GRXSTS_PKTSTS_RX_DATA: {
+      // In packet received, pop this entry --> ACK interrupt
+      const uint16_t byte_count = grxstsp_bm.byte_count;
+      hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+      TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,);
+      hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
+
+      if (byte_count) {
+        dfifo_read_packet(dwc2, edpt->buffer + xfer->xferred_bytes, byte_count);
+        xfer->xferred_bytes += byte_count;
+        xfer->fifo_bytes = byte_count;
+      }
+      break;
+    }
+
+    case GRXSTS_PKTSTS_RX_COMPLETE:
+      // In transfer complete: After this entry is popped from the rx FIFO, dwc2 asserts a Transfer Completed
+      // interrupt --> handle_channel_irq()
+      break;
+
+    case GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR:
+      TU_ASSERT(0, ); // maybe try to change DToggle
+      break;
+
+    case GRXSTS_PKTSTS_HOST_CHANNEL_HALTED:
+      // triggered when channel.hcchar_bm.disable is set
+      // TODO handle later
+      break;
+
+    default: break; // ignore other status
+  }
+}
+
+// return true if there is still pending data and need more ISR
+static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) {
+  // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough)
+  volatile dwc2_hptxsts_t* txsts_bm = (volatile dwc2_hptxsts_t*) (is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts);
+
+  const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
+  for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
+    dwc2_channel_t* channel = &dwc2->channel[ch_id];
+    // skip writing to FIFO if channel is expecting halted.
+    if (!(channel->hcintmsk & HCINT_HALTED) && (channel->hcchar_bm.ep_dir == TUSB_DIR_OUT)) {
+      hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+      TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
+      hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
+
+      const uint16_t remain_packets = channel->hctsiz_bm.packet_count;
+      for (uint16_t i = 0; i < remain_packets; i++) {
+        const uint16_t remain_bytes = edpt->buflen - xfer->fifo_bytes;
+        const uint16_t xact_bytes = tu_min16(remain_bytes, channel->hcchar_bm.ep_size);
+
+        // skip if there is not enough space in FIFO and RequestQueue.
+        // Packet's last word written to FIFO will trigger a request queue
+        if ((xact_bytes > (txsts_bm->fifo_available << 2)) || (txsts_bm->req_queue_available == 0)) {
+          return true;
+        }
+
+        dfifo_write_packet(dwc2, ch_id, edpt->buffer + xfer->fifo_bytes, xact_bytes);
+        xfer->fifo_bytes += xact_bytes;
+      }
+    }
+  }
+
+  return false; // no channel has pending data
+}
+
+static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) {
+  hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+  dwc2_channel_t* channel = &dwc2->channel[ch_id];
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
+  bool is_done = false;
+
+  // if (channel->hcsplt_bm.split_en) {
+  // if (edpt->hcchar_bm.ep_num == 1) {
+  //   TU_LOG1("Frame %u, ch %u: ep %u, hcint 0x%04lX ", dwc2->hfnum_bm.num, ch_id, channel->hcchar_bm.ep_num, hcint);
+  //   print_hcint(hcint);
+  // }
+
+  if (hcint & HCINT_XFER_COMPLETE) {
+    if (edpt->hcchar_bm.ep_num != 0) {
+      edpt->next_pid = channel->hctsiz_bm.pid; // save pid (already toggled)
+    }
+
+    const uint16_t remain_packets = channel->hctsiz_bm.packet_count;
+    if (channel->hcsplt_bm.split_en && remain_packets && xfer->fifo_bytes == edpt->hcchar_bm.ep_size) {
+      // Split can only complete 1 transaction (up to 1 packet) at a time, schedule more
+      channel->hcsplt_bm.split_compl = 0;
+    } else {
+      xfer->result = XFER_RESULT_SUCCESS;
+    }
+
+    channel_disable(dwc2, channel);
+  } else if (hcint & (HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_STALL)) {
+    if (hcint & HCINT_STALL) {
+      xfer->result = XFER_RESULT_STALLED;
+    } else if (hcint & HCINT_BABBLE_ERR) {
+      xfer->result = XFER_RESULT_FAILED;
+    } else if (hcint & HCINT_XACT_ERR) {
+      xfer->err_count++;
+      channel->hcintmsk |= HCINT_ACK;
+    }
+
+    channel_disable(dwc2, channel);
+  } else if (hcint & HCINT_NYET) {
+    // restart complete split
+    channel->hcsplt_bm.split_compl = 1;
+    xfer->halted_nyet = 1;
+    channel_disable(dwc2, channel);
+  } else if (hcint & HCINT_NAK) {
+    // NAK received, re-enable channel if request queue is available
+    if (channel->hcsplt_bm.split_en) {
+      channel->hcsplt_bm.split_compl = 0; // restart with start-split
+    }
+
+    channel_disable(dwc2, channel);
+  } else if (hcint & HCINT_ACK) {
+    xfer->err_count = 0;
+
+    if (channel->hcsplt_bm.split_en) {
+      if (!channel->hcsplt_bm.split_compl) {
+        // start split is ACK --> do complete split
+        channel->hcintmsk |= HCINT_NYET;
+        channel->hcsplt_bm.split_compl = 1;
+        channel_send_in_token(dwc2, channel);
+      } else {
+        // do nothing for complete split with DATA, this will trigger XferComplete and handled there
+      }
+    } else {
+      // ACK with data
+      const uint16_t remain_packets = channel->hctsiz_bm.packet_count;
+      if (remain_packets) {
+        // still more packet to receive, also reset to start split
+        channel->hcsplt_bm.split_compl = 0;
+        channel_send_in_token(dwc2, channel);
+      }
+    }
+  } else if (hcint & HCINT_HALTED) {
+    channel->hcintmsk &= ~HCINT_HALTED;
+    if (xfer->halted_sof_schedule) {
+      // de-allocate channel but does not complete xfer, we schedule it in the SOF interrupt
+      channel_dealloc(dwc2, ch_id);
+    } else if (xfer->result != XFER_RESULT_INVALID) {
+      is_done = true;
+    } else if (xfer->err_count == HCD_XFER_ERROR_MAX) {
+      xfer->result = XFER_RESULT_FAILED;
+      is_done = true;
+    } else {
+      // got here due to NAK or NYET
+      channel_xfer_in_retry(dwc2, ch_id, hcint);
+    }
+  } else if (hcint & HCINT_DATATOGGLE_ERR) {
+    xfer->err_count = 0;
+    TU_ASSERT(false);
+  }
+  return is_done;
+}
+
+static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) {
+  hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+  dwc2_channel_t* channel = &dwc2->channel[ch_id];
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
+  bool is_done = false;
+
+  if (hcint & HCINT_XFER_COMPLETE) {
+    is_done = true;
+    xfer->result = XFER_RESULT_SUCCESS;
+    channel->hcintmsk &= ~HCINT_ACK;
+  } else if (hcint & HCINT_STALL) {
+    xfer->result = XFER_RESULT_STALLED;
+    channel_disable(dwc2, channel);
+  } else if (hcint & HCINT_NYET) {
+    xfer->err_count = 0;
+    if (channel->hcsplt_bm.split_en) {
+      // retry complete split
+      channel->hcsplt_bm.split_compl = 1;
+      channel->hcchar |= HCCHAR_CHENA;
+    } else {
+      edpt->do_ping = 1;
+      channel_xfer_out_wrapup(dwc2, ch_id);
+      channel_disable(dwc2, channel);
+    }
+  } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR)) {
+    // clean up transfer so far, disable and start again later
+    channel_xfer_out_wrapup(dwc2, ch_id);
+    channel_disable(dwc2, channel);
+    if (hcint & HCINT_XACT_ERR) {
+      xfer->err_count++;
+      channel->hcintmsk |= HCINT_ACK;
+    } else {
+      // NAK disable channel to flush all posted request and try again
+      edpt->do_ping = 1;
+      xfer->err_count = 0;
+    }
+  } else if (hcint & HCINT_HALTED) {
+    channel->hcintmsk &= ~HCINT_HALTED;
+    if (xfer->result != XFER_RESULT_INVALID) {
+      is_done = true;
+    } else if (xfer->err_count == HCD_XFER_ERROR_MAX) {
+      xfer->result = XFER_RESULT_FAILED;
+      is_done = true;
+    } else {
+      // Got here due to NAK or NYET
+      TU_ASSERT(channel_xfer_start(dwc2, ch_id));
+    }
+  } else if (hcint & HCINT_ACK) {
+    xfer->err_count = 0;
+    channel->hcintmsk &= ~HCINT_ACK;
+    if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) {
+      // start split is ACK --> do complete split
+      channel->hcsplt_bm.split_compl = 1;
+      channel->hcchar |= HCCHAR_CHENA;
+    }
+  }
+
+  if (is_done) {
+    xfer->xferred_bytes += xfer->fifo_bytes;
+    xfer->fifo_bytes = 0;
+  }
+
+  return is_done;
+}
+#endif
+
+#if CFG_TUH_DWC2_DMA_ENABLE
+static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) {
+  hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+  dwc2_channel_t* channel = &dwc2->channel[ch_id];
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
+
+  bool is_done = false;
+
+  // TU_LOG1("in  hcint = %02lX\r\n", hcint);
+
+  if (hcint & HCINT_HALTED) {
+    if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL | HCINT_BABBLE_ERR)) {
+      const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size;
+      const uint16_t remain_packets = channel->hctsiz_bm.packet_count;
+      const uint16_t actual_len = edpt->buflen - remain_bytes;
+      xfer->xferred_bytes += actual_len;
+
+      is_done = true;
+
+      if (hcint & HCINT_STALL) {
+        xfer->result = XFER_RESULT_STALLED;
+      } else if (hcint & HCINT_BABBLE_ERR) {
+        xfer->result = XFER_RESULT_FAILED;
+      } else if (channel->hcsplt_bm.split_en && remain_packets && actual_len == edpt->hcchar_bm.ep_size) {
+        // Split can only complete 1 transaction (up to 1 packet) at a time, schedule more
+        is_done = false;
+        edpt->buffer += actual_len;
+        edpt->buflen -= actual_len;
+
+        channel->hcsplt_bm.split_compl = 0;
+        channel_xfer_in_retry(dwc2, ch_id, hcint);
+      } else {
+        xfer->result = XFER_RESULT_SUCCESS;
+      }
+
+      xfer->err_count = 0;
+      channel->hcintmsk &= ~HCINT_ACK;
+    } else if (hcint & HCINT_XACT_ERR) {
+      xfer->err_count++;
+      if (xfer->err_count >=  HCD_XFER_ERROR_MAX) {
+        is_done = true;
+        xfer->result = XFER_RESULT_FAILED;
+      } else {
+        channel->hcintmsk |= HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR;
+        channel->hcsplt_bm.split_compl = 0;
+        channel_xfer_in_retry(dwc2, ch_id, hcint);
+      }
+    } else if (hcint & HCINT_NYET) {
+      // Must handle nyet before nak or ack. Could get a nyet at the same time as either of those on a BULK/CONTROL
+      // OUT that started with a PING. The nyet takes precedence.
+      if (channel->hcsplt_bm.split_en) {
+        // split not yet mean hub has no data, retry complete split
+        channel->hcsplt_bm.split_compl = 1;
+        channel_xfer_in_retry(dwc2, ch_id, hcint);
+      }
+    } else if (hcint & HCINT_ACK) {
+      xfer->err_count = 0;
+      channel->hcintmsk &= ~HCINT_ACK;
+      if (channel->hcsplt_bm.split_en) {
+        // start split is ACK --> do complete split
+        // TODO: for ISO must use xact_pos to plan complete split based on microframe (up to 187.5 bytes/uframe)
+        channel->hcsplt_bm.split_compl = 1;
+        if (edpt_is_periodic(channel->hcchar_bm.ep_type)) {
+          channel->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame
+        }
+        channel_send_in_token(dwc2, channel);
+      }
+    } else if (hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR)) {
+      xfer->err_count = 0;
+      channel->hcintmsk &= ~(HCINT_NAK | HCINT_DATATOGGLE_ERR);
+      channel->hcsplt_bm.split_compl = 0; // restart with start-split
+      channel_xfer_in_retry(dwc2, ch_id, hcint);
+    } else if (hcint & HCINT_FARME_OVERRUN) {
+      // retry start-split in next binterval
+      channel_xfer_in_retry(dwc2, ch_id, hcint);
+    }
+  }
+
+  return is_done;
+}
+
+static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) {
+  hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+  dwc2_channel_t* channel = &dwc2->channel[ch_id];
+  hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
+
+  bool is_done = false;
+
+  // TU_LOG1("out hcint = %02lX\r\n", hcint);
+
+  if (hcint & HCINT_HALTED) {
+    if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL)) {
+      is_done = true;
+      xfer->err_count = 0;
+      if (hcint & HCINT_XFER_COMPLETE) {
+        xfer->result = XFER_RESULT_SUCCESS;
+        xfer->xferred_bytes += edpt->buflen;
+      } else {
+        xfer->result = XFER_RESULT_STALLED;
+        channel_xfer_out_wrapup(dwc2, ch_id);
+      }
+      channel->hcintmsk &= ~HCINT_ACK;
+    } else if (hcint & HCINT_XACT_ERR) {
+     if (hcint & (HCINT_NAK | HCINT_NYET | HCINT_ACK)) {
+       xfer->err_count = 0;
+       // clean up transfer so far and start again
+       channel_xfer_out_wrapup(dwc2, ch_id);
+       channel_xfer_start(dwc2, ch_id);
+     } else {
+       xfer->err_count++;
+       if (xfer->err_count >= HCD_XFER_ERROR_MAX) {
+         xfer->result = XFER_RESULT_FAILED;
+         is_done = true;
+       } else {
+         // clean up transfer so far and start again
+         channel_xfer_out_wrapup(dwc2, ch_id);
+         channel_xfer_start(dwc2, ch_id);
+       }
+     }
+    } else if (hcint & HCINT_NYET) {
+      if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl) {
+        // split not yet mean hub has no data, retry complete split
+        channel->hcsplt_bm.split_compl = 1;
+        channel->hcchar |= HCCHAR_CHENA;
+      }
+    } else if (hcint & HCINT_ACK) {
+      xfer->err_count = 0;
+      if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) {
+        // start split is ACK --> do complete split
+        channel->hcsplt_bm.split_compl = 1;
+        channel->hcchar |= HCCHAR_CHENA;
+      }
+    }
+  } else if (hcint & HCINT_ACK) {
+    xfer->err_count = 0;
+    channel->hcintmsk &= ~HCINT_ACK;
+  }
+
+  return is_done;
+}
+#endif
+
+static void handle_channel_irq(uint8_t rhport, bool in_isr) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const bool is_dma = dma_host_enabled(dwc2);
+  const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
+
+  for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
+    if (tu_bit_test(dwc2->haint, ch_id)) {
+      dwc2_channel_t* channel = &dwc2->channel[ch_id];
+      hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+      TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,);
+      dwc2_channel_char_t hcchar_bm = channel->hcchar_bm;
+
+      const uint32_t hcint = channel->hcint;
+      channel->hcint = hcint; // clear interrupt
+
+      bool is_done = false;
+      if (is_dma) {
+        #if CFG_TUH_DWC2_DMA_ENABLE
+        if (hcchar_bm.ep_dir == TUSB_DIR_OUT) {
+          is_done = handle_channel_out_dma(dwc2, ch_id, hcint);
+        } else {
+          is_done = handle_channel_in_dma(dwc2, ch_id, hcint);
+          if (is_done && (channel->hcdma > xfer->xferred_bytes)) {
+            // hcdma is increased by word --> need to align4
+            hcd_dcache_invalidate((void*) tu_align4(channel->hcdma - xfer->xferred_bytes), xfer->xferred_bytes);
+          }
+        }
+        #endif
+      } else {
+        #if CFG_TUH_DWC2_SLAVE_ENABLE
+        if (hcchar_bm.ep_dir == TUSB_DIR_OUT) {
+          is_done = handle_channel_out_slave(dwc2, ch_id, hcint);
+        } else {
+          is_done = handle_channel_in_slave(dwc2, ch_id, hcint);
+        }
+        #endif
+      }
+
+      if (is_done) {
+        const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir);
+        hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->xferred_bytes, xfer->result, in_isr);
+        channel_dealloc(dwc2, ch_id);
+      }
+    }
+  }
+}
+
+// SOF is enabled for scheduled periodic transfer
+static bool handle_sof_irq(uint8_t rhport, bool in_isr) {
+  (void) in_isr;
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  bool more_isr = false;
+
+  // If highspeed then SOF is 125us, else 1ms
+  const uint32_t ucount = (hprt_speed_get(dwc2) == TUSB_SPEED_HIGH ? 1 : 8);
+
+  for(uint8_t ep_id = 0; ep_id < CFG_TUH_DWC2_ENDPOINT_MAX; ep_id++) {
+    hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
+    if (edpt->hcchar_bm.enable && edpt_is_periodic(edpt->hcchar_bm.ep_type) && edpt->uframe_countdown > 0) {
+      edpt->uframe_countdown -= tu_min32(ucount, edpt->uframe_countdown);
+      if (edpt->uframe_countdown == 0) {
+        if (!edpt_xfer_kickoff(dwc2, ep_id)) {
+          edpt->uframe_countdown = ucount; // failed to start, try again next frame
+        }
+      }
+
+      more_isr = true;
+    }
+  }
+
+  return more_isr;
+}
+
+// Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit)
+static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) {
+  uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL;
+
+  const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm;
+  uint32_t phy_clock;
+
+  if (gusbcfg_bm.phy_sel) {
+    phy_clock = 48; // dedicated FS is 48Mhz
+    if (speed == TUSB_SPEED_LOW) {
+      hcfg |= HCFG_FSLS_PHYCLK_SEL_6MHZ;
+    } else {
+      hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ;
+    }
+  } else {
+    if (gusbcfg_bm.ulpi_utmi_sel) {
+      phy_clock = 60; // ULPI 8-bit is 60Mhz
+    } else {
+      // UTMI+ 16-bit is 30Mhz, 8-bit is 60Mhz
+      phy_clock = gusbcfg_bm.phy_if16 ? 30 : 60;
+
+      // Enable UTMI+ low power mode 48Mhz external clock if not highspeed
+      if (speed == TUSB_SPEED_HIGH) {
+        dwc2->gusbcfg &= ~GUSBCFG_PHYLPCS;
+      } else {
+        dwc2->gusbcfg |= GUSBCFG_PHYLPCS;
+        // may need to reset port
+      }
+    }
+    hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ;
+  }
+
+  dwc2->hcfg = hcfg;
+
+  uint32_t hfir = dwc2->hfir & ~HFIR_FRIVL_Msk;
+  if (speed == TUSB_SPEED_HIGH) {
+    hfir |= 125*phy_clock;
+  } else {
+    hfir |= 1000*phy_clock;
+  }
+
+  dwc2->hfir = hfir;
+}
+
+/* Handle Host Port interrupt, possible source are:
+   - Connection Detection
+   - Enable Change
+   - Over Current Change
+*/
+static void handle_hprt_irq(uint8_t rhport, bool in_isr) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  uint32_t hprt = dwc2->hprt & ~HPRT_W1_MASK;
+  const dwc2_hprt_t hprt_bm = dwc2->hprt_bm;
+
+  if (dwc2->hprt & HPRT_CONN_DETECT) {
+    // Port Connect Detect
+    hprt |= HPRT_CONN_DETECT;
+
+    if (hprt_bm.conn_status) {
+      hcd_event_device_attach(rhport, in_isr);
+    } else {
+      hcd_event_device_remove(rhport, in_isr);
+    }
+  }
+
+  if (dwc2->hprt & HPRT_ENABLE_CHANGE) {
+    // Port enable change
+    hprt |= HPRT_ENABLE_CHANGE;
+
+    if (hprt_bm.enable) {
+      // Port enable
+      const tusb_speed_t speed = hprt_speed_get(dwc2);
+      port0_enable(dwc2, speed);
+    } else {
+      // TU_ASSERT(false, );
+    }
+  }
+
+  dwc2->hprt = hprt; // clear interrupt
+}
+
+/* Interrupt Hierarchy
+               HCINTn       HPRT
+                 |           |
+               HAINT.CHn     |
+                 |           |
+    GINTSTS :  HCInt     | PrtInt | NPTxFEmp | PTxFEmpp | RXFLVL | SOF
+*/
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const uint32_t gintmsk = dwc2->gintmsk;
+  const uint32_t gintsts = dwc2->gintsts & gintmsk;
+
+  // TU_LOG1_HEX(gintsts);
+
+  if (gintsts & GINTSTS_CONIDSTSCHNG) {
+    // Connector ID status change
+    dwc2->gintsts = GINTSTS_CONIDSTSCHNG;
+
+    //if (dwc2->gotgctl)
+    // dwc2->hprt = HPRT_POWER; // power on port to turn on VBUS
+    //dwc2->gintmsk |= GINTMSK_PRTIM;
+    // TODO wait for SRP if OTG
+  }
+
+  if (gintsts & GINTSTS_SOF) {
+    const bool more_sof = handle_sof_irq(rhport, in_isr);
+    if (!more_sof) {
+      dwc2->gintmsk &= ~GINTSTS_SOF;
+    }
+  }
+
+  if (gintsts & GINTSTS_HPRTINT) {
+    // Host port interrupt: source is cleared in HPRT register
+    // TU_LOG1_HEX(dwc2->hprt);
+    handle_hprt_irq(rhport, in_isr);
+  }
+
+  if (gintsts & GINTSTS_HCINT) {
+    // Host Channel interrupt: source is cleared in HCINT register
+    // must be handled after TX FIFO empty
+    handle_channel_irq(rhport, in_isr);
+  }
+
+#if CFG_TUH_DWC2_SLAVE_ENABLE
+  // RxFIFO non-empty interrupt handling
+  if (gintsts & GINTSTS_RXFLVL) {
+    // RXFLVL bit is read-only
+    dwc2->gintmsk &= ~GINTSTS_RXFLVL; // disable RXFLVL interrupt while reading
+
+    do {
+      handle_rxflvl_irq(rhport); // read all packets
+    } while(dwc2->gintsts & GINTSTS_RXFLVL);
+
+    dwc2->gintmsk |= GINTSTS_RXFLVL;
+  }
+
+  if (gintsts & GINTSTS_NPTX_FIFO_EMPTY) {
+    // NPTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written
+    const bool more_nptxfe = handle_txfifo_empty(dwc2, false);
+    if (!more_nptxfe) {
+      // no more pending packet, disable interrupt
+      dwc2->gintmsk &= ~GINTSTS_NPTX_FIFO_EMPTY;
+    }
+  }
+
+  if (gintsts & GINTSTS_PTX_FIFO_EMPTY) {
+    // PTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written
+    const bool more_ptxfe = handle_txfifo_empty(dwc2, true);
+    if (!more_ptxfe) {
+      // no more pending packet, disable interrupt
+      dwc2->gintmsk &= ~GINTSTS_PTX_FIFO_EMPTY;
+    }
+  }
+#endif
+}
+
+#endif
diff --git a/src/portable/synopsys/dwc2/hwcfg_list.md b/src/portable/synopsys/dwc2/hwcfg_list.md
deleted file mode 100644
index b5590da00..000000000
--- a/src/portable/synopsys/dwc2/hwcfg_list.md
+++ /dev/null
@@ -1,777 +0,0 @@
-# DWC2 Hardware Configuration Registers
-
-## Broadcom BCM2711 (Pi4)
-
-dwc2->guid = 2708A000
-dwc2->gsnpsid = 4F54280A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 228DDD50
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 1
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 7
-hw_cfg2->num_host_ch = 7
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 0
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = FF000E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 4080
-
-dwc2->ghwcfg4 = 1FF00020
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 0
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 15
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## EFM32GG FS
-
-dwc2->guid = 0
-dwc2->gsnpsid = 4F54330A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 228F5910
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 6
-hw_cfg2->num_host_ch = 13
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 0
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 1F204E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 1
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 498
-
-dwc2->ghwcfg4 = 1BF08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 13
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## ESP32-S2 Fullspeed
-
-dwc2->guid = 0
-dwc2->gsnpsid = 4F54400A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 224DD930
-hw_cfg2->op_mode = 2
-hw_cfg2->arch = 3
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 1
-hw_cfg2->fs_phy_type = 2
-hw_cfg2->num_dev_ep = 6
-hw_cfg2->num_host_ch = 9
-hw_cfg2->period_channel_support = 0
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 1
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 22
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = C804B5
-hw_cfg3->xfer_size_width = 10
-hw_cfg3->packet_size_width = 5
-hw_cfg3->otg_enable = 0
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 1
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 1
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 23130
-
-dwc2->ghwcfg4 = D3F0A030
-hw_cfg4->num_dev_period_in_ep = 10
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 0
-hw_cfg4->hibernation = 1
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 1
-hw_cfg4->acg_enable = 1
-hw_cfg4->utmi_phy_data_width = 1
-hw_cfg4->dev_ctrl_ep_num = 10
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 0
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 0
-hw_cfg4->dedicated_fifos = 0
-hw_cfg4->num_dev_in_eps = 13
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 1
-
-## STM32F407 and STM32F207
-
-STM32F407 and STM32F207 are exactly the same
-
-### STM32F407 Fullspeed
-
-dwc2->guid = 1200
-dwc2->gsnpsid = 4F54281A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229DCD20
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 3
-hw_cfg2->num_host_ch = 7
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 20001E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = FF08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 7
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-### STM32F407 Highspeed
-
-dwc2->guid = 1100
-dwc2->gsnpsid = 4F54281A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED590
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 2
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 3F403E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 1
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 1012
-
-dwc2->ghwcfg4 = 17F00030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32F411 Fullspeed
-
-dwc2->guid = 1200
-dwc2->gsnpsid = 4F54281A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229DCD20
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 3
-hw_cfg2->num_host_ch = 7
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 20001E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = FF08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 7
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32F412 FS
-
-dwc2->guid = 2000
-dwc2->gsnpsid = 4F54320A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED520
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 200D1E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = 17F08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32F723
-
-### STM32F723 HighSpeed
-
-dwc2->guid = 3100
-dwc2->gsnpsid = 4F54330A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229FE1D0
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 3
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 8
-hw_cfg2->num_host_ch = 15
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 3EED2E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 1
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 1006
-
-dwc2->ghwcfg4 = 23F00030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 1
-hw_cfg4->dma_desc_enable = 1
-hw_cfg4->dma_dynamic = 0
-
-### STM32F723 Fullspeed
-
-dwc2->guid = 3000
-dwc2->gsnpsid = 4F54330A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED520
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 200D1E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = 17F08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32F767 FS
-
-dwc2->guid = 2000
-dwc2->gsnpsid = 4F54320A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED520
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 200D1E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = 17F08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32H743 (both cores HS)
-
-dwc2->guid = 2300
-dwc2->gsnpsid = 4F54330A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229FE190
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 2
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 8
-hw_cfg2->num_host_ch = 15
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 3B8D2E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 1
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 952
-
-dwc2->ghwcfg4 = E3F00030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 1
-hw_cfg4->dma_desc_enable = 1
-hw_cfg4->dma_dynamic = 1
-
-## STM32L476 FS
-
-dwc2->guid = 2000
-dwc2->gsnpsid = 4F54310A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED520
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 200D1E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = 17F08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## GD32VF103 Fullspeed
-
-dwc2->guid = 1000
-dwc2->gsnpsid = 0
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 0
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 0
-hw_cfg2->num_dev_ep = 0
-hw_cfg2->num_host_ch = 0
-hw_cfg2->period_channel_support = 0
-hw_cfg2->enable_dynamic_fifo = 0
-hw_cfg2->mul_cpu_int = 0
-hw_cfg2->nperiod_tx_q_depth = 0
-hw_cfg2->host_period_tx_q_depth = 0
-hw_cfg2->dev_token_q_depth = 0
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 0
-hw_cfg3->xfer_size_width = 0
-hw_cfg3->packet_size_width = 0
-hw_cfg3->otg_enable = 0
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 0
-
-dwc2->ghwcfg4 = 0
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 0
-hw_cfg4->ahb_freq_min = 0
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 0
-hw_cfg4->vbus_valid_filter_enabled = 0
-hw_cfg4->a_valid_filter_enabled = 0
-hw_cfg4->b_valid_filter_enabled = 0
-hw_cfg4->dedicated_fifos = 0
-hw_cfg4->num_dev_in_eps = 0
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## XMC4500
-
-dwc2->guid = AEC000
-dwc2->gsnpsid = 4F54292A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 228F5930
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 6
-hw_cfg2->num_host_ch = 13
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 0
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 27A01E5
-hw_cfg3->xfer_size_width = 5
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 634
-
-dwc2->ghwcfg4 = DBF08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 13
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 1
diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c
index 26b5dce9d..3738ac0cb 100644
--- a/src/portable/template/dcd_template.c
+++ b/src/portable/template/dcd_template.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_NONE
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_NONE
 
 #include "device/dcd.h"
 
@@ -40,54 +40,45 @@
  *------------------------------------------------------------------*/
 
 // Initialize controller to device mode
-void dcd_init (uint8_t rhport)
-{
-  (void) rhport;
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rhport; (void) rh_init;
+  return true;
 }
 
 // Enable device interrupt
-void dcd_int_enable (uint8_t rhport)
-{
+void dcd_int_enable (uint8_t rhport) {
   (void) rhport;
 }
 
 // Disable device interrupt
-void dcd_int_disable (uint8_t rhport)
-{
+void dcd_int_disable (uint8_t rhport) {
   (void) rhport;
 }
 
 // Receive Set Address request, mcu port must also include status IN response
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr) {
   (void) rhport;
   (void) dev_addr;
 }
 
 // Wake up host
-void dcd_remote_wakeup (uint8_t rhport)
-{
+void dcd_remote_wakeup (uint8_t rhport) {
   (void) rhport;
 }
 
 // Connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(uint8_t rhport)
-{
+void dcd_connect(uint8_t rhport) {
   (void) rhport;
 }
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(uint8_t rhport)
-{
+void dcd_disconnect(uint8_t rhport) {
   (void) rhport;
 }
 
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
   (void) rhport;
   (void) en;
-
-  // TODO implement later
 }
 
 //--------------------------------------------------------------------+
@@ -95,21 +86,34 @@ void dcd_sof_enable(uint8_t rhport, bool en)
 //--------------------------------------------------------------------+
 
 // Configure endpoint's registers according to descriptor
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
-{
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) {
   (void) rhport;
   (void) ep_desc;
   return false;
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
-{
+// Allocate packet buffer used by ISO endpoints
+// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
+  (void) rhport;
+  (void) ep_addr;
+  (void) largest_packet_size;
+  return false;
+}
+
+// Configure and enable an ISO endpoint according to descriptor
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) {
+  (void) rhport;
+  (void) desc_ep;
+  return false;
+}
+
+void dcd_edpt_close_all (uint8_t rhport) {
   (void) rhport;
 }
 
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) {
   (void) rhport;
   (void) ep_addr;
   (void) buffer;
@@ -118,8 +122,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 }
 
 // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) {
   (void) rhport;
   (void) ep_addr;
   (void) ff;
@@ -128,15 +131,13 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 }
 
 // Stall endpoint
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
   (void) ep_addr;
 }
 
 // clear stall, data toggle is also reset to DATA0
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
   (void) ep_addr;
 }
diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c
new file mode 100644
index 000000000..d8bca196f
--- /dev/null
+++ b/src/portable/template/hcd_template.c
@@ -0,0 +1,163 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && CFG_TUSB_MCU == OPT_MCU_NONE
+
+#include "host/hcd.h"
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// optional hcd configuration, called by tuh_configure()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  (void) cfg_id;
+  (void) cfg_param;
+
+  return false;
+}
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rhport;
+  (void) rh_init;
+  return false;
+}
+
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void) rhport;
+  (void) in_isr;
+}
+
+// Enable USB interrupt
+void hcd_int_enable (uint8_t rhport) {
+  (void) rhport;
+}
+
+// Disable USB interrupt
+void hcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport) {
+  (void) rhport;
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport) {
+  (void) rhport;
+
+  return false;
+}
+
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
+void hcd_port_reset(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Complete bus reset sequence, may be required by some controllers
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  (void) rhport;
+
+  return TUSB_SPEED_FULL;
+}
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_desc;
+
+  return false;
+}
+
+// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  (void) buffer;
+  (void) buflen;
+
+  return false;
+}
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) setup_packet;
+
+  return false;
+}
+
+// clear stall, data toggle is also reset to DATA0
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+#endif
diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index b4dfda575..3752ae251 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -94,7 +94,8 @@ static void bus_reset(void)
   USBOEPCNT_0 &= ~NAK;
   USBIEPCNT_0 &= ~NAK;
 
-  USBCTL |= FEN; // Enable responding to packets.
+  // Enable responding to packets.
+  USBCTL |= FEN;
 
   // Dedicated buffers in hardware for SETUP and EP0, no setup needed.
   // Now safe to respond to SETUP packets.
@@ -103,13 +104,34 @@ static void bus_reset(void)
   USBKEYPID = 0;
 }
 
+// Controls reset behavior of the USB module on receipt of a bus reset event.
+// - enable: When true, bus reset events will cause a reset the USB module.
+static void enable_functional_reset(const bool enable)
+{
+  // Check whether or not the USB configuration registers were
+  // locked prior to this function being called so that, if
+  // necessary, the lock state can be restored on exit.
+  bool unlocked = (USBKEYPID == 0xA528) ? true : false;
+
+  if(!unlocked) USBKEYPID = USBKEY;
+
+  if(enable)
+  {
+    USBCTL |= FRSTE;
+  }
+  else
+  {
+    USBCTL &= ~FRSTE;
+  }
+
+  if(!unlocked) USBKEYPID = 0;
+}
 
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
-void dcd_init (uint8_t rhport)
-{
-  (void) rhport;
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rhport; (void) rh_init;
 
   USBKEYPID = USBKEY;
 
@@ -131,13 +153,18 @@ void dcd_init (uint8_t rhport)
 
   USBVECINT = 0;
 
-  // Enable reset and wait for it before continuing.
-  USBIE |= RSTRIE;
-
-  // Enable pullup.
-  USBCNF |= PUR_EN;
+  if(USBPWRCTL & USBBGVBV) {// Bus power detected?
+    USBPWRCTL |= VBOFFIE;   // Enable bus-power-removed interrupt.
+    USBIE |= RSTRIE;        // Enable reset and wait for it before continuing.
+    USBCNF |= PUR_EN;       // Enable pullup.
+  } else {
+    USBPWRCTL |= VBONIE;    // Enable bus-power-applied interrupt.
+    USBCNF &= ~USB_EN;      // Disable USB module until bus power is detected.
+  }
 
   USBKEYPID = 0;
+
+  return true;
 }
 
 // There is no "USB peripheral interrupt disable" bit on MSP430, so we have
@@ -306,6 +333,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   return true;
 }
 
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport; (void) ep_addr;
+  // TODO implement dcd_edpt_close()
+}
+
 void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
@@ -610,14 +642,80 @@ static void handle_setup_packet(void)
     _setup_packet[i] = setup_buf[i];
   }
 
-  // Clearing SETUPIFG by reading USBVECINT does not set NAK, so now that we
-  // have a SETUP packet, force NAKs until tinyusb can handle the SETUP
-  // packet and prepare for a new xfer.
+  // Force NAKs until tinyusb can handle the SETUP packet and prepare for a new xfer.
   USBIEPCNT_0 |= NAK;
   USBOEPCNT_0 |= NAK;
+
+  // Clear SETUPIFG to avoid handling in the USBVECINT switch statement.
+  // When handled there the NAKs applied to the endpoints above are
+  // cleared by hardware and the host will receive stale/duplicate data.
+  //
+  // Excerpt from MSP430x5xx and MSP430x6xx Family User's Guide:
+  //
+  // "...the SETUPIFG is cleared upon reading USBIV. In addition, the NAK on
+  // input endpoint 0 and output endpoint 0 is also cleared."
+  USBIEPCNF_0 &= ~UBME; // Errata USB10 workaround.
+  USBOEPCNF_0 &= ~UBME; // Errata USB10 workaround.
+  USBIFG &= ~SETUPIFG;
+  USBIEPCNF_0 |= UBME;  // Errata USB10 workaround.
+  USBOEPCNF_0 |= UBME;  // Errata USB10 workaround.
   dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true);
 }
 
+#if CFG_TUSB_OS == OPT_OS_NONE
+TU_ATTR_ALWAYS_INLINE static inline void tu_delay(uint32_t ms) {
+  // msp430 can run up to 25Mhz -> 40ns per cycle. 1 ms = 25000 cycles
+  // each loop need 4 cycle: 1 sub, 1 cmp, 1 jump, 1 nop
+  volatile uint32_t cycles = (25000 * ms) >> 2;
+  while (cycles > 0) {
+    cycles--;
+    asm("nop");
+  }
+}
+#else
+#define tu_delay(ms) osal_task_delay(ms)
+#endif
+
+static void handle_bus_power_event(void *param) {
+  (void) param;
+
+  tu_delay(5);                 // Bus power settling delay.
+
+  USBKEYPID = USBKEY;
+
+  if(USBPWRCTL & USBBGVBV) {          // Event caused by application of bus power.
+    USBPWRCTL |= VBOFFIE;             // Enable bus-power-removed interrupt.
+    USBPLLDIVB = USBPLLDIVB;          // For some reason the PLL will *NOT* lock unless the divider
+                                      // register is re-written. The assumption here is that this
+                                      // register was already properly configured during board-level
+                                      // initialization.
+    USBPLLCTL |= (UPLLEN | UPFDEN);   // Enable the PLL.
+
+    uint16_t attempts = 0;
+    do {                              // Poll the PLL, checking for a successful lock.
+      USBPLLIR = 0;
+      tu_delay(1);
+      attempts++;
+    } while ((attempts < 10) && (USBPLLIR != 0));
+
+    // A successful lock is indicated by all PLL-related interrupt flags being cleared.
+    if(!USBPLLIR) {
+      const tusb_rhport_init_t rhport_init = {
+        .role = TUSB_ROLE_DEVICE,
+        .speed = TUSB_SPEED_FULL
+      };
+      dcd_init(0, &rhport_init);         // Re-initialize the USB module.
+    }
+  } else {                            // Event caused by removal of bus power.
+    USBPWRCTL |= VBONIE;              // Enable bus-power-applied interrupt.
+    USBPLLCTL &= ~(UPLLEN | UPFDEN);  // Disable the PLL.
+    USBCNF = 0;                       // Disable the USB module.
+    dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, false);
+  }
+
+  USBKEYPID = 0;
+}
+
 void dcd_int_handler(uint8_t rhport)
 {
   (void) rhport;
@@ -628,6 +726,7 @@ void dcd_int_handler(uint8_t rhport)
 
   if(setup_status)
   {
+    enable_functional_reset(true);
     handle_setup_packet();
   }
 
@@ -646,11 +745,32 @@ void dcd_int_handler(uint8_t rhport)
 
   switch(curr_vector)
   {
+    case USBVECINT_NONE:
+      break;
+
     case USBVECINT_RSTR:
+      enable_functional_reset(false); // Errata USB4 workaround.
       bus_reset();
       dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
       break;
 
+    case USBVECINT_PWR_VBUSOn:
+    case USBVECINT_PWR_VBUSOff: {
+      USBKEYPID = USBKEY;
+      // Prevent (possibly) unstable power from generating spurious interrupts.
+      USBPWRCTL &= ~(VBONIE | VBOFFIE);
+      USBKEYPID = 0;
+
+      dcd_event_t event;
+
+      event.rhport = 0;
+      event.event_id = USBD_EVENT_FUNC_CALL;
+      event.func_call.func = handle_bus_power_event;
+
+      dcd_event_handler(&event, true);
+      }
+      break;
+
     // Clear the (hardware-enforced) NAK on EP 0 after a SETUP packet
     // is received. At this point, even though the hardware is no longer
     // forcing NAKs, the EP0 NAK bits should still be set to avoid
@@ -675,10 +795,12 @@ void dcd_int_handler(uint8_t rhport)
       break;
 
     case USBVECINT_INPUT_ENDPOINT0:
+      enable_functional_reset(true);
       transmit_packet(0);
       break;
 
     case USBVECINT_OUTPUT_ENDPOINT0:
+      enable_functional_reset(true);
       receive_packet(0);
       break;
 
@@ -710,7 +832,6 @@ void dcd_int_handler(uint8_t rhport)
 
     default:
       while(true);
-      break;
   }
 
 }
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
index e368b5f39..a03c94558 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -336,9 +336,9 @@ static void dcd_reset(void)
 }
 
 // Initializes the USB peripheral for device mode and enables it.
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   (void) rhport;
+  (void) rh_init;
 
   usb_pullup_out_write(0);
 
@@ -352,6 +352,8 @@ void dcd_init(uint8_t rhport)
 
   // Turn on the external pullup
   usb_pullup_out_write(1);
+
+  return true;
 }
 
 // Enables or disables the USB device interrupt(s). May be used to
@@ -436,6 +438,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport; (void) ep_addr;
+  // TODO implement dcd_edpt_close()
+}
+
 void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
@@ -465,7 +472,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
       enable = 1;
     usb_out_ctrl_write((0 << CSR_USB_OUT_CTRL_STALL_OFFSET) | (enable << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | tu_edpt_number(ep_addr));
   }
-  // IN endpoints will get unstalled when more data is written.
+  // IN endpoints will get un-stalled when more data is written.
 }
 
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.h b/src/portable/valentyusb/eptri/dcd_eptri.h
index 0fa6ecc64..d67635d7c 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.h
+++ b/src/portable/valentyusb/eptri/dcd_eptri.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/portable/wch/ch32_usbfs_reg.h b/src/portable/wch/ch32_usbfs_reg.h
new file mode 100644
index 000000000..68be64f5e
--- /dev/null
+++ b/src/portable/wch/ch32_usbfs_reg.h
@@ -0,0 +1,175 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Matthew Tran
+ * Copyright (c) 2024 hathach
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef USB_CH32_USBFS_REG_H
+#define USB_CH32_USBFS_REG_H
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_CH32F20X
+  #include <ch32f20x.h>
+#elif CFG_TUSB_MCU == OPT_MCU_CH32V103
+  #include <ch32v10x.h>
+  typedef struct
+  {
+    __IO uint8_t  BASE_CTRL;
+    __IO uint8_t  UDEV_CTRL;
+    __IO uint8_t  INT_EN;
+    __IO uint8_t  DEV_ADDR;
+    __IO uint8_t  Reserve0;
+    __IO uint8_t  MIS_ST;
+    __IO uint8_t  INT_FG;
+    __IO uint8_t  INT_ST;
+    __IO uint32_t RX_LEN;
+    __IO uint8_t  UEP4_1_MOD;
+    __IO uint8_t  UEP2_3_MOD;
+    __IO uint8_t  UEP5_6_MOD;
+    __IO uint8_t  UEP7_MOD;
+    __IO uint32_t UEP0_DMA;
+    __IO uint32_t UEP1_DMA;
+    __IO uint32_t UEP2_DMA;
+    __IO uint32_t UEP3_DMA;
+    __IO uint32_t UEP4_DMA;
+    __IO uint32_t UEP5_DMA;
+    __IO uint32_t UEP6_DMA;
+    __IO uint32_t UEP7_DMA;
+    __IO uint16_t UEP0_TX_LEN;
+    __IO uint8_t  UEP0_TX_CTRL;
+    __IO uint8_t  UEP0_RX_CTRL;
+    __IO uint16_t UEP1_TX_LEN;
+    __IO uint8_t  UEP1_TX_CTRL;
+    __IO uint8_t  UEP1_RX_CTRL;
+    __IO uint16_t UEP2_TX_LEN;
+    __IO uint8_t  UEP2_TX_CTRL;
+    __IO uint8_t  UEP2_RX_CTRL;
+    __IO uint16_t UEP3_TX_LEN;
+    __IO uint8_t  UEP3_TX_CTRL;
+    __IO uint8_t  UEP3_RX_CTRL;
+    __IO uint16_t UEP4_TX_LEN;
+    __IO uint8_t  UEP4_TX_CTRL;
+    __IO uint8_t  UEP4_RX_CTRL;
+    __IO uint16_t UEP5_TX_LEN;
+    __IO uint8_t  UEP5_TX_CTRL;
+    __IO uint8_t  UEP5_RX_CTRL;
+    __IO uint16_t UEP6_TX_LEN;
+    __IO uint8_t  UEP6_TX_CTRL;
+    __IO uint8_t  UEP6_RX_CTRL;
+    __IO uint16_t UEP7_TX_LEN;
+    __IO uint8_t  UEP7_TX_CTRL;
+    __IO uint8_t  UEP7_RX_CTRL;
+    __IO uint32_t Reserve1;
+    __IO uint32_t OTG_CR;
+    __IO uint32_t OTG_SR;
+  } USBOTG_FS_TypeDef;
+
+  #define USBOTG_FS ((USBOTG_FS_TypeDef *) 0x40023400)
+#elif CFG_TUSB_MCU == OPT_MCU_CH32V20X
+  #include <ch32v20x.h>
+#elif CFG_TUSB_MCU == OPT_MCU_CH32V307
+  #include <ch32v30x.h>
+  #define USBHD_IRQn OTG_FS_IRQn
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+// CTRL
+#define USBFS_CTRL_DMA_EN    (1 << 0)
+#define USBFS_CTRL_CLR_ALL   (1 << 1)
+#define USBFS_CTRL_RESET_SIE (1 << 2)
+#define USBFS_CTRL_INT_BUSY  (1 << 3)
+#define USBFS_CTRL_SYS_CTRL  (1 << 4)
+#define USBFS_CTRL_DEV_PUEN  (1 << 5)
+#define USBFS_CTRL_LOW_SPEED (1 << 6)
+#define USBFS_CTRL_HOST_MODE (1 << 7)
+
+// INT_EN
+#define USBFS_INT_EN_BUS_RST  (1 << 0)
+#define USBFS_INT_EN_DETECT   (1 << 0)
+#define USBFS_INT_EN_TRANSFER (1 << 1)
+#define USBFS_INT_EN_SUSPEND  (1 << 2)
+#define USBFS_INT_EN_HST_SOF  (1 << 3)
+#define USBFS_INT_EN_FIFO_OV  (1 << 4)
+#define USBFS_INT_EN_DEV_NAK  (1 << 6)
+#define USBFS_INT_EN_DEV_SOF  (1 << 7)
+
+// INT_FG
+#define USBFS_INT_FG_BUS_RST  (1 << 0)
+#define USBFS_INT_FG_DETECT   (1 << 0)
+#define USBFS_INT_FG_TRANSFER (1 << 1)
+#define USBFS_INT_FG_SUSPEND  (1 << 2)
+#define USBFS_INT_FG_HST_SOF  (1 << 3)
+#define USBFS_INT_FG_FIFO_OV  (1 << 4)
+#define USBFS_INT_FG_SIE_FREE (1 << 5)
+#define USBFS_INT_FG_TOG_OK   (1 << 6)
+#define USBFS_INT_FG_IS_NAK   (1 << 7)
+
+// INT_ST
+#define USBFS_INT_ST_MASK_UIS_ENDP(x)  (((x) >> 0) & 0x0F)
+#define USBFS_INT_ST_MASK_UIS_TOKEN(x) (((x) >> 4) & 0x03)
+
+// UDEV_CTRL
+#define USBFS_UDEV_CTRL_PORT_EN   (1 << 0)
+#define USBFS_UDEV_CTRL_GP_BIT    (1 << 1)
+#define USBFS_UDEV_CTRL_LOW_SPEED (1 << 2)
+#define USBFS_UDEV_CTRL_DM_PIN    (1 << 4)
+#define USBFS_UDEV_CTRL_DP_PIN    (1 << 5)
+#define USBFS_UDEV_CTRL_PD_DIS    (1 << 7)
+
+// TX_CTRL
+#define USBFS_EP_T_RES_MASK (3 << 0)
+#define USBFS_EP_T_TOG      (1 << 2)
+#define USBFS_EP_T_AUTO_TOG (1 << 3)
+
+#define USBFS_EP_T_RES_ACK   (0 << 0)
+#define USBFS_EP_T_RES_NYET  (1 << 0)
+#define USBFS_EP_T_RES_NAK   (2 << 0)
+#define USBFS_EP_T_RES_STALL (3 << 0)
+
+// RX_CTRL
+#define USBFS_EP_R_RES_MASK (3 << 0)
+#define USBFS_EP_R_TOG      (1 << 2)
+#define USBFS_EP_R_AUTO_TOG (1 << 3)
+
+#define USBFS_EP_R_RES_ACK   (0 << 0)
+#define USBFS_EP_R_RES_NYET  (1 << 0)
+#define USBFS_EP_R_RES_NAK   (2 << 0)
+#define USBFS_EP_R_RES_STALL (3 << 0)
+
+// token PID
+#define PID_OUT   0
+#define PID_SOF   1
+#define PID_IN    2
+#define PID_SETUP 3
+
+#endif // USB_CH32_USBFS_REG_H
diff --git a/src/portable/wch/ch32_usbhs_reg.h b/src/portable/wch/ch32_usbhs_reg.h
new file mode 100644
index 000000000..87300b497
--- /dev/null
+++ b/src/portable/wch/ch32_usbhs_reg.h
@@ -0,0 +1,395 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Matthew Tran
+ * Copyright (c) 2024 hathach
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef USB_CH32_USBHS_REG_H
+#define USB_CH32_USBHS_REG_H
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_CH32V307
+  #include <ch32v30x.h>
+#elif CFG_TUSB_MCU == OPT_MCU_CH32F20X
+  #include <ch32f20x.h>
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+
+/******************* GLOBAL ******************/
+
+// USB CONTROL
+#define USBHS_CONTROL_OFFSET 0x00
+#define USBHS_DMA_EN         (1 << 0)
+#define USBHS_ALL_CLR        (1 << 1)
+#define USBHS_FORCE_RST      (1 << 2)
+#define USBHS_INT_BUSY_EN    (1 << 3)
+#define USBHS_DEV_PU_EN      (1 << 4)
+#define USBHS_SPEED_MASK     (3 << 5)
+#define USBHS_FULL_SPEED     (0 << 5)
+#define USBHS_HIGH_SPEED     (1 << 5)
+#define USBHS_LOW_SPEED      (2 << 5)
+#define USBHS_HOST_MODE      (1 << 7)
+
+// USB_INT_EN
+#define USBHS_INT_EN_OFFSET 0x02
+#define USBHS_BUS_RST_EN    (1 << 0)
+#define USBHS_DETECT_EN     (1 << 0)
+#define USBHS_TRANSFER_EN   (1 << 1)
+#define USBHS_SUSPEND_EN    (1 << 2)
+#define USBHS_SOF_ACT_EN    (1 << 3)
+#define USBHS_FIFO_OV_EN    (1 << 4)
+#define USBHS_SETUP_ACT_EN  (1 << 5)
+#define USBHS_ISO_ACT_EN    (1 << 6)
+#define USBHS_DEV_NAK_EN    (1 << 7)
+
+// USB DEV AD
+#define USBHS_DEV_AD_OFFSET 0x03
+
+// USB FRAME_NO
+#define USBHS_FRAME_NO_OFFSET 0x04
+#define USBHS_FRAME_NO_NUM_MASK (0x7FF)
+#define USBHS_FRAME_NO_MICROFRAME_SHIFT (11)
+#define USBHS_FRAME_NO_MICROFRAME_MASK  (0x7 << USBHS_FRAME_NO_MICROFRAME_SHIFT)
+
+// USB SUSPEND
+#define USBHS_SUSPEND_OFFSET    0x06
+#define USBHS_DEV_REMOTE_WAKEUP (1 << 2)
+#define USBHS_LINESTATE_MASK    (2 << 4) /* Read Only */
+
+// RESERVED0
+
+// USB SPEED TYPE
+#define USBHS_SPEED_TYPE_OFFSET 0x08
+#define USBHS_SPEED_TYPE_MASK    0x03
+#define USBHS_SPEED_TYPE_FULL    0
+#define USBHS_SPEED_TYPE_HIGH    1
+#define USBHS_SPEED_TYPE_LOW     2
+
+// USB_MIS_ST
+#define USBHS_MIS_ST_OFFSET 0x09
+#define USBHS_SPLIT_CAN     (1 << 0)
+#define USBHS_ATTACH        (1 << 1)
+#define USBHS_SUSPEND       (1 << 2)
+#define USBHS_BUS_RESET     (1 << 3)
+#define USBHS_R_FIFO_RDY    (1 << 4)
+#define USBHS_SIE_FREE      (1 << 5)
+#define USBHS_SOF_ACT       (1 << 6)
+#define USBHS_SOF_PRES      (1 << 7)
+
+// INT_FLAG
+#define USBHS_INT_FLAG_OFFSET 0x0A
+#define USBHS_BUS_RST_FLAG    (1 << 0)
+#define USBHS_DETECT_FLAG     (1 << 0)
+#define USBHS_TRANSFER_FLAG   (1 << 1)
+#define USBHS_SUSPEND_FLAG    (1 << 2)
+#define USBHS_HST_SOF_FLAG    (1 << 3)
+#define USBHS_FIFO_OV_FLAG    (1 << 4)
+#define USBHS_SETUP_FLAG      (1 << 5)
+#define USBHS_ISO_ACT_FLAG    (1 << 6)
+
+// INT_ST
+#define USBHS_INT_ST_OFFSET   0x0B
+#define USBHS_DEV_UIS_IS_NAK  (1 << 7)
+#define USBHS_DEV_UIS_TOG_OK  (1 << 6)
+#define MASK_UIS_TOKEN        (3 << 4)
+#define USBHS_TOKEN_PID_OUT   (0 << 4)
+#define USBHS_TOKEN_PID_SOF   (1 << 4)
+#define USBHS_TOKEN_PID_IN    (2 << 4)
+#define USBHS_TOKEN_PID_SETUP (3 << 4)
+#define MASK_UIS_ENDP         (0x0F)
+#define MASK_UIS_H_RES        (0x0F)
+
+#define USBHS_TOGGLE_OK (0x40)
+#define USBHS_HOST_RES  (0x0f)
+
+//USB_RX_LEN
+#define USBHS_RX_LEN_OFFSET 0x0C
+/******************* DEVICE ******************/
+
+//UEP_CONFIG
+#define USBHS_UEP_CONFIG_OFFSET 0x10
+#define USBHS_EP0_T_EN          (1 << 0)
+#define USBHS_EP0_R_EN          (1 << 16)
+
+#define USBHS_EP1_T_EN (1 << 1)
+#define USBHS_EP1_R_EN (1 << 17)
+
+#define USBHS_EP2_T_EN (1 << 2)
+#define USBHS_EP2_R_EN (1 << 18)
+
+#define USBHS_EP3_T_EN (1 << 3)
+#define USBHS_EP3_R_EN (1 << 19)
+
+#define USBHS_EP4_T_EN (1 << 4)
+#define USBHS_EP4_R_EN (1 << 20)
+
+#define USBHS_EP5_T_EN (1 << 5)
+#define USBHS_EP5_R_EN (1 << 21)
+
+#define USBHS_EP6_T_EN (1 << 6)
+#define USBHS_EP6_R_EN (1 << 22)
+
+#define USBHS_EP7_T_EN (1 << 7)
+#define USBHS_EP7_R_EN (1 << 23)
+
+#define USBHS_EP8_T_EN (1 << 8)
+#define USBHS_EP8_R_EN (1 << 24)
+
+#define USBHS_EP9_T_EN (1 << 9)
+#define USBHS_EP9_R_EN (1 << 25)
+
+#define USBHS_EP10_T_EN (1 << 10)
+#define USBHS_EP10_R_EN (1 << 26)
+
+#define USBHS_EP11_T_EN (1 << 11)
+#define USBHS_EP11_R_EN (1 << 27)
+
+#define USBHS_EP12_T_EN (1 << 12)
+#define USBHS_EP12_R_EN (1 << 28)
+
+#define USBHS_EP13_T_EN (1 << 13)
+#define USBHS_EP13_R_EN (1 << 29)
+
+#define USBHS_EP14_T_EN (1 << 14)
+#define USBHS_EP14_R_EN (1 << 30)
+
+#define USBHS_EP15_T_EN (1 << 15)
+#define USBHS_EP15_R_EN (1 << 31)
+
+//UEP_TYPE
+#define USBHS_UEP_TYPE_OFFSET 0x14
+#define USBHS_EP0_T_TYP       (1 << 0)
+#define USBHS_EP0_R_TYP       (1 << 16)
+
+#define USBHS_EP1_T_TYP (1 << 1)
+#define USBHS_EP1_R_TYP (1 << 17)
+
+#define USBHS_EP2_T_TYP (1 << 2)
+#define USBHS_EP2_R_TYP (1 << 18)
+
+#define USBHS_EP3_T_TYP (1 << 3)
+#define USBHS_EP3_R_TYP (1 << 19)
+
+#define USBHS_EP4_T_TYP (1 << 4)
+#define USBHS_EP4_R_TYP (1 << 20)
+
+#define USBHS_EP5_T_TYP (1 << 5)
+#define USBHS_EP5_R_TYP (1 << 21)
+
+#define USBHS_EP6_T_TYP (1 << 6)
+#define USBHS_EP6_R_TYP (1 << 22)
+
+#define USBHS_EP7_T_TYP (1 << 7)
+#define USBHS_EP7_R_TYP (1 << 23)
+
+#define USBHS_EP8_T_TYP (1 << 8)
+#define USBHS_EP8_R_TYP (1 << 24)
+
+#define USBHS_EP9_T_TYP (1 << 8)
+#define USBHS_EP9_R_TYP (1 << 25)
+
+#define USBHS_EP10_T_TYP (1 << 10)
+#define USBHS_EP10_R_TYP (1 << 26)
+
+#define USBHS_EP11_T_TYP (1 << 11)
+#define USBHS_EP11_R_TYP (1 << 27)
+
+#define USBHS_EP12_T_TYP (1 << 12)
+#define USBHS_EP12_R_TYP (1 << 28)
+
+#define USBHS_EP13_T_TYP (1 << 13)
+#define USBHS_EP13_R_TYP (1 << 29)
+
+#define USBHS_EP14_T_TYP (1 << 14)
+#define USBHS_EP14_R_TYP (1 << 30)
+
+#define USBHS_EP15_T_TYP (1 << 15)
+#define USBHS_EP15_R_TYP (1 << 31)
+
+/* BUF_MOD UEP1~15 */
+#define USBHS_BUF_MOD_OFFSET  0x18
+#define USBHS_EP0_BUF_MOD     (1 << 0)
+#define USBHS_EP0_ISO_BUF_MOD (1 << 16)
+
+#define USBHS_EP1_BUF_MOD     (1 << 1)
+#define USBHS_EP1_ISO_BUF_MOD (1 << 17)
+
+#define USBHS_EP2_BUF_MOD     (1 << 2)
+#define USBHS_EP2_ISO_BUF_MOD (1 << 18)
+
+#define USBHS_EP3_BUF_MOD     (1 << 3)
+#define USBHS_EP3_ISO_BUF_MOD (1 << 19)
+
+#define USBHS_EP4_BUF_MOD     (1 << 4)
+#define USBHS_EP4_ISO_BUF_MOD (1 << 20)
+
+#define USBHS_EP5_BUF_MOD     (1 << 5)
+#define USBHS_EP5_ISO_BUF_MOD (1 << 21)
+
+#define USBHS_EP6_BUF_MOD     (1 << 6)
+#define USBHS_EP6_ISO_BUF_MOD (1 << 22)
+
+#define USBHS_EP7_BUF_MOD     (1 << 7)
+#define USBHS_EP7_ISO_BUF_MOD (1 << 23)
+
+#define USBHS_EP8_BUF_MOD     (1 << 8)
+#define USBHS_EP8_ISO_BUF_MOD (1 << 24)
+
+#define USBHS_EP9_BUF_MOD     (1 << 9)
+#define USBHS_EP9_ISO_BUF_MOD (1 << 25)
+
+#define USBHS_EP10_BUF_MOD     (1 << 10)
+#define USBHS_EP10_ISO_BUF_MOD (1 << 26)
+
+#define USBHS_EP11_BUF_MOD     (1 << 11)
+#define USBHS_EP11_ISO_BUF_MOD (1 << 27)
+
+#define USBHS_EP12_BUF_MOD     (1 << 12)
+#define USBHS_EP12_ISO_BUF_MOD (1 << 28)
+
+#define USBHS_EP13_BUF_MOD     (1 << 13)
+#define USBHS_EP13_ISO_BUF_MOD (1 << 29)
+
+#define USBHS_EP14_BUF_MOD     (1 << 14)
+#define USBHS_EP14_ISO_BUF_MOD (1 << 30)
+
+#define USBHS_EP15_BUF_MOD     (1 << 15)
+#define USBHS_EP15_ISO_BUF_MOD (1 << 31)
+//USBHS_EPn_T_EN  USBHS_EPn_R_EN  USBHS_EPn_BUF_MOD  Description: Arrange from low to high with UEPn_DMA as the starting address
+//      0               0               x            The endpoint is disabled and the UEPn_*_DMA buffers are not used.
+//      1               0               0            The first address of the receive (OUT) buffer is UEPn_RX_DMA
+//      1               0               1            RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA
+//      0               1               0            The first address of the transmit (IN) buffer is UEPn_TX_DMA.
+//      0               1               1            RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA
+
+/* USB0_DMA */
+#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address
+
+/* USBX_RX_DMA */
+#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address
+
+#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address
+
+#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address
+
+#define USBHS_UEPx_T_LEN_OFFSET(n)   (0xD8 + 4 * (n)) // endpoint x DMA buffer address
+#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address
+#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address
+
+// UEPn_T_LEN
+#define USBHS_EP_T_LEN_MASK (0x7FF)
+
+//UEPn_TX_CTRL
+#define USBHS_EP_T_RES_MASK  (3 << 0)
+#define USBHS_EP_T_RES_ACK   (0 << 0)
+#define USBHS_EP_T_RES_NYET  (1 << 0)
+#define USBHS_EP_T_RES_NAK   (2 << 0)
+#define USBHS_EP_T_RES_STALL (3 << 0)
+
+#define USBHS_EP_T_TOG_MASK (3 << 3)
+#define USBHS_EP_T_TOG_0    (0 << 3)
+#define USBHS_EP_T_TOG_1    (1 << 3)
+#define USBHS_EP_T_TOG_2    (2 << 3)
+#define USBHS_EP_T_TOG_M    (3 << 3)
+
+#define USBHS_EP_T_AUTOTOG (1 << 5)
+
+//UEPn_RX_CTRL
+#define USBHS_EP_R_RES_MASK  (3 << 0)
+#define USBHS_EP_R_RES_ACK   (0 << 0)
+#define USBHS_EP_R_RES_NYET  (1 << 0)
+#define USBHS_EP_R_RES_NAK   (2 << 0)
+#define USBHS_EP_R_RES_STALL (3 << 0)
+
+#define USBHS_EP_R_TOG_MASK (3 << 3)
+#define USBHS_EP_R_TOG_0    (0 << 3)
+#define USBHS_EP_R_TOG_1    (1 << 3)
+#define USBHS_EP_R_TOG_2    (2 << 3)
+#define USBHS_EP_R_TOG_M    (3 << 3)
+
+#define USBHS_EP_R_AUTOTOG (1 << 5)
+
+#define USBHS_TOG_MATCH (1 << 6)
+
+/******************* HOST ******************/
+// USB HOST_CTRL
+#define USBHS_SEND_BUS_RESET   (1 << 0)
+#define USBHS_SEND_BUS_SUSPEND (1 << 1)
+#define USBHS_SEND_BUS_RESUME  (1 << 2)
+#define USBHS_REMOTE_WAKE      (1 << 3)
+#define USBHS_PHY_SUSPENDM     (1 << 4)
+#define USBHS_UH_SOFT_FREE     (1 << 6)
+#define USBHS_SEND_SOF_EN      (1 << 7)
+
+//UH_CONFIG
+#define USBHS_HOST_TX_EN (1 << 3)
+#define USBHS_HOST_RX_EN (1 << 18)
+
+// HOST_EP_TYPE
+#define USBHS_ENDP_TX_ISO (1 << 3)
+#define USBHS_ENDP_RX_ISO (1 << (16 + 2))
+
+// R32_UH_EP_PID
+#define USBHS_HOST_MASK_TOKEN (0x0f)
+#define USBHS_HOST_MASK_ENDP  (0x0f << 4)
+
+//R8_UH_RX_CTRL
+#define USBHS_EP_R_RES_MASK  (3 << 0)
+#define USBHS_EP_R_RES_ACK   (0 << 0)
+#define USBHS_EP_R_RES_NYET  (1 << 0)
+#define USBHS_EP_R_RES_NAK   (2 << 0)
+#define USBHS_EP_R_RES_STALL (3 << 0)
+
+#define USBHS_UH_R_RES_NO   (1 << 2)
+#define USBHS_UH_R_TOG_1    (1 << 3)
+#define USBHS_UH_R_TOG_2    (2 << 3)
+#define USBHS_UH_R_TOG_3    (3 << 3)
+#define USBHS_UH_R_TOG_AUTO (1 << 5)
+#define USBHS_UH_R_DATA_NO  (1 << 6)
+//R8_UH_TX_CTRL
+#define USBHS_UH_T_RES_MASK  (3 << 0)
+#define USBHS_UH_T_RES_ACK   (0 << 0)
+#define USBHS_UH_T_RES_NYET  (1 << 0)
+#define USBHS_UH_T_RES_NAK   (2 << 0)
+#define USBHS_UH_T_RES_STALL (3 << 0)
+
+#define USBHS_UH_T_RES_NO   (1 << 2)
+#define USBHS_UH_T_TOG_1    (1 << 3)
+#define USBHS_UH_T_TOG_2    (2 << 3)
+#define USBHS_UH_T_TOG_3    (3 << 3)
+#define USBHS_UH_T_TOG_AUTO (1 << 5)
+#define USBHS_UH_T_DATA_NO  (1 << 6)
+
+
+#endif
diff --git a/src/portable/wch/dcd_ch32_usbfs.c b/src/portable/wch/dcd_ch32_usbfs.c
new file mode 100644
index 000000000..c248ba14e
--- /dev/null
+++ b/src/portable/wch/dcd_ch32_usbfs.c
@@ -0,0 +1,348 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Matthew Tran
+ * Copyright (c) 2024 hathach
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_WCH_USBFS) && CFG_TUD_WCH_USBIP_USBFS
+
+#include "device/dcd.h"
+#include "ch32_usbfs_reg.h"
+
+/* private defines */
+#define EP_MAX (8)
+
+#define EP_DMA(ep)     ((&USBOTG_FS->UEP0_DMA)[ep])
+#define EP_TX_LEN(ep)  ((&USBOTG_FS->UEP0_TX_LEN)[2 * ep])
+#define EP_TX_CTRL(ep) ((&USBOTG_FS->UEP0_TX_CTRL)[4 * ep])
+#define EP_RX_CTRL(ep) ((&USBOTG_FS->UEP0_RX_CTRL)[4 * ep])
+
+/* private data */
+struct usb_xfer {
+  bool valid;
+  uint8_t* buffer;
+  size_t len;
+  size_t processed_len;
+  size_t max_size;
+};
+
+static struct {
+  bool ep0_tog;
+  bool isochronous[EP_MAX];
+  struct usb_xfer xfer[EP_MAX][2];
+  TU_ATTR_ALIGNED(4) uint8_t buffer[EP_MAX][2][64];
+  TU_ATTR_ALIGNED(4) struct {
+    // OUT transfers >64 bytes will overwrite queued IN data!
+    uint8_t out[64];
+    uint8_t in[1023];
+    uint8_t pad;
+  } ep3_buffer;
+} data;
+
+/* private helpers */
+static void update_in(uint8_t rhport, uint8_t ep, bool force) {
+  struct usb_xfer* xfer = &data.xfer[ep][TUSB_DIR_IN];
+  if (xfer->valid) {
+    if (force || xfer->len) {
+      size_t len = TU_MIN(xfer->max_size, xfer->len);
+      if (ep == 0) {
+        memcpy(data.buffer[ep][TUSB_DIR_OUT], xfer->buffer, len); // ep0 uses same chunk
+      } else if (ep == 3) {
+        memcpy(data.ep3_buffer.in, xfer->buffer, len);
+      } else {
+        memcpy(data.buffer[ep][TUSB_DIR_IN], xfer->buffer, len);
+      }
+      xfer->buffer += len;
+      xfer->len -= len;
+      xfer->processed_len += len;
+
+      EP_TX_LEN(ep) = len;
+      if (ep == 0) {
+        EP_TX_CTRL(0) = USBFS_EP_T_RES_ACK | (data.ep0_tog ? USBFS_EP_T_TOG : 0);
+        data.ep0_tog = !data.ep0_tog;
+      } else if (data.isochronous[ep]) {
+        EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~(USBFS_EP_T_RES_MASK)) | USBFS_EP_T_RES_NYET;
+      } else {
+        EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~(USBFS_EP_T_RES_MASK)) | USBFS_EP_T_RES_ACK;
+      }
+    } else {
+      xfer->valid = false;
+      EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~(USBFS_EP_T_RES_MASK)) | USBFS_EP_T_RES_NAK;
+      dcd_event_xfer_complete(
+          rhport, ep | TUSB_DIR_IN_MASK, xfer->processed_len,
+          XFER_RESULT_SUCCESS, true);
+    }
+  }
+}
+
+static void update_out(uint8_t rhport, uint8_t ep, size_t rx_len) {
+  struct usb_xfer* xfer = &data.xfer[ep][TUSB_DIR_OUT];
+  if (xfer->valid) {
+    size_t len = TU_MIN(xfer->max_size, TU_MIN(xfer->len, rx_len));
+    if (ep == 3) {
+      memcpy(xfer->buffer, data.ep3_buffer.out, len);
+    } else {
+      memcpy(xfer->buffer, data.buffer[ep][TUSB_DIR_OUT], len);
+    }
+    xfer->buffer += len;
+    xfer->len -= len;
+    xfer->processed_len += len;
+
+    if (xfer->len == 0 || len < xfer->max_size) {
+      xfer->valid = false;
+      dcd_event_xfer_complete(rhport, ep, xfer->processed_len, XFER_RESULT_SUCCESS, true);
+    }
+
+    if (ep == 0) {
+      EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+    }
+  }
+}
+
+/* public functions */
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rh_init;
+  // init registers
+  USBOTG_FS->BASE_CTRL = USBFS_CTRL_SYS_CTRL | USBFS_CTRL_INT_BUSY | USBFS_CTRL_DMA_EN;
+  USBOTG_FS->UDEV_CTRL = USBFS_UDEV_CTRL_PD_DIS | USBFS_UDEV_CTRL_PORT_EN;
+  USBOTG_FS->DEV_ADDR = 0x00;
+
+  USBOTG_FS->INT_FG = 0xFF;
+  USBOTG_FS->INT_EN = USBFS_INT_EN_BUS_RST | USBFS_INT_EN_TRANSFER | USBFS_INT_EN_SUSPEND;
+
+  // setup endpoint 0
+  EP_DMA(0) = (uint32_t) &data.buffer[0][0];
+  EP_TX_LEN(0) = 0;
+  EP_TX_CTRL(0) = USBFS_EP_T_RES_NAK;
+  EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+
+  // enable other endpoints but NAK everything
+  USBOTG_FS->UEP4_1_MOD = 0xCC;
+  USBOTG_FS->UEP2_3_MOD = 0xCC;
+  USBOTG_FS->UEP5_6_MOD = 0xCC;
+  USBOTG_FS->UEP7_MOD = 0x0C;
+
+  for (uint8_t ep = 1; ep < EP_MAX; ep++) {
+    EP_DMA(ep) = (uint32_t) &data.buffer[ep][0];
+    EP_TX_LEN(ep) = 0;
+    EP_TX_CTRL(ep) = USBFS_EP_T_AUTO_TOG | USBFS_EP_T_RES_NAK;
+    EP_RX_CTRL(ep) = USBFS_EP_R_AUTO_TOG | USBFS_EP_R_RES_NAK;
+  }
+  EP_DMA(3) = (uint32_t) &data.ep3_buffer.out[0];
+
+  dcd_connect(rhport);
+
+  return true;
+}
+
+void dcd_int_handler(uint8_t rhport) {
+  (void) rhport;
+  uint8_t status = USBOTG_FS->INT_FG;
+  if (status & USBFS_INT_FG_TRANSFER) {
+    uint8_t ep = USBFS_INT_ST_MASK_UIS_ENDP(USBOTG_FS->INT_ST);
+    uint8_t token = USBFS_INT_ST_MASK_UIS_TOKEN(USBOTG_FS->INT_ST);
+
+    switch (token) {
+      case PID_OUT: {
+        uint16_t rx_len = USBOTG_FS->RX_LEN;
+        update_out(rhport, ep, rx_len);
+        break;
+      }
+
+      case PID_IN:
+        update_in(rhport, ep, false);
+        break;
+
+      case PID_SETUP:
+        // setup clears stall
+        EP_TX_CTRL(0) = USBFS_EP_T_RES_NAK;
+        EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+
+        data.ep0_tog = true;
+        dcd_event_setup_received(rhport, &data.buffer[0][TUSB_DIR_OUT][0], true);
+        break;
+    }
+
+    USBOTG_FS->INT_FG = USBFS_INT_FG_TRANSFER;
+  } else if (status & USBFS_INT_FG_BUS_RST) {
+    data.ep0_tog = true;
+    data.xfer[0][TUSB_DIR_OUT].max_size = 64;
+    data.xfer[0][TUSB_DIR_IN].max_size = 64;
+
+    //dcd_event_bus_reset(rhport, (USBOTG_FS->BASE_CTRL & USBFS_CTRL_LOW_SPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL, true);
+    dcd_event_bus_reset(rhport, (USBOTG_FS->UDEV_CTRL & USBFS_UDEV_CTRL_LOW_SPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL, true);
+
+    USBOTG_FS->DEV_ADDR = 0x00;
+    EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+
+    USBOTG_FS->INT_FG = USBFS_INT_FG_BUS_RST;
+  } else if (status & USBFS_INT_FG_SUSPEND) {
+    dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_SUSPEND};
+    dcd_event_handler(&event, true);
+    USBOTG_FS->INT_FG = USBFS_INT_FG_SUSPEND;
+  }
+}
+
+void dcd_int_enable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_EnableIRQ(USBHD_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_DisableIRQ(USBHD_IRQn);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  (void) dev_addr;
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0); // zlp status response
+}
+
+void dcd_remote_wakeup(uint8_t rhport) {
+  (void) rhport;
+  // TODO optional
+}
+
+void dcd_connect(uint8_t rhport) {
+  (void) rhport;
+  USBOTG_FS->BASE_CTRL |= USBFS_CTRL_DEV_PUEN;
+}
+
+void dcd_disconnect(uint8_t rhport) {
+  (void) rhport;
+  USBOTG_FS->BASE_CTRL &= ~USBFS_CTRL_DEV_PUEN;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en) {
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) {
+  (void) rhport;
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS) {
+    USBOTG_FS->DEV_ADDR = (uint8_t) request->wValue;
+  }
+  EP_TX_CTRL(0) = USBFS_EP_T_RES_NAK;
+  EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) {
+  (void) rhport;
+  uint8_t ep = tu_edpt_number(desc_ep->bEndpointAddress);
+  uint8_t dir = tu_edpt_dir(desc_ep->bEndpointAddress);
+  TU_ASSERT(ep < EP_MAX);
+
+  data.isochronous[ep] = desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS;
+  data.xfer[ep][dir].max_size = tu_edpt_packet_size(desc_ep);
+
+  if (ep != 0) {
+    if (dir == TUSB_DIR_OUT) {
+      if (data.isochronous[ep]) {
+        EP_RX_CTRL(ep) = USBFS_EP_R_AUTO_TOG | USBFS_EP_R_RES_NYET;
+      } else {
+        EP_RX_CTRL(ep) = USBFS_EP_R_AUTO_TOG | USBFS_EP_R_RES_ACK;
+      }
+    } else {
+      EP_TX_LEN(ep) = 0;
+      EP_TX_CTRL(ep) = USBFS_EP_T_AUTO_TOG | USBFS_EP_T_RES_NAK;
+    }
+  }
+  return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport) {
+  (void) rhport;
+  // TODO optional
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport;
+  (void) ep_addr;
+  // TODO optional
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+  (void) rhport;
+  uint8_t ep = tu_edpt_number(ep_addr);
+  uint8_t dir = tu_edpt_dir(ep_addr);
+
+  struct usb_xfer* xfer = &data.xfer[ep][dir];
+  dcd_int_disable(rhport);
+  xfer->valid = true;
+  xfer->buffer = buffer;
+  xfer->len = total_bytes;
+  xfer->processed_len = 0;
+  dcd_int_enable(rhport);
+
+  if (dir == TUSB_DIR_IN) {
+    update_in(rhport, ep, true);
+  }
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport;
+  uint8_t ep = tu_edpt_number(ep_addr);
+  uint8_t dir = tu_edpt_dir(ep_addr);
+  if (ep == 0) {
+    if (dir == TUSB_DIR_OUT) {
+      EP_RX_CTRL(0) = USBFS_EP_R_RES_STALL;
+    } else {
+      EP_TX_LEN(0) = 0;
+      EP_TX_CTRL(0) = USBFS_EP_T_RES_STALL;
+    }
+  } else {
+    if (dir == TUSB_DIR_OUT) {
+      EP_RX_CTRL(ep) = (EP_RX_CTRL(ep) & ~USBFS_EP_R_RES_MASK) | USBFS_EP_R_RES_STALL;
+    } else {
+      EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~USBFS_EP_T_RES_MASK) | USBFS_EP_T_RES_STALL;
+    }
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport;
+  uint8_t ep = tu_edpt_number(ep_addr);
+  uint8_t dir = tu_edpt_dir(ep_addr);
+  if (ep == 0) {
+    if (dir == TUSB_DIR_OUT) {
+      EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+    }
+  } else {
+    if (dir == TUSB_DIR_OUT) {
+      EP_RX_CTRL(ep) = (EP_RX_CTRL(ep) & ~(USBFS_EP_R_RES_MASK | USBFS_EP_R_TOG)) | USBFS_EP_R_RES_ACK;
+    } else {
+      EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~(USBFS_EP_T_RES_MASK | USBFS_EP_T_TOG)) | USBFS_EP_T_RES_NAK;
+    }
+  }
+}
+
+#endif
diff --git a/src/portable/wch/dcd_ch32_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c
new file mode 100644
index 000000000..f8bf3c889
--- /dev/null
+++ b/src/portable/wch/dcd_ch32_usbhs.c
@@ -0,0 +1,423 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ * Copyright (c) 2023 Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_WCH_USBHS) && CFG_TUD_WCH_USBIP_USBHS
+#include "ch32_usbhs_reg.h"
+
+#include "device/dcd.h"
+
+// Max number of bi-directional endpoints including EP0
+#define EP_MAX  16
+
+typedef struct {
+  uint8_t* buffer;
+  uint16_t total_len;
+  uint16_t queued_len;
+  uint16_t max_size;
+  bool is_last_packet;
+  bool is_iso;
+} xfer_ctl_t;
+
+typedef enum {
+  EP_RESPONSE_ACK,
+  EP_RESPONSE_NAK,
+} ep_response_list_t;
+
+#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
+static xfer_ctl_t xfer_status[EP_MAX][2];
+
+#define EP_TX_LEN(ep)     *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep) * 2)
+#define EP_TX_CTRL(ep)    *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep) * 4)
+#define EP_RX_CTRL(ep)    *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep) * 4)
+#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep) * 2)
+
+#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1))
+#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1))
+
+/* Endpoint Buffer */
+TU_ATTR_ALIGNED(4) static uint8_t ep0_buffer[CFG_TUD_ENDPOINT0_SIZE];
+
+static void ep_set_response_and_toggle(uint8_t ep_num, tusb_dir_t ep_dir, ep_response_list_t response_type) {
+  if (ep_dir == TUSB_DIR_IN) {
+    uint8_t response = (response_type == EP_RESPONSE_ACK) ? USBHS_EP_T_RES_ACK : USBHS_EP_T_RES_NAK;
+    if (ep_num == 0) {
+      if (response_type == EP_RESPONSE_ACK) {
+        if (EP_TX_LEN(ep_num) == 0) {
+          EP_TX_CTRL(ep_num) |= USBHS_EP_T_TOG_1;
+        } else {
+          EP_TX_CTRL(ep_num) ^= USBHS_EP_T_TOG_1;
+        }
+      }
+    }
+    if (xfer_status[ep_num][TUSB_DIR_IN].is_iso == true) {
+      EP_TX_CTRL(ep_num) = USBHS_EP_T_AUTOTOG;
+    } else {
+      EP_TX_CTRL(ep_num) = (EP_TX_CTRL(ep_num) & ~(USBHS_EP_T_RES_MASK)) | response;
+    }
+  } else {
+    uint8_t response = (response_type == EP_RESPONSE_ACK) ? USBHS_EP_R_RES_ACK : USBHS_EP_R_RES_NAK;
+    if (ep_num == 0) {
+      if (response_type == EP_RESPONSE_ACK) {
+        if (xfer_status[ep_num][TUSB_DIR_OUT].queued_len == 0) {
+          EP_RX_CTRL(ep_num) |= USBHS_EP_R_TOG_1;
+        }
+      } else {
+        EP_RX_CTRL(ep_num) ^= USBHS_EP_R_TOG_1;
+      }
+    }
+    EP_RX_CTRL(ep_num) = (EP_RX_CTRL(ep_num) & ~(USBHS_EP_R_RES_MASK)) | response;
+  }
+}
+
+static void xfer_data_packet(uint8_t ep_num, tusb_dir_t ep_dir, xfer_ctl_t* xfer) {
+  if (ep_dir == TUSB_DIR_IN) {
+    uint16_t remaining = xfer->total_len - xfer->queued_len;
+    uint16_t next_tx_size = TU_MIN(remaining, xfer->max_size);
+
+    if (ep_num == 0) {
+      memcpy(ep0_buffer, &xfer->buffer[xfer->queued_len], next_tx_size);
+    } else {
+      EP_TX_DMA_ADDR(ep_num) = (uint32_t) &xfer->buffer[xfer->queued_len];
+    }
+
+    EP_TX_LEN(ep_num) = next_tx_size;
+    xfer->queued_len += next_tx_size;
+    if (xfer->queued_len == xfer->total_len) {
+      xfer->is_last_packet = true;
+    }
+    if (xfer->is_iso == true) {
+      /* Enable EP to generate ISA_ACT interrupt */
+      USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << ep_num);
+    }
+  } else { /* TUSB_DIR_OUT */
+    uint16_t left_to_receive = xfer->total_len - xfer->queued_len;
+    uint16_t max_possible_rx_size = TU_MIN(xfer->max_size, left_to_receive);
+
+    if (max_possible_rx_size == left_to_receive) {
+      xfer->is_last_packet = true;
+    }
+
+    if (ep_num > 0) {
+      EP_RX_DMA_ADDR(ep_num) = (uint32_t) &xfer->buffer[xfer->queued_len];
+      EP_RX_MAX_LEN(ep_num) = max_possible_rx_size;
+    }
+  }
+  ep_set_response_and_toggle(ep_num, ep_dir, USBHS_EP_R_RES_ACK);
+}
+
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  (void) rhport;
+  (void) rh_init;
+
+  memset(&xfer_status, 0, sizeof(xfer_status));
+
+  USBHSD->HOST_CTRL = 0x00;
+  USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM;
+
+  USBHSD->CONTROL = 0;
+
+#if TUD_OPT_HIGH_SPEED
+  USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
+#else
+  #error OPT_MODE_FULL_SPEED not currently supported on CH32
+  USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
+#endif
+
+  USBHSD->INT_EN = 0;
+  USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_BUS_RST_EN | USBHS_SUSPEND_EN | USBHS_ISO_ACT_EN;
+
+  USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
+  USBHSD->ENDP_TYPE = 0x00;
+  USBHSD->BUF_MODE = 0x00;
+
+  for (int ep = 0; ep < EP_MAX; ep++) {
+    EP_TX_LEN(ep) = 0;
+    EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
+    EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+
+    EP_RX_MAX_LEN(ep) = 0;
+  }
+
+  USBHSD->UEP0_DMA = (uint32_t) ep0_buffer;
+  USBHSD->UEP0_MAX_LEN = CFG_TUD_ENDPOINT0_SIZE;
+  xfer_status[0][TUSB_DIR_OUT].max_size = CFG_TUD_ENDPOINT0_SIZE;
+  xfer_status[0][TUSB_DIR_IN].max_size = CFG_TUD_ENDPOINT0_SIZE;
+
+  USBHSD->DEV_AD = 0;
+  USBHSD->CONTROL |= USBHS_DEV_PU_EN;
+
+  return true;
+}
+
+void dcd_int_enable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_EnableIRQ(USBHS_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_DisableIRQ(USBHS_IRQn);
+}
+
+void dcd_edpt_close_all(uint8_t rhport) {
+  (void) rhport;
+
+  for (size_t ep = 1; ep < EP_MAX; ep++) {
+    EP_TX_LEN(ep) = 0;
+    EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
+    EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+
+    EP_RX_MAX_LEN(ep) = 0;
+  }
+
+  USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  (void) dev_addr;
+
+  // Response with zlp status
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0);
+}
+
+void dcd_remote_wakeup(uint8_t rhport) {
+  (void) rhport;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en) {
+  (void) rhport;
+  if (en) {
+    USBHSD->INT_EN |= USBHS_SOF_ACT_EN;
+  } else {
+    USBHSD->INT_EN &= ~(USBHS_SOF_ACT_EN);
+  }
+}
+
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) {
+  (void) rhport;
+
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS) {
+    USBHSD->DEV_AD = (uint8_t) request->wValue;
+  }
+
+  EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
+  EP_RX_CTRL(0) = USBHS_EP_R_RES_NAK | USBHS_EP_R_TOG_0;
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
+  (void) rhport;
+
+  uint8_t const ep_num = tu_edpt_number(desc_edpt->bEndpointAddress);
+  tusb_dir_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
+
+  TU_ASSERT(ep_num < EP_MAX);
+
+  if (ep_num == 0) {
+    return true;
+  }
+
+  xfer_ctl_t* xfer = XFER_CTL_BASE(ep_num, dir);
+  xfer->max_size = tu_edpt_packet_size(desc_edpt);
+
+  xfer->is_iso = (desc_edpt->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+  if (dir == TUSB_DIR_OUT) {
+    USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << ep_num);
+    EP_RX_CTRL(ep_num) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+    if (xfer->is_iso == true) {
+      USBHSD->ENDP_TYPE |= (USBHS_EP0_R_TYP << ep_num);
+    }
+    EP_RX_MAX_LEN(ep_num) = xfer->max_size;
+  } else {
+    if (xfer->is_iso == true) {
+      USBHSD->ENDP_TYPE |= (USBHS_EP0_T_TYP << ep_num);
+    } else {
+      /* Enable all types except Isochronous to avoid ISO_ACT interrupt generation */
+      USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << ep_num);
+    }
+    EP_TX_LEN(ep_num) = 0;
+    EP_TX_CTRL(ep_num) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
+  }
+
+  return true;
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport;
+
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+
+  if (dir == TUSB_DIR_OUT) {
+    EP_RX_CTRL(ep_num) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+    EP_RX_MAX_LEN(ep_num) = 0;
+    USBHSD->ENDP_TYPE &= ~(USBHS_EP0_R_TYP << ep_num);
+    USBHSD->ENDP_CONFIG &= ~(USBHS_EP0_R_EN << ep_num);
+  } else {  // TUSB_DIR_IN
+    EP_TX_CTRL(ep_num) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
+    EP_TX_LEN(ep_num) = 0;
+    USBHSD->ENDP_TYPE &= ~(USBHS_EP0_T_TYP << ep_num);
+    USBHSD->ENDP_CONFIG &= ~(USBHS_EP0_T_EN << ep_num);
+  }
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport;
+
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+
+  if (dir == TUSB_DIR_OUT) {
+    EP_RX_CTRL(ep_num) = USBHS_EP_R_RES_STALL;
+  } else {
+    EP_TX_LEN(0) = 0;
+    EP_TX_CTRL(ep_num) = USBHS_EP_T_RES_STALL;
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport;
+
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+
+  if (dir == TUSB_DIR_OUT) {
+    EP_RX_CTRL(ep_num) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+  } else {
+    EP_TX_CTRL(ep_num) = USBHS_EP_T_AUTOTOG | USBHS_EP_R_RES_NAK;
+  }
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+  (void) rhport;
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+
+  xfer_ctl_t* xfer = XFER_CTL_BASE(ep_num, dir);
+  xfer->buffer = buffer;
+  xfer->total_len = total_bytes;
+  xfer->queued_len = 0;
+  xfer->is_last_packet = false;
+
+  xfer_data_packet(ep_num, dir, xfer);
+
+  return true;
+}
+
+void dcd_int_handler(uint8_t rhport) {
+  (void) rhport;
+
+  uint8_t int_flag = USBHSD->INT_FG;
+  uint8_t int_status = USBHSD->INT_ST;
+
+  if (int_flag & (USBHS_ISO_ACT_FLAG | USBHS_TRANSFER_FLAG)) {
+    uint8_t const token = int_status & MASK_UIS_TOKEN;
+
+    if (token == USBHS_TOKEN_PID_SOF) {
+      uint32_t frame_count = USBHSD->FRAME_NO & USBHS_FRAME_NO_NUM_MASK;
+      dcd_event_sof(rhport, frame_count, true);
+    }else {
+      uint8_t const ep_num = int_status & MASK_UIS_ENDP;
+      tusb_dir_t const ep_dir = (token == USBHS_TOKEN_PID_IN) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+      uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir);
+      xfer_ctl_t* xfer = XFER_CTL_BASE(ep_num, ep_dir);
+
+      if (token == USBHS_TOKEN_PID_OUT) {
+        uint16_t rx_len = USBHSD->RX_LEN;
+
+        if (ep_num == 0) {
+          memcpy(&xfer->buffer[xfer->queued_len], ep0_buffer, rx_len);
+        }
+
+        xfer->queued_len += rx_len;
+        if (rx_len < xfer->max_size) {
+          xfer->is_last_packet = true;
+        }
+      } else if (token == USBHS_TOKEN_PID_IN) {
+        if (xfer->is_iso && xfer->is_last_packet) {
+          /* Disable EP to avoid ISO_ACT interrupt generation */
+          USBHSD->ENDP_CONFIG &= ~(USBHS_EP0_T_EN << ep_num);
+        } else {
+          // Do nothing, no need to update xfer->is_last_packet, it is already updated in xfer_data_packet
+        }
+      }
+
+      if (xfer->is_last_packet == true) {
+        ep_set_response_and_toggle(ep_num, ep_dir, EP_RESPONSE_NAK);
+        dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+      } else {
+        /* prepare next part of packet to xref */
+        xfer_data_packet(ep_num, ep_dir, xfer);
+      }
+    }
+
+    USBHSD->INT_FG = (int_flag & (USBHS_ISO_ACT_FLAG | USBHS_TRANSFER_FLAG)); /* Clear flag */
+  } else if (int_flag & USBHS_SETUP_FLAG) {
+    ep_set_response_and_toggle(0, TUSB_DIR_IN, EP_RESPONSE_NAK);
+    ep_set_response_and_toggle(0, TUSB_DIR_OUT, EP_RESPONSE_NAK);
+    dcd_event_setup_received(0, ep0_buffer, true);
+
+    USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
+  } else if (int_flag & USBHS_BUS_RST_FLAG) {
+    // TODO CH32 does not detect actual speed at this time (should be known at end of reset)
+    // This interrupt probably triggered at start of bus reset
+//    tusb_speed_t actual_speed;
+//    switch(USBHSD->SPEED_TYPE & USBHS_SPEED_TYPE_MASK){
+//      case USBHS_SPEED_TYPE_HIGH:
+//        actual_speed = TUSB_SPEED_HIGH;
+//        break;
+//      case USBHS_SPEED_TYPE_FULL:
+//        actual_speed = TUSB_SPEED_FULL;
+//        break;
+//      case USBHS_SPEED_TYPE_LOW:
+//        actual_speed = TUSB_SPEED_LOW;
+//        break;
+//      default:
+//        TU_ASSERT(0,);
+//        break;
+//    }
+//    dcd_event_bus_reset(0, actual_speed, true);
+
+    dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true);
+
+    USBHSD->DEV_AD = 0;
+    EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
+    EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
+
+    USBHSD->INT_FG = USBHS_BUS_RST_FLAG; /* Clear flag */
+  } else if (int_flag & USBHS_SUSPEND_FLAG) {
+    dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_SUSPEND};
+    dcd_event_handler(&event, true);
+
+    USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */
+  }
+}
+
+#endif
diff --git a/src/tinyusb.mk b/src/tinyusb.mk
new file mode 100644
index 000000000..89ea0212c
--- /dev/null
+++ b/src/tinyusb.mk
@@ -0,0 +1,26 @@
+# C source files
+TINYUSB_SRC_C += \
+	src/tusb.c \
+	src/common/tusb_fifo.c \
+	src/device/usbd.c \
+	src/device/usbd_control.c \
+	src/typec/usbc.c \
+	src/class/audio/audio_device.c \
+	src/class/cdc/cdc_device.c \
+	src/class/dfu/dfu_device.c \
+	src/class/dfu/dfu_rt_device.c \
+	src/class/hid/hid_device.c \
+	src/class/midi/midi_device.c \
+	src/class/msc/msc_device.c \
+	src/class/net/ecm_rndis_device.c \
+	src/class/net/ncm_device.c \
+	src/class/usbtmc/usbtmc_device.c \
+	src/class/video/video_device.c \
+	src/class/vendor/vendor_device.c \
+  src/host/usbh.c \
+  src/host/hub.c \
+  src/class/cdc/cdc_host.c \
+  src/class/hid/hid_host.c \
+  src/class/msc/msc_host.c \
+  src/class/vendor/vendor_host.c \
+  src/typec/usbc.c \
diff --git a/src/tusb.c b/src/tusb.c
index c3787ff8f..85ab1d6ae 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -31,168 +31,243 @@
 #include "tusb.h"
 #include "common/tusb_private.h"
 
-// TODO clean up
 #if CFG_TUD_ENABLED
 #include "device/usbd_pvt.h"
 #endif
 
-bool tusb_init(void)
-{
-#if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT)
-  // init device stack CFG_TUSB_RHPORTx_MODE must be defined
-  TU_ASSERT ( tud_init(TUD_OPT_RHPORT) );
+#if CFG_TUH_ENABLED
+#include "host/usbh_pvt.h"
 #endif
 
-#if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT)
-  // init host stack CFG_TUSB_RHPORTx_MODE must be defined
-  TU_ASSERT( tuh_init(TUH_OPT_RHPORT) );
+tusb_role_t _tusb_rhport_role[TUP_USBIP_CONTROLLER_NUM] = { TUSB_ROLE_INVALID };
+
+//--------------------------------------------------------------------
+// Weak/Default API, can be overwritten by Application
+//--------------------------------------------------------------------
+
+TU_ATTR_WEAK void tusb_time_delay_ms_api(uint32_t ms) {
+#if CFG_TUSB_OS != OPT_OS_NONE
+  osal_task_delay(ms);
+#else
+  // delay using millis() (if implemented) and/or frame number if possible
+  const uint32_t time_ms = tusb_time_millis_api();
+  while ((tusb_time_millis_api() - time_ms) < ms) {}
 #endif
+}
+
+//--------------------------------------------------------------------+
+// Public API
+//--------------------------------------------------------------------+
+bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  //  backward compatible called with tusb_init(void)
+  #if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT)
+  if (rh_init == NULL) {
+    #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT)
+    // init device stack CFG_TUSB_RHPORTx_MODE must be defined
+    const tusb_rhport_init_t dev_init = {
+      .role = TUSB_ROLE_DEVICE,
+      .speed = TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL
+    };
+    TU_ASSERT ( tud_rhport_init(TUD_OPT_RHPORT, &dev_init) );
+    _tusb_rhport_role[TUD_OPT_RHPORT] = TUSB_ROLE_DEVICE;
+    #endif
+
+    #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT)
+    // init host stack CFG_TUSB_RHPORTx_MODE must be defined
+    const tusb_rhport_init_t host_init = {
+      .role = TUSB_ROLE_HOST,
+      .speed = TUH_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL
+    };
+    TU_ASSERT( tuh_rhport_init(TUH_OPT_RHPORT, &host_init) );
+    _tusb_rhport_role[TUH_OPT_RHPORT] = TUSB_ROLE_HOST;
+    #endif
+
+    return true;
+  }
+  #endif
+
+  // new API with explicit rhport and role
+  TU_ASSERT(rhport < TUP_USBIP_CONTROLLER_NUM && rh_init->role != TUSB_ROLE_INVALID);
+  _tusb_rhport_role[rhport] = rh_init->role;
+
+  #if CFG_TUD_ENABLED
+  if (rh_init->role == TUSB_ROLE_DEVICE) {
+    TU_ASSERT(tud_rhport_init(rhport, rh_init));
+  }
+  #endif
+
+  #if CFG_TUH_ENABLED
+  if (rh_init->role == TUSB_ROLE_HOST) {
+    TU_ASSERT(tuh_rhport_init(rhport, rh_init));
+  }
+  #endif
 
   return true;
 }
 
-bool tusb_inited(void)
-{
+bool tusb_inited(void) {
   bool ret = false;
 
-#if CFG_TUD_ENABLED
+  #if CFG_TUD_ENABLED
   ret = ret || tud_inited();
-#endif
+  #endif
 
-#if CFG_TUH_ENABLED
+  #if CFG_TUH_ENABLED
   ret = ret || tuh_inited();
-#endif
+  #endif
 
   return ret;
 }
 
+void tusb_int_handler(uint8_t rhport, bool in_isr) {
+  TU_VERIFY(rhport < TUP_USBIP_CONTROLLER_NUM,);
+
+  #if CFG_TUD_ENABLED
+  if (_tusb_rhport_role[rhport] == TUSB_ROLE_DEVICE) {
+    (void) in_isr;
+    dcd_int_handler(rhport);
+  }
+  #endif
+
+  #if CFG_TUH_ENABLED
+  if (_tusb_rhport_role[rhport] == TUSB_ROLE_HOST) {
+    hcd_int_handler(rhport, in_isr);
+  }
+  #endif
+}
+
 //--------------------------------------------------------------------+
-// Internal Helper for both Host and Device stack
+// Descriptor helper
 //--------------------------------------------------------------------+
 
-bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
-{
+uint8_t const* tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1) {
+  while (desc + 1 < end) {
+    if (desc[1] == byte1) return desc;
+    desc += desc[DESC_OFFSET_LEN];
+  }
+  return NULL;
+}
+
+uint8_t const* tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2) {
+  while (desc + 2 < end) {
+    if (desc[1] == byte1 && desc[2] == byte2) return desc;
+    desc += desc[DESC_OFFSET_LEN];
+  }
+  return NULL;
+}
+
+uint8_t const* tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3) {
+  while (desc + 3 < end) {
+    if (desc[1] == byte1 && desc[2] == byte2 && desc[3] == byte3) return desc;
+    desc += desc[DESC_OFFSET_LEN];
+  }
+  return NULL;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint Helper for both Host and Device stack
+//--------------------------------------------------------------------+
+
+bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) {
   (void) mutex;
 
-#if TUSB_OPT_MUTEX
   // pre-check to help reducing mutex lock
   TU_VERIFY((ep_state->busy == 0) && (ep_state->claimed == 0));
-  osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-#endif
+  (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   // can only claim the endpoint if it is not busy and not claimed yet.
   bool const available = (ep_state->busy == 0) && (ep_state->claimed == 0);
-  if (available)
-  {
+  if (available) {
     ep_state->claimed = 1;
   }
 
-#if TUSB_OPT_MUTEX
-  osal_mutex_unlock(mutex);
-#endif
-
+  (void) osal_mutex_unlock(mutex);
   return available;
 }
 
-bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
-{
+bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) {
   (void) mutex;
-
-#if TUSB_OPT_MUTEX
-  osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-#endif
+  (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   // can only release the endpoint if it is claimed and not busy
   bool const ret = (ep_state->claimed == 1) && (ep_state->busy == 0);
-  if (ret)
-  {
+  if (ret) {
     ep_state->claimed = 0;
   }
 
-#if TUSB_OPT_MUTEX
-  osal_mutex_unlock(mutex);
-#endif
-
+  (void) osal_mutex_unlock(mutex);
   return ret;
 }
 
-bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed)
-{
+bool tu_edpt_validate(tusb_desc_endpoint_t const* desc_ep, tusb_speed_t speed) {
   uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep);
   TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size);
 
-  switch (desc_ep->bmAttributes.xfer)
-  {
-    case TUSB_XFER_ISOCHRONOUS:
-    {
+  switch (desc_ep->bmAttributes.xfer) {
+    case TUSB_XFER_ISOCHRONOUS: {
       uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 1023);
       TU_ASSERT(max_packet_size <= spec_size);
+      break;
     }
-    break;
 
     case TUSB_XFER_BULK:
-      if (speed == TUSB_SPEED_HIGH)
-      {
+      if (speed == TUSB_SPEED_HIGH) {
         // Bulk highspeed must be EXACTLY 512
         TU_ASSERT(max_packet_size == 512);
-      }else
-      {
+      } else {
         // TODO Bulk fullspeed can only be 8, 16, 32, 64
         TU_ASSERT(max_packet_size <= 64);
       }
-    break;
+      break;
 
-    case TUSB_XFER_INTERRUPT:
-    {
+    case TUSB_XFER_INTERRUPT: {
       uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64);
       TU_ASSERT(max_packet_size <= spec_size);
+      break;
     }
-    break;
 
-    default: return false;
+    default:
+      return false;
   }
 
   return true;
 }
 
-void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id)
-{
+void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len,
+                         uint8_t driver_id) {
   uint8_t const* p_desc = (uint8_t const*) desc_itf;
   uint8_t const* desc_end = p_desc + desc_len;
 
-  while( p_desc < desc_end )
-  {
-    if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
-    {
+  while (p_desc < desc_end) {
+    if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) {
       uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
-
       TU_LOG(2, "  Bind EP %02x to driver id %u\r\n", ep_addr, driver_id);
       ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id;
     }
-
     p_desc = tu_desc_next(p_desc);
   }
 }
 
-uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len)
-{
+uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) {
   uint8_t const* p_desc = (uint8_t const*) desc_itf;
   uint16_t len = 0;
 
-  while (itf_count--)
-  {
+  while (itf_count--) {
     // Next on interface desc
     len += tu_desc_len(desc_itf);
     p_desc = tu_desc_next(p_desc);
 
-    while (len < max_len)
-    {
+    while (len < max_len) {
+      if (tu_desc_len(p_desc) == 0) {
+        // Escape infinite loop
+        break;
+      }
       // return on IAD regardless of itf count
-      if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len;
-
-      if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
-           ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 )
-      {
+      if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) {
+        return len;
+      }
+      if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
+          ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0) {
         break;
       }
 
@@ -204,45 +279,232 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf,
   return len;
 }
 
-/*------------------------------------------------------------------*/
-/* Debug
- *------------------------------------------------------------------*/
+//--------------------------------------------------------------------+
+// Endpoint Stream Helper for both Host and Device stack
+//--------------------------------------------------------------------+
+
+bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
+                         void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) {
+  (void) is_tx;
+
+  s->is_host = is_host;
+  tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable);
+
+  #if OSAL_MUTEX_REQUIRED
+  if (ff_buf && ff_bufsize) {
+    osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutexdef);
+    tu_fifo_config_mutex(&s->ff, is_tx ? new_mutex : NULL, is_tx ? NULL : new_mutex);
+  }
+  #endif
+
+  s->ep_buf = ep_buf;
+  s->ep_bufsize = ep_bufsize;
+
+  return true;
+}
+
+bool tu_edpt_stream_deinit(tu_edpt_stream_t* s) {
+  (void) s;
+  #if OSAL_MUTEX_REQUIRED
+  if (s->ff.mutex_wr) osal_mutex_delete(s->ff.mutex_wr);
+  if (s->ff.mutex_rd) osal_mutex_delete(s->ff.mutex_rd);
+  #endif
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool stream_claim(uint8_t hwid, tu_edpt_stream_t* s) {
+  if (s->is_host) {
+    #if CFG_TUH_ENABLED
+    return usbh_edpt_claim(hwid, s->ep_addr);
+    #endif
+  } else {
+    #if CFG_TUD_ENABLED
+    return usbd_edpt_claim(hwid, s->ep_addr);
+    #endif
+  }
+  return false;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool stream_xfer(uint8_t hwid, tu_edpt_stream_t* s, uint16_t count) {
+  if (s->is_host) {
+    #if CFG_TUH_ENABLED
+    return usbh_edpt_xfer(hwid, s->ep_addr, count ? s->ep_buf : NULL, count);
+    #endif
+  } else {
+    #if CFG_TUD_ENABLED
+    return usbd_edpt_xfer(hwid, s->ep_addr, count ? s->ep_buf : NULL, count);
+    #endif
+  }
+  return false;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool stream_release(uint8_t hwid, tu_edpt_stream_t* s) {
+  if (s->is_host) {
+    #if CFG_TUH_ENABLED
+    return usbh_edpt_release(hwid, s->ep_addr);
+    #endif
+  } else {
+    #if CFG_TUD_ENABLED
+    return usbd_edpt_release(hwid, s->ep_addr);
+    #endif
+  }
+  return false;
+}
+
+//--------------------------------------------------------------------+
+// Stream Write
+//--------------------------------------------------------------------+
+bool tu_edpt_stream_write_zlp_if_needed(uint8_t hwid, tu_edpt_stream_t* s, uint32_t last_xferred_bytes) {
+  // ZLP condition: no pending data, last transferred bytes is multiple of packet size
+  const uint16_t mps = s->is_mps512 ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+  TU_VERIFY(!tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (mps - 1))));
+  TU_VERIFY(stream_claim(hwid, s));
+  TU_ASSERT(stream_xfer(hwid, s, 0));
+  return true;
+}
+
+uint32_t tu_edpt_stream_write_xfer(uint8_t hwid, tu_edpt_stream_t* s) {
+  // skip if no data
+  TU_VERIFY(tu_fifo_count(&s->ff), 0);
+
+  TU_VERIFY(stream_claim(hwid, s), 0);
+
+  // Pull data from FIFO -> EP buf
+  uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
+
+  if (count) {
+    TU_ASSERT(stream_xfer(hwid, s, count), 0);
+    return count;
+  } else {
+    // Release endpoint since we don't make any transfer
+    // Note: data is dropped if terminal is not connected
+    stream_release(hwid, s);
+    return 0;
+  }
+}
+
+uint32_t tu_edpt_stream_write(uint8_t hwid, tu_edpt_stream_t* s, void const* buffer, uint32_t bufsize) {
+  TU_VERIFY(bufsize); // TODO support ZLP
+
+  if (0 == tu_fifo_depth(&s->ff)) {
+    // no fifo for buffered
+    TU_VERIFY(stream_claim(hwid, s), 0);
+    const uint32_t xact_len = tu_min32(bufsize, s->ep_bufsize);
+    memcpy(s->ep_buf, buffer, xact_len);
+    TU_ASSERT(stream_xfer(hwid, s, (uint16_t) xact_len), 0);
+    return xact_len;
+  } else {
+    const uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
+
+    // flush if fifo has more than packet size or
+    // in rare case: fifo depth is configured too small (which never reach packet size)
+    const uint16_t mps = s->is_mps512 ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+    if ((tu_fifo_count(&s->ff) >= mps) || (tu_fifo_depth(&s->ff) < mps)) {
+      tu_edpt_stream_write_xfer(hwid, s);
+    }
+    return ret;
+  }
+}
+
+uint32_t tu_edpt_stream_write_available(uint8_t hwid, tu_edpt_stream_t* s) {
+  if (tu_fifo_depth(&s->ff)) {
+    return (uint32_t) tu_fifo_remaining(&s->ff);
+  } else {
+    bool is_busy = true;
+    if (s->is_host) {
+      #if CFG_TUH_ENABLED
+      is_busy = usbh_edpt_busy(hwid, s->ep_addr);
+      #endif
+    } else {
+      #if CFG_TUD_ENABLED
+      is_busy = usbd_edpt_busy(hwid, s->ep_addr);
+      #endif
+    }
+    return is_busy ? 0 : s->ep_bufsize;
+  }
+}
+
+//--------------------------------------------------------------------+
+// Stream Read
+//--------------------------------------------------------------------+
+uint32_t tu_edpt_stream_read_xfer(uint8_t hwid, tu_edpt_stream_t* s) {
+  if (0 == tu_fifo_depth(&s->ff)) {
+    // no fifo for buffered
+    TU_VERIFY(stream_claim(hwid, s), 0);
+    TU_ASSERT(stream_xfer(hwid, s, s->ep_bufsize), 0);
+    return s->ep_bufsize;
+  } else {
+    const uint16_t mps = s->is_mps512 ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+    uint16_t available = tu_fifo_remaining(&s->ff);
+
+    // Prepare for incoming data but only allow what we can store in the ring buffer.
+    // TODO Actually we can still carry out the transfer, keeping count of received bytes
+    // and slowly move it to the FIFO when read().
+    // This pre-check reduces endpoint claiming
+    TU_VERIFY(available >= mps);
+
+    TU_VERIFY(stream_claim(hwid, s), 0);
+
+    // get available again since fifo can be changed before endpoint is claimed
+    available = tu_fifo_remaining(&s->ff);
+
+    if (available >= mps) {
+      // multiple of packet size limit by ep bufsize
+      uint16_t count = (uint16_t) (available & ~(mps - 1));
+      count = tu_min16(count, s->ep_bufsize);
+      TU_ASSERT(stream_xfer(hwid, s, count), 0);
+      return count;
+    } else {
+      // Release endpoint since we don't make any transfer
+      stream_release(hwid, s);
+      return 0;
+    }
+  }
+}
+
+uint32_t tu_edpt_stream_read(uint8_t hwid, tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) {
+  uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize);
+  tu_edpt_stream_read_xfer(hwid, s);
+  return num_read;
+}
+
+//--------------------------------------------------------------------+
+// Debug
+//--------------------------------------------------------------------+
+
 #if CFG_TUSB_DEBUG
 #include <ctype.h>
 
-#if CFG_TUSB_DEBUG >= 2
-
-char const* const tu_str_speed[] = { "Full", "Low", "High" };
-char const* const tu_str_std_request[] =
-{
-  "Get Status"        ,
-  "Clear Feature"     ,
-  "Reserved"          ,
-  "Set Feature"       ,
-  "Reserved"          ,
-  "Set Address"       ,
-  "Get Descriptor"    ,
-  "Set Descriptor"    ,
-  "Get Configuration" ,
-  "Set Configuration" ,
-  "Get Interface"     ,
-  "Set Interface"     ,
-  "Synch Frame"
+#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
+char const* const tu_str_speed[] = {"Full", "Low", "High"};
+char const* const tu_str_std_request[] = {
+    "Get Status",
+    "Clear Feature",
+    "Reserved",
+    "Set Feature",
+    "Reserved",
+    "Set Address",
+    "Get Descriptor",
+    "Set Descriptor",
+    "Get Configuration",
+    "Set Configuration",
+    "Get Interface",
+    "Set Interface",
+    "Synch Frame"
 };
 
+char const* const tu_str_xfer_result[] = {
+    "OK", "FAILED", "STALLED", "TIMEOUT"
+};
 #endif
 
-static void dump_str_line(uint8_t const* buf, uint16_t count)
-{
+static void dump_str_line(uint8_t const* buf, uint16_t count) {
   tu_printf("  |");
-
   // each line is 16 bytes
-  for(uint16_t i=0; i<count; i++)
-  {
-    const char ch = buf[i];
+  for (uint16_t i = 0; i < count; i++) {
+    int ch = buf[i];
     tu_printf("%c", isprint(ch) ? ch : '.');
   }
-
   tu_printf("|\r\n");
 }
 
@@ -251,42 +513,30 @@ static void dump_str_line(uint8_t const* buf, uint16_t count)
  *  - count : number of item
  *  - indent: prefix spaces on every line
  */
-void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
-{
+void tu_print_mem(void const* buf, uint32_t count, uint8_t indent) {
   uint8_t const size = 1; // fixed 1 byte for now
-
-  if ( !buf || !count )
-  {
+  if (!buf || !count) {
     tu_printf("NULL\r\n");
     return;
   }
 
-  uint8_t const *buf8 = (uint8_t const *) buf;
-
+  uint8_t const* buf8 = (uint8_t const*) buf;
   char format[] = "%00X";
-  format[2] += 2*size;
+  format[2] += (uint8_t) (2 * size); // 1 byte = 2 hex digits
+  const uint8_t item_per_line = 16 / size;
 
-  const uint8_t item_per_line  = 16 / size;
+  for (unsigned int i = 0; i < count; i++) {
+    unsigned int value = 0;
 
-  for(unsigned int i=0; i<count; i++)
-  {
-    unsigned int value=0;
-
-    if ( i%item_per_line == 0 )
-    {
+    if (i % item_per_line == 0) {
       // Print Ascii
-      if ( i != 0 )
-      {
-        dump_str_line(buf8-16, 16);
-      }
-
-      for(uint8_t s=0; s < indent; s++) tu_printf(" ");
-
+      if (i != 0) dump_str_line(buf8 - 16, 16);
+      for (uint8_t s = 0; s < indent; s++) tu_printf(" ");
       // print offset or absolute address
-      tu_printf("%04X: ", 16*i/item_per_line);
+      tu_printf("%04X: ", 16 * i / item_per_line);
     }
 
-    memcpy(&value, buf8, size);
+    tu_memcpy_s(&value, sizeof(value), buf8, size);
     buf8 += size;
 
     tu_printf(" ");
@@ -294,19 +544,16 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
   }
 
   // fill up last row to 16 for printing ascii
-  const uint32_t remain = count%16;
-  uint8_t nback = (uint8_t)(remain ? remain : 16);
-
-  if ( remain )
-  {
-    for(uint32_t i=0; i< 16-remain; i++)
-    {
+  const uint32_t remain = count % 16;
+  uint8_t nback = (uint8_t) (remain ? remain : 16);
+  if (remain) {
+    for (uint32_t i = 0; i < 16 - remain; i++) {
       tu_printf(" ");
-      for(int j=0; j<2*size; j++) tu_printf(" ");
+      for (int j = 0; j < 2 * size; j++) tu_printf(" ");
     }
   }
 
-  dump_str_line(buf8-nback, nback);
+  dump_str_line(buf8 - nback, nback);
 }
 
 #endif
diff --git a/src/tusb.h b/src/tusb.h
index 093c053f7..dfba21ddf 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -38,7 +38,10 @@
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
 
-#include "class/hid/hid.h"
+//------------- TypeC -------------//
+#if CFG_TUC_ENABLED
+  #include "typec/usbc.h"
+#endif
 
 //------------- HOST -------------//
 #if CFG_TUH_ENABLED
@@ -63,7 +66,10 @@
   #if CFG_TUH_VENDOR
     #include "class/vendor/vendor_host.h"
   #endif
-
+#else
+  #ifndef tuh_int_handler
+  #define tuh_int_handler(...)
+  #endif
 #endif
 
 //------------- DEVICE -------------//
@@ -117,24 +123,62 @@
   #if CFG_TUD_BTH
     #include "class/bth/bth_device.h"
   #endif
+#else
+  #ifndef tud_int_handler
+  #define tud_int_handler(...)
+  #endif
 #endif
 
 
 //--------------------------------------------------------------------+
-// APPLICATION API
+// User API
 //--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED || CFG_TUD_ENABLED
 
-// Initialize device/host stack
+// Internal helper for backward compatible with tusb_init(void)
+bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
+
+// Initialize roothub port with device/host role
 // Note: when using with RTOS, this should be called after scheduler/kernel is started.
-// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
-bool tusb_init(void);
+// Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+// Note2: defined as macro for backward compatible with tusb_init(void), can be changed to function in the future.
+#if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT)
+  #define _tusb_init_arg0()        tusb_rhport_init(0, NULL)
+#else
+  #define _tusb_init_arg0()        TU_VERIFY_STATIC(false, "CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE must be defined")
+#endif
+
+#define _tusb_init_arg1(_rhport)             _tusb_init_arg0()
+#define _tusb_init_arg2(_rhport, _rh_init)   tusb_rhport_init(_rhport, _rh_init)
+#define tusb_init(...)                       TU_FUNC_OPTIONAL_ARG(_tusb_init, __VA_ARGS__)
 
 // Check if stack is initialized
 bool tusb_inited(void);
 
+// Called to handle usb interrupt/event. tusb_init(rhport, role) must be called before
+void tusb_int_handler(uint8_t rhport, bool in_isr);
+
 // TODO
 // bool tusb_teardown(void);
 
+#else
+
+#define tusb_init(...)  (false)
+#define tusb_int_handler(...)  do {}while(0)
+#define tusb_inited()  (false)
+
+#endif
+
+//--------------------------------------------------------------------+
+// API Implemented by user
+//--------------------------------------------------------------------+
+
+// Get current milliseconds, required by some port/configuration without RTOS
+uint32_t tusb_time_millis_api(void);
+
+// Delay in milliseconds, use tusb_time_millis_api() by default. required by some port/configuration with no RTOS
+void tusb_time_delay_ms_api(uint32_t ms);
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index b905fc7ce..84319939a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -27,14 +27,14 @@
 #ifndef _TUSB_OPTION_H_
 #define _TUSB_OPTION_H_
 
-// To avoid GCC compiler warnings when -pedantic option is used (strict ISO C)
-typedef int make_iso_compilers_happy;
-
 #include "common/tusb_compiler.h"
 
+// Version is release as major.minor.revision eg 1.0.0
 #define TUSB_VERSION_MAJOR     0
-#define TUSB_VERSION_MINOR     14
+#define TUSB_VERSION_MINOR     18
 #define TUSB_VERSION_REVISION  0
+
+#define TUSB_VERSION_NUMBER    (TUSB_VERSION_MAJOR * 10000 + TUSB_VERSION_MINOR * 100 + TUSB_VERSION_REVISION)
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 
 //--------------------------------------------------------------------+
@@ -53,9 +53,13 @@ typedef int make_iso_compilers_happy;
 #define OPT_MCU_LPC18XX             6 ///< NXP LPC18xx
 #define OPT_MCU_LPC40XX             7 ///< NXP LPC40xx
 #define OPT_MCU_LPC43XX             8 ///< NXP LPC43xx
-#define OPT_MCU_LPC51UXX            9 ///< NXP LPC51U6x
-#define OPT_MCU_LPC54XXX           10 ///< NXP LPC54xxx
-#define OPT_MCU_LPC55XX            11 ///< NXP LPC55xx
+#define OPT_MCU_LPC51               9 ///< NXP LPC51
+#define OPT_MCU_LPC51UXX            OPT_MCU_LPC51 ///< NXP LPC51
+#define OPT_MCU_LPC54              10 ///< NXP LPC54
+#define OPT_MCU_LPC55              11 ///< NXP LPC55
+// legacy naming
+#define OPT_MCU_LPC54XXX           OPT_MCU_LPC54
+#define OPT_MCU_LPC55XX            OPT_MCU_LPC55
 
 // NRF
 #define OPT_MCU_NRF5X             100 ///< Nordic nRF5x series
@@ -85,6 +89,11 @@ typedef int make_iso_compilers_happy;
 #define OPT_MCU_STM32G4           311 ///< ST G4
 #define OPT_MCU_STM32WB           312 ///< ST WB
 #define OPT_MCU_STM32U5           313 ///< ST U5
+#define OPT_MCU_STM32L5           314 ///< ST L5
+#define OPT_MCU_STM32H5           315 ///< ST H5
+#define OPT_MCU_STM32U0           316 ///< ST U0
+#define OPT_MCU_STM32H7RS         317 ///< ST F7RS
+#define OPT_MCU_STM32C0           318 ///< ST C0
 
 // Sony
 #define OPT_MCU_CXD56             400 ///< SONY CXD56
@@ -99,9 +108,9 @@ typedef int make_iso_compilers_happy;
 #define OPT_MCU_VALENTYUSB_EPTRI  600 ///< Fomu eptri config
 
 // NXP iMX RT
-#define OPT_MCU_MIMXRT            700             ///< NXP iMX RT Series
-#define OPT_MCU_MIMXRT10XX        OPT_MCU_MIMXRT  ///< RT10xx
-#define OPT_MCU_MIMXRT11XX        OPT_MCU_MIMXRT  ///< RT11xx
+#define OPT_MCU_MIMXRT1XXX        700                 ///< NXP iMX RT1xxx Series
+#define OPT_MCU_MIMXRT10XX        OPT_MCU_MIMXRT1XXX  ///< RT10xx
+#define OPT_MCU_MIMXRT11XX        OPT_MCU_MIMXRT1XXX  ///< RT11xx
 
 // Nuvoton
 #define OPT_MCU_NUC121            800
@@ -112,6 +121,14 @@ typedef int make_iso_compilers_happy;
 // Espressif
 #define OPT_MCU_ESP32S2           900 ///< Espressif ESP32-S2
 #define OPT_MCU_ESP32S3           901 ///< Espressif ESP32-S3
+#define OPT_MCU_ESP32             902 ///< Espressif ESP32 (for host max3421e)
+#define OPT_MCU_ESP32C3           903 ///< Espressif ESP32-C3
+#define OPT_MCU_ESP32C6           904 ///< Espressif ESP32-C6
+#define OPT_MCU_ESP32C2           905 ///< Espressif ESP32-C2
+#define OPT_MCU_ESP32H2           906 ///< Espressif ESP32-H2
+#define OPT_MCU_ESP32P4           907 ///< Espressif ESP32-P4
+#define TUSB_MCU_VENDOR_ESPRESSIF (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU
+#define TUP_MCU_ESPRESSIF        TUSB_MCU_VENDOR_ESPRESSIF //  for backward compatibility
 
 // Dialog
 #define OPT_MCU_DA1469X          1000 ///< Dialog Semiconductor DA1469x
@@ -120,8 +137,13 @@ typedef int make_iso_compilers_happy;
 #define OPT_MCU_RP2040           1100 ///< Raspberry Pi RP2040
 
 // NXP Kinetis
-#define OPT_MCU_MKL25ZXX         1200 ///< NXP MKL25Zxx
-#define OPT_MCU_K32L2BXX         1201 ///< NXP K32L2Bxx
+#define OPT_MCU_KINETIS_KL       1200 ///< NXP KL series
+#define OPT_MCU_KINETIS_K32L     1201 ///< NXP K32L series
+#define OPT_MCU_KINETIS_K32      1201 ///< Alias to K32L
+#define OPT_MCU_KINETIS_K        1202 ///< NXP K series
+
+#define OPT_MCU_MKL25ZXX         1200 ///< Alias to KL (obsolete)
+#define OPT_MCU_K32L2BXX         1201 ///< Alias to K32 (obsolete)
 
 // Silabs
 #define OPT_MCU_EFM32GG          1300 ///< Silabs EFM32GG
@@ -130,6 +152,7 @@ typedef int make_iso_compilers_happy;
 #define OPT_MCU_RX63X            1400 ///< Renesas RX63N/631
 #define OPT_MCU_RX65X            1401 ///< Renesas RX65N/RX651
 #define OPT_MCU_RX72N            1402 ///< Renesas RX72N
+#define OPT_MCU_RAXXX            1403 ///< Renesas RA generic
 
 // Mind Motion
 #define OPT_MCU_MM32F327X        1500 ///< Mind Motion MM32F327
@@ -160,10 +183,26 @@ typedef int make_iso_compilers_happy;
 // Allwinner
 #define OPT_MCU_F1C100S          2100 ///< Allwinner F1C100s family
 
-// Helper to check if configured MCU is one of listed
+// WCH
+#define OPT_MCU_CH32V307         2200 ///< WCH CH32V307
+#define OPT_MCU_CH32F20X         2210 ///< WCH CH32F20x
+#define OPT_MCU_CH32V20X         2220 ///< WCH CH32V20X
+#define OPT_MCU_CH32V103         2230 ///< WCH CH32V103
+
+// NXP LPC MCX
+#define OPT_MCU_MCXN9            2300  ///< NXP MCX N9 Series
+#define OPT_MCU_MCXA15           2301  ///< NXP MCX A15 Series
+
+// Analog Devices
+#define OPT_MCU_MAX32690         2400  ///< ADI MAX32690
+#define OPT_MCU_MAX32666         2401  ///< ADI MAX32666/5
+#define OPT_MCU_MAX32650         2402  ///< ADI MAX32650/1/2
+#define OPT_MCU_MAX78002         2403  ///< ADI MAX78002
+
+// Check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
-#define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == _m)
-#define TU_CHECK_MCU(...)   (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__))
+#define _TU_CHECK_MCU(_m)    (CFG_TUSB_MCU == _m)
+#define TU_CHECK_MCU(...)    (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__))
 
 //--------------------------------------------------------------------+
 // Supported OS
@@ -176,20 +215,11 @@ typedef int make_iso_compilers_happy;
 #define OPT_OS_PICO       5  ///< Raspberry Pi Pico SDK
 #define OPT_OS_RTTHREAD   6  ///< RT-Thread
 #define OPT_OS_RTX4       7  ///< Keil RTX 4
+#define OPT_OS_ZEPHYR     8  ///< Zephyr
 
-// Allow to use command line to change the config name/location
-#ifdef CFG_TUSB_CONFIG_FILE
-  #include CFG_TUSB_CONFIG_FILE
-#else
-  #include "tusb_config.h"
-#endif
-
-#include "common/tusb_mcu.h"
-
-//--------------------------------------------------------------------
-// RootHub Mode Configuration
-// CFG_TUSB_RHPORTx_MODE contains operation mode and speed for that port
-//--------------------------------------------------------------------
+//--------------------------------------------------------------------+
+// Mode and Speed
+//--------------------------------------------------------------------+
 
 // Low byte is operational mode
 #define OPT_MODE_NONE           0x0000 ///< Disabled
@@ -203,7 +233,78 @@ typedef int make_iso_compilers_happy;
 #define OPT_MODE_HIGH_SPEED     0x0400 ///< High Speed
 #define OPT_MODE_SPEED_MASK     0xff00
 
-//------------- Roothub as Device -------------//
+//--------------------------------------------------------------------+
+// Include tusb_config.h
+//--------------------------------------------------------------------+
+
+// Allow to use command line to change the config name/location
+#ifdef CFG_TUSB_CONFIG_FILE
+  #include CFG_TUSB_CONFIG_FILE
+#else
+  #include "tusb_config.h"
+#endif
+
+#include "common/tusb_mcu.h"
+
+//--------------------------------------------------------------------+
+// USBIP
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUD_DWC2_SLAVE_ENABLE
+  #ifndef CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT
+  #define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT 1
+  #endif
+
+  #define CFG_TUD_DWC2_SLAVE_ENABLE CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT
+#endif
+
+// Enable DWC2 DMA for device
+#ifndef CFG_TUD_DWC2_DMA_ENABLE
+  #ifndef CFG_TUD_DWC2_DMA_ENABLE_DEFAULT
+  #define CFG_TUD_DWC2_DMA_ENABLE_DEFAULT 0
+  #endif
+
+  #define CFG_TUD_DWC2_DMA_ENABLE CFG_TUD_DWC2_DMA_ENABLE_DEFAULT
+#endif
+
+// Enable DWC2 Slave mode for host
+#ifndef CFG_TUH_DWC2_SLAVE_ENABLE
+  #ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
+  #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT 1
+  #endif
+
+  #define CFG_TUH_DWC2_SLAVE_ENABLE CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
+#endif
+
+// Enable DWC2 DMA for host
+#ifndef CFG_TUH_DWC2_DMA_ENABLE
+  #ifndef CFG_TUH_DWC2_DMA_ENABLE_DEFAULT
+  #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0
+  #endif
+
+  #define CFG_TUH_DWC2_DMA_ENABLE   CFG_TUH_DWC2_DMA_ENABLE_DEFAULT
+#endif
+
+// Enable PIO-USB software host controller
+#ifndef CFG_TUH_RPI_PIO_USB
+  #define CFG_TUH_RPI_PIO_USB 0
+#endif
+
+#ifndef CFG_TUD_RPI_PIO_USB
+  #define CFG_TUD_RPI_PIO_USB 0
+#endif
+
+// MAX3421 Host controller option
+#ifndef CFG_TUH_MAX3421
+  #define CFG_TUH_MAX3421  0
+#endif
+
+
+//--------------------------------------------------------------------
+// RootHub Mode detection
+//--------------------------------------------------------------------
+
+//------------- Root hub as Device -------------//
 
 #if defined(CFG_TUSB_RHPORT0_MODE) && ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE)
   #define TUD_RHPORT_MODE     (CFG_TUSB_RHPORT0_MODE)
@@ -231,7 +332,7 @@ typedef int make_iso_compilers_happy;
 // highspeed support indicator
 #define TUD_OPT_HIGH_SPEED    (CFG_TUD_MAX_SPEED ? (CFG_TUD_MAX_SPEED & OPT_MODE_HIGH_SPEED) : TUP_RHPORT_HIGHSPEED)
 
-//------------- Roothub as Host -------------//
+//------------- Root hub as Host -------------//
 
 #if defined(CFG_TUSB_RHPORT0_MODE) && ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST)
   #define TUH_RHPORT_MODE  (CFG_TUSB_RHPORT0_MODE)
@@ -256,6 +357,10 @@ typedef int make_iso_compilers_happy;
 // For backward compatible
 #define TUSB_OPT_HOST_ENABLED   CFG_TUH_ENABLED
 
+// highspeed support indicator
+#define TUH_OPT_HIGH_SPEED    (CFG_TUH_MAX_SPEED ? (CFG_TUH_MAX_SPEED & OPT_MODE_HIGH_SPEED) : TUP_RHPORT_HIGHSPEED)
+
+
 //--------------------------------------------------------------------+
 // TODO move later
 //--------------------------------------------------------------------+
@@ -264,7 +369,7 @@ typedef int make_iso_compilers_happy;
 // In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
 // to generate unaligned access code.
 // LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM
-#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX)
+#if TUD_OPT_HIGH_SPEED && TU_CHECK_MCU(OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX)
   #define TUP_MCU_STRICT_ALIGN   1
 #else
   #define TUP_MCU_STRICT_ALIGN   0
@@ -280,32 +385,75 @@ typedef int make_iso_compilers_happy;
   #define CFG_TUSB_DEBUG 0
 #endif
 
-// place data in accessible RAM for usb controller
+// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
+#ifndef CFG_TUH_LOG_LEVEL
+  #define CFG_TUH_LOG_LEVEL   2
+#endif
+
+// Level where CFG_TUSB_DEBUG must be at least for USBD is logged
+#ifndef CFG_TUD_LOG_LEVEL
+  #define CFG_TUD_LOG_LEVEL   2
+#endif
+
+// Memory section for placing buffer used for usb transferring. If MEM_SECTION is different for
+// host and device use: CFG_TUD_MEM_SECTION, CFG_TUH_MEM_SECTION instead
 #ifndef CFG_TUSB_MEM_SECTION
   #define CFG_TUSB_MEM_SECTION
 #endif
 
-// alignment requirement of buffer used for endpoint transferring
+// Alignment requirement of buffer used for usb transferring. if MEM_ALIGN is different for
+// host and device controller use: CFG_TUD_MEM_ALIGN, CFG_TUH_MEM_ALIGN instead
 #ifndef CFG_TUSB_MEM_ALIGN
   #define CFG_TUSB_MEM_ALIGN      TU_ATTR_ALIGNED(4)
 #endif
 
+#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE
+  #ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
+  #endif
+
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
+#endif
+
 // OS selection
 #ifndef CFG_TUSB_OS
   #define CFG_TUSB_OS             OPT_OS_NONE
 #endif
 
 #ifndef CFG_TUSB_OS_INC_PATH
-  #define CFG_TUSB_OS_INC_PATH
-#endif
+  #ifndef CFG_TUSB_OS_INC_PATH_DEFAULT
+  #define CFG_TUSB_OS_INC_PATH_DEFAULT
+  #endif
 
-// mutex is only needed for RTOS TODO also required with multiple core MCUs
-#define TUSB_OPT_MUTEX      (CFG_TUSB_OS != OPT_OS_NONE)
+  #define CFG_TUSB_OS_INC_PATH  CFG_TUSB_OS_INC_PATH_DEFAULT
+#endif
 
 //--------------------------------------------------------------------
 // Device Options (Default)
 //--------------------------------------------------------------------
 
+// Attribute to place data in accessible RAM for device controller (default: CFG_TUSB_MEM_SECTION)
+#ifndef CFG_TUD_MEM_SECTION
+  #define CFG_TUD_MEM_SECTION     CFG_TUSB_MEM_SECTION
+#endif
+
+// Attribute to align memory for device controller (default: CFG_TUSB_MEM_ALIGN)
+#ifndef CFG_TUD_MEM_ALIGN
+  #define CFG_TUD_MEM_ALIGN       CFG_TUSB_MEM_ALIGN
+#endif
+
+#ifndef CFG_TUD_MEM_DCACHE_ENABLE
+  #ifndef CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  0
+  #endif
+
+  #define CFG_TUD_MEM_DCACHE_ENABLE   CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT
+#endif
+
+#ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE
+  #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
+#endif
+
 #ifndef CFG_TUD_ENDPOINT0_SIZE
   #define CFG_TUD_ENDPOINT0_SIZE  64
 #endif
@@ -314,6 +462,29 @@ typedef int make_iso_compilers_happy;
   #define CFG_TUD_INTERFACE_MAX   16
 #endif
 
+// default to max hardware endpoint, but can be smaller to save RAM
+#ifndef CFG_TUD_ENDPPOINT_MAX
+  #define CFG_TUD_ENDPPOINT_MAX   TUP_DCD_ENDPOINT_MAX
+#endif
+
+#if CFG_TUD_ENDPPOINT_MAX > TUP_DCD_ENDPOINT_MAX
+  #error "CFG_TUD_ENDPPOINT_MAX must be less than or equal to TUP_DCD_ENDPOINT_MAX"
+#endif
+
+// USB 2.0 7.1.20: compliance test mode support
+#ifndef CFG_TUD_TEST_MODE
+  #define CFG_TUD_TEST_MODE       0
+#endif
+
+//------------- Device Class Driver -------------//
+#ifndef CFG_TUD_BTH
+  #define CFG_TUD_BTH             0
+#endif
+
+#if CFG_TUD_BTH && !defined(CFG_TUD_BTH_ISO_ALT_COUNT)
+#error CFG_TUD_BTH_ISO_ALT_COUNT must be defined to tell Bluetooth driver the number of ISO endpoints to use
+#endif
+
 #ifndef CFG_TUD_CDC
   #define CFG_TUD_CDC             0
 #endif
@@ -354,10 +525,6 @@ typedef int make_iso_compilers_happy;
   #define CFG_TUD_DFU             0
 #endif
 
-#ifndef CFG_TUD_BTH
-  #define CFG_TUD_BTH             0
-#endif
-
 #ifndef CFG_TUD_ECM_RNDIS
   #ifdef CFG_TUD_NET
     #warning "CFG_TUD_NET is renamed to CFG_TUD_ECM_RNDIS"
@@ -384,45 +551,108 @@ typedef int make_iso_compilers_happy;
   #endif
 #endif // CFG_TUH_ENABLED
 
+// Attribute to place data in accessible RAM for host controller (default: CFG_TUSB_MEM_SECTION)
+#ifndef CFG_TUH_MEM_SECTION
+  #define CFG_TUH_MEM_SECTION   CFG_TUSB_MEM_SECTION
+#endif
+
+// Attribute to align memory for host controller
+#ifndef CFG_TUH_MEM_ALIGN
+  #define CFG_TUH_MEM_ALIGN     CFG_TUSB_MEM_ALIGN
+#endif
+
+#ifndef CFG_TUH_MEM_DCACHE_ENABLE
+  #ifndef CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  0
+  #endif
+
+  #define CFG_TUH_MEM_DCACHE_ENABLE   CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT
+#endif
+
+#ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE
+  #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
+#endif
+
 //------------- CLASS -------------//
 
 #ifndef CFG_TUH_HUB
-#define CFG_TUH_HUB    0
+  #define CFG_TUH_HUB    0
 #endif
 
 #ifndef CFG_TUH_CDC
-#define CFG_TUH_CDC    0
+  #define CFG_TUH_CDC    0
+#endif
+
+// FTDI is not part of CDC class, only to re-use CDC driver API
+#ifndef CFG_TUH_CDC_FTDI
+  #define CFG_TUH_CDC_FTDI 0
+#endif
+
+// List of product IDs that can use the FTDI CDC driver. 0x0403 is FTDI's VID
+#ifndef CFG_TUH_CDC_FTDI_VID_PID_LIST
+  #define CFG_TUH_CDC_FTDI_VID_PID_LIST \
+    {0x0403, 0x6001}, {0x0403, 0x6006}, {0x0403, 0x6010}, {0x0403, 0x6011}, \
+    {0x0403, 0x6014}, {0x0403, 0x6015}, {0x0403, 0x8372}, {0x0403, 0xFBFA}, \
+    {0x0403, 0xCD18}
+#endif
+
+// CP210X is not part of CDC class, only to re-use CDC driver API
+#ifndef CFG_TUH_CDC_CP210X
+  #define CFG_TUH_CDC_CP210X 0
+#endif
+
+// List of product IDs that can use the CP210X CDC driver. 0x10C4 is Silicon Labs' VID
+#ifndef CFG_TUH_CDC_CP210X_VID_PID_LIST
+  #define CFG_TUH_CDC_CP210X_VID_PID_LIST \
+    {0x10C4, 0xEA60}, {0x10C4, 0xEA70}
+#endif
+
+#ifndef CFG_TUH_CDC_CH34X
+  // CH34X is not part of CDC class, only to re-use CDC driver API
+  #define CFG_TUH_CDC_CH34X 0
+#endif
+
+// List of product IDs that can use the CH34X CDC driver
+#ifndef CFG_TUH_CDC_CH34X_VID_PID_LIST
+  #define CFG_TUH_CDC_CH34X_VID_PID_LIST \
+    { 0x1a86, 0x5523 }, /* ch341 chip */ \
+    { 0x1a86, 0x7522 }, /* ch340k chip */ \
+    { 0x1a86, 0x7523 }, /* ch340 chip */ \
+    { 0x1a86, 0xe523 }, /* ch330 chip */ \
+    { 0x4348, 0x5523 }, /* ch340 custom chip */ \
+    { 0x2184, 0x0057 }, /* overtaken from Linux Kernel driver /drivers/usb/serial/ch341.c */ \
+    { 0x9986, 0x7523 }  /* overtaken from Linux Kernel driver /drivers/usb/serial/ch341.c */
 #endif
 
 #ifndef CFG_TUH_HID
-#define CFG_TUH_HID    0
+  #define CFG_TUH_HID    0
 #endif
 
 #ifndef CFG_TUH_MIDI
-#define CFG_TUH_MIDI   0
+  #define CFG_TUH_MIDI   0
 #endif
 
 #ifndef CFG_TUH_MSC
-#define CFG_TUH_MSC    0
+  #define CFG_TUH_MSC    0
 #endif
 
 #ifndef CFG_TUH_VENDOR
-#define CFG_TUH_VENDOR 0
+  #define CFG_TUH_VENDOR 0
 #endif
 
 #ifndef CFG_TUH_API_EDPT_XFER
-#define CFG_TUH_API_EDPT_XFER 0
+  #define CFG_TUH_API_EDPT_XFER 0
 #endif
 
-// Enable PIO-USB software host controller
-#ifndef CFG_TUH_RPI_PIO_USB
-#define CFG_TUH_RPI_PIO_USB 0
-#endif
+//--------------------------------------------------------------------+
+// TypeC Options (Default)
+//--------------------------------------------------------------------+
 
-#ifndef CFG_TUD_RPI_PIO_USB
-#define CFG_TUD_RPI_PIO_USB 0
-#endif
+#ifndef CFG_TUC_ENABLED
+#define CFG_TUC_ENABLED 0
 
+#define tuc_int_handler(_p)
+#endif
 
 //------------------------------------------------------------------
 // Configuration Validation
@@ -431,6 +661,9 @@ typedef int make_iso_compilers_happy;
 //  #error Control Endpoint Max Packet Size cannot be larger than 64
 //#endif
 
+// To avoid GCC compiler warnings when -pedantic option is used (strict ISO C)
+typedef int make_iso_compilers_happy;
+
 #endif /* _TUSB_OPTION_H_ */
 
 /** @} */
diff --git a/src/typec/pd_types.h b/src/typec/pd_types.h
new file mode 100644
index 000000000..1b2968f65
--- /dev/null
+++ b/src/typec/pd_types.h
@@ -0,0 +1,237 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_PD_TYPES_H_
+#define _TUSB_PD_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "common/tusb_compiler.h"
+
+// Start of all packed definitions for compiler without per-type packed
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
+
+//--------------------------------------------------------------------+
+// TYPE-C
+//--------------------------------------------------------------------+
+
+typedef enum {
+  TUSB_TYPEC_PORT_SRC,
+  TUSB_TYPEC_PORT_SNK,
+  TUSB_TYPEC_PORT_DRP
+} tusb_typec_port_type_t;
+
+enum {
+  PD_CTRL_RESERVED = 0,            // 0b00000: 0
+  PD_CTRL_GOOD_CRC,                // 0b00001: 1
+  PD_CTRL_GO_TO_MIN,               // 0b00010: 2
+  PD_CTRL_ACCEPT,                  // 0b00011: 3
+  PD_CTRL_REJECT,                  // 0b00100: 4
+  PD_CTRL_PING,                    // 0b00101: 5
+  PD_CTRL_PS_READY,                // 0b00110: 6
+  PD_CTRL_GET_SOURCE_CAP,          // 0b00111: 7
+  PD_CTRL_GET_SINK_CAP,            // 0b01000: 8
+  PD_CTRL_DR_SWAP,                 // 0b01001: 9
+  PD_CTRL_PR_SWAP,                 // 0b01010: 10
+  PD_CTRL_VCONN_SWAP,              // 0b01011: 11
+  PD_CTRL_WAIT,                    // 0b01100: 12
+  PD_CTRL_SOFT_RESET,              // 0b01101: 13
+  PD_CTRL_DATA_RESET,              // 0b01110: 14
+  PD_CTRL_DATA_RESET_COMPLETE,     // 0b01111: 15
+  PD_CTRL_NOT_SUPPORTED,           // 0b10000: 16
+  PD_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
+  PD_CTRL_GET_STATUS,              // 0b10010: 18
+  PD_CTRL_FR_SWAP,                 // 0b10011: 19
+  PD_CTRL_GET_PPS_STATUS,          // 0b10100: 20
+  PD_CTRL_GET_COUNTRY_CODES,       // 0b10101: 21
+  PD_CTRL_GET_SINK_CAP_EXTENDED,   // 0b10110: 22
+  PD_CTRL_GET_SOURCE_INFO,         // 0b10111: 23
+  PD_CTRL_REVISION,                // 0b11000: 24
+};
+
+enum {
+  PD_DATA_RESERVED = 0,     // 0b00000: 0
+  PD_DATA_SOURCE_CAP,       // 0b00001: 1
+  PD_DATA_REQUEST,          // 0b00010: 2
+  PD_DATA_BIST,             // 0b00011: 3
+  PD_DATA_SINK_CAP,         // 0b00100: 4
+  PD_DATA_BATTERY_STATUS,   // 0b00101: 5
+  PD_DATA_ALERT,            // 0b00110: 6
+  PD_DATA_GET_COUNTRY_INFO, // 0b00111: 7
+  PD_DATA_ENTER_USB,        // 0b01000: 8
+  PD_DATA_EPR_REQUEST,      // 0b01001: 9
+  PD_DATA_EPR_MODE,         // 0b01010: 10
+  PD_DATA_SRC_INFO,         // 0b01011: 11
+  PD_DATA_REVISION,         // 0b01100: 12
+  PD_DATA_RESERVED_13,      // 0b01101: 13
+  PD_DATA_RESERVED_14,      // 0b01110: 14
+  PD_DATA_VENDOR_DEFINED,   // 0b01111: 15
+};
+
+enum {
+  PD_REV_10	= 0x0,
+  PD_REV_20	= 0x1,
+  PD_REV_30	= 0x2,
+};
+
+enum {
+  PD_DATA_ROLE_UFP	= 0x0,
+  PD_DATA_ROLE_DFP	= 0x1,
+};
+
+enum {
+  PD_POWER_ROLE_SINK	= 0x0,
+  PD_POWER_ROLE_SOURCE	= 0x1,
+};
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t msg_type   : 5; // [0:4]
+  uint16_t data_role  : 1; // [5] SOP only: 0 UFP, 1 DFP
+  uint16_t specs_rev  : 2; // [6:7]
+  uint16_t power_role : 1; // [8] SOP only: 0 Sink, 1 Source
+  uint16_t msg_id     : 3; // [9:11]
+  uint16_t n_data_obj : 3; // [12:14]
+  uint16_t extended   : 1; // [15]
+} pd_header_t;
+TU_VERIFY_STATIC(sizeof(pd_header_t) == 2, "size is not correct");
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t data_size     : 9; // [0:8]
+  uint16_t reserved      : 1; // [9]
+  uint16_t request_chunk : 1; // [10]
+  uint16_t chunk_number  : 4; // [11:14]
+  uint16_t chunked       : 1; // [15]
+} pd_header_extended_t;
+TU_VERIFY_STATIC(sizeof(pd_header_extended_t) == 2, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Source Capability
+//--------------------------------------------------------------------+
+
+// All table references are from USBPD Specification rev3.1 version 1.8
+enum {
+  PD_PDO_TYPE_FIXED = 0, // Vmin = Vmax
+  PD_PDO_TYPE_BATTERY,
+  PD_PDO_TYPE_VARIABLE, // non-battery
+  PD_PDO_TYPE_APDO, // Augmented Power Data Object
+};
+
+// Fixed Power Data Object (PDO) table 6-9
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_max_10ma          : 10; // [9..0] Max current in 10mA unit
+  uint32_t voltage_50mv              : 10; // [19..10] Voltage in 50mV unit
+  uint32_t current_peak              :  2; // [21..20] Peak current
+  uint32_t reserved                  :  1; // [22] Reserved
+  uint32_t epr_mode_capable          :  1; // [23] epr_mode_capable
+  uint32_t unchunked_ext_msg_support :  1; // [24] UnChunked Extended Message Supported
+  uint32_t dual_role_data            :  1; // [25] Dual Role Data
+  uint32_t usb_comm_capable          :  1; // [26] USB Communications Capable
+  uint32_t unconstrained_power       :  1; // [27] Unconstrained Power
+  uint32_t usb_suspend_supported     :  1; // [28] USB Suspend Supported
+  uint32_t dual_role_power           :  1; // [29] Dual Role Power
+  uint32_t type                      :  2; // [30] Fixed Supply type = PD_PDO_TYPE_FIXED
+} pd_pdo_fixed_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_fixed_t) == 4, "Invalid size");
+
+// Battery Power Data Object (PDO) table 6-12
+typedef struct TU_ATTR_PACKED {
+  uint32_t power_max_250mw   : 10; // [9..0] Max allowable power in 250mW unit
+  uint32_t voltage_min_50mv  : 10; // [19..10] Minimum voltage in 50mV unit
+  uint32_t voltage_max_50mv  : 10; // [29..20] Maximum voltage in 50mV unit
+  uint32_t type              :  2; // [31..30] Battery type = PD_PDO_TYPE_BATTERY
+} pd_pdo_battery_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_battery_t) == 4, "Invalid size");
+
+// Variable Power Data Object (PDO) table 6-11
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_max_10ma  : 10; // [9..0] Max current in 10mA unit
+  uint32_t voltage_min_50mv  : 10; // [19..10] Minimum voltage in 50mV unit
+  uint32_t voltage_max_50mv  : 10; // [29..20] Maximum voltage in 50mV unit
+  uint32_t type              :  2; // [31..30] Variable Supply type = PD_PDO_TYPE_VARIABLE
+} pd_pdo_variable_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_variable_t) == 4, "Invalid size");
+
+// Augmented Power Data Object (PDO) table 6-13
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_max_50ma  :  7; // [6..0] Max current in 50mA unit
+  uint32_t reserved1         :  1; // [7] Reserved
+  uint32_t voltage_min_100mv :  8; // [15..8] Minimum Voltage in 100mV unit
+  uint32_t reserved2         :  1; // [16] Reserved
+  uint32_t voltage_max_100mv :  8; // [24..17] Maximum Voltage in 100mV unit
+  uint32_t reserved3         :  2; // [26..25] Reserved
+  uint32_t pps_power_limited :  1; // [27] PPS Power Limited
+  uint32_t spr_programmable  :  2; // [29..28] SPR Programmable Power Supply
+  uint32_t type              :  2; // [31..30] Augmented Power Data Object = PD_PDO_TYPE_APDO
+} pd_pdo_apdo_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_apdo_t) == 4, "Invalid size");
+
+//--------------------------------------------------------------------+
+// Request
+//--------------------------------------------------------------------+
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_extremum_10ma     : 10; // [9..0] Max (give back = 0) or Min (give back = 1) current in 10mA unit
+  uint32_t current_operate_10ma      : 10; // [19..10] Operating current in 10mA unit
+  uint32_t reserved                  :  2; // [21..20] Reserved
+  uint32_t epr_mode_capable          :  1; // [22] EPR mode capable
+  uint32_t unchunked_ext_msg_support :  1; // [23] UnChunked Extended Message Supported
+  uint32_t no_usb_suspend            :  1; // [24] No USB Suspend
+  uint32_t usb_comm_capable          :  1; // [25] USB Communications Capable
+  uint32_t capability_mismatch       :  1; // [26] Capability Mismatch
+  uint32_t give_back_flag            :  1; // [27] GiveBack Flag: 0 = Max, 1 = Min
+  uint32_t object_position           :  4; // [31..28] Object Position
+} pd_rdo_fixed_variable_t;
+TU_VERIFY_STATIC(sizeof(pd_rdo_fixed_variable_t) == 4, "Invalid size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t power_extremum_250mw      : 10; // [9..0] Max (give back = 0) or Min (give back = 1) operating power in 250mW unit
+  uint32_t power_operate_250mw       : 10; // [19..10] Operating power in 250mW unit
+  uint32_t reserved                  :  2; // [21..20] Reserved
+  uint32_t epr_mode_capable          :  1; // [22] EPR mode capable
+  uint32_t unchunked_ext_msg_support :  1; // [23] UnChunked Extended Message Supported
+  uint32_t no_usb_suspend            :  1; // [24] No USB Suspend
+  uint32_t usb_comm_capable          :  1; // [25] USB Communications Capable
+  uint32_t capability_mismatch       :  1; // [26] Capability Mismatch
+  uint32_t give_back_flag            :  1; // [27] GiveBack Flag: 0 = Max, 1 = Min
+  uint32_t object_position           :  4; // [31..28] Object Position
+} pd_rdo_battery_t;
+TU_VERIFY_STATIC(sizeof(pd_rdo_battery_t) == 4, "Invalid size");
+
+
+TU_ATTR_PACKED_END  // End of all packed definitions
+TU_ATTR_BIT_FIELD_ORDER_END
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/typec/tcd.h b/src/typec/tcd.h
new file mode 100644
index 000000000..bcbdab8ed
--- /dev/null
+++ b/src/typec/tcd.h
@@ -0,0 +1,143 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_TCD_H_
+#define _TUSB_TCD_H_
+
+#include "common/tusb_common.h"
+#include "pd_types.h"
+
+#include "osal/osal.h"
+#include "common/tusb_fifo.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+enum {
+  TCD_EVENT_INVALID = 0,
+  TCD_EVENT_CC_CHANGED,
+  TCD_EVENT_RX_COMPLETE,
+  TCD_EVENT_TX_COMPLETE,
+};
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t rhport;
+  uint8_t event_id;
+
+  union {
+    struct {
+      uint8_t cc_state[2];
+    } cc_changed;
+
+    struct TU_ATTR_PACKED {
+      uint16_t result : 2;
+      uint16_t xferred_bytes : 14;
+    } xfer_complete;
+  };
+
+} tcd_event_t;
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Initialize controller
+bool tcd_init(uint8_t rhport, uint32_t port_type);
+
+// Enable interrupt
+void tcd_int_enable (uint8_t rhport);
+
+// Disable interrupt
+void tcd_int_disable(uint8_t rhport);
+
+// Interrupt Handler
+void tcd_int_handler(uint8_t rhport);
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tcd_msg_receive(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes);
+bool tcd_msg_send(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes);
+
+//--------------------------------------------------------------------+
+// Event API (implemented by stack)
+// Called by TCD to notify stack
+//--------------------------------------------------------------------+
+
+extern void tcd_event_handler(tcd_event_t const * event, bool in_isr);
+
+TU_ATTR_ALWAYS_INLINE static inline
+void tcd_event_cc_changed(uint8_t rhport, uint8_t cc1, uint8_t cc2, bool in_isr) {
+  tcd_event_t event = {
+    .rhport   = rhport,
+    .event_id = TCD_EVENT_CC_CHANGED,
+    .cc_changed = {
+        .cc_state = {cc1, cc2 }
+    }
+  };
+
+  tcd_event_handler(&event, in_isr);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline
+void tcd_event_rx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t result, bool in_isr) {
+  tcd_event_t event = {
+    .rhport   = rhport,
+    .event_id = TCD_EVENT_RX_COMPLETE,
+    .xfer_complete = {
+        .xferred_bytes = xferred_bytes,
+        .result        = result
+    }
+  };
+
+  tcd_event_handler(&event, in_isr);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline
+void tcd_event_tx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t result, bool in_isr) {
+  tcd_event_t event = {
+      .rhport   = rhport,
+      .event_id = TCD_EVENT_TX_COMPLETE,
+      .xfer_complete = {
+          .xferred_bytes = xferred_bytes,
+          .result        = result
+      }
+  };
+
+  tcd_event_handler(&event, in_isr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/typec/usbc.c b/src/typec/usbc.c
new file mode 100644
index 000000000..fdf2a0cd6
--- /dev/null
+++ b/src/typec/usbc.c
@@ -0,0 +1,219 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (thach@tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUC_ENABLED
+
+#include "tcd.h"
+#include "usbc.h"
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Debug level of USBD
+#define USBC_DEBUG   2
+#define TU_LOG_USBC(...)   TU_LOG(USBC_DEBUG, __VA_ARGS__)
+
+// Event queue
+// usbc_int_set() is used as mutex in OS NONE config
+void usbc_int_set(bool enabled);
+OSAL_QUEUE_DEF(usbc_int_set, _usbc_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t);
+tu_static osal_queue_t _usbc_q;
+
+// if stack is initialized
+static bool _usbc_inited = false;
+
+// if port is initialized
+static bool _port_inited[TUP_TYPEC_RHPORTS_NUM];
+
+// Max possible PD size is 262 bytes
+static uint8_t _rx_buf[64] TU_ATTR_ALIGNED(4);
+static uint8_t _tx_buf[64] TU_ATTR_ALIGNED(4);
+
+bool usbc_msg_send(uint8_t rhport, pd_header_t const* header, void const* data);
+bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end);
+bool parse_msg_control(uint8_t rhport, pd_header_t const* header);
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+bool tuc_inited(uint8_t rhport) {
+  return _usbc_inited && _port_inited[rhport];
+}
+
+bool tuc_init(uint8_t rhport, uint32_t port_type) {
+  // Initialize stack
+  if (!_usbc_inited) {
+    tu_memclr(_port_inited, sizeof(_port_inited));
+
+    _usbc_q = osal_queue_create(&_usbc_qdef);
+    TU_ASSERT(_usbc_q != NULL);
+
+    _usbc_inited = true;
+  }
+
+  // skip if port already initialized
+  if ( _port_inited[rhport] ) {
+    return true;
+  }
+
+  TU_LOG_USBC("USBC init on port %u\r\n", rhport);
+  TU_LOG_INT(USBC_DEBUG, sizeof(tcd_event_t));
+
+  TU_ASSERT(tcd_init(rhport, port_type));
+  tcd_int_enable(rhport);
+
+  _port_inited[rhport] = true;
+  return true;
+}
+
+void tuc_task_ext(uint32_t timeout_ms, bool in_isr) {
+  (void) in_isr; // not implemented yet
+
+  // Skip if stack is not initialized
+  if (!_usbc_inited) return;
+
+  // Loop until there is no more events in the queue
+  while (1) {
+    tcd_event_t event;
+    if (!osal_queue_receive(_usbc_q, &event, timeout_ms)) return;
+
+    switch (event.event_id) {
+      case TCD_EVENT_CC_CHANGED:
+        break;
+
+      case TCD_EVENT_RX_COMPLETE:
+        // TODO process message here in ISR, move to thread later
+        if (event.xfer_complete.result == XFER_RESULT_SUCCESS) {
+          pd_header_t const* header = (pd_header_t const*) _rx_buf;
+
+          if (header->n_data_obj == 0) {
+            parse_msg_control(event.rhport, header);
+
+          }else {
+            uint8_t const* p_end = _rx_buf + event.xfer_complete.xferred_bytes;
+            uint8_t const * dobj = _rx_buf + sizeof(pd_header_t);
+
+            parse_msg_data(event.rhport, header, dobj, p_end);
+          }
+        }
+
+        // prepare for next message
+        tcd_msg_receive(event.rhport, _rx_buf, sizeof(_rx_buf));
+        break;
+
+      case TCD_EVENT_TX_COMPLETE:
+        break;
+
+      default: break;
+    }
+  }
+}
+
+bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end) {
+  if (tuc_pd_data_received_cb) {
+    tuc_pd_data_received_cb(rhport, header, dobj, p_end);
+  }
+
+  return true;
+}
+
+bool parse_msg_control(uint8_t rhport, pd_header_t const* header) {
+  if (tuc_pd_control_received_cb) {
+    tuc_pd_control_received_cb(rhport, header);
+  }
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool usbc_msg_send(uint8_t rhport, pd_header_t const* header, void const* data) {
+  // copy header
+  memcpy(_tx_buf, header, sizeof(pd_header_t));
+
+  // copy data objcet if available
+  uint16_t const n_data_obj = header->n_data_obj;
+  if (n_data_obj > 0) {
+    memcpy(_tx_buf + sizeof(pd_header_t), data, n_data_obj * 4);
+  }
+
+  return tcd_msg_send(rhport, _tx_buf, sizeof(pd_header_t) + n_data_obj * 4);
+}
+
+bool tuc_msg_request(uint8_t rhport, void const* rdo) {
+  pd_header_t const header = {
+      .msg_type = PD_DATA_REQUEST,
+      .data_role = PD_DATA_ROLE_UFP,
+      .specs_rev = PD_REV_30,
+      .power_role = PD_POWER_ROLE_SINK,
+      .msg_id = 0,
+      .n_data_obj = 1,
+      .extended = 0,
+  };
+
+  return usbc_msg_send(rhport, &header, rdo);
+}
+
+void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
+  (void) in_isr;
+  switch(event->event_id) {
+    case TCD_EVENT_CC_CHANGED:
+      if (event->cc_changed.cc_state[0] || event->cc_changed.cc_state[1]) {
+        // Attach, start receiving
+        tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf));
+      }else {
+        // Detach
+      }
+      break;
+
+    default: break;
+  }
+
+  osal_queue_send(_usbc_q, event, in_isr);
+}
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+void usbc_int_set(bool enabled) {
+  // Disable all controllers since they shared the same event queue
+  for (uint8_t p = 0; p < TUP_TYPEC_RHPORTS_NUM; p++) {
+    if ( _port_inited[p] ) {
+      if (enabled) {
+        tcd_int_enable(p);
+      }else {
+        tcd_int_disable(p);
+      }
+    }
+  }
+}
+
+#endif
diff --git a/src/typec/usbc.h b/src/typec/usbc.h
new file mode 100644
index 000000000..9fbff9bc6
--- /dev/null
+++ b/src/typec/usbc.h
@@ -0,0 +1,91 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_UTCD_H_
+#define _TUSB_UTCD_H_
+
+#include "common/tusb_common.h"
+#include "pd_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// TypeC Configuration
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUC_TASK_QUEUE_SZ
+#define CFG_TUC_TASK_QUEUE_SZ   8
+#endif
+
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
+
+// Init typec stack on a port
+bool tuc_init(uint8_t rhport, uint32_t port_type);
+
+// Check if typec port is initialized
+bool tuc_inited(uint8_t rhport);
+
+// Task function should be called in main/rtos loop, extended version of tud_task()
+// - timeout_ms: millisecond to wait, zero = no wait, 0xFFFFFFFF = wait forever
+// - in_isr: if function is called in ISR
+void tuc_task_ext(uint32_t timeout_ms, bool in_isr);
+
+// Task function should be called in main/rtos loop
+TU_ATTR_ALWAYS_INLINE static inline
+void tuc_task (void) {
+  tuc_task_ext(UINT32_MAX, false);
+}
+
+#ifndef _TUSB_TCD_H_
+extern void tcd_int_handler(uint8_t rhport);
+#endif
+
+// Interrupt handler, name alias to TCD
+#define tuc_int_handler tcd_int_handler
+
+//--------------------------------------------------------------------+
+// Callbacks
+//--------------------------------------------------------------------+
+
+TU_ATTR_WEAK bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end);
+TU_ATTR_WEAK bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header);
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tuc_msg_request(uint8_t rhport, void const* rdo);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc
new file mode 100644
index 000000000..046a90555
--- /dev/null
+++ b/test/fuzz/dcd_fuzz.cc
@@ -0,0 +1,209 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+#include "device/dcd.h"
+#include "fuzz/fuzz_private.h"
+#include <assert.h>
+#include <cstdint>
+#include <limits>
+
+#define UNUSED(x) (void)(x)
+
+//--------------------------------------------------------------------+
+// State tracker
+//--------------------------------------------------------------------+
+struct State {
+  bool interrupts_enabled;
+  bool sof_enabled;
+  uint8_t address;
+};
+
+tu_static State state = {false, 0, 0};
+
+//--------------------------------------------------------------------+
+// Controller API
+// All no-ops as we are fuzzing.
+//--------------------------------------------------------------------+
+extern "C" {
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+  UNUSED(rhport);
+  UNUSED(rh_init);
+  return true;
+}
+
+void dcd_int_handler(uint8_t rhport) {
+  assert(_fuzz_data_provider.has_value());
+
+  if (!state.interrupts_enabled) {
+    return;
+  }
+
+  // Choose if we want to generate a signal based on the fuzzed data.
+  if (_fuzz_data_provider->ConsumeBool()) {
+    dcd_event_bus_signal(
+        rhport,
+        // Choose a random event based on the fuzz data.
+        (dcd_eventid_t)_fuzz_data_provider->ConsumeIntegralInRange<uint8_t>(
+            DCD_EVENT_INVALID + 1, DCD_EVENT_COUNT - 1),
+        // Identify trigger as either an interrupt or a syncrhonous call
+        // depending on fuzz data.
+        _fuzz_data_provider->ConsumeBool());
+  }
+
+  if (_fuzz_data_provider->ConsumeBool()) {
+    constexpr size_t kSetupFrameLength = 8;
+    std::vector<uint8_t> setup =
+        _fuzz_data_provider->ConsumeBytes<uint8_t>(kSetupFrameLength);
+    // Fuzz consumer may return less than requested. If this is the case
+    // we want to make sure that at least that length is allocated and available
+    // to the signal handler.
+    if (setup.size() != kSetupFrameLength) {
+      setup.resize(kSetupFrameLength);
+    }
+    dcd_event_setup_received(rhport, setup.data(),
+                             // Identify trigger as either an interrupt or a
+                             // syncrhonous call depending on fuzz data.
+                             _fuzz_data_provider->ConsumeBool());
+  }
+}
+
+void dcd_int_enable(uint8_t rhport) {
+  state.interrupts_enabled = true;
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_int_disable(uint8_t rhport) {
+  state.interrupts_enabled = false;
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  UNUSED(rhport);
+  state.address = dev_addr;
+  // Respond with status.
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  return;
+}
+
+void dcd_remote_wakeup(uint8_t rhport) {
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_connect(uint8_t rhport) {
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_disconnect(uint8_t rhport) {
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en) {
+  state.sof_enabled = en;
+  UNUSED(rhport);
+  return;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
+  UNUSED(rhport);
+  UNUSED(desc_ep);
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// Close all non-control endpoints, cancel all pending transfers if any.
+// Invoked when switching from a non-zero Configuration by SET_CONFIGURE
+// therefore required for multiple configuration support.
+void dcd_edpt_close_all(uint8_t rhport) {
+  UNUSED(rhport);
+  return;
+}
+
+// Close an endpoint.
+// Since it is weak, caller must TU_ASSERT this function's existence before
+// calling it.
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  UNUSED(rhport);
+  UNUSED(ep_addr);
+  return;
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to
+// notify the stack
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer,
+                   uint16_t total_bytes) {
+  UNUSED(rhport);
+  UNUSED(buffer);
+  UNUSED(total_bytes);
+
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
+  if (dir == TUSB_DIR_IN) {
+    std::vector<uint8_t> temp =
+        _fuzz_data_provider->ConsumeBytes<uint8_t>(total_bytes);
+    std::copy(temp.begin(), temp.end(), buffer);
+  }
+  // Ignore output data as it's not useful for fuzzing without a more
+  // complex fuzzed backend. But we need to make sure it's not
+  // optimised out.
+  volatile uint8_t *dont_optimise0 = buffer;
+  volatile uint16_t dont_optimise1 = total_bytes;
+  UNUSED(dont_optimise0);
+  UNUSED(dont_optimise1);
+
+
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+/* TODO: implement a fuzzed version of this.
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff,
+                        uint16_t total_bytes) {}
+*/
+
+// Stall endpoint, any queuing transfer should be removed from endpoint
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+
+  UNUSED(rhport);
+  UNUSED(ep_addr);
+  return;
+}
+
+// clear stall, data toggle is also reset to DATA0
+// This API never calls with control endpoints, since it is auto cleared when
+// receiving setup packet
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+
+  UNUSED(rhport);
+  UNUSED(ep_addr);
+  return;
+}
+}
diff --git a/test/fuzz/device/cdc/CMakeLists.txt b/test/fuzz/device/cdc/CMakeLists.txt
new file mode 100644
index 000000000..c60f292b9
--- /dev/null
+++ b/test/fuzz/device/cdc/CMakeLists.txt
@@ -0,0 +1,29 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/test/fuzz/device/cdc/Makefile b/test/fuzz/device/cdc/Makefile
new file mode 100644
index 000000000..7071df057
--- /dev/null
+++ b/test/fuzz/device/cdc/Makefile
@@ -0,0 +1,11 @@
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.c))
+SRC_CXX += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.cc))
+
+include ../../rules.mk
diff --git a/test/fuzz/device/cdc/cdc_seed_corpus.zip b/test/fuzz/device/cdc/cdc_seed_corpus.zip
new file mode 100644
index 000000000..81bc2240d
Binary files /dev/null and b/test/fuzz/device/cdc/cdc_seed_corpus.zip differ
diff --git a/test/fuzz/device/cdc/src/fuzz.cc b/test/fuzz/device/cdc/src/fuzz.cc
new file mode 100644
index 000000000..0560e8621
--- /dev/null
+++ b/test/fuzz/device/cdc/src/fuzz.cc
@@ -0,0 +1,174 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <cassert>
+#include <fuzzer/FuzzedDataProvider.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "class/cdc/cdc_device.h"
+#include "fuzz/fuzz.h"
+#include "tusb.h"
+#include <cstdint>
+#include <string>
+#include <vector>
+
+extern "C" {
+
+#define FUZZ_ITERATIONS 500
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+void cdc_task(FuzzedDataProvider *provider);
+
+extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
+  FuzzedDataProvider provider(Data, Size);
+  std::vector<uint8_t> callback_data = provider.ConsumeBytes<uint8_t>(
+      provider.ConsumeIntegralInRange<size_t>(0, Size));
+  fuzz_init(callback_data.data(), callback_data.size());
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
+
+  for (int i = 0; i < FUZZ_ITERATIONS; i++) {
+    if (provider.remaining_bytes() == 0) {
+      return 0;
+    }
+    tud_int_handler(provider.ConsumeIntegral<uint8_t>());
+    tud_task(); // tinyusb device task
+    cdc_task(&provider);
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// USB CDC
+//--------------------------------------------------------------------+
+enum CdcApiFuncs {
+  kCdcNConnected,
+  kCdcNGetLineState,
+  kCdcNGetLineCoding,
+  kCdcNSetWantedChar,
+  kCdcNAvailable,
+  kCdcNRead,
+  kCdcNReadChar,
+  kCdcNReadFlush,
+  kCdcNPeek,
+  kCdcNWrite,
+  kCdcNWriteChar,
+  kCdcNWriteStr,
+  kCdcNWriteFlush,
+  kCdcNWriteAvailable,
+  kCdcNWriteClear,
+  // We don't need to fuzz tud_cdc_<not n>* as they are just wrappers
+  // calling with n==0.
+  kMaxValue,
+};
+
+void cdc_task(FuzzedDataProvider *provider) {
+
+  assert(provider != NULL);
+  const int kMaxBufferSize = 4096;
+  switch (provider->ConsumeEnum<CdcApiFuncs>()) {
+  case kCdcNConnected:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_connected(0);
+    break;
+  case kCdcNGetLineState:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_get_line_state(0);
+    break;
+  case kCdcNGetLineCoding: {
+    cdc_line_coding_t coding;
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_get_line_coding(0, &coding);
+  } break;
+  case kCdcNSetWantedChar:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_set_wanted_char(0, provider->ConsumeIntegral<char>());
+    break;
+  case kCdcNAvailable:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_available(0);
+    break;
+  case kCdcNRead: {
+    std::vector<uint8_t> buffer;
+    buffer.resize(provider->ConsumeIntegralInRange<size_t>(0, kMaxBufferSize));
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_read(0, buffer.data(), buffer.size());
+    break;
+  }
+  case kCdcNReadChar:
+    // TODO: Fuzz interface number
+    tud_cdc_n_read_char(0);
+    break;
+  case kCdcNReadFlush:
+    // TODO: Fuzz interface number
+    tud_cdc_n_read_flush(0);
+    break;
+  case kCdcNPeek: {
+    uint8_t peak = 0;
+    tud_cdc_n_peek(0, &peak);
+    break;
+  }
+  case kCdcNWrite: {
+    std::vector<uint8_t> buffer = provider->ConsumeBytes<uint8_t>(
+        provider->ConsumeIntegralInRange<size_t>(0, kMaxBufferSize));
+
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_write(0, buffer.data(), buffer.size());
+  } break;
+
+case kCdcNWriteChar:
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_char(0, provider->ConsumeIntegral<char>());
+  break;
+case kCdcNWriteStr: {
+  std::string str = provider->ConsumeRandomLengthString(kMaxBufferSize);
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_str(0, str.c_str());
+  break;
+}
+case kCdcNWriteFlush:
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_flush(0);
+  break;
+case kCdcNWriteAvailable:
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_available(0);
+  break;
+case kCdcNWriteClear:
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_clear(0);
+  break;
+case kMaxValue:
+  // Noop.
+  break;
+}
+}
+}
diff --git a/test/fuzz/device/cdc/src/tusb_config.h b/test/fuzz/device/cdc/src/tusb_config.h
new file mode 100644
index 000000000..10a8a825a
--- /dev/null
+++ b/test/fuzz/device/cdc/src/tusb_config.h
@@ -0,0 +1,114 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN    __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC              1
+#define CFG_TUD_MSC              0
+#define CFG_TUD_HID              0
+#define CFG_TUD_MIDI             0
+#define CFG_TUD_VENDOR           0
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// MSC Buffer size of Device Mass storage
+#define CFG_TUD_MSC_EP_BUFSIZE   512
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/test/fuzz/device/cdc/src/usb_descriptors.cc b/test/fuzz/device/cdc/src/usb_descriptors.cc
new file mode 100644
index 000000000..0f636f05d
--- /dev/null
+++ b/test/fuzz/device/cdc/src/usb_descriptors.cc
@@ -0,0 +1,229 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save
+ * device driver after the first plug.
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n))
+#define USB_PID                                                                \
+  (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(HID, 2) | _PID_MAP(MIDI, 3) |          \
+   _PID_MAP(VENDOR, 4))
+
+#define USB_VID 0xCafe
+#define USB_BCD 0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const *tud_descriptor_device_cb(void) {
+  static tusb_desc_device_t const desc_device = {
+      .bLength = sizeof(tusb_desc_device_t),
+      .bDescriptorType = TUSB_DESC_DEVICE,
+      .bcdUSB = USB_BCD,
+
+      // Use Interface Association Descriptor (IAD) for CDC
+      // As required by USB Specs IAD's subclass must be common class (2) and
+      // protocol must be IAD (1)
+      .bDeviceClass = TUSB_CLASS_MISC,
+      .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+      .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+      .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+      .idVendor = USB_VID,
+      .idProduct = USB_PID,
+      .bcdDevice = 0x0100,
+
+      .iManufacturer = 0x01,
+      .iProduct = 0x02,
+      .iSerialNumber = 0x03,
+
+      .bNumConfigurations = 0x01};
+
+  return (uint8_t const *)&desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum { ITF_NUM_CDC = 0, ITF_NUM_CDC_DATA, ITF_NUM_TOTAL };
+
+#define EPNUM_CDC_NOTIF 0x81
+#define EPNUM_CDC_OUT 0x02
+#define EPNUM_CDC_IN 0x82
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+
+// full speed configuration
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP notification address and size, EP data
+    // address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT,
+                       EPNUM_CDC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and
+// other_speed_configuration
+
+// high speed configuration
+uint8_t const desc_hs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP notification address and size, EP data
+    // address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT,
+                       EPNUM_CDC_IN, 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change
+// configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength = sizeof(tusb_desc_device_qualifier_t),
+    .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
+    .bcdUSB = USB_BCD,
+
+    .bDeviceClass = TUSB_CLASS_MISC,
+    .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved = 0x00};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete. device_qualifier descriptor describes
+// information about a high-speed capable device that would change if the device
+// were operating at the other speed. If not highspeed capable stall this
+// request.
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const *)&desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete Configuration descriptor in the other speed
+// e.g if high speed then this is for full speed and vice versa
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration
+                                              : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration
+                                              : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] = {
+    (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                  // 1: Manufacturer
+    "TinyUSB Device",           // 2: Product
+    "123456789012",             // 3: Serials, should use chip ID
+    "TinyUSB CDC",              // 4: CDC Interface
+};
+
+static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void)langid;
+
+  uint8_t chr_count;
+
+  if (index == 0) {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  } else {
+    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+    if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])))
+      return NULL;
+
+    const char *str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = (uint8_t)strlen(str);
+    if (chr_count > 31)
+      chr_count = 31;
+
+    // Convert ASCII string into UTF-16
+    for (uint8_t i = 0; i < chr_count; i++) {
+      _desc_str[1 + i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/test/fuzz/device/msc/CMakeLists.txt b/test/fuzz/device/msc/CMakeLists.txt
new file mode 100644
index 000000000..8bff217cb
--- /dev/null
+++ b/test/fuzz/device/msc/CMakeLists.txt
@@ -0,0 +1,29 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/test/fuzz/device/msc/Makefile b/test/fuzz/device/msc/Makefile
new file mode 100644
index 000000000..7071df057
--- /dev/null
+++ b/test/fuzz/device/msc/Makefile
@@ -0,0 +1,11 @@
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.c))
+SRC_CXX += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.cc))
+
+include ../../rules.mk
diff --git a/test/fuzz/device/msc/msc_seed_corpus.zip b/test/fuzz/device/msc/msc_seed_corpus.zip
new file mode 100644
index 000000000..81bc2240d
Binary files /dev/null and b/test/fuzz/device/msc/msc_seed_corpus.zip differ
diff --git a/test/fuzz/device/msc/src/fuzz.cc b/test/fuzz/device/msc/src/fuzz.cc
new file mode 100644
index 000000000..371d49882
--- /dev/null
+++ b/test/fuzz/device/msc/src/fuzz.cc
@@ -0,0 +1,61 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <cassert>
+#include <fuzzer/FuzzedDataProvider.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "class/cdc/cdc_device.h"
+#include "fuzz/fuzz.h"
+#include "tusb.h"
+#include <cstdint>
+#include <string>
+#include <vector>
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+#define FUZZ_ITERATIONS 500
+
+extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
+  FuzzedDataProvider provider(Data, Size);
+  std::vector<uint8_t> callback_data = provider.ConsumeBytes<uint8_t>(
+      provider.ConsumeIntegralInRange<size_t>(0, Size));
+  fuzz_init(callback_data.data(), callback_data.size());
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
+
+  for (int i = 0; i < FUZZ_ITERATIONS; i++) {
+    if (provider.remaining_bytes() == 0) {
+      return 0;
+    }
+    tud_int_handler(provider.ConsumeIntegral<uint8_t>());
+    tud_task(); // tinyusb device task
+  }
+
+  return 0;
+}
diff --git a/test/fuzz/device/msc/src/tusb_config.h b/test/fuzz/device/msc/src/tusb_config.h
new file mode 100644
index 000000000..ca39c6b0a
--- /dev/null
+++ b/test/fuzz/device/msc/src/tusb_config.h
@@ -0,0 +1,114 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN    __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC              0
+#define CFG_TUD_MSC              1
+#define CFG_TUD_HID              0
+#define CFG_TUD_MIDI             0
+#define CFG_TUD_VENDOR           0
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// MSC Buffer size of Device Mass storage
+#define CFG_TUD_MSC_EP_BUFSIZE   512
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/test/fuzz/device/msc/src/usb_descriptors.cc b/test/fuzz/device/msc/src/usb_descriptors.cc
new file mode 100644
index 000000000..efe4d0a3c
--- /dev/null
+++ b/test/fuzz/device/msc/src/usb_descriptors.cc
@@ -0,0 +1,224 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save
+ * device driver after the first plug.
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n))
+#define USB_PID                                                                \
+  (0x4000 | _PID_MAP(MSC, 0) | _PID_MAP(HID, 1) | _PID_MAP(MIDI, 2) |          \
+   _PID_MAP(VENDOR, 3))
+#define USB_VID 0xCafe
+#define USB_BCD 0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const *tud_descriptor_device_cb(void) {
+  tu_static tusb_desc_device_t const desc_device = {
+      .bLength = sizeof(tusb_desc_device_t),
+      .bDescriptorType = TUSB_DESC_DEVICE,
+      .bcdUSB = USB_BCD,
+
+      // Use Interface Association Descriptor (IAD) for CDC
+      // As required by USB Specs IAD's subclass must be common class (2) and
+      // protocol must be IAD (1)
+      .bDeviceClass = TUSB_CLASS_MISC,
+      .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+      .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+      .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+      .idVendor = USB_VID,
+      .idProduct = USB_PID,
+      .bcdDevice = 0x0100,
+
+      .iManufacturer = 0x01,
+      .iProduct = 0x02,
+      .iSerialNumber = 0x03,
+
+      .bNumConfigurations = 0x01};
+
+  return (uint8_t const *)&desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum { ITF_NUM_MSC = 0, ITF_NUM_TOTAL };
+
+#define EPNUM_MSC_OUT 0x05
+#define EPNUM_MSC_IN 0x85
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_MSC_DESC_LEN)
+
+// full speed configuration
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 4, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and
+// other_speed_configuration
+
+// high speed configuration
+uint8_t const desc_hs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 4, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change
+// configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength = sizeof(tusb_desc_device_qualifier_t),
+    .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
+    .bcdUSB = USB_BCD,
+
+    .bDeviceClass = TUSB_CLASS_MISC,
+    .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved = 0x00};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete. device_qualifier descriptor describes
+// information about a high-speed capable device that would change if the device
+// were operating at the other speed. If not highspeed capable stall this
+// request.
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const *)&desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete Configuration descriptor in the other speed
+// e.g if high speed then this is for full speed and vice versa
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration
+                                              : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration
+                                              : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] = {
+    (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                  // 1: Manufacturer
+    "TinyUSB Device",           // 2: Product
+    "123456789012",             // 3: Serials, should use chip ID
+    "TinyUSB MSC",              // 4: MSC Interface
+
+};
+
+tu_static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void)langid;
+
+  uint8_t chr_count;
+
+  if (index == 0) {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  } else {
+    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+    if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])))
+      return NULL;
+
+    const char *str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = (uint8_t)strlen(str);
+    if (chr_count > 31)
+      chr_count = 31;
+
+    // Convert ASCII string into UTF-16
+    for (uint8_t i = 0; i < chr_count; i++) {
+      _desc_str[1 + i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/test/fuzz/device/net/CMakeLists.txt b/test/fuzz/device/net/CMakeLists.txt
new file mode 100644
index 000000000..8bff217cb
--- /dev/null
+++ b/test/fuzz/device/net/CMakeLists.txt
@@ -0,0 +1,29 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/test/fuzz/device/net/Makefile b/test/fuzz/device/net/Makefile
new file mode 100644
index 000000000..4e99604ad
--- /dev/null
+++ b/test/fuzz/device/net/Makefile
@@ -0,0 +1,70 @@
+DEPS_SUBMODULES += lib/lwip
+
+include ../../make.mk
+
+# suppress warning caused by lwip
+CFLAGS += \
+  -Wno-error=null-dereference \
+  -Wno-error=unused-parameter \
+  -Wno-error=unused-variable
+
+INC += \
+  src \
+  $(TOP)/hw \
+  $(TOP)/lib/lwip/src/include \
+  $(TOP)/lib/lwip/src/include/ipv4 \
+  $(TOP)/lib/lwip/src/include/lwip/apps \
+  $(TOP)/lib/networking
+
+# Example source
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.c))
+SRC_CXX += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.cc))
+
+# lwip sources
+SRC_C += \
+  lib/lwip/src/core/altcp.c \
+  lib/lwip/src/core/altcp_alloc.c \
+  lib/lwip/src/core/altcp_tcp.c \
+  lib/lwip/src/core/def.c \
+  lib/lwip/src/core/dns.c \
+  lib/lwip/src/core/inet_chksum.c \
+  lib/lwip/src/core/init.c \
+  lib/lwip/src/core/ip.c \
+  lib/lwip/src/core/mem.c \
+  lib/lwip/src/core/memp.c \
+  lib/lwip/src/core/netif.c \
+  lib/lwip/src/core/pbuf.c \
+  lib/lwip/src/core/raw.c \
+  lib/lwip/src/core/stats.c \
+  lib/lwip/src/core/sys.c \
+  lib/lwip/src/core/tcp.c \
+  lib/lwip/src/core/tcp_in.c \
+  lib/lwip/src/core/tcp_out.c \
+  lib/lwip/src/core/timeouts.c \
+  lib/lwip/src/core/udp.c \
+  lib/lwip/src/core/ipv4/autoip.c \
+  lib/lwip/src/core/ipv4/dhcp.c \
+  lib/lwip/src/core/ipv4/etharp.c \
+  lib/lwip/src/core/ipv4/icmp.c \
+  lib/lwip/src/core/ipv4/igmp.c \
+  lib/lwip/src/core/ipv4/ip4.c \
+  lib/lwip/src/core/ipv4/ip4_addr.c \
+  lib/lwip/src/core/ipv4/ip4_frag.c \
+  lib/lwip/src/core/ipv6/dhcp6.c \
+  lib/lwip/src/core/ipv6/ethip6.c \
+  lib/lwip/src/core/ipv6/icmp6.c \
+  lib/lwip/src/core/ipv6/inet6.c \
+  lib/lwip/src/core/ipv6/ip6.c \
+  lib/lwip/src/core/ipv6/ip6_addr.c \
+  lib/lwip/src/core/ipv6/ip6_frag.c \
+  lib/lwip/src/core/ipv6/mld6.c \
+  lib/lwip/src/core/ipv6/nd6.c \
+  lib/lwip/src/netif/ethernet.c \
+  lib/lwip/src/netif/slipif.c \
+  lib/lwip/src/apps/http/httpd.c \
+  lib/lwip/src/apps/http/fs.c \
+  lib/networking/dhserver.c \
+  lib/networking/dnserver.c \
+  lib/networking/rndis_reports.c
+
+include ../../rules.mk
diff --git a/test/fuzz/device/net/src/arch/cc.h b/test/fuzz/device/net/src/arch/cc.h
new file mode 100644
index 000000000..9f30b91cb
--- /dev/null
+++ b/test/fuzz/device/net/src/arch/cc.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __CC_H__
+#define __CC_H__
+
+//#include "cpu.h"
+
+typedef int sys_prot_t;
+
+
+
+/* define compiler specific symbols */
+#if defined (__ICCARM__)
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+#define PACK_STRUCT_USE_INCLUDES
+
+#elif defined (__CC_ARM)
+
+#define PACK_STRUCT_BEGIN __packed
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#elif defined (__GNUC__)
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#elif defined (__TASKING__)
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#endif
+
+#define LWIP_PLATFORM_ASSERT(x) do { if(!(x)) while(1); } while(0)
+
+#endif /* __CC_H__ */
diff --git a/test/fuzz/device/net/src/fuzz.cc b/test/fuzz/device/net/src/fuzz.cc
new file mode 100644
index 000000000..a6935928a
--- /dev/null
+++ b/test/fuzz/device/net/src/fuzz.cc
@@ -0,0 +1,99 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <cassert>
+#include <fuzzer/FuzzedDataProvider.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "class/cdc/cdc_device.h"
+#include "class/net/net_device.h"
+#include "fuzz/fuzz.h"
+#include "tusb.h"
+#include <cstdint>
+#include <string>
+#include <vector>
+
+extern "C" {
+
+#define FUZZ_ITERATIONS 500
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+void net_task(FuzzedDataProvider *provider);
+
+extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
+  FuzzedDataProvider provider(Data, Size);
+  std::vector<uint8_t> callback_data = provider.ConsumeBytes<uint8_t>(
+      provider.ConsumeIntegralInRange<size_t>(0, Size));
+  fuzz_init(callback_data.data(), callback_data.size());
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
+
+  for (int i = 0; i < FUZZ_ITERATIONS; i++) {
+    if (provider.remaining_bytes() == 0) {
+      return 0;
+    }
+    tud_int_handler(provider.ConsumeIntegral<uint8_t>());
+    tud_task(); // tinyusb device task
+    net_task(&provider);
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// USB CDC
+//--------------------------------------------------------------------+
+enum NetApiFuncs {
+  kNetworkRecvRenew,
+  kNetworkCanXmit,
+  kNetworkXmit,
+  kMaxValue,
+};
+
+void net_task(FuzzedDataProvider *provider) {
+
+  assert(provider != NULL);
+  switch (provider->ConsumeEnum<NetApiFuncs>()) {
+
+  case kNetworkRecvRenew:
+    tud_network_recv_renew();
+    break;
+  case kNetworkCanXmit:
+ (void)tud_network_can_xmit(provider->ConsumeIntegral<uint16_t>());
+  case kNetworkXmit:
+    // TODO: Actually pass real values here later.
+    tud_network_xmit(NULL, 0);
+
+  case kMaxValue:
+    // Noop.
+    break;
+  }
+}
+}
diff --git a/test/fuzz/device/net/src/lwipopts.h b/test/fuzz/device/net/src/lwipopts.h
new file mode 100644
index 000000000..336c9243d
--- /dev/null
+++ b/test/fuzz/device/net/src/lwipopts.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+/* Prevent having to link sys_arch.c (we don't test the API layers in unit tests) */
+#define NO_SYS                          1
+#define MEM_ALIGNMENT                   4
+#define LWIP_RAW                        0
+#define LWIP_NETCONN                    0
+#define LWIP_SOCKET                     0
+#define LWIP_DHCP                       0
+#define LWIP_ICMP                       1
+#define LWIP_UDP                        1
+#define LWIP_TCP                        1
+#define LWIP_IPV4                       1
+#define LWIP_IPV6                       0
+#define ETH_PAD_SIZE                    0
+#define LWIP_IP_ACCEPT_UDP_PORT(p)      ((p) == PP_NTOHS(67))
+
+#define TCP_MSS                         (1500 /*mtu*/ - 20 /*iphdr*/ - 20 /*tcphhr*/)
+#define TCP_SND_BUF                     (2 * TCP_MSS)
+#define TCP_WND                         (TCP_MSS)
+
+#define ETHARP_SUPPORT_STATIC_ENTRIES   1
+
+#define LWIP_HTTPD_CGI                  0
+#define LWIP_HTTPD_SSI                  0
+#define LWIP_HTTPD_SSI_INCLUDE_TAG      0
+
+#define LWIP_SINGLE_NETIF               1
+
+#define PBUF_POOL_SIZE                  2
+
+#define HTTPD_USE_CUSTOM_FSDATA         0
+
+#define LWIP_MULTICAST_PING             1
+#define LWIP_BROADCAST_PING             1
+#define LWIP_IPV6_MLD                   0
+#define LWIP_IPV6_SEND_ROUTER_SOLICIT   0
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/test/fuzz/device/net/src/tusb_config.h b/test/fuzz/device/net/src/tusb_config.h
new file mode 100644
index 000000000..6ad859337
--- /dev/null
+++ b/test/fuzz/device/net/src/tusb_config.h
@@ -0,0 +1,122 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN    __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC              1
+#define CFG_TUD_MSC              0
+#define CFG_TUD_HID              0
+#define CFG_TUD_MIDI             0
+#define CFG_TUD_VENDOR           0
+
+// Network class has 2 drivers: ECM/RNDIS and NCM.
+// Only one of the drivers can be enabled
+#define CFG_TUD_ECM_RNDIS     1
+#define CFG_TUD_NCM           (1-CFG_TUD_ECM_RNDIS)
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// MSC Buffer size of Device Mass storage
+#define CFG_TUD_MSC_EP_BUFSIZE   512
+
+
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/test/fuzz/device/net/src/usb_descriptors.cc b/test/fuzz/device/net/src/usb_descriptors.cc
new file mode 100644
index 000000000..5597d49d5
--- /dev/null
+++ b/test/fuzz/device/net/src/usb_descriptors.cc
@@ -0,0 +1,229 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save
+ * device driver after the first plug.
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n))
+#define USB_PID                                                                \
+  (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(HID, 2) | _PID_MAP(MIDI, 3) |          \
+   _PID_MAP(VENDOR, 4))
+
+#define USB_VID 0xCafe
+#define USB_BCD 0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const *tud_descriptor_device_cb(void) {
+  tu_static tusb_desc_device_t const desc_device = {
+      .bLength = sizeof(tusb_desc_device_t),
+      .bDescriptorType = TUSB_DESC_DEVICE,
+      .bcdUSB = USB_BCD,
+
+      // Use Interface Association Descriptor (IAD) for CDC
+      // As required by USB Specs IAD's subclass must be common class (2) and
+      // protocol must be IAD (1)
+      .bDeviceClass = TUSB_CLASS_MISC,
+      .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+      .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+      .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+      .idVendor = USB_VID,
+      .idProduct = USB_PID,
+      .bcdDevice = 0x0100,
+
+      .iManufacturer = 0x01,
+      .iProduct = 0x02,
+      .iSerialNumber = 0x03,
+
+      .bNumConfigurations = 0x01};
+
+  return (uint8_t const *)&desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum { ITF_NUM_CDC = 0, ITF_NUM_CDC_DATA, ITF_NUM_TOTAL };
+
+#define EPNUM_CDC_NOTIF 0x81
+#define EPNUM_CDC_OUT 0x02
+#define EPNUM_CDC_IN 0x82
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+
+// full speed configuration
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP notification address and size, EP data
+    // address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT,
+                       EPNUM_CDC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and
+// other_speed_configuration
+
+// high speed configuration
+uint8_t const desc_hs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP notification address and size, EP data
+    // address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT,
+                       EPNUM_CDC_IN, 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change
+// configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength = sizeof(tusb_desc_device_qualifier_t),
+    .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
+    .bcdUSB = USB_BCD,
+
+    .bDeviceClass = TUSB_CLASS_MISC,
+    .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved = 0x00};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete. device_qualifier descriptor describes
+// information about a high-speed capable device that would change if the device
+// were operating at the other speed. If not highspeed capable stall this
+// request.
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const *)&desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete Configuration descriptor in the other speed
+// e.g if high speed then this is for full speed and vice versa
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration
+                                              : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration
+                                              : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] = {
+    (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                  // 1: Manufacturer
+    "TinyUSB Device",           // 2: Product
+    "123456789012",             // 3: Serials, should use chip ID
+    "TinyUSB CDC",              // 4: CDC Interface
+};
+
+tu_static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void)langid;
+
+  uint8_t chr_count;
+
+  if (index == 0) {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  } else {
+    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+    if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])))
+      return NULL;
+
+    const char *str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = (uint8_t)strlen(str);
+    if (chr_count > 31)
+      chr_count = 31;
+
+    // Convert ASCII string into UTF-16
+    for (uint8_t i = 0; i < chr_count; i++) {
+      _desc_str[1 + i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/test/fuzz/dicts/cdc.dict b/test/fuzz/dicts/cdc.dict
new file mode 100644
index 000000000..421eb8ed9
--- /dev/null
+++ b/test/fuzz/dicts/cdc.dict
@@ -0,0 +1,73 @@
+# List of supported OIDs
+RNDIS_OID_GEN_SUPPORTED_LIST="\x00\x01\x01\x01"
+# Hardware status
+RNDIS_OID_GEN_HARDWARE_STATUS="\x00\x01\x01\x02"
+# Media types supported (encoded)
+RNDIS_OID_GEN_MEDIA_SUPPORTED="\x00\x01\x01\x03"
+# Media types in use (encoded)
+RNDIS_OID_GEN_MEDIA_IN_USE="\x00\x01\x01\x04"
+RNDIS_OID_GEN_MAXIMUM_LOOKAHEAD="\x00\x01\x01\x05"
+# Maximum frame size in bytes
+RNDIS_OID_GEN_MAXIMUM_FRAME_SIZE="\x00\x01\x01\x06"
+# Link speed in units of 100 bps
+RNDIS_OID_GEN_LINK_SPEED="\x00\x01\x01\x07"
+# Transmit buffer space
+RNDIS_OID_GEN_TRANSMIT_BUFFER_SPACE="\x00\x01\x01\x08"
+# Receive buffer space
+RNDIS_OID_GEN_RECEIVE_BUFFER_SPACE="\x00\x01\x01\x09"
+# NDIS version number used by the driver
+RNDIS_OID_GEN_DRIVER_VERSION="\x00\x01\x01\x10"
+# Maximum total packet length in bytes
+RNDIS_OID_GEN_MAXIMUM_TOTAL_SIZE="\x00\x01\x01\x11"
+# Optional protocol flags (encoded)
+RNDIS_OID_GEN_PROTOCOL_OPTIONS="\x00\x01\x01\x12"
+# Optional NIC flags (encoded)
+RNDIS_OID_GEN_MAC_OPTIONS="\x00\x01\x01\x13"
+# Whether the NIC is connected to the network
+RNDIS_OID_GEN_MEDIA_CONNECT_STATUS="\x00\x01\x01\x14"
+# The maximum number of send packets the driver can accept per call to its MiniportSendPacketsfunction
+RNDIS_OID_GEN_MAXIMUM_SEND_PACKETS="\x00\x01\x01\x15"
+# Vendor-assigned version number of the driver
+RNDIS_OID_GEN_VENDOR_DRIVER_VERSION="\x00\x01\x01\x16"
+# The custom GUIDs (Globally Unique Identifier) supported by the miniport driver
+RNDIS_OID_GEN_SUPPORTED_GUIDS="\x00\x01\x01\x17"
+# List of network-layer addresses associated with the binding between a transport and the driver
+RNDIS_OID_GEN_NETWORK_LAYER_ADDRESSES="\x00\x01\x01\x18"
+# Size of packets' additional headers
+RNDIS_OID_GEN_TRANSPORT_HEADER_OFFSET="\x00\x01\x01\x19"
+RNDIS_OID_GEN_MEDIA_CAPABILITIES="\x00\x01\x02\x01"
+# Physical media supported by the miniport driver (encoded)
+RNDIS_OID_GEN_PHYSICAL_MEDIUM="\x00\x01\x02\x02"
+# Permanent station address
+RNDIS_OID_802_3_PERMANENT_ADDRESS="\x01\x01\x01\x01"
+# Current station address
+RNDIS_OID_802_3_CURRENT_ADDRESS="\x01\x01\x01\x02"
+# Current multicast address list
+RNDIS_OID_802_3_MULTICAST_LIST="\x01\x01\x01\x03"
+# Maximum size of multicast address list
+RNDIS_OID_802_3_MAXIMUM_LIST_SIZE="\x01\x01\x01\x04"
+# Directed packets. Directed packets contain a destination address equal to the station address of the NIC.
+RNDIS_PACKET_TYPE_DIRECTED="\x00\x00\x00\x01"
+# Multicast address packets sent to addresses in the multicast address list.
+RNDIS_PACKET_TYPE_MULTICAST="\x00\x00\x00\x02"
+# All multicast address packets, not just the ones enumerated in the multicast address list.
+RNDIS_PACKET_TYPE_ALL_MULTICAST="\x00\x00\x00\x04"
+# Broadcast packets.
+RNDIS_PACKET_TYPE_BROADCAST="\x00\x00\x00\x08"
+# All source routing packets. If the protocol driver sets this bit, the NDIS library attempts to act as a source routing bridge.
+RNDIS_PACKET_TYPE_SOURCE_ROUTING="\x00\x00\x00\x10"
+# Specifies all packets regardless of whether VLAN filtering is enabled or not and whether the VLAN identifier matches or not.
+RNDIS_PACKET_TYPE_PROMISCUOUS="\x00\x00\x00\x20"
+# SMT packets that an FDDI NIC receives.
+RNDIS_PACKET_TYPE_SMT="\x00\x00\x00\x40"
+# All packets sent by installed protocols and all packets indicated by the NIC that is identified by a given NdisBindingHandle.
+RNDIS_PACKET_TYPE_ALL_LOCAL="\x00\x00\x00\x80"
+# Packets sent to the current group address.
+RNDIS_PACKET_TYPE_GROUP="\x00\x00\x10\x00"
+# All functional address packets, not just the ones in the current functional address.
+RNDIS_PACKET_TYPE_ALL_FUNCTIONAL="\x00\x00\x20\x00"
+# Functional address packets sent to addresses included in the current functional address.
+RNDIS_PACKET_TYPE_FUNCTIONAL="\x00\x00\x40\x00"
+# NIC driver frames that a Token Ring NIC receives.
+RNDIS_PACKET_TYPE_MAC_FRAME="\x00\x00\x80\x00"
+RNDIS_PACKET_TYPE_NO_LOCAL="\x00\x01\x00\x00"
diff --git a/test/fuzz/fuzz.cc b/test/fuzz/fuzz.cc
new file mode 100644
index 000000000..2e4186f1a
--- /dev/null
+++ b/test/fuzz/fuzz.cc
@@ -0,0 +1,34 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "fuzzer/FuzzedDataProvider.h"
+#include <optional>
+
+std::optional<FuzzedDataProvider> _fuzz_data_provider;
+
+extern "C" int fuzz_init(const uint8_t *data, size_t size) {
+  _fuzz_data_provider.emplace(data, size);
+  return 0;
+}
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h b/test/fuzz/fuzz.h
similarity index 87%
rename from hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
rename to test/fuzz/fuzz.h
index 1d3565d5c..6aa4949a1 100644
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
+++ b/test/fuzz/fuzz.h
@@ -1,7 +1,7 @@
-/* 
+/*
  * The MIT License (MIT)
  *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2022 Nathaniel Brough
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -21,18 +21,17 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  *
- * This file is part of the TinyUSB stack.
  */
 
-#ifndef BOARD_H_
-#define BOARD_H_
+#pragma once
+#include <stdint.h>
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+int fuzz_init(const uint8_t *data, size_t size);
+
 #ifdef __cplusplus
- }
+}
 #endif
-
-#endif /* BOARD_H_ */
diff --git a/test/fuzz/fuzz_private.h b/test/fuzz/fuzz_private.h
new file mode 100644
index 000000000..0d791fcdc
--- /dev/null
+++ b/test/fuzz/fuzz_private.h
@@ -0,0 +1,30 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#pragma once
+#include "fuzzer/FuzzedDataProvider.h"
+#include <optional>
+
+extern std::optional<FuzzedDataProvider> _fuzz_data_provider;
diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk
new file mode 100644
index 000000000..b7b6d6a75
--- /dev/null
+++ b/test/fuzz/make.mk
@@ -0,0 +1,134 @@
+# ---------------------------------------
+# Common make definition for all examples
+# ---------------------------------------
+
+#-------------- TOP and CURRENT_PATH ------------
+
+# Set TOP to be the path to get from the current directory (where make was
+# invoked) to the top of the tree. $(lastword $(MAKEFILE_LIST)) returns
+# the name of this makefile relative to where make was invoked.
+THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
+
+# strip off /tools/top.mk to get for example ../../..
+# and Set TOP to an absolute path
+TOP = $(abspath $(subst make.mk,../..,$(THIS_MAKEFILE)))
+
+# Set CURRENT_PATH to the relative path from TOP to the current directory, ie examples/device/cdc_msc_freertos
+CURRENT_PATH = $(subst $(TOP)/,,$(abspath .))
+
+# Detect whether shell style is windows or not
+# https://stackoverflow.com/questions/714100/os-detecting-makefile/52062069#52062069
+ifeq '$(findstring ;,$(PATH))' ';'
+# PATH contains semicolon - so we're definitely on Windows.
+CMDEXE := 1
+
+# makefile shell commands should use syntax for DOS CMD, not unix sh
+# Unfortunately, SHELL may point to sh or bash, which can't accept DOS syntax.
+# We can't just use sh, because while sh and/or bash shell may be available,
+# many Windows environments won't have utilities like realpath used below, so...
+# Force DOS command shell on Windows.
+SHELL := cmd.exe
+endif
+
+# Build directory
+BUILD := _build
+PROJECT := $(notdir $(CURDIR))
+
+# Handy check parameter function
+check_defined = \
+    $(strip $(foreach 1,$1, \
+    $(call __check_defined,$1,$(strip $(value 2)))))
+__check_defined = \
+    $(if $(value $1),, \
+    $(error Undefined make flag: $1$(if $2, ($2))))
+
+#-------------- Fuzz harness compiler  ------------
+
+CC ?= clang
+CXX ?= clang++
+GDB ?= gdb
+OBJCOPY = objcopy
+SIZE = size
+MKDIR = mkdir
+
+ifeq ($(CMDEXE),1)
+  CP = copy
+  RM = del
+  PYTHON = python
+else
+  SED = sed
+  CP = cp
+  RM = rm
+  PYTHON = python3
+endif
+
+#-------------- Fuzz harness flags ------------
+COVERAGE_FLAGS ?= -fsanitize-coverage=trace-pc-guard
+SANITIZER_FLAGS ?= -fsanitize=fuzzer \
+                   -fsanitize=address
+
+CFLAGS += $(COVERAGE_FLAGS) $(SANITIZER_FLAGS)
+
+#-------------- Source files and compiler flags --------------
+INC += $(TOP)/test
+
+# Compiler Flags
+CFLAGS += \
+  -ggdb \
+  -fdata-sections \
+  -ffunction-sections \
+  -fno-strict-aliasing \
+  -Wall \
+  -Wextra \
+  -Werror \
+  -Wfatal-errors \
+  -Wdouble-promotion \
+  -Wstrict-prototypes \
+  -Wstrict-overflow \
+  -Werror-implicit-function-declaration \
+  -Wfloat-equal \
+  -Wundef \
+  -Wshadow \
+  -Wwrite-strings \
+  -Wsign-compare \
+  -Wmissing-format-attribute \
+  -Wunreachable-code \
+  -Wcast-align \
+  -Wcast-qual \
+  -Wnull-dereference \
+  -Wuninitialized \
+  -Wunused \
+  -Wredundant-decls \
+  -O1
+
+CFLAGS += \
+	-Wno-error=unreachable-code \
+  -DOPT_MCU_FUZZ=1 \
+  -DCFG_TUSB_MCU=OPT_MCU_FUZZ \
+  -D_FUZZ
+
+CXXFLAGS += \
+  -xc++ \
+  -Wno-c++11-narrowing \
+  -fno-implicit-templates
+
+# conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion
+#  -Wconversion
+
+# Debugging/Optimization
+ifeq ($(DEBUG), 1)
+  CFLAGS += -Og
+else
+  CFLAGS += $(CFLAGS_OPTIMIZED)
+endif
+
+# Log level is mapped to TUSB DEBUG option
+ifneq ($(LOG),)
+  CMAKE_DEFSYM +=	-DLOG=$(LOG)
+  CFLAGS += -DCFG_TUSB_DEBUG=$(LOG)
+endif
+
+# Logger: default is uart, can be set to rtt or swo
+ifneq ($(LOGGER),)
+	CMAKE_DEFSYM +=	-DLOGGER=$(LOGGER)
+endif
diff --git a/test/fuzz/msc_fuzz.cc b/test/fuzz/msc_fuzz.cc
new file mode 100644
index 000000000..6e838a682
--- /dev/null
+++ b/test/fuzz/msc_fuzz.cc
@@ -0,0 +1,162 @@
+#include "fuzz/fuzz_private.h"
+#include "tusb.h"
+#include <cassert>
+#include <array>
+#include <limits>
+
+#if CFG_TUD_MSC==1
+
+// Whether host does safe eject.
+// tud_msc_get_maxlun_cb returns a uint8_t so the max logical units that are
+// allowed is 255, so we need to keep track of 255 fuzzed logical units.
+static std::array<bool, std::numeric_limits<uint8_t>::max()> ejected = {false};
+
+extern "C" {
+// Invoked when received SCSI_CMD_INQUIRY
+// Application fill vendor id, product id and revision with string up to 8, 16,
+// 4 characters respectively
+void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8],
+                        uint8_t product_id[16], uint8_t product_rev[4]) {
+  (void)lun;
+  assert(_fuzz_data_provider.has_value());
+
+  std::string vid = _fuzz_data_provider->ConsumeBytesAsString(8);
+  std::string pid = _fuzz_data_provider->ConsumeBytesAsString(16);
+  std::string rev = _fuzz_data_provider->ConsumeBytesAsString(4);
+
+  memcpy(vendor_id, vid.c_str(), strlen(vid.c_str()));
+  memcpy(product_id, pid.c_str(), strlen(pid.c_str()));
+  memcpy(product_rev, rev.c_str(), strlen(rev.c_str()));
+}
+
+// Invoked when received Test Unit Ready command.
+// return true allowing host to read/write this LUN e.g SD card inserted
+bool tud_msc_test_unit_ready_cb(uint8_t lun) {
+  // RAM disk is ready until ejected
+  if (ejected[lun]) {
+    // Additional Sense 3A-00 is NOT_FOUND
+    tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3a, 0x00);
+    return false;
+  }
+
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// Invoked when received SCSI_CMD_READ_CAPACITY_10 and
+// SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size Application update
+// block count and block size
+void tud_msc_capacity_cb(uint8_t lun, uint32_t *block_count,
+                         uint16_t *block_size) {
+  (void)lun;
+  *block_count = _fuzz_data_provider->ConsumeIntegral<uint32_t>();
+  *block_size = _fuzz_data_provider->ConsumeIntegral<uint16_t>();
+}
+
+// Invoked when received Start Stop Unit command
+// - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage
+// - Start = 1 : active mode, if load_eject = 1 : load disk storage
+bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start,
+                           bool load_eject) {
+  (void)power_condition;
+  assert(_fuzz_data_provider.has_value());
+
+  if (load_eject) {
+    if (start) {
+      // load disk storage
+    } else {
+      // unload disk storage
+      ejected[lun] = true;
+    }
+  }
+
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// Callback invoked when received READ10 command.
+// Copy disk's data to buffer (up to bufsize) and return number of copied bytes.
+int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset,
+                          void *buffer, uint32_t bufsize) {
+  assert(_fuzz_data_provider.has_value());
+  (void)lun;
+  (void)lba;
+  (void)offset;
+
+  std::vector<uint8_t> consumed_buffer = _fuzz_data_provider->ConsumeBytes<uint8_t>(
+      _fuzz_data_provider->ConsumeIntegralInRange<uint32_t>(0, bufsize));
+  memcpy(buffer, consumed_buffer.data(), consumed_buffer.size());
+
+  // Sometimes return an error code;
+  if (_fuzz_data_provider->ConsumeBool()) {
+    return _fuzz_data_provider->ConsumeIntegralInRange(
+        std::numeric_limits<int32_t>::min(), -1);
+  }
+
+  return consumed_buffer.size();
+}
+
+bool tud_msc_is_writable_cb(uint8_t lun) {
+  assert(_fuzz_data_provider.has_value());
+  (void)lun;
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// Callback invoked when received WRITE10 command.
+// Process data in buffer to disk's storage and return number of written bytes
+int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset,
+                           uint8_t *buffer, uint32_t bufsize) {
+  // Ignore these as they are outputs and don't affect the return value.
+  (void)lun;
+  (void)lba;
+  (void)offset;
+  (void)buffer;
+  assert(_fuzz_data_provider.has_value());
+
+  // -ve error codes -> bufsize.
+  return _fuzz_data_provider->ConsumeIntegralInRange<int32_t>(
+      std::numeric_limits<int32_t>::min(), bufsize);
+}
+
+// Callback invoked when received an SCSI command not in built-in list below
+// - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE
+// - READ10 and WRITE10 has their own callbacks
+int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer,
+                        uint16_t bufsize) {
+  (void)buffer;
+  (void)bufsize;
+  assert(_fuzz_data_provider.has_value());
+
+  switch (scsi_cmd[0]) {
+  case SCSI_CMD_TEST_UNIT_READY:
+    break;
+  case SCSI_CMD_INQUIRY:
+    break;
+  case SCSI_CMD_MODE_SELECT_6:
+    break;
+  case SCSI_CMD_MODE_SENSE_6:
+    break;
+  case SCSI_CMD_START_STOP_UNIT:
+    break;
+  case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
+    break;
+  case SCSI_CMD_READ_CAPACITY_10:
+    break;
+  case SCSI_CMD_REQUEST_SENSE:
+    break;
+  case SCSI_CMD_READ_FORMAT_CAPACITY:
+    break;
+  case SCSI_CMD_READ_10:
+    break;
+  case SCSI_CMD_WRITE_10:
+    break;
+  default:
+    // Set Sense = Invalid Command Operation
+    tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+    return _fuzz_data_provider->ConsumeIntegralInRange<int32_t>(
+        std::numeric_limits<int32_t>::min(), -1);
+  }
+
+  return 0;
+}
+}
+
+#endif
diff --git a/test/fuzz/net_fuzz.cc b/test/fuzz/net_fuzz.cc
new file mode 100644
index 000000000..468437b0c
--- /dev/null
+++ b/test/fuzz/net_fuzz.cc
@@ -0,0 +1,74 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb_config.h"
+#if defined(CFG_TUD_ECM_RNDIS) || defined(CFG_TUD_NCM)
+
+#include "class/net/net_device.h"
+#include "fuzz_private.h"
+#include <cassert>
+#include <cstdint>
+#include <vector>
+#include "lwip/sys.h"
+
+extern "C" {
+bool tud_network_recv_cb(const uint8_t *src, uint16_t size) {
+  assert(_fuzz_data_provider.has_value());
+  (void)src;
+  (void)size;
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// client must provide this: copy from network stack packet pointer to dst
+uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg) {
+  (void)ref;
+  (void)arg;
+
+  assert(_fuzz_data_provider.has_value());
+
+  uint16_t size = _fuzz_data_provider->ConsumeIntegral<uint16_t>();
+  std::vector<uint8_t> temp = _fuzz_data_provider->ConsumeBytes<uint8_t>(size);
+  memcpy(dst, temp.data(), temp.size());
+  return size;
+}
+
+/* lwip has provision for using a mutex, when applicable */
+sys_prot_t sys_arch_protect(void) { return 0; }
+void sys_arch_unprotect(sys_prot_t pval) { (void)pval; }
+
+//------------- ECM/RNDIS -------------//
+
+// client must provide this: initialize any network state back to the beginning
+void tud_network_init_cb(void) {
+  // NoOp.
+}
+
+// client must provide this: 48-bit MAC address
+// TODO removed later since it is not part of tinyusb stack
+uint8_t tud_network_mac_address[6] = {0};
+
+}   // extern "C"
+
+#endif
diff --git a/test/fuzz/rules.mk b/test/fuzz/rules.mk
new file mode 100644
index 000000000..ee91c706d
--- /dev/null
+++ b/test/fuzz/rules.mk
@@ -0,0 +1,159 @@
+# ---------------------------------------
+# Common make rules for all examples
+# ---------------------------------------
+
+# Set all as default goal
+.DEFAULT_GOAL := all
+
+# ---------------------------------------
+# Compiler Flags
+# ---------------------------------------
+
+LIBS_GCC ?=  -lm
+
+# libc
+LIBS += $(LIBS_GCC)
+
+ifneq ($(BOARD), spresense)
+LIBS += -lc -Wl,-Bstatic -lc++ -Wl,-Bdynamic
+endif
+
+# TinyUSB Stack source
+SRC_C += \
+	src/tusb.c \
+	src/common/tusb_fifo.c \
+	src/device/usbd.c \
+	src/device/usbd_control.c \
+	src/class/audio/audio_device.c \
+	src/class/cdc/cdc_device.c \
+	src/class/dfu/dfu_device.c \
+	src/class/dfu/dfu_rt_device.c \
+	src/class/hid/hid_device.c \
+	src/class/midi/midi_device.c \
+	src/class/msc/msc_device.c \
+	src/class/net/ecm_rndis_device.c \
+	src/class/net/ncm_device.c \
+	src/class/usbtmc/usbtmc_device.c \
+	src/class/video/video_device.c \
+	src/class/vendor/vendor_device.c
+
+
+# Fuzzers are c++
+SRC_CXX += \
+	test/fuzz/dcd_fuzz.cc \
+	test/fuzz/fuzz.cc \
+	test/fuzz/msc_fuzz.cc \
+	test/fuzz/net_fuzz.cc \
+	test/fuzz/usbd_fuzz.cc
+
+# TinyUSB stack include
+INC += $(TOP)/src
+
+CFLAGS += $(addprefix -I,$(INC))
+CXXFLAGS += -std=c++17
+
+# LTO makes it difficult to analyze map file for optimizing size purpose
+# We will run this option in ci
+ifeq ($(NO_LTO),1)
+CFLAGS := $(filter-out -flto,$(CFLAGS))
+endif
+
+ifneq ($(LD_FILE),)
+LDFLAGS_LD_FILE ?= -Wl,-T,$(TOP)/$(LD_FILE)
+endif
+
+LDFLAGS += $(CFLAGS) $(LDFLAGS_LD_FILE) -fuse-ld=lld -Wl,-Map=$@.map -Wl,--cref -Wl,-gc-sections
+ifneq ($(SKIP_NANOLIB), 1)
+endif
+
+ASFLAGS += $(CFLAGS)
+
+# Assembly files can be name with upper case .S, convert it to .s
+SRC_S := $(SRC_S:.S=.s)
+
+# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
+# assembly file should be placed first in linking order
+# '_asm' suffix is added to object of assembly file
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_CXX:.cc=_cxx.o))
+
+# Verbose mode
+ifeq ("$(V)","1")
+$(info CFLAGS  $(CFLAGS) ) $(info )
+$(info LDFLAGS $(LDFLAGS)) $(info )
+$(info ASFLAGS $(ASFLAGS)) $(info )
+endif
+
+# ---------------------------------------
+# Rules
+# ---------------------------------------
+
+all: $(BUILD)/$(PROJECT)
+
+OBJ_DIRS = $(sort $(dir $(OBJ)))
+$(OBJ): | $(OBJ_DIRS)
+$(OBJ_DIRS):
+ifeq ($(CMDEXE),1)
+	@$(MKDIR) $(subst /,\,$@)
+else
+	@$(MKDIR) -p $@
+endif
+
+$(BUILD)/$(PROJECT): $(OBJ)
+	@echo LINK $@
+	@ $(CXX) -o $@  $(LIB_FUZZING_ENGINE) $^ $(LIBS) $(LDFLAGS)
+
+# We set vpath to point to the top of the tree so that the source files
+# can be located. By following this scheme, it allows a single build rule
+# to be used to compile all .c files.
+vpath %.c . $(TOP)
+$(BUILD)/obj/%.o: %.c
+	@echo CC $(notdir $@)
+	@$(CC) $(CFLAGS) -c -MD -o $@ $<
+
+# All cpp srcs
+vpath %.cc . $(TOP)
+$(BUILD)/obj/%_cxx.o: %.cc
+	@echo CXX $(notdir $@)
+	@$(CXX) $(CFLAGS) $(CXXFLAGS) -c -MD -o $@ $<
+
+# ASM sources lower case .s
+vpath %.s . $(TOP)
+$(BUILD)/obj/%_asm.o: %.s
+	@echo AS $(notdir $@)
+	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
+
+# ASM sources upper case .S
+vpath %.S . $(TOP)
+$(BUILD)/obj/%_asm.o: %.S
+	@echo AS $(notdir $@)
+	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
+
+.PHONY: clean
+clean:
+ifeq ($(CMDEXE),1)
+	rd /S /Q $(subst /,\,$(BUILD))
+else
+	$(RM) -rf $(BUILD)
+endif
+# ---------------- GNU Make End -----------------------
+
+# get depenecies
+.PHONY: get-deps
+get-deps:
+	$(PYTHON) $(TOP)/tools/get_deps.py $(DEPS_SUBMODULES)
+
+size: $(BUILD)/$(PROJECT)
+	-@echo ''
+	@$(SIZE) $<
+	-@echo ''
+
+# linkermap must be install previously at https://github.com/hathach/linkermap
+linkermap: $(BUILD)/$(PROJECT)
+	@linkermap -v $<.map
+
+# Print out the value of a make variable.
+# https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile
+print-%:
+	@echo $* = $($*)
diff --git a/test/fuzz/usbd_fuzz.cc b/test/fuzz/usbd_fuzz.cc
new file mode 100644
index 000000000..45c5fd7ea
--- /dev/null
+++ b/test/fuzz/usbd_fuzz.cc
@@ -0,0 +1,73 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "fuzz/fuzz_private.h"
+#include "tusb.h"
+// #include "usb_descriptors.h"
+
+#ifndef CFG_FUZZ_MAX_STRING_LEN
+#define CFG_FUZZ_MAX_STRING_LEN 1000
+#endif
+
+extern "C" {
+
+/* TODO: Implement a fuzzed version of this.
+uint8_t const *tud_descriptor_bos_cb(void) {  }
+*/
+
+/* TODO: Implement a fuzzed version of this.
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {}
+*/
+
+/* TODO: Implement a fuzzed version of this.
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {}
+*/
+
+void tud_mount_cb(void) {
+  // NOOP
+}
+
+void tud_umount_cb(void) {
+  // NOOP
+}
+
+void tud_suspend_cb(bool remote_wakeup_en) {
+  (void)remote_wakeup_en;
+  // NOOP
+}
+
+void tud_resume_cb(void) {
+  // NOOP
+}
+
+/* TODO: Implement a fuzzed version of this.
+bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage,
+                                tusb_control_request_t const *request) {}
+*/
+
+/* TODO: Implement a fuzzed version of this.
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {}
+*/
+}
diff --git a/test/hil/hfp.json b/test/hil/hfp.json
new file mode 100644
index 000000000..8ba7a8f44
--- /dev/null
+++ b/test/hil/hfp.json
@@ -0,0 +1,40 @@
+{
+    "boards": [
+        {
+            "name": "stm32l412nucleo",
+            "uid": "41003B000E504E5457323020",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "774470029",
+                "args": "-device STM32L412KB"
+            }
+        },
+        {
+            "name": "stm32f746disco",
+            "uid": "210041000C51343237303334",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "770935966",
+                "args": "-device STM32F746NG"
+            }
+        },
+        {
+            "name": "lpcxpresso43s67",
+            "uid": "08F000044528BAAA8D858F58C50700F5",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "728973776",
+                "args": "-device LPC43S67_M4"
+            }
+        }
+    ]
+}
diff --git a/test/hil/hil_ci_set_matrix.py b/test/hil/hil_ci_set_matrix.py
new file mode 100644
index 000000000..67ce2abb8
--- /dev/null
+++ b/test/hil/hil_ci_set_matrix.py
@@ -0,0 +1,44 @@
+import argparse
+import json
+import os
+
+
+def main():
+    parser = argparse.ArgumentParser()
+    parser.add_argument('config_file', help='Configuration JSON file')
+    args = parser.parse_args()
+
+    config_file = args.config_file
+
+    # if config file is not found, try to find it in the same directory as this script
+    if not os.path.exists(config_file):
+        config_file = os.path.join(os.path.dirname(__file__), config_file)
+    with open(config_file) as f:
+        config = json.load(f)
+
+    matrix = {
+        'arm-gcc': [],
+        'esp-idf': []
+    }
+    for board in config['boards']:
+        name = board['name']
+        flasher = board['flasher']
+        if flasher['name'] == 'esptool':
+            toolchain = 'esp-idf'
+        else:
+            toolchain = 'arm-gcc'
+
+        if 'build' in board and 'flags_on' in board['build']:
+            for f in board['build']['flags_on']:
+                if f == '':
+                    matrix[toolchain].append(f'-b {name}')
+                else:
+                    matrix[toolchain].append(f'-b {name} -f1 {f.replace(" ", " -f1 ")}')
+        else:
+            matrix[toolchain].append(f'-b {name}')
+
+    print(json.dumps(matrix))
+
+
+if __name__ == '__main__':
+    main()
diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py
new file mode 100755
index 000000000..a9f5dc1e1
--- /dev/null
+++ b/test/hil/hil_test.py
@@ -0,0 +1,634 @@
+#!/usr/bin/env python3
+#
+# The MIT License (MIT)
+#
+# Copyright (c) 2023 HiFiPhile
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+# udev rules :
+# ACTION=="add", SUBSYSTEM=="tty", SUBSYSTEMS=="usb", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", SYMLINK+="ttyUSB_%c.%s{bInterfaceNumber}"
+# ACTION=="add", SUBSYSTEM=="block", SUBSYSTEMS=="usb", ENV{ID_FS_USAGE}=="filesystem", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", RUN{program}+="/usr/bin/systemd-mount --no-block --automount=yes --collect $devnode /media/blkUSB_%c.%s{bInterfaceNumber}"
+
+import argparse
+import os
+import re
+import sys
+import time
+import serial
+import subprocess
+import json
+import glob
+from multiprocessing import Pool
+import fs
+
+ENUM_TIMEOUT = 30
+
+STATUS_OK = "\033[32mOK\033[0m"
+STATUS_FAILED = "\033[31mFailed\033[0m"
+STATUS_SKIPPED = "\033[33mSkipped\033[0m"
+
+verbose = False
+
+WCH_RISCV_CONTENT = """
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
+"""
+
+# -------------------------------------------------------------
+# Path
+# -------------------------------------------------------------
+OPENCOD_ADI_PATH = f'{os.getenv("HOME")}/app/openocd_adi'
+TINYUSB_ROOT = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
+
+# get usb serial by id
+def get_serial_dev(id, vendor_str, product_str, ifnum):
+    if vendor_str and product_str:
+        # known vendor and product
+        vendor_str = vendor_str.replace(' ', '_')
+        product_str = product_str.replace(' ', '_')
+        return f'/dev/serial/by-id/usb-{vendor_str}_{product_str}_{id}-if{ifnum:02d}'
+    else:
+        # just use id: mostly for cp210x/ftdi flasher
+        pattern = f'/dev/serial/by-id/usb-*_{id}-if{ifnum:02d}*'
+        port_list = glob.glob(pattern)
+        return port_list[0]
+
+
+# get usb disk by id
+def get_disk_dev(id, vendor_str, lun):
+    return f'/dev/disk/by-id/usb-{vendor_str}_Mass_Storage_{id}-0:{lun}'
+
+
+def get_hid_dev(id, vendor_str, product_str, event):
+    return f'/dev/input/by-id/usb-{vendor_str}_{product_str}_{id}-{event}'
+
+
+def open_serial_dev(port):
+    timeout = ENUM_TIMEOUT
+    ser = None
+    while timeout:
+        if os.path.exists(port):
+            try:
+                # slight delay since kernel may occupy the port briefly
+                time.sleep(0.5)
+                timeout = timeout - 0.5
+                ser = serial.Serial(port, baudrate=115200, timeout=5)
+                break
+            except serial.SerialException:
+                pass
+        time.sleep(0.5)
+        timeout = timeout - 0.5
+
+    assert timeout, f'Cannot open port f{port}' if os.path.exists(port) else f'Port {port} not existed'
+    return ser
+
+
+def read_disk_file(uid, lun, fname):
+    # open_fs("fat://{dev}) require 'pip install pyfatfs'
+    dev = get_disk_dev(uid, 'TinyUSB', lun)
+    timeout = ENUM_TIMEOUT
+    while timeout:
+        if os.path.exists(dev):
+            fat = fs.open_fs(f'fat://{dev}?read_only=true')
+            try:
+                with fat.open(fname, 'rb') as f:
+                    data = f.read()
+            finally:
+                fat.close()
+            assert data, f'Cannot read file {fname} from {dev}'
+            return data
+        time.sleep(1)
+        timeout -= 1
+
+    assert timeout, f'Storage {dev} not existed'
+    return None
+
+
+# -------------------------------------------------------------
+# Flashing firmware
+# -------------------------------------------------------------
+def run_cmd(cmd, cwd=None):
+    r = subprocess.run(cmd, cwd=cwd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    if r.returncode != 0:
+        title = f'COMMAND FAILED: {cmd}'
+        print()
+        if os.getenv('CI'):
+            print(f"::group::{title}")
+            print(r.stdout.decode("utf-8"))
+            print(f"::endgroup::")
+        else:
+            print(title)
+            print(r.stdout.decode("utf-8"))
+    elif verbose:
+        print(cmd)
+        print(r.stdout.decode("utf-8"))
+    return r
+
+
+def flash_jlink(board, firmware):
+    flasher = board['flasher']
+    script = ['halt', 'r', f'loadfile {firmware}.elf', 'r', 'go', 'exit']
+    f_jlink = f'{board["name"]}_{os.path.basename(firmware)}.jlink'
+    with open(f_jlink, 'w') as f:
+        f.writelines(f'{s}\n' for s in script)
+    ret = run_cmd(f'JLinkExe -USB {flasher["uid"]} {flasher["args"]} -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile {f_jlink}')
+    os.remove(f_jlink)
+    return ret
+
+
+def reset_jlink(board):
+    flasher = board['flasher']
+    script = ['halt', 'r', 'go', 'exit']
+    f_jlink = f'{board["name"]}_reset.jlink'
+    if not os.path.exists(f_jlink):
+        with open(f_jlink, 'w') as f:
+            f.writelines(f'{s}\n' for s in script)
+    ret = run_cmd(f'JLinkExe -USB {flasher["uid"]} {flasher["args"]} -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile {f_jlink}')
+    return ret
+
+
+def flash_stlink(board, firmware):
+    flasher = board['flasher']
+    return run_cmd(f'STM32_Programmer_CLI --connect port=swd sn={flasher["uid"]} --write {firmware}.elf --go')
+
+
+def reset_stlink(board):
+    flasher = board['flasher']
+    return run_cmd(f'STM32_Programmer_CLI --connect port=swd sn={flasher["uid"]} --rst --go')
+
+def flash_stflash(board, firmware):
+    flasher = board['flasher']
+    ret = run_cmd(f'st-flash --serial {flasher["uid"]} write {firmware}.bin 0x8000000')
+    return ret
+
+
+def reset_stflash(board):
+    flasher = board['flasher']
+    return subprocess.CompletedProcess(args=['dummy'], returncode=0)
+
+
+def flash_openocd(board, firmware):
+    flasher = board['flasher']
+    ret = run_cmd(f'openocd -c "tcl_port disabled" -c "gdb_port disabled" -c "adapter serial {flasher["uid"]}" '
+                  f'{flasher["args"]} -c init -c halt -c "program {firmware}.elf verify" -c reset -c exit')
+    return ret
+
+
+def reset_openocd(board):
+    flasher = board['flasher']
+    ret = run_cmd(f'openocd -c "tcl_port disabled" -c "gdb_port disabled" -c "adapter serial {flasher["uid"]}" '
+                  f'{flasher["args"]} -c "reset exit"')
+    return ret
+
+
+def flash_openocd_wch(board, firmware):
+    flasher = board['flasher']
+    f_wch = f"wch-riscv_{board['uid']}.cfg"
+    if not os.path.exists(f_wch):
+        with open(f_wch, 'w') as file:
+            file.write(WCH_RISCV_CONTENT)
+
+    ret = run_cmd(f'openocd_wch -c "adapter serial {flasher["uid"]}" -f {f_wch} '
+                  f'-c "program {firmware}.elf reset exit"')
+    return ret
+
+
+def reset_openocd_wch(board):
+    flasher = board['flasher']
+    f_wch = f"wch-riscv_{board['uid']}.cfg"
+    if not os.path.exists(f_wch):
+        with open(f_wch, 'w') as file:
+            file.write(WCH_RISCV_CONTENT)
+
+    ret = run_cmd(f'openocd_wch -c "adapter serial {flasher["uid"]}" -f {f_wch} -c "program reset exit"')
+    return ret
+
+
+def flash_openocd_adi(board, firmware):
+    flasher = board['flasher']
+    ret = run_cmd(f'{OPENCOD_ADI_PATH}/src/openocd -c "adapter serial {flasher["uid"]}" -s {OPENCOD_ADI_PATH}/tcl '
+                  f'{flasher["args"]} -c "program {firmware}.elf reset exit"')
+    return ret
+
+
+def reset_openocd_adi(board):
+    flasher = board['flasher']
+    ret = run_cmd(f'{OPENCOD_ADI_PATH}/src/openocd -c "adapter serial {flasher["uid"]}" -s {OPENCOD_ADI_PATH}/tcl '
+                  f'{flasher["args"]} -c "program reset exit"')
+    return ret
+
+
+def flash_wlink_rs(board, firmware):
+    flasher = board['flasher']
+    # wlink use index for probe selection and lacking usb serial support
+    ret = run_cmd(f'wlink flash {firmware}.elf')
+    return ret
+
+
+def reset_wlink_rs(board):
+    flasher = board['flasher']
+    # wlink use index for probe selection and lacking usb serial support
+    ret = run_cmd(f'wlink reset')
+    return ret
+
+
+def flash_esptool(board, firmware):
+    flasher = board['flasher']
+    port = get_serial_dev(flasher["uid"], None, None, 0)
+    fw_dir = os.path.dirname(f'{firmware}.bin')
+    with open(f'{fw_dir}/config.env') as f:
+        idf_target = json.load(f)['IDF_TARGET']
+    with open(f'{fw_dir}/flash_args') as f:
+        flash_args = f.read().strip().replace('\n', ' ')
+    command = (f'esptool.py --chip {idf_target} -p {port} {flasher["args"]} '
+               f'--before=default_reset --after=hard_reset write_flash {flash_args}')
+    ret = run_cmd(command, cwd=fw_dir)
+    return ret
+
+
+def reset_esptool(board):
+    flasher = board['flasher']
+    return subprocess.CompletedProcess(args=['dummy'], returncode=0)
+
+
+def flash_uniflash(board, firmware):
+    flasher = board['flasher']
+    ret = run_cmd(f'dslite.sh {flasher["args"]} -f {firmware}.hex')
+    return ret
+
+
+def reset_uniflash(board):
+    flasher = board['flasher']
+    return subprocess.CompletedProcess(args=['dummy'], returncode=0)
+
+
+# -------------------------------------------------------------
+# Tests: dual
+# -------------------------------------------------------------
+def test_dual_host_info_to_device_cdc(board):
+    uid = board['uid']
+    declared_devs = [f'{d["vid_pid"]}_{d["serial"]}' for d in board['tests']['dev_attached']]
+    port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0)
+    ser = open_serial_dev(port)
+
+    # read from cdc, first line should contain vid/pid and serial
+    data = ser.read(1000)
+    ser.close()
+    if len(data) == 0:
+        assert False, 'No data from device'
+    lines = data.decode('utf-8').splitlines()
+
+    enum_dev_sn = []
+    for l in lines:
+        vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l)
+        if vid_pid_sn:
+            print(f'\r\n  {l} ', end='')
+            enum_dev_sn.append(f'{vid_pid_sn.group(1)}_{vid_pid_sn.group(2)}_{vid_pid_sn.group(3)}')
+
+    if set(declared_devs) != set(enum_dev_sn):
+        failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}'
+        assert False, failed_msg
+    return 0
+
+
+# -------------------------------------------------------------
+# Tests: host
+# -------------------------------------------------------------
+def test_host_device_info(board):
+    flasher = board['flasher']
+    declared_devs = [f'{d["vid_pid"]}_{d["serial"]}' for d in board['tests']['dev_attached']]
+
+    port = get_serial_dev(flasher["uid"], None, None, 0)
+    ser = open_serial_dev(port)
+
+    # reset device since we can miss the first line
+    ret = globals()[f'reset_{flasher["name"].lower()}'](board)
+    assert ret.returncode == 0,  'Failed to reset device'
+
+    data = ser.read(1000)
+    ser.close()
+    if len(data) == 0:
+        assert False, 'No data from device'
+
+    lines = data.decode('utf-8').splitlines()
+    enum_dev_sn = []
+    for l in lines:
+        vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l)
+        if vid_pid_sn:
+            print(f'\r\n  {l} ', end='')
+            enum_dev_sn.append(f'{vid_pid_sn.group(1)}_{vid_pid_sn.group(2)}_{vid_pid_sn.group(3)}')
+
+    if set(declared_devs) != set(enum_dev_sn):
+        failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}'
+        assert False, failed_msg
+
+    return 0
+
+
+# -------------------------------------------------------------
+# Tests: device
+# -------------------------------------------------------------
+def test_device_board_test(board):
+    # Dummy test
+    pass
+
+
+def test_device_cdc_dual_ports(board):
+    uid = board['uid']
+    port = [
+        get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0),
+        get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 2)
+    ]
+    ser = [open_serial_dev(p) for p in port]
+
+    str_test = [ b"test_no1", b"test_no2" ]
+    # Echo test write to each port and read back
+    for i in range(len(str_test)):
+        s = str_test[i]
+        l = len(s)
+        ser[i].write(s)
+        ser[i].flush()
+        rd = [ ser[i].read(l) for i in range(len(ser)) ]
+        assert rd[0] == s.lower(), f'Port1 wrong data: expected {s.lower()} was {rd[0]}'
+        assert rd[1] == s.upper(), f'Port2 wrong data: expected {s.upper()} was {rd[1]}'
+    ser[0].close()
+    ser[1].close()
+
+
+def test_device_cdc_msc(board):
+    uid = board['uid']
+    # Echo test
+    port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0)
+    ser = open_serial_dev(port)
+
+    test_str = b"test_str"
+    ser.write(test_str)
+    ser.flush()
+    rd_str = ser.read(len(test_str))
+    ser.close()
+    assert  rd_str == test_str, f'CDC wrong data: expected: {test_str} was {rd_str}'
+
+    # Block test
+    data = read_disk_file(uid,0,'README.TXT')
+    readme = \
+    b"This is tinyusb's MassStorage Class demo.\r\n\r\n\
+If you find any bugs or get any questions, feel free to file an\r\n\
+issue at github.com/hathach/tinyusb"
+
+    assert data == readme, 'MSC wrong data'
+
+
+def test_device_cdc_msc_freertos(board):
+    test_device_cdc_msc(board)
+
+
+def test_device_dfu(board):
+    uid = board['uid']
+
+    # Wait device enum
+    timeout = ENUM_TIMEOUT
+    while timeout:
+        ret = run_cmd(f'dfu-util -l')
+        stdout = ret.stdout.decode()
+        if f'serial="{uid}"' in stdout and 'Found DFU: [cafe:4000]' in stdout:
+            break
+        time.sleep(1)
+        timeout = timeout - 1
+
+    assert timeout, 'Device not available'
+
+    f_dfu0 = f'dfu0_{uid}'
+    f_dfu1 = f'dfu1_{uid}'
+
+    # Test upload
+    try:
+        os.remove(f_dfu0)
+        os.remove(f_dfu1)
+    except OSError:
+        pass
+
+    ret = run_cmd(f'dfu-util -S {uid} -a 0 -U {f_dfu0}')
+    assert ret.returncode == 0, 'Upload failed'
+
+    ret = run_cmd(f'dfu-util -S {uid} -a 1 -U {f_dfu1}')
+    assert ret.returncode == 0, 'Upload failed'
+
+    with open(f_dfu0) as f:
+        assert 'Hello world from TinyUSB DFU! - Partition 0' in f.read(), 'Wrong uploaded data'
+
+    with open(f_dfu1) as f:
+        assert 'Hello world from TinyUSB DFU! - Partition 1' in f.read(), 'Wrong uploaded data'
+
+    os.remove(f_dfu0)
+    os.remove(f_dfu1)
+
+
+def test_device_dfu_runtime(board):
+    uid = board['uid']
+
+    # Wait device enum
+    timeout = ENUM_TIMEOUT
+    while timeout:
+        ret = run_cmd(f'dfu-util -l')
+        stdout = ret.stdout.decode()
+        if f'serial="{uid}"' in stdout and 'Found Runtime: [cafe:4000]' in stdout:
+            break
+        time.sleep(1)
+        timeout = timeout - 1
+
+    assert timeout, 'Device not available'
+
+
+def test_device_hid_boot_interface(board):
+    uid = board['uid']
+    kbd = get_hid_dev(uid, 'TinyUSB', 'TinyUSB_Device', 'event-kbd')
+    mouse1 = get_hid_dev(uid, 'TinyUSB', 'TinyUSB_Device', 'if01-event-mouse')
+    mouse2 = get_hid_dev(uid, 'TinyUSB', 'TinyUSB_Device', 'if01-mouse')
+    # Wait device enum
+    timeout = ENUM_TIMEOUT
+    while timeout:
+        if os.path.exists(kbd) and os.path.exists(mouse1) and os.path.exists(mouse2):
+            break
+        time.sleep(1)
+        timeout = timeout - 1
+
+    assert timeout, 'HID device not available'
+
+
+def test_device_hid_composite_freertos(id):
+    # TODO implement later
+    pass
+
+
+# -------------------------------------------------------------
+# Main
+# -------------------------------------------------------------
+# device tests
+# note don't test 2 examples with cdc or 2 msc next to each other
+device_tests = [
+    'device/cdc_dual_ports',
+    'device/dfu',
+    'device/cdc_msc',
+    'device/dfu_runtime',
+    'device/cdc_msc_freertos',
+    'device/hid_boot_interface',
+]
+
+dual_tests = [
+    'dual/host_info_to_device_cdc',
+]
+
+host_test = [
+    'host/device_info',
+]
+
+
+def test_board(board):
+    name = board['name']
+    flasher = board['flasher']
+
+    # default to all tests
+    test_list = []
+
+    if 'tests' in board:
+        board_tests = board['tests']
+        if 'device' in board_tests and board_tests['device'] == True:
+            test_list += list(device_tests)
+        if 'dual' in board_tests and board_tests['dual'] == True:
+            test_list += dual_tests
+        if 'host' in board_tests and board_tests['host'] == True:
+            test_list += host_test
+        if 'only' in board_tests:
+            test_list = board_tests['only']
+        if 'skip' in board_tests:
+            for skip in board_tests['skip']:
+                if skip in test_list:
+                    test_list.remove(skip)
+                    print(f'{name:25} {skip:30} ... Skip')
+
+    # board_test is added last to disable board's usb
+    test_list.append('device/board_test')
+
+    err_count = 0
+    flags_on_list = [""]
+    if 'build' in board and 'flags_on' in board['build']:
+        flags_on_list = board['build']['flags_on']
+
+    for f1 in flags_on_list:
+        f1_str = ""
+        if f1 != "":
+            f1_str = '-f1_' + f1.replace(' ', '_')
+        for test in test_list:
+            fw_dir = f'{TINYUSB_ROOT}/cmake-build/cmake-build-{name}{f1_str}/{test}'
+            if not os.path.exists(fw_dir):
+                fw_dir = f'{TINYUSB_ROOT}/examples/cmake-build-{name}{f1_str}/{test}'
+            fw_name = f'{fw_dir}/{os.path.basename(test)}'
+            print(f'{name+f1_str:40} {test:30} ... ', end='')
+
+            if not os.path.exists(fw_dir) or not (os.path.exists(f'{fw_name}.elf') or os.path.exists(f'{fw_name}.bin')):
+                print('Skip (no binary)')
+                continue
+
+            # flash firmware. It may fail randomly, retry a few times
+            max_rety = 2
+            for i in range(max_rety):
+                ret = globals()[f'flash_{flasher["name"].lower()}'](board, fw_name)
+                if ret.returncode == 0:
+                    try:
+                        globals()[f'test_{test.replace("/", "_")}'](board)
+                        print('OK')
+                        break
+                    except Exception as e:
+                        if i == max_rety - 1:
+                            err_count += 1
+                            print(STATUS_FAILED)
+                            print(f'  {e}')
+                        else:
+                            print()
+                            print(f'  Test failed: {e}, retry {i+1}')
+                            time.sleep(1)
+                else:
+                    print(f'Flashing failed, retry {i+1}')
+                    time.sleep(1)
+
+            if ret.returncode != 0:
+                err_count += 1
+                print(f'Flash {STATUS_FAILED}')
+
+    return err_count
+
+
+def main():
+    """
+    Hardware test on specified boards
+    """
+    global verbose
+
+    duration = time.time()
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument('config_file', help='Configuration JSON file')
+    parser.add_argument('-b', '--board', action='append', default=[], help='Boards to test, all if not specified')
+    parser.add_argument('-v', '--verbose', action='store_true', help='Verbose output')
+    args = parser.parse_args()
+
+    config_file = args.config_file
+    boards = args.board
+    verbose = args.verbose
+
+    # if config file is not found, try to find it in the same directory as this script
+    if not os.path.exists(config_file):
+        config_file = os.path.join(os.path.dirname(__file__), config_file)
+    with open(config_file) as f:
+        config = json.load(f)
+
+    if len(boards) == 0:
+        config_boards = config['boards']
+    else:
+        config_boards = [e for e in config['boards'] if e['name'] in boards]
+
+    with Pool(processes=os.cpu_count()) as pool:
+        err_count = sum(pool.map(test_board, config_boards))
+
+    duration = time.time() - duration
+    print()
+    print("-" * 30)
+    print(f'Total failed: {err_count} in {duration:.1f}s')
+    print("-" * 30)
+    sys.exit(err_count)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/test/hil/requirements.txt b/test/hil/requirements.txt
new file mode 100644
index 000000000..c33980c9d
--- /dev/null
+++ b/test/hil/requirements.txt
@@ -0,0 +1,2 @@
+fs
+pyfatfs
diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json
new file mode 100644
index 000000000..7393226eb
--- /dev/null
+++ b/test/hil/tinyusb.json
@@ -0,0 +1,231 @@
+{
+    "boards": [
+        {
+            "name": "espressif_p4_function_ev",
+            "uid": "6055F9F98715",
+            "build" : {
+                "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE"]
+            },
+            "tests": {
+                "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos", "host/device_info"],
+                "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002427"}]
+            },
+            "flasher": {
+                "name": "esptool",
+                "uid": "4ea4f48f6bc3ee11bbb9d00f9e1b1c54",
+                "args": "-b 1500000"
+            },
+            "comment": "Use TS3USB30 mux to test both device and host"
+        },
+        {
+            "name": "espressif_s3_devkitm",
+            "uid": "84F703C084E4",
+            "build" : {
+                "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"]
+            },
+            "tests": {
+                "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"]
+            },
+            "flasher": {
+                "name": "esptool",
+                "uid": "3ea619acd1cdeb11a0a0b806e93fd3f1",
+                "args": "-b 1500000"
+            }
+        },
+        {
+            "name": "feather_nrf52840_express",
+            "uid": "1F0479CD0F764471",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "000682804350",
+                "args": "-device nrf52840_xxaa"
+            }
+        },
+        {
+            "name": "max32666fthr",
+            "uid": "0C81464124010B20FF0A08CC2C",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "openocd_adi",
+                "uid": "E6614C311B597D32",
+                "args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg"
+            }
+        },
+        {
+            "name": "metro_m4_express",
+            "uid": "9995AD485337433231202020FF100A34",
+            "tests": {
+                "device": true, "host": false, "dual": false,
+                "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}]
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "123456",
+                "args": "-device ATSAMD51J19"
+            }
+        },
+        {
+            "name": "lpcxpresso11u37",
+            "uid": "17121919",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "000724441579",
+                "args": "-device LPC11U37/401"
+            }
+        },
+        {
+            "name": "ra4m1_ek",
+            "uid": "152E163038303131393346E46F26574B",
+            "tests": {
+                "device": true, "host": false, "dual": false,
+                "skip": ["device/cdc_msc", "device/cdc_msc_freertos"]
+            },
+            "comment": "MSC is slow to enumerated #2602",
+            "flasher": {
+                "name": "jlink",
+                "uid": "000831174392",
+                "args": "-device R7FA4M1AB"
+            }
+        },
+        {
+            "name": "raspberry_pi_pico",
+            "uid": "E6614C311B764A37",
+            "tests": {
+                "device": true, "host": false, "dual": false,
+                "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002470"}]
+            },
+            "flasher": {
+                "name": "openocd",
+                "uid": "E6614103E72C1D2F",
+                "args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\""
+            }
+        },
+        {
+            "name": "raspberry_pi_pico2",
+            "uid": "560AE75E1C7152C9",
+            "tests": {
+                "device": true, "host": false, "dual": false,
+                "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "533D004242"}]
+            },
+            "flasher": {
+                "name": "openocd",
+                "uid": "E6633861A3978538",
+                "args": "-f interface/cmsis-dap.cfg -f target/rp2350.cfg -c \"adapter speed 5000\""
+            }
+        },
+        {
+            "name": "stm32f072disco",
+            "uid": "3A001A001357364230353532",
+            "flasher": {
+                "name": "jlink",
+                "uid": "779541626",
+                "args": "-device stm32f072rb"
+            }
+        },
+        {
+            "name": "stm32f723disco",
+            "uid": "460029001951373031313335",
+            "build" : {
+                "flags_on": ["", "CFG_TUH_DWC2_DMA_ENABLE"]
+            },
+            "tests": {
+                "device": true, "host": true, "dual": false,
+                "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2003414"}]
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "000776606156",
+                "args": "-device stm32f723ie"
+            },
+            "comment": "Device port0 FS (slave only), Host port1 HS with DMA"
+        },
+        {
+            "name": "stm32h743nucleo",
+            "uid": "110018000951383432343236",
+            "build" : {
+                "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"]
+            },
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "stlink",
+                "uid": "004C00343137510F39383538",
+                "args": ""
+            }
+        },
+        {
+            "name": "stm32g0b1nucleo",
+            "uid": "4D0038000450434E37343120",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "openocd",
+                "uid": "066FFF495087534867063844",
+                "args": "-f interface/stlink.cfg -f target/stm32g0x.cfg"
+            }
+        }
+    ],
+    "boards-skip": [
+        {
+            "name": "stm32f769disco",
+            "uid": "21002F000F51363531383437",
+            "build" : {
+                "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"]
+            },
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "000778170924",
+                "args": "-device stm32f769ni"
+            }
+        },
+        {
+            "name": "mimxrt1015_evk",
+            "uid": "DC28F865D2111D228D00B0543A70463C",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "000726284213",
+                "args": "-device MIMXRT1015DAF5A"
+            }
+        },
+        {
+            "name": "nanoch32v203",
+            "uid": "CDAB277B0FBC03E339E339E3",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "openocd_wch",
+                "uid": "EBCA8F0670AF",
+                "args": ""
+            }
+        },
+        {
+            "name": "stm32f407disco",
+            "uid": "30001A000647313332353735",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "jlink",
+                "uid": "000773661813",
+                "args": "-device stm32f407vg"
+            }
+        }
+    ]
+}
diff --git a/test/project.yml b/test/project.yml
deleted file mode 100644
index dc4a9cb28..000000000
--- a/test/project.yml
+++ /dev/null
@@ -1,106 +0,0 @@
----
-
-# Notes:
-# Sample project C code is not presently written to produce a release artifact.
-# As such, release build options are disabled.
-# This sample, therefore, only demonstrates running a collection of unit tests.
-
-:project:
-  :use_exceptions: TRUE
-  :use_mocks: TRUE
-  :use_test_preprocessor: TRUE
-  :use_auxiliary_dependencies: TRUE
-  :use_deep_dependencies: TRUE
-  :build_root: _build
-#  :release_build: TRUE
-  :test_file_prefix: test_
-  :which_ceedling: vendor/ceedling
-  :default_tasks:
-    - test:all
-
-#:test_build:
-#  :use_assembly: TRUE
-
-#:release_build:
-#  :output: MyApp.out
-#  :use_assembly: FALSE
-
-:environment:
-
-:extension:
-  :executable: .out
-
-:paths:
-  :test:
-    - +:test/**
-    - -:test/support
-  :source:
-    - ../src/**
-  :support:
-    - test/support
-
-:defines:
-  # in order to add common defines:
-  #  1) remove the trailing [] from the :common: section
-  #  2) add entries to the :common: section (e.g. :test: has TEST defined)
-  :common: &common_defines
-    - _UNITY_TEST_
-  :test:
-    - *common_defines
-  :test_preprocess:
-    - *common_defines
-
-:cmock:
-  :mock_prefix: mock_
-  :when_no_prototypes: :warn
-  :enforce_strict_ordering: TRUE
-  :plugins:
-    - :ignore
-    - :ignore_arg
-    - :return_thru_ptr
-    - :callback
-    - :array
-  :treat_as:
-    uint8:    HEX8
-    uint16:   HEX16
-    uint32:   UINT32
-    int8:     INT8
-    bool:     UINT8
-
-# Add -gcov to the plugins list to make sure of the gcov plugin
-# You will need to have gcov and gcovr both installed to make it work.
-# For more information on these options, see docs in plugins/gcov
-:gcov:
-    :html_report: TRUE
-    :html_report_type: detailed
-    :html_medium_threshold: 75
-    :html_high_threshold: 90
-    :xml_report: FALSE
-
-#:tools:
-# Ceedling defaults to using gcc for compiling, linking, etc.
-# As [:tools] is blank, gcc will be used (so long as it's in your system path)
-# See documentation to configure a given toolchain for use
-
-# LIBRARIES
-# These libraries are automatically injected into the build process. Those specified as
-# common will be used in all types of builds. Otherwise, libraries can be injected in just
-# tests or releases. These options are MERGED with the options in supplemental yaml files.
-:libraries:
-  :placement: :end
-  :flag: "${1}"  # or "-L ${1}" for example
-  :common: &common_libraries []
-  :test:
-    - *common_libraries
-  :release:
-    - *common_libraries
-
-:plugins:
-  :load_paths:
-    - vendor/ceedling/plugins
-  :enabled:
-    - stdout_pretty_tests_report
-    - module_generator
-    - raw_output_report
-    - colour_report
-...
diff --git a/test/ceedling b/test/unit-test/ceedling
similarity index 100%
rename from test/ceedling
rename to test/unit-test/ceedling
diff --git a/test/unit-test/project.yml b/test/unit-test/project.yml
new file mode 100644
index 000000000..6c86b0205
--- /dev/null
+++ b/test/unit-test/project.yml
@@ -0,0 +1,437 @@
+# =========================================================================
+#   Ceedling - Test-Centered Build System for C
+#   ThrowTheSwitch.org
+#   Copyright (c) 2010-25 Mike Karlesky, Mark VanderVoord, & Greg Williams
+#   SPDX-License-Identifier: MIT
+# =========================================================================
+
+---
+:project:
+  # how to use ceedling. If you're not sure, leave this as `gem` and `?`
+  :which_ceedling: gem
+  :ceedling_version: 1.0.0
+  :verbosity: 3
+
+  # optional features. If you don't need them, keep them turned off for performance
+  :use_mocks: TRUE
+  :use_test_preprocessor: :mocks # options are :none, :mocks, :tests, or :all
+  :use_deep_dependencies: :all   # options are :none, :mocks, :tests, or :all
+  :use_backtrace: :simple        # options are :none, :simple, or :gdb
+  :use_decorators: :auto         # decorate Ceedling's output text. options are :auto, :all, or :none
+
+  # tweak the way ceedling handles automatic tasks
+  :build_root: _build
+  :test_file_prefix: test_
+  :default_tasks:
+    - test:all
+
+  # performance options. If your tools start giving mysterious errors, consider
+  # dropping this to 1 to force single-tasking
+  :test_threads: 8
+  :compile_threads: 8
+
+  # enable release build (more details in release_build section below)
+  :release_build: FALSE
+
+# Specify where to find mixins and any that should be enabled automatically
+:mixins:
+  :enabled: []
+  :load_paths: []
+
+# further details to configure the way Ceedling handles test code
+:test_build:
+  :use_assembly: FALSE
+
+:test_runner:
+  # Insert additional #include statements in a generated runner
+  :includes:
+    - osal.h
+
+# further details to configure the way Ceedling handles release code
+:release_build:
+  :output: MyApp.out
+  :use_assembly: FALSE
+  :artifacts: []
+
+# Plugins are optional Ceedling features which can be enabled. Ceedling supports
+# a variety of plugins which may effect the way things are compiled, reported,
+# or may provide new command options. Refer to the readme in each plugin for
+# details on how to use it.
+:plugins:
+  :load_paths: []
+  :enabled:
+    #- beep                           # beeps when finished, so you don't waste time waiting for ceedling
+    - module_generator                # handy for quickly creating source, header, and test templates
+    #- gcov                           # test coverage using gcov. Requires gcc, gcov, and a coverage analyzer like gcovr
+    #- bullseye                       # test coverage using bullseye. Requires bullseye for your platform
+    #- command_hooks                  # write custom actions to be called at different points during the build process
+    #- compile_commands_json_db       # generate a compile_commands.json file
+    #- dependencies                   # automatically fetch 3rd party libraries, etc.
+    #- subprojects                    # managing builds and test for static libraries
+    #- fake_function_framework        # use FFF instead of CMock
+
+    # Report options (You'll want to choose one stdout option, but may choose multiple stored options if desired)
+    #- report_build_warnings_log
+    #- report_tests_gtestlike_stdout
+    #- report_tests_ide_stdout
+    #- report_tests_log_factory
+    - report_tests_pretty_stdout
+    #- report_tests_raw_output_log
+    #- report_tests_teamcity_stdout
+
+# Specify which reports you'd like from the log factory
+:report_tests_log_factory:
+  :reports:
+    - json
+    - junit
+    - cppunit
+    - html
+
+# override the default extensions for your system and toolchain
+:extension:
+  #:header: .h
+  #:source: .c
+  #:assembly: .s
+  #:dependencies: .d
+  #:object: .o
+  :executable: .out
+  #:testpass: .pass
+  #:testfail: .fail
+  #:subprojects: .a
+
+# This is where Ceedling should look for your source and test files.
+# see documentation for the many options for specifying this.
+:paths:
+  :test:
+    - +:test/**
+    - -:test/support
+  :source:
+    - ../../src/**
+  :include:
+    - ../../src/**
+  :support:
+    - test/support
+  :libraries: []
+
+# You can even specify specific files to add or remove from your test
+# and release collections. Usually it's better to use paths and let
+# Ceedling do the work for you!
+:files:
+  :test: []
+  :source: []
+
+# Compilation symbols to be injected into builds
+# See documentation for advanced options:
+#  - Test name matchers for different symbols per test executable build
+#  - Referencing symbols in multiple lists using advanced YAML
+#  - Specifying symbols used during test preprocessing
+:defines:
+  :test:
+    - _UNITY_TEST_
+  :release: []
+
+  # Enable to inject name of a test as a unique compilation symbol into its respective executable build.
+  :use_test_definition: FALSE
+
+# Configure additional command line flags provided to tools used in each build step
+# :flags:
+#   :release:
+#     :compile:         # Add '-Wall' and '--02' to compilation of all files in release target
+#       - -Wall
+#       - --O2
+#   :test:
+#     :compile:
+#       '(_|-)special': # Add '-pedantic' to compilation of all files in all test executables with '_special' or '-special' in their names
+#         - -pedantic
+#       '*':            # Add '-foo' to compilation of all files in all test executables
+#         - -foo
+
+# Configuration Options specific to CMock. See CMock docs for details
+:cmock:
+  # Core configuration
+  :plugins:                        # What plugins should be used by CMock?
+    - :ignore
+    - :ignore_arg
+    - :return_thru_ptr
+    - :callback
+    - :array
+  :verbosity:  2                   # the options being 0 errors only, 1 warnings and errors, 2 normal info, 3 verbose
+  :when_no_prototypes:  :warn      # the options being :ignore, :warn, or :error
+
+  # File configuration
+  :skeleton_path:  ''              # Subdirectory to store stubs when generated (default: '')
+  :mock_prefix:  'mock_'           # Prefix to append to filenames for mocks
+  :mock_suffix:  ''                # Suffix to append to filenames for mocks
+
+  # Parser configuration
+  :strippables:  ['(?:__attribute__\s*\([ (]*.*?[ )]*\)+)']
+  :attributes:
+     - __ramfunc
+     - __irq
+     - __fiq
+     - register
+     - extern
+  :c_calling_conventions:
+     - __stdcall
+     - __cdecl
+     - __fastcall
+  :treat_externs:  :exclude        # the options being :include or :exclud
+  :treat_inlines:  :exclude        # the options being :include or :exclud
+
+  # Type handling configuration
+  #:unity_helper_path: ''          # specify a string of where to find a unity_helper.h file to discover custom type assertions
+  :treat_as:                       # optionally add additional types to map custom types
+    uint8:    HEX8
+    uint16:   HEX16
+    uint32:   UINT32
+    int8:     INT8
+    bool:     UINT8
+  #:treat_as_array:  {}            # hint to cmock that these types are pointers to something
+  #:treat_as_void:  []             # hint to cmock that these types are actually aliases of void
+  :memcmp_if_unknown:  true        # allow cmock to use the memory comparison assertions for unknown types
+  :when_ptr:  :compare_data        # hint to cmock how to handle pointers in general, the options being :compare_ptr, :compare_data, or :smart
+
+  # Mock generation configuration
+  :weak:  ''                       # Symbol to use to declare weak functions
+  :enforce_strict_ordering: true   # Do we want cmock to enforce ordering of all function calls?
+  :fail_on_unexpected_calls: true  # Do we want cmock to fail when it encounters a function call that wasn't expected?
+  :callback_include_count: true    # Do we want cmock to include the number of calls to this callback, when using callbacks?
+  :callback_after_arg_check: false # Do we want cmock to enforce an argument check first when using a callback?
+  #:includes: []                   # You can add additional includes here, or specify the location with the options below
+  #:includes_h_pre_orig_header: []
+  #:includes_h_post_orig_header: []
+  #:includes_c_pre_header:  []
+  #:includes_c_post_header:  []
+  #:array_size_type:  []            # Specify a type or types that should be used for array lengths
+  #:array_size_name:  'size|len'    # Specify a name or names that CMock might automatically recognize as the length of an array
+  :exclude_setjmp_h:  false        # Don't use setjmp when running CMock. Note that this might result in late reporting or out-of-order failures.
+
+# Configuration options specific to Unity.
+:unity:
+  :defines:
+    - UNITY_EXCLUDE_FLOAT
+
+# You can optionally have ceedling create environment variables for you before
+# performing the rest of its tasks.
+:environment: []
+# :environment:
+#   # List enforces order allowing later to reference earlier with inline Ruby substitution
+#   - :var1: value
+#   - :var2: another value
+#   - :path:            # Special PATH handling with platform-specific path separators
+#     - #{ENV['PATH']}  # Environment variables can use inline Ruby substitution
+#     - /another/path/to/include
+
+# LIBRARIES
+# These libraries are automatically injected into the build process. Those specified as
+# common will be used in all types of builds. Otherwise, libraries can be injected in just
+# tests or releases. These options are MERGED with the options in supplemental yaml files.
+:libraries:
+  :placement: :end
+  :flag: "-l${1}"
+  :path_flag: "-L ${1}"
+  :system: []    # for example, you might list 'm' to grab the math library
+  :test: []
+  :release: []
+
+################################################################
+# PLUGIN CONFIGURATION
+################################################################
+
+# Add -gcov to the plugins list to make sure of the gcov plugin
+# You will need to have gcov and gcovr both installed to make it work.
+# For more information on these options, see docs in plugins/gcov
+:gcov:
+  :summaries: TRUE                # Enable simple coverage summaries to console after tests
+  :report_task: FALSE             # Disabled dedicated report generation task (this enables automatic report generation)
+  :utilities:
+    - gcovr           # Use gcovr to create the specified reports (default).
+    #- ReportGenerator # Use ReportGenerator to create the specified reports.
+  :reports: # Specify one or more reports to generate.
+    # Make an HTML summary report.
+    - HtmlBasic
+    # - HtmlDetailed
+    # - Text
+    # - Cobertura
+    # - SonarQube
+    # - JSON
+    # - HtmlInline
+    # - HtmlInlineAzure
+    # - HtmlInlineAzureDark
+    # - HtmlChart
+    # - MHtml
+    # - Badges
+    # - CsvSummary
+    # - Latex
+    # - LatexSummary
+    # - PngChart
+    # - TeamCitySummary
+    # - lcov
+    # - Xml
+    # - XmlSummary
+  :gcovr:
+    # :html_artifact_filename: TestCoverageReport.html
+    # :html_title: Test Coverage Report
+    :html_medium_threshold: 75
+    :html_high_threshold: 90
+    # :html_absolute_paths: TRUE
+    # :html_encoding: UTF-8
+
+# :module_generator:
+#   :project_root: ./
+#   :source_root: source/
+#   :inc_root: includes/
+#   :test_root: tests/
+#   :naming: :snake #options: :bumpy, :camel, :caps, or :snake
+#   :includes:
+#     :tst: []
+#     :src: []
+#   :boilerplates:
+#     :src: ""
+#     :inc: ""
+#     :tst: ""
+
+# :dependencies:
+#   :libraries:
+#     - :name: WolfSSL
+#       :source_path:   third_party/wolfssl/source
+#       :build_path:    third_party/wolfssl/build
+#       :artifact_path: third_party/wolfssl/install
+#       :fetch:
+#         :method: :zip
+#         :source: \\shared_drive\third_party_libs\wolfssl\wolfssl-4.2.0.zip
+#       :environment:
+#         - CFLAGS+=-DWOLFSSL_DTLS_ALLOW_FUTURE
+#       :build:
+#         - "autoreconf -i"
+#         - "./configure --enable-tls13 --enable-singlethreaded"
+#         - make
+#         - make install
+#       :artifacts:
+#         :static_libraries:
+#           - lib/wolfssl.a
+#         :dynamic_libraries:
+#           - lib/wolfssl.so
+#         :includes:
+#           - include/**
+
+# :subprojects:
+#   :paths:
+#    - :name: libprojectA
+#      :source:
+#        - ./subprojectA/source
+#      :include:
+#        - ./subprojectA/include
+#      :build_root: ./subprojectA/build
+#      :defines: []
+
+# :command_hooks:
+#   :pre_mock_preprocess:
+#   :post_mock_preprocess:
+#   :pre_test_preprocess:
+#   :post_test_preprocess:
+#   :pre_mock_generate:
+#   :post_mock_generate:
+#   :pre_runner_generate:
+#   :post_runner_generate:
+#   :pre_compile_execute:
+#   :post_compile_execute:
+#   :pre_link_execute:
+#   :post_link_execute:
+#   :pre_test_fixture_execute:
+#   :post_test_fixture_execute:
+#   :pre_test:
+#   :post_test:
+#   :pre_release:
+#   :post_release:
+#   :pre_build:
+#   :post_build:
+#   :post_error:
+
+################################################################
+# TOOLCHAIN CONFIGURATION
+################################################################
+
+#:tools:
+# Ceedling defaults to using gcc for compiling, linking, etc.
+# As [:tools] is blank, gcc will be used (so long as it's in your system path)
+# See documentation to configure a given toolchain for use
+#:tools:
+#  :test_compiler:
+#     :executable: gcc
+#     :name: 'gcc compiler'
+#     :arguments:
+#        - -I"$": COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE               #expands to -I search paths
+#        - -I"$": COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR   #expands to -I search paths
+#        - -D$: COLLECTION_DEFINES_TEST_AND_VENDOR  #expands to all -D defined symbols
+#        #- -fsanitize=address
+#        - -c ${1}                       #source code input file (Ruby method call param list sub)
+#        - -o ${2}                       #object file output (Ruby method call param list sub)
+#  :test_linker:
+#     :executable: gcc
+#     :name: 'gcc linker'
+#     :arguments:
+#        #- -fsanitize=address
+#        - ${1}               #list of object files to link (Ruby method call param list sub)
+#        - -o ${2}            #executable file output (Ruby method call param list sub)
+#   :test_compiler:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :test_linker:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :test_assembler:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :test_fixture:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :test_includes_preprocessor:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :test_file_preprocessor:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :test_file_preprocessor_directives:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :test_dependencies_generator:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :release_compiler:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :release_linker:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :release_assembler:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+#   :release_dependencies_generator:
+#     :executable:
+#     :arguments: []
+#     :name:
+#     :optional: FALSE
+...
diff --git a/test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c
similarity index 95%
rename from test/test/device/msc/test_msc_device.c
rename to test/unit-test/test/device/msc/test_msc_device.c
index 00bb86ccf..3ab46b0f9 100644
--- a/test/test/device/msc/test_msc_device.c
+++ b/test/unit-test/test/device/msc/test_msc_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, hathach (tinyusb.org)
@@ -28,11 +28,12 @@
 #include "unity.h"
 
 // Files to test
+#include "osal/osal.h"
 #include "tusb_fifo.h"
 #include "tusb.h"
 #include "usbd.h"
-TEST_FILE("usbd_control.c")
-TEST_FILE("msc_device.c")
+TEST_SOURCE_FILE("usbd_control.c")
+TEST_SOURCE_FILE("msc_device.c")
 
 // Mock File
 #include "mock_dcd.h"
@@ -41,6 +42,10 @@ TEST_FILE("msc_device.c")
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
+uint32_t tusb_time_millis_api(void) {
+  return 0;
+}
+
 enum
 {
   EDPT_CTRL_OUT = 0x00,
@@ -196,10 +201,14 @@ void setUp(void)
   dcd_int_disable_Ignore();
   dcd_int_enable_Ignore();
 
-  if ( !tusb_inited() )
-  {
-    dcd_init_Expect(rhport);
-    tusb_init();
+  if ( !tud_inited() ) {
+    tusb_rhport_init_t dev_init = {
+      .role = TUSB_ROLE_DEVICE,
+      .speed = TUSB_SPEED_AUTO
+    };
+
+    dcd_init_ExpectAndReturn(0, &dev_init, true);
+    tusb_init(0, &dev_init);
   }
 
   dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, false);
diff --git a/test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c
similarity index 93%
rename from test/test/device/usbd/test_usbd.c
rename to test/unit-test/test/device/usbd/test_usbd.c
index c90383b57..f0153da3f 100644
--- a/test/test/device/usbd/test_usbd.c
+++ b/test/unit-test/test/device/usbd/test_usbd.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -25,10 +25,11 @@
 #include "unity.h"
 
 // Files to test
+#include "osal/osal.h"
 #include "tusb_fifo.h"
 #include "tusb.h"
 #include "usbd.h"
-TEST_FILE("usbd_control.c")
+TEST_SOURCE_FILE("usbd_control.c")
 
 // Mock File
 #include "mock_dcd.h"
@@ -38,6 +39,10 @@ TEST_FILE("usbd_control.c")
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
+uint32_t tusb_time_millis_api(void) {
+  return 0;
+}
+
 enum
 {
   EDPT_CTRL_OUT = 0x00,
@@ -101,38 +106,38 @@ uint8_t const* desc_configuration;
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
-uint8_t const * tud_descriptor_device_cb(void)
-{
+uint8_t const * tud_descriptor_device_cb(void) {
   return desc_device;
 }
 
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index) {
   return desc_configuration;
 }
 
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
 
   return NULL;
 }
 
-void setUp(void)
-{
+void setUp(void) {
   dcd_int_disable_Ignore();
   dcd_int_enable_Ignore();
 
-  if ( !tusb_inited() )
-  {
+  if ( !tud_inited() ) {
+    tusb_rhport_init_t dev_init = {
+      .role = TUSB_ROLE_DEVICE,
+      .speed = TUSB_SPEED_AUTO
+    };
+
     mscd_init_Expect();
-    dcd_init_Expect(rhport);
-    tusb_init();
+    dcd_init_ExpectAndReturn(0, &dev_init, true);
+
+    tusb_init(0, &dev_init);
   }
 }
 
-void tearDown(void)
-{
+void tearDown(void) {
 }
 
 //--------------------------------------------------------------------+
diff --git a/test/test/support/tusb_config.h b/test/unit-test/test/support/tusb_config.h
similarity index 98%
rename from test/test/support/tusb_config.h
rename to test/unit-test/test/support/tusb_config.h
index 0455f933b..00818fae5 100644
--- a/test/test/support/tusb_config.h
+++ b/test/unit-test/test/support/tusb_config.h
@@ -51,7 +51,7 @@
 
 // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
 #ifndef CFG_TUSB_DEBUG
-#define CFG_TUSB_DEBUG           0
+#define CFG_TUSB_DEBUG           1
 #endif
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
diff --git a/test/unit-test/test/test_common_func.c b/test/unit-test/test/test_common_func.c
new file mode 100644
index 000000000..981531dd7
--- /dev/null
+++ b/test/unit-test/test/test_common_func.c
@@ -0,0 +1,82 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <string.h>
+#include "unity.h"
+
+#include "tusb_common.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+
+//------------- IMPLEMENTATION -------------//
+
+void setUp(void)
+{
+}
+
+void tearDown(void)
+{
+}
+
+void test_TU_ARGS_NUM(void)
+{
+  TEST_ASSERT_EQUAL( 0, TU_ARGS_NUM());
+  TEST_ASSERT_EQUAL( 1, TU_ARGS_NUM(a1));
+  TEST_ASSERT_EQUAL( 2, TU_ARGS_NUM(a1, a2));
+  TEST_ASSERT_EQUAL( 3, TU_ARGS_NUM(a1, a2, a3));
+  TEST_ASSERT_EQUAL( 4, TU_ARGS_NUM(a1, a2, a3, a4));
+  TEST_ASSERT_EQUAL( 5, TU_ARGS_NUM(a1, a2, a3, a4, a5));
+  TEST_ASSERT_EQUAL( 6, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6));
+  TEST_ASSERT_EQUAL( 7, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7));
+  TEST_ASSERT_EQUAL( 8, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8));
+  TEST_ASSERT_EQUAL( 9, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9));
+  TEST_ASSERT_EQUAL(10, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10));
+  TEST_ASSERT_EQUAL(11, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11));
+  TEST_ASSERT_EQUAL(12, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12));
+  TEST_ASSERT_EQUAL(13, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13));
+  TEST_ASSERT_EQUAL(14, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14));
+  TEST_ASSERT_EQUAL(15, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15));
+  TEST_ASSERT_EQUAL(16, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16));
+  TEST_ASSERT_EQUAL(17, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17));
+  TEST_ASSERT_EQUAL(18, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18));
+  TEST_ASSERT_EQUAL(19, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19));
+  TEST_ASSERT_EQUAL(20, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20));
+  TEST_ASSERT_EQUAL(21, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21));
+  TEST_ASSERT_EQUAL(22, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22));
+  TEST_ASSERT_EQUAL(23, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23));
+  TEST_ASSERT_EQUAL(24, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24));
+  TEST_ASSERT_EQUAL(25, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25));
+  TEST_ASSERT_EQUAL(26, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26));
+  TEST_ASSERT_EQUAL(27, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27));
+  TEST_ASSERT_EQUAL(28, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28));
+  TEST_ASSERT_EQUAL(29, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29));
+  TEST_ASSERT_EQUAL(30, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30));
+  TEST_ASSERT_EQUAL(31, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30, a31));
+  TEST_ASSERT_EQUAL(32, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30, a31, a32));
+}
diff --git a/test/test/test_fifo.c b/test/unit-test/test/test_fifo.c
similarity index 62%
rename from test/test/test_fifo.c
rename to test/unit-test/test/test_fifo.c
index 0a5f4d3b9..3b4deb33e 100644
--- a/test/test/test_fifo.c
+++ b/test/unit-test/test/test_fifo.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -26,17 +26,27 @@
 
 #include <string.h>
 #include "unity.h"
+
+#include "osal/osal.h"
 #include "tusb_fifo.h"
 
-#define FIFO_SIZE 10
-TU_FIFO_DEF(tu_ff, FIFO_SIZE, uint8_t, false);
+#define FIFO_SIZE   64
+uint8_t tu_ff_buf[FIFO_SIZE * sizeof(uint8_t)];
+tu_fifo_t tu_ff = TU_FIFO_INIT(tu_ff_buf, FIFO_SIZE, uint8_t, false);
+
 tu_fifo_t* ff = &tu_ff;
 tu_fifo_buffer_info_t info;
 
+uint8_t test_data[4096];
+uint8_t rd_buf[FIFO_SIZE];
+
 void setUp(void)
 {
   tu_fifo_clear(ff);
   memset(&info, 0, sizeof(tu_fifo_buffer_info_t));
+
+  for(int i=0; i<sizeof(test_data); i++) test_data[i] = i;
+  memset(rd_buf, 0, sizeof(rd_buf));
 }
 
 void tearDown(void)
@@ -60,86 +70,136 @@ void test_normal(void)
 
 void test_item_size(void)
 {
-  TU_FIFO_DEF(ff4, FIFO_SIZE, uint32_t, false);
-  tu_fifo_clear(&ff4);
+  uint8_t ff4_buf[FIFO_SIZE * sizeof(uint32_t)];
+  tu_fifo_t ff4 = TU_FIFO_INIT(ff4_buf, FIFO_SIZE, uint32_t, false);
 
-  uint32_t data[20];
-  for(uint32_t i=0; i<sizeof(data)/4; i++) data[i] = i;
+  uint32_t data4[2*FIFO_SIZE];
+  for(uint32_t i=0; i<sizeof(data4)/4; i++) data4[i] = i;
 
-  tu_fifo_write_n(&ff4, data, 10);
+  // fill up fifo
+  tu_fifo_write_n(&ff4, data4, FIFO_SIZE);
 
-  uint32_t rd[10];
+  uint32_t rd_buf4[FIFO_SIZE];
   uint16_t rd_count;
 
   // read 0 -> 4
-  rd_count = tu_fifo_read_n(&ff4, rd, 5);
+  rd_count = tu_fifo_read_n(&ff4, rd_buf4, 5);
   TEST_ASSERT_EQUAL( 5, rd_count );
-  TEST_ASSERT_EQUAL_UINT32_ARRAY( data, rd, rd_count ); // 0 -> 4
+  TEST_ASSERT_EQUAL_UINT32_ARRAY( data4, rd_buf4, rd_count ); // 0 -> 4
 
-  tu_fifo_write_n(&ff4, data+10, 5);
+  tu_fifo_write_n(&ff4, data4+FIFO_SIZE, 5);
 
-  // read 5 -> 14
-  rd_count = tu_fifo_read_n(&ff4, rd, 10);
-  TEST_ASSERT_EQUAL( 10, rd_count );
-  TEST_ASSERT_EQUAL_UINT32_ARRAY( data+5, rd, rd_count ); // 5 -> 14
+  // read all 5 -> 68
+  rd_count = tu_fifo_read_n(&ff4, rd_buf4, FIFO_SIZE);
+  TEST_ASSERT_EQUAL( FIFO_SIZE, rd_count );
+  TEST_ASSERT_EQUAL_UINT32_ARRAY( data4+5, rd_buf4, rd_count ); // 5 -> 68
 }
 
 void test_read_n(void)
 {
-  // prepare data
-  uint8_t data[20];
-  for(int i=0; i<sizeof(data); i++) data[i] = i;
-
-  for(uint8_t i=0; i < FIFO_SIZE; i++) tu_fifo_write(ff, data+i);
-
-  uint8_t rd[10];
   uint16_t rd_count;
 
+  // fill up fifo
+  for(uint8_t i=0; i < FIFO_SIZE; i++) tu_fifo_write(ff, test_data+i);
+
   // case 1: Read index + count < depth
   // read 0 -> 4
-  rd_count = tu_fifo_read_n(ff, rd, 5);
+  rd_count = tu_fifo_read_n(ff, rd_buf, 5);
   TEST_ASSERT_EQUAL( 5, rd_count );
-  TEST_ASSERT_EQUAL_MEMORY( data, rd, rd_count ); // 0 -> 4
+  TEST_ASSERT_EQUAL_MEMORY( test_data, rd_buf, rd_count ); // 0 -> 4
 
   // case 2: Read index + count > depth
   // write 10, 11, 12
-  tu_fifo_write(ff, data+10);
-  tu_fifo_write(ff, data+11);
-  tu_fifo_write(ff, data+12);
+  tu_fifo_write(ff, test_data+FIFO_SIZE);
+  tu_fifo_write(ff, test_data+FIFO_SIZE+1);
+  tu_fifo_write(ff, test_data+FIFO_SIZE+2);
 
-  rd_count = tu_fifo_read_n(ff, rd, 7);
+  rd_count = tu_fifo_read_n(ff, rd_buf, 7);
   TEST_ASSERT_EQUAL( 7, rd_count );
 
-  TEST_ASSERT_EQUAL_MEMORY( data+5, rd, rd_count ); // 5 -> 11
+  TEST_ASSERT_EQUAL_MEMORY( test_data+5, rd_buf, rd_count ); // 5 -> 11
 
   // Should only read until empty
-  TEST_ASSERT_EQUAL( 1, tu_fifo_read_n(ff, rd, 100) );
+  TEST_ASSERT_EQUAL( FIFO_SIZE-5+3-7, tu_fifo_read_n(ff, rd_buf, 100) );
 }
 
 void test_write_n(void)
 {
-  // prepare data
-  uint8_t data[20];
-  for(int i=0; i<sizeof(data); i++) data[i] = i;
-
   // case 1: wr + count < depth
-  tu_fifo_write_n(ff, data, 8); // wr = 8, count = 8
+  tu_fifo_write_n(ff, test_data, 32); // wr = 32, count = 32
 
-  uint8_t rd[10];
   uint16_t rd_count;
 
-  rd_count = tu_fifo_read_n(ff, rd, 5); // wr = 8, count = 3
-  TEST_ASSERT_EQUAL( 5, rd_count );
-  TEST_ASSERT_EQUAL_MEMORY( data, rd, rd_count ); // 0 -> 4
+  rd_count = tu_fifo_read_n(ff, rd_buf, 16); // wr = 32, count = 16
+  TEST_ASSERT_EQUAL( 16, rd_count );
+  TEST_ASSERT_EQUAL_MEMORY( test_data, rd_buf, rd_count );
 
   // case 2: wr + count > depth
-  tu_fifo_write_n(ff, data+8, 6); // wr = 3, count = 9
+  tu_fifo_write_n(ff, test_data+32, 40); // wr = 72 -> 8, count = 56
 
-  for(rd_count=0; rd_count<7; rd_count++) tu_fifo_read(ff, rd+rd_count); // wr = 3, count = 2
+  tu_fifo_read_n(ff, rd_buf, 32); // count = 24
+  TEST_ASSERT_EQUAL_MEMORY( test_data+16, rd_buf, rd_count);
 
-  TEST_ASSERT_EQUAL_MEMORY( data+5, rd, rd_count); // 5 -> 11
+  TEST_ASSERT_EQUAL(24, tu_fifo_count(ff));
+}
 
-  TEST_ASSERT_EQUAL(2, tu_fifo_count(ff));
+void test_write_double_overflowed(void)
+{
+  tu_fifo_set_overwritable(ff, true);
+
+  uint8_t rd_buf[FIFO_SIZE] = { 0 };
+  uint8_t* buf = test_data;
+
+  // full
+  buf += tu_fifo_write_n(ff, buf, FIFO_SIZE);
+  TEST_ASSERT_EQUAL(FIFO_SIZE, tu_fifo_count(ff));
+
+  // write more, should still full
+  buf += tu_fifo_write_n(ff, buf, FIFO_SIZE-8);
+  TEST_ASSERT_EQUAL(FIFO_SIZE, tu_fifo_count(ff));
+
+  // double overflowed: in total, write more than > 2*FIFO_SIZE
+  buf += tu_fifo_write_n(ff, buf, 16);
+  TEST_ASSERT_EQUAL(FIFO_SIZE, tu_fifo_count(ff));
+
+  // reading back should give back data from last FIFO_SIZE write
+  tu_fifo_read_n(ff, rd_buf, FIFO_SIZE);
+
+  TEST_ASSERT_EQUAL_MEMORY(buf-16, rd_buf+FIFO_SIZE-16, 16);
+
+  // TODO whole buffer should match, but we deliberately not implement it
+  // TEST_ASSERT_EQUAL_MEMORY(buf-FIFO_SIZE, rd_buf, FIFO_SIZE);
+}
+
+static uint16_t help_write(uint16_t total, uint16_t n)
+{
+  tu_fifo_write_n(ff, test_data, n);
+  total = tu_min16(FIFO_SIZE, total + n);
+
+  TEST_ASSERT_EQUAL(total, tu_fifo_count(ff));
+  TEST_ASSERT_EQUAL(FIFO_SIZE - total, tu_fifo_remaining(ff));
+
+  return total;
+}
+
+void test_write_overwritable2(void)
+{
+  tu_fifo_set_overwritable(ff, true);
+
+  // based on actual crash tests detected by fuzzing
+  uint16_t total = 0;
+
+  total = help_write(total, 12);
+  total = help_write(total, 55);
+  total = help_write(total, 73);
+  total = help_write(total, 55);
+  total = help_write(total, 75);
+  total = help_write(total, 84);
+  total = help_write(total, 1);
+  total = help_write(total, 10);
+  total = help_write(total, 12);
+  total = help_write(total, 25);
+  total = help_write(total, 192);
 }
 
 void test_peek(void)
@@ -315,4 +375,4 @@ void test_rd_idx_wrap()
   n = tu_fifo_read_n(&ff10, dst, 4);
   TEST_ASSERT_EQUAL(n, 2);
   TEST_ASSERT_EQUAL(ff10.rd_idx, 6);
-}
\ No newline at end of file
+}
diff --git a/test/vendor/ceedling/bin/ceedling b/test/vendor/ceedling/bin/ceedling
deleted file mode 100644
index fa099590a..000000000
--- a/test/vendor/ceedling/bin/ceedling
+++ /dev/null
@@ -1,337 +0,0 @@
-#!/usr/bin/env ruby
-
-#these are always used
-require 'rubygems'
-require 'fileutils'
-
-# Check for the main project file (either the one defined in the ENV or the default)
-main_filepath = ENV['CEEDLING_MAIN_PROJECT_FILE']
-project_found = (!main_filepath.nil? && File.exists?(main_filepath))
-if (!project_found)
-  main_filepath = "project.yml"
-  project_found = File.exists?(main_filepath)
-end
-
-def is_windows?
-  return ((RbConfig::CONFIG['host_os'] =~ /mswin|mingw/) ? true : false) if defined?(RbConfig)
-  return ((Config::CONFIG['host_os'] =~ /mswin|mingw/) ? true : false)
-end
-
-unless (project_found)
-#===================================== We Do Not Have A Project ================================================
-
-  puts "Welcome to Ceedling!"
-  require 'thor'
-
-  def here
-    File.dirname(__FILE__) + "/.."
-  end
-
-  class CeedlingTasks < Thor
-    include Thor::Actions
-
-    desc "new PROJECT_NAME", "create a new ceedling project"
-    method_option :docs, :type => :boolean, :default => false, :desc => "Add docs in project vendor directory"
-    method_option :local, :type => :boolean, :default => false, :desc => "Create a copy of Ceedling in the project vendor directory"
-    method_option :gitignore, :type => :boolean, :default => false, :desc => "Create a gitignore file for ignoring ceedling generated files"
-    method_option :no_configs, :type => :boolean, :default => false, :desc => "Don't install starter configuration files"
-    method_option :noconfigs, :type => :boolean, :default => false
-
-    #deprecated:
-    method_option :no_docs, :type => :boolean, :default => false
-    method_option :nodocs, :type => :boolean, :default => false
-    method_option :as_gem, :type => :boolean, :default => false
-    method_option :asgem, :type => :boolean, :default => false
-    method_option :with_ignore, :type => :boolean, :default => false
-    method_option :withignore, :type => :boolean, :default => false
-    def new(name, silent = false)
-      copy_assets_and_create_structure(name, silent, false, options)
-    end
-
-    desc "upgrade PROJECT_NAME", "upgrade ceedling for a project (not req'd if gem used)"
-    method_option :docs, :type => :boolean, :default => false, :desc => "Add docs in project vendor directory"
-    method_option :local, :type => :boolean, :default => false, :desc => "Create a copy of Ceedling in the project vendor directory"
-    method_option :no_configs, :type => :boolean, :default => false, :desc => "Don't install starter configuration files"
-    method_option :noconfigs, :type => :boolean, :default => false
-
-    #deprecated:
-    method_option :no_docs, :type => :boolean, :default => false
-    method_option :nodocs, :type => :boolean, :default => false
-    def upgrade(name, silent = false)
-      copy_assets_and_create_structure(name, silent, true, options || {:upgrade => true})
-    end
-
-    no_commands do
-      def copy_assets_and_create_structure(name, silent=false, force=false, options = {})
-
-        puts "WARNING: --no_docs deprecated. It is now the default. Specify -docs if you want docs installed." if (options[:no_docs] || options[:nodocs])
-        puts "WARNING: --as_gem deprecated. It is now the default. Specify -local if you want ceedling installed to this project." if (options[:as_gem] || options[:asgem])
-        puts "WARNING: --with_ignore deprecated. It is now called -gitignore" if (options[:with_ignore] || options[:with_ignore])
-
-        use_docs     = options[:docs] || false
-        use_configs  = !(options[:no_configs] || options[:noconfigs] || false)
-        use_gem      = !(options[:local])
-        use_ignore   = options[:gitignore] || false
-        is_upgrade   = options[:upgrade] || false
-
-        ceedling_path     = File.join(name, 'vendor', 'ceedling')
-        source_path       = File.join(name, 'src')
-        test_path         = File.join(name, 'test')
-        test_support_path = File.join(name, 'test/support')
-
-        # If it's not an upgrade, make sure we have the paths we expect
-        if (!is_upgrade)
-          [source_path, test_path, test_support_path].each do |d|
-            FileUtils.mkdir_p d
-          end
-        end
-
-        # Genarate gitkeep in test support path
-        FileUtils.touch(File.join(test_support_path, '.gitkeep'))
-
-        # If documentation requested, create a place to dump them and do so
-        if use_docs
-          doc_path = File.join(ceedling_path, 'docs')
-          FileUtils.mkdir_p doc_path
-
-          in_doc_path = lambda {|f| File.join(doc_path, f)}
-
-          doc_files = [
-                        'docs/CeedlingPacket.md',
-                        'vendor/c_exception/docs/CException.md',
-                        'vendor/cmock/docs/CMock_Summary.md',
-                        'vendor/unity/docs/UnityAssertionsCheatSheetSuitableforPrintingandPossiblyFraming.pdf',
-                        'vendor/unity/docs/UnityAssertionsReference.md',
-                        'vendor/unity/docs/UnityConfigurationGuide.md',
-                        'vendor/unity/docs/UnityGettingStartedGuide.md',
-                        'vendor/unity/docs/UnityHelperScriptsGuide.md',
-                        'vendor/unity/docs/ThrowTheSwitchCodingStandard.md',
-                      ]
-
-          doc_files.each do |f|
-            copy_file(f, in_doc_path.call(File.basename(f)), :force => force)
-          end
-        end
-
-        # If installed locally to project, copy ceedling, unity, cmock, & supports to vendor
-        unless use_gem
-          FileUtils.mkdir_p ceedling_path
-
-          #copy full folders from ceedling gem into project
-          %w{plugins lib bin}.map do |f|
-            {:src => f, :dst => File.join(ceedling_path, f)}
-          end.each do |f|
-            directory(f[:src], f[:dst], :force => force)
-          end
-
-          # mark ceedling as an executable
-          File.chmod(0755, File.join(ceedling_path, 'bin', 'ceedling')) unless is_windows?
-
-          #copy necessary subcomponents from ceedling gem into project
-          sub_components = [
-            {:src => 'vendor/c_exception/lib/',     :dst => 'vendor/c_exception/lib'},
-            {:src => 'vendor/cmock/config/',        :dst => 'vendor/cmock/config'},
-            {:src => 'vendor/cmock/lib/',           :dst => 'vendor/cmock/lib'},
-            {:src => 'vendor/cmock/src/',           :dst => 'vendor/cmock/src'},
-            {:src => 'vendor/deep_merge/lib/',      :dst => 'vendor/deep_merge/lib'},
-            {:src => 'vendor/diy/lib',              :dst => 'vendor/diy/lib'},
-            {:src => 'vendor/unity/auto/',          :dst => 'vendor/unity/auto'},
-            {:src => 'vendor/unity/src/',           :dst => 'vendor/unity/src'},
-          ]
-
-          sub_components.each do |c|
-            directory(c[:src], File.join(ceedling_path, c[:dst]), :force => force)
-          end
-        end
-
-        # We're copying in a configuration file if we haven't said not to
-        if (use_configs)
-          if use_gem
-            copy_file(File.join('assets', 'project_as_gem.yml'), File.join(name, 'project.yml'), :force => force)
-          else
-            copy_file(File.join('assets', 'project_with_guts.yml'), File.join(name, 'project.yml'), :force => force)
-            if is_windows?
-              copy_file(File.join('assets', 'ceedling.cmd'), File.join(name, 'ceedling.cmd'), :force => force)
-            else
-              copy_file(File.join('assets', 'ceedling'), File.join(name, 'ceedling'), :force => force)
-              File.chmod(0755, File.join(name, 'ceedling'))
-            end
-          end
-        end
-
-        # Copy the gitignore file if requested
-        if (use_ignore)
-          copy_file(File.join('assets', 'default_gitignore'), File.join(name, '.gitignore'), :force => force)
-        end
-
-        unless silent
-          puts "\n"
-          puts "Project '#{name}' #{force ? "upgraded" : "created"}!"
-          puts " - Tool documentation is located in vendor/ceedling/docs" if use_docs
-          puts " - Execute 'ceedling help' to view available test & build tasks"
-          puts ''
-        end
-      end
-    end
-
-    desc "examples", "list available example projects"
-    def examples()
-      puts "Available sample projects:"
-      FileUtils.cd(File.join(here, "examples")) do
-        Dir["*"].each {|proj| puts "  #{proj}"}
-      end
-    end
-
-    desc "example PROJ_NAME [DEST]", "new specified example project (in DEST, if specified)"
-    def example(proj_name, dest=nil)
-      if dest.nil? then dest = proj_name end
-
-      copy_assets_and_create_structure(dest, true, false, {:local=>true, :docs=>true})
-
-      dest_src      = File.join(dest,'src')
-      dest_test     = File.join(dest,'test')
-      dest_project  = File.join(dest,'project.yml')
-
-      directory "examples/#{proj_name}/src",         dest_src
-      directory "examples/#{proj_name}/test",        dest_test
-      remove_file dest_project
-      copy_file "examples/#{proj_name}/project.yml", dest_project
-
-      puts "\n"
-      puts "Example project '#{proj_name}' created!"
-      puts " - Tool documentation is located in vendor/ceedling/docs"
-      puts " - Execute 'ceedling help' to view available test & build tasks"
-      puts ''
-    end
-
-    desc "version", "return the version of the tools installed"
-    def version()
-      require 'ceedling/version.rb'
-      puts "  Ceedling::   #{Ceedling::Version::CEEDLING}"
-      puts "  CMock::      #{Ceedling::Version::CMOCK}"
-      puts "  Unity::      #{Ceedling::Version::UNITY}"
-      puts "  CException:: #{Ceedling::Version::CEXCEPTION}"
-    end
-  end
-
-  if (ARGV[0] =~ /^\-T$/)
-    puts "\n(No Project Detected, Therefore Showing Options to Create Projects)"
-    CeedlingTasks.tasks.each_pair do |k,v|
-      puts v.usage.ljust(25,' ') + v.description
-    end
-    puts "\n"
-  else
-    CeedlingTasks.source_root here
-    CeedlingTasks.start
-  end
-
-#===================================== We Have A Project Already ================================================
-else
-  require 'yaml'
-  require 'rbconfig'
-
-  #determine platform
-  platform = begin
-    case(RbConfig::CONFIG['host_os'])
-      when /mswin|mingw|cygwin/i
-        :mswin
-      when /darwin/
-        :osx
-      else
-        :linux
-    end
-  rescue
-    :linux
-  end
-
-  #create our default meta-runner option set
-  options = {
-    :pretest => nil,
-    :args => [],
-    :add_path => [],
-    :path_connector => (platform == :mswin) ? ";" : ":",
-    :graceful_fail => false,
-    :which_ceedling => (Dir.exists?("vendor/ceedling") ? "vendor/ceedling" : 'gem'),
-    :default_tasks => [ 'test:all' ],
-    :list_tasks => false
-  }
-
-  #guess that we need a special script file first if it exists
-  if (platform == :mswin)
-    options[:pretest] = File.exists?("#{ platform.to_s }_setup.bat") ? "#{ platform.to_s }_setup.bat" : nil
-  else
-    options[:pretest] = File.exists?("#{ platform.to_s }_setup.sh") ? "source #{ platform.to_s }_setup.sh" : nil
-  end
-
-  #merge in project settings if they can be found here
-  yaml_options = YAML.load_file(main_filepath)
-  if (yaml_options[:paths])
-    options[:add_path] = yaml_options[:paths][:tools] || []
-  else
-    options[:add_path] = []
-  end
-  options[:graceful_fail]  = yaml_options[:graceful_fail] if yaml_options[:graceful_fail]
-  options[:which_ceedling] = yaml_options[:project][:which_ceedling] if (yaml_options[:project] && yaml_options[:project][:which_ceedling])
-  options[:default_tasks]  = yaml_options[:default_tasks] if yaml_options[:default_tasks]
-
-  #sort through command line options
-  ARGV.each do |v|
-    case(v)
-      when /^(?:new|examples?|templates?)$/
-        puts "\nOops. You called ceedling with argument '#{v}'.\n" +
-             "      This is an operation that will create a new project... \n" +
-             "      but it looks like you're already in a project. If you really \n" +
-             "      want to do this, try moving to an empty folder.\n\n"
-        abort
-      when /^help$/
-        options[:list_tasks] = true
-      when /^-T$/
-        options[:list_tasks] = true
-      when /^project:(\w+)/
-        ENV['CEEDLING_USER_PROJECT_FILE'] = "#{$1}.yml"
-      else
-        options[:args].push(v)
-    end
-  end
-
-  #add to the path
-  if (options[:add_path] && !options[:add_path].empty?)
-    path = ENV["PATH"]
-    options[:add_path].each do |p|
-      f = File.expand_path(File.dirname(__FILE__),p)
-      path = (f + options[:path_connector] + path) unless path.include? f
-    end
-    ENV["PATH"] = path
-  end
-
-  # Load Ceedling (either through the rakefile OR directly)
-  if (File.exists?("rakefile.rb"))
-    load 'rakefile.rb'
-  else
-    if (options[:which_ceedling] == 'gem')
-      require 'ceedling'
-    else
-      load "#{options[:which_ceedling]}/lib/ceedling.rb"
-    end
-    Ceedling.load_project
-  end
-
-  Rake.application.standard_exception_handling do
-    if options[:list_tasks]
-      # Display helpful task list when requested. This required us to dig into Rake internals a bit
-      Rake.application.define_singleton_method(:name=) {|n| @name = n}
-      Rake.application.name = 'ceedling'
-      Rake.application.options.show_tasks = :tasks
-      Rake.application.options.show_task_pattern = /^(?!.*build).*$/
-      Rake.application.display_tasks_and_comments()
-    else
-      task :default => options[:default_tasks]
-
-      # Run our Tasks!
-      Rake.application.collect_command_line_tasks(options[:args])
-      Rake.application.top_level
-    end
-  end
-  true
-#===================================================================================================================
-end
diff --git a/test/vendor/ceedling/docs/CException.md b/test/vendor/ceedling/docs/CException.md
deleted file mode 100644
index c3718191f..000000000
--- a/test/vendor/ceedling/docs/CException.md
+++ /dev/null
@@ -1,292 +0,0 @@
-
-CException
-==========
-
-CException is a basic exception framework for C, suitable for use in
-embedded applications.  It provides an exception framework similar in
-use to C++, but with much less overhead.
-
-
-CException uses C standard library functions `setjmp` and `longjmp` to
-operate.  As long as the target system has these two functions defined,
-this library should be useable with very little configuration.  It
-even supports environments where multiple program flows are in use,
-such as real-time operating systems.
-
-
-There are about a gabillion exception frameworks using a similar
-setjmp/longjmp method out there... and there will probably be more
-in the future. Unfortunately, when we started our last embedded
-project, all those that existed either (a) did not support multiple
-tasks (therefore multiple stacks) or (b) were way more complex than
-we really wanted.  CException was born.
-
-
-*Why use CException?*
-
-
-0. It's ANSI C, and it beats passing error codes around.
-1. You want something simple... CException throws a single id. You can
-   define those ID's to be whatever you like. You might even choose which
-   type that number is for your project. But that's as far as it goes.
-   We weren't interested in passing objects or structs or strings...
-   just simple error codes.
-2. Performance... CException can be configured for single tasking or
-   multitasking. In single tasking, there is very little overhead past
-   the setjmp/longjmp calls (which are already fast). In multitasking,
-   your only additional overhead is the time it takes you to determine
-   a unique task id 0 - num_tasks.
-
-
-For the latest version, go to [ThrowTheSwitch.org](http://throwtheswitch.org)
-
-
-CONTENTS OF THIS DOCUMENT
-=========================
-
-* Usage
-* Limitations
-*API
-* Configuration
-* Testing
-* License
-
-
-Usage
------
-
-Code that is to be protected are wrapped in `Try { } Catch { }` blocks.
-The code directly following the Try call is "protected", meaning that
-if any Throws occur, program control is directly transferred to the
-start of the Catch block.
-
-
-A numerical exception ID is included with Throw, and is made accessible
-from the Catch block.
-
-
-Throws can occur from within function calls (nested as deeply as you
-like) or directly from within the function itself.
-
-
-
-Limitations
------------
-
-
-This library was made to be as fast as possible, and provide basic
-exception handling.  It is not a full-blown exception library.  Because
-of this, there are a few limitations that should be observed in order
-to successfully utilize this library:
-
-1. Do not directly "return" from within a `Try` block, nor `goto`
-   into or out of a `Try` block.
-
-   *Why?*
-
-   The `Try` macro allocates some local memory and alters a global
-   pointer.  These are cleaned up at the top of the `Catch` macro.
-   Gotos and returns would bypass some of these steps, resulting in
-   memory leaks or unpredictable behavior.
-
-
-2. If (a) you change local (stack) variables within your `Try` block,
-   AND (b) wish to make use of the updated values after an exception
-   is thrown, those variables should be made `volatile`. Note that this
-   is ONLY for locals and ONLY when you need access to them after a
-   `Throw`.
-
-   *Why?*
-
-   Compilers optimize.  There is no way to guarantee that the actual
-   memory location was updated and not just a register unless the
-   variable is marked volatile.
-
-
-3. Memory which is `malloc`'d or `new`'d is not automatically released
-   when an error is thrown.  This will sometimes be desirable, and
-   othertimes may not.  It will be the responsibility of the `Catch`
-   block to perform this kind of cleanup.
-
-   *Why?*
-
-   There's just no easy way to track `malloc`'d memory, etc., without
-   replacing or wrapping malloc calls or something like that.  This
-   is a light framework, so these options were not desirable.
-
-
-
-API
----
-
-###Try
-
-`Try` is a macro which starts a protected block.  It MUST be followed by
-a pair of braces or a single protected line (similar to an 'if'),
-enclosing the data that is to be protected.  It **must** be followed by a
-`Catch` block (don't worry, you'll get compiler errors to let you know if
-you mess any of that up).
-
-
-###Catch(e)
-
-`Catch` is a macro which ends the `Try` block and starts the error handling
-block. The `Catch` block is called if and only if an exception was thrown
-while within the `Try` block.  This error was thrown by a `Throw` call
-somewhere within `Try` (or within a function called within `Try`, or a function
-called by a function called within `Try`, etc).
-
-The single parameter `e` is filled with the error code which was thrown.
-This can be used for reporting, conditional cleanup, etc. (or you can just
-ignore it if you really want... people ignore return codes all the time,
-right?).  `e` should be of type `EXCEPTION_T`
-
-
-###Throw(e)
-
-This is the method of throwing an error. A `Throw` should only occur from within a
-protected (`Try` ... `Catch`) block, though it may easily be nested many function
-calls deep without an impact on performance or functionality. `Throw` takes
-a single argument, which is an exception id which will be passed to `Catch`
-as the reason for the error.
-
-If you wish to rethrow an error, this can be done by calling `Throw(e)` with
-the error code you just caught.  It **is** valid to throw from a catch block.
-
-
-###ExitTry()
-
-On rare occasion, you might want to immediately exit your current `Try` block
-but **not** treat this as an error. Don't run the `Catch`. Just start executing
-from after the `Catch` as if nothing had happened... That's what `ExitTry` is
-for.
-
-
-CONFIGURATION
--------------
-
-CException is a mostly portable library.  It has one universal
-dependency, and some macros which are required if working in a
-multi-tasking environment.
-
-1. The standard C library setjmp must be available.  Since this is part
-   of the standard library, chances are good that you'll be fine.
-
-2. If working in a multitasking environment, methods for obtaining an
-   index into an array of frames and to get the overall number of
-   id's are required.  If the OS supports a method to retrieve Task
-   ID's, and those Tasks are number 0, 1, 2... you are in an ideal
-   situation.  Otherwise, a more creative mapping function may be
-   required.  Note that this function is likely to be called twice
-   for each protected block and once during a throw.  This is the
-   only overhead in the system.
-
-
-Exception.h
------------
-
-By convention, most projects include `Exception.h` which defines any
-further requirements, then calls `CException.h` to do the gruntwork.  All
-of these are optional.  You could directly include `CException.h` if
-you wanted and just use the defaults provided.
-
-* `EXCEPTION_T`
-  * Set this to the type you want your exception id's to be.  Defaults to 'unsigned int'.
-
-* `EXCEPTION_NONE`
-  * Set this to a number which will never be an exception id in your system.  Defaults to `0x5a5a5a5a`.
-
-* `EXCEPTION_GET_ID`
-  * If in a multi-tasking environment, this should be
-    set to be a call to the function described in #2 above.
-    Defaults to just return `0` all the time (good for
-    single tasking environments)
-
-* `EXCEPTION_NUM_ID`
-  * If in a multi-tasking environment, this should be set
-    to the number of ID's required (usually the number of
-    tasks in the system).  Defaults to `1` (for single
-    tasking environments).
-
-* `CEXCEPTION_NO_CATCH_HANDLER(id)`
-  * This macro can be optionally specified.
-    It allows you to specify code to be called when a Throw
-    is made outside of `Try` ... `Catch` protection.  Consider
-    this the emergency fallback plan for when something has
-    gone terribly wrong.
-
-
-You may also want to include any header files which will commonly be
-needed by the rest of your application where it uses exception handling
-here.  For example, OS header files or exception codes would be useful.
-
-
-Finally, there are some hook macros which you can implement to inject
-your own target-specific code in particular places. It is a rare instance
-where you will need these, but they are here if you need them:
-
-
-* `CEXCEPTION_HOOK_START_TRY`
-  * called immediately before the Try block
-
-* `CEXCEPTION_HOOK_HAPPY_TRY`
-  * called immediately after the Try block if no exception was thrown
-
-* `CEXCEPTION_HOOK_AFTER_TRY`
-  * called immediately after the Try block OR before an exception is caught
-
-* `CEXCEPTION_HOOK_START_CATCH`
-  * called immediately before the catch
-
-
-
-TESTING
--------
-
-
-If you want to validate that CException works with your tools or that
-it works with your custom configuration, you may want to run the test
-suite.
-
-
-The test suite included makes use of the `Unity` Test Framework.  It will
-require a native C compiler. The example makefile uses MinGW's gcc.
-Modify the makefile to include the proper paths to tools, then run `make`
-to compile and run the test application.
-
-* `C_COMPILER`
-  * The C compiler to use to perform the tests
-
-* `C_LIBS`
-  * The path to the C libraries (including setjmp)
-
-* `UNITY_DIR`
-  * The path to the Unity framework (required to run tests)
-    (get it at [ThrowTheSwitch.org](http://throwtheswitch.org))
-
-
-
-LICENSE
--------
-
-This software is licensed under the MIT License
-
-Copyright (c) 2007-2017 Mark VanderVoord
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
diff --git a/test/vendor/ceedling/docs/CMock_Summary.md b/test/vendor/ceedling/docs/CMock_Summary.md
deleted file mode 100644
index 87f9c00b8..000000000
--- a/test/vendor/ceedling/docs/CMock_Summary.md
+++ /dev/null
@@ -1,603 +0,0 @@
-CMock: A Summary
-================
-
-*[ThrowTheSwitch.org](http://throwtheswitch.org)*
-
-*This documentation is released under a Creative Commons 3.0 Attribution Share-Alike License*
-
-
-What Exactly Are We Talking About Here?
----------------------------------------
-
-CMock is a nice little tool which takes your header files and creates
-a Mock interface for it so that you can more easily unit test modules
-that touch other modules. For each function prototype in your
-header, like this one:
-
-    int DoesSomething(int a, int b);
-
-
-...you get an automatically generated DoesSomething function
-that you can link to instead of your real DoesSomething function.
-By using this Mocked version, you can then verify that it receives
-the data you want, and make it return whatever data you desire,
-make it throw errors when you want, and more... Create these for
-everything your latest real module touches, and you're suddenly
-in a position of power: You can control and verify every detail
-of your latest creation.
-
-To make that easier, CMock also gives you a bunch of functions
-like the ones below, so you can tell that generated DoesSomething
-function how to behave for each test:
-
-    void DoesSomething_ExpectAndReturn(int a, int b, int toReturn);
-    void DoesSomething_ExpectAndThrow(int a, int b, EXCEPTION_T error);
-    void DoesSomething_StubWithCallback(CMOCK_DoesSomething_CALLBACK YourCallback);
-    void DoesSomething_IgnoreAndReturn(int toReturn);
-
-
-You can pile a bunch of these back to back, and it remembers what
-you wanted to pass when, like so:
-
-    test_CallsDoesSomething_ShouldDoJustThat(void)
-    {
-        DoesSomething_ExpectAndReturn(1,2,3);
-        DoesSomething_ExpectAndReturn(4,5,6);
-        DoesSomething_ExpectAndThrow(7,8, STATUS_ERROR_OOPS);
-
-        CallsDoesSomething( );
-    }
-
-
-This test will call CallsDoesSomething, which is the function
-we are testing. We are expecting that function to call DoesSomething
-three times. The first time, we check to make sure it's called
-as DoesSomething(1, 2) and we'll magically return a 3. The second
-time we check for DoesSomething(4, 5) and we'll return a 6. The
-third time we verify DoesSomething(7, 8) and we'll throw an error
-instead of returning anything. If CallsDoesSomething gets
-any of this wrong, it fails the test. It will fail if you didn't
-call DoesSomething enough, or too much, or with the wrong arguments,
-or in the wrong order.
-
-CMock is based on Unity, which it uses for all internal testing.
-It uses Ruby to do all the main work (versions 2.0.0 and above).
-
-
-Installing
-==========
-
-The first thing you need to do to install CMock is to get yourself
-a copy of Ruby. If you're on linux or osx, you probably already
-have it. You can prove it by typing the following:
-
-    ruby --version
-
-
-If it replied in a way that implies ignorance, then you're going to
-need to install it. You can go to [ruby-lang](https://ruby-lang.org)
-to get the latest version. You're also going to need to do that if it
-replied with a version that is older than 2.0.0. Go ahead. We'll wait.
-
-Once you have Ruby, you have three options:
-
-* Clone the latest [CMock repo on github](https://github.com/ThrowTheSwitch/CMock/)
-* Download the latest [CMock zip from github](https://github.com/ThrowTheSwitch/CMock/)
-* Install Ceedling (which has it built in!) through your commandline using `gem install ceedling`.
-
-
-Generated Mock Module Summary
-=============================
-
-In addition to the mocks themselves, CMock will generate the
-following functions for use in your tests. The expect functions
-are always generated. The other functions are only generated
-if those plugins are enabled:
-
-
-Expect:
--------
-
-Your basic staple Expects which will be used for most of your day
-to day CMock work. By calling this, you are telling CMock that you
-expect that function to be called during your test. It also specifies
-which arguments you expect it to be called with, and what return
-value you want returned when that happens. You can call this function
-multiple times back to back in order to queue up multiple calls.
-
-* `void func(void)` => `void func_Expect(void)`
-* `void func(params)` => `void func_Expect(expected_params)`
-* `retval func(void)` => `void func_ExpectAndReturn(retval_to_return)`
-* `retval func(params)` => `void func_ExpectAndReturn(expected_params, retval_to_return)`
-
-
-ExpectAnyArgs:
---------------
-
-This behaves just like the Expects calls, except that it doesn't really
-care what the arguments are that the mock gets called with. It still counts
-the number of times the mock is called and it still handles return values
-if there are some.
-
-* `void func(void)` => `void func_ExpectAnyArgs(void)`
-* `void func(params)` => `void func_ExpectAnyArgs(void)`
-* `retval func(void)` => `void func_ExpectAnyArgsAndReturn(retval_to_return)`
-* `retval func(params)` => `void func_ExpectAnyArgsAndReturn(retval_to_return)`
-
-
-Array:
-------
-
-An ExpectWithArray is another variant of Expect. Like expect, it cares about
-the number of times a mock is called, the arguments it is called with, and the
-values it is to return. This variant has another feature, though. For anything
-that resembles a pointer or array, it breaks the argument into TWO arguments.
-The first is the original pointer. The second specify the number of elements
-it is to verify of that array. If you specify 1, it'll check one object. If 2,
-it'll assume your pointer is pointing at the first of two elements in an array.
-If you specify zero elements, it will check just the pointer if
-`:smart` mode is configured or fail if `:compare_data` is set.
-
-* `void func(void)` => (nothing. In fact, an additional function is only generated if the params list contains pointers)
-* `void func(ptr * param, other)` => `void func_ExpectWithArray(ptr* param, int param_depth, other)`
-* `retval func(void)` => (nothing. In fact, an additional function is only generated if the params list contains pointers)
-* `retval func(other, ptr* param)` => `void func_ExpectWithArrayAndReturn(other, ptr* param, int param_depth, retval_to_return)`
-
-
-Ignore:
--------
-
-Maybe you don't care about the number of times a particular function is called or
-the actual arguments it is called with. In that case, you want to use Ignore. Ignore
-only needs to be called once per test. It will then ignore any further calls to that
-particular mock. The IgnoreAndReturn works similarly, except that it has the added
-benefit of knowing what to return when that call happens. If the mock is called more
-times than IgnoreAndReturn was called, it will keep returning the last value without
-complaint. If it's called less times, it will also ignore that. You SAID you didn't
-care how many times it was called, right?
-
-* `void func(void)` => `void func_Ignore(void)`
-* `void func(params)` => `void func_Ignore(void)`
-* `retval func(void)` => `void func_IgnoreAndReturn(retval_to_return)`
-* `retval func(params)` => `void func_IgnoreAndReturn(retval_to_return)`
-
-
-Ignore Arg:
-------------
-
-Maybe you overall want to use Expect and its similar variations, but you don't care
-what is passed to a particular argument. This is particularly useful when that argument
-is a pointer to a value that is supposed to be filled in by the function. You don't want
-to use ExpectAnyArgs, because you still care about the other arguments. Instead, before
-any of your Expect calls are made, you can call this function. It tells CMock to ignore
-a particular argument for the rest of this test, for this mock function.
-
-* `void func(params)` => `void func_IgnoreArg_paramName(void)`
-
-
-ReturnThruPtr:
---------------
-
-Another option which operates on a particular argument of a function is the ReturnThruPtr
-plugin. For every argument that resembles a pointer or reference, CMock generates an
-instance of this function. Just as the AndReturn functions support injecting one or more
-return values into a queue, this function lets you specify one or more return values which
-are queued up and copied into the space being pointed at each time the mock is called.
-
-* `void func(param1)` => `void func_ReturnThruPtr_paramName(val_to_return)`
-* => `void func_ReturnArrayThruPtr_paramName(cal_to_return, len)`
-* => `void func_ReturnMemThruPtr_paramName(val_to_return, size)`
-
-
-Callback:
----------
-
-If all those other options don't work, and you really need to do something custom, you
-still have a choice. As soon as you stub a callback in a test, it will call the callback
-whenever the mock is encountered and return the retval returned from the callback (if any)
-instead of performing the usual expect checks. It can be configured to check the arguments
-first (like expects) or just jump directly to the callback.
-
-* `void func(void)` => `void func_StubWithCallback(CMOCK_func_CALLBACK callback)`
-where `CMOCK_func_CALLBACK` looks like: `void func(int NumCalls)`
-* `void func(params)` => `void func_StubWithCallback(CMOCK_func_CALLBACK callback)`
-where `CMOCK_func_CALLBACK` looks like: `void func(params, int NumCalls)`
-* `retval func(void)` => `void func_StubWithCallback(CMOCK_func_CALLBACK callback)`
-where `CMOCK_func_CALLBACK` looks like: `retval func(int NumCalls)`
-* `retval func(params)` => `void func_StubWithCallback(CMOCK_func_CALLBACK callback)`
-where `CMOCK_func_CALLBACK` looks like: `retval func(params, int NumCalls)`
-
-
-Cexception:
------------
-
-Finally, if you are using Cexception for error handling, you can use this to throw errors
-from inside mocks. Like Expects, it remembers which call was supposed to throw the error,
-and it still checks parameters first.
-
-* `void func(void)` => `void func_ExpectAndThrow(value_to_throw)`
-* `void func(params)` => `void func_ExpectAndThrow(expected_params, value_to_throw)`
-* `retval func(void)` => `void func_ExpectAndThrow(value_to_throw)`
-* `retval func(params)` => `void func_ExpectAndThrow(expected_params, value_to_throw)`
-
-
-
-Running CMock
-=============
-
-CMock is a Ruby script and class. You can therefore use it directly
-from the command line, or include it in your own scripts or rakefiles.
-
-
-Mocking from the Command Line
------------------------------
-
-After unpacking CMock, you will find cmock.rb in the 'lib' directory.
-This is the file that you want to run. It takes a list of header files
-to be mocked, as well as an optional yaml file for a more detailed
-configuration (see config options below).
-
-For example, this will create three mocks using the configuration
-specified in MyConfig.yml:
-
-    ruby cmock.rb -oMyConfig.yml super.h duper.h awesome.h
-
-And this will create two mocks using the default configuration:
-
-    ruby cmock.rb ../mocking/stuff/is/fun.h ../try/it/yourself.h
-
-
-Mocking From Scripts or Rake
-----------------------------
-
-CMock can be used directly from your own scripts or from a rakefile.
-Start by including cmock.rb, then create an instance of CMock.
-When you create your instance, you may initialize it in one of
-three ways.
-
-You may specify nothing, allowing it to run with default settings:
-
-    require 'cmock.rb'
-    cmock = CMock.new
-
-You may specify a YAML file containing the configuration options
-you desire:
-
-    cmock = CMock.new('../MyConfig.yml')
-
-You may specify the options explicitly:
-
-    cmock = Cmock.new(:plugins => [:cexception, :ignore], :mock_path => 'my/mocks/')
-
-
-Config Options:
----------------
-
-The following configuration options can be specified in the
-yaml file or directly when instantiating.
-
-Passed as Ruby, they look like this:
-
-        { :attributes => [“__funky”, “__intrinsic”], :when_ptr => :compare }
-
-Defined in the yaml file, they look more like this:
-
-        :cmock:
-          :attributes:
-            - __funky
-            - __intrinsic
-          :when_ptr: :compare
-
-In all cases, you can just include the things that you want to override
-from the defaults. We've tried to specify what the defaults are below.
-
-* `:attributes`:
-  These are attributes that CMock should ignore for you for testing
-  purposes. Custom compiler extensions and externs are handy things to
-  put here. If your compiler is choking on some extended syntax, this
-  is often a good place to look.
-
-  * defaults: ['__ramfunc', '__irq', '__fiq', 'register', 'extern']
-  * **note:** this option will reinsert these attributes onto the mock's calls.
-    If that isn't what you are looking for, check out :strippables.
-
-* `:c_calling_conventions`:
-  Similarly, CMock may need to understand which C calling conventions
-  might show up in your codebase. If it encounters something it doesn't
-  recognize, it's not going to mock it. We have the most common covered,
-  but there are many compilers out there, and therefore many other options.
-
-  * defaults: ['__stdcall', '__cdecl', '__fastcall']
-  * **note:** this option will reinsert these attributes onto the mock's calls.
-    If that isn't what you are looking for, check out :strippables.
-
-* `:callback_after_arg_check`:
-  Tell `:callback` plugin to do the normal argument checking **before** it
-  calls the callback function by setting this to true. When false, the
-  callback function is called **instead** of the argument verification.
-
-  * default: false
-
-* `:callback_include_count`:
-  Tell `:callback` plugin to include an extra parameter to specify the
-  number of times the callback has been called. If set to false, the
-  callback has the same interface as the mocked function. This can be
-  handy when you're wanting to use callback as a stub.
-
-  * default: true
-
-* `:cexception_include`:
-  Tell `:cexception` plugin where to find CException.h... You only need to
-  define this if it's not in your build path already... which it usually
-  will be for the purpose of your builds.
-
-  * default: *nil*
-
-* `:enforce_strict_ordering`:
-  CMock always enforces the order that you call a particular function,
-  so if you expect GrabNabber(int size) to be called three times, it
-  will verify that the sizes are in the order you specified. You might
-  *also* want to make sure that all different functions are called in a
-  particular order. If so, set this to true.
-
-  * default: false
-
-* `:framework`:
-  Currently the only option is `:unity.` Eventually if we support other
-  unity test frameworks (or if you write one for us), they'll get added
-  here.
-
-  : default: :unity
-
-* `:includes`:
-  An array of additional include files which should be added to the
-  mocks. Useful for global types and definitions used in your project.
-  There are more specific versions if you care WHERE in the mock files
-  the includes get placed. You can define any or all of these options.
-
-  * `:includes`
-  * `:includes_h_pre_orig_header`
-  * `:includes_h_post_orig_header`
-  * `:includes_c_pre_header`
-  * `:includes_c_post_header`
-  * default: nil #for all 5 options
-
-* `:memcmp_if_unknown`:
-  C developers create a lot of types, either through typedef or preprocessor
-  macros. CMock isn't going to automatically know what you were thinking all
-  the time (though it tries its best). If it comes across a type it doesn't
-  recognize, you have a choice on how you want it to handle it. It can either
-  perform a raw memory comparison and report any differences, or it can fail
-  with a meaningful message. Either way, this feature will only happen after
-  all other mechanisms have failed (The thing encountered isn't a standard
-  type. It isn't in the :treat_as list. It isn't in a custom unity_helper).
-
-  * default: true
-
-* `:mock_path`:
-  The directory where you would like the mock files generated to be
-  placed.
-
-  * default: mocks
-
-* `:mock_prefix`:
-  The prefix to prepend to your mock files. For example, if it's “Mock”, a file
-  “USART.h” will get a mock called “MockUSART.c”. This CAN be used with a suffix
-  at the same time.
-
-  * default: Mock
-
-* `:mock_suffix`:
-  The suffix to append to your mock files. For example, it it's "_Mock", a file
-  "USART.h" will get a mock called "USART_Mock.h". This CAN be used with a prefix
-  at the same time.
-
-  * default: ""
-
-* `:plugins`:
-  An array of which plugins to enable. ':expect' is always active. Also
-  available currently:
-
-  * `:ignore`
-  * `:ignore_arg`
-  * `:expect_any_args`
-  * `:array`
-  * `:cexception`
-  * `:callback`
-  * `:return_thru_ptr`
-
-* `:strippables`:
-  An array containing a list of items to remove from the header
-  before deciding what should be mocked. This can be something simple
-  like a compiler extension CMock wouldn't recognize, or could be a
-  regex to reject certain function name patterns. This is a great way to
-  get rid of compiler extensions when your test compiler doesn't support
-  them. For example, use `:strippables: ['(?:functionName\s*\(+.*?\)+)']`
-  to prevent a function `functionName` from being mocked. By default, it
-  is ignoring all gcc attribute extensions.
-
-  * default: ['(?:__attribute__\s*\(+.*?\)+)']
-
-* `:subdir`:
-  This is a relative subdirectory for your mocks.  Set this to e.g. "sys" in
-  order to create a mock for `sys/types.h` in `(:mock_path)/sys/`.
-
-  * default: ""
-
-* `:treat_as`:
-  The `:treat_as` list is a shortcut for when you have created typedefs
-  of standard types. Why create a custom unity helper for UINT16 when
-  the unity function TEST_ASSERT_EQUAL_HEX16 will work just perfectly?
-  Just add 'UINT16' => 'HEX16' to your list (actually, don't. We already
-  did that one for you). Maybe you have a type that is a pointer to an
-  array of unsigned characters? No problem, just add 'UINT8_T*' =>
-  'HEX8*'
-
-  * NOTE: unlike the other options, your specifications MERGE with the
-    default list. Therefore, if you want to override something, you must
-    reassign it to something else (or to *nil* if you don't want it)
-
-  * default:
-    * 'int': 'INT'
-    * 'char': 'INT8'
-    * 'short': 'INT16'
-    * 'long': 'INT'
-    * 'int8': 'INT8'
-    * 'int16': 'INT16'
-    * 'int32': 'INT'
-    * 'int8_t': 'INT8'
-    * 'int16_t': 'INT16'
-    * 'int32_t': 'INT'
-    * 'INT8_T': 'INT8'
-    * 'INT16_T': 'INT16'
-    * 'INT32_T': 'INT'
-    * 'bool': 'INT'
-    * 'bool_t': 'INT'
-    * 'BOOL': 'INT'
-    * 'BOOL_T': 'INT'
-    * 'unsigned int': 'HEX32'
-    * 'unsigned long': 'HEX32'
-    * 'uint32': 'HEX32'
-    * 'uint32_t': 'HEX32'
-    * 'UINT32': 'HEX32'
-    * 'UINT32_T': 'HEX32'
-    * 'void*': 'HEX8_ARRAY'
-    * 'unsigned short': 'HEX16'
-    * 'uint16': 'HEX16'
-    * 'uint16_t': 'HEX16'
-    * 'UINT16': 'HEX16'
-    * 'UINT16_T': 'HEX16'
-    * 'unsigned char': 'HEX8'
-    * 'uint8': 'HEX8'
-    * 'uint8_t': 'HEX8'
-    * 'UINT8': 'HEX8'
-    * 'UINT8_T': 'HEX8'
-    * 'char*': 'STRING'
-    * 'pCHAR': 'STRING'
-    * 'cstring': 'STRING'
-    * 'CSTRING': 'STRING'
-    * 'float': 'FLOAT'
-    * 'double': 'FLOAT'
-
-* `:treat_as_void`:
-  We've seen "fun" legacy systems typedef 'void' with a custom type,
-  like MY_VOID. Add any instances of those to this list to help CMock
-  understand how to deal with your code.
-
-  * default: []
-
-* `:treat_externs`:
-  This specifies how you want CMock to handle functions that have been
-  marked as extern in the header file. Should it mock them?
-
-  * `:include` will mock externed functions
-  * `:exclude` will ignore externed functions (default).
-
-* `:unity_helper_path`:
-  If you have created a header with your own extensions to unity to
-  handle your own types, you can set this argument to that path. CMock
-  will then automagically pull in your helpers and use them. The only
-  trick is that you make sure you follow the naming convention:
-  `UNITY_TEST_ASSERT_EQUAL_YourType`. If it finds macros of the right
-  shape that match that pattern, it'll use them.
-
-  * default: []
-
-* `:verbosity`:
-  How loud should CMock be?
-
-  * 0 for errors only
-  * 1 for errors and warnings
-  * 2 for normal (default)
-  * 3 for verbose
-
-* `:weak`:
-  When set this to some value, the generated mocks are defined as weak
-  symbols using the configured format. This allows them to be overridden
-  in particular tests.
-
-  * Set to '__attribute ((weak))' for weak mocks when using GCC.
-  * Set to any non-empty string for weak mocks when using IAR.
-  * default: ""
-
-* `:when_no_prototypes`:
-  When you give CMock a header file and ask it to create a mock out of
-  it, it usually contains function prototypes (otherwise what was the
-  point?). You can control what happens when this isn't true. You can
-  set this to `:warn,` `:ignore,` or `:error`
-
-  * default: :warn
-
-* `:when_ptr`:
-  You can customize how CMock deals with pointers (c strings result in
-  string comparisons... we're talking about **other** pointers here). Your
-  options are `:compare_ptr` to just verify the pointers are the same,
-  `:compare_data` or `:smart` to verify that the data is the same.
-  `:compare_data` and `:smart` behaviors will change slightly based on
-  if you have the array plugin enabled. By default, they compare a
-  single element of what is being pointed to. So if you have a pointer
-  to a struct called ORGAN_T, it will compare one ORGAN_T (whatever that
-  is).
-
-  * default: :smart
-
-* `:fail_on_unexpected_calls`:
-  By default, CMock will fail a test if a mock is called without _Expect and _Ignore
-  called first. While this forces test writers to be more explicit in their expectations,
-  it can clutter tests with _Expect or _Ignore calls for functions which are not the focus
-  of the test. While this is a good indicator that this module should be refactored, some
-  users are not fans of the additional noise.
-
-  Therefore, :fail_on_unexpected_calls can be set to false to force all mocks to start with
-  the assumption that they are operating as _Ignore unless otherwise specified.
-
-  * default: true
-  * **note:**
-    If this option is disabled, the mocked functions will return
-    a default value (0) when called (and only if they have to return something of course).
-
-
-Compiled Options:
------------------
-
-A number of #defines also exist for customizing the cmock experience.
-Feel free to pass these into your compiler or whatever is most
-convenient. CMock will otherwise do its best to guess what you want
-based on other settings, particularly Unity's settings.
-
-* `CMOCK_MEM_STATIC` or `CMOCK_MEM_DYNAMIC`
-  Define one of these to determine if you want to dynamically add
-  memory during tests as required from the heap. If static, you
-  can control the total footprint of Cmock. If dynamic, you will
-  need to make sure you make some heap space available for Cmock.
-
-* `CMOCK_MEM_SIZE`
-  In static mode this is the total amount of memory you are allocating
-  to Cmock. In Dynamic mode this is the size of each chunk allocated
-  at once (larger numbers grab more memory but require less mallocs).
-
-* `CMOCK_MEM_ALIGN`
-  The way to align your data to. Not everything is as flexible as
-  a PC, as most embedded designers know. This defaults to 2, meaning
-  align to the closest 2^2 -> 4 bytes (32 bits). You can turn off alignment
-  by setting 0, force alignment to the closest uint16 with 1 or even
-  to the closest uint64 with 3.
-
-* `CMOCK_MEM_PTR_AS_INT`
-  This is used internally to hold pointers... it needs to be big
-  enough. On most processors a pointer is the same as an unsigned
-  long... but maybe that's not true for yours?
-
-* `CMOCK_MEM_INDEX_TYPE`
-  This needs to be something big enough to point anywhere in Cmock's
-  memory space... usually it's an unsigned int.
-
-Examples
-========
-
-You can look in the [examples directory](/examples/) for a couple of examples on how
-you might tool CMock into your build process. You may also want to consider
-using [Ceedling](https://throwtheswitch.org/ceedling). Please note that
-these examples are meant to show how the build process works. They have
-failing tests ON PURPOSE to show what that would look like. Don't be alarmed. ;)
-
diff --git a/test/vendor/ceedling/docs/CeedlingPacket.md b/test/vendor/ceedling/docs/CeedlingPacket.md
deleted file mode 100644
index 88cd02025..000000000
--- a/test/vendor/ceedling/docs/CeedlingPacket.md
+++ /dev/null
@@ -1,2060 +0,0 @@
-[All code is copyright Š 2010-2012 Ceedling Project
-by Mike Karlesky, Mark VanderVoord, and Greg Williams.
-
-This Documentation Is Released Under a
-Creative Commons 3.0 Attribution Share-Alike License]
-
-What the What?
-
-Assembling build environments for C projects - especially with
-automated unit tests - is a pain. Whether it's Make or Rake or Premake
-or what-have-you, set up with an all-purpose build environment
-tool is tedious and requires considerable glue code to pull together
-the necessary tools and libraries. Ceedling allows you to generate
-an entire test and build environment for a C project from a single
-YAML configuration file. Ceedling is written in Ruby and works
-with the Rake build tool plus other goodness like Unity and CMock
-- the unit testing and mocking frameworks for C. Ceedling and
-its complementary tools can support the tiniest of embedded
-processors, the beefiest 64 bit power houses available, and
-everything in between.
-
-For a build project including unit tests and using the default
-toolchain gcc, the configuration file could be as simple as this:
-
-```yaml
-:project:
-  :build_root: project/build/
-  :release_build: TRUE
-
-:paths:
-  :test:
-    - tests/**
-  :source:
-    - source/**
-```
-
-From the command line, to build the release version of your project,
-you would simply run `ceedling release`. To run all your unit tests,
-you would run `ceedling test:all`. That's it!
-
-Of course, many more advanced options allow you to configure
-your project with a variety of features to meet a variety of needs.
-Ceedling can work with practically any command line toolchain
-and directory structure – all by way of the configuration file.
-Further, because Ceedling piggy backs on Rake, you can add your
-own Rake tasks to accomplish project tasks outside of testing
-and release builds. A facility for plugins also allows you to
-extend Ceedling's capabilities for needs such as custom code
-metrics reporting and coverage testing.
-
-What's with this Name?
-
-Glad you asked. Ceedling is tailored for unit tested C projects
-and is built upon / around Rake (Rake is a Make replacement implemented
-in the Ruby scripting language). So, we've got C, our Rake, and
-the fertile soil of a build environment in which to grow and tend
-your project and its unit tests. Ta da - _Ceedling_.
-
-What Do You Mean "tailored for unit tested C projects"?
-
-Well, we like to write unit tests for our C code to make it lean and
-mean (that whole [Test-Driven Development][tdd]
-thing). Along the way, this style of writing C code spawned two
-tools to make the job easier: a unit test framework for C called
-_Unity_ and a mocking library called _CMock_. And, though it's
-not directly related to testing, a C framework for exception
-handling called _CException_ also came along.
-
-[tdd]: http://en.wikipedia.org/wiki/Test-driven_development
-
-These tools and frameworks are great, but they require quite
-a bit of environment support to pull them all together in a convenient,
-usable fashion. We started off with Rakefiles to assemble everything.
-These ended up being quite complicated and had to be hand-edited
-or created anew for each new project. Ceedling replaces all that
-tedium and rework with a configuration file that ties everything
-together.
-
-Though Ceedling is tailored for unit testing, it can also go right ahead
-and build your final binary release artifact for you as well. Or,
-Ceedling and your tests can live alongside your existing release build
-setup. That said, Ceedling is more powerful as a unit test build
-environment than it is a general purpose release build environment;
-complicated projects including separate bootloaders or multiple library
-builds, etc. are not its strong suit.
-
-Hold on. Back up. Ruby? Rake? YAML? Unity? CMock? CException?
-
-Seem overwhelming? It's not bad at all, and for the benefits tests
-bring us, it's all worth it.
-
-[Ruby][] is a handy scripting
-language like Perl or Python. It's a modern, full featured language
-that happens to be quite handy for accomplishing tasks like code
-generation or automating one's workflow while developing in
-a compiled language such as C.
-
-[Ruby]: http://www.ruby-lang.org/en/
-
-[Rake][] is a utility written in Ruby
-for accomplishing dependency tracking and task automation
-common to building software. It's a modern, more flexible replacement
-for [Make][]).
-Rakefiles are Ruby files, but they contain build targets similar
-in nature to that of Makefiles (but you can also run Ruby code in
-your Rakefile).
-
-[Rake]: http://rubyrake.org/
-[Make]: http://en.wikipedia.org/wiki/Make_(software)
-
-[YAML][] is a "human friendly data serialization standard for all
-programming languages." It's kinda like a markup language, but don't
-call it that. With a YAML library, you can [serialize][] data structures
-to and from the file system in a textual, human readable form. Ceedling
-uses a serialized data structure as its configuration input.
-
-[YAML]: http://en.wikipedia.org/wiki/Yaml
-[serialize]: http://en.wikipedia.org/wiki/Serialization
-
-[Unity] is a [unit test framework][test] for C. It provides facilities
-for test assertions, executing tests, and collecting / reporting test
-results. Unity derives its name from its implementation in a single C
-source file (plus two C header files) and from the nature of its
-implementation - Unity will build in any C toolchain and is configurable
-for even the very minimalist of processors.
-
-[Unity]: http://github.com/ThrowTheSwitch/Unity
-[test]: http://en.wikipedia.org/wiki/Unit_testing
-
-[CMock] is a tool written in Ruby able to generate entire
-[mock functions][mock] in C code from a given C header file. Mock
-functions are invaluable in [interaction-based unit testing][ut].
-CMock's generated C code uses Unity.
-
-[CMock]: http://github.com/ThrowTheSwitch/CMock
-[mock]: http://en.wikipedia.org/wiki/Mock_object
-[ut]: http://martinfowler.com/articles/mocksArentStubs.html
-
-[CException] is a C source and header file that provide a simple
-[exception mechanism][exn] for C by way of wrapping up the
-[setjmp / longjmp][setjmp] standard library calls. Exceptions are a much
-cleaner and preferable alternative to managing and passing error codes
-up your return call trace.
-
-[CException]: http://github.com/ThrowTheSwitch/CException
-[exn]: http://en.wikipedia.org/wiki/Exception_handling
-[setjmp]: http://en.wikipedia.org/wiki/Setjmp.h
-
-Notes
------
-
-* YAML support is included with Ruby - requires no special installation
-  or configuration.
-
-* Unity, CMock, and CException are bundled with Ceedling, and
-  Ceedling is designed to glue them all together for your project
-  as seamlessly as possible.
-
-
-Installation & Setup: What Exactly Do I Need to Get Started?
-------------------------------------------------------------
-
-As a [Ruby gem](http://docs.rubygems.org/read/chapter/1):
-
-1. [Download and install Ruby](http://www.ruby-lang.org/en/downloads/)
-
-2. Use Ruby's command line gem package manager to install Ceedling:
-   `gem install ceedling`
-   (Unity, CMock, and CException come along with Ceedling for free)
-
-3. Execute Ceedling at command line to create example project
-   or an empty Ceedling project in your filesystem (executing
-   `ceedling help` first is, well, helpful).
-
-Gem install notes:
-
-1. Steps 1-2 are a one time affair for your local environment.
-   When steps 1-2 are completed once, only step 3 is needed for
-   each new project.
-
-
-
-General notes:
-
-1. Certain advanced features of Ceedling rely on gcc and cpp
-   as preprocessing tools. In most *nix systems, these tools
-   are already available. For Windows environments, we recommend
-   the [mingw project](http://www.mingw.org/) (Minimalist
-   GNU for Windows). This represents an optional, additional
-   setup / installation step to complement the list above. Upon
-   installing mingw ensure your system path is updated or set
-   [:environment][:path] in your `project.yml` file (see
-   environment section later in this document).
-
-2. To use a project file name other than the default `project.yml`
-   or place the project file in a directory other than the one
-   in which you'll run Rake, create an environment variable
-   `CEEDLING_MAIN_PROJECT_FILE` with your desired project
-   file path.
-
-3. To better understand Rake conventions, Rake execution,
-   and Rakefiles, consult the [Rake tutorial, examples, and
-   user guide](http://rubyrake.org/).
-
-4. When using Ceedling in Windows environments, a test file name may 
-   not include the sequences “patch” or “setup”. The Windows Installer 
-   Detection Technology (part of UAC), requires administrator 
-   privileges to execute file names with these strings.
-
-
-
-Now What? How Do I Make It GO?
-------------------------------
-
-We're getting a little ahead of ourselves here, but it's good
-context on how to drive this bus. Everything is done via the command
-line. We'll cover conventions and how to actually configure
-your project in later sections.
-
-To run tests, build your release artifact, etc., you will be interacting
-with Rake on the command line. Ceedling works with Rake to present
-you with named tasks that coordinate the file generation and
-build steps needed to accomplish something useful. You can also
-add your own independent Rake tasks or create plugins to extend
-Ceedling (more on this later).
-
-
-* `ceedling [no arguments]`:
-
-  Run the default Rake task (conveniently recognized by the name default
-  by Rake). Neither Rake nor Ceedling provide a default task. Rake will
-  abort if run without arguments when no default task is defined. You can
-  conveniently define a default task in the Rakefile discussed in the
-  preceding setup & installation section of this document.
-
-* `ceedling -T`:
-
-  List all available Rake tasks with descriptions (Rake tasks without
-  descriptions are not listed). -T is a command line switch for Rake and
-  not the same as tasks that follow.
-
-* `ceedling <tasks...> --trace`:
-
-  For advanced users troubleshooting a confusing build error, debug
-  Ceedling or a plugin, --trace provides a stack trace of dependencies
-  walked during task execution and any Ruby failures along the way. Note
-  that --trace is a command line switch for Rake and is not the same as
-  tasks that follow.
-
-* `ceedling environment`:
-
-  List all configured environment variable names and string values. This
-  task is helpful in verifying the evaluatio of any Ruby expressions in
-  the [:environment] section of your config file.`: Note: Ceedling may
-  set some convenience environment variables by default.
-
-* `ceedling paths:*`:
-
-  List all paths collected from [:paths] entries in your YAML config
-  file where * is the name of any section contained in [:paths]. This
-  task is helpful in verifying the expansion of path wildcards / globs
-  specified in the [:paths] section of your config file.
-
-* `ceedling files:assembly`
-* `ceedling files:header`
-* `ceedling files:source`
-* `ceedling files:test`
-
-  List all files and file counts collected from the relevant search
-  paths specified by the [:paths] entries of your YAML config file. The
-  files:assembly task will only be available if assembly support is
-  enabled in the [:release_build] section of your configuration file.
-
-* `ceedling options:*`:
-
-  Load and merge configuration settings into the main project
-  configuration. Each task is named after a *.yml file found in the
-  configured options directory. See documentation for the configuration
-  setting [:project][:options_path] and for options files in advanced
-  topics.
-
-* `ceedling test:all`:
-
-  Run all unit tests (rebuilding anything that's changed along the way).
-
-* `ceedling test:delta`:
-
-  Run only those unit tests for which the source or test files have
-  changed (i.e. incremental build). Note: with the
-  [:project][:use_test_preprocessor] configuration file option set,
-  runner files are always regenerated limiting the total efficiency this
-  text execution option can afford.
-
-* `ceedling test:*`:
-
-  Execute the named test file or the named source file that has an
-  accompanying test. No path. Examples: ceedling test:foo.c or ceed
-  test:test_foo.c
-
-* `ceedling test:pattern[*]`:
-
-  Execute any tests whose name and/or path match the regular expression
-  pattern (case sensitive). Example: ceedling "test:pattern[(I|i)nit]" will
-  execute all tests named for initialization testing. Note: quotes may
-  be necessary around the ceedling parameter to distinguish regex characters
-  from command line operators.
-
-* `ceedling test:path[*]`:
-
-  Execute any tests whose path contains the given string (case
-  sensitive). Example: ceedling test:path[foo/bar] will execute all tests
-  whose path contains foo/bar. Note: both directory separator characters
-  / and \ are valid.
-
-* `ceedling release`:
-
-  Build all source into a release artifact (if the release build option
-  is configured).
-
-* `ceedling release:compile:*`:
-
-  Sometimes you just need to compile a single file dagnabit. Example:
-  ceedling release:compile:foo.c
-
-* `ceedling release:assemble:*`:
-
-  Sometimes you just need to assemble a single file doggonit. Example:
-  ceedling release:assemble:foo.s
-
-* `ceedling module:create[Filename]`:
-* `ceedling module:create[<Path:>Filename]`:
-
-  It's often helpful to create a file automatically. What's better than
-  that? Creating a source file, a header file, and a corresponding test
-  file all in one step!
-
-  There are also patterns which can be specified to automatically generate
-  a bunch of files. Try `ceedling module:create[Poodles,mch]` for example!
-
-  The module generator has several options you can configure.
-  F.e. Generating the source/header/test file in a subdirectory (by adding <Path> when calling module:create).
-  For more info, refer to the [Module Generator](https://github.com/ThrowTheSwitch/Ceedling/blob/master/docs/CeedlingPacket.md#module-generator) section.
-
-* `ceedling logging <tasks...>`:
-
-  Enable logging to <build path>/logs. Must come before test and release
-  tasks to log their steps and output. Log names are a concatenation of
-  project, user, and option files loaded. User and option files are
-  documented in the advanced topics section of this document.
-
-* `ceedling verbosity[x] <tasks...>`:
-
-  Change the default verbosity level. [x] ranges from 0 (quiet) to 4
-  (obnoxious). Level [3] is the default. The verbosity task must precede
-  all tasks in the command line list for which output is desired to be
-  seen. Verbosity settings are generally most meaningful in conjunction
-  with test and release tasks.
-
-* `ceedling summary`:
-
-  If plugins are enabled, this task will execute the summary method of
-  any plugins supporting it. This task is intended to provide a quick
-  roundup of build artifact metrics without re-running any part of the
-  build.
-
-* `ceedling clean`:
-
-  Deletes all toolchain binary artifacts (object files, executables),
-  test results, and any temporary files. Clean produces no output at the
-  command line unless verbosity has been set to an appreciable level.
-
-* `ceedling clobber`:
-
-  Extends clean task's behavior to also remove generated files: test
-  runners, mocks, preprocessor output. Clobber produces no output at the
-  command line unless verbosity has been set to an appreciable level.
-
-To better understand Rake conventions, Rake execution, and
-Rakefiles, consult the [Rake tutorial, examples, and user guide][guide].
-
-[guide]: http://rubyrake.org/
-
-At present, none of Ceedling's commands provide persistence.
-That is, they must each be specified at the command line each time
-they are needed. For instance, Ceedling's verbosity command
-only affects output at the time it's run.
-
-Individual test and release file tasks
-are not listed in `-T` output. Because so many files may be present
-it's unwieldy to list them all.
-
-Multiple rake tasks can be executed at the command line (order
-is executed as provided). For example, `ceed
-clobber test:all release` will removed all generated files;
-build and run all tests; and then build all source - in that order.
-If any Rake task fails along the way, execution halts before the
-next task.
-
-The `clobber` task removes certain build directories in the
-course of deleting generated files. In general, it's best not
-to add to source control any Ceedling generated directories
-below the root of your top-level build directory. That is, leave
-anything Ceedling & its accompanying tools generate out of source
-control (but go ahead and add the top-level build directory that
-holds all that stuff). Also, since Ceedling is pretty smart about
-what it rebuilds and regenerates, you needn't clobber often.
-
-Important Conventions
-=====================
-
-Directory Structure, Filenames & Extensions
--------------------------------------------
-
-Much of Ceedling's functionality is driven by collecting files
-matching certain patterns inside the paths it's configured
-to search. See the documentation for the [:extensions] section
-of your configuration file (found later in this document) to
-configure the file extensions Ceedling uses to match and collect
-files. Test file naming is covered later in this section.
-
-Test files and source files must be segregated by directories.
-Any directory structure will do. Tests can be held in subdirectories
-within source directories, or tests and source directories
-can be wholly separated at the top of your project's directory
-tree.
-
-Search Path Order
------------------
-
-When Ceedling searches for files (e.g. looking for header files
-to mock) or when it provides search paths to any of the default
-gcc toolchain executables, it organizes / prioritizes its search
-paths. The order is always: test paths, support paths, source
-paths, and then include paths. This can be useful, for instance,
-in certain testing scenarios where we desire Ceedling or a compiler
-to find a stand-in header file in our support directory before
-the actual source header file of the same name.
-
-This convention only holds when Ceedling is using its default
-tool configurations and / or when tests are involved. If you define
-your own tools in the configuration file (see the [:tools] section
-documented later in this here document), you have complete control
-over what directories are searched and in what order. Further,
-test and support directories are only searched when appropriate.
-That is, when running a release build, test and support directories
-are not used at all.
-
-Source Files & Binary Release Artifacts
----------------------------------------
-
-Your binary release artifact results from the compilation and
-linking of all source files Ceedling finds in the specified source
-directories. At present only source files with a single (configurable)
-extension are recognized. That is, *.c and *.cc files will not
-both be recognized - only one or the other. See the configuration
-options and defaults in the documentation for the [:extensions]
-sections of your configuration file (found later in this document).
-
-Test Files & Executable Test Fixtures
--------------------------------------
-
-Ceedling builds each individual test file with its accompanying
-source file(s) into a single, monolithic test fixture executable.
-Test files are recognized by a naming convention: a (configurable)
-prefix such as "`test_`" in the file name with the same file extension
-as used by your C source files. See the configuration options
-and defaults in the documentation for the [:project] and [:extensions]
-sections of your configuration file (found later in this document).
-Depending on your configuration options, Ceedling can recognize
-a variety of test file naming patterns in your test search paths.
-For example: `test_some_super_functionality.c`, `TestYourSourceFile.cc`,
-or `testing_MyAwesomeCode.C` could each be valid test file
-names. Note, however, that Ceedling can recognize only one test
-file naming convention per project.
-
-Ceedling knows what files to compile and link into each individual
-test executable by way of the #include list contained in each
-test file. Any C source files in the configured search directories
-that correspond to the header files included in a test file will
-be compiled and linked into the resulting test fixture executable.
-From this same #include list, Ceedling knows which files to mock
-and compile and link into the test executable (if you use mocks
-in your tests). That was a lot of clauses and information in a very
-few sentences; the example that follows in a bit will make it clearer.
-
-By naming your test functions according to convention, Ceedling
-will extract and collect into a runner C file calls to all your
-test case functions. This runner file handles all the execution
-minutiae so that your test file can be quite simple and so that
-you never forget to wire up a test function to be executed. In this
-generated runner lives the `main()` entry point for the resulting
-test executable. There are no configuration options for the
-naming convention of your test case functions. A test case function
-signature must have these three elements: void return, void
-parameter list, and the function name prepended with lowercase
-"`test`". In other words, a test function signature should look
-like this: `void test``[any name you like]``(void)`.
-
-A commented sample test file follows on the next page. Also, see
-the sample project contained in the Ceedling documentation
-bundle.
-
-```c
-// test_foo.c -----------------------------------------------
-#include "unity.h"     // compile/link in Unity test framework
-#include "types.h"     // header file with no *.c file -- no compilation/linking
-#include "foo.h"       // source file foo.c under test
-#include "mock_bar.h"  // bar.h will be found and mocked as mock_bar.c + compiled/linked in;
-                       // foo.c includes bar.h and uses functions declared in it
-#include "mock_baz.h"  // baz.h will be found and mocked as mock_baz.c + compiled/linked in
-                       // foo.c includes baz.h and uses functions declared in it
-
-
-void setUp(void) {}    // every test file requires this function;
-                       // setUp() is called by the generated runner before each test case function
-
-void tearDown(void) {} // every test file requires this function;
-                       // tearDown() is called by the generated runner before each test case function
-
-// a test case function
-void test_Foo_Function1_should_Call_Bar_AndGrill(void)
-{
-    Bar_AndGrill_Expect();                    // setup function from mock_bar.c that instructs our
-                                              // framework to expect Bar_AndGrill() to be called once
-    TEST_ASSERT_EQUAL(0xFF, Foo_Function1()); // assertion provided by Unity
-                                              // Foo_Function1() calls Bar_AndGrill() & returns a byte
-}
-
-// another test case function
-void test_Foo_Function2_should_Call_Baz_Tec(void)
-{
-    Baz_Tec_ExpectAnd_Return(1);       // setup function provided by mock_baz.c that instructs our
-                                       // framework to expect Baz_Tec() to be called once and return 1
-    TEST_ASSERT_TRUE(Foo_Function2()); // assertion provided by Unity
-}
-
-// end of test_foo.c ----------------------------------------
-```
-
-From the test file specified above Ceedling will generate `test_foo_runner.c`;
-this runner file will contain `main()` and call both of the example
-test case functions.
-
-The final test executable will be `test_foo.exe` (for Windows
-machines or `test_foo.out` for *nix systems - depending on default
-or configured file extensions). Based on the #include list above,
-the test executable will be the output of the linker having processed
-`unity.o`, `foo.o`, `mock_bar.o`, `mock_baz.o`, `test_foo.o`,
-and `test_foo_runner.o`. Ceedling finds the files, generates
-mocks, generates a runner, compiles all the files, and links
-everything into the test executable. Ceedling will then run
-the test executable and collect test results from it to be reported
-to the developer at the command line.
-
-For more on the assertions and mocks shown, consult the documentation
-for Unity and CMock.
-
-The Magic of Dependency Tracking
---------------------------------
-
-Ceedling is pretty smart in using Rake to build up your project's
-dependencies. This means that Ceedling automagically rebuilds
-all the appropriate files in your project when necessary: when
-your configuration changes, Ceedling or any of the other tools
-are updated, or your source or test files change. For instance,
-if you modify a header file that is mocked, Ceedling will ensure
-that the mock is regenerated and all tests that use that mock are
-rebuilt and re-run when you initiate a relevant testing task.
-When you see things rebuilding, it's for a good reason. Ceedling
-attempts to regenerate and rebuild only what's needed for a given
-execution of a task. In the case of large projects, assembling
-dependencies and acting upon them can cause some delay in executing
-tasks.
-
-With one exception, the trigger to rebuild or regenerate a file
-is always a disparity in timestamps between a target file and
-its source - if an input file is newer than its target dependency,
-the target is rebuilt or regenerated. For example, if the C source
-file from which an object file is compiled is newer than that object
-file on disk, recompilation will occur (of course, if no object
-file exists on disk, compilation will always occur). The one
-exception to this dependency behavior is specific to your input
-configuration. Only if your logical configuration changes
-will a system-wide rebuild occur. Reorganizing your input configuration
-or otherwise updating its file timestamp without modifying
-the values within the file will not trigger a rebuild. This behavior
-handles the various ways in which your input configuration can
-change (discussed later in this document) without having changed
-your actual project YAML file.
-
-Ceedling needs a bit of help to accomplish its magic with deep
-dependencies. Shallow dependencies are straightforward:
-a mock is dependent on the header file from which it's generated,
-a test file is dependent upon the source files it includes (see
-the preceding conventions section), etc. Ceedling handles
-these "out of the box." Deep dependencies are specifically a
-C-related phenomenon and occur as a consequence of include statements
-within C source files. Say a source file includes a header file
-and that header file in turn includes another header file which
-includes still another header file. A change to the deepest header
-file should trigger a recompilation of the source file, a relinking
-of all the object files comprising a test fixture, and a new execution
-of that test fixture.
-
-Ceedling can handle deep dependencies but only with the help
-of a C preprocessor. Ceedling is quite capable, but a full C preprocessor
-it ain't. Your project can be configured to use a C preprocessor
-or not. Simple projects or large projects constructed so as to
-be quite flat in their include structure generally don't need
-deep dependency preprocessing - and can enjoy the benefits of
-faster execution. Legacy code, on the other hand, will almost
-always want to be tested with deep preprocessing enabled. Set
-up of the C preprocessor is covered in the documentation for the
-[:project] and [:tools] section of the configuration file (later
-in this document). Ceedling contains all the configuration
-necessary to use the gcc preprocessor by default. That is, as
-long as gcc is in your system search path, deep preprocessing
-of deep dependencies is available to you by simply enabling it
-in your project configuration file.
-
-Ceedling's Build Output
------------------------
-
-Ceedling requires a top-level build directory for all the stuff
-that it, the accompanying test tools, and your toolchain generate.
-That build directory's location is configured in the [:project]
-section of your configuration file (discussed later). There
-can be a ton of generated files. By and large, you can live a full
-and meaningful life knowing absolutely nothing at all about
-the files and directories generated below the root build directory.
-
-As noted already, it's good practice to add your top-level build
-directory to source control but nothing generated beneath it.
-You'll spare yourself headache if you let Ceedling delete and
-regenerate files and directories in a non-versioned corner
-of your project's filesystem beneath the top-level build directory.
-
-The `artifacts` directory is the one and only directory you may
-want to know about beneath the top-level build directory. The
-subdirectories beneath `artifacts` will hold your binary release
-target output (if your project is configured for release builds)
-and will serve as the conventional location for plugin output.
-This directory structure was chosen specifically because it
-tends to work nicely with Continuous Integration setups that
-recognize and list build artifacts for retrieval / download.
-
-The Almighty Project Configuration File (in Glorious YAML)
-----------------------------------------------------------
-
-Please consult YAML documentation for the finer points of format
-and to understand details of our YAML-based configuration file.
-We recommend [Wikipedia's entry on YAML](http://en.wikipedia.org/wiki/Yaml)
-for this. A few highlights from that reference page:
-
-* YAML streams are encoded using the set of printable Unicode
-  characters, either in UTF-8 or UTF-16
-
-* Whitespace indentation is used to denote structure; however
-  tab characters are never allowed as indentation
-
-* Comments begin with the number sign ( # ), can start anywhere
-  on a line, and continue until the end of the line unless enclosed
-  by quotes
-
-* List members are denoted by a leading hyphen ( - ) with one member
-  per line, or enclosed in square brackets ( [ ] ) and separated
-  by comma space ( , )
-
-* Hashes are represented using the colon space ( : ) in the form
-  key: value, either one per line or enclosed in curly braces
-  ( { } ) and separated by comma space ( , )
-
-* Strings (scalars) are ordinarily unquoted, but may be enclosed
-  in double-quotes ( " ), or single-quotes ( ' )
-
-* YAML requires that colons and commas used as list separators
-  be followed by a space so that scalar values containing embedded
-  punctuation can generally be represented without needing
-  to be enclosed in quotes
-
-* Repeated nodes are initially denoted by an ampersand ( & ) and
-  thereafter referenced with an asterisk ( * )
-
-
-Notes on what follows:
-
-* Each of the following sections represent top-level entries
-  in the YAML configuration file.
-
-* Unless explicitly specified in the configuration file, default
-  values are used by Ceedling.
-
-* These three settings, at minimum, must be specified:
-  * [:project][:build_root]
-  * [:paths][:source]
-  * [:paths][:test]
-
-* As much as is possible, Ceedling validates your settings in
-  properly formed YAML.
-
-* Improperly formed YAML will cause a Ruby error when the YAML
-  is parsed. This is usually accompanied by a complaint with
-  line and column number pointing into the project file.
-
-* Certain advanced features rely on gcc and cpp as preprocessing
-  tools. In most *nix systems, these tools are already available.
-  For Windows environments, we recommend the [mingw project](http://www.mingw.org/)
-  (Minimalist GNU for Windows).
-
-* Ceedling is primarily meant as a build tool to support automated
-  unit testing. All the heavy lifting is involved there. Creating
-  a simple binary release build artifact is quite trivial in
-  comparison. Consequently, most default options and the construction
-  of Ceedling itself is skewed towards supporting testing though
-  Ceedling can, of course, build your binary release artifact
-  as well. Note that complex binary release artifacts (e.g.
-  application + bootloader or multiple libraries) are beyond
-  Ceedling's release build ability.
-
-
-Conventions / features of Ceedling-specific YAML:
-
-* Any second tier setting keys anywhere in YAML whose names end
-  in `_path` or `_paths` are automagically processed like all
-  Ceedling-specific paths in the YAML to have consistent directory
-  separators (i.e. "/") and to take advantage of inline Ruby
-  string expansion (see [:environment] setting below for further
-  explanation of string expansion).
-
-
-**Let's Be Careful Out There:** Ceedling performs validation
-on the values you set in your configuration file (this assumes
-your YAML is correct and will not fail format parsing, of course).
-That said, validation is limited to only those settings Ceedling
-uses and those that can be reasonably validated. Ceedling does
-not limit what can exist within your configuration file. In this
-way, you can take full advantage of YAML as well as add sections
-and values for use in your own custom plugins (documented later).
-The consequence of this is simple but important. A misspelled
-configuration section name or value name is unlikely to cause
-Ceedling any trouble. Ceedling will happily process that section
-or value and simply use the properly spelled default maintained
-internally - thus leading to unexpected behavior without warning.
-
-project: global project settings
-
-
-* `build_root`:
-
-  Top level directory into which generated path structure and files are
-  placed. Note: this is one of the handful of configuration values that
-  must be set. The specified path can be absolute or relative to your
-  working directory.
-
-  **Default**: (none)
-
-* `use_exceptions`:
-
-  Configures the build environment to make use of CException. Note that
-  if you do not use exceptions, there's no harm in leaving this as its
-  default value.
-
-  **Default**: TRUE
-
-* `use_mocks`:
-
-  Configures the build environment to make use of CMock. Note that if
-  you do not use mocks, there's no harm in leaving this setting as its
-  default value.
-
-  **Default**: TRUE
-
-* `use_test_preprocessor`:
-
-  This option allows Ceedling to work with test files that contain
-  conditional compilation statements (e.g. #ifdef) and header files you
-  wish to mock that contain conditional preprocessor statements and/or
-  macros.
-
-  Ceedling and CMock are advanced tools with sophisticated parsers.
-  However, they do not include entire C language preprocessors.
-  Consequently, with this option enabled, Ceedling will use gcc's
-  preprocessing mode and the cpp preprocessor tool to strip down /
-  expand test files and headers to their applicable content which can
-  then be processed by Ceedling and CMock.
-
-  With this option enabled, the gcc & cpp tools must exist in an
-  accessible system search path and test runner files are always
-  regenerated.
-
-  **Default**: FALSE
-
-* `use_deep_dependencies`:
-
-  The base rules and tasks that Ceedling creates using Rake capture most
-  of the dependencies within a standard project (e.g. when the source
-  file accompanying a test file changes, the corresponding test fixture
-  executable will be rebuilt when tests are re-run). However, deep
-  dependencies cannot be captured this way. If a typedef or macro
-  changes in a header file three levels of #include statements deep,
-  this option allows the appropriate incremental build actions to occur
-  for both test execution and release builds.
-
-  This is accomplished by using the dependencies discovery mode of gcc.
-  With this option enabled, gcc must exist in an accessible system
-  search path.
-
-  **Default**: FALSE
-
-* `generate_deep_dependencies`:
-
-  When `use_deep_dependencies` is set to TRUE, Ceedling will run a separate
-  build step to generate the deep dependencies. If you are using gcc as your
-  primary compiler, or another compiler that can generate makefile rules as
-  a side effect of compilation, then you can set this to FALSE to avoid the
-  extra build step but still use the deep dependencies data when deciding
-  which source files to rebuild.
-
-  **Default**: TRUE
-
-* `test_file_prefix`:
-
-  Ceedling collects test files by convention from within the test file
-  search paths. The convention includes a unique name prefix and a file
-  extension matching that of source files.
-
-  Why not simply recognize all files in test directories as test files?
-  By using the given convention, we have greater flexibility in what we
-  do with C files in the test directories.
-
-  **Default**: "test_"
-
-* `options_paths`:
-
-  Just as you may have various build configurations for your source
-  codebase, you may need variations of your project configuration.
-
-  By specifying options paths, Ceedling will search for other project
-  YAML files, make command line tasks available (ceedling options:variation
-  for a variation.yml file), and merge the project configuration of
-  these option files in with the main project file at runtime. See
-  advanced topics.
-
-  Note these Rake tasks at the command line - like verbosity or logging
-  control - must come before the test or release task they are meant to
-  modify.
-
-  **Default**: [] (empty)
-
-* `release_build`:
-
-  When enabled, a release Rake task is exposed. This configuration
-  option requires a corresponding release compiler and linker to be
-  defined (gcc is used as the default).
-
-  More release configuration options are available in the release_build
-  section.
-
-  **Default**: FALSE
-
-
-Example `[:project]` YAML blurb
-
-```yaml
-:project:
-  :build_root: project_awesome/build
-  :use_exceptions: FALSE
-  :use_test_preprocessor: TRUE
-  :use_deep_dependencies: TRUE
-  :options_paths:
-    - project/options
-    - external/shared/options
-  :release_build: TRUE
-```
-
-Ceedling is primarily concerned with facilitating the somewhat
-complicated mechanics of automating unit tests. The same mechanisms
-are easily capable of building a final release binary artifact
-(i.e. non test code; the thing that is your final working software
-that you execute on target hardware).
-
-
-* `output`:
-
-  The name of your release build binary artifact to be found in <build
-  path>/artifacts/release. Ceedling sets the default artifact file
-  extension to that as is explicitly specified in the [:extensions]
-  section or as is system specific otherwise.
-
-  **Default**: `project.exe` or `project.out`
-
-* `use_assembly`:
-
-  If assembly code is present in the source tree, this option causes
-  Ceedling to create appropriate build directories and use an assembler
-  tool (default is the GNU tool as - override available in the [:tools]
-  section.
-
-  **Default**: FALSE
-
-* `artifacts`:
-
-  By default, Ceedling copies to the <build path>/artifacts/release
-  directory the output of the release linker and (optionally) a map
-  file. Many toolchains produce other important output files as well.
-  Adding a file path to this list will cause Ceedling to copy that file
-  to the artifacts directory. The artifacts directory is helpful for
-  organizing important build output files and provides a central place
-  for tools such as Continuous Integration servers to point to build
-  output. Selectively copying files prevents incidental build cruft from
-  needlessly appearing in the artifacts directory. Note that inline Ruby
-  string replacement is available in the artifacts paths (see discussion
-  in the [:environment] section).
-
-  **Default**: [] (empty)
-
-Example `[:release_build]` YAML blurb
-
-```yaml
-:release_build:
-  :output: top_secret.bin
-  :use_assembly: TRUE
-  :artifacts:
-    - build/release/out/c/top_secret.s19
-```
-
-**paths**: options controlling search paths for source and header
-(and assembly) files
-
-* `test`:
-
-  All C files containing unit test code. Note: this is one of the
-  handful of configuration values that must be set.
-
-  **Default**: [] (empty)
-
-* `source`:
-
-  All C files containing release code (code to be tested). Note: this is
-  one of the handful of configuration values that must be set.
-
-  **Default**: [] (empty)
-
-* `support`:
-
-  Any C files you might need to aid your unit testing. For example, on
-  occasion, you may need to create a header file containing a subset of
-  function signatures matching those elsewhere in your code (e.g. a
-  subset of your OS functions, a portion of a library API, etc.). Why?
-  To provide finer grained control over mock function substitution or
-  limiting the size of the generated mocks.
-
-  **Default**: [] (empty)
-
-* `include`:
-
-  Any header files not already in the source search path. Note there's
-    no practical distinction between this search path and the source
-    search path; it's merely to provide options or to support any
-    peculiar source tree organization.
-
-  **Default**: [] (empty)
-
-* `test_toolchain_include`:
-
-  System header files needed by the test toolchain - should your
-  compiler be unable to find them, finds the wrong system include search
-  path, or you need a creative solution to a tricky technical problem.
-  Note that if you configure your own toolchain in the [:tools] section,
-  this search path is largely meaningless to you. However, this is a
-  convenient way to control the system include path should you rely on
-  the default gcc tools.
-
-  **Default**: [] (empty)
-
-* `release_toolchain_include`:
-
-  Same as preceding albeit related to the release toolchain.
-
-  **Default**: [] (empty)
-
-* `<custom>`
-
-  Any paths you specify for custom list. List is available to tool
-  configurations and/or plugins. Note a distinction. The preceding names
-  are recognized internally to Ceedling and the path lists are used to
-  build collections of files contained in those paths. A custom list is
-  just that - a custom list of paths.
-
-Notes on path grammar within the [:paths] section:
-
-* Order of search paths listed in [:paths] is preserved when used by an
-  entry in the [:tools] section
-
-* Wherever multiple path lists are combined for use Ceedling prioritizes
-  path groups as follows:
-  test paths, support paths, source paths, include paths.
-
-  This can be useful, for instance, in certain testing scenarios where
-  we desire Ceedling or the compiler to find a stand-in header file before
-  the actual source header file of the same name.
-
-* Paths:
-
-  1. can be absolute or relative
-
-  2. can be singly explicit - a single fully specified path
-
-  3. can include a glob operator (more on this below)
-
-  4. can use inline Ruby string replacement (see [:environment]
-     section for more)
-
-  5. default as an addition to a specific search list (more on this
-     in the examples)
-
-  6. can act to subtract from a glob included in the path list (more
-     on this in the examples)
-
-
-[Globs](http://ruby.about.com/od/beginningruby/a/dir2.htm)
-as used by Ceedling are wildcards for specifying directories
-without the need to list each and every required search path.
-Ceedling globs operate just as Ruby globs except that they are
-limited to matching directories and not files. Glob operators
-include the following * ** ? [-] {,} (note: this list is space separated
-and not comma separated as commas are used within the bracket
-operators).
-
-* `*`:
-
-  All subdirectories of depth 1 below the parent path and including the
-  parent path
-
-* `**`:
-
-  All subdirectories recursively discovered below the parent path and
-  including the parent path
-
-* `?`:
-
-  Single alphanumeric character wildcard
-
-* `[x-y]`:
-
-  Single alphanumeric character as found in the specified range
-
-* `{x,y}`:
-
-  Single alphanumeric character from the specified list
-
-Example [:paths] YAML blurbs
-
-```yaml
-:paths:
-  :source:              #together the following comprise all source search paths
-    - project/source/*  #expansion yields all subdirectories of depth 1 plus parent directory
-    - project/lib       #single path
-  :test:                #all test search paths
-    - project/**/test?  #expansion yields any subdirectory found anywhere in the project that
-                        #begins with "test" and contains 5 characters
-
-:paths:
-  :source:                           #all source search paths
-    - +:project/source/**            #all subdirectories recursively discovered plus parent directory
-    - -:project/source/os/generated  #subtract os/generated directory from expansion of above glob
-                                     #note that '+:' notation is merely aesthetic; default is to add
-
-  :test:                             #all test search paths
-    - project/test/bootloader        #explicit, single search paths (searched in the order specified)
-    - project/test/application
-    - project/test/utilities
-
-  :custom:                           #custom path list
-    - "#{PROJECT_ROOT}/other"        #inline Ruby string expansion
-```
-
-Globs and inline Ruby string expansion can require trial and
-error to arrive at your intended results. Use the `ceedling paths:*`
-command line options (documented in preceding section) to verify
-your settings.
-
-Ceedling relies on file collections automagically assembled
-from paths, globs, and file extensions. File collections greatly
-simplify project set up. However, sometimes you need to remove
-from or add individual files to those collections.
-
-
-* `test`:
-
-  Modify the collection of unit test C files.
-
-  **Default**: [] (empty)
-
-* `source`:
-
-  Modify the collection of all source files used in unit test builds and release builds.
-
-  **Default**: [] (empty)
-
-* `assembly`:
-
-  Modify the (optional) collection of assembly files used in release builds.
-
-  **Default**: [] (empty)
-
-* `include`:
-
-  Modify the collection of all source header files used in unit test builds (e.g. for mocking) and release builds.
-
-  **Default**: [] (empty)
-
-* `support`:
-
-  Modify the collection of supporting C files available to unit tests builds.
-
-  **Default**: [] (empty)
-
-
-Note: All path grammar documented in [:paths] section applies
-to [:files] path entries - albeit at the file path level and not
-the directory level.
-
-Example [:files] YAML blurb
-
-```yaml
-:files:
-  :source:
-    - callbacks/comm.c        # entry defaults to file addition
-    - +:callbacks/comm*.c     # add all comm files matching glob pattern
-    - -:source/board/atm134.c # not our board
-  :test:
-    - -:test/io/test_output_manager.c # remove unit tests from test build
-```
-
-**environment:** inserts environment variables into the shell
-instance executing configured tools
-
-Ceedling creates environment variables from any key / value
-pairs in the environment section. Keys become an environment
-variable name in uppercase. The values are strings assigned
-to those environment variables. These value strings are either
-simple string values in YAML or the concatenation of a YAML array.
-
-Ceedling is able to execute inline Ruby string substitution
-code to set environment variables. This evaluation occurs when
-the project file is first processed for any environment pair's
-value string including the Ruby string substitution pattern
-`#{â€Ļ}`. Note that environment value strings that _begin_ with
-this pattern should always be enclosed in quotes. YAML defaults
-to processing unquoted text as a string; quoting text is optional.
-If an environment pair's value string begins with the Ruby string
-substitution pattern, YAML will interpret the string as a Ruby
-comment (because of the `#`). Enclosing each environment value
-string in quotes is a safe practice.
-
-[:environment] entries are processed in the configured order
-(later entries can reference earlier entries).
-
-Special case: PATH handling
-
-In the specific case of specifying an environment key named _path_,
-an array of string values will be concatenated with the appropriate
-platform-specific path separation character (e.g. ':' on *nix,
-';' on Windows). All other instances of environment keys assigned
-YAML arrays use simple concatenation.
-
-Example [:environment] YAML blurb
-
-```yaml
-:environment:
-  - :license_server: gizmo.intranet        #LICENSE_SERVER set with value "gizmo.intranet"
-  - :license: "#{`license.exe`}"           #LICENSE set to string generated from shelling out to
-                                           #execute license.exe; note use of enclosing quotes
-
-  - :path:                                 #concatenated with path separator (see special case above)
-     - Tools/gizmo/bin                     #prepend existing PATH with gizmo path
-     - "#{ENV['PATH']}"                    #pattern #{â€Ļ} triggers ruby evaluation string substitution
-                                           #note: value string must be quoted because of '#'
-
-  - :logfile: system/logs/thingamabob.log  #LOGFILE set with path for a log file
-```
-
-**extension**: configure file name extensions used to collect lists of files searched in [:paths]
-
-* `header`:
-
-  C header files
-
-  **Default**: .h
-
-* `source`:
-
-  C code files (whether source or test files)
-
-  **Default**: .c
-
-* `assembly`:
-
-  Assembly files (contents wholly assembly instructions)
-
-  **Default**: .s
-
-* `object`:
-
-  Resulting binary output of C code compiler (and assembler)
-
-  **Default**: .o
-
-* `executable`:
-
-  Binary executable to be loaded and executed upon target hardware
-
-  **Default**: .exe or .out (Win or *nix)
-
-* `testpass`:
-
-  Test results file (not likely to ever need a new value)
-
-  **Default**: .pass
-
-* `testfail`:
-
-  Test results file (not likely to ever need a new value)
-
-  **Default**: .fail
-
-* `dependencies`:
-
-  File containing make-style dependency rules created by gcc preprocessor
-
-  **Default**: .d
-
-
-Example [:extension] YAML blurb
-
-    :extension:
-      :source: .cc
-      :executable: .bin
-
-**defines**: command line defines used in test and release compilation by configured tools
-
-* `test`:
-
-  Defines needed for testing. Useful for:
-
-  1. test files containing conditional compilation statements (i.e.
-  tests active in only certain contexts)
-
-  2. testing legacy source wherein the isolation of source under test
-  afforded by Ceedling and its complementary tools leaves certain
-  symbols unset when source files are compiled in isolation
-
-  **Default**: [] (empty)
-
-* `test_preprocess`:
-
-  If [:project][:use_test_preprocessor] or
-  [:project][:use_deep_dependencies] is set and code is structured in a
-  certain way, the gcc preprocessor may need symbol definitions to
-  properly preprocess files to extract function signatures for mocking
-  and extract deep dependencies for incremental builds.
-
-  **Default**: [] (empty)
-
-* `release`:
-
-  Defines needed for the release build binary artifact.
-
-  **Default**: [] (empty)
-
-* `release_preprocess`:
-
-  If [:project][:use_deep_dependencies] is set and code is structured in
-  a certain way, the gcc preprocessor may need symbol definitions to
-  properly preprocess files for incremental release builds due to deep
-  dependencies.
-
-  **Default**: [] (empty)
-
-
-Example [:defines] YAML blurb
-
-```yaml
-:defines:
-  :test:
-    - UNIT_TESTING  #for select cases in source to allow testing with a changed behavior or interface
-    - OFF=0
-    - ON=1
-    - FEATURE_X=ON
-  :source:
-    - FEATURE_X=ON
-```
-
-
-**libraries**: command line defines used in test and release compilation by configured tools
-
-Ceedling allows you to pull in specific libraries for the purpose of release and test builds.
-It has a few levels of support for this. Start by adding a :libraries main section in your
-configuration. In this section, you can optionally have the following subsections:
-
-* `test`:
-
-  Library files that should be injected into your tests when linking occurs.
-  These can be specified as either relative or absolute paths. These files MUST
-  exist when the test attempts to build.
-
-* `source`:
-
-  Library files that should be injected into your release when linking occurs. These
-  can be specified as either relative or absolute paths. These files MUST exist when
-  the release attempts to build UNLESS you are using the subprojects plugin. In that
-  case, it will attempt to build that library for you as a dynamic dependency.
-
-* `system`:
-
-  These libraries are assumed to be in the tool path somewhere and shouldn't need to be
-  specified. The libraries added here will be injected into releases and tests.
-
-* `flag`:
-
-  This is the method of adding an argument for each library. For example, gcc really likes
-  it when you specify “-l${1}”
-
-Notes:
-
-* If you've specified your own link step, you are going to want to add ${4} to your argument
-list in the place where library files should be added to the command call. For gcc, this is
-often the very end. Other tools may vary.
-
-
-**flags**: configure per-file compilation and linking flags
-
-Ceedling tools (see later [:tools] section) are used to configure
-compilation and linking of test and source files. These tool
-configurations are a one-size-fits-all approach. Should individual files
-require special compilation or linking flags, the settings in the
-[:flags] section work in conjunction with tool definitions by way of
-argument substitution to achieve this.
-
-* `release`:
-
-  [:compile] or [:link] flags for release build
-
-* `test`:
-
-  [:compile] or [:link] flags for test build
-
-Notes:
-
-* Ceedling works with the [:release] and [:test] build contexts
-  as-is; plugins can add additional contexts
-
-* Only [:compile] and [:link] are recognized operations beneath
-  a context
-
-* File specifiers do not include a path or file extension
-
-* File specifiers are case sensitive (must match original file
-  name)
-
-* File specifiers do support regular expressions if encased in quotes
-
-* '*' is a special (optional) file specifier to provide flags
-  to all files not otherwise specified
-
-
-Example [:flags] YAML blurb
-
-```yaml
-:flags:
-  :release:
-    :compile:
-      :main:       # add '-Wall' to compilation of main.c
-        - -Wall
-      :fan:        # add '--O2' to compilation of fan.c
-        - --O2
-      :'test_.+':   # add '-pedantic' to all test-files
-        - -pedantic
-      :*:          # add '-foo' to compilation of all files not main.c or fan.c
-        - -foo
-  :test:
-    :compile:
-      :main:       # add '--O1' to compilation of main.c as part of test builds including main.c
-        - --O1
-    :link:
-      :test_main:  # add '--bar --baz' to linking of test_main.exe
-        - --bar
-        - --baz
-```
-
-Ceedling sets values for a subset of CMock settings. All CMock
-options are available to be set, but only those options set by
-Ceedling in an automated fashion are documented below. See CMock
-documentation.
-
-**cmock**: configure CMock's code generation options and set symbols used to modify CMock's compiled features
-Ceedling sets values for a subset of CMock settings. All CMock options are available to be set, but only those options set by Ceedling in an automated fashion are documented below. See CMock documentation.
-
-* `enforce_strict_ordering`:
-
-  Tests fail if expected call order is not same as source order
-
-  **Default**: TRUE
-
-* `mock_path`:
-
-  Path for generated mocks
-
-  **Default**: <build path>/tests/mocks
-
-* `defines`:
-
-  List of conditional compilation symbols used to configure CMock's
-  compiled features. See CMock documentation to understand available
-  options. No symbols must be set unless defaults are inappropriate for
-  your specific environment. All symbols are used only by Ceedling to
-  compile CMock C code; contents of [:defines] are ignored by CMock's
-  Ruby code when instantiated.
-
-  **Default**: [] (empty)
-
-* `verbosity`:
-
-  If not set, defaults to Ceedling's verbosity level
-
-* `plugins`:
-
-  If [:project][:use_exceptions] is enabled, the internal plugins list is pre-populated with 'cexception'.
-
-  Whether or not you have included [:cmock][:plugins] in your
-  configuration file, Ceedling automatically adds 'cexception' to the
-  plugin list if exceptions are enabled. To add to the list Ceedling
-  provides CMock, simply add [:cmock][:plugins] to your configuration
-  and specify your desired additional plugins.
-
-* `includes`:
-
-  If [:cmock][:unity_helper] set, pre-populated with unity_helper file
-  name (no path).
-
-  The [:cmock][:includes] list works identically to the plugins list
-  above with regard to adding additional files to be inserted within
-  mocks as #include statements.
-
-
-The last four settings above are directly tied to other Ceedling
-settings; hence, why they are listed and explained here. The
-first setting above, [:enforce_strict_ordering], defaults
-to FALSE within CMock. It is set to TRUE by default in Ceedling
-as our way of encouraging you to use strict ordering. It's a teeny
-bit more expensive in terms of code generated, test execution
-time, and complication in deciphering test failures. However,
-it's good practice. And, of course, you can always disable it
-by overriding the value in the Ceedling YAML configuration file.
-
-
-**cexception**: configure symbols used to modify CException's compiled features
-
-* `defines`:
-
-  List of conditional compilation symbols used to configure CException's
-  features in its source and header files. See CException documentation
-  to understand available options. No symbols must be set unless the
-  defaults are inappropriate for your specific environment.
-
-  **Default**: [] (empty)
-
-
-**unity**: configure symbols used to modify Unity's compiled features
-
-* `defines`:
-
-  List of conditional compilation symbols used to configure Unity's
-  features in its source and header files. See Unity documentation to
-  understand available options. No symbols must be set unless the
-  defaults are inappropriate for your specific environment. Most Unity 
-  defines can be easily configured through the YAML file.
-
-  **Default**: [] (empty)
-
-Example [:unity] YAML blurbs
-```yaml
-:unity: #itty bitty processor & toolchain with limited test execution options
-  :defines:
-    - UNITY_INT_WIDTH=16           #16 bit processor without support for 32 bit instructions
-    - UNITY_EXCLUDE_FLOAT          #no floating point unit
-
-:unity: #great big gorilla processor that grunts and scratches
-  :defines:
-    - UNITY_SUPPORT_64                    #big memory, big counters, big registers
-    - UNITY_LINE_TYPE=\"unsigned int\"    #apparently we're using really long test files,
-    - UNITY_COUNTER_TYPE=\"unsigned int\" #and we've got a ton of test cases in those test files
-    - UNITY_FLOAT_TYPE=\"double\"         #you betcha
-```
-
-
-Notes on Unity configuration:
-
-* **Verification** - Ceedling does no verification of your configuration
-  values. In a properly configured setup, your Unity configuration
-  values are processed, collected together with any test define symbols
-  you specify elsewhere, and then passed to your toolchain during test
-  compilation. Unity's conditional compilation statements, your
-  toolchain's preprocessor, and/or your toolchain's compiler will
-  complain appropriately if your specified configuration values are
-  incorrect, incomplete, or incompatible.
-
-* **Routing $stdout** - Unity defaults to using `putchar()` in C's
-  standard library to display test results. For more exotic environments
-  than a desktop with a terminal (e.g. running tests directly on a
-  non-PC target), you have options. For example, you could create a
-  routine that transmits a character via RS232 or USB. Once you have
-  that routine, you can replace `putchar()` calls in Unity by overriding
-  the function-like macro `UNITY_OUTPUT_CHAR`. Consult your toolchain
-  and shell documentation. Eventhough this can also be defined in the YAML file
-  most shell environments do not handle parentheses as command line arguments 
-  very well. To still be able to add this functionality all necessary 
-  options can be defined in the `unity_config.h`. Unity needs to be told to look for 
-  the `unity_config.h` in the YAML file, though. 
-
-Example [:unity] YAML blurbs
-```yaml
-:unity:
-  :defines:
-  	- UNITY_INCLUDE_CONFIG_H
-```
-
-Example unity_config.h
-```
-#ifndef UNITY_CONFIG_H
-#define UNITY_CONFIG_H
-
-#include "uart_output.h" //Helper library for your custom environment
-
-#define UNITY_INT_WIDTH 16
-#define UNITY_OUTPUT_START() uart_init(F_CPU, BAUD) //Helperfunction to init UART
-#define UNITY_OUTPUT_CHAR(a) uart_putchar(a) //Helperfunction to forward char via UART
-#define UNITY_OUTPUT_COMPLETE() uart_complete() //Helperfunction to inform that test has ended
-
-#endif
-```
-
-
-**tools**: a means for representing command line tools for use under
-Ceedling's automation framework
-
-Ceedling requires a variety of tools to work its magic. By default,
-the GNU toolchain (gcc, cpp, as) are configured and ready for
-use with no additions to the project configuration YAML file.
-However, as most work will require a project-specific toolchain,
-Ceedling provides a generic means for specifying / overriding
-tools.
-
-* `test_compiler`:
-
-  Compiler for test & source-under-test code
-  ${1}: input source ${2}: output object ${3}: optional output list ${4}: optional output dependencies file
-
-  **Default**: gcc
-
-* `test_linker`:
-
-  Linker to generate test fixture executables
-  ${1}: input objects ${2}: output binary ${3}: optional output map ${4}: optional library list
-
-  **Default**: gcc
-
-* `test_fixture`:
-
-  Executable test fixture
-  ${1}: simulator as executable with ${1} as input binary file argument or native test executable
-
-  **Default**: ${1}
-
-* `test_includes_preprocessor`:
-
-  Extractor of #include statements
-  ${1}: input source file
-
-  **Default**: cpp
-
-* `test_file_preprocessor`:
-
-  Preprocessor of test files (macros, conditional compilation statements)
-  ${1}: input source file ${2}: preprocessed output source file
-
-  **Default**: gcc
-
-* `test_dependencies_generator`:
-
-  Discovers deep dependencies of source & test (for incremental builds)
-  ${1}: input source file ${2}: compiled object filepath ${3}: output dependencies file
-
-  **Default**: gcc
-
-* `release_compiler`:
-
-  Compiler for release source code
-  ${1}: input source ${2}: output object ${3}: optional output list ${4}: optional output dependencies file
-
-  **Default**: gcc
-
-* `release_assembler`:
-
-  Assembler for release assembly code
-  ${1}: input assembly source file ${2}: output object file
-
-  **Default**: as
-
-* `release_linker`:
-
-  Linker for release source code
-  ${1}: input objects ${2}: output binary ${3}: optional output map ${4}: optional library list
-
-  **Default**: gcc
-
-* `release_dependencies_generator`:
-
-  Discovers deep dependencies of source files (for incremental builds)
-  ${1}: input source file ${2}: compiled object filepath ${3}: output dependencies file
-
-  **Default**: gcc
-
-
-A Ceedling tool has a handful of configurable elements:
-
-1. [:executable] (required) - Command line executable having
-   the form of:
-
-2. [:arguments] (required) - List of command line arguments
-   and substitutions
-
-3. [:name] - Simple name (e.g. "nickname") of tool beyond its
-   executable name (if not explicitly set then Ceedling will
-   form a name from the tool's YAML entry name)
-
-4. [:stderr_redirect] - Control of capturing $stderr messages
-   {:none, :auto, :win, :unix, :tcsh}.
-   Defaults to :none if unspecified; create a custom entry by
-   specifying a simple string instead of any of the available
-   symbols.
-
-5. [:background_exec] - Control execution as background process
-   {:none, :auto, :win, :unix}.
-   Defaults to :none if unspecified.
-
-
-Tool Element Runtime Substitution
----------------------------------
-
-To accomplish useful work on multiple files, a configured tool will most
-often require that some number of its arguments or even the executable
-itself change for each run. Consequently, every tool's argument list and
-executable field possess two means for substitution at runtime. Ceedling
-provides two kinds of inline Ruby execution and a notation for
-populating elements with dynamically gathered values within the build
-environment.
-
-Tool Element Runtime Substitution: Inline Ruby Execution
---------------------------------------------------------
-
-In-line Ruby execution works similarly to that demonstrated for the
-[:environment] section except that substitution occurs as the tool is
-executed and not at the time the configuration file is first scanned.
-
-* `#{...}`:
-
-  Ruby string substitution pattern wherein the containing string is
-  expanded to include the string generated by Ruby code between the
-  braces. Multiple instances of this expansion can occur within a single
-  tool element entry string. Note that if this string substitution
-  pattern occurs at the very beginning of a string in the YAML
-  configuration the entire string should be enclosed in quotes (see the
-  [:environment] section for further explanation on this point).
-
-* `{...} `:
-
-  If an entire tool element string is enclosed with braces, it signifies
-  that Ceedling should execute the Ruby code contained within those
-  braces. Say you have a collection of paths on disk and some of those
-  paths include spaces. Further suppose that a single tool that must use
-  those paths requires those spaces to be escaped, but all other uses of
-  those paths requires the paths to remain unchanged. You could use this
-  Ceedling feature to insert Ruby code that iterates those paths and
-  escapes those spaces in the array as used by the tool of this example.
-
-Tool Element Runtime Substitution: Notational Substitution
-----------------------------------------------------------
-
-A Ceedling tool's other form of dynamic substitution relies on a '$'
-notation. These '$' operators can exist anywhere in a string and can be
-decorated in any way needed. To use a literal '$', escape it as '\\$'.
-
-* `$`:
-
-  Simple substitution for value(s) globally available within the runtime
-  (most often a string or an array).
-
-* `${#}`:
-
-  When a Ceedling tool's command line is expanded from its configured
-  representation and used within Ceedling Ruby code, certain calls to
-  that tool will be made with a parameter list of substitution values.
-  Each numbered substitution corresponds to a position in a parameter
-  list. Ceedling Ruby code expects that configured compiler and linker
-  tools will contain ${1} and ${2} replacement arguments. In the case of
-  a compiler ${1} will be a C code file path, and ${2} will be the file
-  path of the resulting object file. For a linker ${1} will be an array
-  of object files to link, and ${2} will be the resulting binary
-  executable. For an executable test fixture ${1} is either the binary
-  executable itself (when using a local toolchain such as gcc) or a
-  binary input file given to a simulator in its arguments.
-
-
-Example [:tools] YAML blurbs
-
-```yaml
-:tools:
-  :test_compiler:
-     :executable: compiler              #exists in system search path
-     :name: 'acme test compiler'
-     :arguments:
-        - -I"$": COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE               #expands to -I search paths
-        - -I"$": COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR   #expands to -I search paths
-        - -D$: COLLECTION_DEFINES_TEST_AND_VENDOR  #expands to all -D defined symbols
-        - --network-license             #simple command line argument
-        - -optimize-level 4             #simple command line argument
-        - "#{`args.exe -m acme.prj`}"   #in-line ruby sub to shell out & build string of arguments
-        - -c ${1}                       #source code input file (Ruby method call param list sub)
-        - -o ${2}                       #object file output (Ruby method call param list sub)
-  :test_linker:
-     :executable: /programs/acme/bin/linker.exe    #absolute file path
-     :name: 'acme test linker'
-     :arguments:
-        - ${1}               #list of object files to link (Ruby method call param list sub)
-        - -l$-lib:           #inline yaml array substitution to link in foo-lib and bar-lib
-           - foo
-           - bar
-        - -o ${2}            #executable file output (Ruby method call param list sub)
-  :test_fixture:
-     :executable: tools/bin/acme_simulator.exe  #relative file path to command line simulator
-     :name: 'acme test fixture'
-     :stderr_redirect: :win                     #inform Ceedling what model of $stderr capture to use
-     :arguments:
-        - -mem large   #simple command line argument
-        - -f "${1}"    #binary executable input file to simulator (Ruby method call param list sub)
-```
-
-Resulting command line constructions from preceding example [:tools] YAML blurbs
-
-    > compiler -I"/usr/include” -I”project/tests”
-      -I"project/tests/support” -I”project/source” -I”project/include”
-      -DTEST -DLONG_NAMES -network-license -optimize-level 4 arg-foo
-      arg-bar arg-baz -c project/source/source.c -o
-      build/tests/out/source.o
-
-[notes: (1.) "arg-foo arg-bar arg-baz" is a fabricated example
-string collected from $stdout as a result of shell execution
-of args.exe
-(2.) the -c and -o arguments are
-fabricated examples simulating a single compilation step for
-a test; ${1} & ${2} are single files]
-
-    > \programs\acme\bin\linker.exe thing.o unity.o
-      test_thing_runner.o test_thing.o mock_foo.o mock_bar.o -lfoo-lib
-      -lbar-lib -o build\tests\out\test_thing.exe
-
-[note: in this scenario ${1} is an array of all the object files
-needed to link a test fixture executable]
-
-    > tools\bin\acme_simulator.exe -mem large -f "build\tests\out\test_thing.bin 2>&1”
-
-[note: (1.) :executable could have simply been ${1} - if we were compiling
-and running native executables instead of cross compiling (2.) we're using
-$stderr redirection to allow us to capture simulator error messages to
-$stdout for display at the run's conclusion]
-
-
-Notes:
-
-* The upper case names are Ruby global constants that Ceedling
-  builds
-
-* "COLLECTION_" indicates that Ceedling did some work to assemble
-  the list. For instance, expanding path globs, combining multiple
-  path globs into a convenient summation, etc.
-
-* At present, $stderr redirection is primarily used to capture
-  errors from test fixtures so that they can be displayed at the
-  conclusion of a test run. For instance, if a simulator detects
-  a memory access violation or a divide by zero error, this notice
-  might go unseen in all the output scrolling past in a terminal.
-
-* The preprocessing tools can each be overridden with non-gcc
-  equivalents. However, this is an advanced feature not yet
-  documented and requires that the replacement toolchain conform
-  to the same conventions used by gcc.
-
-**Ceedling Collection Used in Compilation**:
-
-* `COLLECTION_PATHS_TEST`:
-
-  All test paths
-
-* `COLLECTION_PATHS_SOURCE`:
-
-  All source paths
-
-* `COLLECTION_PATHS_INCLUDE`:
-
-  All include paths
-
-* `COLLECTION_PATHS_SUPPORT`:
-
-  All test support paths
-
-* `COLLECTION_PATHS_SOURCE_AND_INCLUDE`:
-
-  All source and include paths
-
-* `COLLECTION_PATHS_SOURCE_INCLUDE_VENDOR`:
-
-  All source and include paths + applicable vendor paths (e.g.
-  CException's source path if exceptions enabled)
-
-* `COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE`:
-
-  All test toolchain include paths
-
-* `COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE`:
-
-  All test, source, and include paths
-
-* `COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR`:
-
-  All test, source, include, and applicable vendor paths (e.g. Unity's
-  source path plus CMock and CException's source paths if mocks and
-  exceptions are enabled)
-
-* `COLLECTION_PATHS_RELEASE_TOOLCHAIN_INCLUDE`:
-
-  All release toolchain include paths
-
-* `COLLECTION_DEFINES_TEST_AND_VENDOR`:
-
-  All symbols specified in [:defines][:test] + symbols defined for
-  enabled vendor tools - e.g. [:unity][:defines], [:cmock][:defines],
-  and [:cexception][:defines]
-
-* `COLLECTION_DEFINES_RELEASE_AND_VENDOR`:
-
-  All symbols specified in [:defines][:release] plus symbols defined by
-[:cexception][:defines] if exceptions are ena bled
-
-
-Notes:
-
-* Other collections exist within Ceedling. However, they are
-  only useful for advanced features not yet documented.
-
-* Wherever multiple path lists are combined for use Ceedling prioritizes
-  path groups as follows: test paths, support paths, source paths, include
-  paths.
-  This can be useful, for instance, in certain testing scenarios
-  where we desire Ceedling or the compiler to find a stand-in header file
-  before the actual source header file of the same name.
-
-
-**plugins**: Ceedling extensions
-
-* `load_paths`:
-
-  Base paths to search for plugin subdirectories or extra ruby functionalit
-
-  **Default**: [] (empty)
-
-* `enabled`:
-
-  List of plugins to be used - a plugin's name is identical to the
-  subdirectory that contains it (and the name of certain files within
-  that subdirectory)
-
-  **Default**: [] (empty)
-
-
-Plugins can provide a variety of added functionality to Ceedling. In
-general use, it's assumed that at least one reporting plugin will be
-used to format test results. However, if no reporting plugins are
-specified, Ceedling will print to `$stdout` the (quite readable) raw
-test results from all test fixtures executed.
-
-Example [:plugins] YAML blurb
-
-```yaml
-:plugins:
-  :load_paths:
-    - project/tools/ceedling/plugins  #home to your collection of plugin directories
-    - project/support                 #maybe home to some ruby code your custom plugins share
-  :enabled:
-    - stdout_pretty_tests_report      #nice test results at your command line
-    - our_custom_code_metrics_report  #maybe you needed line count and complexity metrics, so you
-                                      #created a plugin to scan all your code and collect that info
-```
-
-* `stdout_pretty_tests_report`:
-
-  Prints to $stdout a well-formatted list of ignored and failed tests,
-  final test counts, and any extraneous output (e.g. printf statements
-  or simulator memory errors) collected from executing the test
-  fixtures. Meant to be used with runs at the command line.
-
-* `stdout_ide_tests_report`:
-
-  Prints to $stdout simple test results formatted such that an IDE
-  executing test-related Rake tasks can recognize file paths and line
-  numbers in test failures, etc. Thus, you can click a test result in
-  your IDE's execution window and jump to the failure (or ignored test)
-  in your test file (obviously meant to be used with an [IDE like
-  Eclipse][ide], etc).
-
-  [ide]: http://throwtheswitch.org/white-papers/using-with-ides.html
-
-* `xml_tests_report`:
-
-  Creates an XML file of test results in the xUnit format (handy for
-  Continuous Integration build servers or as input to other reporting
-  tools). Produces a file report.xml in <build root>/artifacts/tests.
-
-* `bullseye`:
-
-  Adds additional Rake tasks to execute tests with the commercial code
-  coverage tool provided by [Bullseye][]. See readme.txt inside the bullseye
-  plugin directory for configuration and use instructions. Note:
-  Bullseye only works with certain compilers and linkers (healthy list
-  of supported toolchains though).
-
-  [bullseye]: http://www.bullseye.com
-
-* `gcov`:
-
-  Adds additional Rake tasks to execute tests with the GNU code coverage
-  tool [gcov][]. See readme.txt inside the gcov directory for configuration
-  and use instructions. Only works with GNU compiler and linker.
-
-  [gcov]: http://gcc.gnu.org/onlinedocs/gcc/Gcov.html
-
-* `warnings_report`:
-
-  Scans compiler and linker `$stdout / $stderr` output for the word
-  'warning' (case insensitive). All code warnings (or tool warnings) are
-  logged to a file warnings.log in the appropriate `<build
-  root>/artifacts` directory (e.g. test/ for test tasks, `release/` for a
-  release build, or even `bullseye/` for bullseye runs).
-
-Module Generator
-========================
-Ceedling includes a plugin called module_generator that will create a source, header and test file for you.
-There are several possibilities to configure this plugin through your project.yml to suit your project's needs.
-
-Directory Structure
--------------------------------------------
-
-The default configuration for directory/project structure is:
-```yaml
-:module_generator:
-  :project_root: ./
-  :source_root: src/
-  :test_root: test/
-```
-You can change these variables in your project.yml file to comply with your project's directory structure.
-
-If you call `ceedling module:create`, it will create three files:
-1. A source file in the source_root
-2. A header file in the source_root
-3. A test file in the test_root
-
-If you want your header file to be in another location,
-you can specify the ':inc_root:" in your project.yml file:
-```yaml
-:module_generator:
-  :inc_root: inc/
-```
-The module_generator will then create the header file in your defined ':inc_root:'.
-By default, ':inc_root:' is not defined so the module_generator will use the source_root.
-
-Sometimes, your project can't be divided into a single src, inc, and test folder. You have several directories
-with sources/..., something like this for example:
-<project_root>
- - myDriver
-   - src
-   - inc
-   - test
- - myOtherDriver
-   - src
-   - inc
-   - test
- - ...
-
-Don't worry, you don't have to manually create the source/header/test files.
-The module_generator can accept a path to create a source_root/inc_root/test_root folder with your files:
-`ceedling module:create[<module_root_path>:<module_name>]`
-
-F.e., applied to the above project structure:
-`ceedling module:create[myOtherDriver:driver]`
-This will make the module_generator run in the subdirectory 'myOtherDriver' and generate the module files
-for you in that directory. So, this command will generate the following files:
-1. A source file 'driver.c' in <project_root>/myOtherDriver/<source_root>
-2. A header file 'driver.h' in <project_root>/myOtherDriver/<source_root> (or <inc_root> if specified)
-3. A test file 'test_driver.c' in <project_root>/myOtherDriver/<test_root>
-
-Naming
--------------------------------------------
-By default, the module_generator will generate your files in lowercase.
-`ceedling module:create[mydriver]` and `ceedling module:create[myDriver]`(note the uppercase) will generate the same files:
-1. mydriver.c
-2. mydriver.h
-3. test_mydriver.c
-
-You can configure the module_generator to use a differect naming mechanism through the project.yml:
-```yaml
-:module_generator:
-  :naming: "camel"
-```
-There are other possibilities as well (bumpy, camel, snake, caps).
-Refer to the unity module generator for more info (the unity module generator is used under the hood by module_generator).
-
-Advanced Topics (Coming)
-========================
-
-Modifying Your Configuration without Modifying Your Project File: Option Files & User Files
--------------------------------------------------------------------------------------------
-
-Modifying your project file without modifying your project file
-
-Debugging and/or printf()
--------------------------
-
-When you gotta get your hands dirty...
-
-Ceedling Plays Nice with Others - Using Ceedling for Tests Alongside Another Release Build Setup
-------------------------------------------------------------------------------------------------
-
-You've got options.
-
-Adding Handy Rake Tasks for Your Project (without Fancy Pants Custom Plugins)
------------------------------------------------------------------------------
-
-Simple as snot.
-
-Working with Non-Desktop Testing Environments
----------------------------------------------
-
-For those crazy platforms lacking command line simulators and for which
-cross-compiling on the desktop just ain't gonna get it done.
-
-Creating Custom Plugins
------------------------
-
-Oh boy. This is going to take some explaining.
diff --git a/test/vendor/ceedling/docs/ThrowTheSwitchCodingStandard.md b/test/vendor/ceedling/docs/ThrowTheSwitchCodingStandard.md
deleted file mode 100644
index bf4c099bb..000000000
--- a/test/vendor/ceedling/docs/ThrowTheSwitchCodingStandard.md
+++ /dev/null
@@ -1,206 +0,0 @@
-īģŋ# ThrowTheSwitch.org Coding Standard
-
-Hi. Welcome to the coding standard for ThrowTheSwitch.org. For the most part,
-we try to follow these standards to unify our contributors' code into a cohesive
-unit (puns intended). You might find places where these standards aren't
-followed. We're not perfect. Please be polite where you notice these discrepancies
-and we'll try to be polite when we notice yours.
-
-;)
-
-
-## Why Have A Coding Standard?
-
-Being consistent makes code easier to understand. We've tried to keep
-our standard simple because we also believe that we can only expect someone to
-follow something that is understandable. Please do your best.
-
-
-## Our Philosophy
-
-Before we get into details on syntax, let's take a moment to talk about our
-vision for these tools. We're C developers and embedded software developers.
-These tools are great to test any C code, but catering to embedded software has
-made us more tolerant of compiler quirks. There are a LOT of quirky compilers
-out there. By quirky I mean "doesn't follow standards because they feel like
-they have a license to do as they wish."
-
-Our philosophy is "support every compiler we can". Most often, this means that
-we aim for writing C code that is standards compliant (often C89... that seems
-to be a sweet spot that is almost always compatible). But it also means these
-tools are tolerant of things that aren't common. Some that aren't even
-compliant. There are configuration options to override the size of standard
-types. There are configuration options to force Unity to not use certain
-standard library functions. A lot of Unity is configurable and we have worked
-hard to make it not TOO ugly in the process.
-
-Similarly, our tools that parse C do their best. They aren't full C parsers
-(yet) and, even if they were, they would still have to accept non-standard
-additions like gcc extensions or specifying `@0x1000` to force a variable to
-compile to a particular location. It's just what we do, because we like
-everything to Just Workâ„ĸ.
-
-Speaking of having things Just Workâ„ĸ, that's our second philosophy. By that, we
-mean that we do our best to have EVERY configuration option have a logical
-default. We believe that if you're working with a simple compiler and target,
-you shouldn't need to configure very much... we try to make the tools guess as
-much as they can, but give the user the power to override it when it's wrong.
-
-
-## Naming Things
-
-Let's talk about naming things. Programming is all about naming things. We name
-files, functions, variables, and so much more. While we're not always going to
-find the best name for something, we actually put a bit of effort into
-finding *What Something WANTS to be Called*â„ĸ.
-
-When naming things, we follow this hierarchy, the first being the
-most important to us (but we do all four when possible):
-1. Readable
-2. Descriptive
-3. Consistent
-4. Memorable
-
-
-#### Readable
-
-We want to read our code. This means we like names and flow that are more
-naturally read. We try to avoid double negatives. We try to avoid cryptic
-abbreviations (sticking to ones we feel are common).
-
-
-#### Descriptive
-
-We like descriptive names for things, especially functions and variables.
-Finding the right name for something is an important endeavor. You might notice
-from poking around our code that this often results in names that are a little
-longer than the average. Guilty. We're okay with a bit more typing if it
-means our code is easier to understand.
-
-There are two exceptions to this rule that we also stick to as religiously as
-possible:
-
-First, while we realize hungarian notation (and similar systems for encoding
-type information into variable names) is providing a more descriptive name, we
-feel that (for the average developer) it takes away from readability and is to be avoided.
-
-Second, loop counters and other local throw-away variables often have a purpose
-which is obvious. There's no need, therefore, to get carried away with complex
-naming. We find i, j, and k are better loop counters than loopCounterVar or
-whatnot. We only break this rule when we see that more description could improve
-understanding of an algorithm.
-
-
-#### Consistent
-
-We like consistency, but we're not really obsessed with it. We try to name our
-configuration macros in a consistent fashion... you'll notice a repeated use of
-UNITY_EXCLUDE_BLAH or UNITY_USES_BLAH macros. This helps users avoid having to
-remember each macro's details.
-
-
-#### Memorable
-
-Where ever it doesn't violate the above principles, we try to apply memorable
-names. Sometimes this means using something that is simply descriptive, but
-often we strive for descriptive AND unique... we like quirky names that stand
-out in our memory and are easier to search for. Take a look through the file
-names in Ceedling and you'll get a good idea of what we are talking about here.
-Why use preprocess when you can use preprocessinator? Or what better describes a
-module in charge of invoking tasks during releases than release_invoker? Don't
-get carried away. The names are still descriptive and fulfill the above
-requirements, but they don't feel stale.
-
-
-## C and C++ Details
-
-We don't really want to add to the style battles out there. Tabs or spaces?
-How many spaces? Where do the braces go? These are age-old questions that will
-never be answered... or at least not answered in a way that will make everyone
-happy.
-
-We've decided on our own style preferences. If you'd like to contribute to these
-projects (and we hope that you do), then we ask if you do your best to follow
-the same. It will only hurt a little. We promise.
-
-
-#### Whitespace
-
-Our C-style is to use spaces and to use 4 of them per indent level. It's a nice
-power-of-2 number that looks decent on a wide-screen. We have no more reason
-than that. We break that rule when we have lines that wrap (macros or function
-arguments or whatnot). When that happens, we like to indent further to line
-things up in nice tidy columns.
-
-```C
-    if (stuff_happened)
-    {
-        do_something();
-    }
-```
-
-
-#### Case
-
-- Files - all lower case with underscores.
-- Variables - all lower case with underscores
-- Macros - all caps with underscores.
-- Typedefs - all caps with underscores. (also ends with _T).
-- Functions - camel cased. Usually named ModuleName_FuncName
-- Constants and Globals - camel cased.
-
-
-#### Braces
-
-The left brace is on the next line after the declaration. The right brace is
-directly below that. Everything in between in indented one level. If you're
-catching an error and you have a one-line, go ahead and to it on the same line.
-
-```C
-    while (blah)
-    {
-        //Like so. Even if only one line, we use braces.
-    }
-```
-
-
-#### Comments
-
-Do you know what we hate? Old-school C block comments. BUT, we're using them
-anyway. As we mentioned, our goal is to support every compiler we can,
-especially embedded compilers. There are STILL C compilers out there that only
-support old-school block comments. So that is what we're using. We apologize. We
-think they are ugly too.
-
-
-## Ruby Details
-
-Is there really such thing as a Ruby coding standard? Ruby is such a free form
-language, it seems almost sacrilegious to suggest that people should comply to
-one method! We'll keep it really brief!
-
-
-#### Whitespace
-
-Our Ruby style is to use spaces and to use 2 of them per indent level. It's a
-nice power-of-2 number that really grooves with Ruby's compact style. We have no
-more reason than that. We break that rule when we have lines that wrap. When
-that happens, we like to indent further to line things up in nice tidy columns.
-
-
-#### Case
-
-- Files - all lower case with underscores.
-- Variables - all lower case with underscores
-- Classes, Modules, etc - Camel cased.
-- Functions - all lower case with underscores
-- Constants - all upper case with underscores
-
-
-## Documentation
-
-Egad. Really? We use mark down and we like pdf files because they can be made to
-look nice while still being portable. Good enough?
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/docs/UnityAssertionsCheatSheetSuitableforPrintingandPossiblyFraming.pdf b/test/vendor/ceedling/docs/UnityAssertionsCheatSheetSuitableforPrintingandPossiblyFraming.pdf
deleted file mode 100644
index 28f0c3214..000000000
Binary files a/test/vendor/ceedling/docs/UnityAssertionsCheatSheetSuitableforPrintingandPossiblyFraming.pdf and /dev/null differ
diff --git a/test/vendor/ceedling/docs/UnityAssertionsReference.md b/test/vendor/ceedling/docs/UnityAssertionsReference.md
deleted file mode 100644
index eb855f3c0..000000000
--- a/test/vendor/ceedling/docs/UnityAssertionsReference.md
+++ /dev/null
@@ -1,779 +0,0 @@
-# Unity Assertions Reference
-
-## Background and Overview
-
-### Super Condensed Version
-
-- An assertion establishes truth (i.e. boolean True) for a single condition.
-Upon boolean False, an assertion stops execution and reports the failure.
-- Unity is mainly a rich collection of assertions and the support to gather up
-and easily execute those assertions.
-- The structure of Unity allows you to easily separate test assertions from
-source code in, well, test code.
-- Unity's assertions:
-- Come in many, many flavors to handle different C types and assertion cases.
-- Use context to provide detailed and helpful failure messages.
-- Document types, expected values, and basic behavior in your source code for
-free.
-
-
-### Unity Is Several Things But Mainly It's Assertions
-
-One way to think of Unity is simply as a rich collection of assertions you can
-use to establish whether your source code behaves the way you think it does.
-Unity provides a framework to easily organize and execute those assertions in
-test code separate from your source code.
-
-
-### What's an Assertion?
-
-At their core, assertions are an establishment of truth - boolean truth. Was this
-thing equal to that thing? Does that code doohickey have such-and-such property
-or not? You get the idea. Assertions are executable code (to appreciate the big
-picture on this read up on the difference between
-[link:Dynamic Verification and Static Analysis]). A failing assertion stops
-execution and reports an error through some appropriate I/O channel (e.g.
-stdout, GUI, file, blinky light).
-
-Fundamentally, for dynamic verification all you need is a single assertion
-mechanism. In fact, that's what the [assert() macro in C's standard library](http://en.wikipedia.org/en/wiki/Assert.h)
-is for. So why not just use it? Well, we can do far better in the reporting
-department. C's `assert()` is pretty dumb as-is and is particularly poor for
-handling common data types like arrays, structs, etc. And, without some other
-support, it's far too tempting to litter source code with C's `assert()`'s. It's
-generally much cleaner, manageable, and more useful to separate test and source
-code in the way Unity facilitates.
-
-
-### Unity's Assertions: Helpful Messages _and_ Free Source Code Documentation
-
-Asserting a simple truth condition is valuable, but using the context of the
-assertion is even more valuable. For instance, if you know you're comparing bit
-flags and not just integers, then why not use that context to give explicit,
-readable, bit-level feedback when an assertion fails?
-
-That's what Unity's collection of assertions do - capture context to give you
-helpful, meaningful assertion failure messages. In fact, the assertions
-themselves also serve as executable documentation about types and values in your
-source code. So long as your tests remain current with your source and all those
-tests pass, you have a detailed, up-to-date view of the intent and mechanisms in
-your source code. And due to a wondrous mystery, well-tested code usually tends
-to be well designed code.
-
-
-## Assertion Conventions and Configurations
-
-### Naming and Parameter Conventions
-
-The convention of assertion parameters generally follows this order:
-
-    TEST_ASSERT_X( {modifiers}, {expected}, actual, {size/count} )
-
-The very simplest assertion possible uses only a single "actual" parameter (e.g.
-a simple null check).
-
-"Actual" is the value being tested and unlike the other parameters in an
-assertion construction is the only parameter present in all assertion variants.
-"Modifiers" are masks, ranges, bit flag specifiers, floating point deltas.
-"Expected" is your expected value (duh) to compare to an "actual" value; it's
-marked as an optional parameter because some assertions only need a single
-"actual" parameter (e.g. null check).
-"Size/count" refers to string lengths, number of array elements, etc.
-
-Many of Unity's assertions are clear duplications in that the same data type
-is handled by several assertions. The differences among these are in how failure
-messages are presented. For instance, a `_HEX` variant of an assertion prints
-the expected and actual values of that assertion formatted as hexadecimal.
-
-
-#### TEST_ASSERT_X_MESSAGE Variants
-
-_All_ assertions are complemented with a variant that includes a simple string
-message as a final parameter. The string you specify is appended to an assertion
-failure message in Unity output.
-
-For brevity, the assertion variants with a message parameter are not listed
-below. Just tack on `_MESSAGE` as the final component to any assertion name in
-the reference list below and add a string as the final parameter.
-
-_Example:_
-
-    TEST_ASSERT_X( {modifiers}, {expected}, actual, {size/count} )
-
-becomes messageified like thus...
-
-    TEST_ASSERT_X_MESSAGE( {modifiers}, {expected}, actual, {size/count}, message )
-
-Notes:
-- The `_MESSAGE` variants intentionally do not support `printf` style formatting 
-  since many embedded projects don't support or avoid `printf` for various reasons.
-  It is possible to use `sprintf` before the assertion to assemble a complex fail
-  message, if necessary.
-- If you want to output a counter value within an assertion fail message (e.g. from 
-  a loop) , building up an array of results and then using one of the `_ARRAY` 
-  assertions (see below) might be a handy alternative to `sprintf`.
-
-
-#### TEST_ASSERT_X_ARRAY Variants
-
-Unity provides a collection of assertions for arrays containing a variety of
-types. These are documented in the Array section below. These are almost on par
-with the `_MESSAGE`variants of Unity's Asserts in that for pretty much any Unity
-type assertion you can tack on `_ARRAY` and run assertions on an entire block of
-memory.
-
-    TEST_ASSERT_EQUAL_TYPEX_ARRAY( expected, actual, {size/count} )
-
-"Expected" is an array itself.
-"Size/count" is one or two parameters necessary to establish the number of array
-elements and perhaps the length of elements within the array.
-
-Notes:
-- The `_MESSAGE` variant convention still applies here to array assertions. The
-`_MESSAGE` variants of the `_ARRAY` assertions have names ending with
-`_ARRAY_MESSAGE`.
-- Assertions for handling arrays of floating point values are grouped with float
-and double assertions (see immediately following section).
-
-
-### TEST_ASSERT_EACH_EQUAL_X Variants
-
-Unity provides a collection of assertions for arrays containing a variety of
-types which can be compared to a single value as well. These are documented in
-the Each Equal section below. these are almost on par with the `_MESSAGE`
-variants of Unity's Asserts in that for pretty much any Unity type assertion you
-can inject _EACH_EQUAL and run assertions on an entire block of memory.
-
-    TEST_ASSERT_EACH_EQUAL_TYPEX( expected, actual, {size/count} )
-
-"Expected" is a single value to compare to.
-"Actual" is an array where each element will be compared to the expected value.
-"Size/count" is one of two parameters necessary to establish the number of array
-elements and perhaps the length of elements within the array.
-
-Notes:
-- The `_MESSAGE` variant convention still applies here to Each Equal assertions.
-- Assertions for handling Each Equal of floating point values are grouped with
-float and double assertions (see immediately following section).
-
-
-### Configuration
-
-#### Floating Point Support Is Optional
-
-Support for floating point types is configurable. That is, by defining the
-appropriate preprocessor symbols, floats and doubles can be individually enabled
-or disabled in Unity code. This is useful for embedded targets with no floating
-point math support (i.e. Unity compiles free of errors for fixed point only
-platforms). See Unity documentation for specifics.
-
-
-#### Maximum Data Type Width Is Configurable
-
-Not all targets support 64 bit wide types or even 32 bit wide types. Define the
-appropriate preprocessor symbols and Unity will omit all operations from
-compilation that exceed the maximum width of your target. See Unity
-documentation for specifics.
-
-
-## The Assertions in All Their Blessed Glory
-
-### Basic Fail and Ignore
-
-##### `TEST_FAIL()`
-
-This fella is most often used in special conditions where your test code is
-performing logic beyond a simple assertion. That is, in practice, `TEST_FAIL()`
-will always be found inside a conditional code block.
-
-_Examples:_
-- Executing a state machine multiple times that increments a counter your test
-code then verifies as a final step.
-- Triggering an exception and verifying it (as in Try / Catch / Throw - see the
-[CException](https://github.com/ThrowTheSwitch/CException) project).
-
-##### `TEST_IGNORE()`
-
-Marks a test case (i.e. function meant to contain test assertions) as ignored.
-Usually this is employed as a breadcrumb to come back and implement a test case.
-An ignored test case has effects if other assertions are in the enclosing test
-case (see Unity documentation for more).
-
-### Boolean
-
-##### `TEST_ASSERT (condition)`
-
-##### `TEST_ASSERT_TRUE (condition)`
-
-##### `TEST_ASSERT_FALSE (condition)`
-
-##### `TEST_ASSERT_UNLESS (condition)`
-
-A simple wording variation on `TEST_ASSERT_FALSE`.The semantics of
-`TEST_ASSERT_UNLESS` aid readability in certain test constructions or
-conditional statements.
-
-##### `TEST_ASSERT_NULL (pointer)`
-
-##### `TEST_ASSERT_NOT_NULL (pointer)`
-
-
-### Signed and Unsigned Integers (of all sizes)
-
-Large integer sizes can be disabled for build targets that do not support them.
-For example, if your target only supports up to 16 bit types, by defining the
-appropriate symbols Unity can be configured to omit 32 and 64 bit operations
-that would break compilation (see Unity documentation for more). Refer to
-Advanced Asserting later in this document for advice on dealing with other word
-sizes.
-
-##### `TEST_ASSERT_EQUAL_INT (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_INT8 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_INT16 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_INT32 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_INT64 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL (expected, actual)`
-
-##### `TEST_ASSERT_NOT_EQUAL (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT8 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT16 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT32 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT64 (expected, actual)`
-
-
-### Unsigned Integers (of all sizes) in Hexadecimal
-
-All `_HEX` assertions are identical in function to unsigned integer assertions
-but produce failure messages with the `expected` and `actual` values formatted
-in hexadecimal. Unity output is big endian.
-
-##### `TEST_ASSERT_EQUAL_HEX (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_HEX8 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_HEX16 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_HEX32 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_HEX64 (expected, actual)`
-
-
-### Masked and Bit-level Assertions
-
-Masked and bit-level assertions produce output formatted in hexadecimal. Unity
-output is big endian.
-
-
-##### `TEST_ASSERT_BITS (mask, expected, actual)`
-
-Only compares the masked (i.e. high) bits of `expected` and `actual` parameters.
-
-
-##### `TEST_ASSERT_BITS_HIGH (mask, actual)`
-
-Asserts the masked bits of the `actual` parameter are high.
-
-
-##### `TEST_ASSERT_BITS_LOW (mask, actual)`
-
-Asserts the masked bits of the `actual` parameter are low.
-
-
-##### `TEST_ASSERT_BIT_HIGH (bit, actual)`
-
-Asserts the specified bit of the `actual` parameter is high.
-
-
-##### `TEST_ASSERT_BIT_LOW (bit, actual)`
-
-Asserts the specified bit of the `actual` parameter is low.
-
-### Integer Less Than / Greater Than
-
-These assertions verify that the `actual` parameter is less than or greater
-than `threshold` (exclusive). For example, if the threshold value is 0 for the
-greater than assertion will fail if it is 0 or less.
-
-##### `TEST_ASSERT_GREATER_THAN (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_INT (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_INT8 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_INT16 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_INT32 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_UINT (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_UINT8 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_UINT16 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_UINT32 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_HEX8 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_HEX16 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_HEX32 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_INT (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_INT8 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_INT16 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_INT32 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_UINT (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_UINT8 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_UINT16 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_UINT32 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_HEX8 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_HEX16 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_HEX32 (threshold, actual)`
-
-
-### Integer Ranges (of all sizes)
-
-These assertions verify that the `expected` parameter is within +/- `delta`
-(inclusive) of the `actual` parameter. For example, if the expected value is 10
-and the delta is 3 then the assertion will fail for any value outside the range
-of 7 - 13.
-
-##### `TEST_ASSERT_INT_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_INT8_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_INT16_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_INT32_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_INT64_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT8_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT16_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT32_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT64_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX8_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX16_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX32_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX64_WITHIN (delta, expected, actual)`
-
-
-### Structs and Strings
-
-##### `TEST_ASSERT_EQUAL_PTR (expected, actual)`
-
-Asserts that the pointers point to the same memory location.
-
-
-##### `TEST_ASSERT_EQUAL_STRING (expected, actual)`
-
-Asserts that the null terminated (`'\0'`)strings are identical. If strings are
-of different lengths or any portion of the strings before their terminators
-differ, the assertion fails. Two NULL strings (i.e. zero length) are considered
-equivalent.
-
-
-##### `TEST_ASSERT_EQUAL_MEMORY (expected, actual, len)`
-
-Asserts that the contents of the memory specified by the `expected` and `actual`
-pointers is identical. The size of the memory blocks in bytes is specified by
-the `len` parameter.
-
-
-### Arrays
-
-`expected` and `actual` parameters are both arrays. `num_elements` specifies the
-number of elements in the arrays to compare.
-
-`_HEX` assertions produce failure messages with expected and actual array
-contents formatted in hexadecimal.
-
-For array of strings comparison behavior, see comments for
-`TEST_ASSERT_EQUAL_STRING` in the preceding section.
-
-Assertions fail upon the first element in the compared arrays found not to
-match. Failure messages specify the array index of the failed comparison.
-
-##### `TEST_ASSERT_EQUAL_INT_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_INT8_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_INT16_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_INT32_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_INT64_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT8_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT16_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT32_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT64_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX8_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX16_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX32_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX64_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_PTR_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_STRING_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_MEMORY_ARRAY (expected, actual, len, num_elements)`
-
-`len` is the memory in bytes to be compared at each array element.
-
-
-### Each Equal (Arrays to Single Value)
-
-`expected` are single values and `actual` are arrays. `num_elements` specifies
-the number of elements in the arrays to compare.
-
-`_HEX` assertions produce failure messages with expected and actual array
-contents formatted in hexadecimal.
-
-Assertions fail upon the first element in the compared arrays found not to
-match. Failure messages specify the array index of the failed comparison.
-
-#### `TEST_ASSERT_EACH_EQUAL_INT (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_INT8 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_INT16 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_INT32 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_INT64 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT8 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT16 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT32 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT64 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX8 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX16 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX32 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX64 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_PTR (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_STRING (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_MEMORY (expected, actual, len, num_elements)`
-
-`len` is the memory in bytes to be compared at each array element.
-
-
-### Floating Point (If enabled)
-
-##### `TEST_ASSERT_FLOAT_WITHIN (delta, expected, actual)`
-
-Asserts that the `actual` value is within +/- `delta` of the `expected` value.
-The nature of floating point representation is such that exact evaluations of
-equality are not guaranteed.
-
-
-##### `TEST_ASSERT_EQUAL_FLOAT (expected, actual)`
-
-Asserts that the ?actual?value is "close enough to be considered equal" to the
-`expected` value. If you are curious about the details, refer to the Advanced
-Asserting section for more details on this. Omitting a user-specified delta in a
-floating point assertion is both a shorthand convenience and a requirement of
-code generation conventions for CMock.
-
-
-##### `TEST_ASSERT_EQUAL_FLOAT_ARRAY (expected, actual, num_elements)`
-
-See Array assertion section for details. Note that individual array element
-float comparisons are executed using T?EST_ASSERT_EQUAL_FLOAT?.That is, user
-specified delta comparison values requires a custom-implemented floating point
-array assertion.
-
-
-##### `TEST_ASSERT_FLOAT_IS_INF (actual)`
-
-Asserts that `actual` parameter is equivalent to positive infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NEG_INF (actual)`
-
-Asserts that `actual` parameter is equivalent to negative infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NAN (actual)`
-
-Asserts that `actual` parameter is a Not A Number floating point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_DETERMINATE (actual)`
-
-Asserts that ?actual?parameter is a floating point representation usable for
-mathematical operations. That is, the `actual` parameter is neither positive
-infinity nor negative infinity nor Not A Number floating point representations.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NOT_INF (actual)`
-
-Asserts that `actual` parameter is a value other than positive infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NOT_NEG_INF (actual)`
-
-Asserts that `actual` parameter is a value other than negative infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NOT_NAN (actual)`
-
-Asserts that `actual` parameter is a value other than Not A Number floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE (actual)`
-
-Asserts that `actual` parameter is not usable for mathematical operations. That
-is, the `actual` parameter is either positive infinity or negative infinity or
-Not A Number floating point representations.
-
-
-### Double (If enabled)
-
-##### `TEST_ASSERT_DOUBLE_WITHIN (delta, expected, actual)`
-
-Asserts that the `actual` value is within +/- `delta` of the `expected` value.
-The nature of floating point representation is such that exact evaluations of
-equality are not guaranteed.
-
-
-##### `TEST_ASSERT_EQUAL_DOUBLE (expected, actual)`
-
-Asserts that the `actual` value is "close enough to be considered equal" to the
-`expected` value. If you are curious about the details, refer to the Advanced
-Asserting section for more details. Omitting a user-specified delta in a
-floating point assertion is both a shorthand convenience and a requirement of
-code generation conventions for CMock.
-
-
-##### `TEST_ASSERT_EQUAL_DOUBLE_ARRAY (expected, actual, num_elements)`
-
-See Array assertion section for details. Note that individual array element
-double comparisons are executed using `TEST_ASSERT_EQUAL_DOUBLE`.That is, user
-specified delta comparison values requires a custom implemented double array
-assertion.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_INF (actual)`
-
-Asserts that `actual` parameter is equivalent to positive infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NEG_INF (actual)`
-
-Asserts that `actual` parameter is equivalent to negative infinity floating point
-representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NAN (actual)`
-
-Asserts that `actual` parameter is a Not A Number floating point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_DETERMINATE (actual)`
-
-Asserts that `actual` parameter is a floating point representation usable for
-mathematical operations. That is, the ?actual?parameter is neither positive
-infinity nor negative infinity nor Not A Number floating point representations.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NOT_INF (actual)`
-
-Asserts that `actual` parameter is a value other than positive infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF (actual)`
-
-Asserts that `actual` parameter is a value other than negative infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NOT_NAN (actual)`
-
-Asserts that `actual` parameter is a value other than Not A Number floating
-point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE (actual)`
-
-Asserts that `actual` parameter is not usable for mathematical operations. That
-is, the `actual` parameter is either positive infinity or negative infinity or
-Not A Number floating point representations.
-
-
-## Advanced Asserting: Details On Tricky Assertions
-
-This section helps you understand how to deal with some of the trickier
-assertion situations you may run into. It will give you a glimpse into some of
-the under-the-hood details of Unity's assertion mechanisms. If you're one of
-those people who likes to know what is going on in the background, read on. If
-not, feel free to ignore the rest of this document until you need it.
-
-
-### How do the EQUAL assertions work for FLOAT and DOUBLE?
-
-As you may know, directly checking for equality between a pair of floats or a
-pair of doubles is sloppy at best and an outright no-no at worst. Floating point
-values can often be represented in multiple ways, particularly after a series of
-operations on a value. Initializing a variable to the value of 2.0 is likely to
-result in a floating point representation of 2 x 20,but a series of
-mathematical operations might result in a representation of 8 x 2-2
-that also evaluates to a value of 2. At some point repeated operations cause
-equality checks to fail.
-
-So Unity doesn't do direct floating point comparisons for equality. Instead, it
-checks if two floating point values are "really close." If you leave Unity
-running with defaults, "really close" means "within a significant bit or two."
-Under the hood, `TEST_ASSERT_EQUAL_FLOAT` is really `TEST_ASSERT_FLOAT_WITHIN`
-with the `delta` parameter calculated on the fly. For single precision, delta is
-the expected value multiplied by 0.00001, producing a very small proportional
-range around the expected value.
-
-If you are expecting a value of 20,000.0 the delta is calculated to be 0.2. So
-any value between 19,999.8 and 20,000.2 will satisfy the equality check. This
-works out to be roughly a single bit of range for a single-precision number, and
-that's just about as tight a tolerance as you can reasonably get from a floating
-point value.
-
-So what happens when it's zero? Zero - even more than other floating point
-values - can be represented many different ways. It doesn't matter if you have
-0 x 20 or 0 x 263.It's still zero, right? Luckily, if you
-subtract these values from each other, they will always produce a difference of
-zero, which will still fall between 0 plus or minus a delta of 0. So it still
-works!
-
-Double precision floating point numbers use a much smaller multiplier, again
-approximating a single bit of error.
-
-If you don't like these ranges and you want to make your floating point equality
-assertions less strict, you can change these multipliers to whatever you like by
-defining UNITY_FLOAT_PRECISION and UNITY_DOUBLE_PRECISION. See Unity
-documentation for more.
-
-
-### How do we deal with targets with non-standard int sizes?
-
-It's "fun" that C is a standard where something as fundamental as an integer
-varies by target. According to the C standard, an `int` is to be the target's
-natural register size, and it should be at least 16-bits and a multiple of a
-byte. It also guarantees an order of sizes:
-
-```C
-char <= short <= int <= long <= long long
-```
-
-Most often, `int` is 32-bits. In many cases in the embedded world, `int` is
-16-bits. There are rare microcontrollers out there that have 24-bit integers,
-and this remains perfectly standard C.
-
-To make things even more interesting, there are compilers and targets out there
-that have a hard choice to make. What if their natural register size is 10-bits
-or 12-bits? Clearly they can't fulfill _both_ the requirement to be at least
-16-bits AND the requirement to match the natural register size. In these
-situations, they often choose the natural register size, leaving us with
-something like this:
-
-```C
-char (8 bit) <= short (12 bit) <= int (12 bit) <= long (16 bit)
-```
-
-Um... yikes. It's obviously breaking a rule or two... but they had to break SOME
-rules, so they made a choice.
-
-When the C99 standard rolled around, it introduced alternate standard-size types.
-It also introduced macros for pulling in MIN/MAX values for your integer types.
-It's glorious! Unfortunately, many embedded compilers can't be relied upon to
-use the C99 types (Sometimes because they have weird register sizes as described
-above. Sometimes because they don't feel like it?).
-
-A goal of Unity from the beginning was to support every combination of
-microcontroller or microprocessor and C compiler. Over time, we've gotten really
-close to this. There are a few tricks that you should be aware of, though, if
-you're going to do this effectively on some of these more idiosyncratic targets.
-
-First, when setting up Unity for a new target, you're going to want to pay
-special attention to the macros for automatically detecting types
-(where available) or manually configuring them yourself. You can get information
-on both of these in Unity's documentation.
-
-What about the times where you suddenly need to deal with something odd, like a
-24-bit `int`? The simplest solution is to use the next size up. If you have a
-24-bit `int`, configure Unity to use 32-bit integers. If you have a 12-bit
-`int`, configure Unity to use 16 bits. There are two ways this is going to
-affect you:
-
-1. When Unity displays errors for you, it's going to pad the upper unused bits
-with zeros.
-2. You're going to have to be careful of assertions that perform signed
-operations, particularly `TEST_ASSERT_INT_WITHIN`.Such assertions might wrap
-your `int` in the wrong place, and you could experience false failures. You can
-always back down to a simple `TEST_ASSERT` and do the operations yourself.
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/docs/UnityConfigurationGuide.md b/test/vendor/ceedling/docs/UnityConfigurationGuide.md
deleted file mode 100644
index dace20c54..000000000
--- a/test/vendor/ceedling/docs/UnityConfigurationGuide.md
+++ /dev/null
@@ -1,433 +0,0 @@
-īģŋ# Unity Configuration Guide
-
-## C Standards, Compilers and Microcontrollers
-
-The embedded software world contains its challenges. Compilers support different
-revisions of the C Standard. They ignore requirements in places, sometimes to
-make the language more usable in some special regard. Sometimes it's to simplify
-their support. Sometimes it's due to specific quirks of the microcontroller they
-are targeting. Simulators add another dimension to this menagerie.
-
-Unity is designed to run on almost anything that is targeted by a C compiler. It
-would be awesome if this could be done with zero configuration. While there are
-some targets that come close to this dream, it is sadly not universal. It is
-likely that you are going to need at least a couple of the configuration options
-described in this document.
-
-All of Unity's configuration options are `#defines`. Most of these are simple
-definitions. A couple are macros with arguments. They live inside the
-unity_internals.h header file. We don't necessarily recommend opening that file
-unless you really need to. That file is proof that a cross-platform library is
-challenging to build. From a more positive perspective, it is also proof that a
-great deal of complexity can be centralized primarily to one place to
-provide a more consistent and simple experience elsewhere.
-
-
-### Using These Options
-
-It doesn't matter if you're using a target-specific compiler and a simulator or
-a native compiler. In either case, you've got a couple choices for configuring
-these options:
-
-1. Because these options are specified via C defines, you can pass most of these
-options to your compiler through command line compiler flags. Even if you're
-using an embedded target that forces you to use their overbearing IDE for all
-configuration, there will be a place somewhere in your project to configure
-defines for your compiler.
-2. You can create a custom `unity_config.h` configuration file (present in your
-toolchain's search paths). In this file, you will list definitions and macros
-specific to your target. All you must do is define `UNITY_INCLUDE_CONFIG_H` and
-Unity will rely on `unity_config.h` for any further definitions it may need.
-
-
-## The Options
-
-### Integer Types
-
-If you've been a C developer for long, you probably already know that C's
-concept of an integer varies from target to target. The C Standard has rules
-about the `int` matching the register size of the target microprocessor. It has
-rules about the `int` and how its size relates to other integer types. An `int`
-on one target might be 16 bits while on another target it might be 64. There are
-more specific types in compilers compliant with C99 or later, but that's
-certainly not every compiler you are likely to encounter. Therefore, Unity has a
-number of features for helping to adjust itself to match your required integer
-sizes. It starts off by trying to do it automatically.
-
-
-##### `UNITY_EXCLUDE_STDINT_H`
-
-The first thing that Unity does to guess your types is check `stdint.h`.
-This file includes defines like `UINT_MAX` that Unity can use to
-learn a lot about your system. It's possible you don't want it to do this
-(um. why not?) or (more likely) it's possible that your system doesn't
-support `stdint.h`. If that's the case, you're going to want to define this.
-That way, Unity will know to skip the inclusion of this file and you won't
-be left with a compiler error.
-
-_Example:_
-        #define UNITY_EXCLUDE_STDINT_H
-
-
-##### `UNITY_EXCLUDE_LIMITS_H`
-
-The second attempt to guess your types is to check `limits.h`. Some compilers
-that don't support `stdint.h` could include `limits.h` instead. If you don't
-want Unity to check this file either, define this to make it skip the inclusion.
-
-_Example:_
-        #define UNITY_EXCLUDE_LIMITS_H
-
-
-If you've disabled both of the automatic options above, you're going to have to
-do the configuration yourself. Don't worry. Even this isn't too bad... there are
-just a handful of defines that you are going to specify if you don't like the
-defaults.
-
-
-##### `UNITY_INT_WIDTH`
-
-Define this to be the number of bits an `int` takes up on your system. The
-default, if not autodetected, is 32 bits.
-
-_Example:_
-        #define UNITY_INT_WIDTH 16
-
-
-##### `UNITY_LONG_WIDTH`
-
-Define this to be the number of bits a `long` takes up on your system. The
-default, if not autodetected, is 32 bits. This is used to figure out what kind
-of 64-bit support your system can handle. Does it need to specify a `long` or a
-`long long` to get a 64-bit value. On 16-bit systems, this option is going to be
-ignored.
-
-_Example:_
-        #define UNITY_LONG_WIDTH 16
-
-
-##### `UNITY_POINTER_WIDTH`
-
-Define this to be the number of bits a pointer takes up on your system. The
-default, if not autodetected, is 32-bits. If you're getting ugly compiler
-warnings about casting from pointers, this is the one to look at.
-
-_Example:_
-        #define UNITY_POINTER_WIDTH 64
-
-
-##### `UNITY_SUPPORT_64`
-
-Unity will automatically include 64-bit support if it auto-detects it, or if
-your `int`, `long`, or pointer widths are greater than 32-bits. Define this to
-enable 64-bit support if none of the other options already did it for you. There
-can be a significant size and speed impact to enabling 64-bit support on small
-targets, so don't define it if you don't need it.
-
-_Example:_
-        #define UNITY_SUPPORT_64
-
-
-### Floating Point Types
-
-In the embedded world, it's not uncommon for targets to have no support for
-floating point operations at all or to have support that is limited to only
-single precision. We are able to guess integer sizes on the fly because integers
-are always available in at least one size. Floating point, on the other hand, is
-sometimes not available at all. Trying to include `float.h` on these platforms
-would result in an error. This leaves manual configuration as the only option.
-
-
-##### `UNITY_INCLUDE_FLOAT`
-
-##### `UNITY_EXCLUDE_FLOAT`
-
-##### `UNITY_INCLUDE_DOUBLE`
-
-##### `UNITY_EXCLUDE_DOUBLE`
-
-By default, Unity guesses that you will want single precision floating point
-support, but not double precision. It's easy to change either of these using the
-include and exclude options here. You may include neither, either, or both, as
-suits your needs. For features that are enabled, the following floating point
-options also become available.
-
-_Example:_
-
-        //what manner of strange processor is this?
-        #define UNITY_EXCLUDE_FLOAT
-        #define UNITY_INCLUDE_DOUBLE
-
-
-##### `UNITY_EXCLUDE_FLOAT_PRINT`
-
-Unity aims for as small of a footprint as possible and avoids most standard
-library calls (some embedded platforms don’t have a standard library!). Because
-of this, its routines for printing integer values are minimalist and hand-coded.
-Therefore, the display of floating point values during a failure are optional.
-By default, Unity will print the actual results of floating point assertion
-failure (e.g. ”Expected 4.56 Was 4.68”). To not include this extra support, you
-can use this define to instead respond to a failed assertion with a message like
-”Values Not Within Delta”. If you would like verbose failure messages for floating
-point assertions, use these options to give more explicit failure messages.
-
-_Example:_
-        #define UNITY_EXCLUDE_FLOAT_PRINT
-
-
-##### `UNITY_FLOAT_TYPE`
-
-If enabled, Unity assumes you want your `FLOAT` asserts to compare standard C
-floats. If your compiler supports a specialty floating point type, you can
-always override this behavior by using this definition.
-
-_Example:_
-        #define UNITY_FLOAT_TYPE float16_t
-
-
-##### `UNITY_DOUBLE_TYPE`
-
-If enabled, Unity assumes you want your `DOUBLE` asserts to compare standard C
-doubles. If you would like to change this, you can specify something else by
-using this option. For example, defining `UNITY_DOUBLE_TYPE` to `long double`
-could enable gargantuan floating point types on your 64-bit processor instead of
-the standard `double`.
-
-_Example:_
-        #define UNITY_DOUBLE_TYPE long double
-
-
-##### `UNITY_FLOAT_PRECISION`
-
-##### `UNITY_DOUBLE_PRECISION`
-
-If you look up `UNITY_ASSERT_EQUAL_FLOAT` and `UNITY_ASSERT_EQUAL_DOUBLE` as
-documented in the big daddy Unity Assertion Guide, you will learn that they are
-not really asserting that two values are equal but rather that two values are
-"close enough" to equal. "Close enough" is controlled by these precision
-configuration options. If you are working with 32-bit floats and/or 64-bit
-doubles (the normal on most processors), you should have no need to change these
-options. They are both set to give you approximately 1 significant bit in either
-direction. The float precision is 0.00001 while the double is 10-12.
-For further details on how this works, see the appendix of the Unity Assertion
-Guide.
-
-_Example:_
-        #define UNITY_FLOAT_PRECISION 0.001f
-
-
-### Toolset Customization
-
-In addition to the options listed above, there are a number of other options
-which will come in handy to customize Unity's behavior for your specific
-toolchain. It is possible that you may not need to touch any of these... but
-certain platforms, particularly those running in simulators, may need to jump
-through extra hoops to run properly. These macros will help in those
-situations.
-
-
-##### `UNITY_OUTPUT_CHAR(a)`
-
-##### `UNITY_OUTPUT_FLUSH()`
-
-##### `UNITY_OUTPUT_START()`
-
-##### `UNITY_OUTPUT_COMPLETE()`
-
-By default, Unity prints its results to `stdout` as it runs. This works
-perfectly fine in most situations where you are using a native compiler for
-testing. It works on some simulators as well so long as they have `stdout`
-routed back to the command line. There are times, however, where the simulator
-will lack support for dumping results or you will want to route results
-elsewhere for other reasons. In these cases, you should define the
-`UNITY_OUTPUT_CHAR` macro. This macro accepts a single character at a time (as
-an `int`, since this is the parameter type of the standard C `putchar` function
-most commonly used). You may replace this with whatever function call you like.
-
-_Example:_
-Say you are forced to run your test suite on an embedded processor with no
-`stdout` option. You decide to route your test result output to a custom serial
-`RS232_putc()` function you wrote like thus:
-        #include "RS232_header.h"
-        ...
-        #define UNITY_OUTPUT_CHAR(a) RS232_putc(a)
-        #define UNITY_OUTPUT_START() RS232_config(115200,1,8,0)
-        #define UNITY_OUTPUT_FLUSH() RS232_flush()
-        #define UNITY_OUTPUT_COMPLETE() RS232_close()
-
-_Note:_
-`UNITY_OUTPUT_FLUSH()` can be set to the standard out flush function simply by
-specifying `UNITY_USE_FLUSH_STDOUT`. No other defines are required.
-
-
-##### `UNITY_WEAK_ATTRIBUTE`
-
-##### `UNITY_WEAK_PRAGMA`
-
-##### `UNITY_NO_WEAK`
-
-For some targets, Unity can make the otherwise required setUp() and tearDown()
-functions optional. This is a nice convenience for test writers since setUp and
-tearDown don’t often actually do anything. If you’re using gcc or clang, this
-option is automatically defined for you. Other compilers can also support this
-behavior, if they support a C feature called weak functions. A weak function is
-a function that is compiled into your executable unless a non-weak version of
-the same function is defined elsewhere. If a non-weak version is found, the weak
-version is ignored as if it never existed. If your compiler supports this feature,
-you can let Unity know by defining UNITY_WEAK_ATTRIBUTE or UNITY_WEAK_PRAGMA as
-the function attributes that would need to be applied to identify a function as
-weak. If your compiler lacks support for weak functions, you will always need to
-define setUp and tearDown functions (though they can be and often will be just
-empty). You can also force Unity to NOT use weak functions by defining
-UNITY_NO_WEAK. The most common options for this feature are:
-
-_Example:_
-        #define UNITY_WEAK_ATTRIBUTE weak
-        #define UNITY_WEAK_ATTRIBUTE __attribute__((weak))
-        #define UNITY_WEAK_PRAGMA
-        #define UNITY_NO_WEAK
-
-
-##### `UNITY_PTR_ATTRIBUTE`
-
-Some compilers require a custom attribute to be assigned to pointers, like
-`near` or `far`. In these cases, you can give Unity a safe default for these by
-defining this option with the attribute you would like.
-
-_Example:_
-        #define UNITY_PTR_ATTRIBUTE __attribute__((far))
-        #define UNITY_PTR_ATTRIBUTE near
-
-
-##### `UNITY_PRINT_EOL`
-
-By default, Unity outputs \n at the end of each line of output. This is easy
-to parse by the scripts, by Ceedling, etc, but it might not be ideal for YOUR
-system. Feel free to override this and to make it whatever you wish.
-
-_Example:_
-        #define UNITY_PRINT_EOL { UNITY_OUTPUT_CHAR('\r'); UNITY_OUTPUT_CHAR('\n') }
-
-
-
-##### `UNITY_EXCLUDE_DETAILS`
-
-This is an option for if you absolutely must squeeze every byte of memory out of
-your system. Unity stores a set of internal scratchpads which are used to pass
-extra detail information around. It's used by systems like CMock in order to
-report which function or argument flagged an error. If you're not using CMock and
-you're not using these details for other things, then you can exclude them.
-
-_Example:_
-        #define UNITY_EXCLUDE_DETAILS
-
-
-
-##### `UNITY_EXCLUDE_SETJMP`
-
-If your embedded system doesn't support the standard library setjmp, you can
-exclude Unity's reliance on this by using this define. This dropped dependence
-comes at a price, though. You will be unable to use custom helper functions for
-your tests, and you will be unable to use tools like CMock. Very likely, if your
-compiler doesn't support setjmp, you wouldn't have had the memory space for those
-things anyway, though... so this option exists for those situations.
-
-_Example:_
-        #define UNITY_EXCLUDE_SETJMP
-
-##### `UNITY_OUTPUT_COLOR`
-
-If you want to add color using ANSI escape codes you can use this define.
-t
-_Example:_
-        #define UNITY_OUTPUT_COLOR
-
-
-
-## Getting Into The Guts
-
-There will be cases where the options above aren't quite going to get everything
-perfect. They are likely sufficient for any situation where you are compiling
-and executing your tests with a native toolchain (e.g. clang on Mac). These
-options may even get you through the majority of cases encountered in working
-with a target simulator run from your local command line. But especially if you
-must run your test suite on your target hardware, your Unity configuration will
-require special help. This special help will usually reside in one of two
-places: the `main()` function or the `RUN_TEST` macro. Let's look at how these
-work.
-
-
-##### `main()`
-
-Each test module is compiled and run on its own, separate from the other test
-files in your project. Each test file, therefore, has a `main` function. This
-`main` function will need to contain whatever code is necessary to initialize
-your system to a workable state. This is particularly true for situations where
-you must set up a memory map or initialize a communication channel for the
-output of your test results.
-
-A simple main function looks something like this:
-
-        int main(void) {
-            UNITY_BEGIN();
-            RUN_TEST(test_TheFirst);
-            RUN_TEST(test_TheSecond);
-            RUN_TEST(test_TheThird);
-            return UNITY_END();
-        }
-
-You can see that our main function doesn't bother taking any arguments. For our
-most barebones case, we'll never have arguments because we just run all the
-tests each time. Instead, we start by calling `UNITY_BEGIN`. We run each test
-(in whatever order we wish). Finally, we call `UNITY_END`, returning its return
-value (which is the total number of failures).
-
-It should be easy to see that you can add code before any test cases are run or
-after all the test cases have completed. This allows you to do any needed
-system-wide setup or teardown that might be required for your special
-circumstances.
-
-
-##### `RUN_TEST`
-
-The `RUN_TEST` macro is called with each test case function. Its job is to
-perform whatever setup and teardown is necessary for executing a single test
-case function. This includes catching failures, calling the test module's
-`setUp()` and `tearDown()` functions, and calling `UnityConcludeTest()`. If
-using CMock or test coverage, there will be additional stubs in use here. A
-simple minimalist RUN_TEST macro looks something like this:
-
-        #define RUN_TEST(testfunc) \
-            UNITY_NEW_TEST(#testfunc) \
-            if (TEST_PROTECT()) { \
-                setUp(); \
-                testfunc(); \
-            } \
-            if (TEST_PROTECT() && (!TEST_IS_IGNORED)) \
-                tearDown(); \
-            UnityConcludeTest();
-
-So that's quite a macro, huh? It gives you a glimpse of what kind of stuff Unity
-has to deal with for every single test case. For each test case, we declare that
-it is a new test. Then we run `setUp` and our test function. These are run
-within a `TEST_PROTECT` block, the function of which is to handle failures that
-occur during the test. Then, assuming our test is still running and hasn't been
-ignored, we run `tearDown`. No matter what, our last step is to conclude this
-test before moving on to the next.
-
-Let's say you need to add a call to `fsync` to force all of your output data to
-flush to a file after each test. You could easily insert this after your
-`UnityConcludeTest` call. Maybe you want to write an xml tag before and after
-each result set. Again, you could do this by adding lines to this macro. Updates
-to this macro are for the occasions when you need an action before or after
-every single test case throughout your entire suite of tests.
-
-
-## Happy Porting
-
-The defines and macros in this guide should help you port Unity to just about
-any C target we can imagine. If you run into a snag or two, don't be afraid of
-asking for help on the forums. We love a good challenge!
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/docs/UnityGettingStartedGuide.md b/test/vendor/ceedling/docs/UnityGettingStartedGuide.md
deleted file mode 100644
index 5e4427ce9..000000000
--- a/test/vendor/ceedling/docs/UnityGettingStartedGuide.md
+++ /dev/null
@@ -1,192 +0,0 @@
-# Unity - Getting Started
-
-## Welcome
-
-Congratulations. You're now the proud owner of your very own pile of bits! What
-are you going to do with all these ones and zeros? This document should be able
-to help you decide just that.
-
-Unity is a unit test framework. The goal has been to keep it small and
-functional. The core Unity test framework is three files: a single C file and a
-couple header files. These team up to provide functions and macros to make
-testing easier.
-
-Unity was designed to be cross-platform. It works hard to stick with C standards
-while still providing support for the many embedded C compilers that bend the
-rules. Unity has been used with many compilers, including GCC, IAR, Clang,
-Green Hills, Microchip, and MS Visual Studio. It's not much work to get it to
-work with a new target.
-
-
-### Overview of the Documents
-
-#### Unity Assertions reference
-
-This document will guide you through all the assertion options provided by
-Unity. This is going to be your unit testing bread and butter. You'll spend more
-time with assertions than any other part of Unity.
-
-
-#### Unity Assertions Cheat Sheet
-
-This document contains an abridged summary of the assertions described in the
-previous document. It's perfect for printing and referencing while you
-familiarize yourself with Unity's options.
-
-
-#### Unity Configuration Guide
-
-This document is the one to reference when you are going to use Unity with a new
-target or compiler. It'll guide you through the configuration options and will
-help you customize your testing experience to meet your needs.
-
-
-#### Unity Helper Scripts
-
-This document describes the helper scripts that are available for simplifying
-your testing workflow. It describes the collection of optional Ruby scripts
-included in the auto directory of your Unity installation. Neither Ruby nor
-these scripts are necessary for using Unity. They are provided as a convenience
-for those who wish to use them.
-
-
-#### Unity License
-
-What's an open source project without a license file? This brief document
-describes the terms you're agreeing to when you use this software. Basically, we
-want it to be useful to you in whatever context you want to use it, but please
-don't blame us if you run into problems.
-
-
-### Overview of the Folders
-
-If you have obtained Unity through Github or something similar, you might be
-surprised by just how much stuff you suddenly have staring you in the face.
-Don't worry, Unity itself is very small. The rest of it is just there to make
-your life easier. You can ignore it or use it at your convenience. Here's an
-overview of everything in the project.
-
-- `src` - This is the code you care about! This folder contains a C file and two
-header files. These three files _are_ Unity.
-- `docs` - You're reading this document, so it's possible you have found your way
-into this folder already. This is where all the handy documentation can be
-found.
-- `examples` - This contains a few examples of using Unity.
-- `extras` - These are optional add ons to Unity that are not part of the core
-project. If you've reached us through James Grenning's book, you're going to
-want to look here.
-- `test` - This is how Unity and its scripts are all tested. If you're just using
-Unity, you'll likely never need to go in here. If you are the lucky team member
-who gets to port Unity to a new toolchain, this is a good place to verify
-everything is configured properly.
-- `auto` - Here you will find helpful Ruby scripts for simplifying your test
-workflow. They are purely optional and are not required to make use of Unity.
-
-
-## How to Create A Test File
-
-Test files are C files. Most often you will create a single test file for each C
-module that you want to test. The test file should include unity.h and the
-header for your C module to be tested.
-
-Next, a test file will include a `setUp()` and `tearDown()` function. The setUp
-function can contain anything you would like to run before each test. The
-tearDown function can contain anything you would like to run after each test.
-Both functions accept no arguments and return nothing. You may leave either or
-both of these blank if you have no need for them. If you're using a compiler
-that is configured to make these functions optional, you may leave them off
-completely. Not sure? Give it a try. If you compiler complains that it can't
-find setUp or tearDown when it links, you'll know you need to at least include
-an empty function for these.
-
-The majority of the file will be a series of test functions. Test functions
-follow the convention of starting with the word "test_" or "spec_". You don't HAVE
-to name them this way, but it makes it clear what functions are tests for other
-developers.  Also, the automated scripts that come with Unity or Ceedling will default
-to looking for test functions to be prefixed this way. Test functions take no arguments 
-and return nothing. All test accounting is handled internally in Unity.
-
-Finally, at the bottom of your test file, you will write a `main()` function.
-This function will call `UNITY_BEGIN()`, then `RUN_TEST` for each test, and
-finally `UNITY_END()`.This is what will actually trigger each of those test
-functions to run, so it is important that each function gets its own `RUN_TEST`
-call.
-
-Remembering to add each test to the main function can get to be tedious. If you
-enjoy using helper scripts in your build process, you might consider making use
-of our handy generate_test_runner.rb script. This will create the main function
-and all the calls for you, assuming that you have followed the suggested naming
-conventions. In this case, there is no need for you to include the main function
-in your test file at all.
-
-When you're done, your test file will look something like this:
-
-```C
-#include "unity.h"
-#include "file_to_test.h"
-
-void setUp(void) {
-    // set stuff up here
-}
-
-void tearDown(void) {
-    // clean stuff up here
-}
-
-void test_function_should_doBlahAndBlah(void) {
-    //test stuff
-}
-
-void test_function_should_doAlsoDoBlah(void) {
-    //more test stuff
-}
-
-int main(void) {
-    UNITY_BEGIN();
-    RUN_TEST(test_function_should_doBlahAndBlah);
-    RUN_TEST(test_function_should_doAlsoDoBlah);
-    return UNITY_END();
-}
-```
-
-It's possible that you will need more customization than this, eventually.
-For that sort of thing, you're going to want to look at the configuration guide.
-This should be enough to get you going, though.
-
-
-## How to Build and Run A Test File
-
-This is the single biggest challenge to picking up a new unit testing framework,
-at least in a language like C or C++. These languages are REALLY good at getting
-you "close to the metal" (why is the phrase metal? Wouldn't it be more accurate
-to say "close to the silicon"?). While this feature is usually a good thing, it
-can make testing more challenging.
-
-You have two really good options for toolchains. Depending on where you're
-coming from, it might surprise you that neither of these options is running the
-unit tests on your hardware.
-There are many reasons for this, but here's a short version:
-- On hardware, you have too many constraints (processing power, memory, etc),
-- On hardware, you don't have complete control over all registers,
-- On hardware, unit testing is more challenging,
-- Unit testing isn't System testing. Keep them separate.
-
-Instead of running your tests on your actual hardware, most developers choose to
-develop them as native applications (using gcc or MSVC for example) or as
-applications running on a simulator. Either is a good option. Native apps have
-the advantages of being faster and easier to set up. Simulator apps have the
-advantage of working with the same compiler as your target application. The
-options for configuring these are discussed in the configuration guide.
-
-To get either to work, you might need to make a few changes to the file
-containing your register set (discussed later).
-
-In either case, a test is built by linking unity, the test file, and the C
-file(s) being tested. These files create an executable which can be run as the
-test set for that module. Then, this process is repeated for the next test file.
-This flexibility of separating tests into individual executables allows us to
-much more thoroughly unit test our system and it keeps all the test code out of
-our final release!
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/docs/UnityHelperScriptsGuide.md b/test/vendor/ceedling/docs/UnityHelperScriptsGuide.md
deleted file mode 100644
index 12d68d30e..000000000
--- a/test/vendor/ceedling/docs/UnityHelperScriptsGuide.md
+++ /dev/null
@@ -1,260 +0,0 @@
-# Unity Helper Scripts
-
-## With a Little Help From Our Friends
-
-Sometimes what it takes to be a really efficient C programmer is a little non-C.
-The Unity project includes a couple of Ruby scripts for making your life just a tad
-easier. They are completely optional. If you choose to use them, you'll need a
-copy of Ruby, of course. Just install whatever the latest version is, and it is
-likely to work. You can find Ruby at [ruby-lang.org](https://ruby-labg.org/).
-
-
-### `generate_test_runner.rb`
-
-Are you tired of creating your own `main` function in your test file? Do you
-keep forgetting to add a `RUN_TEST` call when you add a new test case to your
-suite? Do you want to use CMock or other fancy add-ons but don't want to figure
-out how to create your own `RUN_TEST` macro?
-
-Well then we have the perfect script for you!
-
-The `generate_test_runner` script processes a given test file and automatically
-creates a separate test runner file that includes ?main?to execute the test
-cases within the scanned test file. All you do then is add the generated runner
-to your list of files to be compiled and linked, and presto you're done!
-
-This script searches your test file for void function signatures having a
-function name beginning with "test" or "spec". It treats each of these
-functions as a test case and builds up a test suite of them. For example, the
-following includes three test cases:
-
-```C
-void testVerifyThatUnityIsAwesomeAndWillMakeYourLifeEasier(void)
-{
-  ASSERT_TRUE(1);
-}
-void test_FunctionName_should_WorkProperlyAndReturn8(void) {
-  ASSERT_EQUAL_INT(8, FunctionName());
-}
-void spec_Function_should_DoWhatItIsSupposedToDo(void) {
-  ASSERT_NOT_NULL(Function(5));
-}
-```
-
-You can run this script a couple of ways. The first is from the command line:
-
-```Shell
-ruby generate_test_runner.rb TestFile.c NameOfRunner.c
-```
-
-Alternatively, if you include only the test file parameter, the script will copy
-the name of the test file and automatically append "_Runner" to the name of the
-generated file. The example immediately below will create TestFile_Runner.c.
-
-```Shell
-ruby generate_test_runner.rb TestFile.c
-```
-
-You can also add a [YAML](http://www.yaml.org/) file to configure extra options.
-Conveniently, this YAML file is of the same format as that used by Unity and
-CMock. So if you are using YAML files already, you can simply pass the very same
-file into the generator script.
-
-```Shell
-ruby generate_test_runner.rb TestFile.c my_config.yml
-```
-
-The contents of the YAML file `my_config.yml` could look something like the
-example below. If you're wondering what some of these options do, you're going
-to love the next section of this document.
-
-```YAML
-:unity:
-  :includes:
-    - stdio.h
-    - microdefs.h
-  :cexception: 1
-  :suit_setup: "blah = malloc(1024);"
-  :suite_teardown: "free(blah);"
-```
-
-If you would like to force your generated test runner to include one or more
-header files, you can just include those at the command line too. Just make sure
-these are _after_ the YAML file, if you are using one:
-
-```Shell
-ruby generate_test_runner.rb TestFile.c my_config.yml extras.h
-```
-
-Another option, particularly if you are already using Ruby to orchestrate your
-builds - or more likely the Ruby-based build tool Rake - is requiring this
-script directly. Anything that you would have specified in a YAML file can be
-passed to the script as part of a hash. Let's push the exact same requirement
-set as we did above but this time through Ruby code directly:
-
-```Ruby
-require "generate_test_runner.rb"
-options = {
-  :includes => ["stdio.h", "microdefs.h"],
-  :cexception => 1,
-  :suite_setup => "blah = malloc(1024);",
-  :suite_teardown => "free(blah);"
-}
-UnityTestRunnerGenerator.new.run(testfile, runner_name, options)
-```
-
-If you have multiple files to generate in a build script (such as a Rakefile),
-you might want to instantiate a generator object with your options and call it
-to generate each runner afterwards. Like thus:
-
-```Ruby
-gen = UnityTestRunnerGenerator.new(options)
-test_files.each do |f|
-  gen.run(f, File.basename(f,'.c')+"Runner.c"
-end
-```
-
-#### Options accepted by generate_test_runner.rb:
-
-The following options are available when executing `generate_test_runner`. You
-may pass these as a Ruby hash directly or specify them in a YAML file, both of
-which are described above. In the `examples` directory, Example 3's Rakefile
-demonstrates using a Ruby hash.
-
-
-##### `:includes`
-
-This option specifies an array of file names to be `#include`'d at the top of
-your runner C file. You might use it to reference custom types or anything else
-universally needed in your generated runners.
-
-
-##### `:suite_setup`
-
-Define this option with C code to be executed _before any_ test cases are run.
-
-Alternatively, if your C compiler supports weak symbols, you can leave this
-option unset and instead provide a `void suiteSetUp(void)` function in your test
-suite.  The linker will look for this symbol and fall back to a Unity-provided
-stub if it is not found.
-
-
-##### `:suite_teardown`
-
-Define this option with C code to be executed _after all_ test cases have
-finished.  An integer variable `num_failures` is available for diagnostics.
-The code should end with a `return` statement; the value returned will become
-the exit code of `main`.  You can normally just return `num_failures`.
-
-Alternatively, if your C compiler supports weak symbols, you can leave this
-option unset and instead provide a `int suiteTearDown(int num_failures)`
-function in your test suite.  The linker will look for this symbol and fall
-back to a Unity-provided stub if it is not found.
-
-
-##### `:enforce_strict_ordering`
-
-This option should be defined if you have the strict order feature enabled in
-CMock (see CMock documentation). This generates extra variables required for
-everything to run smoothly. If you provide the same YAML to the generator as
-used in CMock's configuration, you've already configured the generator properly.
-
-##### `:mock_prefix` and `:mock_suffix`
-
-Unity automatically generates calls to Init, Verify and Destroy for every file
-included in the main test file that starts with the given mock prefix and ends
-with the given mock suffix, file extension not included. By default, Unity
-assumes a `Mock` prefix and no suffix.
-
-##### `:plugins`
-
-This option specifies an array of plugins to be used (of course, the array can
-contain only a single plugin). This is your opportunity to enable support for
-CException support, which will add a check for unhandled exceptions in each
-test, reporting a failure if one is detected. To enable this feature using Ruby:
-
-```Ruby
-:plugins => [ :cexception ]
-```
-
-Or as a yaml file:
-
-```YAML
-:plugins:
-  -:cexception
-```
-
-If you are using CMock, it is very likely that you are already passing an array
-of plugins to CMock. You can just use the same array here. This script will just
-ignore the plugins that don't require additional support.
-
-
-### `unity_test_summary.rb`
-
-A Unity test file contains one or more test case functions. Each test case can
-pass, fail, or be ignored. Each test file is run individually producing results
-for its collection of test cases. A given project will almost certainly be
-composed of multiple test files. Therefore, the suite of tests is comprised of
-one or more test cases spread across one or more test files. This script
-aggregates individual test file results to generate a summary of all executed
-test cases. The output includes how many tests were run, how many were ignored,
-and how many failed. In addition, the output includes a listing of which
-specific tests were ignored and failed. A good example of the breadth and
-details of these results can be found in the `examples` directory. Intentionally
-ignored and failing tests in this project generate corresponding entries in the
-summary report.
-
-If you're interested in other (prettier?) output formats, check into the
-Ceedling build tool project (ceedling.sourceforge.net) that works with Unity and
-CMock and supports xunit-style xml as well as other goodies.
-
-This script assumes the existence of files ending with the extensions
-`.testpass` and `.testfail`.The contents of these files includes the test
-results summary corresponding to each test file executed with the extension set
-according to the presence or absence of failures for that test file. The script
-searches a specified path for these files, opens each one it finds, parses the
-results, and aggregates and prints a summary. Calling it from the command line
-looks like this:
-
-```Shell
-ruby unity_test_summary.rb build/test/
-```
-
-You can optionally specify a root path as well. This is really helpful when you
-are using relative paths in your tools' setup, but you want to pull the summary
-into an IDE like Eclipse for clickable shortcuts.
-
-```Shell
-ruby unity_test_summary.rb build/test/ ~/projects/myproject/
-```
-
-Or, if you're more of a Windows sort of person:
-
-```Shell
-ruby unity_test_summary.rb build\teat\ C:\projects\myproject\
-```
-
-When configured correctly, you'll see a final summary, like so:
-
-```Shell
---------------------------
-UNITY IGNORED TEST SUMMARY
---------------------------
-blah.c:22:test_sandwiches_should_HaveBreadOnTwoSides:IGNORE
-
--------------------------
-UNITY FAILED TEST SUMMARY
--------------------------
-blah.c:87:test_sandwiches_should_HaveCondiments:FAIL:Expected 1 was 0
-meh.c:38:test_soda_should_BeCalledPop:FAIL:Expected "pop" was "coke"
-
---------------------------
-OVERALL UNITY TEST SUMMARY
---------------------------
-45 TOTAL TESTS 2 TOTAL FAILURES 1 IGNORED
-```
-
-How convenient is that?
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/lib/ceedling.rb b/test/vendor/ceedling/lib/ceedling.rb
deleted file mode 100644
index 7f3400236..000000000
--- a/test/vendor/ceedling/lib/ceedling.rb
+++ /dev/null
@@ -1,99 +0,0 @@
-##
-# This module defines the interface for interacting with and loading a project
-# with Ceedling.
-module Ceedling
-  ##
-  # Returns the location where the gem is installed.
-  # === Return
-  # _String_ - The location where the gem lives.
-  def self.location
-    File.join( File.dirname(__FILE__), '..')
-  end
-
-  ##
-  # Return the path to the "built-in" plugins.
-  # === Return
-  # _String_ - The path where the default plugins live.
-  def self.load_path
-    File.join( self.location, 'plugins')
-  end
-
-  ##
-  # Return the path to the Ceedling Rakefile
-  # === Return
-  # _String_
-  def self.rakefile
-    File.join( self.location, 'lib', 'ceedling', 'rakefile.rb' )
-  end
-
-  ##
-  # This method selects the project file that Ceedling will use by setting the
-  # CEEDLING_MAIN_PROJECT_FILE environment variable before loading the ceedling
-  # rakefile. A path supplied as an argument to this method will override the
-  # current value of the environment variable. If no path is supplied as an
-  # argument then the existing value of the environment variable is used. If
-  # the environment variable has not been set and no argument has been supplied
-  # then a default path of './project.yml' will be used.
-  #
-  # === Arguments
-  # +options+ _Hash_::
-  #   A hash containing the options for ceedling. Currently the following
-  #   options are supported:
-  #   * +config+ - The path to the project YAML configuration file.
-  #   * +root+ - The root of the project directory.
-  #   * +prefix+ - A prefix to prepend to plugin names in order to determine the
-  #     corresponding gem name.
-  #   * +plugins+ - The list of ceedling plugins to load
-  def self.load_project(options = {})
-    # Make sure our path to the yaml file is setup
-    if options.has_key? :config
-      ENV['CEEDLING_MAIN_PROJECT_FILE'] = options[:config]
-    elsif ENV['CEEDLING_MAIN_PROJECT_FILE'].nil?
-      ENV['CEEDLING_MAIN_PROJECT_FILE'] = './project.yml'
-    end
-
-    # Register the plugins
-    if options.has_key? :plugins
-      options[:plugins].each do |plugin|
-        register_plugin( plugin, options[:prefix] )
-      end
-    end
-
-    # Define the root of the project if specified
-    Object.const_set('PROJECT_ROOT', options[:root]) if options.has_key? :root
-
-    # Load ceedling
-    load "#{self.rakefile}"
-  end
-
-  ##
-  # Register a plugin for ceedling to use when a project is loaded. This method
-  # *must* be called prior to calling the _load_project_ method.
-  #
-  # This method is intended to be used for loading plugins distributed via the
-  # RubyGems mechanism. As such, the following gem structure is assumed for
-  # plugins.
-  #
-  # * The gem name must be prefixed with 'ceedling-' followed by the plugin
-  #   name (ex. 'ceedling-bullseye')
-  #
-  # * The contents of the plugin must be isntalled into a subdirectory of
-  #   the gem with the same name as the plugin (ex. 'bullseye/')
-  #
-  # === Arguments
-  # +name+ _String_:: The name of the plugin to load.
-  # +prefix+ _String_::
-  #   (optional, default = nil) The prefix to use for the full gem name.
-  def self.register_plugin(name, prefix=nil)
-    # Figure out the full name of the gem and location
-    prefix   ||= 'ceedling-'
-    gem_name   = prefix + name
-    gem_dir    = Gem::Specification.find_by_name(gem_name).gem_dir()
-
-    # Register the plugin with Ceedling
-    require 'ceedling/defaults'
-    DEFAULT_CEEDLING_CONFIG[:plugins][:enabled]    << name
-    DEFAULT_CEEDLING_CONFIG[:plugins][:load_paths] << gem_dir
-  end
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb b/test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
deleted file mode 100644
index b7d57f8f4..000000000
--- a/test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
+++ /dev/null
@@ -1,39 +0,0 @@
-require 'ceedling/constants'
-
-##
-# Utilities for raiser and reporting errors during building.
-class BuildInvokerUtils
-
-  constructor :configurator, :streaminator
- 
-  ##
-  # Processes exceptions and tries to display a useful message for the user.
-  #
-  # ==== Attriboops...utes
-  #
-  # * _exception_:  The exception given by a rescue statement.
-  # * _context_:    A symbol representing where in the build the exception
-  # occurs. 
-  # * _test_build_: A bool to signify if the exception occurred while building
-  # from test or source.
-  #
-  def process_exception(exception, context, test_build=true)
-    if (exception.message =~ /Don't know how to build task '(.+)'/i)
-      error_header  = "ERROR: Rake could not find file referenced in source"
-      error_header += " or test" if (test_build) 
-      error_header += ": '#{$1}'. Possible stale dependency."
-      
-      @streaminator.stderr_puts( error_header )
-
-      if (@configurator.project_use_deep_dependencies)
-        help_message = "Try fixing #include statements or adding missing file. Then run '#{REFRESH_TASK_ROOT}#{context.to_s}' task and try again."      
-        @streaminator.stderr_puts( help_message )
-      end
-      
-      raise ''
-    else
-      raise exception
-    end
-  end
-  
-end
diff --git a/test/vendor/ceedling/lib/ceedling/cacheinator.rb b/test/vendor/ceedling/lib/ceedling/cacheinator.rb
deleted file mode 100644
index 519a4aab4..000000000
--- a/test/vendor/ceedling/lib/ceedling/cacheinator.rb
+++ /dev/null
@@ -1,47 +0,0 @@
-
-class Cacheinator
-
-  constructor :cacheinator_helper, :file_path_utils, :file_wrapper, :yaml_wrapper
-  
-  def cache_test_config(hash)
-    @yaml_wrapper.dump( @file_path_utils.form_test_build_cache_path( INPUT_CONFIGURATION_CACHE_FILE), hash )
-  end
-
-  def cache_release_config(hash)
-    @yaml_wrapper.dump( @file_path_utils.form_release_build_cache_path( INPUT_CONFIGURATION_CACHE_FILE ), hash )
-  end
-
-  
-  def diff_cached_test_file( filepath )
-    cached_filepath = @file_path_utils.form_test_build_cache_path( filepath )
-  
-    if (@file_wrapper.exist?( cached_filepath ) and (!@file_wrapper.compare( filepath, cached_filepath )))
-      @file_wrapper.cp(filepath, cached_filepath, {:preserve => false})
-      return filepath
-    elsif (!@file_wrapper.exist?( cached_filepath ))
-      @file_wrapper.cp(filepath, cached_filepath, {:preserve => false}) 
-      return filepath
-    end
-
-    return cached_filepath
-  end
-
-  def diff_cached_test_config?(hash)
-    cached_filepath = @file_path_utils.form_test_build_cache_path(INPUT_CONFIGURATION_CACHE_FILE)
-
-    return @cacheinator_helper.diff_cached_config?( cached_filepath, hash )
-  end
-
-  def diff_cached_test_defines?(files)
-    cached_filepath = @file_path_utils.form_test_build_cache_path(DEFINES_DEPENDENCY_CACHE_FILE)
-
-    return @cacheinator_helper.diff_cached_defines?( cached_filepath, files )
-  end
-
-  def diff_cached_release_config?(hash)
-    cached_filepath = @file_path_utils.form_release_build_cache_path(INPUT_CONFIGURATION_CACHE_FILE)
-
-    return @cacheinator_helper.diff_cached_config?( cached_filepath, hash )
-  end
-  
-end
diff --git a/test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb b/test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
deleted file mode 100644
index 2a161854b..000000000
--- a/test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
+++ /dev/null
@@ -1,31 +0,0 @@
-
-class CacheinatorHelper
-
-  constructor :file_wrapper, :yaml_wrapper
-  
-  def diff_cached_config?(cached_filepath, hash)
-    return true if ( not @file_wrapper.exist?(cached_filepath) )
-    return true if ( (@file_wrapper.exist?(cached_filepath)) and (!(@yaml_wrapper.load(cached_filepath) == hash)) )
-    return false
-  end
-
-  def diff_cached_defines?(cached_filepath, files)
-    current_defines = COLLECTION_DEFINES_TEST_AND_VENDOR.reject(&:empty?)
-
-    current_dependency = Hash[files.collect { |source| [source, current_defines.dup] }]
-    if not @file_wrapper.exist?(cached_filepath)
-      @yaml_wrapper.dump(cached_filepath, current_dependency)
-      return false
-    end
-
-    dependencies = @yaml_wrapper.load(cached_filepath)
-    if dependencies.values_at(*current_dependency.keys) != current_dependency.values
-      dependencies.merge!(current_dependency)
-      @yaml_wrapper.dump(cached_filepath, dependencies)
-      return true
-    end
-
-    return false
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/cmock_builder.rb b/test/vendor/ceedling/lib/ceedling/cmock_builder.rb
deleted file mode 100644
index 4a74aa842..000000000
--- a/test/vendor/ceedling/lib/ceedling/cmock_builder.rb
+++ /dev/null
@@ -1,15 +0,0 @@
-require 'cmock'
-
-class CmockBuilder
-  
-  attr_accessor :cmock
-  
-  def setup 
-    @cmock = nil
-  end
-  
-  def manufacture(cmock_config)
-    @cmock = CMock.new(cmock_config)
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/configurator.rb b/test/vendor/ceedling/lib/ceedling/configurator.rb
deleted file mode 100644
index b5ad8982e..000000000
--- a/test/vendor/ceedling/lib/ceedling/configurator.rb
+++ /dev/null
@@ -1,363 +0,0 @@
-require 'ceedling/defaults'
-require 'ceedling/constants'
-require 'ceedling/file_path_utils'
-require 'deep_merge'
-
-
-
-class Configurator
-
-  attr_reader :project_config_hash, :script_plugins, :rake_plugins
-  attr_accessor :project_logging, :project_debug, :project_verbosity, :sanity_checks
-
-  constructor(:configurator_setup, :configurator_builder, :configurator_plugins, :cmock_builder, :yaml_wrapper, :system_wrapper) do
-    @project_logging   = false
-    @project_debug     = false
-    @project_verbosity = Verbosity::NORMAL
-    @sanity_checks     = TestResultsSanityChecks::NORMAL
-  end
-
-  def setup
-    # special copy of cmock config to provide to cmock for construction
-    @cmock_config_hash = {}
-
-    # note: project_config_hash is an instance variable so constants and accessors created
-    # in eval() statements in build() have something of proper scope and persistence to reference
-    @project_config_hash = {}
-    @project_config_hash_backup = {}
-
-    @script_plugins = []
-    @rake_plugins   = []
-  end
-
-
-  def replace_flattened_config(config)
-    @project_config_hash.merge!(config)
-    @configurator_setup.build_constants_and_accessors(@project_config_hash, binding())
-  end
-
-
-  def store_config
-    @project_config_hash_backup = @project_config_hash.clone
-  end
-
-
-  def restore_config
-    @project_config_hash = @project_config_hash_backup
-    @configurator_setup.build_constants_and_accessors(@project_config_hash, binding())
-  end
-
-
-  def reset_defaults(config)
-    [:test_compiler,
-     :test_linker,
-     :test_fixture,
-     :test_includes_preprocessor,
-     :test_file_preprocessor,
-     :test_dependencies_generator,
-     :release_compiler,
-     :release_assembler,
-     :release_linker,
-     :release_dependencies_generator].each do |tool|
-      config[:tools].delete(tool) if (not (config[:tools][tool].nil?))
-    end
-  end
-
-
-  # The default values defined in defaults.rb (eg. DEFAULT_TOOLS_TEST) are populated
-  # into @param config
-  def populate_defaults(config)
-    new_config = DEFAULT_CEEDLING_CONFIG.deep_clone
-    new_config.deep_merge!(config)
-    config.replace(new_config)
-
-    @configurator_builder.populate_defaults( config, DEFAULT_TOOLS_TEST )
-    @configurator_builder.populate_defaults( config, DEFAULT_TOOLS_TEST_PREPROCESSORS ) if (config[:project][:use_test_preprocessor])
-    @configurator_builder.populate_defaults( config, DEFAULT_TOOLS_TEST_DEPENDENCIES )  if (config[:project][:use_deep_dependencies])
-
-    @configurator_builder.populate_defaults( config, DEFAULT_TOOLS_RELEASE )              if (config[:project][:release_build])
-    @configurator_builder.populate_defaults( config, DEFAULT_TOOLS_RELEASE_ASSEMBLER )    if (config[:project][:release_build] and config[:release_build][:use_assembly])
-    @configurator_builder.populate_defaults( config, DEFAULT_TOOLS_RELEASE_DEPENDENCIES ) if (config[:project][:release_build] and config[:project][:use_deep_dependencies])
-  end
-
-
-  def populate_unity_defaults(config)
-      unity = config[:unity] || {}
-      @runner_config = unity.merge(@runner_config || config[:test_runner] || {})
-  end
-
-  def populate_cmock_defaults(config)
-    # cmock has its own internal defaults handling, but we need to set these specific values
-    # so they're present for the build environment to access;
-    # note: these need to end up in the hash given to initialize cmock for this to be successful
-    cmock = config[:cmock] || {}
-
-    # yes, we're duplicating the default mock_prefix in cmock, but it's because we need CMOCK_MOCK_PREFIX always available in Ceedling's environment
-    cmock[:mock_prefix] = 'Mock' if (cmock[:mock_prefix].nil?)
-
-    # just because strict ordering is the way to go
-    cmock[:enforce_strict_ordering] = true                                                  if (cmock[:enforce_strict_ordering].nil?)
-
-    cmock[:mock_path] = File.join(config[:project][:build_root], TESTS_BASE_PATH, 'mocks')  if (cmock[:mock_path].nil?)
-    cmock[:verbosity] = @project_verbosity                                                  if (cmock[:verbosity].nil?)
-
-    cmock[:plugins] = []                             if (cmock[:plugins].nil?)
-    cmock[:plugins].map! { |plugin| plugin.to_sym }
-    cmock[:plugins] << (:cexception)                 if (!cmock[:plugins].include?(:cexception) and (config[:project][:use_exceptions]))
-    cmock[:plugins].uniq!
-
-    cmock[:unity_helper] = false                     if (cmock[:unity_helper].nil?)
-
-    if (cmock[:unity_helper])
-      cmock[:unity_helper] = [cmock[:unity_helper]] if cmock[:unity_helper].is_a? String
-      cmock[:includes] += cmock[:unity_helper].map{|helper| File.basename(helper) }
-      cmock[:includes].uniq!
-    end
-
-    @runner_config = cmock.merge(@runner_config || config[:test_runner] || {})
-
-    @cmock_builder.manufacture(cmock)
-  end
-
-
-  def get_runner_config
-    @runner_config
-  end
-
-
-  # grab tool names from yaml and insert into tool structures so available for error messages
-  # set up default values
-  def tools_setup(config)
-    config[:tools].each_key do |name|
-      tool = config[:tools][name]
-
-      # populate name if not given
-      tool[:name] = name.to_s if (tool[:name].nil?)
-
-      # handle inline ruby string substitution in executable
-      if (tool[:executable] =~ RUBY_STRING_REPLACEMENT_PATTERN)
-        tool[:executable].replace(@system_wrapper.module_eval(tool[:executable]))
-      end
-
-      # populate stderr redirect option
-      tool[:stderr_redirect] = StdErrRedirect::NONE if (tool[:stderr_redirect].nil?)
-
-      # populate background execution option
-      tool[:background_exec] = BackgroundExec::NONE if (tool[:background_exec].nil?)
-
-      # populate optional option to control verification of executable in search paths
-      tool[:optional] = false if (tool[:optional].nil?)
-    end
-  end
-
-
-  def tools_supplement_arguments(config)
-    tools_name_prefix = 'tools_'
-    config[:tools].each_key do |name|
-      tool = @project_config_hash[(tools_name_prefix + name.to_s).to_sym]
-
-      # smoosh in extra arguments if specified at top-level of config (useful for plugins & default gcc tools)
-      # arguments are squirted in at _end_ of list
-      top_level_tool = (tools_name_prefix + name.to_s).to_sym
-      if (not config[top_level_tool].nil?)
-         # adding and flattening is not a good idea: might over-flatten if there's array nesting in tool args
-         tool[:arguments].concat config[top_level_tool][:arguments]
-      end
-    end
-  end
-
-
-  def find_and_merge_plugins(config)
-    # plugins must be loaded before generic path evaluation & magic that happen later;
-    # perform path magic here as discrete step
-    config[:plugins][:load_paths].each do |path|
-      path.replace(@system_wrapper.module_eval(path)) if (path =~ RUBY_STRING_REPLACEMENT_PATTERN)
-      FilePathUtils::standardize(path)
-    end
-
-    config[:plugins][:load_paths] << FilePathUtils::standardize(Ceedling.load_path)
-    config[:plugins][:load_paths].uniq!
-
-    paths_hash = @configurator_plugins.add_load_paths(config)
-
-    @rake_plugins   = @configurator_plugins.find_rake_plugins(config, paths_hash)
-    @script_plugins = @configurator_plugins.find_script_plugins(config, paths_hash)
-    config_plugins  = @configurator_plugins.find_config_plugins(config, paths_hash)
-    plugin_defaults = @configurator_plugins.find_plugin_defaults(config, paths_hash)
-
-    config_plugins.each do |plugin|
-      plugin_config = @yaml_wrapper.load(plugin)
-      config.deep_merge(plugin_config)
-    end
-
-    plugin_defaults.each do |defaults|
-      @configurator_builder.populate_defaults( config, @yaml_wrapper.load(defaults) )
-    end
-
-    # special plugin setting for results printing
-    config[:plugins][:display_raw_test_results] = true if (config[:plugins][:display_raw_test_results].nil?)
-
-    paths_hash.each_pair { |name, path| config[:plugins][name] = path }
-  end
-
-
-  def merge_imports(config)
-    if config[:import]
-      until config[:import].empty?
-        path = config[:import].shift
-        path = @system_wrapper.module_eval(path) if (path =~ RUBY_STRING_REPLACEMENT_PATTERN)
-        config.deep_merge!(@yaml_wrapper.load(path))
-      end
-    end
-    config.delete(:import)
-  end
-
-
-  def eval_environment_variables(config)
-    config[:environment].each do |hash|
-      key   = hash.keys[0]
-      value = hash[key]
-      items = []
-
-      interstitial = ((key == :path) ? File::PATH_SEPARATOR : '')
-      items = ((value.class == Array) ? hash[key] : [value])
-
-      items.each { |item| item.replace( @system_wrapper.module_eval( item ) ) if (item =~ RUBY_STRING_REPLACEMENT_PATTERN) }
-      hash[key] = items.join( interstitial )
-
-      @system_wrapper.env_set( key.to_s.upcase, hash[key] )
-    end
-  end
-
-
-  def eval_paths(config)
-    # [:plugins]:[load_paths] already handled
-
-    paths = [ # individual paths that don't follow convention processed below
-      config[:project][:build_root],
-      config[:release_build][:artifacts]]
-
-    eval_path_list( paths )
-
-    config[:paths].each_pair { |collection, paths| eval_path_list( paths ) }
-
-    config[:files].each_pair { |collection, files| eval_path_list( files ) }
-
-    # all other paths at secondary hash key level processed by convention:
-    # ex. [:toplevel][:foo_path] & [:toplevel][:bar_paths] are evaluated
-    config.each_pair { |parent, child| eval_path_list( collect_path_list( child ) ) }
-  end
-
-
-  def standardize_paths(config)
-    # [:plugins]:[load_paths] already handled
-
-    paths = [ # individual paths that don't follow convention processed below
-      config[:project][:build_root],
-      config[:release_build][:artifacts]] # cmock path in case it was explicitly set in config
-
-    paths.flatten.each { |path| FilePathUtils::standardize( path ) }
-
-    config[:paths].each_pair do |collection, paths|
-      # ensure that list is an array (i.e. handle case of list being a single string,
-      # or a multidimensional array)
-      config[:paths][collection] = [paths].flatten.map{|path| FilePathUtils::standardize( path )}
-    end
-
-    config[:files].each_pair { |collection, files| files.each{ |path| FilePathUtils::standardize( path ) } }
-
-    config[:tools].each_pair { |tool, config| FilePathUtils::standardize( config[:executable] ) if (config.include? :executable) }
-
-    # all other paths at secondary hash key level processed by convention:
-    # ex. [:toplevel][:foo_path] & [:toplevel][:bar_paths] are standardized
-    config.each_pair do |parent, child|
-      collect_path_list( child ).each { |path| FilePathUtils::standardize( path ) }
-    end
-  end
-
-
-  def validate(config)
-    # collect felonies and go straight to jail
-    raise if (not @configurator_setup.validate_required_sections( config ))
-
-    # collect all misdemeanors, everybody on probation
-    blotter = []
-    blotter << @configurator_setup.validate_required_section_values( config )
-    blotter << @configurator_setup.validate_paths( config )
-    blotter << @configurator_setup.validate_tools( config )
-    blotter << @configurator_setup.validate_plugins( config )
-
-    raise if (blotter.include?( false ))
-  end
-
-
-  # create constants and accessors (attached to this object) from given hash
-  def build(config, *keys)
-    # create flattened & expanded configuration hash
-    built_config = @configurator_setup.build_project_config( config, @configurator_builder.flattenify( config ) )
-
-    @project_config_hash = built_config.clone
-    store_config()
-
-    @configurator_setup.build_constants_and_accessors(built_config, binding())
-
-    # top-level keys disappear when we flatten, so create global constants & accessors to any specified keys
-    keys.each do |key|
-      hash = { key => config[key] }
-      @configurator_setup.build_constants_and_accessors(hash, binding())
-    end
-  end
-
-
-  # add to constants and accessors as post build step
-  def build_supplement(config_base, config_more)
-    # merge in our post-build additions to base configuration hash
-    config_base.deep_merge!( config_more )
-
-    # flatten our addition hash
-    config_more_flattened = @configurator_builder.flattenify( config_more )
-
-    # merge our flattened hash with built hash from previous build
-    @project_config_hash.deep_merge!( config_more_flattened )
-    store_config()
-
-    # create more constants and accessors
-    @configurator_setup.build_constants_and_accessors(config_more_flattened, binding())
-
-    # recreate constants & update accessors with new merged, base values
-    config_more.keys.each do |key|
-      hash = { key => config_base[key] }
-      @configurator_setup.build_constants_and_accessors(hash, binding())
-    end
-  end
-
-
-  def insert_rake_plugins(plugins)
-    plugins.each do |plugin|
-      @project_config_hash[:project_rakefile_component_files] << plugin
-    end
-  end
-
-  ### private ###
-
-  private
-
-  def collect_path_list( container )
-    paths = []
-    container.each_key { |key| paths << container[key] if (key.to_s =~ /_path(s)?$/) } if (container.class == Hash)
-    return paths.flatten
-  end
-
-  def eval_path_list( paths )
-    if paths.kind_of?(Array)
-      paths = Array.new(paths)
-    end
-
-    paths.flatten.each do |path|
-      path.replace( @system_wrapper.module_eval( path ) ) if (path =~ RUBY_STRING_REPLACEMENT_PATTERN)
-    end
-  end
-
-
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_builder.rb b/test/vendor/ceedling/lib/ceedling/configurator_builder.rb
deleted file mode 100644
index da8a816f5..000000000
--- a/test/vendor/ceedling/lib/ceedling/configurator_builder.rb
+++ /dev/null
@@ -1,458 +0,0 @@
-require 'rubygems'
-require 'rake'            # for ext() method
-require 'ceedling/file_path_utils' # for class methods
-require 'ceedling/defaults'
-require 'ceedling/constants'       # for Verbosity constants class & base file paths
-
-
-
-class ConfiguratorBuilder
-
-  constructor :file_system_utils, :file_wrapper, :system_wrapper
-
-
-  def build_global_constants(config)
-    config.each_pair do |key, value|
-      formatted_key = key.to_s.upcase
-      # undefine global constant if it already exists
-      Object.send(:remove_const, formatted_key.to_sym) if @system_wrapper.constants_include?(formatted_key)
-      # create global constant
-      Object.module_eval("#{formatted_key} = value")
-    end
-  end
-
-
-  def build_accessor_methods(config, context)
-    config.each_pair do |key, value|
-      # fill configurator object with accessor methods
-      eval("def #{key.to_s.downcase}() return @project_config_hash[:#{key.to_s}] end", context)
-    end
-  end
-
-
-  # create a flattened hash from the original configuration structure
-  def flattenify(config)
-    new_hash = {}
-
-    config.each_key do | parent |
-
-      # gracefully handle empty top-level entries
-      next if (config[parent].nil?)
-
-      case config[parent]
-      when Array
-        config[parent].each do |hash|
-          key = "#{parent.to_s.downcase}_#{hash.keys[0].to_s.downcase}".to_sym
-          new_hash[key] = hash[hash.keys[0]]
-        end
-      when Hash
-        config[parent].each_pair do | child, value |
-          key = "#{parent.to_s.downcase}_#{child.to_s.downcase}".to_sym
-          new_hash[key] = value
-        end
-      # handle entries with no children, only values
-      else
-        new_hash["#{parent.to_s.downcase}".to_sym] = config[parent]
-      end
-
-    end
-
-    return new_hash
-  end
-
-
-  def populate_defaults(config, defaults)
-    defaults.keys.sort.each do |section|
-      defaults[section].keys.sort.each do |entry|
-        config[section] = {} if config[section].nil?
-        config[section][entry] = defaults[section][entry].deep_clone if (config[section][entry].nil?)
-      end
-    end
-  end
-
-
-  def clean(in_hash)
-    # ensure that include files inserted into test runners have file extensions & proper ones at that
-    in_hash[:test_runner_includes].map!{|include| include.ext(in_hash[:extension_header])}
-  end
-
-
-  def set_build_paths(in_hash)
-    out_hash = {}
-
-    project_build_artifacts_root = File.join(in_hash[:project_build_root], 'artifacts')
-    project_build_tests_root     = File.join(in_hash[:project_build_root], TESTS_BASE_PATH)
-    project_build_release_root   = File.join(in_hash[:project_build_root], RELEASE_BASE_PATH)
-
-    paths = [
-      [:project_build_artifacts_root,  project_build_artifacts_root, true ],
-      [:project_build_tests_root,      project_build_tests_root,     true ],
-      [:project_build_release_root,    project_build_release_root,   in_hash[:project_release_build] ],
-
-      [:project_test_artifacts_path,            File.join(project_build_artifacts_root, TESTS_BASE_PATH), true ],
-      [:project_test_runners_path,              File.join(project_build_tests_root, 'runners'),           true ],
-      [:project_test_results_path,              File.join(project_build_tests_root, 'results'),           true ],
-      [:project_test_build_output_path,         File.join(project_build_tests_root, 'out'),               true ],
-      [:project_test_build_output_asm_path,     File.join(project_build_tests_root, 'out', 'asm'),        true ],
-      [:project_test_build_output_c_path,       File.join(project_build_tests_root, 'out', 'c'),          true ],
-      [:project_test_build_cache_path,          File.join(project_build_tests_root, 'cache'),             true ],
-      [:project_test_dependencies_path,         File.join(project_build_tests_root, 'dependencies'),      true ],
-
-      [:project_release_artifacts_path,         File.join(project_build_artifacts_root, RELEASE_BASE_PATH), in_hash[:project_release_build] ],
-      [:project_release_build_cache_path,       File.join(project_build_release_root, 'cache'),             in_hash[:project_release_build] ],
-      [:project_release_build_output_path,      File.join(project_build_release_root, 'out'),               in_hash[:project_release_build] ],
-      [:project_release_build_output_asm_path,  File.join(project_build_release_root, 'out', 'asm'),        in_hash[:project_release_build] ],
-      [:project_release_build_output_c_path,    File.join(project_build_release_root, 'out', 'c'),          in_hash[:project_release_build] ],
-      [:project_release_dependencies_path,      File.join(project_build_release_root, 'dependencies'),      in_hash[:project_release_build] ],
-
-      [:project_log_path,   File.join(in_hash[:project_build_root], 'logs'), true ],
-      [:project_temp_path,  File.join(in_hash[:project_build_root], 'temp'), true ],
-
-      [:project_test_preprocess_includes_path,  File.join(project_build_tests_root, 'preprocess/includes'), in_hash[:project_use_test_preprocessor] ],
-      [:project_test_preprocess_files_path,     File.join(project_build_tests_root, 'preprocess/files'),    in_hash[:project_use_test_preprocessor] ],
-    ]
-
-    out_hash[:project_build_paths] = []
-
-    # fetch already set mock path
-    out_hash[:project_build_paths] << in_hash[:cmock_mock_path] if (in_hash[:project_use_mocks])
-
-    paths.each do |path|
-      build_path_name          = path[0]
-      build_path               = path[1]
-      build_path_add_condition = path[2]
-
-      # insert path into build paths if associated with true condition
-      out_hash[:project_build_paths] << build_path if build_path_add_condition
-      # set path symbol name and path for each entry in paths array
-      out_hash[build_path_name] = build_path
-    end
-
-    return out_hash
-  end
-
-
-  def set_force_build_filepaths(in_hash)
-    out_hash = {}
-
-    out_hash[:project_test_force_rebuild_filepath]    = File.join( in_hash[:project_test_dependencies_path], 'force_build' )
-    out_hash[:project_release_force_rebuild_filepath] = File.join( in_hash[:project_release_dependencies_path], 'force_build' ) if (in_hash[:project_release_build])
-
-    return out_hash
-  end
-
-
-  def set_rakefile_components(in_hash)
-    out_hash = {
-      :project_rakefile_component_files =>
-        [File.join(CEEDLING_LIB, 'ceedling', 'tasks_base.rake'),
-         File.join(CEEDLING_LIB, 'ceedling', 'tasks_filesystem.rake'),
-         File.join(CEEDLING_LIB, 'ceedling', 'tasks_tests.rake'),
-         File.join(CEEDLING_LIB, 'ceedling', 'tasks_vendor.rake'),
-         File.join(CEEDLING_LIB, 'ceedling', 'rules_tests.rake')]}
-
-    out_hash[:project_rakefile_component_files] << File.join(CEEDLING_LIB, 'ceedling', 'rules_cmock.rake') if (in_hash[:project_use_mocks])
-    out_hash[:project_rakefile_component_files] << File.join(CEEDLING_LIB, 'ceedling', 'rules_preprocess.rake') if (in_hash[:project_use_test_preprocessor])
-    out_hash[:project_rakefile_component_files] << File.join(CEEDLING_LIB, 'ceedling', 'rules_tests_deep_dependencies.rake') if (in_hash[:project_use_deep_dependencies])
-    out_hash[:project_rakefile_component_files] << File.join(CEEDLING_LIB, 'ceedling', 'tasks_tests_deep_dependencies.rake') if (in_hash[:project_use_deep_dependencies])
-
-    out_hash[:project_rakefile_component_files] << File.join(CEEDLING_LIB, 'ceedling', 'rules_release_deep_dependencies.rake') if (in_hash[:project_release_build] and in_hash[:project_use_deep_dependencies])
-    out_hash[:project_rakefile_component_files] << File.join(CEEDLING_LIB, 'ceedling', 'rules_release.rake') if (in_hash[:project_release_build])
-    out_hash[:project_rakefile_component_files] << File.join(CEEDLING_LIB, 'ceedling', 'tasks_release_deep_dependencies.rake') if (in_hash[:project_release_build] and in_hash[:project_use_deep_dependencies])
-    out_hash[:project_rakefile_component_files] << File.join(CEEDLING_LIB, 'ceedling', 'tasks_release.rake') if (in_hash[:project_release_build])
-
-    return out_hash
-  end
-
-
-  def set_release_target(in_hash)
-    return {} if (not in_hash[:project_release_build])
-
-    release_target_file = ((in_hash[:release_build_output].nil?) ? (DEFAULT_RELEASE_TARGET_NAME.ext(in_hash[:extension_executable])) : in_hash[:release_build_output])
-    release_map_file    = ((in_hash[:release_build_output].nil?) ? (DEFAULT_RELEASE_TARGET_NAME.ext(in_hash[:extension_map])) : in_hash[:release_build_output].ext(in_hash[:extension_map]))
-
-    return {
-      # tempted to make a helper method in file_path_utils? stop right there, pal. you'll introduce a cyclical dependency
-      :project_release_build_target => File.join(in_hash[:project_build_release_root], release_target_file),
-      :project_release_build_map    => File.join(in_hash[:project_build_release_root], release_map_file)
-      }
-  end
-
-
-  def collect_project_options(in_hash)
-    options = []
-
-    in_hash[:project_options_paths].each do |path|
-      options << @file_wrapper.directory_listing( File.join(path, '*.yml') )
-    end
-
-    return {
-      :collection_project_options => options.flatten
-      }
-  end
-
-
-  def expand_all_path_globs(in_hash)
-    out_hash = {}
-    path_keys = []
-
-    in_hash.each_key do |key|
-      next if (not key.to_s[0..4] == 'paths')
-      path_keys << key
-    end
-
-    # sorted to provide assured order of traversal in test calls on mocks
-    path_keys.sort.each do |key|
-      out_hash["collection_#{key.to_s}".to_sym] = @file_system_utils.collect_paths( in_hash[key] )
-    end
-
-    return out_hash
-  end
-
-
-  def collect_source_and_include_paths(in_hash)
-    return {
-      :collection_paths_source_and_include =>
-        ( in_hash[:collection_paths_source] +
-          in_hash[:collection_paths_include] ).select {|x| File.directory?(x)}
-      }
-  end
-
-
-  def collect_source_include_vendor_paths(in_hash)
-    extra_paths = []
-    extra_paths << File.join(in_hash[:cexception_vendor_path], CEXCEPTION_LIB_PATH) if (in_hash[:project_use_exceptions])
-
-    return {
-      :collection_paths_source_include_vendor =>
-        in_hash[:collection_paths_source_and_include] +
-        extra_paths
-      }
-  end
-
-
-  def collect_test_support_source_include_paths(in_hash)
-    return {
-      :collection_paths_test_support_source_include =>
-        (in_hash[:collection_paths_test] +
-        in_hash[:collection_paths_support] +
-        in_hash[:collection_paths_source] +
-        in_hash[:collection_paths_include] ).select {|x| File.directory?(x)}
-      }
-  end
-
-
-  def collect_vendor_paths(in_hash)
-    return {:collection_paths_vendor => get_vendor_paths(in_hash)}
-  end
-
-
-  def collect_test_support_source_include_vendor_paths(in_hash)
-    return {
-      :collection_paths_test_support_source_include_vendor =>
-        in_hash[:collection_paths_test_support_source_include] +
-        get_vendor_paths(in_hash)
-      }
-  end
-
-
-  def collect_tests(in_hash)
-    all_tests = @file_wrapper.instantiate_file_list
-
-    in_hash[:collection_paths_test].each do |path|
-      all_tests.include( File.join(path, "#{in_hash[:project_test_file_prefix]}*#{in_hash[:extension_source]}") )
-    end
-
-    @file_system_utils.revise_file_list( all_tests, in_hash[:files_test] )
-
-    return {:collection_all_tests => all_tests}
-  end
-
-
-  def collect_assembly(in_hash)
-    all_assembly = @file_wrapper.instantiate_file_list
-
-    return {:collection_all_assembly => all_assembly} if ((not in_hash[:release_build_use_assembly]) && (not in_hash[:test_build_use_assembly]))
-
-    # Sprinkle in all assembly files we can find in the source folders
-    in_hash[:collection_paths_source].each do |path|
-      all_assembly.include( File.join(path, "*#{in_hash[:extension_assembly]}") )
-    end
-
-    # Also add all assembly files we can find in the support folders
-    in_hash[:collection_paths_support].each do |path|
-      all_assembly.include( File.join(path, "*#{in_hash[:extension_assembly]}") )
-    end
-
-    # Also add files that we are explicitly adding via :files:assembly: section
-    @file_system_utils.revise_file_list( all_assembly, in_hash[:files_assembly] )
-
-    return {:collection_all_assembly => all_assembly}
-  end
-
-
-  def collect_source(in_hash)
-    all_source = @file_wrapper.instantiate_file_list
-    in_hash[:collection_paths_source].each do |path|
-      if File.exists?(path) and not File.directory?(path)
-        all_source.include( path )
-      else
-        all_source.include( File.join(path, "*#{in_hash[:extension_source]}") )
-      end
-    end
-    @file_system_utils.revise_file_list( all_source, in_hash[:files_source] )
-
-    return {:collection_all_source => all_source}
-  end
-
-
-  def collect_headers(in_hash)
-    all_headers = @file_wrapper.instantiate_file_list
-
-    paths =
-      in_hash[:collection_paths_test] +
-      in_hash[:collection_paths_support] +
-      in_hash[:collection_paths_source] +
-      in_hash[:collection_paths_include]
-
-    paths.each do |path|
-      all_headers.include( File.join(path, "*#{in_hash[:extension_header]}") )
-    end
-
-    @file_system_utils.revise_file_list( all_headers, in_hash[:files_include] )
-
-    return {:collection_all_headers => all_headers}
-  end
-
-
-  def collect_release_existing_compilation_input(in_hash)
-    release_input = @file_wrapper.instantiate_file_list
-
-    paths =
-      in_hash[:collection_paths_source] +
-      in_hash[:collection_paths_include]
-
-    paths << File.join(in_hash[:cexception_vendor_path], CEXCEPTION_LIB_PATH) if (in_hash[:project_use_exceptions])
-
-    paths.each do |path|
-      release_input.include( File.join(path, "*#{in_hash[:extension_header]}") )
-      if File.exists?(path) and not File.directory?(path)
-        release_input.include( path )
-      else
-        release_input.include( File.join(path, "*#{in_hash[:extension_source]}") )
-      end
-    end
-
-    @file_system_utils.revise_file_list( release_input, in_hash[:files_source] )
-    @file_system_utils.revise_file_list( release_input, in_hash[:files_include] )
-    # finding assembly files handled explicitly through other means
-
-    return {:collection_release_existing_compilation_input => release_input}
-  end
-
-
-  def collect_all_existing_compilation_input(in_hash)
-    all_input = @file_wrapper.instantiate_file_list
-
-    paths =
-      in_hash[:collection_paths_test] +
-      in_hash[:collection_paths_support] +
-      in_hash[:collection_paths_source] +
-      in_hash[:collection_paths_include] +
-      [File.join(in_hash[:unity_vendor_path], UNITY_LIB_PATH)]
-
-    paths << File.join(in_hash[:cexception_vendor_path], CEXCEPTION_LIB_PATH) if (in_hash[:project_use_exceptions])
-    paths << File.join(in_hash[:cmock_vendor_path],      CMOCK_LIB_PATH)      if (in_hash[:project_use_mocks])
-
-    paths.each do |path|
-      all_input.include( File.join(path, "*#{in_hash[:extension_header]}") )
-      if File.exists?(path) and not File.directory?(path)
-        all_input.include( path )
-      else
-        all_input.include( File.join(path, "*#{in_hash[:extension_source]}") )
-        all_input.include( File.join(path, "*#{in_hash[:extension_assembly]}") ) if (defined?(TEST_BUILD_USE_ASSEMBLY) && TEST_BUILD_USE_ASSEMBLY)
-      end
-    end
-
-    @file_system_utils.revise_file_list( all_input, in_hash[:files_test] )
-    @file_system_utils.revise_file_list( all_input, in_hash[:files_support] )
-    @file_system_utils.revise_file_list( all_input, in_hash[:files_source] )
-    @file_system_utils.revise_file_list( all_input, in_hash[:files_include] )
-    # finding assembly files handled explicitly through other means
-
-    return {:collection_all_existing_compilation_input => all_input}
-  end
-
-
-  def collect_test_and_vendor_defines(in_hash)
-    test_defines = in_hash[:defines_test].clone
-
-    test_defines.concat(in_hash[:unity_defines])
-    test_defines.concat(in_hash[:cmock_defines])      if (in_hash[:project_use_mocks])
-    test_defines.concat(in_hash[:cexception_defines]) if (in_hash[:project_use_exceptions])
-
-    return {:collection_defines_test_and_vendor => test_defines}
-  end
-
-
-  def collect_release_and_vendor_defines(in_hash)
-    release_defines = in_hash[:defines_release].clone
-
-    release_defines.concat(in_hash[:cexception_defines]) if (in_hash[:project_use_exceptions])
-
-    return {:collection_defines_release_and_vendor => release_defines}
-  end
-
-
-  def collect_release_artifact_extra_link_objects(in_hash)
-    objects = []
-
-    # no build paths here so plugins can remap if necessary (i.e. path mapping happens at runtime)
-    objects << CEXCEPTION_C_FILE.ext( in_hash[:extension_object] ) if (in_hash[:project_use_exceptions])
-
-    return {:collection_release_artifact_extra_link_objects => objects}
-  end
-
-
-  def collect_test_fixture_extra_link_objects(in_hash)
-    #  Note: Symbols passed to compiler at command line can change Unity and CException behavior / configuration;
-    #    we also handle those dependencies elsewhere in compilation dependencies
-
-    objects = [UNITY_C_FILE]
-
-    in_hash[:files_support].each { |file| objects << File.basename(file) }
-
-    # we don't include paths here because use of plugins or mixing different compilers may require different build paths
-    objects << CEXCEPTION_C_FILE if (in_hash[:project_use_exceptions])
-    objects << CMOCK_C_FILE      if (in_hash[:project_use_mocks])
-
-    # if we're using mocks & a unity helper is defined & that unity helper includes a source file component (not only a header of macros),
-    # then link in the unity_helper object file too
-    if ( in_hash[:project_use_mocks] and in_hash[:cmock_unity_helper] )
-      in_hash[:cmock_unity_helper].each do |helper|
-        if @file_wrapper.exist?(helper.ext(in_hash[:extension_source]))
-          objects << File.basename(helper)
-        end
-      end
-    end
-
-    # no build paths here so plugins can remap if necessary (i.e. path mapping happens at runtime)
-    objects.map! { |object| object.ext(in_hash[:extension_object]) }
-
-    return { :collection_test_fixture_extra_link_objects => objects }
-  end
-
-
-  private
-
-  def get_vendor_paths(in_hash)
-    vendor_paths = []
-    vendor_paths << File.join(in_hash[:unity_vendor_path],      UNITY_LIB_PATH)
-    vendor_paths << File.join(in_hash[:cexception_vendor_path], CEXCEPTION_LIB_PATH) if (in_hash[:project_use_exceptions])
-    vendor_paths << File.join(in_hash[:cmock_vendor_path],      CMOCK_LIB_PATH)      if (in_hash[:project_use_mocks])
-    vendor_paths << in_hash[:cmock_mock_path]                                        if (in_hash[:project_use_mocks])
-
-    return vendor_paths
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_plugins.rb b/test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
deleted file mode 100644
index 70ca884a2..000000000
--- a/test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
+++ /dev/null
@@ -1,111 +0,0 @@
-require 'ceedling/constants'
-
-class ConfiguratorPlugins
-
-  constructor :stream_wrapper, :file_wrapper, :system_wrapper
-  attr_reader :rake_plugins, :script_plugins
-
-  def setup
-    @rake_plugins   = []
-    @script_plugins = []
-  end
-
-
-  def add_load_paths(config)
-    plugin_paths = {}
-
-    config[:plugins][:enabled].each do |plugin|
-      config[:plugins][:load_paths].each do |root|
-        path = File.join(root, plugin)
-
-        is_script_plugin = ( not @file_wrapper.directory_listing( File.join( path, 'lib', '*.rb' ) ).empty? )
-        is_rake_plugin = ( not @file_wrapper.directory_listing( File.join( path, '*.rake' ) ).empty? )
-
-        if is_script_plugin or is_rake_plugin
-          plugin_paths[(plugin + '_path').to_sym] = path
-
-          if is_script_plugin
-            @system_wrapper.add_load_path( File.join( path, 'lib') )
-          end
-          break
-        end
-      end
-    end
-
-    return plugin_paths
-  end
-
-
-  # gather up and return .rake filepaths that exist on-disk
-  def find_rake_plugins(config, plugin_paths)
-    @rake_plugins = []
-    plugins_with_path = []
-
-    config[:plugins][:enabled].each do |plugin|
-      if path = plugin_paths[(plugin + '_path').to_sym]
-        rake_plugin_path = File.join(path, "#{plugin}.rake")
-        if (@file_wrapper.exist?(rake_plugin_path))
-          plugins_with_path << rake_plugin_path
-          @rake_plugins << plugin
-        end
-      end
-    end
-
-    return plugins_with_path
-  end
-
-
-  # gather up and return just names of .rb classes that exist on-disk
-  def find_script_plugins(config, plugin_paths)
-    @script_plugins = []
-
-    config[:plugins][:enabled].each do |plugin|
-      if path = plugin_paths[(plugin + '_path').to_sym]
-        script_plugin_path = File.join(path, "lib", "#{plugin}.rb")
-
-        if @file_wrapper.exist?(script_plugin_path)
-          @script_plugins << plugin
-        end
-      end
-    end
-
-    return @script_plugins
-  end
-
-
-  # gather up and return configuration .yml filepaths that exist on-disk
-  def find_config_plugins(config, plugin_paths)
-    plugins_with_path = []
-
-    config[:plugins][:enabled].each do |plugin|
-      if path = plugin_paths[(plugin + '_path').to_sym]
-        config_plugin_path = File.join(path, "config", "#{plugin}.yml")
-
-        if @file_wrapper.exist?(config_plugin_path)
-          plugins_with_path << config_plugin_path
-        end
-      end
-    end
-
-    return plugins_with_path
-  end
-
-
-  # gather up and return default .yml filepaths that exist on-disk
-  def find_plugin_defaults(config, plugin_paths)
-    defaults_with_path = []
-
-    config[:plugins][:enabled].each do |plugin|
-      if path = plugin_paths[(plugin + '_path').to_sym]
-        default_path = File.join(path, 'config', 'defaults.yml')
-
-        if @file_wrapper.exist?(default_path)
-          defaults_with_path << default_path
-        end
-      end
-    end
-
-    return defaults_with_path
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_setup.rb b/test/vendor/ceedling/lib/ceedling/configurator_setup.rb
deleted file mode 100644
index 1d029b065..000000000
--- a/test/vendor/ceedling/lib/ceedling/configurator_setup.rb
+++ /dev/null
@@ -1,127 +0,0 @@
-
-# add sort-ability to symbol so we can order keys array in hash for test-ability
-class Symbol
-  include Comparable
-
-  def <=>(other)
-    self.to_s <=> other.to_s
-  end
-end
-
-
-class ConfiguratorSetup
-
-  constructor :configurator_builder, :configurator_validator, :configurator_plugins, :stream_wrapper
-
-
-  def build_project_config(config, flattened_config)
-    ### flesh out config
-    @configurator_builder.clean(flattened_config)
-
-    ### add to hash values we build up from configuration & file system contents
-    flattened_config.merge!(@configurator_builder.set_build_paths(flattened_config))
-    flattened_config.merge!(@configurator_builder.set_force_build_filepaths(flattened_config))
-    flattened_config.merge!(@configurator_builder.set_rakefile_components(flattened_config))
-    flattened_config.merge!(@configurator_builder.set_release_target(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_project_options(flattened_config))
-
-    ### iterate through all entries in paths section and expand any & all globs to actual paths
-    flattened_config.merge!(@configurator_builder.expand_all_path_globs(flattened_config))
-
-    flattened_config.merge!(@configurator_builder.collect_vendor_paths(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_source_and_include_paths(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_source_include_vendor_paths(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_test_support_source_include_paths(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_test_support_source_include_vendor_paths(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_tests(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_assembly(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_source(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_headers(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_release_existing_compilation_input(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_all_existing_compilation_input(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_test_and_vendor_defines(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_release_and_vendor_defines(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_release_artifact_extra_link_objects(flattened_config))
-    flattened_config.merge!(@configurator_builder.collect_test_fixture_extra_link_objects(flattened_config))
-
-    return flattened_config
-  end
-
-
-  def build_constants_and_accessors(config, context)
-    @configurator_builder.build_global_constants(config)
-    @configurator_builder.build_accessor_methods(config, context)
-  end
-
-
-  def validate_required_sections(config)
-    validation = []
-    validation << @configurator_validator.exists?(config, :project)
-    validation << @configurator_validator.exists?(config, :paths)
-
-    return false if (validation.include?(false))
-    return true
-  end
-
-  def validate_required_section_values(config)
-    validation = []
-    validation << @configurator_validator.exists?(config, :project, :build_root)
-    validation << @configurator_validator.exists?(config, :paths, :test)
-    validation << @configurator_validator.exists?(config, :paths, :source)
-
-    return false if (validation.include?(false))
-    return true
-  end
-
-  def validate_paths(config)
-    validation = []
-
-    if config[:cmock][:unity_helper]
-      config[:cmock][:unity_helper].each do |path|
-        validation << @configurator_validator.validate_filepath_simple( path, :cmock, :unity_helper ) 
-      end
-    end
-
-    config[:project][:options_paths].each do |path|
-      validation << @configurator_validator.validate_filepath_simple( path, :project, :options_paths )
-    end
-
-    config[:plugins][:load_paths].each do |path|
-      validation << @configurator_validator.validate_filepath_simple( path, :plugins, :load_paths )
-    end
-
-    config[:paths].keys.sort.each do |key|
-      validation << @configurator_validator.validate_path_list(config, :paths, key)
-    end
-
-    return false if (validation.include?(false))
-    return true
-  end
-
-  def validate_tools(config)
-    validation = []
-
-    config[:tools].keys.sort.each do |key|
-      validation << @configurator_validator.exists?(config, :tools, key, :executable)
-      validation << @configurator_validator.validate_executable_filepath(config, :tools, key, :executable) if (not config[:tools][key][:optional])
-      validation << @configurator_validator.validate_tool_stderr_redirect(config, :tools, key)
-    end
-
-    return false if (validation.include?(false))
-    return true
-  end
-
-  def validate_plugins(config)
-    missing_plugins =
-      Set.new( config[:plugins][:enabled] ) -
-      Set.new( @configurator_plugins.rake_plugins ) -
-      Set.new( @configurator_plugins.script_plugins )
-
-    missing_plugins.each do |plugin|
-      @stream_wrapper.stderr_puts("ERROR: Ceedling plugin '#{plugin}' contains no rake or ruby class entry point. (Misspelled or missing files?)")
-    end
-
-    return ( (missing_plugins.size > 0) ? false : true )
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_validator.rb b/test/vendor/ceedling/lib/ceedling/configurator_validator.rb
deleted file mode 100644
index fc0210124..000000000
--- a/test/vendor/ceedling/lib/ceedling/configurator_validator.rb
+++ /dev/null
@@ -1,193 +0,0 @@
-require 'rubygems'
-require 'rake' # for ext()
-require 'ceedling/constants'
-require 'ceedling/tool_executor'    # for argument replacement pattern
-require 'ceedling/file_path_utils'  # for glob handling class methods
-
-
-class ConfiguratorValidator
-  
-  constructor :file_wrapper, :stream_wrapper, :system_wrapper
-
-  # walk into config hash verify existence of data at key depth
-  def exists?(config, *keys)
-    hash  = retrieve_value(config, keys)
-    exist = !hash[:value].nil?
-
-    if (not exist)
-      # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-      @stream_wrapper.stderr_puts("ERROR: Required config file entry #{format_key_sequence(keys, hash[:depth])} does not exist.")    
-    end
-    
-    return exist
-  end
-
-
-  # walk into config hash. verify directory path(s) at given key depth
-  def validate_path_list(config, *keys)
-    hash = retrieve_value(config, keys)
-    list = hash[:value]
-
-    # return early if we couldn't walk into hash and find a value
-    return false if (list.nil?)
-
-    path_list = []
-    exist = true
-    
-    case list
-      when String then path_list << list
-      when Array  then path_list =  list
-    end
-    
-    path_list.each do |path|
-      base_path = FilePathUtils::extract_path(path) # lop off add/subtract notation & glob specifiers
-      
-      if (not @file_wrapper.exist?(base_path))
-        # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-        @stream_wrapper.stderr_puts("ERROR: Config path #{format_key_sequence(keys, hash[:depth])}['#{base_path}'] does not exist on disk.") 
-        exist = false
-      end 
-    end
-    
-    return exist
-  end
-
-  
-  # simple path verification
-  def validate_filepath_simple(path, *keys)
-    validate_path = path
-    
-    if (not @file_wrapper.exist?(validate_path))
-      # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-      @stream_wrapper.stderr_puts("ERROR: Config path '#{validate_path}' associated with #{format_key_sequence(keys, keys.size)} does not exist on disk.") 
-      return false
-    end 
-    
-    return true
-  end
- 
-  # walk into config hash. verify specified file exists.
-  def validate_filepath(config, *keys)
-    hash          = retrieve_value(config, keys)
-    filepath      = hash[:value]
-
-    # return early if we couldn't walk into hash and find a value
-    return false if (filepath.nil?)
-
-    # skip everything if we've got an argument replacement pattern
-    return true if (filepath =~ TOOL_EXECUTOR_ARGUMENT_REPLACEMENT_PATTERN)
-    
-    if (not @file_wrapper.exist?(filepath))
-
-      # See if we can deal with it internally.
-      if GENERATED_DIR_PATH.include?(filepath)      
-        # we already made this directory before let's make it again.
-        FileUtils.mkdir_p File.join(File.dirname(__FILE__), filepath)
-        @stream_wrapper.stderr_puts("WARNING: Generated filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk. Recreating") 
- 
-      else
-        # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-        @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk.")
-        return false
-      end
-    end      
-
-    return true
-  end
-
-  # walk into config hash. verify specified file exists.
-  def validate_executable_filepath(config, *keys)
-    exe_extension = config[:extension][:executable]
-    hash          = retrieve_value(config, keys)
-    filepath      = hash[:value]
-
-    # return early if we couldn't walk into hash and find a value
-    return false if (filepath.nil?)
-
-    # skip everything if we've got an argument replacement pattern
-    return true if (filepath =~ TOOL_EXECUTOR_ARGUMENT_REPLACEMENT_PATTERN)
-    
-    # if there's no path included, verify file exists somewhere in system search paths
-    if (not filepath.include?('/'))
-      exists = false
-      
-      @system_wrapper.search_paths.each do |path|
-        if (@file_wrapper.exist?( File.join(path, filepath)) )
-          exists = true
-          break
-        end
-        
-        if (@file_wrapper.exist?( (File.join(path, filepath)).ext( exe_extension ) ))
-          exists = true
-          break
-        elsif (@system_wrapper.windows? and @file_wrapper.exist?( (File.join(path, filepath)).ext( EXTENSION_WIN_EXE ) ))
-          exists = true
-          break
-        end
-      end
-      
-      if (not exists)
-        # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-        @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist in system search paths.") 
-        return false        
-      end
-      
-    # if there is a path included, check that explicit filepath exists
-    else
-      if (not @file_wrapper.exist?(filepath))
-        # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-        @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk.") 
-        return false
-      end      
-    end
-
-    return true
-  end
-  
-  def validate_tool_stderr_redirect(config, tools, tool)
-    redirect = config[tools][tool][:stderr_redirect]
-    if (redirect.class == Symbol)
-      # map constants and force to array of strings for runtime universality across ruby versions
-      if (not StdErrRedirect.constants.map{|constant| constant.to_s}.include?(redirect.to_s.upcase))
-        error = "ERROR: [:#{tools}][:#{tool}][:stderr_redirect][:#{redirect}] is not a recognized option " +
-                "{#{StdErrRedirect.constants.map{|constant| ':' + constant.to_s.downcase}.join(', ')}}."
-        @stream_wrapper.stderr_puts(error) 
-        return false        
-      end
-    end
-    
-    return true
-  end
-  
-  private #########################################
-  
-  
-  def retrieve_value(config, keys)
-    value = nil
-    hash  = config
-    depth = 0
-
-    # walk into hash & extract value at requested key sequence
-    keys.each do |symbol|
-      depth += 1
-      if (not hash[symbol].nil?)
-        hash  = hash[symbol]
-        value = hash
-      else
-        value = nil
-        break
-      end
-    end
-    
-    return {:value => value, :depth => depth}
-  end
-
-
-  def format_key_sequence(keys, depth)
-    walked_keys    = keys.slice(0, depth)
-    formatted_keys = walked_keys.map{|key| "[:#{key.to_s}]"}
-    
-    return formatted_keys.join
-  end
-  
-end
diff --git a/test/vendor/ceedling/lib/ceedling/constants.rb b/test/vendor/ceedling/lib/ceedling/constants.rb
deleted file mode 100644
index 993ce8db2..000000000
--- a/test/vendor/ceedling/lib/ceedling/constants.rb
+++ /dev/null
@@ -1,97 +0,0 @@
-
-class Verbosity
-  SILENT      = 0  # as silent as possible (though there are some messages that must be spit out)
-  ERRORS      = 1  # only errors
-  COMPLAIN    = 2  # spit out errors and warnings/notices
-  NORMAL      = 3  # errors, warnings/notices, standard status messages
-  OBNOXIOUS   = 4  # all messages including extra verbose output (used for lite debugging / verification)
-  DEBUG       = 5  # special extra verbose output for hardcore debugging
-end
-
-
-class TestResultsSanityChecks
-  NONE      = 0  # no sanity checking of test results
-  NORMAL    = 1  # perform non-problematic checks
-  THOROUGH  = 2  # perform checks that require inside knowledge of system workings
-end
-
-
-class StdErrRedirect
-  NONE = :none
-  AUTO = :auto
-  WIN  = :win
-  UNIX = :unix
-  TCSH = :tcsh
-end
-
-
-class BackgroundExec
-  NONE = :none
-  AUTO = :auto
-  WIN  = :win
-  UNIX = :unix
-end
-
-unless defined?(PROJECT_ROOT)
-  PROJECT_ROOT = Dir.pwd()
-end
-
-GENERATED_DIR_PATH = [['vendor', 'ceedling'], 'src', "test", ['test', 'support'], 'build'].each{|p| File.join(*p)}
-
-EXTENSION_WIN_EXE    = '.exe'
-EXTENSION_NONWIN_EXE = '.out'
-
-
-CEXCEPTION_ROOT_PATH = 'c_exception'
-CEXCEPTION_LIB_PATH  = "#{CEXCEPTION_ROOT_PATH}/lib"
-CEXCEPTION_C_FILE    = 'CException.c'
-CEXCEPTION_H_FILE    = 'CException.h'
-
-UNITY_ROOT_PATH        = 'unity'
-UNITY_LIB_PATH         = "#{UNITY_ROOT_PATH}/src"
-UNITY_C_FILE           = 'unity.c'
-UNITY_H_FILE           = 'unity.h'
-UNITY_INTERNALS_H_FILE = 'unity_internals.h'
-
-CMOCK_ROOT_PATH = 'cmock'
-CMOCK_LIB_PATH  = "#{CMOCK_ROOT_PATH}/src"
-CMOCK_C_FILE    = 'cmock.c'
-CMOCK_H_FILE    = 'cmock.h'
-
-
-DEFAULT_CEEDLING_MAIN_PROJECT_FILE = 'project.yml' unless defined?(DEFAULT_CEEDLING_MAIN_PROJECT_FILE) # main project file
-DEFAULT_CEEDLING_USER_PROJECT_FILE = 'user.yml'    unless defined?(DEFAULT_CEEDLING_USER_PROJECT_FILE) # supplemental user config file
-
-INPUT_CONFIGURATION_CACHE_FILE     = 'input.yml'   unless defined?(INPUT_CONFIGURATION_CACHE_FILE)     # input configuration file dump
-DEFINES_DEPENDENCY_CACHE_FILE      = 'defines_dependency.yml' unless defined?(DEFINES_DEPENDENCY_CACHE_FILE) # preprocessor definitions for files
-
-TEST_ROOT_NAME    = 'test'                unless defined?(TEST_ROOT_NAME)
-TEST_TASK_ROOT    = TEST_ROOT_NAME + ':'  unless defined?(TEST_TASK_ROOT)
-TEST_SYM          = TEST_ROOT_NAME.to_sym unless defined?(TEST_SYM)
-
-RELEASE_ROOT_NAME = 'release'                unless defined?(RELEASE_ROOT_NAME)
-RELEASE_TASK_ROOT = RELEASE_ROOT_NAME + ':'  unless defined?(RELEASE_TASK_ROOT)
-RELEASE_SYM       = RELEASE_ROOT_NAME.to_sym unless defined?(RELEASE_SYM)
-
-REFRESH_ROOT_NAME = 'refresh'                unless defined?(REFRESH_ROOT_NAME)
-REFRESH_TASK_ROOT = REFRESH_ROOT_NAME + ':'  unless defined?(REFRESH_TASK_ROOT)
-REFRESH_SYM       = REFRESH_ROOT_NAME.to_sym unless defined?(REFRESH_SYM)
-
-UTILS_ROOT_NAME   = 'utils'                unless defined?(UTILS_ROOT_NAME)
-UTILS_TASK_ROOT   = UTILS_ROOT_NAME + ':'  unless defined?(UTILS_TASK_ROOT)
-UTILS_SYM         = UTILS_ROOT_NAME.to_sym unless defined?(UTILS_SYM)
-
-OPERATION_COMPILE_SYM  = :compile  unless defined?(OPERATION_COMPILE_SYM)
-OPERATION_ASSEMBLE_SYM = :assemble unless defined?(OPERATION_ASSEMBLE_SYM)
-OPERATION_LINK_SYM     = :link     unless defined?(OPERATION_LINK_SYM)
-
-
-RUBY_STRING_REPLACEMENT_PATTERN = /#\{.+\}/
-RUBY_EVAL_REPLACEMENT_PATTERN   = /^\{(.+)\}$/
-TOOL_EXECUTOR_ARGUMENT_REPLACEMENT_PATTERN = /(\$\{(\d+)\})/
-TEST_STDOUT_STATISTICS_PATTERN  = /\n-+\s*(\d+)\s+Tests\s+(\d+)\s+Failures\s+(\d+)\s+Ignored\s+(OK|FAIL)\s*/i
-
-NULL_FILE_PATH = '/dev/null'
-
-TESTS_BASE_PATH   = TEST_ROOT_NAME
-RELEASE_BASE_PATH = RELEASE_ROOT_NAME
diff --git a/test/vendor/ceedling/lib/ceedling/defaults.rb b/test/vendor/ceedling/lib/ceedling/defaults.rb
deleted file mode 100644
index 9e391fa09..000000000
--- a/test/vendor/ceedling/lib/ceedling/defaults.rb
+++ /dev/null
@@ -1,418 +0,0 @@
-require 'ceedling/constants'
-require 'ceedling/system_wrapper'
-require 'ceedling/file_path_utils'
-
-#this should be defined already, but not always during system specs
-CEEDLING_VENDOR = File.expand_path(File.dirname(__FILE__) + '/../../vendor') unless defined? CEEDLING_VENDOR
-CEEDLING_PLUGINS = [] unless defined? CEEDLING_PLUGINS
-
-DEFAULT_TEST_COMPILER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
-  :name => 'default_test_compiler'.freeze,
-  :stderr_redirect => StdErrRedirect::NONE.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [
-    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR'}.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE'}.freeze,
-    {"-D$" => 'COLLECTION_DEFINES_TEST_AND_VENDOR'}.freeze,
-    "-DGNU_COMPILER".freeze,
-    "-g".freeze,
-    "-c \"${1}\"".freeze,
-    "-o \"${2}\"".freeze,
-    # gcc's list file output options are complex; no use of ${3} parameter in default config
-    "-MMD".freeze,
-    "-MF \"${4}\"".freeze,
-    ].freeze
-  }
-
-DEFAULT_TEST_LINKER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
-  :name => 'default_test_linker'.freeze,
-  :stderr_redirect => StdErrRedirect::NONE.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [
-    "\"${1}\"".freeze,
-    "-o \"${2}\"".freeze,
-    "".freeze,
-    "${4}".freeze
-    ].freeze
-  }
-
-DEFAULT_TEST_FIXTURE_TOOL = {
-  :executable => '${1}'.freeze,
-  :name => 'default_test_fixture'.freeze,
-  :stderr_redirect => StdErrRedirect::AUTO.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [].freeze
-  }
-
-DEFAULT_TEST_INCLUDES_PREPROCESSOR_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
-  :name => 'default_test_includes_preprocessor'.freeze,
-  :stderr_redirect => StdErrRedirect::NONE.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [
-    '-E'.freeze, # OSX clang
-    '-MM'.freeze,
-    '-MG'.freeze,
-    # avoid some possibility of deep system lib header file complications by omitting vendor paths
-    # if cpp is run on *nix system, escape spaces in paths; if cpp on windows just use the paths collection as is
-    # {"-I\"$\"" => "{SystemWrapper.windows? ? COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE : COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE.map{|path| path.gsub(\/ \/, \'\\\\ \') }}"}.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR'}.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE'}.freeze,
-    {"-D$" => 'COLLECTION_DEFINES_TEST_AND_VENDOR'}.freeze,
-    {"-D$" => 'DEFINES_TEST_PREPROCESS'}.freeze,
-    "-DGNU_COMPILER".freeze, # OSX clang
-    '-w'.freeze,
-    # '-nostdinc'.freeze, # disabled temporarily due to stdio access violations on OSX
-    "\"${1}\"".freeze
-    ].freeze
-  }
-
-DEFAULT_TEST_FILE_PREPROCESSOR_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
-  :name => 'default_test_file_preprocessor'.freeze,
-  :stderr_redirect => StdErrRedirect::NONE.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [
-    '-E'.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR'}.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE'}.freeze,
-    {"-D$" => 'COLLECTION_DEFINES_TEST_AND_VENDOR'}.freeze,
-    {"-D$" => 'DEFINES_TEST_PREPROCESS'}.freeze,
-    "-DGNU_COMPILER".freeze,
-    # '-nostdinc'.freeze, # disabled temporarily due to stdio access violations on OSX
-    "\"${1}\"".freeze,
-    "-o \"${2}\"".freeze
-    ].freeze
-  }
-
-# Disable the -MD flag for OSX LLVM Clang, since unsupported
-if RUBY_PLATFORM =~ /darwin/ && `gcc --version 2> /dev/null` =~ /Apple LLVM version .* \(clang/m # OSX w/LLVM Clang
-  MD_FLAG = '' # Clang doesn't support the -MD flag
-else
-  MD_FLAG = '-MD'
-end
-
-DEFAULT_TEST_DEPENDENCIES_GENERATOR_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
-  :name => 'default_test_dependencies_generator'.freeze,
-  :stderr_redirect => StdErrRedirect::NONE.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [
-    '-E'.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR'}.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE'}.freeze,
-    {"-D$" => 'COLLECTION_DEFINES_TEST_AND_VENDOR'}.freeze,
-    {"-D$" => 'DEFINES_TEST_PREPROCESS'}.freeze,
-    "-DGNU_COMPILER".freeze,
-    "-MT \"${3}\"".freeze,
-    '-MM'.freeze,
-    MD_FLAG.freeze,
-    '-MG'.freeze,
-    "-MF \"${2}\"".freeze,
-    "-c \"${1}\"".freeze,
-    # '-nostdinc'.freeze,
-    ].freeze
-  }
-
-DEFAULT_RELEASE_DEPENDENCIES_GENERATOR_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
-  :name => 'default_release_dependencies_generator'.freeze,
-  :stderr_redirect => StdErrRedirect::NONE.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [
-    '-E'.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_SOURCE_INCLUDE_VENDOR'}.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_RELEASE_TOOLCHAIN_INCLUDE'}.freeze,
-    {"-D$" => 'COLLECTION_DEFINES_RELEASE_AND_VENDOR'}.freeze,
-    {"-D$" => 'DEFINES_RELEASE_PREPROCESS'}.freeze,
-    "-DGNU_COMPILER".freeze,
-    "-MT \"${3}\"".freeze,
-    '-MM'.freeze,
-    MD_FLAG.freeze,
-    '-MG'.freeze,
-    "-MF \"${2}\"".freeze,
-    "-c \"${1}\"".freeze,
-    # '-nostdinc'.freeze,
-    ].freeze
-  }
-
-
-DEFAULT_RELEASE_COMPILER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
-  :name => 'default_release_compiler'.freeze,
-  :stderr_redirect => StdErrRedirect::NONE.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [
-    {"-I\"$\"" => 'COLLECTION_PATHS_SOURCE_INCLUDE_VENDOR'}.freeze,
-    {"-I\"$\"" => 'COLLECTION_PATHS_RELEASE_TOOLCHAIN_INCLUDE'}.freeze,
-    {"-D$" => 'COLLECTION_DEFINES_RELEASE_AND_VENDOR'}.freeze,
-    "-DGNU_COMPILER".freeze,
-    "-c \"${1}\"".freeze,
-    "-o \"${2}\"".freeze,
-    # gcc's list file output options are complex; no use of ${3} parameter in default config
-    "-MMD".freeze,
-    "-MF \"${4}\"".freeze,
-    ].freeze
-  }
-
-DEFAULT_RELEASE_ASSEMBLER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('as').freeze,
-  :name => 'default_release_assembler'.freeze,
-  :stderr_redirect => StdErrRedirect::NONE.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [
-    {"-I\"$\"" => 'COLLECTION_PATHS_SOURCE_AND_INCLUDE'}.freeze,
-    "\"${1}\"".freeze,
-    "-o \"${2}\"".freeze,
-    ].freeze
-  }
-
-DEFAULT_RELEASE_LINKER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
-  :name => 'default_release_linker'.freeze,
-  :stderr_redirect => StdErrRedirect::NONE.freeze,
-  :background_exec => BackgroundExec::NONE.freeze,
-  :optional => false.freeze,
-  :arguments => [
-    "\"${1}\"".freeze,
-    "-o \"${2}\"".freeze,
-    "".freeze,
-    "${4}".freeze
-    ].freeze
-  }
-
-
-DEFAULT_TOOLS_TEST = {
-  :tools => {
-    :test_compiler => DEFAULT_TEST_COMPILER_TOOL,
-    :test_linker   => DEFAULT_TEST_LINKER_TOOL,
-    :test_fixture  => DEFAULT_TEST_FIXTURE_TOOL,
-    }
-  }
-
-DEFAULT_TOOLS_TEST_PREPROCESSORS = {
-  :tools => {
-    :test_includes_preprocessor => DEFAULT_TEST_INCLUDES_PREPROCESSOR_TOOL,
-    :test_file_preprocessor     => DEFAULT_TEST_FILE_PREPROCESSOR_TOOL,
-    }
-  }
-
-DEFAULT_TOOLS_TEST_DEPENDENCIES = {
-  :tools => {
-    :test_dependencies_generator => DEFAULT_TEST_DEPENDENCIES_GENERATOR_TOOL,
-    }
-  }
-
-
-DEFAULT_TOOLS_RELEASE = {
-  :tools => {
-    :release_compiler => DEFAULT_RELEASE_COMPILER_TOOL,
-    :release_linker   => DEFAULT_RELEASE_LINKER_TOOL,
-    }
-  }
-
-DEFAULT_TOOLS_RELEASE_ASSEMBLER = {
-  :tools => {
-    :release_assembler => DEFAULT_RELEASE_ASSEMBLER_TOOL,
-    }
-  }
-
-DEFAULT_TOOLS_RELEASE_DEPENDENCIES = {
-  :tools => {
-    :release_dependencies_generator => DEFAULT_RELEASE_DEPENDENCIES_GENERATOR_TOOL,
-    }
-  }
-
-
-DEFAULT_RELEASE_TARGET_NAME = 'project'
-
-DEFAULT_CEEDLING_CONFIG = {
-    :project => {
-      # :build_root must be set by user
-      :use_exceptions => true,
-      :use_mocks => true,
-      :compile_threads => 1,
-      :test_threads => 1,
-      :use_test_preprocessor => false,
-      :use_deep_dependencies => false,
-      :generate_deep_dependencies => true, # only applicable if use_deep_dependencies is true
-      :test_file_prefix => 'test_',
-      :options_paths => [],
-      :release_build => false,
-    },
-
-    :release_build => {
-      # :output is set while building configuration -- allows smart default system-dependent file extension handling
-      :use_assembly => false,
-      :artifacts => [],
-    },
-
-    :paths => {
-      :test => [],   # must be populated by user
-      :source => [], # must be populated by user
-      :support => [],
-      :include => [],
-      :test_toolchain_include => [],
-      :release_toolchain_include => [],
-    },
-
-    :files => {
-      :test => [],
-      :source => [],
-      :assembly => [],
-      :support => [],
-      :include => [],
-    },
-
-    # unlike other top-level entries, environment's value is an array to preserve order
-    :environment => [
-      # when evaluated, this provides wider text field for rake task comments
-      {:rake_columns => '120'},
-    ],
-
-    :defines => {
-      :test => [],
-      :test_preprocess => [],
-      :release => [],
-      :release_preprocess => [],
-      :use_test_definition => false,
-    },
-
-    :libraries => {
-      :test => [],
-      :test_preprocess => [],
-      :release => [],
-      :release_preprocess => [],
-    },
-
-    :flags => {},
-
-    :extension => {
-      :header => '.h',
-      :source => '.c',
-      :assembly => '.s',
-      :object => '.o',
-      :executable => ( SystemWrapper.windows? ? EXTENSION_WIN_EXE : EXTENSION_NONWIN_EXE ),
-      :map => '.map',
-      :list => '.lst',
-      :testpass => '.pass',
-      :testfail => '.fail',
-      :dependencies => '.d',
-    },
-
-    :unity => {
-      :vendor_path => CEEDLING_VENDOR,
-      :defines => []
-    },
-
-    :cmock => {
-      :vendor_path => CEEDLING_VENDOR,
-      :defines => [],
-      :includes => []
-    },
-
-    :cexception => {
-      :vendor_path => CEEDLING_VENDOR,
-      :defines => []
-    },
-
-    :test_runner => {
-      :includes => [],
-      :file_suffix => '_runner',
-    },
-
-    # all tools populated while building up config structure
-    :tools => {},
-
-    # empty argument lists for default tools
-    # (these can be overridden in project file to add arguments to tools without totally redefining tools)
-    :test_compiler => { :arguments => [] },
-    :test_linker   => { :arguments => [] },
-    :test_fixture  => {
-      :arguments => [],
-      :link_objects => [], # compiled object files to always be linked in (e.g. cmock.o if using mocks)
-    },
-    :test_includes_preprocessor  => { :arguments => [] },
-    :test_file_preprocessor      => { :arguments => [] },
-    :test_dependencies_generator => { :arguments => [] },
-    :release_compiler  => { :arguments => [] },
-    :release_linker    => { :arguments => [] },
-    :release_assembler => { :arguments => [] },
-    :release_dependencies_generator => { :arguments => [] },
-
-    :plugins => {
-      :load_paths => CEEDLING_PLUGINS,
-      :enabled => [],
-    }
-  }.freeze
-
-
-DEFAULT_TESTS_RESULTS_REPORT_TEMPLATE = %q{
-% ignored        = hash[:results][:counts][:ignored]
-% failed         = hash[:results][:counts][:failed]
-% stdout_count   = hash[:results][:counts][:stdout]
-% header_prepend = ((hash[:header].length > 0) ? "#{hash[:header]}: " : '')
-% banner_width   = 25 + header_prepend.length # widest message
-
-% if (stdout_count > 0)
-<%=@ceedling[:plugin_reportinator].generate_banner(header_prepend + 'TEST OUTPUT')%>
-%   hash[:results][:stdout].each do |string|
-%     string[:collection].each do |item|
-<%=string[:source][:path]%><%=File::SEPARATOR%><%=string[:source][:file]%>: "<%=item%>"
-%     end
-%   end
-
-% end
-% if (ignored > 0)
-<%=@ceedling[:plugin_reportinator].generate_banner(header_prepend + 'IGNORED TEST SUMMARY')%>
-%   hash[:results][:ignores].each do |ignore|
-%     ignore[:collection].each do |item|
-<%=ignore[:source][:path]%><%=File::SEPARATOR%><%=ignore[:source][:file]%>:<%=item[:line]%>:<%=item[:test]%>
-% if (item[:message].length > 0)
-: "<%=item[:message]%>"
-% else
-<%="\n"%>
-% end
-%     end
-%   end
-
-% end
-% if (failed > 0)
-<%=@ceedling[:plugin_reportinator].generate_banner(header_prepend + 'FAILED TEST SUMMARY')%>
-%   hash[:results][:failures].each do |failure|
-%     failure[:collection].each do |item|
-<%=failure[:source][:path]%><%=File::SEPARATOR%><%=failure[:source][:file]%>:<%=item[:line]%>:<%=item[:test]%>
-% if (item[:message].length > 0)
-: "<%=item[:message]%>"
-% else
-<%="\n"%>
-% end
-%     end
-%   end
-
-% end
-% total_string = hash[:results][:counts][:total].to_s
-% format_string = "%#{total_string.length}i"
-<%=@ceedling[:plugin_reportinator].generate_banner(header_prepend + 'OVERALL TEST SUMMARY')%>
-% if (hash[:results][:counts][:total] > 0)
-TESTED:  <%=hash[:results][:counts][:total].to_s%>
-PASSED:  <%=sprintf(format_string, hash[:results][:counts][:passed])%>
-FAILED:  <%=sprintf(format_string, failed)%>
-IGNORED: <%=sprintf(format_string, ignored)%>
-% else
-
-No tests executed.
-% end
-
-}
diff --git a/test/vendor/ceedling/lib/ceedling/dependinator.rb b/test/vendor/ceedling/lib/ceedling/dependinator.rb
deleted file mode 100644
index ebd123772..000000000
--- a/test/vendor/ceedling/lib/ceedling/dependinator.rb
+++ /dev/null
@@ -1,98 +0,0 @@
-
-class Dependinator
-
-  constructor :configurator, :project_config_manager, :test_includes_extractor, :file_path_utils, :rake_wrapper, :file_wrapper
-
-  def touch_force_rebuild_files
-    @file_wrapper.touch( @configurator.project_test_force_rebuild_filepath )
-    @file_wrapper.touch( @configurator.project_release_force_rebuild_filepath ) if (@configurator.project_release_build)
-  end
-
-
-
-  def load_release_object_deep_dependencies(dependencies_list)
-    dependencies_list.each do |dependencies_file|
-      if File.exists?(dependencies_file)
-        @rake_wrapper.load_dependencies( dependencies_file )
-      end
-    end
-  end
-
-
-  def enhance_release_file_dependencies(files)
-    files.each do |filepath|
-      @rake_wrapper[filepath].enhance( [@configurator.project_release_force_rebuild_filepath] ) if (@project_config_manager.release_config_changed)
-    end
-  end
-
-
-
-  def load_test_object_deep_dependencies(files_list)
-    dependencies_list = @file_path_utils.form_test_dependencies_filelist(files_list)
-    dependencies_list.each do |dependencies_file|
-      if File.exists?(dependencies_file)
-        @rake_wrapper.load_dependencies(dependencies_file)
-      end
-    end
-  end
-
-
-  def enhance_runner_dependencies(runner_filepath)
-    @rake_wrapper[runner_filepath].enhance( [@configurator.project_test_force_rebuild_filepath] ) if (@project_config_manager.test_config_changed ||
-      @project_config_manager.test_defines_changed)
-  end
-
-
-  def enhance_shallow_include_lists_dependencies(include_lists)
-    include_lists.each do |include_list_filepath|
-      @rake_wrapper[include_list_filepath].enhance( [@configurator.project_test_force_rebuild_filepath] ) if (@project_config_manager.test_config_changed ||
-        @project_config_manager.test_defines_changed)
-    end
-  end
-
-
-  def enhance_preprocesed_file_dependencies(files)
-    files.each do |filepath|
-      @rake_wrapper[filepath].enhance( [@configurator.project_test_force_rebuild_filepath] ) if (@project_config_manager.test_config_changed ||
-        @project_config_manager.test_defines_changed)
-    end
-  end
-
-
-  def enhance_mock_dependencies(mocks_list)
-    # if input configuration or ceedling changes, make sure these guys get rebuilt
-    mocks_list.each do |mock_filepath|
-      @rake_wrapper[mock_filepath].enhance( [@configurator.project_test_force_rebuild_filepath] ) if (@project_config_manager.test_config_changed ||
-        @project_config_manager.test_defines_changed)
-      @rake_wrapper[mock_filepath].enhance( @configurator.cmock_unity_helper )                    if (@configurator.cmock_unity_helper)
-    end
-  end
-
-
-  def enhance_dependencies_dependencies(dependencies)
-    dependencies.each do |dependencies_filepath|
-      @rake_wrapper[dependencies_filepath].enhance( [@configurator.project_test_force_rebuild_filepath] ) if (@project_config_manager.test_config_changed ||
-        @project_config_manager.test_defines_changed)
-    end
-  end
-
-
-  def enhance_test_build_object_dependencies(objects)
-    objects.each do |object_filepath|
-      @rake_wrapper[object_filepath].enhance( [@configurator.project_test_force_rebuild_filepath] ) if (@project_config_manager.test_config_changed ||
-        @project_config_manager.test_defines_changed)
-    end
-  end
-
-
-  def enhance_results_dependencies(result_filepath)
-    @rake_wrapper[result_filepath].enhance( [@configurator.project_test_force_rebuild_filepath] ) if (@project_config_manager.test_config_changed ||
-      @project_config_manager.test_defines_changed)
-  end
-
-
-  def setup_test_executable_dependencies(test, objects)
-    @rake_wrapper.create_file_task( @file_path_utils.form_test_executable_filepath(test), objects )
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/erb_wrapper.rb b/test/vendor/ceedling/lib/ceedling/erb_wrapper.rb
deleted file mode 100644
index 8d70b6d28..000000000
--- a/test/vendor/ceedling/lib/ceedling/erb_wrapper.rb
+++ /dev/null
@@ -1,9 +0,0 @@
-require 'erb'
-
-class ErbWrapper
-  def generate_file(template, data, output_file)
-    File.open(output_file, "w") do |f|
-      f << ERB.new(template, 0, "<>").result(binding)
-    end
-  end
-end
\ No newline at end of file
diff --git a/test/vendor/ceedling/lib/ceedling/file_finder.rb b/test/vendor/ceedling/lib/ceedling/file_finder.rb
deleted file mode 100644
index 53775b7bb..000000000
--- a/test/vendor/ceedling/lib/ceedling/file_finder.rb
+++ /dev/null
@@ -1,149 +0,0 @@
-require 'rubygems'
-require 'rake' # for adding ext() method to string
-require 'thread'
-
-
-class FileFinder
-  SEMAPHORE = Mutex.new
-
-  constructor :configurator, :file_finder_helper, :cacheinator, :file_path_utils, :file_wrapper, :yaml_wrapper
-
-  def prepare_search_sources
-    @all_test_source_and_header_file_collection =
-      @configurator.collection_all_tests +
-      @configurator.collection_all_source +
-      @configurator.collection_all_headers
-  end
-
-
-  def find_header_file(mock_file)
-    header = File.basename(mock_file).sub(/#{@configurator.cmock_mock_prefix}/, '').ext(@configurator.extension_header)
-
-    found_path = @file_finder_helper.find_file_in_collection(header, @configurator.collection_all_headers, :error)
-
-    return found_path
-  end
-
-
-  def find_header_input_for_mock_file(mock_file)
-    found_path = find_header_file(mock_file)
-    mock_input = found_path
-
-    if (@configurator.project_use_test_preprocessor)
-      mock_input = @cacheinator.diff_cached_test_file( @file_path_utils.form_preprocessed_file_filepath( found_path ) )
-    end
-
-    return mock_input
-  end
-
-
-  def find_source_from_test(test, complain)
-    test_prefix  = @configurator.project_test_file_prefix
-    source_paths = @configurator.collection_all_source
-
-    source = File.basename(test).sub(/#{test_prefix}/, '')
-
-    # we don't blow up if a test file has no corresponding source file
-    return @file_finder_helper.find_file_in_collection(source, source_paths, complain)
-  end
-
-
-  def find_test_from_runner_path(runner_path)
-    extension_source = @configurator.extension_source
-
-    test_file = File.basename(runner_path).sub(/#{@configurator.test_runner_file_suffix}#{'\\'+extension_source}/, extension_source)
-
-    found_path = @file_finder_helper.find_file_in_collection(test_file, @configurator.collection_all_tests, :error)
-
-    return found_path
-  end
-
-
-  def find_test_input_for_runner_file(runner_path)
-    found_path   = find_test_from_runner_path(runner_path)
-    runner_input = found_path
-
-    if (@configurator.project_use_test_preprocessor)
-      runner_input = @cacheinator.diff_cached_test_file( @file_path_utils.form_preprocessed_file_filepath( found_path ) )
-    end
-
-    return runner_input
-  end
-
-
-  def find_test_from_file_path(file_path)
-    test_file = File.basename(file_path).ext(@configurator.extension_source)
-
-    found_path = @file_finder_helper.find_file_in_collection(test_file, @configurator.collection_all_tests, :error)
-
-    return found_path
-  end
-
-
-  def find_test_or_source_or_header_file(file_path)
-    file = File.basename(file_path)
-    return @file_finder_helper.find_file_in_collection(file, @all_test_source_and_header_file_collection, :error)
-  end
-
-
-  def find_compilation_input_file(file_path, complain=:error, release=false)
-    found_file = nil
-
-    source_file = File.basename(file_path).ext(@configurator.extension_source)
-
-    # We only collect files that already exist when we start up.
-    # FileLists can produce undesired results for dynamically generated files depending on when they're accessed.
-    # So collect mocks and runners separately and right now.
-
-    SEMAPHORE.synchronize {
-
-      if (source_file =~ /#{@configurator.test_runner_file_suffix}/)
-        found_file =
-          @file_finder_helper.find_file_in_collection(
-            source_file,
-            @file_wrapper.directory_listing( File.join(@configurator.project_test_runners_path, '*') ),
-            complain)
-
-      elsif (@configurator.project_use_mocks and (source_file =~ /#{@configurator.cmock_mock_prefix}/))
-        found_file =
-          @file_finder_helper.find_file_in_collection(
-            source_file,
-            @file_wrapper.directory_listing( File.join(@configurator.cmock_mock_path, '*') ),
-            complain)
-
-      elsif release
-        found_file =
-          @file_finder_helper.find_file_in_collection(
-            source_file,
-            @configurator.collection_release_existing_compilation_input,
-            complain)
-      else
-        temp_complain = (defined?(TEST_BUILD_USE_ASSEMBLY) && TEST_BUILD_USE_ASSEMBLY) ? :ignore : complain
-        found_file =
-          @file_finder_helper.find_file_in_collection(
-            source_file,
-            @configurator.collection_all_existing_compilation_input,
-            temp_complain)
-        found_file ||= find_assembly_file(file_path, false) if (defined?(TEST_BUILD_USE_ASSEMBLY) && TEST_BUILD_USE_ASSEMBLY)
-      end
-    }
-    return found_file
-  end
-
-
-  def find_source_file(file_path, complain)
-    source_file = File.basename(file_path).ext(@configurator.extension_source)
-    return @file_finder_helper.find_file_in_collection(source_file, @configurator.collection_all_source, complain)
-  end
-
-
-  def find_assembly_file(file_path, complain = :error)
-    assembly_file = File.basename(file_path).ext(@configurator.extension_assembly)
-    return @file_finder_helper.find_file_in_collection(assembly_file, @configurator.collection_all_assembly, complain)
-  end
-
-  def find_file_from_list(file_path, file_list, complain)
-    return @file_finder_helper.find_file_in_collection(file_path, file_list, complain)
-  end
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/file_finder_helper.rb b/test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
deleted file mode 100644
index 0a31b44bd..000000000
--- a/test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
+++ /dev/null
@@ -1,54 +0,0 @@
-require 'fileutils'
-require 'ceedling/constants' # for Verbosity enumeration
-
-class FileFinderHelper
-
-  constructor :streaminator
-  
-  
-  def find_file_in_collection(file_name, file_list, complain, extra_message="")
-    file_to_find = nil
-    
-    file_list.each do |item|
-      base_file = File.basename(item)
-
-      # case insensitive comparison
-      if (base_file.casecmp(file_name) == 0)
-        # case sensitive check
-        if (base_file == file_name)
-          file_to_find = item
-          break
-        else
-          blow_up(file_name, "However, a filename having different capitalization was found: '#{item}'.")
-        end
-      end
-      
-    end
-    
-    case (complain)
-      when :error then blow_up(file_name, extra_message) if (file_to_find.nil?)
-      when :warn  then gripe(file_name, extra_message)   if (file_to_find.nil?)
-      #when :ignore then      
-    end
-    
-    return file_to_find
-  end
-
-  private
-  
-  def blow_up(file_name, extra_message="")
-    error = "ERROR: Found no file '#{file_name}' in search paths."
-    error += ' ' if (extra_message.length > 0)
-    @streaminator.stderr_puts(error + extra_message, Verbosity::ERRORS)
-    raise
-  end
-  
-  def gripe(file_name, extra_message="")
-    warning = "WARNING: Found no file '#{file_name}' in search paths."
-    warning += ' ' if (extra_message.length > 0)
-    @streaminator.stderr_puts(warning + extra_message, Verbosity::COMPLAIN)
-  end
-
-end
-
-
diff --git a/test/vendor/ceedling/lib/ceedling/file_path_utils.rb b/test/vendor/ceedling/lib/ceedling/file_path_utils.rb
deleted file mode 100644
index 607039fd5..000000000
--- a/test/vendor/ceedling/lib/ceedling/file_path_utils.rb
+++ /dev/null
@@ -1,200 +0,0 @@
-require 'rubygems'
-require 'rake' # for ext()
-require 'fileutils'
-require 'ceedling/system_wrapper'
-
-# global utility methods (for plugins, project files, etc.)
-def ceedling_form_filepath(destination_path, original_filepath, new_extension=nil)
-  filename = File.basename(original_filepath)
-  filename.replace(filename.ext(new_extension)) if (!new_extension.nil?)
-  return File.join( destination_path.gsub(/\\/, '/'), filename )
-end
-
-class FilePathUtils
-
-  GLOB_MATCHER = /[\*\?\{\}\[\]]/
-
-  constructor :configurator, :file_wrapper
-
-
-  ######### class methods ##########
-
-  # standardize path to use '/' path separator & have no trailing path separator
-  def self.standardize(path)
-    path.strip!
-    path.gsub!(/\\/, '/')
-    path.chomp!('/')
-    return path
-  end
-
-  def self.os_executable_ext(executable)
-    return executable.ext('.exe') if SystemWrapper.windows?
-    return executable
-  end
-
-  # extract directory path from between optional add/subtract aggregation modifiers and up to glob specifiers
-  # note: slightly different than File.dirname in that /files/foo remains /files/foo and does not become /files
-  def self.extract_path(path)
-    path = path.sub(/^(\+|-):/, '')
-
-    # find first occurrence of path separator followed by directory glob specifier: *, ?, {, }, [, ]
-    find_index = (path =~ GLOB_MATCHER)
-
-    # no changes needed (lop off final path separator)
-    return path.chomp('/') if (find_index.nil?)
-
-    # extract up to first glob specifier
-    path = path[0..(find_index-1)]
-
-    # lop off everything up to and including final path separator
-    find_index = path.rindex('/')
-    return path[0..(find_index-1)] if (not find_index.nil?)
-
-    # return string up to first glob specifier if no path separator found
-    return path
-  end
-
-  # return whether the given path is to be aggregated (no aggregation modifier defaults to same as +:)
-  def self.add_path?(path)
-    return (path =~ /^-:/).nil?
-  end
-
-  # get path (and glob) lopping off optional +: / -: prefixed aggregation modifiers
-  def self.extract_path_no_aggregation_operators(path)
-    return path.sub(/^(\+|-):/, '')
-  end
-
-  # all the globs that may be in a path string work fine with one exception;
-  # to recurse through all subdirectories, the glob is dir/**/** but our paths use
-  # convention of only dir/**
-  def self.reform_glob(path)
-    return path if (path =~ /\/\*\*$/).nil?
-    return path + '/**'
-  end
-
-  ######### instance methods ##########
-
-  def form_temp_path(filepath, prefix='')
-    return File.join( @configurator.project_temp_path, prefix + File.basename(filepath) )
-  end
-
-  ### release ###
-  def form_release_build_cache_path(filepath)
-    return File.join( @configurator.project_release_build_cache_path, File.basename(filepath) )
-  end
-
-  def form_release_dependencies_filepath(filepath)
-    return File.join( @configurator.project_release_dependencies_path, File.basename(filepath).ext(@configurator.extension_dependencies) )
-  end
-
-  def form_release_build_c_object_filepath(filepath)
-    return File.join( @configurator.project_release_build_output_c_path, File.basename(filepath).ext(@configurator.extension_object) )
-  end
-
-  def form_release_build_asm_object_filepath(filepath)
-    return File.join( @configurator.project_release_build_output_asm_path, File.basename(filepath).ext(@configurator.extension_object) )
-  end
-
-  def form_release_build_c_objects_filelist(files)
-    return (@file_wrapper.instantiate_file_list(files)).pathmap("#{@configurator.project_release_build_output_c_path}/%n#{@configurator.extension_object}")
-  end
-
-  def form_release_build_asm_objects_filelist(files)
-    return (@file_wrapper.instantiate_file_list(files)).pathmap("#{@configurator.project_release_build_output_asm_path}/%n#{@configurator.extension_object}")
-  end
-
-  def form_release_build_c_list_filepath(filepath)
-    return File.join( @configurator.project_release_build_output_c_path, File.basename(filepath).ext(@configurator.extension_list) )
-  end
-
-  def form_release_dependencies_filelist(files)
-    return (@file_wrapper.instantiate_file_list(files)).pathmap("#{@configurator.project_release_dependencies_path}/%n#{@configurator.extension_dependencies}")
-  end
-
-  ### tests ###
-  def form_test_build_cache_path(filepath)
-    return File.join( @configurator.project_test_build_cache_path, File.basename(filepath) )
-  end
-
-  def form_test_dependencies_filepath(filepath)
-    return File.join( @configurator.project_test_dependencies_path, File.basename(filepath).ext(@configurator.extension_dependencies) )
-  end
-
-  def form_pass_results_filepath(filepath)
-    return File.join( @configurator.project_test_results_path, File.basename(filepath).ext(@configurator.extension_testpass) )
-  end
-
-  def form_fail_results_filepath(filepath)
-    return File.join( @configurator.project_test_results_path, File.basename(filepath).ext(@configurator.extension_testfail) )
-  end
-
-  def form_runner_filepath_from_test(filepath)
-    return File.join( @configurator.project_test_runners_path, File.basename(filepath, @configurator.extension_source)) + @configurator.test_runner_file_suffix + @configurator.extension_source
-  end
-
-  def form_test_filepath_from_runner(filepath)
-    return filepath.sub(/#{TEST_RUNNER_FILE_SUFFIX}/, '')
-  end
-
-  def form_runner_object_filepath_from_test(filepath)
-    return (form_test_build_c_object_filepath(filepath)).sub(/(#{@configurator.extension_object})$/, "#{@configurator.test_runner_file_suffix}\\1")
-  end
-
-  def form_test_build_c_object_filepath(filepath)
-    return File.join( @configurator.project_test_build_output_c_path, File.basename(filepath).ext(@configurator.extension_object) )
-  end
-
-  def form_test_build_asm_object_filepath(filepath)
-    return File.join( @configurator.project_test_build_output_asm_path, File.basename(filepath).ext(@configurator.extension_object) )
-  end
-
-  def form_test_executable_filepath(filepath)
-    return File.join( @configurator.project_test_build_output_path, File.basename(filepath).ext(@configurator.extension_executable) )
-  end
-
-  def form_test_build_map_filepath(filepath)
-    return File.join( @configurator.project_test_build_output_path, File.basename(filepath).ext(@configurator.extension_map) )
-  end
-
-  def form_test_build_list_filepath(filepath)
-    return File.join( @configurator.project_test_build_output_path, File.basename(filepath).ext(@configurator.extension_list) )
-  end
-
-  def form_preprocessed_file_filepath(filepath)
-    return File.join( @configurator.project_test_preprocess_files_path, File.basename(filepath) )
-  end
-
-  def form_preprocessed_includes_list_filepath(filepath)
-    return File.join( @configurator.project_test_preprocess_includes_path, File.basename(filepath) )
-  end
-
-  def form_test_build_objects_filelist(sources)
-    return (@file_wrapper.instantiate_file_list(sources)).pathmap("#{@configurator.project_test_build_output_c_path}/%n#{@configurator.extension_object}")
-  end
-
-  def form_preprocessed_mockable_headers_filelist(mocks)
-    list = @file_wrapper.instantiate_file_list(mocks)
-    headers = list.map do |file|
-      module_name = File.basename(file).sub(/^#{@configurator.cmock_mock_prefix}/, '').sub(/\.[a-zA-Z]+$/,'')
-      "#{@configurator.project_test_preprocess_files_path}/#{module_name}#{@configurator.extension_header}"
-    end
-    return headers
-  end
-
-  def form_mocks_source_filelist(mocks)
-    list = (@file_wrapper.instantiate_file_list(mocks))
-    sources = list.map{|file| "#{@configurator.cmock_mock_path}/#{file}#{@configurator.extension_source}"}
-    return sources
-  end
-
-  def form_test_dependencies_filelist(files)
-    list = @file_wrapper.instantiate_file_list(files)
-    return list.pathmap("#{@configurator.project_test_dependencies_path}/%n#{@configurator.extension_dependencies}")
-  end
-
-  def form_pass_results_filelist(path, files)
-    list = @file_wrapper.instantiate_file_list(files)
-    return list.pathmap("#{path}/%n#{@configurator.extension_testpass}")
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/file_system_utils.rb b/test/vendor/ceedling/lib/ceedling/file_system_utils.rb
deleted file mode 100644
index 97e5856fb..000000000
--- a/test/vendor/ceedling/lib/ceedling/file_system_utils.rb
+++ /dev/null
@@ -1,69 +0,0 @@
-require 'rubygems'
-require 'rake'
-require 'set'
-require 'fileutils'
-require 'ceedling/file_path_utils'
-
-
-class FileSystemUtils
-  
-  constructor :file_wrapper
-
-  # build up path list from input of one or more strings or arrays of (+/-) paths & globs
-  def collect_paths(*paths)
-    raw   = []  # all paths and globs
-    plus  = Set.new # all paths to expand and add
-    minus = Set.new # all paths to remove from plus set
-    
-    # assemble all globs and simple paths, reforming our glob notation to ruby globs
-    paths.each do |paths_container|
-      case (paths_container)
-        when String then raw << (FilePathUtils::reform_glob(paths_container))
-        when Array  then paths_container.each {|path| raw << (FilePathUtils::reform_glob(path))}
-        else raise "Don't know how to handle #{paths_container.class}"
-      end
-    end
-
-    # iterate through each path and glob
-    raw.each do |path|
-    
-      dirs = []  # container for only (expanded) paths
-    
-      # if a glob, expand it and slurp up all non-file paths
-      if path.include?('*')
-        # grab base directory only if globs are snug up to final path separator
-        if (path =~ /\/\*+$/)
-          dirs << FilePathUtils.extract_path(path)
-        end
-        
-        # grab expanded sub-directory globs
-        expanded = @file_wrapper.directory_listing( FilePathUtils.extract_path_no_aggregation_operators(path) )
-        expanded.each do |entry|
-          dirs << entry if @file_wrapper.directory?(entry)
-        end
-        
-      # else just grab simple path
-      # note: we could just run this through glob expansion but such an
-      #       approach doesn't handle a path not yet on disk)
-      else
-        dirs << FilePathUtils.extract_path_no_aggregation_operators(path)
-      end
-      
-      # add dirs to the appropriate set based on path aggregation modifier if present
-      FilePathUtils.add_path?(path) ? plus.merge(dirs) : minus.merge(dirs)
-    end
-
-    return (plus - minus).to_a.uniq
-  end
-
-
-  # given a file list, add to it or remove from it
-  def revise_file_list(list, revisions)
-    revisions.each do |revision|
-      # include or exclude file or glob to file list
-      file = FilePathUtils.extract_path_no_aggregation_operators( revision )
-      FilePathUtils.add_path?(revision) ? list.include(file) : list.exclude(file)
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb b/test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb
deleted file mode 100644
index 807cbd23f..000000000
--- a/test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb
+++ /dev/null
@@ -1,10 +0,0 @@
-
-class FileSystemWrapper
-
-  def cd(path)
-    FileUtils.cd path do
-      yield
-    end
-  end
-
-end
\ No newline at end of file
diff --git a/test/vendor/ceedling/lib/ceedling/file_wrapper.rb b/test/vendor/ceedling/lib/ceedling/file_wrapper.rb
deleted file mode 100644
index 1680ca520..000000000
--- a/test/vendor/ceedling/lib/ceedling/file_wrapper.rb
+++ /dev/null
@@ -1,83 +0,0 @@
-require 'rubygems'
-require 'rake' # for FileList
-require 'fileutils'
-require 'ceedling/constants'
-
-
-class FileWrapper
-
-  def get_expanded_path(path)
-    return File.expand_path(path)
-  end
-
-  def basename(path, extension=nil)
-    return File.basename(path, extension) if extension
-    return File.basename(path)
-  end
-
-  def exist?(filepath)
-    return true if (filepath == NULL_FILE_PATH)
-    return File.exist?(filepath)
-  end
-
-  def directory?(path)
-    return File.directory?(path)
-  end
-
-  def dirname(path)
-    return File.dirname(path)
-  end
-
-  def directory_listing(glob)
-    return Dir.glob(glob, File::FNM_PATHNAME)
-  end
-
-  def rm_f(filepath, options={})
-    FileUtils.rm_f(filepath, options)
-  end
-
-  def rm_r(filepath, options={})
-    FileUtils.rm_r(filepath, options={})
-  end
-
-  def cp(source, destination, options={})
-    FileUtils.cp(source, destination, options)
-  end
-
-  def compare(from, to)
-    return FileUtils.compare_file(from, to)
-  end
-
-  def open(filepath, flags)
-    File.open(filepath, flags) do |file|
-      yield(file)
-    end
-  end
-
-  def read(filepath)
-    return File.read(filepath)
-  end
-
-  def touch(filepath, options={})
-    FileUtils.touch(filepath, options)
-  end
-
-  def write(filepath, contents, flags='w')
-    File.open(filepath, flags) do |file|
-      file.write(contents)
-    end
-  end
-
-  def readlines(filepath)
-    return File.readlines(filepath)
-  end
-
-  def instantiate_file_list(files=[])
-    return FileList.new(files)
-  end
-
-  def mkdir(folder)
-    return FileUtils.mkdir_p(folder)
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/flaginator.rb b/test/vendor/ceedling/lib/ceedling/flaginator.rb
deleted file mode 100644
index 31d62c46a..000000000
--- a/test/vendor/ceedling/lib/ceedling/flaginator.rb
+++ /dev/null
@@ -1,74 +0,0 @@
-require 'rubygems'
-require 'rake' # for ext()
-require 'fileutils'
-require 'ceedling/constants'
-
-
-# :flags:
-#   :release:
-#     :compile:
-#       :'test_.+'
-#         - -pedantic   # add '-pedantic' to every test file
-#       :*:          # add '-foo' to compilation of all files not main.c
-#         - -foo
-#       :main:       # add '-Wall' to compilation of main.c
-#         - -Wall
-#   :test:
-#     :link:
-#       :test_main:  # add '--bar --baz' to linking of test_main.exe
-#         - --bar
-#         - --baz
-
-def partition(hash, &predicate)
-  hash.partition(&predicate).map(&:to_h)
-end
-
-class Flaginator
-
-  constructor :configurator
-
-  def get_flag(hash, file_name)
-    file_key = file_name.to_sym
-   
-    # 1. try literals
-    literals, magic = partition(hash) { |k, v| k.to_s =~ /^\w+$/ }  
-    return literals[file_key] if literals.include?(file_key)
-    
-    any, regex = partition(magic) { |k, v| (k == :'*') || (k == :'.*')  } # glob or regex wild card
-    
-    # 2. try regexes
-    find_res = regex.find { |k, v| file_name =~ /^#{k.to_s}$/ }
-    return find_res[1] if find_res
-    
-    # 3. try anything
-    find_res = any.find { |k, v| file_name =~ /.*/ }
-    return find_res[1] if find_res
-      
-    # 4. well, we've tried
-    return []
-  end
-  
-  def flag_down( operation, context, file )
-    # create configurator accessor method
-    accessor = ('flags_' + context.to_s).to_sym
-
-    # create simple filename key from whatever filename provided
-    file_name = File.basename( file ).ext('')
-    file_key = File.basename( file ).ext('').to_sym
-
-    # if no entry in configuration for flags for this context, bail out
-    return [] if not @configurator.respond_to?( accessor )
-
-    # get flags sub hash associated with this context
-    flags = @configurator.send( accessor )
-
-    # if operation not represented in flags hash, bail out
-    return [] if not flags.include?( operation )
-
-    # redefine flags to sub hash associated with the operation
-    flags = flags[operation]
-
-    return get_flag(flags, file_name)
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/generator.rb b/test/vendor/ceedling/lib/ceedling/generator.rb
deleted file mode 100644
index 828a0c025..000000000
--- a/test/vendor/ceedling/lib/ceedling/generator.rb
+++ /dev/null
@@ -1,183 +0,0 @@
-require 'ceedling/constants'
-
-class Generator
-
-  constructor :configurator,
-              :generator_helper,
-              :preprocessinator,
-              :cmock_builder,
-              :generator_test_runner,
-              :generator_test_results,
-              :flaginator,
-              :test_includes_extractor,
-              :tool_executor,
-              :file_finder,
-              :file_path_utils,
-              :streaminator,
-              :plugin_manager,
-              :file_wrapper
-
-
-  def generate_shallow_includes_list(context, file)
-    @streaminator.stdout_puts("Generating include list for #{File.basename(file)}...", Verbosity::NORMAL)
-    @preprocessinator.preprocess_shallow_includes(file)
-  end
-
-  def generate_preprocessed_file(context, file)
-    @streaminator.stdout_puts("Preprocessing #{File.basename(file)}...", Verbosity::NORMAL)
-    @preprocessinator.preprocess_file(file)
-  end
-
-  def generate_dependencies_file(tool, context, source, object, dependencies)
-    @streaminator.stdout_puts("Generating dependencies for #{File.basename(source)}...", Verbosity::NORMAL)
-
-    command =
-      @tool_executor.build_command_line(
-        tool,
-        [], # extra per-file command line parameters
-        source,
-        dependencies,
-        object)
-
-    @tool_executor.exec( command[:line], command[:options] )
-  end
-
-  def generate_mock(context, header_filepath)
-    arg_hash = {:header_file => header_filepath, :context => context}
-    @plugin_manager.pre_mock_generate( arg_hash )
-
-    begin
-      @cmock_builder.cmock.setup_mocks( arg_hash[:header_file] )
-    rescue
-      raise
-    ensure
-      @plugin_manager.post_mock_generate( arg_hash )
-    end
-  end
-
-  # test_filepath may be either preprocessed test file or original test file
-  def generate_test_runner(context, test_filepath, runner_filepath)
-    arg_hash = {:context => context, :test_file => test_filepath, :runner_file => runner_filepath}
-    @plugin_manager.pre_runner_generate(arg_hash)
-
-    # collect info we need
-    module_name = File.basename(arg_hash[:test_file])
-    test_cases  = @generator_test_runner.find_test_cases( @file_finder.find_test_from_runner_path(runner_filepath) )
-    mock_list   = @test_includes_extractor.lookup_raw_mock_list(arg_hash[:test_file])
-
-    @streaminator.stdout_puts("Generating runner for #{module_name}...", Verbosity::NORMAL)
-
-    test_file_includes = [] # Empty list for now, since apparently unused
-
-    # build runner file
-    begin
-      @generator_test_runner.generate(module_name, runner_filepath, test_cases, mock_list, test_file_includes)
-    rescue
-      raise
-    ensure
-      @plugin_manager.post_runner_generate(arg_hash)
-    end
-  end
-
-  def generate_object_file(tool, operation, context, source, object, list='', dependencies='')
-    shell_result = {}
-    arg_hash = {:tool => tool, :operation => operation, :context => context, :source => source, :object => object, :list => list, :dependencies => dependencies}
-    @plugin_manager.pre_compile_execute(arg_hash)
-
-    @streaminator.stdout_puts("Compiling #{File.basename(arg_hash[:source])}...", Verbosity::NORMAL)
-    command =
-      @tool_executor.build_command_line( arg_hash[:tool],
-                                         @flaginator.flag_down( operation, context, source ),
-                                         arg_hash[:source],
-                                         arg_hash[:object],
-                                         arg_hash[:list],
-                                         arg_hash[:dependencies])
-
-    @streaminator.stdout_puts("Command: #{command}", Verbosity::DEBUG)
-
-    begin
-      shell_result = @tool_executor.exec( command[:line], command[:options] )
-    rescue ShellExecutionException => ex
-      shell_result = ex.shell_result
-      raise ex
-    ensure
-      arg_hash[:shell_result] = shell_result
-      @plugin_manager.post_compile_execute(arg_hash)
-    end
-  end
-
-  def generate_executable_file(tool, context, objects, executable, map='', libraries=[])
-    shell_result = {}
-    arg_hash = { :tool => tool,
-                 :context => context,
-                 :objects => objects,
-                 :executable => executable,
-                 :map => map,
-                 :libraries => libraries
-               }
-
-    @plugin_manager.pre_link_execute(arg_hash)
-
-    @streaminator.stdout_puts("Linking #{File.basename(arg_hash[:executable])}...", Verbosity::NORMAL)
-    command =
-      @tool_executor.build_command_line( arg_hash[:tool],
-                                         @flaginator.flag_down( OPERATION_LINK_SYM, context, executable ),
-                                         arg_hash[:objects],
-                                         arg_hash[:executable],
-                                         arg_hash[:map],
-                                         arg_hash[:libraries]
-                                       )
-    @streaminator.stdout_puts("Command: #{command}", Verbosity::DEBUG)
-
-    begin
-      shell_result = @tool_executor.exec( command[:line], command[:options] )
-    rescue ShellExecutionException => ex
-      notice =    "\n" +
-                  "NOTICE: If the linker reports missing symbols, the following may be to blame:\n" +
-                  "  1. Test lacks #include statements corresponding to needed source files.\n" +
-                  "  2. Project search paths do not contain source files corresponding to #include statements in the test.\n"
-
-      if (@configurator.project_use_mocks)
-        notice += "  3. Test does not #include needed mocks.\n\n"
-      else
-        notice += "\n"
-      end
-
-      @streaminator.stderr_puts(notice, Verbosity::COMPLAIN)
-      shell_result = ex.shell_result
-      raise ''
-    ensure
-      arg_hash[:shell_result] = shell_result
-      @plugin_manager.post_link_execute(arg_hash)
-    end
-  end
-
-  def generate_test_results(tool, context, executable, result)
-    arg_hash = {:tool => tool, :context => context, :executable => executable, :result_file => result}
-    @plugin_manager.pre_test_fixture_execute(arg_hash)
-
-    @streaminator.stdout_puts("Running #{File.basename(arg_hash[:executable])}...", Verbosity::NORMAL)
-
-    # Unity's exit code is equivalent to the number of failed tests, so we tell @tool_executor not to fail out if there are failures
-    # so that we can run all tests and collect all results
-    command = @tool_executor.build_command_line(arg_hash[:tool], [], arg_hash[:executable])
-    @streaminator.stdout_puts("Command: #{command}", Verbosity::DEBUG)
-    command[:options][:boom] = false
-    shell_result = @tool_executor.exec( command[:line], command[:options] )
-
-    #Don't Let The Failure Count Make Us Believe Things Aren't Working
-    shell_result[:exit_code] = 0
-    @generator_helper.test_results_error_handler(executable, shell_result)
-
-    processed = @generator_test_results.process_and_write_results( shell_result,
-                                                                   arg_hash[:result_file],
-                                                                   @file_finder.find_test_from_file_path(arg_hash[:executable]) )
-
-    arg_hash[:result_file]  = processed[:result_file]
-    arg_hash[:results]      = processed[:results]
-    arg_hash[:shell_result] = shell_result # for raw output display if no plugins for formatted display
-
-    @plugin_manager.post_test_fixture_execute(arg_hash)
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/generator_helper.rb b/test/vendor/ceedling/lib/ceedling/generator_helper.rb
deleted file mode 100644
index 343156092..000000000
--- a/test/vendor/ceedling/lib/ceedling/generator_helper.rb
+++ /dev/null
@@ -1,40 +0,0 @@
-require 'ceedling/constants'
-
-
-class GeneratorHelper
-
-  constructor :streaminator
-
-
-  def test_results_error_handler(executable, shell_result)
-    notice = ''
-    error  = false
-    
-    if (shell_result[:output].nil? or shell_result[:output].strip.empty?)
-      error = true
-      # mirror style of generic tool_executor failure output
-      notice  = "\n" +
-                "ERROR: Test executable \"#{File.basename(executable)}\" failed.\n" +
-                "> Produced no output to $stdout.\n"
-    elsif ((shell_result[:output] =~ TEST_STDOUT_STATISTICS_PATTERN).nil?)
-      error = true
-      # mirror style of generic tool_executor failure output
-      notice  = "\n" +
-                "ERROR: Test executable \"#{File.basename(executable)}\" failed.\n" +
-                "> Produced no final test result counts in $stdout:\n" +
-                "#{shell_result[:output].strip}\n"
-    end
-    
-    if (error)
-      # since we told the tool executor to ignore the exit code, handle it explicitly here
-      notice += "> And exited with status: [#{shell_result[:exit_code]}] (count of failed tests).\n" if (shell_result[:exit_code] != nil)
-      notice += "> And then likely crashed.\n"                                                       if (shell_result[:exit_code] == nil)
-
-      notice += "> This is often a symptom of a bad memory access in source or test code.\n\n"
-
-      @streaminator.stderr_puts(notice, Verbosity::COMPLAIN)
-      raise      
-    end
-  end
-  
-end
diff --git a/test/vendor/ceedling/lib/ceedling/generator_test_results.rb b/test/vendor/ceedling/lib/ceedling/generator_test_results.rb
deleted file mode 100644
index 1d0c5201f..000000000
--- a/test/vendor/ceedling/lib/ceedling/generator_test_results.rb
+++ /dev/null
@@ -1,89 +0,0 @@
-require 'rubygems'
-require 'rake' # for .ext()
-require 'ceedling/constants'
-
-class GeneratorTestResults
-
-  constructor :configurator, :generator_test_results_sanity_checker, :yaml_wrapper
-
-  def process_and_write_results(unity_shell_result, results_file, test_file)
-    output_file = results_file
-
-    results = get_results_structure
-
-    results[:source][:path] = File.dirname(test_file)
-    results[:source][:file] = File.basename(test_file)
-    results[:time] = unity_shell_result[:time] unless unity_shell_result[:time].nil?
-
-    # process test statistics
-    if (unity_shell_result[:output] =~ TEST_STDOUT_STATISTICS_PATTERN)
-      results[:counts][:total] = $1.to_i
-      results[:counts][:failed] = $2.to_i
-      results[:counts][:ignored] = $3.to_i
-      results[:counts][:passed] = (results[:counts][:total] - results[:counts][:failed] - results[:counts][:ignored])
-    end
-
-    # remove test statistics lines
-    output_string = unity_shell_result[:output].sub(TEST_STDOUT_STATISTICS_PATTERN, '')
-
-    output_string.lines do |line|
-      # process unity output
-      case line
-      when /(:IGNORE)/
-        elements = extract_line_elements(line, results[:source][:file])
-        results[:ignores] << elements[0]
-        results[:stdout] << elements[1] if (!elements[1].nil?)
-      when /(:PASS$)/
-        elements = extract_line_elements(line, results[:source][:file])
-        results[:successes] << elements[0]
-        results[:stdout] << elements[1] if (!elements[1].nil?)
-      when /(:FAIL)/
-        elements = extract_line_elements(line, results[:source][:file])
-        results[:failures] << elements[0]
-        results[:stdout] << elements[1] if (!elements[1].nil?)
-      else # collect up all other
-        results[:stdout] << line.chomp
-      end
-    end
-
-    @generator_test_results_sanity_checker.verify(results, unity_shell_result[:exit_code])
-
-    output_file = results_file.ext(@configurator.extension_testfail) if (results[:counts][:failed] > 0)
-
-    @yaml_wrapper.dump(output_file, results)
-
-    return { :result_file => output_file, :result => results }
-  end
-
-  private
-
-  def get_results_structure
-    return {
-      :source    => {:path => '', :file => ''},
-      :successes => [],
-      :failures  => [],
-      :ignores   => [],
-      :counts    => {:total => 0, :passed => 0, :failed => 0, :ignored  => 0},
-      :stdout    => [],
-      :time      => 0.0
-      }
-  end
-
-  def extract_line_elements(line, filename)
-    # handle anything preceding filename in line as extra output to be collected
-    stdout = nil
-    stdout_regex = /(.+)#{Regexp.escape(filename)}.+/i
-
-    if (line =~ stdout_regex)
-      stdout = $1.clone
-      line.sub!(/#{Regexp.escape(stdout)}/, '')
-    end
-
-    # collect up test results minus and extra output
-    elements = (line.strip.split(':'))[1..-1]
-
-    return {:test => elements[1], :line => elements[0].to_i, :message => (elements[3..-1].join(':')).strip}, stdout if elements.size >= 3
-    return {:test => '???', :line => -1, :message => nil} #fallback safe option. TODO better handling
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb b/test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb
deleted file mode 100644
index 0b518325b..000000000
--- a/test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb
+++ /dev/null
@@ -1,65 +0,0 @@
-require 'rubygems'
-require 'rake' # for ext() method
-require 'ceedling/constants'
-
-
-class GeneratorTestResultsSanityChecker
-
-  constructor :configurator, :streaminator
-  
-  def verify(results, unity_exit_code)
-  
-    # do no sanity checking if it's disabled
-    return if (@configurator.sanity_checks == TestResultsSanityChecks::NONE)
-    raise "results nil or empty" if results.nil? || results.empty?
-
-    ceedling_ignores_count   = results[:ignores].size 
-    ceedling_failures_count  = results[:failures].size
-    ceedling_tests_summation = (ceedling_ignores_count + ceedling_failures_count + results[:successes].size)
-
-    # Exit code handling is not a sanity check that can always be performed because 
-    # command line simulators may or may not pass through Unity's exit code
-    if (@configurator.sanity_checks >= TestResultsSanityChecks::THOROUGH)
-      # many platforms limit exit codes to a maximum of 255
-      if ((ceedling_failures_count != unity_exit_code) and (unity_exit_code < 255))
-        sanity_check_warning(results[:source][:file], "Unity's exit code (#{unity_exit_code}) does not match Ceedling's summation of failed test cases (#{ceedling_failures_count}).")
-      end
-      
-      if ((ceedling_failures_count < 255) and (unity_exit_code == 255))
-        sanity_check_warning(results[:source][:file], "Ceedling's summation of failed test cases (#{ceedling_failures_count}) is less than Unity's exit code (255 or more).")
-      end
-    end
-    
-    if (ceedling_ignores_count != results[:counts][:ignored])
-      sanity_check_warning(results[:source][:file], "Unity's final ignore count (#{results[:counts][:ignored]}) does not match Ceedling's summation of ignored test cases (#{ceedling_ignores_count}).")
-    end
-    
-    if (ceedling_failures_count != results[:counts][:failed])
-      sanity_check_warning(results[:source][:file], "Unity's final fail count (#{results[:counts][:failed]}) does not match Ceedling's summation of failed test cases (#{ceedling_failures_count}).")
-    end
-
-    if (ceedling_tests_summation != results[:counts][:total])
-      sanity_check_warning(results[:source][:file], "Unity's final test count (#{results[:counts][:total]}) does not match Ceedling's summation of all test cases (#{ceedling_tests_summation}).")
-    end
-    
-  end
-
-  private
-  
-  def sanity_check_warning(file, message)
-    unless defined?(CEEDLING_IGNORE_SANITY_CHECK)
-      notice = "\n" + 
-               "ERROR: Internal sanity check for test fixture '#{file.ext(@configurator.extension_executable)}' finds that #{message}\n" +
-               "  Possible causes:\n" +
-               "    1. Your test + source dereferenced a null pointer.\n" +
-               "    2. Your test + source indexed past the end of a buffer.\n" +
-               "    3. Your test + source committed a memory access violation.\n" +
-               "    4. Your test fixture produced an exit code of 0 despite execution ending prematurely.\n" +
-               "  Sanity check failures of test results are usually a symptom of interrupted test execution.\n\n"
-      
-      @streaminator.stderr_puts( notice )
-      raise
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/generator_test_runner.rb b/test/vendor/ceedling/lib/ceedling/generator_test_runner.rb
deleted file mode 100644
index 6999faf96..000000000
--- a/test/vendor/ceedling/lib/ceedling/generator_test_runner.rb
+++ /dev/null
@@ -1,56 +0,0 @@
-
-class GeneratorTestRunner
-
-  constructor :configurator, :file_path_utils, :file_wrapper
-
-  def find_test_cases(test_file)
-
-    #Pull in Unity's Test Runner Generator
-    require 'generate_test_runner.rb'
-    @test_runner_generator ||= UnityTestRunnerGenerator.new( @configurator.get_runner_config )
-
-    if (@configurator.project_use_test_preprocessor)
-
-      #redirect to use the preprocessor file if we're doing that sort of thing
-      pre_test_file = @file_path_utils.form_preprocessed_file_filepath(test_file)
-
-      #actually look for the tests using Unity's test runner generator
-      contents = @file_wrapper.read(pre_test_file)
-      tests_and_line_numbers = @test_runner_generator.find_tests(contents)
-      @test_runner_generator.find_setup_and_teardown(contents)
-
-      #look up the line numbers in the original file
-      source_lines = @file_wrapper.read(test_file).split("\n")
-      source_index = 0;
-      tests_and_line_numbers.size.times do |i|
-        source_lines[source_index..-1].each_with_index do |line, index|
-          if (line =~ /#{tests_and_line_numbers[i][:test]}/)
-            source_index += index
-            tests_and_line_numbers[i][:line_number] = source_index + 1
-            break
-          end
-        end
-      end
-    else
-      #Just look for the tests using Unity's test runner generator
-      contents = @file_wrapper.read(test_file)
-      tests_and_line_numbers = @test_runner_generator.find_tests(contents)
-      @test_runner_generator.find_setup_and_teardown(contents)
-    end
-
-    return tests_and_line_numbers
-  end
-
-  def generate(module_name, runner_filepath, test_cases, mock_list, test_file_includes=[])
-    require 'generate_test_runner.rb'
-
-    #actually build the test runner using Unity's test runner generator
-    #(there is no need to use preprocessor here because we've already looked up test cases and are passing them in here)
-    @test_runner_generator ||= UnityTestRunnerGenerator.new( @configurator.get_runner_config )
-    @test_runner_generator.generate( module_name,
-                                     runner_filepath,
-                                     test_cases,
-                                     mock_list,
-                                     test_file_includes)
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/loginator.rb b/test/vendor/ceedling/lib/ceedling/loginator.rb
deleted file mode 100644
index 92276e1df..000000000
--- a/test/vendor/ceedling/lib/ceedling/loginator.rb
+++ /dev/null
@@ -1,31 +0,0 @@
-
-class Loginator
-
-  constructor :configurator, :project_file_loader, :project_config_manager, :file_wrapper, :system_wrapper
-
-
-  def setup_log_filepath
-    config_files = []
-    config_files << @project_file_loader.main_file
-    config_files << @project_file_loader.user_file
-    config_files.concat( @project_config_manager.options_files )
-    config_files.compact!
-    config_files.map! { |file| file.ext('') }
-    
-    log_name = config_files.join( '_' )
-
-    @project_log_filepath = File.join( @configurator.project_log_path, log_name.ext('.log') )
-  end
-
-
-  def log(string, heading=nil)
-    return if (not @configurator.project_logging)
-  
-    output  = "\n[#{@system_wrapper.time_now}]"
-    output += " :: #{heading}" if (not heading.nil?)
-    output += "\n#{string.strip}\n"
-
-    @file_wrapper.write(@project_log_filepath, output, 'a')
-  end
-  
-end
diff --git a/test/vendor/ceedling/lib/ceedling/makefile.rb b/test/vendor/ceedling/lib/ceedling/makefile.rb
deleted file mode 100644
index c3d7496d2..000000000
--- a/test/vendor/ceedling/lib/ceedling/makefile.rb
+++ /dev/null
@@ -1,46 +0,0 @@
-
-# modified version of Rake's provided make-style dependency loader
-# customizations: 
-#  (1) handles windows drives in paths -- colons don't confuse task demarcation
-#  (2) handles spaces in directory paths
-
-module Rake
-
-  # Makefile loader to be used with the import file loader.
-  class MakefileLoader
-
-    # Load the makefile dependencies in +fn+.
-    def load(fn)
-      open(fn) do |mf|
-        lines = mf.read
-        lines.gsub!(/#[^\n]*\n/m, "") # remove comments
-        lines.gsub!(/\\\n/, ' ')      # string together line continuations into single line
-        lines.split("\n").each do |line|
-          process_line(line)
-        end
-      end
-    end
-
-    private
-
-    # Process one logical line of makefile data.
-    def process_line(line)
-      # split on presence of task demaractor followed by space (i.e don't get confused by a colon in a win path)
-      file_tasks, args = line.split(/:\s/)
-
-      return if args.nil?
-      
-      # split at non-escaped space boundary between files (i.e. escaped spaces in paths are left alone)
-      dependents = args.split(/\b\s+/)
-      # replace escaped spaces and clean up any extra whitespace
-      dependents.map! { |path| path.gsub(/\\ /, ' ').strip }
-
-      file_tasks.strip.split.each do |file_task|
-        file file_task => dependents
-      end
-    end
-  end
-
-  # Install the handler
-  Rake.application.add_loader('mf', MakefileLoader.new)
-end
diff --git a/test/vendor/ceedling/lib/ceedling/objects.yml b/test/vendor/ceedling/lib/ceedling/objects.yml
deleted file mode 100644
index 2e2e9b9d2..000000000
--- a/test/vendor/ceedling/lib/ceedling/objects.yml
+++ /dev/null
@@ -1,310 +0,0 @@
-
-file_wrapper:
-
-file_system_wrapper:
-
-stream_wrapper:
-
-rake_wrapper:
-
-yaml_wrapper:
-
-system_wrapper:
-
-cmock_builder:
-
-reportinator:
-
-rake_utils:
-  compose:
-    - rake_wrapper  
-
-system_utils:
-  compose:
-    - system_wrapper  
-
-file_path_utils:
-  compose:
-    - configurator
-    - file_wrapper
-
-file_system_utils:
-  compose: file_wrapper
-
-project_file_loader:
-  compose:
-    - yaml_wrapper
-    - stream_wrapper
-    - system_wrapper
-    - file_wrapper
-
-project_config_manager:
-  compose:
-    - cacheinator
-    - configurator
-    - yaml_wrapper
-    - file_wrapper
-
-cacheinator:
-  compose:
-    - cacheinator_helper
-    - file_path_utils
-    - file_wrapper
-    - yaml_wrapper
-
-cacheinator_helper:
-  compose:
-    - file_wrapper
-    - yaml_wrapper
-
-tool_executor:
-  compose:
-    - configurator
-    - tool_executor_helper
-    - streaminator
-    - system_wrapper
-
-tool_executor_helper:
-  compose:
-    - streaminator
-    - system_utils
-    - system_wrapper
-
-configurator:
-  compose:
-    - configurator_setup
-    - configurator_plugins
-    - configurator_builder
-    - cmock_builder
-    - yaml_wrapper
-    - system_wrapper
-
-configurator_setup:
-  compose:
-    - configurator_builder
-    - configurator_validator
-    - configurator_plugins
-    - stream_wrapper
-
-configurator_plugins:
-  compose:
-    - stream_wrapper
-    - file_wrapper
-    - system_wrapper
-
-configurator_validator:
-  compose:
-    - file_wrapper
-    - stream_wrapper
-    - system_wrapper
-
-configurator_builder:
-  compose:
-    - file_system_utils
-    - file_wrapper
-    - system_wrapper
-
-loginator:
-  compose:
-    - configurator
-    - project_file_loader
-    - project_config_manager
-    - file_wrapper
-    - system_wrapper
-
-streaminator:
-  compose:
-    - streaminator_helper
-    - verbosinator
-    - loginator
-    - stream_wrapper
-
-streaminator_helper:
-
-setupinator:
-
-plugin_builder:
-
-plugin_manager:
-  compose:
-    - configurator
-    - plugin_manager_helper
-    - streaminator
-    - reportinator
-    - system_wrapper
-
-plugin_manager_helper:
-
-plugin_reportinator:
-  compose:
-    - plugin_reportinator_helper
-    - plugin_manager
-    - reportinator
-
-plugin_reportinator_helper:
-  compose:
-    - configurator
-    - streaminator
-    - yaml_wrapper
-    - file_wrapper
-
-verbosinator:
-  compose: configurator
-
-file_finder:
-  compose:
-    - configurator
-    - file_finder_helper
-    - cacheinator
-    - file_path_utils
-    - file_wrapper
-    - yaml_wrapper
-
-file_finder_helper:
-  compose: streaminator
-
-test_includes_extractor:
-  compose:
-    - configurator
-    - yaml_wrapper
-    - file_wrapper
-
-task_invoker:
-  compose:
-    - dependinator
-    - rake_utils
-    - rake_wrapper
-    - project_config_manager
-
-flaginator:
-  compose:
-    - configurator
-
-generator:
-  compose:
-    - configurator
-    - generator_helper
-    - preprocessinator
-    - cmock_builder
-    - generator_test_runner
-    - generator_test_results
-    - flaginator
-    - test_includes_extractor
-    - tool_executor
-    - file_finder
-    - file_path_utils
-    - streaminator
-    - plugin_manager
-    - file_wrapper
-
-generator_helper:
-  compose:
-    - streaminator
-
-generator_test_results:
-  compose:
-    - configurator  
-    - generator_test_results_sanity_checker
-    - yaml_wrapper  
-
-generator_test_results_sanity_checker:
-  compose:
-    - configurator  
-    - streaminator
-
-generator_test_runner:
-  compose:
-    - configurator
-    - file_path_utils
-    - file_wrapper
-
-dependinator:
-  compose:
-    - configurator
-    - project_config_manager
-    - test_includes_extractor
-    - file_path_utils        
-    - rake_wrapper
-    - file_wrapper
-
-preprocessinator:
-  compose:
-    - preprocessinator_helper          
-    - preprocessinator_includes_handler
-    - preprocessinator_file_handler
-    - task_invoker    
-    - file_path_utils
-    - yaml_wrapper
-
-preprocessinator_helper:
-  compose:                    
-    - configurator            
-    - test_includes_extractor 
-    - task_invoker            
-    - file_finder             
-    - file_path_utils         
-
-preprocessinator_includes_handler:
-  compose:
-    - configurator    
-    - tool_executor   
-    - task_invoker    
-    - file_path_utils 
-    - yaml_wrapper    
-    - file_wrapper    
-
-preprocessinator_file_handler:
-  compose:
-    - preprocessinator_extractor
-    - configurator   
-    - tool_executor  
-    - file_path_utils
-    - file_wrapper   
-
-preprocessinator_extractor:
-
-test_invoker:
-  compose:
-    - configurator
-    - test_invoker_helper
-    - plugin_manager
-    - streaminator
-    - preprocessinator
-    - task_invoker
-    - dependinator
-    - project_config_manager
-    - build_invoker_utils
-    - file_path_utils
-    - file_wrapper
-
-test_invoker_helper:
-  compose:
-    - configurator
-    - task_invoker
-    - test_includes_extractor
-    - file_finder
-    - file_path_utils
-    - file_wrapper
-
-release_invoker:
-  compose:
-    - configurator
-    - release_invoker_helper
-    - build_invoker_utils
-    - dependinator
-    - task_invoker
-    - file_path_utils
-    - file_wrapper
-
-release_invoker_helper:
-  compose:
-    - configurator
-    - dependinator
-    - task_invoker
-
-build_invoker_utils:
-  compose:
-    - configurator
-    - streaminator
-
-erb_wrapper:
diff --git a/test/vendor/ceedling/lib/ceedling/par_map.rb b/test/vendor/ceedling/lib/ceedling/par_map.rb
deleted file mode 100644
index 98198a2ce..000000000
--- a/test/vendor/ceedling/lib/ceedling/par_map.rb
+++ /dev/null
@@ -1,19 +0,0 @@
-
-
-def par_map(n, things, &block)
-  queue = Queue.new
-  things.each { |thing| queue << thing }
-  threads = (1..n).collect do
-    Thread.new do
-      begin
-        while true
-          yield queue.pop(true)
-        end
-      rescue ThreadError
-
-      end
-    end
-  end
-  threads.each { |t| t.join }
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/plugin.rb b/test/vendor/ceedling/lib/ceedling/plugin.rb
deleted file mode 100644
index f20b3a3b2..000000000
--- a/test/vendor/ceedling/lib/ceedling/plugin.rb
+++ /dev/null
@@ -1,80 +0,0 @@
-
-class String
-  # reformat a multiline string to have given number of whitespace columns;
-  # helpful for formatting heredocs
-  def left_margin(margin=0)
-    non_whitespace_column = 0
-    new_lines = []
-    
-    # find first line with non-whitespace and count left columns of whitespace
-    self.each_line do |line|
-      if (line =~ /^\s*\S/)
-        non_whitespace_column = $&.length - 1
-        break
-      end
-    end
-    
-    # iterate through each line, chopping off leftmost whitespace columns and add back the desired whitespace margin
-    self.each_line do |line|
-      columns = []
-      margin.times{columns << ' '}
-      # handle special case of line being narrower than width to be lopped off
-      if (non_whitespace_column < line.length)
-        new_lines << "#{columns.join}#{line[non_whitespace_column..-1]}"
-      else
-        new_lines << "\n"
-      end
-    end
-    
-    return new_lines.join
-  end
-end
-
-class Plugin
-  attr_reader :name, :environment
-  attr_accessor :plugin_objects
-
-  def initialize(system_objects, name)
-    @environment = []
-    @ceedling = system_objects
-    @name = name
-    self.setup
-  end
-
-  def setup; end
-
-  # mock generation
-  def pre_mock_generate(arg_hash); end
-  def post_mock_generate(arg_hash); end
-
-  # test runner generation
-  def pre_runner_generate(arg_hash); end
-  def post_runner_generate(arg_hash); end
-
-  # compilation (test or source)
-  def pre_compile_execute(arg_hash); end
-  def post_compile_execute(arg_hash); end
-
-  # linking (test or source)
-  def pre_link_execute(arg_hash); end
-  def post_link_execute(arg_hash); end
-
-  # test fixture execution
-  def pre_test_fixture_execute(arg_hash); end
-  def post_test_fixture_execute(arg_hash); end
-
-  # test task
-  def pre_test(test); end
-  def post_test(test); end
-
-  # release task
-  def pre_release; end
-  def post_release; end
-
-  # whole shebang (any use of Ceedling)
-  def pre_build; end
-  def post_build; end
-  
-  def summary; end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_builder.rb b/test/vendor/ceedling/lib/ceedling/plugin_builder.rb
deleted file mode 100644
index 1269141f1..000000000
--- a/test/vendor/ceedling/lib/ceedling/plugin_builder.rb
+++ /dev/null
@@ -1,53 +0,0 @@
-require 'ceedling/plugin'
-
-class PluginBuilder
-
-  attr_accessor :plugin_objects
-
-  def construct_plugin(plugin_name, object_map_yaml, system_objects)
-    # @streaminator.stdout_puts("Constructing plugin #{plugin_name}...", Verbosity::OBNOXIOUS)
-    object_map = {}
-    @plugin_objects = {}
-    @system_objects = system_objects
-
-    if object_map_yaml
-      @object_map = YAML.load(object_map_yaml)
-      @object_map.each_key do |obj|
-        construct_object(obj)
-      end
-    else
-      raise "Invalid object map for plugin #{plugin_name}!"
-    end
-
-    return @plugin_objects
-  end
-
-  private
-  
-  def camelize(underscored_name)
-    return underscored_name.gsub(/(_|^)([a-z0-9])/) {$2.upcase}
-  end
-
-  def construct_object(obj)
-    if @plugin_objects[obj].nil?
-      if @object_map[obj] && @object_map[obj]['compose']
-        @object_map[obj]['compose'].each do |dep|
-          construct_object(dep)
-        end
-      end
-      build_object(obj)
-    end
-  end
-
-  def build_object(new_object)
-    if @plugin_objects[new_object.to_sym].nil?
-      # @streaminator.stdout_puts("Building plugin object #{new_object}", Verbosity::OBNOXIOUS)
-      require new_object
-      class_name = camelize(new_object)
-      new_instance = eval("#{class_name}.new(@system_objects, class_name.to_s)")
-      new_instance.plugin_objects = @plugin_objects
-      @plugin_objects[new_object.to_sym] = new_instance
-    end
-  end
-
-end
\ No newline at end of file
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_manager.rb b/test/vendor/ceedling/lib/ceedling/plugin_manager.rb
deleted file mode 100644
index 0468f2fc4..000000000
--- a/test/vendor/ceedling/lib/ceedling/plugin_manager.rb
+++ /dev/null
@@ -1,107 +0,0 @@
-require 'ceedling/constants'
-
-class PluginManager
-
-  constructor :configurator, :plugin_manager_helper, :streaminator, :reportinator, :system_wrapper
-
-  def setup
-    @build_fail_registry = []
-    @plugin_objects = [] # so we can preserve order
-  end
-
-  def load_plugin_scripts(script_plugins, system_objects)
-    environment = []
-
-    script_plugins.each do |plugin|
-      # protect against instantiating object multiple times due to processing config multiple times (option files, etc)
-      next if (@plugin_manager_helper.include?(@plugin_objects, plugin))
-      begin
-        @system_wrapper.require_file( "#{plugin}.rb" )
-        object = @plugin_manager_helper.instantiate_plugin_script( camelize(plugin), system_objects, plugin )
-        @plugin_objects << object
-        environment += object.environment
-
-        # add plugins to hash of all system objects
-        system_objects[plugin.downcase.to_sym] = object
-      rescue
-        puts "Exception raised while trying to load plugin: #{plugin}"
-        raise
-      end
-    end
-
-    yield( { :environment => environment } ) if (environment.size > 0)
-  end
-
-  def plugins_failed?
-    return (@build_fail_registry.size > 0)
-  end
-
-  def print_plugin_failures
-    if (@build_fail_registry.size > 0)
-      report = @reportinator.generate_banner('BUILD FAILURE SUMMARY')
-
-      @build_fail_registry.each do |failure|
-        report += "#{' - ' if (@build_fail_registry.size > 1)}#{failure}\n"
-      end
-
-      report += "\n"
-
-      @streaminator.stderr_puts(report, Verbosity::ERRORS)
-    end
-  end
-
-  def register_build_failure(message)
-    @build_fail_registry << message if (message and not message.empty?)
-  end
-
-  #### execute all plugin methods ####
-
-  def pre_mock_generate(arg_hash); execute_plugins(:pre_mock_generate, arg_hash); end
-  def post_mock_generate(arg_hash); execute_plugins(:post_mock_generate, arg_hash); end
-
-  def pre_runner_generate(arg_hash); execute_plugins(:pre_runner_generate, arg_hash); end
-  def post_runner_generate(arg_hash); execute_plugins(:post_runner_generate, arg_hash); end
-
-  def pre_compile_execute(arg_hash); execute_plugins(:pre_compile_execute, arg_hash); end
-  def post_compile_execute(arg_hash); execute_plugins(:post_compile_execute, arg_hash); end
-
-  def pre_link_execute(arg_hash); execute_plugins(:pre_link_execute, arg_hash); end
-  def post_link_execute(arg_hash); execute_plugins(:post_link_execute, arg_hash); end
-
-  def pre_test_fixture_execute(arg_hash); execute_plugins(:pre_test_fixture_execute, arg_hash); end
-  def post_test_fixture_execute(arg_hash)
-    # special arbitration: raw test results are printed or taken over by plugins handling the job
-    @streaminator.stdout_puts(arg_hash[:shell_result][:output]) if (@configurator.plugins_display_raw_test_results)
-    execute_plugins(:post_test_fixture_execute, arg_hash)
-  end
-
-  def pre_test(test); execute_plugins(:pre_test, test); end
-  def post_test(test); execute_plugins(:post_test, test); end
-
-  def pre_release; execute_plugins(:pre_release); end
-  def post_release; execute_plugins(:post_release); end
-
-  def pre_build; execute_plugins(:pre_build); end
-  def post_build; execute_plugins(:post_build); end
-  def post_error; execute_plugins(:post_error); end
-
-  def summary; execute_plugins(:summary); end
-
-  private ####################################
-
-  def camelize(underscored_name)
-    return underscored_name.gsub(/(_|^)([a-z0-9])/) {$2.upcase}
-  end
-
-  def execute_plugins(method, *args)
-    @plugin_objects.each do |plugin|
-      begin
-        plugin.send(method, *args) if plugin.respond_to?(method)
-      rescue
-        puts "Exception raised in plugin: #{plugin.name}, in method #{method}"
-        raise
-      end
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_manager_helper.rb b/test/vendor/ceedling/lib/ceedling/plugin_manager_helper.rb
deleted file mode 100644
index b18248a65..000000000
--- a/test/vendor/ceedling/lib/ceedling/plugin_manager_helper.rb
+++ /dev/null
@@ -1,19 +0,0 @@
-
-class PluginManagerHelper
-
-  def include?(plugins, name)
-		include = false
-		plugins.each do |plugin|
-			if (plugin.name == name)
-				include = true
-				break
-			end
-		end
-		return include
-  end
-
-  def instantiate_plugin_script(plugin, system_objects, name)
-    return eval("#{plugin}.new(system_objects, name)")
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb b/test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb
deleted file mode 100644
index 8d83727ba..000000000
--- a/test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb
+++ /dev/null
@@ -1,76 +0,0 @@
-require 'ceedling/constants'
-require 'ceedling/defaults'
-
-class PluginReportinator
-  
-  constructor :plugin_reportinator_helper, :plugin_manager, :reportinator
-
-  def setup
-    @test_results_template = nil
-  end
-  
-  
-  def set_system_objects(system_objects)
-    @plugin_reportinator_helper.ceedling = system_objects
-  end
-  
-  
-  def fetch_results(results_path, test, options={:boom => false})
-    return @plugin_reportinator_helper.fetch_results( File.join(results_path, test), options )
-  end
-
-  
-  def generate_banner(message)
-    return @reportinator.generate_banner(message)
-  end
-
-  
-  def assemble_test_results(results_list, options={:boom => false})
-    aggregated_results = get_results_structure
-    
-    results_list.each do |result_path| 
-      results = @plugin_reportinator_helper.fetch_results( result_path, options )
-      @plugin_reportinator_helper.process_results(aggregated_results, results)
-    end
-
-    return aggregated_results
-  end
-  
-  
-  def register_test_results_template(template)
-    @test_results_template = template if (@test_results_template.nil?)
-  end
-  
-  
-  def run_test_results_report(hash, verbosity=Verbosity::NORMAL, &block)
-    run_report( $stdout,
-                ((@test_results_template.nil?) ? DEFAULT_TESTS_RESULTS_REPORT_TEMPLATE : @test_results_template),
-                hash,
-                verbosity,
-                &block )
-  end
-  
-  
-  def run_report(stream, template, hash=nil, verbosity=Verbosity::NORMAL)
-    failure = nil
-    failure = yield() if block_given?
-  
-    @plugin_manager.register_build_failure( failure )
-    
-    @plugin_reportinator_helper.run_report( stream, template, hash, verbosity )
-  end
-  
-  private ###############################
-  
-  def get_results_structure
-    return {
-      :successes => [],
-      :failures  => [],
-      :ignores   => [],
-      :stdout    => [],
-      :counts    => {:total => 0, :passed => 0, :failed => 0, :ignored  => 0, :stdout => 0},
-      :time      => 0.0
-      }
-  end
- 
-end
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb b/test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb
deleted file mode 100644
index 322a530b5..000000000
--- a/test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb
+++ /dev/null
@@ -1,51 +0,0 @@
-require 'erb'
-require 'rubygems'
-require 'rake' # for ext()
-require 'ceedling/constants'
-
-class PluginReportinatorHelper
-  
-  attr_writer :ceedling
-  
-  constructor :configurator, :streaminator, :yaml_wrapper, :file_wrapper
-  
-  def fetch_results(results_path, options)
-    pass_path = File.join(results_path.ext( @configurator.extension_testpass ))
-    fail_path = File.join(results_path.ext( @configurator.extension_testfail ))
-
-    if (@file_wrapper.exist?(fail_path))
-      return @yaml_wrapper.load(fail_path)
-    elsif (@file_wrapper.exist?(pass_path))
-      return @yaml_wrapper.load(pass_path)
-    else
-      if (options[:boom])
-        @streaminator.stderr_puts("Could find no test results for '#{File.basename(results_path).ext(@configurator.extension_source)}'", Verbosity::ERRORS)
-        raise
-      end
-    end
-    
-    return {}
-  end
-
-
-  def process_results(aggregate_results, results)
-    return if (results.empty?)
-    aggregate_results[:successes]        << { :source => results[:source].clone, :collection => results[:successes].clone } if (results[:successes].size > 0)
-    aggregate_results[:failures]         << { :source => results[:source].clone, :collection => results[:failures].clone  } if (results[:failures].size > 0)
-    aggregate_results[:ignores]          << { :source => results[:source].clone, :collection => results[:ignores].clone   } if (results[:ignores].size > 0)
-    aggregate_results[:stdout]           << { :source => results[:source].clone, :collection => results[:stdout].clone    } if (results[:stdout].size > 0)
-    aggregate_results[:counts][:total]   += results[:counts][:total]
-    aggregate_results[:counts][:passed]  += results[:counts][:passed]
-    aggregate_results[:counts][:failed]  += results[:counts][:failed]
-    aggregate_results[:counts][:ignored] += results[:counts][:ignored]
-    aggregate_results[:counts][:stdout]  += results[:stdout].size
-    aggregate_results[:time] += results[:time]
-  end
-
-
-  def run_report(stream, template, hash, verbosity)
-    output = ERB.new(template, 0, "%<>")
-    @streaminator.stream_puts(stream, output.result(binding()), verbosity)
-  end
-  
-end
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator.rb
deleted file mode 100644
index f07750dd2..000000000
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator.rb
+++ /dev/null
@@ -1,42 +0,0 @@
-
-class Preprocessinator
-
-  attr_reader :preprocess_file_proc
-  
-  constructor :preprocessinator_helper, :preprocessinator_includes_handler, :preprocessinator_file_handler, :task_invoker, :file_path_utils, :yaml_wrapper
-
-
-  def setup
-    # fashion ourselves callbacks @preprocessinator_helper can use
-    @preprocess_includes_proc = Proc.new { |filepath| self.preprocess_shallow_includes(filepath) }
-    @preprocess_file_proc     = Proc.new { |filepath| self.preprocess_file(filepath) }
-  end
-
-
-  def preprocess_test_and_invoke_test_mocks(test)
-    @preprocessinator_helper.preprocess_includes(test, @preprocess_includes_proc)
-
-    mocks_list = @preprocessinator_helper.assemble_mocks_list(test)
-
-    @preprocessinator_helper.preprocess_mockable_headers(mocks_list, @preprocess_file_proc)
-
-    @task_invoker.invoke_test_mocks(mocks_list)
-
-    @preprocessinator_helper.preprocess_test_file(test, @preprocess_file_proc)
-    
-    return mocks_list
-  end
-
-  def preprocess_shallow_includes(filepath)
-    includes = @preprocessinator_includes_handler.extract_includes(filepath)
-
-    @preprocessinator_includes_handler.write_shallow_includes_list(
-      @file_path_utils.form_preprocessed_includes_list_filepath(filepath), includes)
-  end
-
-  def preprocess_file(filepath)
-    @preprocessinator_includes_handler.invoke_shallow_includes_list(filepath)
-    @preprocessinator_file_handler.preprocess_file( filepath, @yaml_wrapper.load(@file_path_utils.form_preprocessed_includes_list_filepath(filepath)) )
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb
deleted file mode 100644
index 49509a8b0..000000000
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb
+++ /dev/null
@@ -1,30 +0,0 @@
-class PreprocessinatorExtractor
-  def extract_base_file_from_preprocessed_expansion(filepath)
-    # preprocessing by way of toolchain preprocessor expands macros, eliminates
-    # comments, strips out #ifdef code, etc.  however, it also expands in place
-    # each #include'd file.  so, we must extract only the lines of the file
-    # that belong to the file originally preprocessed
-
-    # iterate through all lines and alternate between extract and ignore modes
-    # all lines between a '#'line containing file name of our filepath and the
-    # next '#'line should be extracted
-
-    base_name  = File.basename(filepath)
-    not_pragma = /^#(?!pragma\b)/ # preprocessor directive that's not a #pragma
-    pattern    = /^#.*(\s|\/|\\|\")#{Regexp.escape(base_name)}/
-    found_file = false # have we found the file we care about?
-
-    lines = []
-    File.readlines(filepath).each do |line|
-      if found_file and not line =~ not_pragma
-        lines << line
-      else
-        found_file = false
-      end
-
-      found_file = true if line =~ pattern
-    end
-
-    return lines
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb
deleted file mode 100644
index b6b5efbc6..000000000
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb
+++ /dev/null
@@ -1,21 +0,0 @@
-
-
-class PreprocessinatorFileHandler
-
-  constructor :preprocessinator_extractor, :configurator, :tool_executor, :file_path_utils, :file_wrapper
-
-
-  def preprocess_file(filepath, includes)
-    preprocessed_filepath = @file_path_utils.form_preprocessed_file_filepath(filepath)
-
-    command = @tool_executor.build_command_line(@configurator.tools_test_file_preprocessor, [], filepath, preprocessed_filepath)
-    @tool_executor.exec(command[:line], command[:options])
-
-    contents = @preprocessinator_extractor.extract_base_file_from_preprocessed_expansion(preprocessed_filepath)
-
-    includes.each{|include| contents.unshift("#include \"#{include}\"")}
-
-    @file_wrapper.write(preprocessed_filepath, contents.join("\n"))
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb
deleted file mode 100644
index 1419a5616..000000000
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb
+++ /dev/null
@@ -1,46 +0,0 @@
-
-
-class PreprocessinatorHelper
-
-  constructor :configurator, :test_includes_extractor, :task_invoker, :file_finder, :file_path_utils
-
-
-  def preprocess_includes(test, preprocess_includes_proc)
-    if (@configurator.project_use_test_preprocessor)
-      preprocessed_includes_list = @file_path_utils.form_preprocessed_includes_list_filepath(test)
-      preprocess_includes_proc.call( @file_finder.find_test_from_file_path(preprocessed_includes_list) )
-      @test_includes_extractor.parse_includes_list(preprocessed_includes_list)
-    else
-      @test_includes_extractor.parse_test_file(test)
-    end
-  end
-
-  def assemble_mocks_list(test)
-    return @file_path_utils.form_mocks_source_filelist( @test_includes_extractor.lookup_raw_mock_list(test) )
-  end
-
-  def preprocess_mockable_headers(mock_list, preprocess_file_proc)
-    if (@configurator.project_use_test_preprocessor)
-      preprocess_files_smartly(
-        @file_path_utils.form_preprocessed_mockable_headers_filelist(mock_list),
-        preprocess_file_proc ) { |file| @file_finder.find_header_file(file) }
-    end
-  end
-
-  def preprocess_test_file(test, preprocess_file_proc)
-    return if (!@configurator.project_use_test_preprocessor)
-
-    preprocess_file_proc.call(test)
-  end
-
-  private ############################
-
-  def preprocess_files_smartly(file_list, preprocess_file_proc)
-    if (@configurator.project_use_deep_dependencies)
-      @task_invoker.invoke_test_preprocessed_files(file_list)
-    else
-      file_list.each { |file| preprocess_file_proc.call( yield(file) ) }
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
deleted file mode 100644
index 703c84f3c..000000000
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
+++ /dev/null
@@ -1,181 +0,0 @@
-
-
-class PreprocessinatorIncludesHandler
-
-  constructor :configurator, :tool_executor, :task_invoker, :file_path_utils, :yaml_wrapper, :file_wrapper
-  @@makefile_cache = {}
-
-  # shallow includes: only those headers a source file explicitly includes
-
-  def invoke_shallow_includes_list(filepath)
-    @task_invoker.invoke_test_shallow_include_lists( [@file_path_utils.form_preprocessed_includes_list_filepath(filepath)] )
-  end
-
-  ##
-  # Ask the preprocessor for a make-style dependency rule of only the headers
-  # the source file immediately includes.
-  #
-  # === Arguments
-  # +filepath+ _String_:: Path to the test file to process.
-  #
-  # === Return
-  # _String_:: The text of the dependency rule generated by the preprocessor.
-  def form_shallow_dependencies_rule(filepath)
-    if @@makefile_cache.has_key?(filepath)
-      return @@makefile_cache[filepath]
-    end
-    # change filename (prefix of '_') to prevent preprocessor from finding
-    # include files in temp directory containing file it's scanning
-    temp_filepath = @file_path_utils.form_temp_path(filepath, '_')
-
-    # read the file and replace all include statements with a decorated version
-    # (decorating the names creates file names that don't exist, thus preventing
-    # the preprocessor from snaking out and discovering the entire include path
-    # that winds through the code). The decorated filenames indicate files that
-    # are included directly by the test file.
-    contents = @file_wrapper.read(filepath)
-
-    if !contents.valid_encoding?
-      contents = contents.encode("UTF-16be", :invalid=>:replace, :replace=>"?").encode('UTF-8')
-    end
-
-    contents.gsub!( /^\s*#include\s+[\"<]\s*(\S+)\s*[\">]/, "#include \"\\1\"\n#include \"@@@@\\1\"" )
-    contents.gsub!( /^\s*TEST_FILE\(\s*\"\s*(\S+)\s*\"\s*\)/, "#include \"\\1\"\n#include \"@@@@\\1\"")
-    @file_wrapper.write( temp_filepath, contents )
-
-    # extract the make-style dependency rule telling the preprocessor to
-    # ignore the fact that it can't find the included files
-    command = @tool_executor.build_command_line(@configurator.tools_test_includes_preprocessor, [], temp_filepath)
-    shell_result = @tool_executor.exec(command[:line], command[:options])
-
-    @@makefile_cache[filepath] = shell_result[:output]
-    return shell_result[:output]
-  end
-
-  ##
-  # Extract the headers that are directly included by a source file using the
-  # provided, annotated Make dependency rule.
-  #
-  # === Arguments
-  # +filepath+ _String_:: C source or header file to extract includes for.
-  #
-  # === Return
-  # _Array_ of _String_:: Array of the direct dependencies for the source file.
-  def extract_includes(filepath)
-    to_process = [filepath]
-    ignore_list = []
-    list = []
-
-    include_paths = @configurator.project_config_hash[:collection_paths_include]
-    include_paths = [] if include_paths.nil?
-    include_paths.map! {|path| File.expand_path(path)}
-
-    while to_process.length > 0
-      target = to_process.shift()
-      ignore_list << target
-      # puts "[HELL] Processing: \t\t#{target}"
-      new_deps, new_to_process = extract_includes_helper(target, include_paths, ignore_list)
-      list += new_deps
-      to_process += new_to_process
-      if (!@configurator.project_config_hash.has_key?(:project_auto_link_deep_dependencies) or
-          !@configurator.project_config_hash[:project_auto_link_deep_dependencies])
-        break
-      else
-        list = list.uniq()
-        to_process = to_process.uniq()
-      end
-    end
-
-    return list
-  end
-
-  def extract_includes_helper(filepath, include_paths, ignore_list)
-    # Extract the dependencies from the make rule
-    hdr_ext = @configurator.extension_header
-    make_rule = self.form_shallow_dependencies_rule(filepath)
-    dependencies = make_rule.split.find_all {|path| path.end_with?(hdr_ext) }.uniq
-    dependencies.map! {|hdr| hdr.gsub('\\','/') }
-
-    # Separate the real files form the annotated ones and remove the '@@@@'
-    annotated_headers, real_headers = dependencies.partition {|hdr| hdr =~ /^@@@@/ }
-    annotated_headers.map! {|hdr| hdr.gsub('@@@@','') }
-    # Matching annotated_headers values against real_headers to ensure that
-    # annotated_headers contain full path entries (as returned by make rule)
-    annotated_headers.map! {|hdr| real_headers.find {|real_hdr| !real_hdr.match(/(.*\/)?#{Regexp.escape(hdr)}/).nil? } }
-    annotated_headers = annotated_headers.compact
-
-    # Find which of our annotated headers are "real" dependencies. This is
-    # intended to weed out dependencies that have been removed due to build
-    # options defined in the project yaml and/or in the headers themselves.
-    list = annotated_headers.find_all do |annotated_header|
-      # find the index of the "real" include that matches the annotated one.
-      idx = real_headers.find_index do |real_header|
-        real_header =~ /^(.*\/)?#{Regexp.escape(annotated_header)}$/
-      end
-      # If we found a real include, delete it from the array and return it,
-      # otherwise return nil. Since nil is falsy this has the effect of making
-      # find_all return only the annotated headers for which a real include was
-      # found/deleted
-      idx ? real_headers.delete_at(idx) : nil
-    end.compact
-
-    # Extract direct dependencies that were also added
-    src_ext = @configurator.extension_source
-    sdependencies = make_rule.split.find_all {|path| path.end_with?(src_ext) }.uniq
-    sdependencies.map! {|hdr| hdr.gsub('\\','/') }
-    list += sdependencies
-
-    to_process = []
-
-    if @configurator.project_config_hash.has_key?(:project_auto_link_deep_dependencies) && @configurator.project_config_hash[:project_auto_link_deep_dependencies]
-      # Creating list of mocks
-      mocks = annotated_headers.find_all do |annotated_header|
-        File.basename(annotated_header) =~ /^#{@configurator.project_config_hash[:cmock_mock_prefix]}.*$/
-      end.compact
-
-      # Creating list of headers that should be recursively pre-processed
-      # Skipping mocks and unity.h
-      headers_to_deep_link = annotated_headers.select do |annotated_header|
-        !(mocks.include? annotated_header) and (annotated_header.match(/^(.*\/)?unity\.h$/).nil?)
-      end
-      headers_to_deep_link.map! {|hdr| File.expand_path(hdr)}
-
-      mocks.each do |mock|
-        dirname = File.dirname(mock)
-        #basename = File.basename(mock).delete_prefix(@configurator.project_config_hash[:cmock_mock_prefix])
-        basename = File.basename(mock).sub(@configurator.project_config_hash[:cmock_mock_prefix], '')
-        if dirname != "."
-          ignore_list << File.join(dirname, basename)
-        else
-          ignore_list << basename
-        end
-      end.compact
-
-      # Filtering list of final includes to only include mocks and anything that is NOT in the ignore_list
-      list = list.select do |item|
-        mocks.include? item or !(ignore_list.any? { |ignore_item| !item.match(/^(.*\/)?#{Regexp.escape(ignore_item)}$/).nil? })
-      end
-
-      headers_to_deep_link.each do |hdr|
-        if (ignore_list.none? {|ignore_header| hdr.match(/^(.*\/)?#{Regexp.escape(ignore_header)}$/)} and
-            include_paths.none? {|include_path| hdr =~ /^#{include_path}\.*/})
-          if File.exist?(hdr)
-            to_process << hdr
-            #source_file = hdr.delete_suffix(hdr_ext) + src_ext
-            source_file = hdr.chomp(hdr_ext) + src_ext
-            if source_file != hdr and File.exist?(source_file)
-              to_process << source_file
-            end
-          end
-        end
-      end
-    end
-
-    return list, to_process
-
-  end
-
-  def write_shallow_includes_list(filepath, list)
-    @yaml_wrapper.dump(filepath, list)
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/project_config_manager.rb b/test/vendor/ceedling/lib/ceedling/project_config_manager.rb
deleted file mode 100644
index 31f7e3a68..000000000
--- a/test/vendor/ceedling/lib/ceedling/project_config_manager.rb
+++ /dev/null
@@ -1,46 +0,0 @@
-require 'ceedling/constants'
-
-
-class ProjectConfigManager
-
-  attr_reader   :options_files, :release_config_changed, :test_config_changed, :test_defines_changed
-  attr_accessor :config_hash
-
-  constructor :cacheinator, :configurator, :yaml_wrapper, :file_wrapper
-
-
-  def setup
-    @options_files = []
-    @release_config_changed = false
-    @test_config_changed    = false
-    @test_defines_changed   = false
-  end
-
-
-  def merge_options(config_hash, option_filepath)
-    @options_files << File.basename( option_filepath )
-    config_hash.deep_merge!( @yaml_wrapper.load( option_filepath ) )
-  end 
-  
-
-  
-  def process_release_config_change
-    # has project configuration changed since last release build
-    @release_config_changed = @cacheinator.diff_cached_release_config?( @config_hash )
-  end
-
-
-  def process_test_config_change
-    # has project configuration changed since last test build
-    @test_config_changed = @cacheinator.diff_cached_test_config?( @config_hash )
-  end
-
-  def process_test_defines_change(files)
-    # has definitions changed since last test build
-    @test_defines_changed = @cacheinator.diff_cached_test_defines?( files )
-    if @test_defines_changed
-      # update timestamp for rake task prerequisites
-      @file_wrapper.touch( @configurator.project_test_force_rebuild_filepath )
-    end
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/project_file_loader.rb b/test/vendor/ceedling/lib/ceedling/project_file_loader.rb
deleted file mode 100644
index bf5dcd41d..000000000
--- a/test/vendor/ceedling/lib/ceedling/project_file_loader.rb
+++ /dev/null
@@ -1,99 +0,0 @@
-require 'ceedling/constants'
-
-
-class ProjectFileLoader
-
-  attr_reader :main_file, :user_file
-
-  constructor :yaml_wrapper, :stream_wrapper, :system_wrapper, :file_wrapper
-
-  def setup
-    @main_file = nil
-    @mixin_files = []
-    @user_file = nil
-
-    @main_project_filepath = ''
-    @mixin_project_filepaths = []
-    @user_project_filepath = ''
-  end
-
-
-  def find_project_files
-    # first go hunting for optional user project file by looking for environment variable and then default location on disk
-    user_filepath = @system_wrapper.env_get('CEEDLING_USER_PROJECT_FILE')
-
-    if ( not user_filepath.nil? and @file_wrapper.exist?(user_filepath) )
-      @user_project_filepath = user_filepath
-    elsif (@file_wrapper.exist?(DEFAULT_CEEDLING_USER_PROJECT_FILE))
-      @user_project_filepath = DEFAULT_CEEDLING_USER_PROJECT_FILE
-    end
-
-    # next check for mixin project files by looking for environment variable
-    mixin_filepaths = @system_wrapper.env_get('CEEDLING_MIXIN_PROJECT_FILES')
-    if ( not mixin_filepaths.nil? )
-      mixin_filepaths.split(File::PATH_SEPARATOR).each do |filepath|
-        if ( @file_wrapper.exist?(filepath) )
-          @mixin_project_filepaths.push(filepath)
-        end
-      end
-    end
-
-    # next check for main project file by looking for environment variable and then default location on disk;
-    # blow up if we don't find this guy -- like, he's so totally important
-    main_filepath = @system_wrapper.env_get('CEEDLING_MAIN_PROJECT_FILE')
-
-    if ( not main_filepath.nil? and @file_wrapper.exist?(main_filepath) )
-      @main_project_filepath = main_filepath
-    elsif (@file_wrapper.exist?(DEFAULT_CEEDLING_MAIN_PROJECT_FILE))
-      @main_project_filepath = DEFAULT_CEEDLING_MAIN_PROJECT_FILE
-    else
-      # no verbosity checking since this is lowest level reporting anyhow &
-      # verbosity checking depends on configurator which in turns needs this class (circular dependency)
-      @stream_wrapper.stderr_puts('Found no Ceedling project file (*.yml)')
-      raise
-    end
-
-    @main_file = File.basename( @main_project_filepath )
-    @mixin_project_filepaths.each do |filepath|
-      @mixin_files.push(File.basename( filepath ))
-    end
-    @user_file = File.basename( @user_project_filepath ) if ( not @user_project_filepath.empty? )
-  end
-
-  def yaml_merger(y1, y2)
-    o1 = y1
-    y2.each_pair do |k,v|
-      if o1[k].nil?
-        o1[k] = v
-      else
-        if (o1[k].instance_of? Hash)
-          o1[k] = yaml_merger(o1[k], v)
-        elsif (o1[k].instance_of? Array)
-          o1[k] += v
-        else
-          o1[k] = v
-        end
-      end
-    end
-    return o1
-  end
-
-  def load_project_config
-    config_hash = @yaml_wrapper.load(@main_project_filepath)
-
-    # if there are mixin project files, then use them
-    @mixin_project_filepaths.each do |filepath|
-      mixin = @yaml_wrapper.load(filepath)
-      config_hash = yaml_merger( config_hash, mixin )
-    end
-
-    # if there's a user project file, then use it
-    if ( not @user_project_filepath.empty? )
-      user_hash = @yaml_wrapper.load(@user_project_filepath)
-      config_hash = yaml_merger( config_hash, user_hash )
-    end
-
-    return config_hash
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/rake_utils.rb b/test/vendor/ceedling/lib/ceedling/rake_utils.rb
deleted file mode 100644
index 3f667c852..000000000
--- a/test/vendor/ceedling/lib/ceedling/rake_utils.rb
+++ /dev/null
@@ -1,17 +0,0 @@
-
-class RakeUtils
-  
-  constructor :rake_wrapper
-
-  def task_invoked?(task_regex)
-    task_invoked = false
-    @rake_wrapper.task_list.each do |task|
-      if ((task.already_invoked) and (task.to_s =~ task_regex))
-        task_invoked = true
-        break
-      end
-    end
-    return task_invoked
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/rake_wrapper.rb b/test/vendor/ceedling/lib/ceedling/rake_wrapper.rb
deleted file mode 100644
index 15e479611..000000000
--- a/test/vendor/ceedling/lib/ceedling/rake_wrapper.rb
+++ /dev/null
@@ -1,33 +0,0 @@
-require 'rubygems'
-require 'rake'
-require 'ceedling/makefile' # our replacement for rake's make-style dependency loader
-
-include Rake::DSL if defined?(Rake::DSL)
-
-class Rake::Task
-  attr_reader :already_invoked
-end
-
-class RakeWrapper
-
-  def initialize
-    @makefile_loader = Rake::MakefileLoader.new # use our custom replacement noted above
-  end
-
-  def [](task)
-    return Rake::Task[task]
-  end
-
-  def task_list
-    return Rake::Task.tasks
-  end
-
-  def create_file_task(file_task, dependencies)
-    file(file_task => dependencies)
-  end
-
-  def load_dependencies(dependencies_path)
-    @makefile_loader.load(dependencies_path)
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/rakefile.rb b/test/vendor/ceedling/lib/ceedling/rakefile.rb
deleted file mode 100644
index 37001bacc..000000000
--- a/test/vendor/ceedling/lib/ceedling/rakefile.rb
+++ /dev/null
@@ -1,86 +0,0 @@
-require 'fileutils'
-
-# get directory containing this here file, back up one directory, and expand to full path
-CEEDLING_ROOT    = File.expand_path(File.dirname(__FILE__) + '/../..')
-CEEDLING_LIB     = File.join(CEEDLING_ROOT, 'lib')
-CEEDLING_VENDOR  = File.join(CEEDLING_ROOT, 'vendor')
-CEEDLING_RELEASE = File.join(CEEDLING_ROOT, 'release')
-
-$LOAD_PATH.unshift( CEEDLING_LIB )
-$LOAD_PATH.unshift( File.join(CEEDLING_VENDOR, 'unity/auto') )
-$LOAD_PATH.unshift( File.join(CEEDLING_VENDOR, 'diy/lib') )
-$LOAD_PATH.unshift( File.join(CEEDLING_VENDOR, 'cmock/lib') )
-$LOAD_PATH.unshift( File.join(CEEDLING_VENDOR, 'deep_merge/lib') )
-
-require 'rake'
-
-#Let's make sure we remember the task descriptions in case we need them
-Rake::TaskManager.record_task_metadata = true
-
-require 'diy'
-require 'constructor'
-
-require 'ceedling/constants'
-require 'ceedling/target_loader'
-
-
-# construct all our objects
-# ensure load path contains all libraries needed first
-lib_ceedling_load_path_temp = File.join(CEEDLING_LIB, 'ceedling')
-$LOAD_PATH.unshift( lib_ceedling_load_path_temp )
-@ceedling = DIY::Context.from_yaml( File.read( File.join(lib_ceedling_load_path_temp, 'objects.yml') ) )
-@ceedling.build_everything
-# now that all objects are built, delete 'lib/ceedling' from load path
-$LOAD_PATH.delete(lib_ceedling_load_path_temp)
-# one-stop shopping for all our setup and such after construction
-@ceedling[:setupinator].ceedling = @ceedling
-
-project_config =
-  begin
-    cfg = @ceedling[:setupinator].load_project_files
-    TargetLoader.inspect(cfg, ENV['TARGET'])
-  rescue TargetLoader::NoTargets
-    cfg
-  rescue TargetLoader::RequestReload
-    @ceedling[:setupinator].load_project_files
-  end
-
-@ceedling[:setupinator].do_setup( project_config )
-
-
-# tell all our plugins we're about to do something
-@ceedling[:plugin_manager].pre_build
-
-# load rakefile component files (*.rake)
-PROJECT_RAKEFILE_COMPONENT_FILES.each { |component| load(component) }
-
-# tell rake to shut up by default (overridden in verbosity / debug tasks as appropriate)
-verbose(false)
-
-
-# end block always executed following rake run
-END {
-  $stdout.flush unless $stdout.nil?
-  $stderr.flush unless $stderr.nil?
-
-  # cache our input configurations to use in comparison upon next execution
-  @ceedling[:cacheinator].cache_test_config( @ceedling[:setupinator].config_hash )    if (@ceedling[:task_invoker].test_invoked?)
-  @ceedling[:cacheinator].cache_release_config( @ceedling[:setupinator].config_hash ) if (@ceedling[:task_invoker].release_invoked?)
-
-  # delete all temp files unless we're in debug mode
-  if (not @ceedling[:configurator].project_debug)
-    @ceedling[:file_wrapper].rm_f( @ceedling[:file_wrapper].directory_listing( File.join(@ceedling[:configurator].project_temp_path, '*') ))
-  end
-
-  # only perform these final steps if we got here without runtime exceptions or errors
-  if (@ceedling[:system_wrapper].ruby_success)
-
-    # tell all our plugins the build is done and process results
-    @ceedling[:plugin_manager].post_build
-    @ceedling[:plugin_manager].print_plugin_failures
-    exit(1) if (@ceedling[:plugin_manager].plugins_failed? && !@ceedling[:setupinator].config_hash[:graceful_fail])
-  else
-    puts "ERROR: Ceedling Failed"
-    @ceedling[:plugin_manager].post_error
-  end
-}
diff --git a/test/vendor/ceedling/lib/ceedling/release_invoker.rb b/test/vendor/ceedling/lib/ceedling/release_invoker.rb
deleted file mode 100644
index 5bfb6cd70..000000000
--- a/test/vendor/ceedling/lib/ceedling/release_invoker.rb
+++ /dev/null
@@ -1,73 +0,0 @@
-require 'ceedling/constants'
-
-
-class ReleaseInvoker
-
-  constructor :configurator, :release_invoker_helper, :build_invoker_utils, :dependinator, :task_invoker, :file_path_utils, :file_wrapper
-
-
-  def setup_and_invoke_c_objects( c_files )
-    objects = @file_path_utils.form_release_build_c_objects_filelist( c_files )
-
-    begin
-      @release_invoker_helper.process_deep_dependencies( @file_path_utils.form_release_dependencies_filelist( c_files ) )
-
-      @dependinator.enhance_release_file_dependencies( objects )
-      @task_invoker.invoke_release_objects( objects )
-    rescue => e
-      @build_invoker_utils.process_exception( e, RELEASE_SYM, false )
-    end
-
-    return objects
-  end
-
-
-  def setup_and_invoke_asm_objects( asm_files )
-    objects = @file_path_utils.form_release_build_asm_objects_filelist( asm_files )
-
-    begin
-      @dependinator.enhance_release_file_dependencies( objects )
-      @task_invoker.invoke_release_objects( objects )
-    rescue => e
-      @build_invoker_utils.process_exception( e, RELEASE_SYM, false )
-    end
-
-    return objects
-  end
-
-
-  def refresh_c_deep_dependencies
-    return if (not @configurator.project_use_deep_dependencies)
-
-    @file_wrapper.rm_f(
-      @file_wrapper.directory_listing(
-        File.join( @configurator.project_release_dependencies_path, '*' + @configurator.extension_dependencies ) ) )
-
-    @release_invoker_helper.process_deep_dependencies(
-      @file_path_utils.form_release_dependencies_filelist(
-        @configurator.collection_all_source ) )
-  end
-
-
-  def artifactinate( *files )
-    files.flatten.each do |file|
-      @file_wrapper.cp( file, @configurator.project_release_artifacts_path ) if @file_wrapper.exist?( file )
-    end
-  end
-
-  def convert_libraries_to_arguments(libraries)
-    args = (libraries || []) + ((defined? LIBRARIES_SYSTEM) ? LIBRARIES_SYSTEM : [])
-    if (defined? LIBRARIES_FLAG)
-      args.map! {|v| LIBRARIES_FLAG.gsub(/\$\{1\}/, v) }
-    end
-    return args
-  end
-
-  def sort_objects_and_libraries(both)
-    extension = "\\" + ((defined? EXTENSION_SUBPROJECTS) ? EXTENSION_SUBPROJECTS : ".LIBRARY")
-    sorted_objects = both.group_by {|v| v.match(/.+#{extension}$/) ? :libraries : :objects }
-    libraries = sorted_objects[:libraries] || []
-    objects   = sorted_objects[:objects]   || []
-    return objects, libraries
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/release_invoker_helper.rb b/test/vendor/ceedling/lib/ceedling/release_invoker_helper.rb
deleted file mode 100644
index f83a2a53a..000000000
--- a/test/vendor/ceedling/lib/ceedling/release_invoker_helper.rb
+++ /dev/null
@@ -1,19 +0,0 @@
-
-
-class ReleaseInvokerHelper
-
-  constructor :configurator, :dependinator, :task_invoker
-
-
-  def process_deep_dependencies(dependencies_list)
-    return if (not @configurator.project_use_deep_dependencies)
-
-    if @configurator.project_generate_deep_dependencies
-      @dependinator.enhance_release_file_dependencies( dependencies_list )
-      @task_invoker.invoke_release_dependencies_files( dependencies_list )
-    end
-
-    @dependinator.load_release_object_deep_dependencies( dependencies_list )
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/reportinator.rb b/test/vendor/ceedling/lib/ceedling/reportinator.rb
deleted file mode 100644
index 0f583d06d..000000000
--- a/test/vendor/ceedling/lib/ceedling/reportinator.rb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-# Pretifies reports
-class Reportinator
-
-  ##
-  # Generates a banner for a message based on the length of the message or a
-  # given width.
-  # ==== Attributes
-  #
-  # * _message_:  The message to put.
-  # * _width_:    The width of the message. If nil the size of the banner is
-  # determined by the length of the message.
-  #
-  # ==== Examples
-  #
-  #    rp = Reportinator.new
-  #    rp.generate_banner("Hello world!") => "------------\nHello world!\n------------\n" 
-  #    rp.generate_banner("Hello world!", 3) => "---\nHello world!\n---\n" 
-  #
-  #
-  def generate_banner(message, width=nil)
-    dash_count = ((width.nil?) ? message.strip.length : width)
-    return "#{'-' * dash_count}\n#{message}\n#{'-' * dash_count}\n"
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/rules_cmock.rake b/test/vendor/ceedling/lib/ceedling/rules_cmock.rake
deleted file mode 100644
index 70ddcbc2e..000000000
--- a/test/vendor/ceedling/lib/ceedling/rules_cmock.rake
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-rule(/#{CMOCK_MOCK_PREFIX}[^\/\\]+#{'\\'+EXTENSION_SOURCE}$/ => [
-    proc do |task_name|
-      @ceedling[:file_finder].find_header_input_for_mock_file(task_name)
-    end  
-  ]) do |mock|
-  @ceedling[:generator].generate_mock(TEST_SYM, mock.source)
-end
diff --git a/test/vendor/ceedling/lib/ceedling/rules_preprocess.rake b/test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
deleted file mode 100644
index c29111272..000000000
--- a/test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
+++ /dev/null
@@ -1,26 +0,0 @@
-
-
-# invocations against this rule should only happen when enhanced dependencies are enabled;
-# otherwise, dependency tracking will be too shallow and preprocessed files could intermittently
-#  fail to be updated when they actually need to be.
-rule(/#{PROJECT_TEST_PREPROCESS_FILES_PATH}\/.+/ => [
-    proc do |task_name|
-      @ceedling[:file_finder].find_test_or_source_or_header_file(task_name)
-    end  
-  ]) do |file|
-  if (not @ceedling[:configurator].project_use_deep_dependencies)
-    raise 'ERROR: Ceedling preprocessing rule invoked though neccessary auxiliary dependency support not enabled.'
-  end
-  @ceedling[:generator].generate_preprocessed_file(TEST_SYM, file.source)
-end
-
-
-# invocations against this rule can always happen as there are no deeper dependencies to consider
-rule(/#{PROJECT_TEST_PREPROCESS_INCLUDES_PATH}\/.+/ => [
-    proc do |task_name|
-      @ceedling[:file_finder].find_test_or_source_or_header_file(task_name)
-    end  
-  ]) do |file|
-  @ceedling[:generator].generate_shallow_includes_list(TEST_SYM, file.source)
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/rules_release.rake b/test/vendor/ceedling/lib/ceedling/rules_release.rake
deleted file mode 100644
index ae39a76e3..000000000
--- a/test/vendor/ceedling/lib/ceedling/rules_release.rake
+++ /dev/null
@@ -1,86 +0,0 @@
-
-RELEASE_COMPILE_TASK_ROOT  = RELEASE_TASK_ROOT + 'compile:'  unless defined?(RELEASE_COMPILE_TASK_ROOT)
-RELEASE_ASSEMBLE_TASK_ROOT = RELEASE_TASK_ROOT + 'assemble:' unless defined?(RELEASE_ASSEMBLE_TASK_ROOT)
-
-
-if (RELEASE_BUILD_USE_ASSEMBLY)
-rule(/#{PROJECT_RELEASE_BUILD_OUTPUT_ASM_PATH}\/#{'.+\\'+EXTENSION_OBJECT}$/ => [
-    proc do |task_name|
-      @ceedling[:file_finder].find_assembly_file(task_name)
-    end
-  ]) do |object|
-  @ceedling[:generator].generate_object_file(
-    TOOLS_RELEASE_ASSEMBLER,
-    OPERATION_ASSEMBLE_SYM,
-    RELEASE_SYM,
-    object.source,
-    object.name )
-end
-end
-
-
-rule(/#{PROJECT_RELEASE_BUILD_OUTPUT_C_PATH}\/#{'.+\\'+EXTENSION_OBJECT}$/ => [
-    proc do |task_name|
-      @ceedling[:file_finder].find_compilation_input_file(task_name, :error, true)
-    end
-  ]) do |object|
-  @ceedling[:generator].generate_object_file(
-    TOOLS_RELEASE_COMPILER,
-    OPERATION_COMPILE_SYM,
-    RELEASE_SYM,
-    object.source,
-    object.name,
-    @ceedling[:file_path_utils].form_release_build_c_list_filepath( object.name ),
-    @ceedling[:file_path_utils].form_release_dependencies_filepath( object.name ) )
-end
-
-
-rule(/#{PROJECT_RELEASE_BUILD_TARGET}/) do |bin_file|
-  objects, libraries = @ceedling[:release_invoker].sort_objects_and_libraries(bin_file.prerequisites)
-  tool     = TOOLS_RELEASE_LINKER.clone
-  lib_args = @ceedling[:release_invoker].convert_libraries_to_arguments(libraries)
-  map_file = @ceedling[:configurator].project_release_build_map
-  @ceedling[:generator].generate_executable_file(
-    tool,
-    RELEASE_SYM,
-    objects,
-    bin_file.name,
-    map_file,
-    lib_args )
-  @ceedling[:release_invoker].artifactinate( bin_file.name, map_file, @ceedling[:configurator].release_build_artifacts )
-end
-
-
-namespace RELEASE_SYM do
-  # use rules to increase efficiency for large projects (instead of iterating through all sources and creating defined tasks)
-
-  namespace :compile do
-    rule(/^#{RELEASE_COMPILE_TASK_ROOT}\S+#{'\\'+EXTENSION_SOURCE}$/ => [ # compile task names by regex
-        proc do |task_name|
-          source = task_name.sub(/#{RELEASE_COMPILE_TASK_ROOT}/, '')
-          @ceedling[:file_finder].find_source_file(source, :error)
-        end
-    ]) do |compile|
-      @ceedling[:rake_wrapper][:directories].invoke
-      @ceedling[:project_config_manager].process_release_config_change
-      @ceedling[:release_invoker].setup_and_invoke_c_objects( [compile.source] )
-    end
-  end
-
-  if (RELEASE_BUILD_USE_ASSEMBLY)
-  namespace :assemble do
-    rule(/^#{RELEASE_ASSEMBLE_TASK_ROOT}\S+#{'\\'+EXTENSION_ASSEMBLY}$/ => [ # assemble task names by regex
-        proc do |task_name|
-          source = task_name.sub(/#{RELEASE_ASSEMBLE_TASK_ROOT}/, '')
-          @ceedling[:file_finder].find_assembly_file(source)
-        end
-    ]) do |assemble|
-      @ceedling[:rake_wrapper][:directories].invoke
-      @ceedling[:project_config_manager].process_release_config_change
-      @ceedling[:release_invoker].setup_and_invoke_asm_objects( [assemble.source] )
-    end
-  end
-  end
-
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake b/test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake
deleted file mode 100644
index 9550783cc..000000000
--- a/test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake
+++ /dev/null
@@ -1,15 +0,0 @@
-
-
-rule(/#{PROJECT_RELEASE_DEPENDENCIES_PATH}\/#{'.+\\'+EXTENSION_DEPENDENCIES}$/ => [
-    proc do |task_name|
-      @ceedling[:file_finder].find_compilation_input_file(task_name, :error, true)
-    end  
-  ]) do |dep|
-  @ceedling[:generator].generate_dependencies_file(
-  	TOOLS_RELEASE_DEPENDENCIES_GENERATOR,
-  	RELEASE_SYM,
-  	dep.source,
-  	@ceedling[:file_path_utils].form_release_build_c_object_filepath(dep.source),
-  	dep.name)
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/rules_tests.rake b/test/vendor/ceedling/lib/ceedling/rules_tests.rake
deleted file mode 100644
index 2b8f7af5b..000000000
--- a/test/vendor/ceedling/lib/ceedling/rules_tests.rake
+++ /dev/null
@@ -1,74 +0,0 @@
-
-
-rule(/#{PROJECT_TEST_FILE_PREFIX}#{'.+'+TEST_RUNNER_FILE_SUFFIX}#{'\\'+EXTENSION_SOURCE}$/ => [
-    proc do |task_name|
-      @ceedling[:file_finder].find_test_input_for_runner_file(task_name)
-    end
-  ]) do |runner|
-  @ceedling[:generator].generate_test_runner(TEST_SYM, runner.source, runner.name)
-end
-
-rule(/#{PROJECT_TEST_BUILD_OUTPUT_C_PATH}\/#{'.+\\'+EXTENSION_OBJECT}$/ => [
-    proc do |task_name|
-      @ceedling[:file_finder].find_compilation_input_file(task_name)
-    end
-  ]) do |object|
-  if (File.basename(object.source) =~ /#{EXTENSION_SOURCE}$/)
-    @ceedling[:generator].generate_object_file(
-      TOOLS_TEST_COMPILER,
-      OPERATION_COMPILE_SYM,
-      TEST_SYM,
-      object.source,
-      object.name,
-      @ceedling[:file_path_utils].form_test_build_list_filepath( object.name ),
-      @ceedling[:file_path_utils].form_test_dependencies_filepath( object.name ))
-  elsif (defined?(TEST_BUILD_USE_ASSEMBLY) && TEST_BUILD_USE_ASSEMBLY)
-    @ceedling[:generator].generate_object_file(
-      TOOLS_TEST_ASSEMBLER,
-      OPERATION_ASSEMBLE_SYM,
-      TEST_SYM,
-      object.source,
-      object.name )
-  end
-end
-
-
-rule(/#{PROJECT_TEST_BUILD_OUTPUT_PATH}\/#{'.+\\'+EXTENSION_EXECUTABLE}$/) do |bin_file|
-
-  lib_args = @ceedling[:test_invoker].convert_libraries_to_arguments()
-
-  @ceedling[:generator].generate_executable_file(
-    TOOLS_TEST_LINKER,
-    TEST_SYM,
-    bin_file.prerequisites,
-    bin_file.name,
-    @ceedling[:file_path_utils].form_test_build_map_filepath( bin_file.name ),
-    lib_args )
-end
-
-
-rule(/#{PROJECT_TEST_RESULTS_PATH}\/#{'.+\\'+EXTENSION_TESTPASS}$/ => [
-    proc do |task_name|
-      @ceedling[:file_path_utils].form_test_executable_filepath(task_name)
-    end
-  ]) do |test_result|
-  @ceedling[:generator].generate_test_results(TOOLS_TEST_FIXTURE, TEST_SYM, test_result.source, test_result.name)
-end
-
-
-namespace TEST_SYM do
-  # use rules to increase efficiency for large projects (instead of iterating through all sources and creating defined tasks)
-
-  rule(/^#{TEST_TASK_ROOT}\S+$/ => [ # test task names by regex
-      proc do |task_name|
-        test = task_name.sub(/#{TEST_TASK_ROOT}/, '')
-        test = "#{PROJECT_TEST_FILE_PREFIX}#{test}" if not (test.start_with?(PROJECT_TEST_FILE_PREFIX))
-        @ceedling[:file_finder].find_test_from_file_path(test)
-      end
-  ]) do |test|
-    @ceedling[:rake_wrapper][:directories].reenable if @ceedling[:task_invoker].first_run == false && @ceedling[:project_config_manager].test_defines_changed
-    @ceedling[:rake_wrapper][:directories].invoke
-    @ceedling[:test_invoker].setup_and_invoke([test.source])
-  end
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake b/test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake
deleted file mode 100644
index 7175ee3f2..000000000
--- a/test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake
+++ /dev/null
@@ -1,15 +0,0 @@
-
-
-rule(/#{PROJECT_TEST_DEPENDENCIES_PATH}\/#{'.+\\'+EXTENSION_DEPENDENCIES}$/ => [
-    proc do |task_name|
-      @ceedling[:file_finder].find_compilation_input_file(task_name)
-    end
-  ]) do |dep|
-  @ceedling[:generator].generate_dependencies_file(
-  	TOOLS_TEST_DEPENDENCIES_GENERATOR,
-    TEST_SYM,
-  	dep.source,
-  	@ceedling[:file_path_utils].form_test_build_c_object_filepath(dep.source),
-  	dep.name)
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/setupinator.rb b/test/vendor/ceedling/lib/ceedling/setupinator.rb
deleted file mode 100644
index 8347b42ab..000000000
--- a/test/vendor/ceedling/lib/ceedling/setupinator.rb
+++ /dev/null
@@ -1,53 +0,0 @@
-
-class Setupinator
-
-  attr_reader :config_hash
-  attr_writer :ceedling
-
-  def setup
-    @ceedling = {}
-    @config_hash = {}
-  end
-
-  def load_project_files
-    @ceedling[:project_file_loader].find_project_files
-    return @ceedling[:project_file_loader].load_project_config
-  end
-
-  def do_setup(config_hash)
-    @config_hash = config_hash
-
-    # load up all the constants and accessors our rake files, objects, & external scripts will need;
-    # note: configurator modifies the cmock section of the hash with a couple defaults to tie 
-    #       project together - the modified hash is used to build cmock object
-    @ceedling[:configurator].populate_defaults( config_hash )
-    @ceedling[:configurator].populate_unity_defaults( config_hash )
-    @ceedling[:configurator].populate_cmock_defaults( config_hash )
-    @ceedling[:configurator].find_and_merge_plugins( config_hash )
-    @ceedling[:configurator].merge_imports( config_hash )
-    @ceedling[:configurator].tools_setup( config_hash )
-    @ceedling[:configurator].eval_environment_variables( config_hash )
-    @ceedling[:configurator].eval_paths( config_hash )
-    @ceedling[:configurator].standardize_paths( config_hash )
-    @ceedling[:configurator].validate( config_hash )
-    @ceedling[:configurator].build( config_hash, :environment )
-    
-    @ceedling[:configurator].insert_rake_plugins( @ceedling[:configurator].rake_plugins )
-    @ceedling[:configurator].tools_supplement_arguments( config_hash )
-    
-    # merge in any environment variables plugins specify, after the main build
-    @ceedling[:plugin_manager].load_plugin_scripts( @ceedling[:configurator].script_plugins, @ceedling ) do |env|
-      @ceedling[:configurator].eval_environment_variables( env )
-      @ceedling[:configurator].build_supplement( config_hash, env )
-    end
-    
-    @ceedling[:plugin_reportinator].set_system_objects( @ceedling )
-    @ceedling[:file_finder].prepare_search_sources
-    @ceedling[:loginator].setup_log_filepath
-    @ceedling[:project_config_manager].config_hash = config_hash
-  end
-
-  def reset_defaults(config_hash)
-    @ceedling[:configurator].reset_defaults( config_hash )
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/stream_wrapper.rb b/test/vendor/ceedling/lib/ceedling/stream_wrapper.rb
deleted file mode 100644
index 7e160527f..000000000
--- a/test/vendor/ceedling/lib/ceedling/stream_wrapper.rb
+++ /dev/null
@@ -1,28 +0,0 @@
-
-class StreamWrapper
-
-  def stdout_override(&fnc)
-    @stdout_overide_fnc = fnc
-  end
-
-  def stdout_puts(string)
-    if @stdout_overide_fnc
-      @stdout_overide_fnc.call(string)
-    else
-      $stdout.puts(string)
-    end
-  end
-
-  def stdout_flush
-    $stdout.flush
-  end
-  
-  def stderr_puts(string)
-    $stderr.puts(string)
-  end
-
-  def stderr_flush
-    $stderr.flush
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/streaminator.rb b/test/vendor/ceedling/lib/ceedling/streaminator.rb
deleted file mode 100644
index b8dcd070f..000000000
--- a/test/vendor/ceedling/lib/ceedling/streaminator.rb
+++ /dev/null
@@ -1,40 +0,0 @@
-require 'ceedling/constants'
-
-class Streaminator
-
-  constructor :streaminator_helper, :verbosinator, :loginator, :stream_wrapper
-
-  # for those objects for whom the configurator has already been instantiated,
-  # Streaminator is a convenience object for handling verbosity and writing to the std streams
-
-  def stdout_puts(string, verbosity=Verbosity::NORMAL)
-    if (@verbosinator.should_output?(verbosity))
-      @stream_wrapper.stdout_puts(string)
-      @stream_wrapper.stdout_flush
-    end
-    
-    # write to log as though Verbosity::OBNOXIOUS
-    @loginator.log( string, @streaminator_helper.extract_name($stdout) )
-  end
-
-  def stderr_puts(string, verbosity=Verbosity::NORMAL)
-    if (@verbosinator.should_output?(verbosity))
-      @stream_wrapper.stderr_puts(string)
-      @stream_wrapper.stderr_flush
-    end
-
-    # write to log as though Verbosity::OBNOXIOUS
-    @loginator.log( string, @streaminator_helper.extract_name($stderr) )
-  end
-
-  def stream_puts(stream, string, verbosity=Verbosity::NORMAL)
-    if (@verbosinator.should_output?(verbosity))
-      stream.puts(string)
-      stream.flush
-    end
-
-    # write to log as though Verbosity::OBNOXIOUS
-    @loginator.log( string, @streaminator_helper.extract_name(stream) )
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/streaminator_helper.rb b/test/vendor/ceedling/lib/ceedling/streaminator_helper.rb
deleted file mode 100644
index 9fb5cc0b7..000000000
--- a/test/vendor/ceedling/lib/ceedling/streaminator_helper.rb
+++ /dev/null
@@ -1,15 +0,0 @@
-
-class StreaminatorHelper
-
-  def extract_name(stream)
-    name = case (stream.fileno)
-      when 0 then '#<IO:$stdin>'
-      when 1 then '#<IO:$stdout>'
-      when 2 then '#<IO:$stderr>'
-      else stream.inspect
-    end
-    
-    return name
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/system_utils.rb b/test/vendor/ceedling/lib/ceedling/system_utils.rb
deleted file mode 100644
index 477aba4f1..000000000
--- a/test/vendor/ceedling/lib/ceedling/system_utils.rb
+++ /dev/null
@@ -1,37 +0,0 @@
-
-class Object
-  def deep_clone
-    Marshal::load(Marshal.dump(self))
-  end
-end
-
-
-##
-# Class containing system utility funcions.
-class SystemUtils
-
-  constructor :system_wrapper
-
-  ##
-  # Sets up the class. 
-  def setup
-    @tcsh_shell = nil
-  end
-
-  ##
-  # Checks the system shell to see if it a tcsh shell.
-  def tcsh_shell?
-    # once run a single time, return state determined at that execution
-    return @tcsh_shell if not @tcsh_shell.nil?
-  
-    result = @system_wrapper.shell_backticks('echo $version')
-
-    if ((result[:exit_code] == 0) and (result[:output].strip =~ /^tcsh/))
-      @tcsh_shell = true
-    else
-      @tcsh_shell = false
-    end
-  
-    return @tcsh_shell
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/system_wrapper.rb b/test/vendor/ceedling/lib/ceedling/system_wrapper.rb
deleted file mode 100644
index 2b0f1edda..000000000
--- a/test/vendor/ceedling/lib/ceedling/system_wrapper.rb
+++ /dev/null
@@ -1,80 +0,0 @@
-require 'rbconfig'
-
-class SystemWrapper
-
-  # static method for use in defaults
-  def self.windows?
-    return ((RbConfig::CONFIG['host_os'] =~ /mswin|mingw/) ? true : false) if defined?(RbConfig)
-    return ((Config::CONFIG['host_os'] =~ /mswin|mingw/) ? true : false)
-  end
-
-  # class method so as to be mockable for tests
-  def windows?
-    return SystemWrapper.windows?
-  end
-
-  def module_eval(string)
-    return Object.module_eval("\"" + string + "\"")
-  end
-
-  def eval(string)
-    return eval(string)
-  end
-
-  def search_paths
-    return ENV['PATH'].split(File::PATH_SEPARATOR)
-  end
-
-  def cmdline_args
-    return ARGV
-  end
-
-  def env_set(name, value)
-    ENV[name] = value
-  end
-
-  def env_get(name)
-    return ENV[name]
-  end
-
-  def time_now
-    return Time.now.asctime
-  end
-
-  def shell_backticks(command, boom = true)
-    retval = `#{command}`.freeze
-    $exit_code = ($?.exitstatus).freeze if boom
-    return {
-      :output    => retval.freeze,
-      :exit_code => ($?.exitstatus).freeze
-    }
-  end
-
-  def shell_system(command, boom = true)
-    system( command )
-    $exit_code = ($?.exitstatus).freeze if boom
-    return {
-      :output    => "".freeze,
-      :exit_code => ($?.exitstatus).freeze
-    }
-  end
-
-  def add_load_path(path)
-    $LOAD_PATH.unshift(path)
-  end
-
-  def require_file(path)
-    require(path)
-  end
-
-  def ruby_success
-    # We are successful if we've never had an exit code that went boom (either because it's empty or it was 0)
-    return ($exit_code.nil? || ($exit_code == 0)) && ($!.nil? || $!.is_a?(SystemExit) && $!.success?)
-  end
-
-  def constants_include?(item)
-    # forcing to strings provides consistency across Ruby versions
-    return Object.constants.map{|constant| constant.to_s}.include?(item.to_s)
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/target_loader.rb b/test/vendor/ceedling/lib/ceedling/target_loader.rb
deleted file mode 100644
index 7fbc09591..000000000
--- a/test/vendor/ceedling/lib/ceedling/target_loader.rb
+++ /dev/null
@@ -1,38 +0,0 @@
-module TargetLoader
-  class NoTargets    < Exception; end
-  class NoDirectory  < Exception; end
-  class NoDefault    < Exception; end
-  class NoSuchTarget < Exception; end
-
-  class RequestReload < Exception; end
-
-  def self.inspect(config, target_name=nil)
-    unless config[:targets]
-      raise NoTargets
-    end
-
-    targets = config[:targets]
-    unless targets[:targets_directory]
-      raise NoDirectory.new("No targets directory specified.")
-    end
-    unless targets[:default_target]
-      raise NoDefault.new("No default target specified.")
-    end
-
-    target_path = lambda {|name| File.join(targets[:targets_directory], name + ".yml")}
-
-    target = if target_name
-               target_path.call(target_name)
-             else
-               target_path.call(targets[:default_target])
-             end
-
-    unless File.exists? target
-      raise NoSuchTarget.new("No such target: #{target}")
-    end
-
-    ENV['CEEDLING_MAIN_PROJECT_FILE'] = target
-
-    raise RequestReload
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/task_invoker.rb b/test/vendor/ceedling/lib/ceedling/task_invoker.rb
deleted file mode 100644
index 642695c46..000000000
--- a/test/vendor/ceedling/lib/ceedling/task_invoker.rb
+++ /dev/null
@@ -1,117 +0,0 @@
-require 'ceedling/par_map'
-
-class TaskInvoker
-
-  attr_accessor :first_run
-
-  constructor :dependinator, :rake_utils, :rake_wrapper, :project_config_manager
-
-  def setup
-    @test_regexs = [/^#{TEST_ROOT_NAME}:/]
-    @release_regexs = [/^#{RELEASE_ROOT_NAME}(:|$)/]
-    @first_run = true
-  end
-  
-  def add_test_task_regex(regex)
-    @test_regexs << regex
-  end
-
-  def add_release_task_regex(regex)
-    @release_regexs << regex
-  end
-  
-  def test_invoked?
-    invoked = false
-    
-    @test_regexs.each do |regex|
-      invoked = true if (@rake_utils.task_invoked?(regex))
-      break if invoked
-    end
-    
-    return invoked
-  end
-  
-  def release_invoked?
-    invoked = false
-    
-    @release_regexs.each do |regex|
-      invoked = true if (@rake_utils.task_invoked?(regex))
-      break if invoked
-    end
-    
-    return invoked
-  end
-
-  def invoked?(regex)
-    return @rake_utils.task_invoked?(regex)
-  end
-
-  
-  def invoke_test_mocks(mocks)
-    @dependinator.enhance_mock_dependencies( mocks )
-    mocks.each { |mock|
-      @rake_wrapper[mock].reenable if @first_run == false && @project_config_manager.test_defines_changed
-      @rake_wrapper[mock].invoke
-    }
-  end
-  
-  def invoke_test_runner(runner)
-    @dependinator.enhance_runner_dependencies( runner )
-    @rake_wrapper[runner].reenable if @first_run == false && @project_config_manager.test_defines_changed
-    @rake_wrapper[runner].invoke
-  end
-
-  def invoke_test_shallow_include_lists(files)
-    @dependinator.enhance_shallow_include_lists_dependencies( files )
-    par_map(PROJECT_COMPILE_THREADS, files) do |file|
-      @rake_wrapper[file].reenable if @first_run == false && @project_config_manager.test_defines_changed
-      @rake_wrapper[file].invoke
-    end
-  end
-
-  def invoke_test_preprocessed_files(files)
-    @dependinator.enhance_preprocesed_file_dependencies( files )
-    par_map(PROJECT_COMPILE_THREADS, files) do |file|
-      @rake_wrapper[file].reenable if @first_run == false && @project_config_manager.test_defines_changed
-      @rake_wrapper[file].invoke
-    end
-  end
-
-  def invoke_test_dependencies_files(files)
-    @dependinator.enhance_dependencies_dependencies( files )
-    par_map(PROJECT_COMPILE_THREADS, files) do |file|
-      @rake_wrapper[file].reenable if @first_run == false && @project_config_manager.test_defines_changed
-      @rake_wrapper[file].invoke
-    end
-  end
-
-  def invoke_test_objects(objects)
-    par_map(PROJECT_COMPILE_THREADS, objects) do |object|
-      @rake_wrapper[object].reenable if @first_run == false && @project_config_manager.test_defines_changed
-      @rake_wrapper[object].invoke
-    end
-  end
-
-  def invoke_test_executable(file)
-    @rake_wrapper[file].invoke
-  end
-
-  def invoke_test_results(result)
-    @dependinator.enhance_results_dependencies( result )
-    @rake_wrapper[result].reenable if @first_run == false && @project_config_manager.test_defines_changed
-    @rake_wrapper[result].invoke
-  end
-
-  def invoke_release_dependencies_files(files)
-    par_map(PROJECT_COMPILE_THREADS, files) do |file|
-      @rake_wrapper[file].invoke
-    end
-  end
-  
-  def invoke_release_objects(objects)
-    par_map(PROJECT_COMPILE_THREADS, objects) do |object|
-      @rake_wrapper[object].invoke
-    end
-  end
-  
-end
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_base.rake b/test/vendor/ceedling/lib/ceedling/tasks_base.rake
deleted file mode 100644
index 8c8253099..000000000
--- a/test/vendor/ceedling/lib/ceedling/tasks_base.rake
+++ /dev/null
@@ -1,111 +0,0 @@
-require 'ceedling/constants'
-require 'ceedling/file_path_utils'
-require 'ceedling/version'
-
-desc "Display build environment version info."
-task :version do
-  puts "  Ceedling:: #{Ceedling::Version::CEEDLING}"
-
-  [
-      ['CException', File.join( CEEDLING_VENDOR, CEXCEPTION_ROOT_PATH)],
-      ['     CMock', File.join( CEEDLING_VENDOR, CMOCK_ROOT_PATH)],
-      ['     Unity', File.join( CEEDLING_VENDOR, UNITY_ROOT_PATH)],
-  ].each do |tool|
-    name      = tool[0]
-    base_path = tool[1]
-
-    version_string = begin
-      @ceedling[:file_wrapper].read( File.join(base_path, 'release', 'version.info') ).strip
-    rescue
-      "UNKNOWN"
-    end
-    build_string = begin
-      @ceedling[:file_wrapper].read( File.join(base_path, 'release', 'build.info') ).strip
-    rescue
-      "UNKNOWN"
-    end
-    puts "#{name}:: #{version_string.empty? ? '#.#.' : (version_string + '.')}#{build_string.empty? ? '?' : build_string}"
-  end
-end
-
-desc "Set verbose output (silent:[#{Verbosity::SILENT}] - obnoxious:[#{Verbosity::OBNOXIOUS}])."
-task :verbosity, :level do |t, args|
-  verbosity_level = args.level.to_i
-
-  if (PROJECT_USE_MOCKS)
-    # don't store verbosity level in setupinator's config hash, use a copy;
-    # otherwise, the input configuration will change and trigger entire project rebuilds
-    hash = @ceedling[:setupinator].config_hash[:cmock].clone
-    hash[:verbosity] = verbosity_level
-
-    @ceedling[:cmock_builder].manufacture( hash )
-  end
-
-  @ceedling[:configurator].project_verbosity = verbosity_level
-
-  # control rake's verbosity with new setting
-  verbose( ((verbosity_level >= Verbosity::OBNOXIOUS) ? true : false) )
-end
-
-desc "Enable logging"
-task :logging do
-  @ceedling[:configurator].project_logging = true
-end
-
-# non advertised debug task
-task :debug do
-  Rake::Task[:verbosity].invoke(Verbosity::DEBUG)
-  Rake.application.options.trace = true
-  @ceedling[:configurator].project_debug = true
-end
-
-# non advertised sanity checking task
-task :sanity_checks, :level do |t, args|
-  check_level = args.level.to_i
-  @ceedling[:configurator].sanity_checks = check_level
-end
-
-# list expanded environment variables
-if (not ENVIRONMENT.empty?)
-desc "List all configured environment variables."
-task :environment do
-  env_list = []
-  ENVIRONMENT.each do |env|
-    env.each_key do |key|
-      name = key.to_s.upcase
-	  env_list.push(" - #{name}: \"#{env[key]}\"")      
-    end
-  end
-  env_list.sort.each do |env_line|
-	puts env_line
-  end
-end
-end
-
-namespace :options do
-
-  COLLECTION_PROJECT_OPTIONS.each do |option_path|
-    option = File.basename(option_path, '.yml')
-
-    desc "Merge #{option} project options."
-    task option.downcase.to_sym do
-      hash = @ceedling[:project_config_manager].merge_options( @ceedling[:setupinator].config_hash, option_path )
-      @ceedling[:setupinator].do_setup( hash )
-      if @ceedling[:configurator].project_release_build
-        load(File.join(CEEDLING_LIB, 'ceedling', 'rules_release.rake'))
-      end
-    end
-  end
-
-end
-
-
-# do not present task if there's no plugins
-if (not PLUGINS_ENABLED.empty?)
-desc "Execute plugin result summaries (no build triggering)."
-task :summary do
-	@ceedling[:plugin_manager].summary
-  puts "\nNOTE: Summaries may be out of date with project sources.\n\n"
-end
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake b/test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake
deleted file mode 100644
index 58fa6511f..000000000
--- a/test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake
+++ /dev/null
@@ -1,103 +0,0 @@
-
-# rather than require 'rake/clean' & try to override, we replicate for finer control
-CLEAN   = Rake::FileList["**/*~", "**/*.bak"]
-CLOBBER = Rake::FileList.new
-
-CLEAN.clear_exclude.exclude { |fn| fn.pathmap("%f") == 'core' && File.directory?(fn) }
-
-CLEAN.include(File.join(PROJECT_TEST_BUILD_OUTPUT_PATH, '*'))
-CLEAN.include(File.join(PROJECT_TEST_RESULTS_PATH, '*'))
-CLEAN.include(File.join(PROJECT_TEST_DEPENDENCIES_PATH, '*'))
-CLEAN.include(File.join(PROJECT_BUILD_RELEASE_ROOT, '*.*'))
-CLEAN.include(File.join(PROJECT_RELEASE_BUILD_OUTPUT_PATH, '*'))
-CLEAN.include(File.join(PROJECT_RELEASE_DEPENDENCIES_PATH, '*'))
-
-CLOBBER.include(File.join(PROJECT_BUILD_ARTIFACTS_ROOT, '**/*'))
-CLOBBER.include(File.join(PROJECT_BUILD_TESTS_ROOT, '**/*'))
-CLOBBER.include(File.join(PROJECT_BUILD_RELEASE_ROOT, '**/*'))
-CLOBBER.include(File.join(PROJECT_LOG_PATH, '**/*'))
-CLOBBER.include(File.join(PROJECT_TEMP_PATH, '**/*'))
-
-# just in case they're using git, let's make sure we allow them to preserved the build directory if desired.
-CLOBBER.exclude(File.join(TESTS_BASE_PATH), '**/.gitkeep')
-
-# because of cmock config, mock path can optionally exist apart from standard test build paths
-CLOBBER.include(File.join(CMOCK_MOCK_PATH, '*'))
-
-REMOVE_FILE_PROC = Proc.new { |fn| rm_r fn rescue nil }
-
-# redefine clean so we can override how it advertises itself
-desc "Delete all build artifacts and temporary products."
-task(:clean) do
-  # because :clean is a prerequisite for :clobber, intelligently display the progress message
-  if (not @ceedling[:task_invoker].invoked?(/^clobber$/))
-    @ceedling[:streaminator].stdout_puts("\nCleaning build artifacts...\n(For large projects, this task may take a long time to complete)\n\n")
-  end
-  begin
-    CLEAN.each { |fn| REMOVE_FILE_PROC.call(fn) }
-  rescue
-  end
-end
-
-# redefine clobber so we can override how it advertises itself
-desc "Delete all generated files (and build artifacts)."
-task(:clobber => [:clean]) do
-  @ceedling[:streaminator].stdout_puts("\nClobbering all generated files...\n(For large projects, this task may take a long time to complete)\n\n")
-  begin
-    CLOBBER.each { |fn| REMOVE_FILE_PROC.call(fn) }
-  rescue
-  end
-end
-
-
-PROJECT_BUILD_PATHS.each { |path| directory(path) }
-
-# create directories that hold build output and generated files & touching rebuild dependency sources
-task(:directories => PROJECT_BUILD_PATHS) { @ceedling[:dependinator].touch_force_rebuild_files }
-
-
-# list paths discovered at load time
-namespace :paths do
-
-  paths = @ceedling[:setupinator].config_hash[:paths]
-  paths.each_key do |section|
-    name = section.to_s.downcase
-    path_list = Object.const_get("COLLECTION_PATHS_#{name.upcase}")
-
-    if (path_list.size != 0)
-      desc "List all collected #{name} paths."
-      task(name.to_sym) { puts "#{name} paths:"; path_list.sort.each {|path| puts " - #{path}" } }
-    end
-  end
-
-end
-
-
-# list files & file counts discovered at load time
-namespace :files do
-
-  categories = [
-    ['test',   COLLECTION_ALL_TESTS],
-    ['source', COLLECTION_ALL_SOURCE],
-    ['header', COLLECTION_ALL_HEADERS]
-    ]
-
-  using_assembly = (defined?(TEST_BUILD_USE_ASSEMBLY) && TEST_BUILD_USE_ASSEMBLY) ||
-                   (defined?(RELEASE_BUILD_USE_ASSEMBLY) && RELEASE_BUILD_USE_ASSEMBLY)
-  categories << ['assembly', COLLECTION_ALL_ASSEMBLY] if using_assembly
-
-  categories.each do |category|
-    name       = category[0]
-    collection = category[1]
-
-    desc "List all collected #{name} files."
-    task(name.to_sym) do
-      puts "#{name} files:"
-      collection.sort.each { |filepath| puts " - #{filepath}" }
-      puts "file count: #{collection.size}"
-    end
-  end
-
-end
-
-
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_release.rake b/test/vendor/ceedling/lib/ceedling/tasks_release.rake
deleted file mode 100644
index b313b2f53..000000000
--- a/test/vendor/ceedling/lib/ceedling/tasks_release.rake
+++ /dev/null
@@ -1,30 +0,0 @@
-require 'ceedling/constants'
-require 'ceedling/file_path_utils'
-
-
-desc "Build release target."
-task RELEASE_SYM => [:directories] do
-  header = "Release build '#{File.basename(PROJECT_RELEASE_BUILD_TARGET)}'"
-  @ceedling[:streaminator].stdout_puts("\n\n#{header}\n#{'-' * header.length}")  
-  
-  begin
-    @ceedling[:plugin_manager].pre_release
-
-    core_objects  = []
-    extra_objects = @ceedling[:file_path_utils].form_release_build_c_objects_filelist( COLLECTION_RELEASE_ARTIFACT_EXTRA_LINK_OBJECTS )
-
-    @ceedling[:project_config_manager].process_release_config_change
-    core_objects.concat( @ceedling[:release_invoker].setup_and_invoke_c_objects( COLLECTION_ALL_SOURCE ) )
-  
-    # if assembler use isn't enabled, COLLECTION_ALL_ASSEMBLY is empty array & nothing happens
-    core_objects.concat( @ceedling[:release_invoker].setup_and_invoke_asm_objects( COLLECTION_ALL_ASSEMBLY ) )
-  
-    # if we're using libraries, we need to add those to our collection as well
-    library_objects = (defined? LIBRARIES_RELEASE && !LIBRARIES_RELEASE.empty?) ? LIBRARIES_RELEASE.flatten.compact : []
-    file( PROJECT_RELEASE_BUILD_TARGET => (core_objects + extra_objects + library_objects) )
-    Rake::Task[PROJECT_RELEASE_BUILD_TARGET].invoke
-  ensure
-    @ceedling[:plugin_manager].post_release  
-  end
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_release_deep_dependencies.rake b/test/vendor/ceedling/lib/ceedling/tasks_release_deep_dependencies.rake
deleted file mode 100644
index db2be5f34..000000000
--- a/test/vendor/ceedling/lib/ceedling/tasks_release_deep_dependencies.rake
+++ /dev/null
@@ -1,9 +0,0 @@
-require 'ceedling/constants'
-
-namespace REFRESH_SYM do
-
-  task RELEASE_SYM do
-    @ceedling[:release_invoker].refresh_c_deep_dependencies
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_tests.rake b/test/vendor/ceedling/lib/ceedling/tasks_tests.rake
deleted file mode 100644
index 5d09c1aff..000000000
--- a/test/vendor/ceedling/lib/ceedling/tasks_tests.rake
+++ /dev/null
@@ -1,60 +0,0 @@
-require 'ceedling/constants'
-
-task :test => [:directories] do
-  Rake.application['test:all'].invoke
-end
-
-namespace TEST_SYM do
-
-  desc "Run all unit tests (also just 'test' works)."
-  task :all => [:directories] do
-    @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS)
-  end
-
-  desc "Run single test ([*] real test or source file name, no path)."
-  task :* do
-    message = "\nOops! '#{TEST_ROOT_NAME}:*' isn't a real task. " +
-              "Use a real test or source file name (no path) in place of the wildcard.\n" +
-              "Example: rake #{TEST_ROOT_NAME}:foo.c\n\n"
-
-    @ceedling[:streaminator].stdout_puts( message )
-  end
-
-  desc "Run tests for changed files."
-  task :delta => [:directories] do
-    @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, TEST_SYM, {:force_run => false})
-  end
-
-  desc "Just build tests without running."
-  task :build_only => [:directories] do
-    @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, TEST_SYM, {:build_only => true})
-  end
-
-  desc "Run tests by matching regular expression pattern."
-  task :pattern, [:regex] => [:directories] do |t, args|
-    matches = []
-
-    COLLECTION_ALL_TESTS.each { |test| matches << test if (test =~ /#{args.regex}/) }
-
-    if (matches.size > 0)
-      @ceedling[:test_invoker].setup_and_invoke(matches, TEST_SYM, {:force_run => false})
-    else
-      @ceedling[:streaminator].stdout_puts("\nFound no tests matching pattern /#{args.regex}/.")
-    end
-  end
-
-  desc "Run tests whose test path contains [dir] or [dir] substring."
-  task :path, [:dir] => [:directories] do |t, args|
-    matches = []
-
-    COLLECTION_ALL_TESTS.each { |test| matches << test if File.dirname(test).include?(args.dir.gsub(/\\/, '/')) }
-
-    if (matches.size > 0)
-      @ceedling[:test_invoker].setup_and_invoke(matches, TEST_SYM, {:force_run => false})
-    else
-      @ceedling[:streaminator].stdout_puts("\nFound no tests including the given path or path component.")
-    end
-  end
-
-end
-
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_tests_deep_dependencies.rake b/test/vendor/ceedling/lib/ceedling/tasks_tests_deep_dependencies.rake
deleted file mode 100644
index f89940716..000000000
--- a/test/vendor/ceedling/lib/ceedling/tasks_tests_deep_dependencies.rake
+++ /dev/null
@@ -1,9 +0,0 @@
-require 'ceedling/constants'
-
-namespace REFRESH_SYM do
-
-  task TEST_SYM do
-    @ceedling[:test_invoker].refresh_deep_dependencies
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_vendor.rake b/test/vendor/ceedling/lib/ceedling/tasks_vendor.rake
deleted file mode 100644
index 63c2ca55b..000000000
--- a/test/vendor/ceedling/lib/ceedling/tasks_vendor.rake
+++ /dev/null
@@ -1,35 +0,0 @@
-require 'ceedling/constants'
-require 'ceedling/file_path_utils'
-
-# create file dependencies to ensure C-based components of vendor tools are recompiled when they are updated with new versions
-# forming these explicitly rather than depend on auxiliary dependencies so all scenarios are explicitly covered
-
-file( @ceedling[:file_path_utils].form_test_build_c_object_filepath( UNITY_C_FILE ) => [
-  File.join( UNITY_VENDOR_PATH, UNITY_LIB_PATH, UNITY_C_FILE ),
-  File.join( UNITY_VENDOR_PATH, UNITY_LIB_PATH, UNITY_H_FILE ),
-  File.join( UNITY_VENDOR_PATH, UNITY_LIB_PATH, UNITY_INTERNALS_H_FILE ) ]
-  )
-
-
-if (PROJECT_USE_MOCKS)
-file( @ceedling[:file_path_utils].form_test_build_c_object_filepath( CMOCK_C_FILE ) => [
-  File.join( CMOCK_VENDOR_PATH, CMOCK_LIB_PATH, CMOCK_C_FILE ),
-  File.join( CMOCK_VENDOR_PATH, CMOCK_LIB_PATH, CMOCK_H_FILE ) ]
-  )
-end
-
-
-if (PROJECT_USE_EXCEPTIONS)
-file( @ceedling[:file_path_utils].form_test_build_c_object_filepath( CEXCEPTION_C_FILE ) => [
-  File.join( CEXCEPTION_VENDOR_PATH, CEXCEPTION_LIB_PATH, CEXCEPTION_C_FILE ),
-  File.join( CEXCEPTION_VENDOR_PATH, CEXCEPTION_LIB_PATH, CEXCEPTION_H_FILE ) ]
-  )
-end
-
-
-if (PROJECT_USE_EXCEPTIONS and PROJECT_RELEASE_BUILD)
-file( @ceedling[:file_path_utils].form_release_build_c_object_filepath( CEXCEPTION_C_FILE ) => [
-  File.join( CEXCEPTION_VENDOR_PATH, CEXCEPTION_LIB_PATH, CEXCEPTION_C_FILE ),
-  File.join( CEXCEPTION_VENDOR_PATH, CEXCEPTION_LIB_PATH, CEXCEPTION_H_FILE ) ]
-  )
-end
diff --git a/test/vendor/ceedling/lib/ceedling/test_includes_extractor.rb b/test/vendor/ceedling/lib/ceedling/test_includes_extractor.rb
deleted file mode 100644
index 50cc7c041..000000000
--- a/test/vendor/ceedling/lib/ceedling/test_includes_extractor.rb
+++ /dev/null
@@ -1,85 +0,0 @@
-
-class TestIncludesExtractor
-
-  constructor :configurator, :yaml_wrapper, :file_wrapper
-
-  def setup
-    @includes  = {}
-    @mocks     = {}
-  end
-
-
-  # for includes_list file, slurp up array from yaml file and sort & store includes
-  def parse_includes_list(includes_list)
-    gather_and_store_includes( includes_list, @yaml_wrapper.load(includes_list) )
-  end
-
-  # open, scan for, and sort & store includes of test file
-  def parse_test_file(test)
-    gather_and_store_includes( test, extract_from_file(test) )
-  end
-
-  # mocks with no file extension
-  def lookup_raw_mock_list(test)
-    file_key = form_file_key(test)
-    return [] if @mocks[file_key].nil?
-    return @mocks[file_key]
-  end
-
-  # includes with file extension
-  def lookup_includes_list(file)
-    file_key = form_file_key(file)
-    return [] if (@includes[file_key]).nil?
-    return @includes[file_key]
-  end
-
-  private #################################
-
-  def form_file_key(filepath)
-    return File.basename(filepath).to_sym
-  end
-
-  def extract_from_file(file)
-    includes = []
-    header_extension = @configurator.extension_header
-
-    contents = @file_wrapper.read(file)
-
-    # remove line comments
-    contents = contents.gsub(/\/\/.*$/, '')
-    # remove block comments
-    contents = contents.gsub(/\/\*.*?\*\//m, '')
-
-    contents.split("\n").each do |line|
-      # look for include statement
-      scan_results = line.scan(/#include\s+\"\s*(.+#{'\\'+header_extension})\s*\"/)
-
-      includes << scan_results[0][0] if (scan_results.size > 0)
-
-      # look for TEST_FILE statement
-      scan_results = line.scan(/TEST_FILE\(\s*\"\s*(.+\.\w+)\s*\"\s*\)/)
-
-      includes << scan_results[0][0] if (scan_results.size > 0)
-    end
-
-    return includes.uniq
-  end
-
-  def gather_and_store_includes(file, includes)
-    mock_prefix      = @configurator.cmock_mock_prefix
-    header_extension = @configurator.extension_header
-    file_key         = form_file_key(file)
-    @mocks[file_key] = []
-
-    # add includes to lookup hash
-    @includes[file_key] = includes
-
-    includes.each do |include_file|
-      # check if include is a mock
-      scan_results = include_file.scan(/(#{mock_prefix}.+)#{'\\'+header_extension}/)
-      # add mock to lookup hash
-      @mocks[file_key] << scan_results[0][0] if (scan_results.size > 0)
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/test_invoker.rb b/test/vendor/ceedling/lib/ceedling/test_invoker.rb
deleted file mode 100644
index 652cb318b..000000000
--- a/test/vendor/ceedling/lib/ceedling/test_invoker.rb
+++ /dev/null
@@ -1,188 +0,0 @@
-require 'ceedling/constants'
-
-
-class TestInvoker
-
-  attr_reader :sources, :tests, :mocks
-
-  constructor :configurator,
-              :test_invoker_helper,
-              :plugin_manager,
-              :streaminator,
-              :preprocessinator,
-              :task_invoker,
-              :dependinator,
-              :project_config_manager,
-              :build_invoker_utils,
-              :file_path_utils,
-              :file_wrapper
-
-  def setup
-    @sources = []
-    @tests   = []
-    @mocks   = []
-  end
-
-  def get_test_definition_str(test)
-    return "-D" + File.basename(test, File.extname(test)).upcase.sub(/@.*$/, "")
-  end
-
-  def get_tools_compilers
-    tools_compilers = Hash.new
-    tools_compilers["for unit test"] = TOOLS_TEST_COMPILER if defined? TOOLS_TEST_COMPILER
-    tools_compilers["for gcov"]      = TOOLS_GCOV_COMPILER if defined? TOOLS_GCOV_COMPILER
-    return tools_compilers
-  end
-
-  def add_test_definition(test)
-    test_definition_str = get_test_definition_str(test)
-    get_tools_compilers.each do |tools_compiler_key, tools_compiler_value|
-      tools_compiler_value[:arguments].push("-D#{File.basename(test, ".*").strip.upcase.sub(/@.*$/, "")}")
-      @streaminator.stdout_puts("Add the definition value in the build option #{tools_compiler_value[:arguments][-1]} #{tools_compiler_key}", Verbosity::OBNOXIOUS)
-    end
-  end
-
-  def delete_test_definition(test)
-    test_definition_str = get_test_definition_str(test)
-    get_tools_compilers.each do |tools_compiler_key, tools_compiler_value|
-      num_options = tools_compiler_value[:arguments].size
-      @streaminator.stdout_puts("Delete the definition value in the build option #{tools_compiler_value[:arguments][-1]} #{tools_compiler_key}", Verbosity::OBNOXIOUS)
-      tools_compiler_value[:arguments].delete_if{|i| i == test_definition_str}
-      if num_options > tools_compiler_value[:arguments].size + 1
-        @streaminator.stderr_puts("WARNING: duplicated test definition.")
-      end
-    end
-  end
-
-  # Convert libraries configuration form YAML configuration
-  # into a string that can be given to the compiler.
-  def convert_libraries_to_arguments()
-    if @configurator.project_config_hash.has_key?(:libraries_test)
-      lib_args = @configurator.project_config_hash[:libraries_test]
-      lib_args.flatten!
-      lib_flag = @configurator.project_config_hash[:libraries_flag]
-      lib_args.map! {|v| lib_flag.gsub(/\$\{1\}/, v) } if (defined? lib_flag)
-      return lib_args
-    end
-  end
-
-
-  def setup_and_invoke(tests, context=TEST_SYM, options={:force_run => true, :build_only => false})
-
-    @tests = tests
-
-    @project_config_manager.process_test_config_change
-
-    @tests.each do |test|
-      # announce beginning of test run
-      header = "Test '#{File.basename(test)}'"
-      @streaminator.stdout_puts("\n\n#{header}\n#{'-' * header.length}")
-
-      begin
-        @plugin_manager.pre_test( test )
-        test_name ="#{File.basename(test)}".chomp('.c')
-        def_test_key="defines_#{test_name.downcase}"
-
-        # Re-define the project out path and pre-processor defines.
-        if @configurator.project_config_hash.has_key?(def_test_key.to_sym)
-          @project_config_manager.test_config_changed
-          defs_bkp = Array.new(COLLECTION_DEFINES_TEST_AND_VENDOR)
-          printf " ************** Specific test definitions for #{test_name} !!! \n"
-          tst_defs_cfg = @configurator.project_config_hash[def_test_key.to_sym]
-
-          orig_path = @configurator.project_test_build_output_path
-          @configurator.project_config_hash[:project_test_build_output_path] = File.join(@configurator.project_test_build_output_path, test_name)
-          @file_wrapper.mkdir(@configurator.project_test_build_output_path)
-          COLLECTION_DEFINES_TEST_AND_VENDOR.replace(tst_defs_cfg)
-          # printf " *  new defines = #{COLLECTION_DEFINES_TEST_AND_VENDOR}\n"
-        end
-
-        # collect up test fixture pieces & parts
-        runner       = @file_path_utils.form_runner_filepath_from_test( test )
-        mock_list    = @preprocessinator.preprocess_test_and_invoke_test_mocks( test )
-        sources      = @test_invoker_helper.extract_sources( test )
-        extras       = @configurator.collection_test_fixture_extra_link_objects
-        core         = [test] + mock_list + sources
-        objects      = @file_path_utils.form_test_build_objects_filelist( [runner] + core + extras )
-        results_pass = @file_path_utils.form_pass_results_filepath( test )
-        results_fail = @file_path_utils.form_fail_results_filepath( test )
-
-        @project_config_manager.process_test_defines_change(sources)
-
-        # add the definition value in the build option for the unit test
-        if @configurator.defines_use_test_definition
-          add_test_definition(test)
-        end
-
-        # clean results files so we have a missing file with which to kick off rake's dependency rules
-        @test_invoker_helper.clean_results( {:pass => results_pass, :fail => results_fail}, options )
-
-        # load up auxiliary dependencies so deep changes cause rebuilding appropriately
-        @test_invoker_helper.process_deep_dependencies( core ) do |dependencies_list|
-          @dependinator.load_test_object_deep_dependencies( dependencies_list )
-        end
-
-        # tell rake to create test runner if needed
-        @task_invoker.invoke_test_runner( runner )
-
-        # enhance object file dependencies to capture externalities influencing regeneration
-        @dependinator.enhance_test_build_object_dependencies( objects )
-
-        # associate object files with executable
-        @dependinator.setup_test_executable_dependencies( test, objects )
-
-        # build test objects
-        @task_invoker.invoke_test_objects( objects )
-
-        # if the option build_only has been specified, build only the executable
-        # but don't run the test
-        if (options[:build_only])
-          executable = @file_path_utils.form_test_executable_filepath( test )
-          @task_invoker.invoke_test_executable( executable )
-        else
-          # 3, 2, 1... launch
-          @task_invoker.invoke_test_results( results_pass )
-        end
-      rescue => e
-        @build_invoker_utils.process_exception( e, context )
-      ensure
-        # delete the definition value in the build option for the unit test
-        if @configurator.defines_use_test_definition
-          delete_test_definition(test)
-        end
-        @plugin_manager.post_test( test )
-        # restore the project test defines
-        if @configurator.project_config_hash.has_key?(def_test_key.to_sym)
-          # @configurator.project_config_hash[:defines_test] =
-          COLLECTION_DEFINES_TEST_AND_VENDOR.replace(defs_bkp)
-          # printf " ---- Restored defines at #{defs_bkp}"
-          @configurator.project_config_hash[:project_test_build_output_path] = orig_path
-          printf " ************** Restored defines and build path\n"
-        end
-      end
-
-      # store away what's been processed
-      @mocks.concat( mock_list )
-      @sources.concat( sources )
-
-      @task_invoker.first_run = false
-    end
-
-    # post-process collected mock list
-    @mocks.uniq!
-
-    # post-process collected sources list
-    @sources.uniq!
-  end
-
-
-  def refresh_deep_dependencies
-    @file_wrapper.rm_f(
-      @file_wrapper.directory_listing(
-        File.join( @configurator.project_test_dependencies_path, '*' + @configurator.extension_dependencies ) ) )
-
-    @test_invoker_helper.process_deep_dependencies(
-      @configurator.collection_all_tests + @configurator.collection_all_source )
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb b/test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb
deleted file mode 100644
index b0a223f56..000000000
--- a/test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb
+++ /dev/null
@@ -1,32 +0,0 @@
-
-class TestInvokerHelper
-
-  constructor :configurator, :task_invoker, :test_includes_extractor, :file_finder, :file_path_utils, :file_wrapper
-
-  def clean_results(results, options)
-    @file_wrapper.rm_f( results[:fail] )
-    @file_wrapper.rm_f( results[:pass] ) if (options[:force_run])
-  end
-
-  def process_deep_dependencies(files)
-    return if (not @configurator.project_use_deep_dependencies)
-
-    dependencies_list = @file_path_utils.form_test_dependencies_filelist( files )
-
-    if @configurator.project_generate_deep_dependencies
-      @task_invoker.invoke_test_dependencies_files( dependencies_list )
-    end
-
-    yield( dependencies_list ) if block_given?
-  end
-  
-  def extract_sources(test)
-    sources  = []
-    includes = @test_includes_extractor.lookup_includes_list(test)
-    
-    includes.each { |include| sources << @file_finder.find_compilation_input_file(include, :ignore) }
-    
-    return sources.compact
-  end
-  
-end
diff --git a/test/vendor/ceedling/lib/ceedling/tool_executor.rb b/test/vendor/ceedling/lib/ceedling/tool_executor.rb
deleted file mode 100644
index 0ab5ddcac..000000000
--- a/test/vendor/ceedling/lib/ceedling/tool_executor.rb
+++ /dev/null
@@ -1,229 +0,0 @@
-require 'ceedling/constants'
-require 'benchmark'
-
-class ShellExecutionException < RuntimeError
-  attr_reader :shell_result
-  def initialize(shell_result)
-    @shell_result = shell_result
-  end
-end
-
-class ToolExecutor
-
-  constructor :configurator, :tool_executor_helper, :streaminator, :system_wrapper
-
-  def setup
-    @tool_name  = ''
-    @executable = ''
-  end
-
-  # build up a command line from yaml provided config
-
-  # @param extra_params is an array of parameters to append to executable
-  def build_command_line(tool_config, extra_params, *args)
-    @tool_name  = tool_config[:name]
-    @executable = tool_config[:executable]
-
-    command = {}
-
-    # basic premise is to iterate top to bottom through arguments using '$' as
-    #  a string replacement indicator to expand globals or inline yaml arrays
-    #  into command line arguments via substitution strings
-    # executable must be quoted if it includes spaces (common on windows)
-    executable = @tool_executor_helper.osify_path_separators( expandify_element(@executable, *args) )
-    executable = "\"#{executable}\"" if executable.include?(' ')
-    command[:line] = [
-      executable,
-      extra_params.join(' ').strip,
-      build_arguments(tool_config[:arguments], *args),
-      ].reject{|s| s.nil? || s.empty?}.join(' ').strip
-
-    command[:options] = {
-      :stderr_redirect => @tool_executor_helper.stderr_redirection(tool_config, @configurator.project_logging),
-      :background_exec => tool_config[:background_exec]
-      }
-
-    return command
-  end
-
-
-  # shell out, execute command, and return response
-  def exec(command, options={}, args=[])
-    options[:boom] = true if (options[:boom].nil?)
-    options[:stderr_redirect] = StdErrRedirect::NONE if (options[:stderr_redirect].nil?)
-    options[:background_exec] = BackgroundExec::NONE if (options[:background_exec].nil?)
-    # build command line
-    command_line = [
-      @tool_executor_helper.background_exec_cmdline_prepend( options ),
-      command.strip,
-      args,
-      @tool_executor_helper.stderr_redirect_cmdline_append( options ),
-      @tool_executor_helper.background_exec_cmdline_append( options ),
-      ].flatten.compact.join(' ')
-
-    @streaminator.stderr_puts("Verbose: #{__method__.to_s}(): #{command_line}", Verbosity::DEBUG)
-
-    shell_result = {}
-
-    # depending on background exec option, we shell out differently
-    time = Benchmark.realtime do
-      if (options[:background_exec] != BackgroundExec::NONE)
-        shell_result = @system_wrapper.shell_system( command_line, options[:boom] )
-      else
-        shell_result = @system_wrapper.shell_backticks( command_line, options[:boom] )
-      end
-    end
-    shell_result[:time] = time
-
-    #scrub the string for illegal output
-    unless shell_result[:output].nil?
-      shell_result[:output] = shell_result[:output].scrub if "".respond_to?(:scrub)
-      shell_result[:output].gsub!(/\033\[\d\dm/,'')
-    end
-
-    @tool_executor_helper.print_happy_results( command_line, shell_result, options[:boom] )
-    @tool_executor_helper.print_error_results( command_line, shell_result, options[:boom] )
-
-    # go boom if exit code isn't 0 (but in some cases we don't want a non-0 exit code to raise)
-    raise ShellExecutionException.new(shell_result) if ((shell_result[:exit_code] != 0) and options[:boom])
-
-    return shell_result
-  end
-
-
-  private #############################
-
-
-  def build_arguments(config, *args)
-    build_string = ''
-
-    return nil if (config.nil?)
-
-    # iterate through each argument
-
-    # the yaml blob array needs to be flattened so that yaml substitution
-    # is handled correctly, since it creates a nested array when an anchor is
-    # dereferenced
-    config.flatten.each do |element|
-      argument = ''
-
-      case(element)
-        # if we find a simple string then look for string replacement operators
-        #  and expand with the parameters in this method's argument list
-        when String then argument = expandify_element(element, *args)
-        # if we find a hash, then we grab the key as a substitution string and expand the
-        #  hash's value(s) within that substitution string
-        when Hash   then argument = dehashify_argument_elements(element)
-      end
-
-      build_string.concat("#{argument} ") if (argument.length > 0)
-    end
-
-    build_string.strip!
-    return build_string if (build_string.length > 0)
-    return nil
-  end
-
-
-  # handle simple text string argument & argument array string replacement operators
-  def expandify_element(element, *args)
-    match = //
-    to_process = nil
-    args_index = 0
-
-    # handle ${#} input replacement
-    if (element =~ TOOL_EXECUTOR_ARGUMENT_REPLACEMENT_PATTERN)
-      args_index = ($2.to_i - 1)
-
-      if (args.nil? or args[args_index].nil?)
-        @streaminator.stderr_puts("ERROR: Tool '#{@tool_name}' expected valid argument data to accompany replacement operator #{$1}.", Verbosity::ERRORS)
-        raise
-      end
-
-      match = /#{Regexp.escape($1)}/
-      to_process = args[args_index]
-    end
-
-    # simple string argument: replace escaped '\$' and strip
-    element.sub!(/\\\$/, '$')
-    element.strip!
-
-    # handle inline ruby execution
-    if (element =~ RUBY_EVAL_REPLACEMENT_PATTERN)
-      element.replace(eval($1))
-    end
-
-    build_string = ''
-
-    # handle array or anything else passed into method to be expanded in place of replacement operators
-    case (to_process)
-      when Array then to_process.each {|value| build_string.concat( "#{element.sub(match, value.to_s)} " ) } if (to_process.size > 0)
-      else build_string.concat( element.sub(match, to_process.to_s) )
-    end
-
-    # handle inline ruby string substitution
-    if (build_string =~ RUBY_STRING_REPLACEMENT_PATTERN)
-      build_string.replace(@system_wrapper.module_eval(build_string))
-    end
-
-    return build_string.strip
-  end
-
-
-  # handle argument hash: keys are substitution strings, values are data to be expanded within substitution strings
-  def dehashify_argument_elements(hash)
-    build_string = ''
-    elements = []
-
-    # grab the substitution string (hash key)
-    substitution = hash.keys[0].to_s
-    # grab the string(s) to squirt into the substitution string (hash value)
-    expand = hash[hash.keys[0]]
-
-    if (expand.nil?)
-      @streaminator.stderr_puts("ERROR: Tool '#{@tool_name}' could not expand nil elements for substitution string '#{substitution}'.", Verbosity::ERRORS)
-      raise
-    end
-
-    # array-ify expansion input if only a single string
-    expansion = ((expand.class == String) ? [expand] : expand)
-
-    expansion.each do |item|
-      # code eval substitution
-      if (item =~ RUBY_EVAL_REPLACEMENT_PATTERN)
-        elements << eval($1)
-      # string eval substitution
-      elsif (item =~ RUBY_STRING_REPLACEMENT_PATTERN)
-        elements << @system_wrapper.module_eval(item)
-      # global constants
-      elsif (@system_wrapper.constants_include?(item))
-        const = Object.const_get(item)
-        if (const.nil?)
-          @streaminator.stderr_puts("ERROR: Tool '#{@tool_name}' found constant '#{item}' to be nil.", Verbosity::ERRORS)
-          raise
-        else
-          elements << const
-        end
-      elsif (item.class == Array)
-        elements << item
-      elsif (item.class == String)
-        @streaminator.stderr_puts("ERROR: Tool '#{@tool_name}' cannot expand nonexistent value '#{item}' for substitution string '#{substitution}'.", Verbosity::ERRORS)
-        raise
-      else
-        @streaminator.stderr_puts("ERROR: Tool '#{@tool_name}' cannot expand value having type '#{item.class}' for substitution string '#{substitution}'.", Verbosity::ERRORS)
-        raise
-      end
-    end
-
-    # expand elements (whether string or array) into substitution string & replace escaped '\$'
-    elements.flatten!
-    elements.each do |element|
-      build_string.concat( substitution.sub(/([^\\]*)\$/, "\\1#{element}") ) # don't replace escaped '\$' but allow us to replace just a lonesome '$'
-      build_string.gsub!(/\\\$/, '$')
-      build_string.concat(' ')
-    end
-
-    return build_string.strip
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/tool_executor_helper.rb b/test/vendor/ceedling/lib/ceedling/tool_executor_helper.rb
deleted file mode 100644
index de4cafe46..000000000
--- a/test/vendor/ceedling/lib/ceedling/tool_executor_helper.rb
+++ /dev/null
@@ -1,164 +0,0 @@
-require 'ceedling/constants' # for Verbosity enumeration & $stderr redirect enumeration
-
-##
-# Helper functions for the tool executor
-class ToolExecutorHelper
-
-  constructor :streaminator, :system_utils, :system_wrapper
-
-  ##
-  # Returns the stderr redirection based on the config and logging.
-  # ==== Attributes
-  #
-  # * _tool_config_:  A hash containing config information.
-  # * _logging_:  A boolean representing if logging is enabled or not.
-  #
-  def stderr_redirection(tool_config, logging)
-    # if there's no logging enabled, return :stderr_redirect unmodified
-    return tool_config[:stderr_redirect] if (not logging)
-
-    # if there is logging enabled but the redirect is a custom value (not enum), return the custom string
-    return tool_config[:stderr_redirect] if (tool_config[:stderr_redirect].class == String)
-
-    # if logging is enabled but there's no custom string, return the AUTO enumeration so $stderr goes into the log
-    return StdErrRedirect::AUTO
-  end
-
-
-  ##
-  # Returns the background execution prepend based on the config.
-  # ==== Attributes
-  #
-  # * _tool_config_:  A hash containing config information.
-  #
-  def background_exec_cmdline_prepend(tool_config)
-    return nil if (tool_config.nil? || tool_config[:background_exec].nil?)
-
-    config_exec = tool_config[:background_exec]
-
-    if ((config_exec == BackgroundExec::AUTO) and (@system_wrapper.windows?))
-      return 'start'
-    end
-
-    if (config_exec == BackgroundExec::WIN)
-      return 'start'
-    end
-
-    return nil
-  end
-
-
-  ##
-  # Modifies an executables path based on platform.
-  # ==== Attributes
-  #
-  # * _executable_:  The executable's path.
-  #
-  def osify_path_separators(executable)
-    return executable.gsub(/\//, '\\') if (@system_wrapper.windows?)
-    return executable
-  end
-
-  ##
-  # Returns the stderr redirect append based on the config.
-  # ==== Attributes
-  #
-  # * _tool_config_:  A hash containing config information.
-  #
-  def stderr_redirect_cmdline_append(tool_config)
-    return nil if (tool_config.nil? || tool_config[:stderr_redirect].nil?)
-
-    config_redirect = tool_config[:stderr_redirect]
-    redirect        = StdErrRedirect::NONE
-
-    if (config_redirect == StdErrRedirect::AUTO)
-       if (@system_wrapper.windows?)
-         redirect = StdErrRedirect::WIN
-       elsif (@system_utils.tcsh_shell?)
-         redirect = StdErrRedirect::TCSH
-       else
-         redirect = StdErrRedirect::UNIX
-       end
-    end
-
-    case redirect
-      # we may need more complicated processing after some learning with various environments
-      when StdErrRedirect::NONE then nil
-      when StdErrRedirect::WIN  then '2>&1'
-      when StdErrRedirect::UNIX then '2>&1'
-      when StdErrRedirect::TCSH then '|&'
-      else redirect.to_s
-    end
-  end
-
-  ##
-  # Returns the background execution append based on the config.
-  # ==== Attributes
-  #
-  # * _tool_config_:  A hash containing config information.
-  #
-  def background_exec_cmdline_append(tool_config)
-    return nil if (tool_config.nil? || tool_config[:background_exec].nil?)
-
-    config_exec = tool_config[:background_exec]
-
-    # if :auto & windows, then we already prepended 'start' and should append nothing
-    return nil if ((config_exec == BackgroundExec::AUTO) and (@system_wrapper.windows?))
-
-    # if :auto & not windows, then we append standard '&'
-    return '&' if ((config_exec == BackgroundExec::AUTO) and (not @system_wrapper.windows?))
-
-    # if explicitly Unix, then append '&'
-    return '&' if (config_exec == BackgroundExec::UNIX)
-
-  # * _command_str_:  A hash containing config information.
-    # all other cases, including :none, :win, & anything unrecognized, append nothing
-    return nil
-  end
-
-  ##
-  # Outputs success results if command succeeded and we have verbosity cranked up.
-  # ==== Attributes
-  #
-  # * _command_str_:  The command ran.
-  # * _shell_results_:  The outputs of the command including exit code and
-  # output.
-  # * _boom_:  A boolean representing if a non zero result is erroneous.
-  #
-  def print_happy_results(command_str, shell_result, boom=true)
-    if ((shell_result[:exit_code] == 0) or ((shell_result[:exit_code] != 0) and not boom))
-      output  = "> Shell executed command:\n"
-      output += "'#{command_str}'\n"
-      output += "> Produced output:\n"             if (not shell_result[:output].empty?)
-      output += "#{shell_result[:output].strip}\n" if (not shell_result[:output].empty?)
-      output += "> And exited with status: [#{shell_result[:exit_code]}].\n" if (shell_result[:exit_code] != 0)
-      output += "\n"
-
-      @streaminator.stdout_puts(output, Verbosity::OBNOXIOUS)
-    end
-  end
-
-  ##
-  # Outputs failures results if command failed and we have verbosity set to minimum error level.
-  # ==== Attributes
-  #
-  # * _command_str_:  The command ran.
-  # * _shell_results_:  The outputs of the command including exit code and
-  # output.
-  # * _boom_:  A boolean representing if a non zero result is erroneous.
-  #
-  def print_error_results(command_str, shell_result, boom=true)
-    if ((shell_result[:exit_code] != 0) and boom)
-      output  = "ERROR: Shell command failed.\n"
-      output += "> Shell executed command:\n"
-      output += "'#{command_str}'\n"
-      output += "> Produced output:\n"             if (not shell_result[:output].empty?)
-      output += "#{shell_result[:output].strip}\n" if (not shell_result[:output].empty?)
-      output += "> And exited with status: [#{shell_result[:exit_code]}].\n" if (shell_result[:exit_code] != nil)
-      output += "> And then likely crashed.\n"                               if (shell_result[:exit_code] == nil)
-      output += "\n"
-
-      @streaminator.stderr_puts(output, Verbosity::ERRORS)
-    end
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/verbosinator.rb b/test/vendor/ceedling/lib/ceedling/verbosinator.rb
deleted file mode 100644
index e8ed38d78..000000000
--- a/test/vendor/ceedling/lib/ceedling/verbosinator.rb
+++ /dev/null
@@ -1,10 +0,0 @@
-
-class Verbosinator
-
-  constructor :configurator
-
-  def should_output?(level)
-    return (level <= @configurator.project_verbosity)
-  end
-
-end
diff --git a/test/vendor/ceedling/lib/ceedling/version.rb b/test/vendor/ceedling/lib/ceedling/version.rb
deleted file mode 100644
index ba917df5a..000000000
--- a/test/vendor/ceedling/lib/ceedling/version.rb
+++ /dev/null
@@ -1,36 +0,0 @@
-
-# @private
-module Ceedling
-  module Version
-    # Check for local or global version of vendor directory in order to look up versions
-    { 
-      "CEXCEPTION" => File.join("vendor","c_exception","lib","CException.h"),
-      "CMOCK"      => File.join("vendor","cmock","src","cmock.h"),
-      "UNITY"      => File.join("vendor","unity","src","unity.h"),
-    }.each_pair do |name, path|
-      filename = if (File.exist?(File.join("..","..",path)))
-        File.join("..","..",path)
-      elsif (File.exist?(File.join(File.dirname(__FILE__),"..","..",path)))
-        File.join(File.dirname(__FILE__),"..","..",path)
-      else
-        eval "#{name} = 'unknown'"
-        continue
-      end
-
-      # Actually look up the versions
-      a = [0,0,0]
-      File.readlines(filename) do |line|
-        ["VERSION_MAJOR", "VERSION_MINOR", "VERSION_BUILD"].each_with_index do |field, i|
-          m = line.match(/#{name}_#{field}\s+(\d+)/)
-          a[i] = m[1] unless (m.nil?)
-        end
-      end
-
-      # Make a constant from each, so that we can use it elsewhere
-      eval "#{name} = '#{a.join(".")}'"
-    end
-
-    GEM = "0.29.0"
-    CEEDLING = GEM
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/version.rb.erb b/test/vendor/ceedling/lib/ceedling/version.rb.erb
deleted file mode 100644
index a31e3abb3..000000000
--- a/test/vendor/ceedling/lib/ceedling/version.rb.erb
+++ /dev/null
@@ -1,15 +0,0 @@
-# @private
-module Ceedling
-  module Version
-    # @private
-    GEM = "0.27.0"
-    # @private
-    CEEDLING = "<%= versions["CEEDLING"] %>"
-    # @private
-    CEXCEPTION = "<%= versions["CEXCEPTION"] %>"
-    # @private
-    CMOCK = "<%= versions["CMOCK"] %>"
-    # @private
-    UNITY = "<%= versions["UNITY"] %>"
-  end
-end
diff --git a/test/vendor/ceedling/lib/ceedling/yaml_wrapper.rb b/test/vendor/ceedling/lib/ceedling/yaml_wrapper.rb
deleted file mode 100644
index 00ece5141..000000000
--- a/test/vendor/ceedling/lib/ceedling/yaml_wrapper.rb
+++ /dev/null
@@ -1,17 +0,0 @@
-require 'yaml'
-require 'erb'
-
-
-class YamlWrapper
-
-  def load(filepath)
-    return YAML.load(ERB.new(File.read(filepath)).result)
-  end
-
-  def dump(filepath, structure)
-    File.open(filepath, 'w') do |output|
-      YAML.dump(structure, output)
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/beep/README.md b/test/vendor/ceedling/plugins/beep/README.md
deleted file mode 100644
index e59d881b3..000000000
--- a/test/vendor/ceedling/plugins/beep/README.md
+++ /dev/null
@@ -1,22 +0,0 @@
-ceedling-beep
-=============
-
-This is a simple plugin that just beeps at the end of a build and/or test sequence. Are you getting too distracted surfing
-the internet, chatting with coworkers, or swordfighting while it's building or testing? The friendly beep will let you know
-it's time to pay attention again.
-
-This plugin has very few configuration options. At this time it can beep on completion of a task and/or on an error condition.
-For each of these, you can configure the method that it should beep.
-
-```
-:tools:
-  :beep_on_done: :bell
-  :beep_on_error: :bell
-```
-
-Each of these have the following options:
-
-  - :bell - this option uses the ASCII bell character out stdout
-  - :speaker_test - this uses the linux speaker-test command if installed
-
-Very likely, we'll be adding to this list if people find this to be useful.
diff --git a/test/vendor/ceedling/plugins/beep/lib/beep.rb b/test/vendor/ceedling/plugins/beep/lib/beep.rb
deleted file mode 100644
index 6a6d01ab2..000000000
--- a/test/vendor/ceedling/plugins/beep/lib/beep.rb
+++ /dev/null
@@ -1,40 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-
-class Beep < Plugin
-
-  attr_reader :config
-
-  def setup
-    @config = {
-      :on_done  => ((defined? TOOLS_BEEP_ON_DONE)  ? TOOLS_BEEP_ON_DONE  : :bell  ),
-      :on_error => ((defined? TOOLS_BEEP_ON_ERROR) ? TOOLS_BEEP_ON_ERROR : :bell  ),
-    }
-  end
-
-  def post_build
-    beep @config[:on_done]
-  end
-
-  def post_error
-    beep @config[:on_error]
-  end
-
-  private
-
-  def beep(method = :none)
-    case method
-    when :bell
-      if (SystemWrapper.windows?)
-        puts "echo '\007'"
-      else
-        puts "echo -ne '\007'"
-      end
-    when :speaker_test
-      `speaker-test -t sine -f 1000 -l 1`
-    else
-      #do nothing with illegal or :none
-    end
-  end
-end
-
diff --git a/test/vendor/ceedling/plugins/bullseye/assets/template.erb b/test/vendor/ceedling/plugins/bullseye/assets/template.erb
deleted file mode 100644
index 504f85583..000000000
--- a/test/vendor/ceedling/plugins/bullseye/assets/template.erb
+++ /dev/null
@@ -1,15 +0,0 @@
-% function_string = hash[:coverage][:functions].to_s
-% branch_string   = hash[:coverage][:branches].to_s
-% format_string   = "%#{[function_string.length, branch_string.length].max}i"
-<%=@ceedling[:plugin_reportinator].generate_banner("#{hash[:header]}: CODE COVERAGE SUMMARY")%>
-% if (!hash[:coverage][:functions].nil?)
-FUNCTIONS: <%=sprintf(format_string, hash[:coverage][:functions])%>%
-% else
-FUNCTIONS: none
-% end
-% if (!hash[:coverage][:branches].nil?)
-BRANCHES:  <%=sprintf(format_string, hash[:coverage][:branches])%>%
-% else
-BRANCHES:  none
-% end
-
diff --git a/test/vendor/ceedling/plugins/bullseye/bullseye.rake b/test/vendor/ceedling/plugins/bullseye/bullseye.rake
deleted file mode 100644
index a7bbebe3a..000000000
--- a/test/vendor/ceedling/plugins/bullseye/bullseye.rake
+++ /dev/null
@@ -1,169 +0,0 @@
-directory(BULLSEYE_BUILD_OUTPUT_PATH)
-directory(BULLSEYE_RESULTS_PATH)
-directory(BULLSEYE_ARTIFACTS_PATH)
-directory(BULLSEYE_DEPENDENCIES_PATH)
-
-CLEAN.include(File.join(BULLSEYE_BUILD_OUTPUT_PATH, '*'))
-CLEAN.include(File.join(BULLSEYE_RESULTS_PATH, '*'))
-CLEAN.include(File.join(BULLSEYE_DEPENDENCIES_PATH, '*'))
-
-CLOBBER.include(File.join(BULLSEYE_BUILD_PATH, '**/*'))
-PLUGINS_BULLSEYE_LIB_PATH = 'C:\\tools\\BullseyeCoverage\\lib' if not defined?(PLUGINS_BULLSEYE_LIB_PATH)
-
-rule(/#{BULLSEYE_BUILD_OUTPUT_PATH}\/#{'.+\\'+EXTENSION_OBJECT}$/ => [
-       proc do |task_name|
-         @ceedling[:file_finder].find_compilation_input_file(task_name)
-       end
-     ]) do |object|
-
-  if File.basename(object.source) =~ /^(#{PROJECT_TEST_FILE_PREFIX}|#{CMOCK_MOCK_PREFIX}|#{BULLSEYE_IGNORE_SOURCES.join('|')})/i
-    @ceedling[:generator].generate_object_file(
-      TOOLS_BULLSEYE_COMPILER,
-      OPERATION_COMPILE_SYM,
-      BULLSEYE_SYM,
-      object.source,
-      object.name,
-      @ceedling[:file_path_utils].form_test_build_list_filepath(object.name)
-    )
-  else
-    @ceedling[BULLSEYE_SYM].generate_coverage_object_file(object.source, object.name)
-  end
-
-end
-
-rule(/#{BULLSEYE_BUILD_OUTPUT_PATH}\/#{'.+\\'+EXTENSION_EXECUTABLE}$/) do |bin_file|
-  @ceedling[:generator].generate_executable_file(
-    TOOLS_BULLSEYE_LINKER,
-    BULLSEYE_SYM,
-    bin_file.prerequisites,
-    bin_file.name,
-    @ceedling[:file_path_utils].form_test_build_map_filepath(bin_file.name)
-  )
-end
-
-rule(/#{BULLSEYE_RESULTS_PATH}\/#{'.+\\'+EXTENSION_TESTPASS}$/ => [
-       proc do |task_name|
-         @ceedling[:file_path_utils].form_test_executable_filepath(task_name)
-       end
-     ]) do |test_result|
-  @ceedling[:generator].generate_test_results(TOOLS_BULLSEYE_FIXTURE, BULLSEYE_SYM, test_result.source, test_result.name)
-end
-
-rule(/#{BULLSEYE_DEPENDENCIES_PATH}\/#{'.+\\'+EXTENSION_DEPENDENCIES}$/ => [
-       proc do |task_name|
-         @ceedling[:file_finder].find_compilation_input_file(task_name)
-       end
-     ]) do |dep|
-  @ceedling[:generator].generate_dependencies_file(
-    TOOLS_TEST_DEPENDENCIES_GENERATOR,
-    BULLSEYE_SYM,
-    dep.source,
-    File.join(BULLSEYE_BUILD_OUTPUT_PATH, File.basename(dep.source).ext(EXTENSION_OBJECT) ),
-    dep.name
-  )
-end
-
-task :directories => [BULLSEYE_BUILD_OUTPUT_PATH, BULLSEYE_RESULTS_PATH, BULLSEYE_DEPENDENCIES_PATH, BULLSEYE_ARTIFACTS_PATH]
-
-namespace BULLSEYE_SYM do
-  task source_coverage: COLLECTION_ALL_SOURCE.pathmap("#{BULLSEYE_BUILD_OUTPUT_PATH}/%n#{@ceedling[:configurator].extension_object}")
-
-  desc 'Run code coverage for all tests'
-  task all: [:directories] do
-    @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
-    @ceedling[BULLSEYE_SYM].enableBullseye(true)
-    @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, BULLSEYE_SYM)
-    @ceedling[:configurator].restore_config
-  end
-
-  desc "Run single test w/ coverage ([*] real test or source file name, no path)."
-  task :* do
-    message = "\nOops! '#{BULLSEYE_ROOT_NAME}:*' isn't a real task. " +
-              "Use a real test or source file name (no path) in place of the wildcard.\n" +
-              "Example: rake #{BULLSEYE_ROOT_NAME}:foo.c\n\n"
-  
-    @ceedling[:streaminator].stdout_puts( message )
-  end
-  
-  desc 'Run tests by matching regular expression pattern.'
-  task :pattern, [:regex] => [:directories] do |_t, args|
-    matches = []
-    
-    COLLECTION_ALL_TESTS.each do |test|
-      matches << test if test =~ /#{args.regex}/
-    end
-  
-    if !matches.empty?
-      @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
-      @ceedling[BULLSEYE_SYM].enableBullseye(true)
-      @ceedling[:test_invoker].setup_and_invoke(matches, BULLSEYE_SYM, force_run: false)
-      @ceedling[:configurator].restore_config
-    else
-      @ceedling[:streaminator].stdout_puts("\nFound no tests matching pattern /#{args.regex}/.")
-    end
-  end
-
-  desc 'Run tests whose test path contains [dir] or [dir] substring.'
-  task :path, [:dir] => [:directories] do |_t, args|
-    matches = []
-    
-    COLLECTION_ALL_TESTS.each do |test|
-      matches << test if File.dirname(test).include?(args.dir.tr('\\', '/'))
-    end
-  
-    if !matches.empty?
-      @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
-      @ceedling[BULLSEYE_SYM].enableBullseye(true)
-      @ceedling[:test_invoker].setup_and_invoke(matches, BULLSEYE_SYM, force_run: false)
-      @ceedling[:configurator].restore_config
-    else
-      @ceedling[:streaminator].stdout_puts("\nFound no tests including the given path or path component.")
-    end
-  end
-
-  desc 'Run code coverage for changed files'
-  task delta: [:directories] do
-    @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
-    @ceedling[BULLSEYE_SYM].enableBullseye(true)
-    @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, BULLSEYE_SYM, {:force_run => false})
-    @ceedling[:configurator].restore_config
-  end
-  
-  # use a rule to increase efficiency for large projects
-  # bullseye test tasks by regex
-  rule(/^#{BULLSEYE_TASK_ROOT}\S+$/ => [
-      proc do |task_name|
-        test = task_name.sub(/#{BULLSEYE_TASK_ROOT}/, '')
-        test = "#{PROJECT_TEST_FILE_PREFIX}#{test}" unless test.start_with?(PROJECT_TEST_FILE_PREFIX)
-        @ceedling[:file_finder].find_test_from_file_path(test)
-      end
-  ]) do |test|
-    @ceedling[:rake_wrapper][:directories].invoke
-    @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
-    @ceedling[BULLSEYE_SYM].enableBullseye(true)
-    @ceedling[:test_invoker].setup_and_invoke([test.source], BULLSEYE_SYM)
-    @ceedling[:configurator].restore_config
-  end
-
-end
-
-if PROJECT_USE_DEEP_DEPENDENCIES
-namespace REFRESH_SYM do
-  task BULLSEYE_SYM do
-    @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
-    @ceedling[BULLSEYE_SYM].enableBullseye(true)
-    @ceedling[:test_invoker].refresh_deep_dependencies
-    @ceedling[:configurator].restore_config
-  end
-end
-end
-
-namespace UTILS_SYM do
-  
-  desc "Open Bullseye code coverage browser"
-  task BULLSEYE_SYM do
-    command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_BROWSER, [])
-    @ceedling[:tool_executor].exec(command[:line], command[:options])
-  end
-  
-end
diff --git a/test/vendor/ceedling/plugins/bullseye/config/defaults.yml b/test/vendor/ceedling/plugins/bullseye/config/defaults.yml
deleted file mode 100644
index ed261d8e5..000000000
--- a/test/vendor/ceedling/plugins/bullseye/config/defaults.yml
+++ /dev/null
@@ -1,57 +0,0 @@
----
-
-:bullseye:
-  :auto_license: TRUE
-:plugins:
-  :bullseye_lib_path: []
-:paths:
-  :bullseye_toolchain_include: []
-
-:tools:
-  :bullseye_instrumentation:
-    :executable: covc
-    :arguments:
-      - '--file $': ENVIRONMENT_COVFILE
-      - -q
-      - ${1}
-  :bullseye_compiler:
-    :executable: gcc
-    :arguments:
-      - -g
-      - -I"$": COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR
-      - -I"$": COLLECTION_PATHS_BULLSEYE_TOOLCHAIN_INCLUDE
-      - -D$: COLLECTION_DEFINES_TEST_AND_VENDOR
-      - -DBULLSEYE_COMPILER
-      - -c "${1}"
-      - -o "${2}"
-  :bullseye_linker:
-    :executable: gcc
-    :arguments:
-      - ${1}
-      - -o ${2}
-      - -L$: PLUGINS_BULLSEYE_LIB_PATH
-      - -lcov
-  :bullseye_fixture:
-    :executable: ${1}
-  :bullseye_report_covsrc:
-    :executable: covsrc
-    :arguments:
-      - '--file $': ENVIRONMENT_COVFILE
-      - -q
-      - -w140
-  :bullseye_report_covfn:
-    :executable: covfn
-    :stderr_redirect: :auto
-    :arguments:
-      - '--file $': ENVIRONMENT_COVFILE
-      - --width 120
-      - --no-source
-      - '"${1}"'
-  :bullseye_browser:
-    :executable: CoverageBrowser
-    :background_exec: :auto
-    :optional: TRUE
-    :arguments:
-      - '"$"': ENVIRONMENT_COVFILE
-
-...
diff --git a/test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb b/test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb
deleted file mode 100644
index ffa444ac7..000000000
--- a/test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb
+++ /dev/null
@@ -1,194 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-
-BULLSEYE_ROOT_NAME         = 'bullseye'
-BULLSEYE_TASK_ROOT         = BULLSEYE_ROOT_NAME + ':'
-BULLSEYE_SYM               = BULLSEYE_ROOT_NAME.to_sym
-
-BULLSEYE_BUILD_PATH        = "#{PROJECT_BUILD_ROOT}/#{BULLSEYE_ROOT_NAME}"
-BULLSEYE_BUILD_OUTPUT_PATH = "#{BULLSEYE_BUILD_PATH}/out"
-BULLSEYE_RESULTS_PATH      = "#{BULLSEYE_BUILD_PATH}/results"
-BULLSEYE_DEPENDENCIES_PATH = "#{BULLSEYE_BUILD_PATH}/dependencies"
-BULLSEYE_ARTIFACTS_PATH    = "#{PROJECT_BUILD_ARTIFACTS_ROOT}/#{BULLSEYE_ROOT_NAME}"
-
-BULLSEYE_IGNORE_SOURCES    = ['unity', 'cmock', 'cexception']
-
-
-class Bullseye < Plugin
-
-  def setup
-    @result_list = []
-    @environment = [ {:covfile => File.join( BULLSEYE_ARTIFACTS_PATH, 'test.cov' )} ]
-    @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..'))
-    @coverage_template_all = @ceedling[:file_wrapper].read(File.join(@plugin_root, 'assets/template.erb'))
-  end
-
-  def config
-    {
-      :project_test_build_output_path     => BULLSEYE_BUILD_OUTPUT_PATH,
-      :project_test_results_path          => BULLSEYE_RESULTS_PATH,
-      :project_test_dependencies_path     => BULLSEYE_DEPENDENCIES_PATH,
-      :defines_test                       => DEFINES_TEST + ['CODE_COVERAGE'],
-      :collection_defines_test_and_vendor => COLLECTION_DEFINES_TEST_AND_VENDOR + ['CODE_COVERAGE']
-    }
-  end
-
-  def generate_coverage_object_file(source, object)
-    arg_hash = {:tool => TOOLS_BULLSEYE_INSTRUMENTATION, :context => BULLSEYE_SYM, :source => source, :object => object}
-    @ceedling[:plugin_manager].pre_compile_execute(arg_hash)
-
-    @ceedling[:streaminator].stdout_puts("Compiling #{File.basename(source)} with coverage...")
-    compile_command  = 
-      @ceedling[:tool_executor].build_command_line(
-        TOOLS_BULLSEYE_COMPILER,
-        @ceedling[:flaginator].flag_down( OPERATION_COMPILE_SYM, BULLSEYE_SYM, source ),
-        source,
-        object,
-        @ceedling[:file_path_utils].form_test_build_list_filepath( object ) )
-    coverage_command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_INSTRUMENTATION, [], compile_command[:line] )
-
-    shell_result     = @ceedling[:tool_executor].exec( coverage_command[:line], coverage_command[:options] )
-    
-    arg_hash[:shell_result] = shell_result
-    @ceedling[:plugin_manager].post_compile_execute(arg_hash)
-  end
-
-  def post_test_fixture_execute(arg_hash)
-    result_file = arg_hash[:result_file]
-  
-    if ((result_file =~ /#{BULLSEYE_RESULTS_PATH}/) and (not @result_list.include?(result_file)))
-      @result_list << arg_hash[:result_file]
-    end
-  end
-
-  def post_build
-    return if (not @ceedling[:task_invoker].invoked?(/^#{BULLSEYE_TASK_ROOT}/))
-
-    # test results
-    results = @ceedling[:plugin_reportinator].assemble_test_results(@result_list)
-    hash = {
-      :header => BULLSEYE_ROOT_NAME.upcase,
-      :results => results
-    }
-    
-    @ceedling[:plugin_reportinator].run_test_results_report(hash) do
-      message = ''
-      message = 'Unit test failures.' if (results[:counts][:failed] > 0)
-      message
-    end
-    
-    # coverage results
-    return if (verify_coverage_file() == false)
-    if (@ceedling[:task_invoker].invoked?(/^#{BULLSEYE_TASK_ROOT}(all|delta)/))
-      command      = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_REPORT_COVSRC, [])
-      shell_result = @ceedling[:tool_executor].exec(command[:line], command[:options])
-      report_coverage_results_all(shell_result[:output])
-    else
-      report_per_function_coverage_results(@ceedling[:test_invoker].sources)
-    end
-  end
-
-  def summary
-    return if (verify_coverage_file() == false)
-    result_list = @ceedling[:file_path_utils].form_pass_results_filelist( BULLSEYE_RESULTS_PATH, COLLECTION_ALL_TESTS )
-
-    # test results
-    # get test results for only those tests in our configuration and of those only tests with results on disk
-    hash = {
-      :header => BULLSEYE_ROOT_NAME.upcase,
-      :results => @ceedling[:plugin_reportinator].assemble_test_results(result_list, {:boom => false})
-    }
-
-    @ceedling[:plugin_reportinator].run_test_results_report(hash)
-    
-    # coverage results
-    command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_REPORT_COVSRC)
-    shell_result = @ceedling[:tool_executor].exec(command[:line], command[:options])
-    report_coverage_results_all(shell_result[:output])
-  end
-  
-  def enableBullseye(enable)
-    if BULLSEYE_AUTO_LICENSE
-      if (enable)
-        args = ['push', 'on']
-        @ceedling[:streaminator].stdout_puts("Enabling Bullseye")
-      else
-        args = ['pop']
-        @ceedling[:streaminator].stdout_puts("Reverting Bullseye to previous state")
-      end
-
-      args.each do |arg| 
-        command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_BUILD_ENABLE_DISABLE, [], arg)
-        shell_result = @ceedling[:tool_executor].exec(command[:line], command[:options])
-      end
-
-    end
-  end
-  
-  private ###################################
-
-  def report_coverage_results_all(coverage)
-    results = {
-      :header => BULLSEYE_ROOT_NAME.upcase,
-      :coverage => {
-        :functions => nil,
-        :branches  => nil
-      }
-    }
-
-    if (coverage =~ /^Total.*?=\s+([0-9]+)\%/)
-      results[:coverage][:functions] = $1.to_i
-    end
-    
-    if (coverage =~ /^Total.*=\s+([0-9]+)\%\s*$/)
-      results[:coverage][:branches] = $1.to_i
-    end
-
-    @ceedling[:plugin_reportinator].run_report($stdout, @coverage_template_all, results)
-  end
-
-  def report_per_function_coverage_results(sources)
-    banner = @ceedling[:plugin_reportinator].generate_banner( "#{BULLSEYE_ROOT_NAME.upcase}: CODE COVERAGE SUMMARY" )
-    @ceedling[:streaminator].stdout_puts "\n" + banner
-
-    coverage_sources = sources.clone
-    coverage_sources.delete_if {|item| item =~ /#{CMOCK_MOCK_PREFIX}.+#{EXTENSION_SOURCE}$/}
-    coverage_sources.delete_if {|item| item =~ /#{BULLSEYE_IGNORE_SOURCES.join('|')}#{EXTENSION_SOURCE}$/}
-
-    coverage_sources.each do |source|
-      command          = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_REPORT_COVFN, [], source)
-      shell_results    = @ceedling[:tool_executor].exec(command[:line], command[:options])
-      coverage_results = shell_results[:output].deep_clone
-      coverage_results.sub!(/.*\n.*\n/,'') # Remove the Bullseye tool banner
-      if (coverage_results =~ /warning cov814: report is empty/)
-        coverage_results = "WARNING: #{source} contains no coverage data!\n\n"
-        @ceedling[:streaminator].stdout_puts(coverage_results, Verbosity::COMPLAIN)
-      else
-        coverage_results += "\n"
-        @ceedling[:streaminator].stdout_puts(coverage_results)
-      end
-    end
-  end
-
-  def verify_coverage_file
-    exist = @ceedling[:file_wrapper].exist?( ENVIRONMENT_COVFILE )
-
-    if (!exist)
-      banner = @ceedling[:plugin_reportinator].generate_banner( "#{BULLSEYE_ROOT_NAME.upcase}: CODE COVERAGE SUMMARY" )
-      @ceedling[:streaminator].stdout_puts "\n" + banner + "\nNo coverage file.\n\n"
-    end
-    
-    return exist
-  end
-  
-end
-
-
-# end blocks always executed following rake run
-END {
-  # cache our input configurations to use in comparison upon next execution
-  if (@ceedling[:task_invoker].invoked?(/^#{BULLSEYE_TASK_ROOT}/))
-    @ceedling[:cacheinator].cache_test_config( @ceedling[:setupinator].config_hash ) 
-    @ceedling[BULLSEYE_SYM].enableBullseye(false)
-  end
-}
diff --git a/test/vendor/ceedling/plugins/colour_report/lib/colour_report.rb b/test/vendor/ceedling/plugins/colour_report/lib/colour_report.rb
deleted file mode 100644
index 1211eab4d..000000000
--- a/test/vendor/ceedling/plugins/colour_report/lib/colour_report.rb
+++ /dev/null
@@ -1,16 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/streaminator'
-require 'ceedling/constants'
-
-class ColourReport < Plugin
-
-  def setup
-    @ceedling[:stream_wrapper].stdout_override(&ColourReport.method(:colour_stdout))
-  end
-
-  def self.colour_stdout(string)
-    require 'colour_reporter.rb'
-    report string
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/command_hooks/README.md b/test/vendor/ceedling/plugins/command_hooks/README.md
deleted file mode 100644
index 8ac64afce..000000000
--- a/test/vendor/ceedling/plugins/command_hooks/README.md
+++ /dev/null
@@ -1,53 +0,0 @@
-ceedling-command-hooks
-======================
-
-Plugin for easily calling command line tools at various points in the build process
-
-Define any of these sections in :tools: to provide additional hooks to be called on demand:
-
-```
-    :pre_mock_generate
-    :post_mock_generate
-    :pre_runner_generate
-    :post_runner_generate
-    :pre_compile_execute
-    :post_compile_execute
-    :pre_link_execute
-    :post_link_execute
-    :pre_test_fixture_execute
-    :pre_test
-    :post_test
-    :pre_release
-    :post_release
-    :pre_build
-    :post_build
-```
-
-Each of these tools can support an :executable string and an :arguments list, like so:
-
-```
-:tools:
-  :post_link_execute:
-    :executable: objcopy.exe
-    :arguments:
-      - ${1} #This is replaced with the executable name
-      - output.srec
-      - --strip-all
-```
-
-You may also specify an array of executables to be called in a particular place, like so:
-
-```
-:tools:
-  :post_test:
-    -  :executable: echo
-       :arguments: "${1} was glorious!"
-    -  :executable: echo
-       :arguments:
-         - it kinda made me cry a little.
-         - you?
-```
-
-Please note that it varies which arguments are being parsed down to the
-hooks. For now see `command_hooks.rb` to figure out which suits you best.
-Happy Tweaking!
diff --git a/test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb b/test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb
deleted file mode 100644
index 4bf8b5312..000000000
--- a/test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb
+++ /dev/null
@@ -1,92 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-class CommandHooks < Plugin
-
-  attr_reader :config
-
-  def setup
-    @config = {
-      :pre_mock_generate         => ((defined? TOOLS_PRE_MOCK_GENERATE)         ? TOOLS_PRE_MOCK_GENERATE         : nil ),
-      :post_mock_generate        => ((defined? TOOLS_POST_MOCK_GENERATE)        ? TOOLS_POST_MOCK_GENERATE        : nil ),
-      :pre_runner_generate       => ((defined? TOOLS_PRE_RUNNER_GENERATE)       ? TOOLS_PRE_RUNNER_GENERATE       : nil ),
-      :post_runner_generate      => ((defined? TOOLS_POST_RUNNER_GENERATE)      ? TOOLS_POST_RUNNER_GENERATE      : nil ),
-      :pre_compile_execute       => ((defined? TOOLS_PRE_COMPILE_EXECUTE)       ? TOOLS_PRE_COMPILE_EXECUTE       : nil ),
-      :post_compile_execute      => ((defined? TOOLS_POST_COMPILE_EXECUTE)      ? TOOLS_POST_COMPILE_EXECUTE      : nil ),
-      :pre_link_execute          => ((defined? TOOLS_PRE_LINK_EXECUTE)          ? TOOLS_PRE_LINK_EXECUTE          : nil ),
-      :post_link_execute         => ((defined? TOOLS_POST_LINK_EXECUTE)         ? TOOLS_POST_LINK_EXECUTE         : nil ),
-      :pre_test_fixture_execute  => ((defined? TOOLS_PRE_TEST_FIXTURE_EXECUTE)  ? TOOLS_PRE_TEST_FIXTURE_EXECUTE  : nil ),
-      :post_test_fixture_execute => ((defined? TOOLS_POST_TEST_FIXTURE_EXECUTE) ? TOOLS_POST_TEST_FIXTURE_EXECUTE : nil ),
-      :pre_test                  => ((defined? TOOLS_PRE_TEST)                  ? TOOLS_PRE_TEST                  : nil ),
-      :post_test                 => ((defined? TOOLS_POST_TEST)                 ? TOOLS_POST_TEST                 : nil ),
-      :pre_release               => ((defined? TOOLS_PRE_RELEASE)               ? TOOLS_PRE_RELEASE               : nil ),
-      :post_release              => ((defined? TOOLS_POST_RELEASE)              ? TOOLS_POST_RELEASE              : nil ),
-      :pre_build                 => ((defined? TOOLS_PRE_BUILD)                 ? TOOLS_PRE_BUILD                 : nil ),
-      :post_build                => ((defined? TOOLS_POST_BUILD)                ? TOOLS_POST_BUILD                : nil ),
-      :post_error                => ((defined? TOOLS_POST_ERROR)                ? TOOLS_POST_ERROR                : nil ),
-    }
-    @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..'))
-  end
-
-  def pre_mock_generate(arg_hash);         run_hook(:pre_mock_generate,         arg_hash[:header_file] ); end
-  def post_mock_generate(arg_hash);        run_hook(:post_mock_generate,        arg_hash[:header_file] ); end
-  def pre_runner_generate(arg_hash);       run_hook(:pre_runner_generate,       arg_hash[:source     ] ); end
-  def post_runner_generate(arg_hash);      run_hook(:post_runner_generate,      arg_hash[:runner_file] ); end
-  def pre_compile_execute(arg_hash);       run_hook(:pre_compile_execute,       arg_hash[:source_file] ); end
-  def post_compile_execute(arg_hash);      run_hook(:post_compile_execute,      arg_hash[:object_file] ); end
-  def pre_link_execute(arg_hash);          run_hook(:pre_link_execute,          arg_hash[:executable]  ); end
-  def post_link_execute(arg_hash);         run_hook(:post_link_execute,         arg_hash[:executable]  ); end
-  def pre_test_fixture_execute(arg_hash);  run_hook(:pre_test_fixture_execute,  arg_hash[:executable]  ); end
-  def post_test_fixture_execute(arg_hash); run_hook(:post_test_fixture_execute, arg_hash[:executable]  ); end
-  def pre_test(test);                      run_hook(:pre_test,                  test                   ); end
-  def post_test(test);                     run_hook(:post_test,                 test                   ); end
-  def pre_release;                         run_hook(:pre_release                                       ); end
-  def post_release;                        run_hook(:post_release                                      ); end
-  def pre_build;                           run_hook(:pre_build                                         ); end
-  def post_build;                          run_hook(:post_build                                        ); end
-  def post_error;                          run_hook(:post_error                                        ); end
-
-  private
-
-  ##
-  # Run a hook if its available.
-  #
-  # :args:
-  #   - hook: Name of the hook to run
-  #   - name: Name of file (default: "")
-  #
-  # :return:
-  #    shell_result.
-  #
-  def run_hook_step(hook, name="")
-    if (hook[:executable])
-      # Handle argument replacemant ({$1}), and get commandline
-      cmd = @ceedling[:tool_executor].build_command_line( hook, [], name )
-      shell_result = @ceedling[:tool_executor].exec(cmd[:line], cmd[:options])
-    end
-  end
-
-  ##
-  # Run a hook if its available.
-  #
-  # If __which_hook__ is an array, run each of them sequentially.
-  #
-  # :args:
-  #   - which_hook: Name of the hook to run
-  #   - name: Name of file
-  #
-  def run_hook(which_hook, name="")
-    if (@config[which_hook])
-      @ceedling[:streaminator].stdout_puts("Running Hook #{which_hook}...", Verbosity::NORMAL)
-      if (@config[which_hook].is_a? Array)
-        @config[which_hook].each do |hook|
-          run_hook_step(hook, name)
-        end
-      elsif (@config[which_hook].is_a? Hash)
-        run_hook_step( @config[which_hook], name )
-      else
-        @ceedling[:streaminator].stdout_puts("Hook #{which_hook} was poorly formed", Verbosity::COMPLAINT)
-      end
-    end
-  end
-end
-
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/README.md b/test/vendor/ceedling/plugins/fake_function_framework/README.md
deleted file mode 100644
index 8042775e5..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/README.md
+++ /dev/null
@@ -1,250 +0,0 @@
-# A Fake Function Framework Plug-in for Ceedling
-
-This is a plug-in for [Ceedling](https://github.com/ThrowTheSwitch/Ceedling) to use the [Fake Function Framework](https://github.com/meekrosoft/fff) for mocking instead of CMock.
-
-Using fff provides less strict mocking than CMock, and allows for more loosely-coupled tests.
-And, when tests fail -- since you get the actual line number of the failure -- it's a lot easier to figure out what went wrong.
-
-## Installing the plug-in
-
-To use the plugin you need to 1) get the contents of this repo and 2) configure your project to use it.
-
-### Get the source
-
-The easiest way to get the source is to just clone this repo into the Ceedling plugin folder for your existing Ceedling project.
-(Don't have a Ceedling project already? [Here are instructions to create one.](http://www.electronvector.com/blog/try-embedded-test-driven-development-right-now-with-ceedling))
-From within `<your-project>/vendor/ceedling/plugins`, run:
-
-`git clone https://github.com/ElectronVector/fake_function_framework.git`
-
-This will create a new folder named `fake_function_framework` in the plugins folder.
-
-### Enable the plug-in.
-
-The plug-in is enabled from within your project.yml file.
-
-In the `:plugins` configuration, add `fake_function_framework` to the list of enabled plugins:
-
-```yaml
-:plugins:
-  :load_paths:
-    - vendor/ceedling/plugins
-  :enabled:
-    - stdout_pretty_tests_report
-    - module_generator
-    - fake_function_framework
-```
-*Note that you could put the plugin source in some other loaction.
-In that case you'd need to add a new path the `:load_paths`.*
-
-## How to use it
-
-You use fff with Ceedling the same way you used to use CMock.
-Modules can still be generated with the default module generator: `rake module:create[my_module]`.
-If you want to "mock" `some_module.h` in your tests, just `#include "mock_some_module.h"`.
-This creates a fake function for each of the functions defined in `some_module.h`.
-
-The name of each fake is the original function name with an appended `_fake`.
-For example, if we're generating fakes for a stack module with `push` and `pop` functions, we would have the fakes `push_fake` and `pop_fake`.
-These fakes are linked into our test executable so that any time our unit under test calls `push` or `pop` our fakes are called instead.
-
-Each of these fakes is actually a structure containing information about how the function was called, and what it might return.
-We can use Unity to inspect these fakes in our tests, and verify the interactions of our units.
-There is also a global structure named `fff` which we can use to check the sequence of calls.
-
-The fakes can also be configured to return particular values, so you can exercise the unit under test however you want.
-
-The examples below explain how to use fff to test a variety of module interactions.
-Each example uses fakes for a "display" module, created from a display.h file with `#include "mock_display.h"`. The `display.h` file must exist and must contain the prototypes for the functions to be faked.
-
-### Test that a function was called once
-
-```c
-void
-test_whenTheDeviceIsReset_thenTheStatusLedIsTurnedOff()
-{
-    // When
-    event_deviceReset();
-
-    // Then
-    TEST_ASSERT_EQUAL(1, display_turnOffStatusLed_fake.call_count);
-}
-```
-
-### Test that a function was NOT called
-
-```c
-void
-test_whenThePowerReadingIsLessThan5_thenTheStatusLedIsNotTurnedOn(void)
-{
-    // When
-    event_powerReadingUpdate(4);
-
-    // Then
-    TEST_ASSERT_EQUAL(0, display_turnOnStatusLed_fake.call_count);
-}
-```
-
-## Test that a single function was called with the correct argument
-
-```c
-void
-test_whenTheVolumeKnobIsMaxed_thenVolumeDisplayIsSetTo11(void)
-{
-    // When
-    event_volumeKnobMaxed();
-
-    // Then
-    TEST_ASSERT_EQUAL(1, display_setVolume_fake.call_count);
-    TEST_ASSERT_EQUAL(11, display_setVolume_fake.arg0_val);
-}
-```
-
-## Test that calls are made in a particular sequence
-
-```c
-void
-test_whenTheModeSelectButtonIsPressed_thenTheDisplayModeIsCycled(void)
-{
-    // When
-    event_modeSelectButtonPressed();
-    event_modeSelectButtonPressed();
-    event_modeSelectButtonPressed();
-
-    // Then
-    TEST_ASSERT_EQUAL_PTR((void*)display_setModeToMinimum, fff.call_history[0]);
-    TEST_ASSERT_EQUAL_PTR((void*)display_setModeToMaximum, fff.call_history[1]);
-    TEST_ASSERT_EQUAL_PTR((void*)display_setModeToAverage, fff.call_history[2]);
-}
-```
-
-## Fake a return value from a function
-
-```c
-void
-test_givenTheDisplayHasAnError_whenTheDeviceIsPoweredOn_thenTheDisplayIsPoweredDown(void)
-{
-    // Given
-    display_isError_fake.return_val = true;
-
-    // When
-    event_devicePoweredOn();
-
-    // Then
-    TEST_ASSERT_EQUAL(1, display_powerDown_fake.call_count);
-}
-```
-
-## Fake a function with a value returned by reference
-
-```c
-void
-test_givenTheUserHasTypedSleep_whenItIsTimeToCheckTheKeyboard_theDisplayIsPoweredDown(void)
-{
-    // Given
-    char mockedEntry[] = "sleep";
-    void return_mock_value(char * entry, int length)
-    {
-        if (length > strlen(mockedEntry))
-        {
-            strncpy(entry, mockedEntry, length);
-        }
-    }
-    display_getKeyboardEntry_fake.custom_fake = return_mock_value;
-
-    // When
-    event_keyboardCheckTimerExpired();
-
-    // Then
-    TEST_ASSERT_EQUAL(1, display_powerDown_fake.call_count);
-}
-```
-
-## Fake a function with a function pointer parameter
-
-```
-void
-test_givenNewDataIsAvailable_whenTheDisplayHasUpdated_thenTheEventIsComplete(void)
-{
-    // A mock function for capturing the callback handler function pointer.
-    void(*registeredCallback)(void) = 0;
-    void mock_display_updateData(int data, void(*callback)(void))
-    {
-        //Save the callback function.
-        registeredCallback = callback;
-    }
-    display_updateData_fake.custom_fake = mock_display_updateData;
-
-    // Given
-    event_newDataAvailable(10);
-
-    // When
-    if (registeredCallback != 0)
-    {
-        registeredCallback();
-    }
-
-    // Then
-    TEST_ASSERT_EQUAL(true, eventProcessor_isLastEventComplete());
-}
-```
-
-## Helper macros
-
-For convenience, there are also some helper macros that create new Unity-style asserts:
-
-- `TEST_ASSERT_CALLED(function)`: Asserts that a function was called once.
-- `TEST_ASSERT_NOT_CALLED(function)`: Asserts that a function was never called.
-- `TEST_ASSERT_CALLED_TIMES(times, function)`: Asserts that a function was called a particular number of times.
-- `TEST_ASSERT_CALLED_IN_ORDER(order, function)`: Asserts that a function was called in a particular order.
-
-Here's how you might use one of these instead of simply checking the call_count value:
-
-```c
-void
-test_whenTheDeviceIsReset_thenTheStatusLedIsTurnedOff()
-{
-    // When
-    event_deviceReset();
-
-    // Then
-    // This how to directly use fff...
-    TEST_ASSERT_EQUAL(1, display_turnOffStatusLed_fake.call_count);
-    // ...and this is how to use the helper macro.
-    TEST_ASSERT_CALLED(display_turnOffStatusLed);
-}
-```
-
-## Test setup
-
-All of the fake functions, and any fff global state are all reset automatically between each test.
-
-## CMock configuration
-
-Use still use some of the CMock configuration options for setting things like the mock prefix, and for including additional header files in the mock files.
-
-```yaml
-:cmock:
-    :mock_prefix: mock_
-        :includes:
-            -
-        :includes_h_pre_orig_header:
-            -
-        :includes_h_post_orig_header:
-            -
-        :includes_c_pre_header:
-            -
-        :includes_c_post_header:
-```
-
-## Running the tests
-
-There are unit and integration tests for the plug-in itself.
-These are run with the default `rake` task.
-The integration test runs the tests for the example project in examples/fff_example.
-For the integration tests to succeed, this repository must be placed in a Ceedling tree in the plugins folder.
-
-## More examples
-
-There is an example project in examples/fff_example.
-It shows how to use the plug-in with some full-size examples.
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/Rakefile b/test/vendor/ceedling/plugins/fake_function_framework/Rakefile
deleted file mode 100644
index bc5594110..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/Rakefile
+++ /dev/null
@@ -1,19 +0,0 @@
-require 'rake'
-require 'rspec/core/rake_task'
-
-desc "Run all rspecs"
-RSpec::Core::RakeTask.new(:spec) do |t|
-    t.pattern = Dir.glob('spec/**/*_spec.rb')
-    t.rspec_opts = '--format documentation'
-    # t.rspec_opts << ' more options'
-end
-
-desc "Run integration test on example"
-task :integration_test do
-    chdir("./examples/fff_example") do
-        sh "rake clobber"
-        sh "rake test:all"
-    end
-end
-
-task :default => [:spec, :integration_test]
\ No newline at end of file
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml
deleted file mode 100644
index 6bda22291..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml
+++ /dev/null
@@ -1,71 +0,0 @@
----
-
-# Notes:
-# Sample project C code is not presently written to produce a release artifact.
-# As such, release build options are disabled.
-# This sample, therefore, only demonstrates running a collection of unit tests.
-
-:project:
-  :use_exceptions: FALSE
-  :use_test_preprocessor: TRUE
-  :use_auxiliary_dependencies: TRUE
-  :build_root: build
-#  :release_build: TRUE
-  :test_file_prefix: test_
-
-#:release_build:
-#  :output: MyApp.out
-#  :use_assembly: FALSE
-
-:environment:
-
-:extension:
-  :executable: .out
-
-:paths:
-  :test:
-    - +:test/**
-  :source:
-    - src/**
-  :support:
-      
-:defines:
-  # in order to add common defines:
-  #  1) remove the trailing [] from the :common: section
-  #  2) add entries to the :common: section (e.g. :test: has TEST defined)
-  :commmon: &common_defines []
-  :test:
-    - *common_defines
-    - TEST
-  :test_preprocess:
-    - *common_defines
-    - TEST
-
-:cmock:
-  :mock_prefix: mock_
-  :when_no_prototypes: :warn
-  :enforce_strict_ordering: TRUE
-  :plugins:
-    - :ignore
-    - :callback
-  :treat_as:
-    uint8:    HEX8
-    uint16:   HEX16
-    uint32:   UINT32
-    int8:     INT8
-    bool:     UINT8
-
-#:tools:
-# Ceedling defaults to using gcc for compiling, linking, etc.
-# As [:tools] is blank, gcc will be used (so long as it's in your system path)
-# See documentation to configure a given toolchain for use
-
-:plugins:
-  :load_paths:
-    # This change from the default is for running Ceedling out of another folder.
-    - ../../../../plugins
-  :enabled:
-    - stdout_pretty_tests_report
-    - module_generator
-    - fake_function_framework
-...
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/rakefile.rb b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/rakefile.rb
deleted file mode 100644
index e484d5fb7..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/rakefile.rb
+++ /dev/null
@@ -1,7 +0,0 @@
-# This change from the default is for running Ceedling out of another folder.
-PROJECT_CEEDLING_ROOT = "../../../.."
-load "#{PROJECT_CEEDLING_ROOT}/lib/ceedling.rb"
-
-Ceedling.load_project
-
-task :default => %w[ test:all release ]
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/bar.c b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/bar.c
deleted file mode 100644
index 6a403234f..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/bar.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "bar.h"
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/bar.h b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/bar.h
deleted file mode 100644
index febc58653..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/bar.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef bar_H
-#define bar_H
-
-#include "custom_types.h"
-
-void bar_turn_on(void);
-void bar_print_message(const char * message);
-void bar_print_message_formatted(const char * format, ...);
-void bar_numbers(int one, int two, char three);
-void bar_const_test(const char * a, char * const b, const int c);
-custom_t bar_needs_custom_type(void);
-const char * bar_return_const_ptr(int one);
-
-#endif // bar_H
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/custom_types.h b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/custom_types.h
deleted file mode 100644
index b426b32ca..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/custom_types.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef custom_types_H
-#define custom_types_H
-
-typedef int custom_t;
-
-#endif
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c
deleted file mode 100644
index 2f03449b0..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <stdio.h>
-#include "display.h"
-
-void display_turnOffStatusLed(void)
-{
-    printf("Display: Status LED off");
-}
\ No newline at end of file
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.h b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.h
deleted file mode 100644
index def29960c..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#include <stdbool.h>
-
-void display_turnOffStatusLed(void);
-void display_turnOnStatusLed(void);
-void display_setVolume(int level);
-void display_setModeToMinimum(void);
-void display_setModeToMaximum(void);
-void display_setModeToAverage(void);
-bool display_isError(void);
-void display_powerDown(void);
-void display_updateData(int data, void(*updateCompleteCallback)(void));
-
-/*
-    The entry is returned (up to `length` bytes) in the provided `entry` buffer.
-*/
-void display_getKeyboardEntry(char * entry, int length);
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/event_processor.c b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/event_processor.c
deleted file mode 100644
index 916a92360..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/event_processor.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
-    This module implements some business logic to test.
-
-    Signal events by calling the functions on the module.
-*/
-
-#include <stdio.h>
-#include <string.h>
-#include "event_processor.h"
-#include "display.h"
-
-void event_deviceReset(void)
-{
-    //printf ("Device reset\n");
-    display_turnOffStatusLed();
-}
-
-void event_volumeKnobMaxed(void)
-{
-    display_setVolume(11);
-}
-
-void event_powerReadingUpdate(int powerReading)
-{
-    if (powerReading >= 5)
-    {
-        display_turnOnStatusLed();
-    }
-}
-
-void event_modeSelectButtonPressed(void)
-{
-    static int mode = 0;
-
-    if (mode == 0)
-    {
-        display_setModeToMinimum();
-        mode++;
-    }
-    else if (mode == 1)
-    {
-        display_setModeToMaximum();
-        mode++;
-    }
-    else if (mode == 2)
-    {
-        display_setModeToAverage();
-        mode++;
-    }
-    else
-    {
-        mode = 0;
-    }
-}
-
-void event_devicePoweredOn(void)
-{
-    if (display_isError())
-    {
-        display_powerDown();
-    }
-}
-
-void event_keyboardCheckTimerExpired(void)
-{
-    char userEntry[100];
-
-    display_getKeyboardEntry(userEntry, 100);
-
-    if (strcmp(userEntry, "sleep") == 0)
-    {
-        display_powerDown();
-    }
-}
-
-static bool event_lastComplete = false;
-
-/* Function called when the display update is complete. */
-static void displayUpdateComplete(void)
-{
-    event_lastComplete = true;
-}
-
-void event_newDataAvailable(int data)
-{
-    event_lastComplete = false;
-    display_updateData(data, displayUpdateComplete);
-}
-
-bool eventProcessor_isLastEventComplete(void)
-{
-    return event_lastComplete;
-}
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/event_processor.h b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/event_processor.h
deleted file mode 100644
index a79e68c56..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/event_processor.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#include <stdbool.h>
-
-void event_deviceReset(void);
-void event_volumeKnobMaxed(void);
-void event_powerReadingUpdate(int powerReading);
-void event_modeSelectButtonPressed(void);
-void event_devicePoweredOn(void);
-void event_keyboardCheckTimerExpired(void);
-void event_newDataAvailable(int data);
-
-bool eventProcessor_isLastEventComplete(void);
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/foo.c b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/foo.c
deleted file mode 100644
index c05b1154e..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/foo.c
+++ /dev/null
@@ -1,16 +0,0 @@
-#include "foo.h"
-#include "bar.h"
-#include "subfolder/zzz.h"
-
-void foo_turn_on(void) {
-  bar_turn_on();
-  zzz_sleep(1, "sleepy");
-}
-
-void foo_print_message(const char * message) {
-  bar_print_message(message);
-}
-
-void foo_print_special_message(void) {
-  bar_print_message_formatted("The numbers are %d, %d and %d", 1, 2, 3);
-}
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/foo.h b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/foo.h
deleted file mode 100644
index 3fea69940..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/foo.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef foo_H
-#define foo_H
-
-void foo_turn_on(void);
-void foo_print_message(const char * message);
-void foo_print_special_message(void);
-
-#endif // foo_H
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.c b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.c
deleted file mode 100644
index 85f370e12..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "zzz.h"
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.h b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.h
deleted file mode 100644
index 32c52940d..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef zzz_H
-#define zzz_H
-
-int zzz_sleep(int time, char * name);
-
-#endif // zzz_H
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_event_processor.c b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_event_processor.c
deleted file mode 100644
index 9f999443d..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_event_processor.c
+++ /dev/null
@@ -1,155 +0,0 @@
-#include "unity.h"
-#include "event_processor.h"
-#include "mock_display.h"
-#include <string.h>
-
-void setUp (void)
-{
-}
-
-void tearDown (void)
-{
-}
-/*
-    Test that a single function was called.
-*/
-void
-test_whenTheDeviceIsReset_thenTheStatusLedIsTurnedOff()
-{
-    // When
-    event_deviceReset();
-
-    // Then
-    TEST_ASSERT_EQUAL(1, display_turnOffStatusLed_fake.call_count);
-    // or use the helper macro...
-    TEST_ASSERT_CALLED(display_turnOffStatusLed);
-}
-
-/*
-    Test that a single function is NOT called.
-*/
-void
-test_whenThePowerReadingIsLessThan5_thenTheStatusLedIsNotTurnedOn(void)
-{
-    // When
-    event_powerReadingUpdate(4);
-
-    // Then
-    TEST_ASSERT_EQUAL(0, display_turnOnStatusLed_fake.call_count);
-    // or use the helper macro...
-    TEST_ASSERT_NOT_CALLED(display_turnOffStatusLed);
-}
-
-/*
-    Test that a single function was called with the correct arugment.
-*/
-void
-test_whenTheVolumeKnobIsMaxed_thenVolumeDisplayIsSetTo11(void)
-{
-    // When
-    event_volumeKnobMaxed();
-
-    // Then
-    TEST_ASSERT_EQUAL(1, display_setVolume_fake.call_count);
-    // or use the helper macro...
-    TEST_ASSERT_CALLED(display_setVolume);
-    TEST_ASSERT_EQUAL(11, display_setVolume_fake.arg0_val);
-}
-
-/*
-    Test a sequence of calls.
-*/
-
-void
-test_whenTheModeSelectButtonIsPressed_thenTheDisplayModeIsCycled(void)
-{
-    // When
-    event_modeSelectButtonPressed();
-    event_modeSelectButtonPressed();
-    event_modeSelectButtonPressed();
-
-    // Then
-    TEST_ASSERT_EQUAL_PTR((void *)display_setModeToMinimum, fff.call_history[0]);
-    TEST_ASSERT_EQUAL_PTR((void *)display_setModeToMaximum, fff.call_history[1]);
-    TEST_ASSERT_EQUAL_PTR((void *)display_setModeToAverage, fff.call_history[2]);
-    // or use the helper macros...
-    TEST_ASSERT_CALLED_IN_ORDER(0, display_setModeToMinimum);
-    TEST_ASSERT_CALLED_IN_ORDER(1, display_setModeToMaximum);
-    TEST_ASSERT_CALLED_IN_ORDER(2, display_setModeToAverage);
-}
-
-/*
-    Mock a return value from a function.
-*/
-void
-test_givenTheDisplayHasAnError_whenTheDeviceIsPoweredOn_thenTheDisplayIsPoweredDown(void)
-{
-    // Given
-    display_isError_fake.return_val = true;
-
-    // When
-    event_devicePoweredOn();
-
-    // Then
-    TEST_ASSERT_EQUAL(1, display_powerDown_fake.call_count);
-    // or use the helper macro...
-    TEST_ASSERT_CALLED(display_powerDown);
-}
-
-/*
-	Mock a sequence of calls with return values.
-*/
-
-/*
-    Mocking a function with a value returned by reference.
-*/
-void
-test_givenTheUserHasTypedSleep_whenItIsTimeToCheckTheKeyboard_theDisplayIsPoweredDown(void)
-{
-    // Given
-    char mockedEntry[] = "sleep";
-    void return_mock_value(char * entry, int length)
-    {
-        if (length > strlen(mockedEntry))
-        {
-            strncpy(entry, mockedEntry, length);
-        }
-    }
-    display_getKeyboardEntry_fake.custom_fake = return_mock_value;
-
-    // When
-    event_keyboardCheckTimerExpired();
-
-    // Then
-    TEST_ASSERT_EQUAL(1, display_powerDown_fake.call_count);
-    // or use the helper macro...
-    TEST_ASSERT_CALLED(display_powerDown);
-}
-
-/*
-    Mock a function with a function pointer parameter.
-*/
-void
-test_givenNewDataIsAvailable_whenTheDisplayHasUpdated_thenTheEventIsComplete(void)
-{
-    // A mock function for capturing the callback handler function pointer.
-    void(*registeredCallback)(void) = 0;
-    void mock_display_updateData(int data, void(*callback)(void))
-    {
-        //Save the callback function.
-        registeredCallback = callback;
-    }
-    display_updateData_fake.custom_fake = mock_display_updateData;
-
-    // Given
-    event_newDataAvailable(10);
-
-    // When
-    if (registeredCallback != 0)
-    {
-        registeredCallback();
-    }
-
-    // Then
-    TEST_ASSERT_EQUAL(true, eventProcessor_isLastEventComplete());
-}
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_foo.c b/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_foo.c
deleted file mode 100644
index 12dd61a10..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_foo.c
+++ /dev/null
@@ -1,47 +0,0 @@
-#include "unity.h"
-#include "foo.h"
-#include "mock_bar.h"
-#include "mock_zzz.h"
-
-void setUp(void)
-{
-}
-
-void tearDown(void)
-{
-}
-
-void test_foo(void)
-{
-	//When
-	foo_turn_on();
-
-	//Then
-	TEST_ASSERT_EQUAL(1, bar_turn_on_fake.call_count);
-	TEST_ASSERT_EQUAL(1, zzz_sleep_fake.call_count);
-	TEST_ASSERT_EQUAL_STRING("sleepy", zzz_sleep_fake.arg1_val);
-}
-
-void test_foo_again(void)
-{
-	//When
-	foo_turn_on();
-
-	//Then
-	TEST_ASSERT_EQUAL(1, bar_turn_on_fake.call_count);
-}
-
-void test_foo_mock_with_const(void)
-{
-	foo_print_message("123");
-
-	TEST_ASSERT_EQUAL(1, bar_print_message_fake.call_count);
-	TEST_ASSERT_EQUAL_STRING("123", bar_print_message_fake.arg0_val);
-}
-
-void test_foo_mock_with_variable_args(void)
-{
-	foo_print_special_message();
-	TEST_ASSERT_EQUAL(1, bar_print_message_formatted_fake.call_count);
-	TEST_ASSERT_EQUAL_STRING("The numbers are %d, %d and %d", bar_print_message_formatted_fake.arg0_val);
-}
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/lib/fake_function_framework.rb b/test/vendor/ceedling/plugins/fake_function_framework/lib/fake_function_framework.rb
deleted file mode 100644
index 51a90b3a5..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/lib/fake_function_framework.rb
+++ /dev/null
@@ -1,87 +0,0 @@
-require 'ceedling/plugin'
-require 'fff_mock_generator'
-
-class FakeFunctionFramework < Plugin
-
-  # Set up Ceedling to use this plugin.
-  def setup
-    # Get the location of this plugin.
-    @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..'))
-    puts "Using fake function framework (fff)..."
-
-    # Switch out the cmock_builder with our own.
-    @ceedling[:cmock_builder].cmock = FffMockGeneratorForCMock.new(@ceedling[:setupinator].config_hash[:cmock])
-
-    # Add the path to fff.h to the include paths.
-    COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR << "#{@plugin_root}/vendor/fff"
-    COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR << "#{@plugin_root}/src"
-  end
-
-  def post_runner_generate(arg_hash)
-    # After the test runner file has been created, append the FFF globals
-    # definition to the end of the test runner. These globals will be shared by
-    # all mocks linked into the test.
-    File.open(arg_hash[:runner_file], 'a') do |f|
-      f.puts
-      f.puts "//=======Defintions of FFF variables====="
-      f.puts %{#include "fff.h"}
-      f.puts "DEFINE_FFF_GLOBALS;"
-    end
-  end
-
-end # class FakeFunctionFramework
-
-class FffMockGeneratorForCMock
-
-    def initialize(options=nil)
-    @cm_config      = CMockConfig.new(options)
-    @cm_parser      = CMockHeaderParser.new(@cm_config)
-    @silent        = (@cm_config.verbosity < 2)
-
-    # These are the additional files to include in the mock files.
-    @includes_h_pre_orig_header  = (@cm_config.includes || @cm_config.includes_h_pre_orig_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-    @includes_h_post_orig_header = (@cm_config.includes_h_post_orig_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-    @includes_c_pre_header       = (@cm_config.includes_c_pre_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-    @includes_c_post_header      = (@cm_config.includes_c_post_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-  end
-
-  def setup_mocks(files)
-    [files].flatten.each do |src|
-      generate_mock (src)
-    end
-  end
-
-  def generate_mock (header_file_to_mock)
-      module_name = File.basename(header_file_to_mock, '.h')
-      puts "Creating mock for #{module_name}..." unless @silent
-      mock_name = @cm_config.mock_prefix + module_name + @cm_config.mock_suffix
-      mock_path = @cm_config.mock_path
-      if @cm_config.subdir
-          # If a subdirectory has been configured, append it to the mock path.
-          mock_path = "#{mock_path}/#{@cm_config.subdir}"
-      end
-      full_path_for_mock = "#{mock_path}/#{mock_name}"
-
-      # Parse the header file so we know what to mock.
-      parsed_header = @cm_parser.parse(module_name, File.read(header_file_to_mock))
-
-      # Create the directory if it doesn't exist.
-      mkdir_p full_path_for_mock.pathmap("%d")
-
-      # Generate the mock header file.
-      puts "Creating mock: #{full_path_for_mock}.h"
-
-      # Create the mock header.
-      File.open("#{full_path_for_mock}.h", 'w') do |f|
-        f.write(FffMockGenerator.create_mock_header(module_name, mock_name, parsed_header,
-          @includes_h_pre_orig_header, @includes_h_post_orig_header))
-      end
-
-      # Create the mock source file.
-      File.open("#{full_path_for_mock}.c", 'w') do |f|
-        f.write(FffMockGenerator.create_mock_source(mock_name, parsed_header,
-          @includes_c_pre_orig_header, @includes_c_post_orig_header))
-      end
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb b/test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb
deleted file mode 100644
index 9dc03a653..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb
+++ /dev/null
@@ -1,163 +0,0 @@
-# Creates mock files from parsed header files that can be linked into applications.
-# The mocks created are compatible with CMock for use with Ceedling.
-
-class FffMockGenerator
-
-  def self.create_mock_header(module_name, mock_name, parsed_header, pre_includes=nil,
-    post_includes=nil)
-    output = StringIO.new
-    write_opening_include_guard(mock_name, output)
-    output.puts
-    write_extra_includes(pre_includes, output)
-    write_header_includes(module_name, output)
-    write_extra_includes(post_includes, output)
-    output.puts
-    write_typedefs(parsed_header, output)
-    output.puts
-    write_function_declarations(parsed_header, output)
-    output.puts
-    write_control_function_prototypes(mock_name, output)
-    output.puts
-    write_closing_include_guard(mock_name, output)
-    output.string
-  end
-
-  def self.create_mock_source (mock_name, parsed_header, pre_includes=nil,
-    post_includes=nil)
-    output = StringIO.new
-    write_extra_includes(pre_includes, output)
-    write_source_includes(mock_name, output)
-    write_extra_includes(post_includes, output)
-    output.puts
-    write_function_definitions(parsed_header, output)
-    output.puts
-    write_control_function_definitions(mock_name, parsed_header, output)
-    output.string
-  end
-
-  private
-
-# Header file generation functions.
-
-  def self.write_opening_include_guard(mock_name, output)
-    output.puts "#ifndef #{mock_name}_H"
-    output.puts "#define #{mock_name}_H"
-  end
-
-  def self.write_header_includes(module_name, output)
-    output.puts %{#include "fff.h"}
-    output.puts %{#include "fff_unity_helper.h"}
-    output.puts %{#include "#{module_name}.h"}
-  end
-
-  def self.write_typedefs(parsed_header, output)
-    return unless parsed_header.key?(:typedefs)
-    parsed_header[:typedefs].each do |typedef|
-      output.puts typedef
-    end
-  end
-
-  def self.write_function_declarations(parsed_header, output)
-    write_function_macros("DECLARE", parsed_header, output)
-  end
-
-
-  def self.write_control_function_prototypes(mock_name, output)
-    output.puts "void #{mock_name}_Init(void);"
-    output.puts "void #{mock_name}_Verify(void);"
-    output.puts "void #{mock_name}_Destroy(void);"
-  end
-
-  def self.write_closing_include_guard(mock_name, output)
-    output.puts "#endif // #{mock_name}_H"
-  end
-
-# Source file generation functions.
-
-  def self.write_source_includes (mock_name, output)
-    output.puts "#include <string.h>"
-    output.puts %{#include "fff.h"}
-    output.puts %{#include "#{mock_name}.h"}
-  end
-
-  def self.write_function_definitions(parsed_header, output)
-    write_function_macros("DEFINE", parsed_header, output)
-  end
-
-  def self.write_control_function_definitions(mock_name, parsed_header, output)
-    output.puts "void #{mock_name}_Init(void)"
-    output.puts "{"
-    # In the init function, reset the FFF globals. These are used for things
-    # like the call history.
-    output.puts "    FFF_RESET_HISTORY();"
-    
-    # Also, reset all of the fakes.
-    if parsed_header[:functions]
-      parsed_header[:functions].each do |function|
-        output.puts "    RESET_FAKE(#{function[:name]})"
-      end
-    end
-    output.puts "}"
-    output.puts "void #{mock_name}_Verify(void)"
-    output.puts "{"
-    output.puts "}"
-    output.puts "void #{mock_name}_Destroy(void)"
-    output.puts "{"
-    output.puts "}"
-  end
-
-# Shared functions.
-
-  def self.write_extra_includes(includes, output)
-    if includes
-      includes.each {|inc| output.puts "#include #{inc}\n"}
-    end
-  end
-
-  def self.write_function_macros(macro_type, parsed_header, output)
-    return unless parsed_header.key?(:functions)
-    parsed_header[:functions].each do |function|
-      name = function[:name]
-      return_type = function[:return][:type]
-      if function.has_key? :modifier
-          # Prepend any modifier. If there isn't one, trim any leading whitespace.
-          return_type = "#{function[:modifier]} #{return_type}".lstrip
-      end
-      arg_count = function[:args].size
-
-      # Check for variable arguments.
-      var_arg_suffix = ""
-      if function[:var_arg]
-        # If there are are variable arguments, then we need to add this argument
-        # to the count, update the suffix that will get added to the macro.
-        arg_count += 1
-        var_arg_suffix = "_VARARG"
-      end
-
-      # Generate the correct macro.
-      if return_type == 'void'
-        output.print "#{macro_type}_FAKE_VOID_FUNC#{arg_count}#{var_arg_suffix}(#{name}"
-      else
-        output.print "#{macro_type}_FAKE_VALUE_FUNC#{arg_count}#{var_arg_suffix}(#{return_type}, #{name}"
-      end
-
-      # Append each argument type.
-      function[:args].each do |arg|
-        output.print ", "
-        if arg[:const?]
-          output.print "const "
-        end
-        output.print "#{arg[:type]}"
-      end
-
-      # If this argument list ends with a variable argument, add it here at the end.
-      if function[:var_arg]
-        output.print ", ..."
-      end
-
-      # Close the declaration.
-      output.puts ");"
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb b/test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb
deleted file mode 100644
index e6ac11dd0..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb
+++ /dev/null
@@ -1,304 +0,0 @@
-require 'stringio'
-require 'fff_mock_generator.rb'
-require 'header_generator.rb'
-
-# Test the contents of the .h file created for the mock.
-describe "FffMockGenerator.create_mock_header" do
-
-  context "when there is nothing to mock," do
-    let(:mock_header) {
-      parsed_header = {}
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated header file starts with an opening include guard" do
-      expect(mock_header).to start_with(
-          "#ifndef mock_display_H\n" +
-          "#define mock_display_H")
-    end
-    it "then the generated file ends with a closing include guard" do
-      expect(mock_header).to end_with(
-          "#endif // mock_display_H\n")
-    end
-    it "then the generated file includes the fff header" do
-      expect(mock_header).to include(
-          %{#include "fff.h"\n})
-    end
-    it "then the generated file has a prototype for the init function" do
-      expect(mock_header).to include(
-          "void mock_display_Init(void);")
-    end
-    it "then the generated file has a prototype for the verify function" do
-      expect(mock_header).to include(
-          "void mock_display_Verify(void);")
-    end
-    it "then the generated file has a prototype for the destroy function" do
-      expect(mock_header).to include(
-          "void mock_display_Destroy(void);")
-    end
-  end
-
-  context "when there is a function with no args and a void return," do
-      let(:mock_header) {
-        parsed_header = create_cmock_style_parsed_header(
-          [{:name => 'display_turnOffStatusLed', :return_type => 'void'}])
-        FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-      }
-      it "then the generated header file starts with an opening include guard" do
-        expect(mock_header).to start_with(
-          "#ifndef mock_display_H\n" +
-          "#define mock_display_H")
-      end
-      it "then the generated header file contains a fake function declaration" do
-        expect(mock_header).to include(
-          "DECLARE_FAKE_VOID_FUNC0(display_turnOffStatusLed);"
-        )
-      end
-      it "then the generated file ends with a closing include guard" do
-          expect(mock_header).to end_with(
-              "#endif // mock_display_H\n")
-      end
-  end
-
-  context "when there is a function with no args and a bool return," do
-    let(:mock_header) {
-      parsed_header = create_cmock_style_parsed_header(
-        [{:name => 'display_isError', :return_type => 'bool'}])
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the fake function declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VALUE_FUNC0(bool, display_isError);"
-      )
-    end
-  end
-
-  context "when there is a function with no args and an int return," do
-    let(:mock_header) {
-      parsed_header = create_cmock_style_parsed_header(
-        [{:name => 'display_isError', :return_type => 'int'}])
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the fake function declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VALUE_FUNC0(int, display_isError);"
-      )
-    end
-  end
-
-  context "when there is a function with args and a void return," do
-    let(:mock_header) {
-      parsed_header = create_cmock_style_parsed_header(
-        [{:name => 'display_setVolume', :return_type => 'void', :args => ['int']}])
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the fake function declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VOID_FUNC1(display_setVolume, int);"
-      )
-    end
-  end
-
-  context "when there is a function with args and a value return," do
-    let(:mock_header) {
-      parsed_header = create_cmock_style_parsed_header(
-        [{:name => 'a_function', :return_type => 'int', :args => ['char *']}])
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the fake function declaration" do
-      expect(mock_header).to include(
-        "FAKE_VALUE_FUNC1(int, a_function, char *);"
-      )
-    end
-  end
-
-  context "when there is a function with many args and a void return," do
-    let(:mock_header) {
-      parsed_header = create_cmock_style_parsed_header(
-        [{:name => 'a_function', :return_type => 'void',
-          :args => ['int', 'char *', 'int', 'int', 'bool', 'applesauce']}])
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the fake function declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VOID_FUNC6(a_function, int, char *, int, int, bool, applesauce);"
-      )
-    end
-  end
-
-  context "when there are multiple functions," do
-    let(:mock_header) {
-      parsed_header = create_cmock_style_parsed_header(
-        [ {:name => 'a_function', :return_type => 'int', :args => ['char *']},
-          {:name => 'another_function', :return_type => 'void'},
-          {:name => 'three', :return_type => 'bool', :args => ['float', 'int']}
-        ])
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the first fake function declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VALUE_FUNC1(int, a_function, char *);"
-      )
-    end
-    it "then the generated file contains the second fake function declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VOID_FUNC0(another_function);"
-      )
-    end
-    it "then the generated file contains the third fake function declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VALUE_FUNC2(bool, three, float, int);"
-      )
-    end
-  end
-
-  context "when there is a typedef," do
-    let(:mock_header) {
-      parsed_header = create_cmock_style_parsed_header(
-        nil, ["typedef void (*displayCompleteCallback) (void);"])
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the typedef" do
-      expect(mock_header).to include(
-        "typedef void (*displayCompleteCallback) (void);"
-      )
-    end
-  end
-
-  context "when there is a void function with variable arguments" do
-    let(:mock_header){
-      parsed_header = {}
-      parsed_header[:functions] = [{
-        :name => "function_with_var_args",
-        :return => {:type => "void"},
-        :var_arg => "...",
-        :args => [{:type => 'char *'}]
-      }]
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the vararg declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VOID_FUNC2_VARARG(function_with_var_args, char *, ...)"
-      )
-    end
-  end
-
-  context "when there is a function with a return value and variable arguments" do
-    let(:mock_header){
-      parsed_header = {}
-      parsed_header[:functions] = [{
-        :name => "function_with_var_args",
-        :return => {:type => "int"},
-        :var_arg => "...",
-        :args => [{:type => 'char *'}]
-      }]
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the vararg declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VALUE_FUNC2_VARARG(int, function_with_var_args, char *, ...)"
-      )
-    end
-  end
-
-  context "when there is a void function with variable arguments and " +
-          "additional arguments" do
-    let(:mock_header){
-      parsed_header = {}
-      parsed_header[:functions] = [{
-        :name => "function_with_var_args",
-        :return => {:type => "void"},
-        :var_arg => "...",
-        :args => [{:type => 'char *'}, {:type => 'int'}]
-      }]
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the vararg declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VOID_FUNC3_VARARG(function_with_var_args, char *, int, ...)"
-      )
-    end
-  end
-
-  context "when there is a function with a pointer to a const value" do
-    let(:mock_header){
-      parsed_header = {}
-      parsed_header[:functions] = [{
-        :name => "const_test_function",
-        :return => {:type => "void"},
-        :args => [{:type => "char *", :name => "a", :ptr? => false, :const? => true},
-                  {:type => "char *", :name => "b", :ptr? => false, :const? => false}]
-      }]
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the correct const argument in the declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VOID_FUNC2(const_test_function, const char *, char *)"
-      )
-    end
-  end
-
-  context "when there is a function that returns a const pointer" do
-    let(:mock_header){
-      parsed_header = {}
-      parsed_header[:functions] = [{
-        :name => "return_const_pointer_test_function",
-        :modifier => "const",
-        :return => {:type => "char *" },
-        :args => [{:type => "int", :name => "a"}]
-      }]
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the correct const return value in the declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VALUE_FUNC1(const char *, return_const_pointer_test_function, int)"
-      )
-    end
-  end
-  
-  context "when there is a function that returns a const int" do
-    let(:mock_header){
-      parsed_header = {}
-      parsed_header[:functions] = [{
-        :name => "return_const_int_test_function",
-        :modifier => "const",
-        :return => {:type => "int" },
-        :args => []
-      }]
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header)
-    }
-    it "then the generated file contains the correct const return value in the declaration" do
-      expect(mock_header).to include(
-        "DECLARE_FAKE_VALUE_FUNC0(const int, return_const_int_test_function)"
-      )
-    end
-  end
-
-  context "when there are pre-includes" do
-    let(:mock_header) {
-      parsed_header = {}
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header,
-        [%{"another_header.h"}])
-    }
-    it "then they are included before the other files" do
-      expect(mock_header).to include(
-        %{#include "another_header.h"\n} +
-        %{#include "fff.h"}
-      )
-    end
-  end
-
-  context "when there are post-includes" do
-    let(:mock_header) {
-      parsed_header = {}
-      FffMockGenerator.create_mock_header("display", "mock_display", parsed_header,
-        nil, [%{"another_header.h"}])
-    }
-    it "then they are included after the other files" do
-      expect(mock_header).to include(
-        %{#include "display.h"\n} +
-        %{#include "another_header.h"\n}
-      )
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb b/test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb
deleted file mode 100644
index 364f8521e..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb
+++ /dev/null
@@ -1,149 +0,0 @@
-require 'stringio'
-require 'fff_mock_generator.rb'
-
-# Test the contents of the .c file created for the mock.
-describe "FffMockGenerator.create_mock_source" do
-
-  context "when there is nothing to mock," do
-    let(:mock_source) {
-      parsed_header = {}
-      FffMockGenerator.create_mock_source("mock_my_module", parsed_header)
-    }
-    it "then the generated file includes the fff header" do
-      expect(mock_source).to include(
-        # fff.h also requires including string.h
-        %{#include <string.h>\n} +
-        %{#include "fff.h"}
-      )
-    end
-    it "then the generated file includes the mock header" do
-      expect(mock_source).to include(
-        %{#include "mock_my_module.h"\n}
-      )
-    end
-    it "then the generated file defines the init function" do
-      expect(mock_source).to include(
-        "void mock_my_module_Init(void)\n" +
-        "{\n" +
-        "    FFF_RESET_HISTORY();\n" +
-        "}"
-      )
-    end
-    it "then the generated file defines the verify function" do
-      expect(mock_source).to include(
-        "void mock_my_module_Verify(void)\n" +
-        "{\n" +
-        "}"
-      )
-    end
-    it "then the generated file defines the destroy function" do
-      expect(mock_source).to include(
-        "void mock_my_module_Destroy(void)\n" +
-        "{\n" +
-        "}"
-      )
-    end
-  end
-
-  context "when there are multiple functions," do
-    let(:mock_source) {
-      parsed_header = create_cmock_style_parsed_header(
-        [ {:name => 'a_function', :return_type => 'int', :args => ['char *']},
-          {:name => 'another_function', :return_type => 'void'},
-          {:name => 'three', :return_type => 'bool', :args => ['float', 'int']}
-        ])
-      FffMockGenerator.create_mock_source("mock_display", parsed_header)
-    }
-    it "then the generated file contains the first fake function definition" do
-      expect(mock_source).to include(
-        "DEFINE_FAKE_VALUE_FUNC1(int, a_function, char *);"
-      )
-    end
-    it "then the generated file contains the second fake function definition" do
-      expect(mock_source).to include(
-        "DEFINE_FAKE_VOID_FUNC0(another_function);"
-      )
-    end
-    it "then the generated file contains the third fake function definition" do
-      expect(mock_source).to include(
-        "DEFINE_FAKE_VALUE_FUNC2(bool, three, float, int);"
-      )
-    end
-    it "then the init function resets all of the fakes" do
-      expect(mock_source).to include(
-        "void mock_display_Init(void)\n" +
-        "{\n" +
-        "    FFF_RESET_HISTORY();\n" +
-        "    RESET_FAKE(a_function)\n" +
-        "    RESET_FAKE(another_function)\n" +
-        "    RESET_FAKE(three)\n" +
-        "}"
-      )
-    end
-  end
-
-  context "when there is a void function with variable arguments and " +
-          "additional arguments" do
-    let(:mock_source){
-      parsed_header = {}
-      parsed_header[:functions] = [{
-        :name => "function_with_var_args",
-        :return => {:type => "void"},
-        :var_arg => "...",
-        :args => [{:type => 'char *'}, {:type => 'int'}]
-      }]
-      FffMockGenerator.create_mock_source("mock_display", parsed_header)
-    }
-    it "then the generated file contains the vararg definition" do
-      expect(mock_source).to include(
-        "DEFINE_FAKE_VOID_FUNC3_VARARG(function_with_var_args, char *, int, ...)"
-      )
-    end
-  end
-
-  context "when there is a function with a pointer to a const value" do
-    let(:mock_source){
-      parsed_header = {}
-      parsed_header[:functions] = [{
-        :name => "const_test_function",
-        :return => {:type => "void"},
-        :args => [{:type => "char *", :name => "a", :ptr? => false, :const? => true},
-                  {:type => "char *", :name => "b", :ptr? => false, :const? => false}]
-      }]
-      FffMockGenerator.create_mock_source("mock_display", parsed_header)
-    }
-    it "then the generated file contains the correct const argument in the declaration" do
-      expect(mock_source).to include(
-        "DEFINE_FAKE_VOID_FUNC2(const_test_function, const char *, char *)"
-      )
-    end
-  end
-
-  context "when there are pre-includes" do
-    let(:mock_source) {
-      parsed_source = {}
-      FffMockGenerator.create_mock_source("mock_display", parsed_source,
-        [%{"another_header.h"}])
-    }
-    it "then they are included before the other files" do
-      expect(mock_source).to include(
-        %{#include "another_header.h"\n} +
-        %{#include <string.h>}
-      )
-    end
-  end
-
-  context "when there are post-includes" do
-    let(:mock_source) {
-      parsed_source = {}
-      FffMockGenerator.create_mock_source("mock_display", parsed_source,
-        nil, [%{"another_header.h"}])
-    }
-    it "then they are included before the other files" do
-      expect(mock_source).to include(
-        %{#include "mock_display.h"\n} +
-        %{#include "another_header.h"\n}
-      )
-    end
-  end
-end
\ No newline at end of file
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb b/test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb
deleted file mode 100644
index cda278440..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb
+++ /dev/null
@@ -1,51 +0,0 @@
-# Create a CMock-style parsed header hash. This the type of hash created by
-# CMock when parsing header files for automock generation. It contains all of
-# includes, typedefs and functions (with return types and arguments) parsed from
-# the header file.
-def create_cmock_style_parsed_header(functions, typedefs = nil)
-  parsed_header = {
-      :includes => nil,
-      :functions => [],
-      :typedefs => []
-  }
-
-  # Add the typedefs.
-  if typedefs
-      typedefs.each do |typedef|
-          parsed_header[:typedefs] << typedef
-      end
-  end
-
-  # Add the functions.
-  if functions
-    functions.each do |function|
-      # Build the array of arguments.
-      args = []
-      if function.key?(:args)
-        function[:args].each do |arg|
-          args << {
-            :type => arg
-          }
-        end
-      end
-      parsed_header[:functions] << {
-        :name => function[:name],
-        :modifier => "",
-        :return => {
-          :type => function[:return_type],
-          :name => "cmock_to_return",
-          :ptr? => false,
-          :const? => false,
-          :str => "void cmock_to_return",
-          :void? => true
-        },
-        :var_arg => nil,
-        :args_string => "void",
-        :args => args,
-        :args_call => "",
-        :contains_ptr? => false
-      }
-    end
-  end
-  parsed_header
-end
\ No newline at end of file
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/spec/spec_helper.rb b/test/vendor/ceedling/plugins/fake_function_framework/spec/spec_helper.rb
deleted file mode 100644
index 25dc80ace..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/spec/spec_helper.rb
+++ /dev/null
@@ -1,96 +0,0 @@
-# This file was generated by the `rspec --init` command. Conventionally, all
-# specs live under a `spec` directory, which RSpec adds to the `$LOAD_PATH`.
-# The generated `.rspec` file contains `--require spec_helper` which will cause
-# this file to always be loaded, without a need to explicitly require it in any
-# files.
-#
-# Given that it is always loaded, you are encouraged to keep this file as
-# light-weight as possible. Requiring heavyweight dependencies from this file
-# will add to the boot time of your test suite on EVERY test run, even for an
-# individual file that may not need all of that loaded. Instead, consider making
-# a separate helper file that requires the additional dependencies and performs
-# the additional setup, and require it from the spec files that actually need
-# it.
-#
-# The `.rspec` file also contains a few flags that are not defaults but that
-# users commonly want.
-#
-# See http://rubydoc.info/gems/rspec-core/RSpec/Core/Configuration
-RSpec.configure do |config|
-  # rspec-expectations config goes here. You can use an alternate
-  # assertion/expectation library such as wrong or the stdlib/minitest
-  # assertions if you prefer.
-  config.expect_with :rspec do |expectations|
-    # This option will default to `true` in RSpec 4. It makes the `description`
-    # and `failure_message` of custom matchers include text for helper methods
-    # defined using `chain`, e.g.:
-    #     be_bigger_than(2).and_smaller_than(4).description
-    #     # => "be bigger than 2 and smaller than 4"
-    # ...rather than:
-    #     # => "be bigger than 2"
-    expectations.include_chain_clauses_in_custom_matcher_descriptions = true
-  end
-
-  # rspec-mocks config goes here. You can use an alternate test double
-  # library (such as bogus or mocha) by changing the `mock_with` option here.
-  config.mock_with :rspec do |mocks|
-    # Prevents you from mocking or stubbing a method that does not exist on
-    # a real object. This is generally recommended, and will default to
-    # `true` in RSpec 4.
-    mocks.verify_partial_doubles = true
-  end
-
-# The settings below are suggested to provide a good initial experience
-# with RSpec, but feel free to customize to your heart's content.
-=begin
-  # These two settings work together to allow you to limit a spec run
-  # to individual examples or groups you care about by tagging them with
-  # `:focus` metadata. When nothing is tagged with `:focus`, all examples
-  # get run.
-  config.filter_run :focus
-  config.run_all_when_everything_filtered = true
-
-  # Allows RSpec to persist some state between runs in order to support
-  # the `--only-failures` and `--next-failure` CLI options. We recommend
-  # you configure your source control system to ignore this file.
-  config.example_status_persistence_file_path = "spec/examples.txt"
-
-  # Limits the available syntax to the non-monkey patched syntax that is
-  # recommended. For more details, see:
-  #   - http://rspec.info/blog/2012/06/rspecs-new-expectation-syntax/
-  #   - http://www.teaisaweso.me/blog/2013/05/27/rspecs-new-message-expectation-syntax/
-  #   - http://rspec.info/blog/2014/05/notable-changes-in-rspec-3/#zero-monkey-patching-mode
-  config.disable_monkey_patching!
-
-  # This setting enables warnings. It's recommended, but in some cases may
-  # be too noisy due to issues in dependencies.
-  config.warnings = true
-
-  # Many RSpec users commonly either run the entire suite or an individual
-  # file, and it's useful to allow more verbose output when running an
-  # individual spec file.
-  if config.files_to_run.one?
-    # Use the documentation formatter for detailed output,
-    # unless a formatter has already been configured
-    # (e.g. via a command-line flag).
-    config.default_formatter = 'doc'
-  end
-
-  # Print the 10 slowest examples and example groups at the
-  # end of the spec run, to help surface which specs are running
-  # particularly slow.
-  config.profile_examples = 10
-
-  # Run specs in random order to surface order dependencies. If you find an
-  # order dependency and want to debug it, you can fix the order by providing
-  # the seed, which is printed after each run.
-  #     --seed 1234
-  config.order = :random
-
-  # Seed global randomization in this process using the `--seed` CLI option.
-  # Setting this allows you to use `--seed` to deterministically reproduce
-  # test failures related to randomization by passing the same `--seed` value
-  # as the one that triggered the failure.
-  Kernel.srand config.seed
-=end
-end
diff --git a/test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h b/test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h
deleted file mode 100644
index de3db44aa..000000000
--- a/test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef fff_unity_helper_H
-#define fff_unity_helper_H
-
-/*
-    FFF helper macros for Unity.
-*/
-
-/*
-    Fail if the function was not called the expected number of times.
-*/
-#define TEST_ASSERT_CALLED_TIMES(times_, function_)                         \
-    TEST_ASSERT_EQUAL_MESSAGE(times_,                                       \
-        function_ ## _fake.call_count,                                      \
-        "Function " #function_ " called the incorrect number of times.")
-/*
-    Fail if the function was not called exactly once.
-*/
-#define TEST_ASSERT_CALLED(function_) TEST_ASSERT_CALLED_TIMES(1, function_)
-
-/*
-    Fail if the function was called 1 or more times.
-*/
-#define TEST_ASSERT_NOT_CALLED(function_) TEST_ASSERT_CALLED_TIMES(0, function_)
-
-/*
-    Fail if the function was not called in this particular order.
-*/
-#define TEST_ASSERT_CALLED_IN_ORDER(order_, function_)                      \
-    TEST_ASSERT_EQUAL_PTR_MESSAGE((void *) function_,                       \
-        fff.call_history[order_],                                           \
-        "Function " #function_ " not called in order " #order_ )
-
-#endif
\ No newline at end of file
diff --git a/test/vendor/ceedling/plugins/gcov/README.md b/test/vendor/ceedling/plugins/gcov/README.md
deleted file mode 100644
index 096ffa100..000000000
--- a/test/vendor/ceedling/plugins/gcov/README.md
+++ /dev/null
@@ -1,101 +0,0 @@
-ceedling-gcov
-=============
-
-# Plugin Overview
-
-Plugin for integrating GNU GCov code coverage tool into Ceedling projects.
-Currently only designed for the gcov command (like LCOV for example). In the
-future we could configure this to work with other code coverage tools.
-
-This plugin currently uses `gcovr` to generate HTML and/or XML reports as a
-utility. The normal gcov plugin _must_ be run first for this report to generate.
-
-## Installation
-
-Gcovr can be installed via pip like so:
-
-```
-pip install gcovr
-```
-
-## Configuration
-
-The gcov plugin supports configuration options via your `project.yml` provided
-by Ceedling.
-
-Generation of HTML reports may be enabled or disabled with the following
-config. Set to `true` to enable or set to `false` to disable.
-
-```
-:gcov:
-  :html_report: true
-```
-
-Generation of XML reports may be enabled or disabled with the following
-config. Set to `true` to enable or set to `false` to disable.
-
-```
-:gcov:
-  :xml_report: true
-```
-
-There are two types of gcovr HTML reports that can be configured in your
-`project.yml`. To create a basic HTML report, with only the overall file
-information, use the following config.
-
-```
-:gcov:
-  :html_report_type: basic
-```
-
-To create a detailed HTML report, with line by line breakdown of the
-coverage, use the following config.
-
-```
-:gcov:
-  :html_report_type: detailed
-```
-
-There are a number of options to control which files are considered part of
-the coverage report. Most often, we only care about coverage on our source code, and not
-on tests or automatically generated mocks, runners, etc. However, there are times 
-where this isn't true... or there are times where we've moved ceedling's directory 
-structure so that the project file isn't at the root of the project anymore. In these
-cases, you may need to tweak the following:
-
-```
-:gcov:
-  :report_root: "."
-  :report_exclude: "^build|^vendor|^test|^support"
-  :report_include: "^src"
-```
-
-One important note about html_report_root: gcovr will only take a single root folder, unlike 
-Ceedling's ability to take as many as you like. So you will need to choose a folder which is 
-a superset of ALL the folders you want, and then use the include or exclude options to set up
-patterns of files to pay attention to or ignore. It's not ideal, but it works.
-
-Finally, there are a number of settings which can be specified in order to adjust the
-default behaviors of gcov:
-
-```
-:gcov:
-  :html_medium_threshold: 75
-  :html_high_threshold: 90
-  :fail_under_line: 30
-  :fail_under_branch: 30
-```
-
-These HTML and XML reports will be found in `build/artifacts/gcov`.
-
-## Example Usage
-
-```
-ceedling gcov:all utils:gcov
-```
-
-## To-Do list
-
-- Generate overall report (combined statistics from all files with coverage)
-- Generate coverage output files
-- Easier option override for better customisation 
diff --git a/test/vendor/ceedling/plugins/gcov/assets/template.erb b/test/vendor/ceedling/plugins/gcov/assets/template.erb
deleted file mode 100644
index 5e5a1742b..000000000
--- a/test/vendor/ceedling/plugins/gcov/assets/template.erb
+++ /dev/null
@@ -1,15 +0,0 @@
-% function_string = hash[:coverage][:functions].to_s
-% branch_string   = hash[:coverage][:branches].to_s
-% format_string   = "%#{[function_string.length, branch_string.length].max}i"
-<%=@ceedling[:plugin_reportinator].generate_banner("#{GCOV_ROOT_NAME.upcase}: CODE COVERAGE SUMMARY")%>
-% if (!hash[:coverage][:functions].nil?)
-FUNCTIONS: <%=sprintf(format_string, hash[:coverage][:functions])%>%
-% else
-FUNCTIONS: none
-% end
-% if (!hash[:coverage][:branches].nil?)
-BRANCHES:  <%=sprintf(format_string, hash[:coverage][:branches])%>%
-% else
-BRANCHES:  none
-% end
-
diff --git a/test/vendor/ceedling/plugins/gcov/config/defaults.yml b/test/vendor/ceedling/plugins/gcov/config/defaults.yml
deleted file mode 100644
index 13bac556e..000000000
--- a/test/vendor/ceedling/plugins/gcov/config/defaults.yml
+++ /dev/null
@@ -1,73 +0,0 @@
----
-
-:tools:
-  :gcov_compiler:
-    :executable: gcc
-    :arguments:
-      - -g
-      - -fprofile-arcs
-      - -ftest-coverage
-      - -I"$": COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR
-      - -I"$": COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE
-      - -D$: COLLECTION_DEFINES_TEST_AND_VENDOR
-      - -DGCOV_COMPILER
-      - -DCODE_COVERAGE
-      - -c "${1}"
-      - -o "${2}"
-  :gcov_linker:
-    :executable: gcc
-    :arguments:
-      - -fprofile-arcs
-      - -ftest-coverage
-      - ${1}
-      - -o ${2}
-      - ${3}
-  :gcov_fixture:
-    :executable: ${1}
-  :gcov_report:
-    :executable: gcov
-    :arguments:
-      - -n
-      - -p
-      - -b
-      - -o "$": GCOV_BUILD_OUTPUT_PATH
-      - "\"${1}\""
-  :gcov_post_report:
-    :executable: gcovr
-    :optional: TRUE
-    :arguments:
-        - -p
-        - -b
-        - ${1}
-        - --html
-        - -o GcovCoverageResults.html
-  :gcov_post_report_basic:
-    :executable: gcovr
-    :optional: TRUE
-    :arguments:
-        - -p
-        - -b
-        - ${1}
-        - --html
-        - -o  "$": GCOV_ARTIFACTS_FILE
-  :gcov_post_report_advanced:
-    :executable: gcovr
-    :optional: TRUE
-    :arguments:
-        - -p
-        - -b
-        - ${1}
-        - --html
-        - --html-details
-        - -o  "$": GCOV_ARTIFACTS_FILE
-  :gcov_post_report_xml:
-    :executable: gcovr
-    :optional: TRUE
-    :arguments:
-        - -p
-        - -b
-        - ${1}
-        - --xml
-        - -o  "$": GCOV_ARTIFACTS_FILE_XML
-
-...
diff --git a/test/vendor/ceedling/plugins/gcov/gcov.rake b/test/vendor/ceedling/plugins/gcov/gcov.rake
deleted file mode 100644
index 3acab8566..000000000
--- a/test/vendor/ceedling/plugins/gcov/gcov.rake
+++ /dev/null
@@ -1,220 +0,0 @@
-directory(GCOV_BUILD_OUTPUT_PATH)
-directory(GCOV_RESULTS_PATH)
-directory(GCOV_ARTIFACTS_PATH)
-directory(GCOV_DEPENDENCIES_PATH)
-
-CLEAN.include(File.join(GCOV_BUILD_OUTPUT_PATH, '*'))
-CLEAN.include(File.join(GCOV_RESULTS_PATH, '*'))
-CLEAN.include(File.join(GCOV_ARTIFACTS_PATH, '*'))
-CLEAN.include(File.join(GCOV_DEPENDENCIES_PATH, '*'))
-
-CLOBBER.include(File.join(GCOV_BUILD_PATH, '**/*'))
-
-rule(/#{GCOV_BUILD_OUTPUT_PATH}\/#{'.+\\' + EXTENSION_OBJECT}$/ => [
-       proc do |task_name|
-         @ceedling[:file_finder].find_compilation_input_file(task_name)
-       end
-     ]) do |object|
-
-  if File.basename(object.source) =~ /^(#{PROJECT_TEST_FILE_PREFIX}|#{CMOCK_MOCK_PREFIX}|#{GCOV_IGNORE_SOURCES.join('|')})/i
-    @ceedling[:generator].generate_object_file(
-      TOOLS_GCOV_COMPILER,
-      OPERATION_COMPILE_SYM,
-      GCOV_SYM,
-      object.source,
-      object.name,
-      @ceedling[:file_path_utils].form_test_build_list_filepath(object.name)
-    )
-  else
-    @ceedling[GCOV_SYM].generate_coverage_object_file(object.source, object.name)
-  end
-end
-
-rule(/#{GCOV_BUILD_OUTPUT_PATH}\/#{'.+\\' + EXTENSION_EXECUTABLE}$/) do |bin_file|
-  lib_args = @ceedling[:test_invoker].convert_libraries_to_arguments()
-
-  @ceedling[:generator].generate_executable_file(
-    TOOLS_GCOV_LINKER,
-    GCOV_SYM,
-    bin_file.prerequisites,
-    bin_file.name,
-    lib_args,
-    @ceedling[:file_path_utils].form_test_build_map_filepath(bin_file.name)
-  )
-end
-
-rule(/#{GCOV_RESULTS_PATH}\/#{'.+\\' + EXTENSION_TESTPASS}$/ => [
-       proc do |task_name|
-         @ceedling[:file_path_utils].form_test_executable_filepath(task_name)
-       end
-     ]) do |test_result|
-  @ceedling[:generator].generate_test_results(TOOLS_GCOV_FIXTURE, GCOV_SYM, test_result.source, test_result.name)
-end
-
-rule(/#{GCOV_DEPENDENCIES_PATH}\/#{'.+\\' + EXTENSION_DEPENDENCIES}$/ => [
-       proc do |task_name|
-         @ceedling[:file_finder].find_compilation_input_file(task_name)
-       end
-     ]) do |dep|
-  @ceedling[:generator].generate_dependencies_file(
-    TOOLS_TEST_DEPENDENCIES_GENERATOR,
-    GCOV_SYM,
-    dep.source,
-    File.join(GCOV_BUILD_OUTPUT_PATH, File.basename(dep.source).ext(EXTENSION_OBJECT)),
-    dep.name
-  )
-end
-
-task directories: [GCOV_BUILD_OUTPUT_PATH, GCOV_RESULTS_PATH, GCOV_DEPENDENCIES_PATH, GCOV_ARTIFACTS_PATH]
-
-namespace GCOV_SYM do
-  task source_coverage: COLLECTION_ALL_SOURCE.pathmap("#{GCOV_BUILD_OUTPUT_PATH}/%n#{@ceedling[:configurator].extension_object}")
-
-  desc 'Run code coverage for all tests'
-  task all: [:directories] do
-    @ceedling[:configurator].replace_flattened_config(@ceedling[GCOV_SYM].config)
-    @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, GCOV_SYM)
-    @ceedling[:configurator].restore_config
-  end
-
-  desc 'Run single test w/ coverage ([*] real test or source file name, no path).'
-  task :* do
-    message = "\nOops! '#{GCOV_ROOT_NAME}:*' isn't a real task. " \
-              "Use a real test or source file name (no path) in place of the wildcard.\n" \
-              "Example: rake #{GCOV_ROOT_NAME}:foo.c\n\n"
-
-    @ceedling[:streaminator].stdout_puts(message)
-  end
-
-  desc 'Run tests by matching regular expression pattern.'
-  task :pattern, [:regex] => [:directories] do |_t, args|
-    matches = []
-
-    COLLECTION_ALL_TESTS.each do |test|
-      matches << test if test =~ /#{args.regex}/
-    end
-
-    if !matches.empty?
-      @ceedling[:configurator].replace_flattened_config(@ceedling[GCOV_SYM].config)
-      @ceedling[:test_invoker].setup_and_invoke(matches, GCOV_SYM, force_run: false)
-      @ceedling[:configurator].restore_config
-    else
-      @ceedling[:streaminator].stdout_puts("\nFound no tests matching pattern /#{args.regex}/.")
-    end
-  end
-
-  desc 'Run tests whose test path contains [dir] or [dir] substring.'
-  task :path, [:dir] => [:directories] do |_t, args|
-    matches = []
-
-    COLLECTION_ALL_TESTS.each do |test|
-      matches << test if File.dirname(test).include?(args.dir.tr('\\', '/'))
-    end
-
-    if !matches.empty?
-      @ceedling[:configurator].replace_flattened_config(@ceedling[GCOV_SYM].config)
-      @ceedling[:test_invoker].setup_and_invoke(matches, GCOV_SYM, force_run: false)
-      @ceedling[:configurator].restore_config
-    else
-      @ceedling[:streaminator].stdout_puts("\nFound no tests including the given path or path component.")
-    end
-  end
-
-  desc 'Run code coverage for changed files'
-  task delta: [:directories] do
-    @ceedling[:configurator].replace_flattened_config(@ceedling[GCOV_SYM].config)
-    @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, GCOV_SYM, force_run: false)
-    @ceedling[:configurator].restore_config
-  end
-
-  # use a rule to increase efficiency for large projects
-  # gcov test tasks by regex
-  rule(/^#{GCOV_TASK_ROOT}\S+$/ => [
-         proc do |task_name|
-           test = task_name.sub(/#{GCOV_TASK_ROOT}/, '')
-           test = "#{PROJECT_TEST_FILE_PREFIX}#{test}" unless test.start_with?(PROJECT_TEST_FILE_PREFIX)
-           @ceedling[:file_finder].find_test_from_file_path(test)
-         end
-       ]) do |test|
-    @ceedling[:rake_wrapper][:directories].invoke
-    @ceedling[:configurator].replace_flattened_config(@ceedling[GCOV_SYM].config)
-    @ceedling[:test_invoker].setup_and_invoke([test.source], GCOV_SYM)
-    @ceedling[:configurator].restore_config
-  end
-end
-
-if PROJECT_USE_DEEP_DEPENDENCIES
-  namespace REFRESH_SYM do
-    task GCOV_SYM do
-      @ceedling[:configurator].replace_flattened_config(@ceedling[GCOV_SYM].config)
-      @ceedling[:test_invoker].refresh_deep_dependencies
-      @ceedling[:configurator].restore_config
-    end
-  end
-end
-
-namespace UTILS_SYM do
-  def gcov_args_builder(opts)
-    args = ""
-    args += "-r \"#{opts[:gcov_report_root] || '.'}\" " 
-    args += "-f \"#{opts[:gcov_report_include]}\" " unless opts[:gcov_report_include].nil?
-    args += "-e \"#{opts[:gcov_report_exclude] || GCOV_FILTER_EXCLUDE}\" "
-    [ :gcov_fail_under_line, :gcov_fail_under_branch, :gcov_html_medium_threshold, :gcov_html_high_threshold].each do |opt|
-      args += "--#{opt.to_s.gsub('_','-').sub(/:?gcov-/,'')} #{opts[opt]} " unless opts[opt].nil?
-    end
-    return args
-  end
-
-  desc 'Create gcov code coverage html report (must run ceedling gcov first)'
-  task GCOV_SYM do
-
-    if !File.directory? GCOV_ARTIFACTS_PATH
-      FileUtils.mkdir_p GCOV_ARTIFACTS_PATH
-    end
-
-    args = gcov_args_builder(@ceedling[:configurator].project_config_hash)
-
-    if @ceedling[:configurator].project_config_hash[:gcov_html_report].nil?
-      puts "In your project.yml, define: \n\n:gcov:\n  :html_report:\n\n to true or false to refine this feature."
-      puts "For now, assumimg you want an html report generated."
-      html_enabled = true
-    else
-      html_enabled = @ceedling[:configurator].project_config_hash[:gcov_html_report]
-    end
-
-    if @ceedling[:configurator].project_config_hash[:gcov_xml_report].nil?
-      puts "In your project.yml, define: \n\n:gcov:\n  :xml_report:\n\n to true or false to refine this feature."
-      puts "For now, assumimg you do not want an xml report generated."
-      xml_enabled = false
-    else
-      xml_enabled = @ceedling[:configurator].project_config_hash[:gcov_xml_report]
-    end
-
-    if html_enabled
-      if @ceedling[:configurator].project_config_hash[:gcov_html_report_type] == 'basic'
-        puts "Creating a basic html report of gcov results in #{GCOV_ARTIFACTS_FILE}..."
-        command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_POST_REPORT_BASIC, [], args)
-        @ceedling[:tool_executor].exec(command[:line], command[:options])
-      elsif @ceedling[:configurator].project_config_hash[:gcov_html_report_type] == 'detailed'
-        puts "Creating a detailed html report of gcov results in #{GCOV_ARTIFACTS_FILE}..."
-        command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_POST_REPORT_ADVANCED, [], args)
-        @ceedling[:tool_executor].exec(command[:line], command[:options])
-
-      else
-        puts "In your project.yml, define: \n\n:gcov:\n  :html_report_type:\n\n to basic or detailed to refine this feature."
-        puts "For now, just creating basic."
-        puts "Creating a basic html report of gcov results in #{GCOV_ARTIFACTS_FILE}..."
-        command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_POST_REPORT_BASIC, [], args)
-        @ceedling[:tool_executor].exec(command[:line], command[:options])
-      end
-    end
-
-    if xml_enabled
-      puts "Creating an xml report of gcov results in #{GCOV_ARTIFACTS_FILE_XML}..."
-      command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_POST_REPORT_XML, [], filter)
-      @ceedling[:tool_executor].exec(command[:line], command[:options])
-    end
-
-    puts "Done."
-  end
-end
diff --git a/test/vendor/ceedling/plugins/gcov/lib/gcov.rb b/test/vendor/ceedling/plugins/gcov/lib/gcov.rb
deleted file mode 100644
index 15a1b4cfa..000000000
--- a/test/vendor/ceedling/plugins/gcov/lib/gcov.rb
+++ /dev/null
@@ -1,113 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-require 'gcov_constants'
-
-class Gcov < Plugin
-  attr_reader :config
-
-  def setup
-    @result_list = []
-
-    @config = {
-      project_test_build_output_path: GCOV_BUILD_OUTPUT_PATH,
-      project_test_build_output_c_path: GCOV_BUILD_OUTPUT_PATH,
-      project_test_results_path: GCOV_RESULTS_PATH,
-      project_test_dependencies_path: GCOV_DEPENDENCIES_PATH,
-      defines_test: DEFINES_TEST + ['CODE_COVERAGE'],
-      gcov_html_report_filter: GCOV_FILTER_EXCLUDE
-    }
-
-    @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..'))
-    @coverage_template_all = @ceedling[:file_wrapper].read(File.join(@plugin_root, 'assets/template.erb'))
-  end
-
-  def generate_coverage_object_file(source, object)
-    lib_args = @ceedling[:test_invoker].convert_libraries_to_arguments()
-    compile_command =
-      @ceedling[:tool_executor].build_command_line(
-        TOOLS_GCOV_COMPILER,
-        @ceedling[:flaginator].flag_down(OPERATION_COMPILE_SYM, GCOV_SYM, source),
-        source,
-        object,
-        @ceedling[:file_path_utils].form_test_build_list_filepath(object),
-        lib_args
-      )
-    @ceedling[:streaminator].stdout_puts("Compiling #{File.basename(source)} with coverage...")
-    @ceedling[:tool_executor].exec(compile_command[:line], compile_command[:options])
-  end
-
-  def post_test_fixture_execute(arg_hash)
-    result_file = arg_hash[:result_file]
-
-    if (result_file =~ /#{GCOV_RESULTS_PATH}/) && !@result_list.include?(result_file)
-      @result_list << arg_hash[:result_file]
-    end
-  end
-
-  def post_build
-    return unless @ceedling[:task_invoker].invoked?(/^#{GCOV_TASK_ROOT}/)
-
-    # test results
-    results = @ceedling[:plugin_reportinator].assemble_test_results(@result_list)
-    hash = {
-      header: GCOV_ROOT_NAME.upcase,
-      results: results
-    }
-
-    @ceedling[:plugin_reportinator].run_test_results_report(hash) do
-      message = ''
-      message = 'Unit test failures.' if results[:counts][:failed] > 0
-      message
-    end
-
-    report_per_file_coverage_results(@ceedling[:test_invoker].sources)
-  end
-
-  def summary
-    result_list = @ceedling[:file_path_utils].form_pass_results_filelist(GCOV_RESULTS_PATH, COLLECTION_ALL_TESTS)
-
-    # test results
-    # get test results for only those tests in our configuration and of those only tests with results on disk
-    hash = {
-      header: GCOV_ROOT_NAME.upcase,
-      results: @ceedling[:plugin_reportinator].assemble_test_results(result_list, boom: false)
-    }
-
-    @ceedling[:plugin_reportinator].run_test_results_report(hash)
-  end
-
-  private ###################################
-
-  def report_per_file_coverage_results(sources)
-    banner = @ceedling[:plugin_reportinator].generate_banner "#{GCOV_ROOT_NAME.upcase}: CODE COVERAGE SUMMARY"
-    @ceedling[:streaminator].stdout_puts "\n" + banner
-
-    coverage_sources = sources.clone
-    coverage_sources.delete_if { |item| item =~ /#{CMOCK_MOCK_PREFIX}.+#{EXTENSION_SOURCE}$/ }
-    coverage_sources.delete_if { |item| item =~ /#{GCOV_IGNORE_SOURCES.join('|')}#{EXTENSION_SOURCE}$/ }
-
-    coverage_sources.each do |source|
-      basename         = File.basename(source)
-      command          = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_REPORT, [], [basename])
-      shell_results    = @ceedling[:tool_executor].exec(command[:line], command[:options])
-      coverage_results = shell_results[:output]
-
-      if coverage_results.strip =~ /(File\s+'#{Regexp.escape(source)}'.+$)/m
-        report = Regexp.last_match(1).lines.to_a[1..-1].map { |line| basename + ' ' + line }.join('')
-        @ceedling[:streaminator].stdout_puts(report + "\n\n")
-      end
-    end
-
-    COLLECTION_ALL_SOURCE.each do |source|
-      unless coverage_sources.include?(source)
-        @ceedling[:streaminator].stdout_puts("Could not find coverage results for " + source + "\n")
-      end
-    end
-  end
-end
-
-# end blocks always executed following rake run
-END {
-  # cache our input configurations to use in comparison upon next execution
-  @ceedling[:cacheinator].cache_test_config(@ceedling[:setupinator].config_hash) if @ceedling[:task_invoker].invoked?(/^#{GCOV_TASK_ROOT}/)
-}
diff --git a/test/vendor/ceedling/plugins/gcov/lib/gcov_constants.rb b/test/vendor/ceedling/plugins/gcov/lib/gcov_constants.rb
deleted file mode 100644
index 539d46f75..000000000
--- a/test/vendor/ceedling/plugins/gcov/lib/gcov_constants.rb
+++ /dev/null
@@ -1,19 +0,0 @@
-
-GCOV_ROOT_NAME         = 'gcov'.freeze
-GCOV_TASK_ROOT         = GCOV_ROOT_NAME + ':'
-GCOV_SYM               = GCOV_ROOT_NAME.to_sym
-
-GCOV_BUILD_PATH        = File.join(PROJECT_BUILD_ROOT, GCOV_ROOT_NAME)
-GCOV_BUILD_OUTPUT_PATH = File.join(GCOV_BUILD_PATH, "out")
-GCOV_RESULTS_PATH      = File.join(GCOV_BUILD_PATH, "results")
-GCOV_DEPENDENCIES_PATH = File.join(GCOV_BUILD_PATH, "dependencies")
-GCOV_ARTIFACTS_PATH    = File.join(PROJECT_BUILD_ARTIFACTS_ROOT, GCOV_ROOT_NAME)
-
-GCOV_ARTIFACTS_FILE    = File.join(GCOV_ARTIFACTS_PATH, "GcovCoverageResults.html")
-GCOV_ARTIFACTS_FILE_XML    = File.join(GCOV_ARTIFACTS_PATH, "GcovCoverageResults.xml")
-
-GCOV_IGNORE_SOURCES    = %w(unity cmock cexception).freeze
-
-GCOV_FILTER_EXCLUDE    = '^vendor.*|^build.*|^test.*|^lib.*'
-
-
diff --git a/test/vendor/ceedling/plugins/junit_tests_report/README.md b/test/vendor/ceedling/plugins/junit_tests_report/README.md
deleted file mode 100644
index 1259fd668..000000000
--- a/test/vendor/ceedling/plugins/junit_tests_report/README.md
+++ /dev/null
@@ -1,36 +0,0 @@
-junit_tests_report
-====================
-
-## Overview
-
-The junit_tests_report plugin creates an XML file of test results in JUnit
-format, which is handy for Continuous Integration build servers or as input
-into other reporting tools. The XML file is output to the appropriate
-`<build_root>/artifacts/` directory (e.g. `artifacts/test/` for test tasks,
-`artifacts/gcov/` for gcov, or `artifacts/bullseye/` for bullseye runs).
-
-## Setup
-
-Enable the plugin in your project.yml by adding `junit_tests_report`
-to the list of enabled plugins.
-
-``` YAML
-:plugins:
-  :enabled:
-    - junit_tests_report
-```
-
-## Configuration
-
-Optionally configure the output / artifact filename in your project.yml with
-the `artifact_filename` configuration option. The default filename is
-`report.xml`.
-
-You can also configure the path that this artifact is stored. This can be done
-by setting `path`. The default is that it will be placed in a subfolder under
-the `build` directory.
-
-``` YAML
-:junit_tests_report:
-  :artifact_filename: report_junit.xml
-```
diff --git a/test/vendor/ceedling/plugins/junit_tests_report/lib/junit_tests_report.rb b/test/vendor/ceedling/plugins/junit_tests_report/lib/junit_tests_report.rb
deleted file mode 100644
index a777d07d7..000000000
--- a/test/vendor/ceedling/plugins/junit_tests_report/lib/junit_tests_report.rb
+++ /dev/null
@@ -1,129 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-
-class JunitTestsReport < Plugin
-
-  def setup
-    @results_list = {}
-    @test_counter = 0
-    @time_result = []
-  end
-
-  def post_test_fixture_execute(arg_hash)
-    context = arg_hash[:context]
-
-    @results_list[context] = [] if (@results_list[context].nil?)
-
-    @results_list[context] << arg_hash[:result_file]
-    @time_result << arg_hash[:shell_result][:time]
-
-  end
-
-  def post_build
-    @results_list.each_key do |context|
-      results = @ceedling[:plugin_reportinator].assemble_test_results(@results_list[context])
-
-      artifact_filename = @ceedling[:configurator].project_config_hash[:junit_tests_report_artifact_filename] || 'report.xml'
-      artifact_fullpath = @ceedling[:configurator].project_config_hash[:junit_tests_report_path] || File.join(PROJECT_BUILD_ARTIFACTS_ROOT, context.to_s)
-      file_path = File.join(artifact_fullpath, artifact_filename)
-
-      @ceedling[:file_wrapper].open( file_path, 'w' ) do |f|
-        @testsuite_counter = 0
-        @testcase_counter = 0
-        suites = reorganise_results( results )
-
-        write_header( results, f )
-        suites.each{|suite| write_suite( suite, f ) }
-        write_footer( f )
-      end
-    end
-  end
-
-  private
-
-  def write_header( results, stream )
-    results[:counts][:time] = @time_result.reduce(0, :+)
-    stream.puts '<?xml version="1.0" encoding="utf-8" ?>'
-    stream.puts('<testsuites tests="%<total>d" failures="%<failed>d" skipped="%<ignored>d" time="%<time>f">' % results[:counts])
-  end
-
-  def write_footer( stream )
-    stream.puts '</testsuites>'
-  end
-
-  def reorganise_results( results )
-    # Reorganise the output by test suite instead of by result
-    suites = Hash.new{ |h,k| h[k] = {collection: [], total: 0, success: 0, failed: 0, ignored: 0, stdout: []} }
-    results[:successes].each do |result|
-      source = result[:source]
-      name = source[:file].sub(/\..{1,4}$/, "")
-      suites[name][:collection] += result[:collection].map{|test| test.merge(result: :success)}
-      suites[name][:total] += result[:collection].length
-      suites[name][:success] += result[:collection].length
-    end
-    results[:failures].each do |result|
-      source = result[:source]
-      name = source[:file].sub(/\..{1,4}$/, "")
-      suites[name][:collection] += result[:collection].map{|test| test.merge(result: :failed)}
-      suites[name][:total] += result[:collection].length
-      suites[name][:failed] += result[:collection].length
-    end
-    results[:ignores].each do |result|
-      source = result[:source]
-      name = source[:file].sub(/\..{1,4}$/, "")
-      suites[name][:collection] += result[:collection].map{|test| test.merge(result: :ignored)}
-      suites[name][:total] += result[:collection].length
-      suites[name][:ignored] += result[:collection].length
-    end
-    results[:stdout].each do |result|
-      source = result[:source]
-      name = source[:file].sub(/\..{1,4}$/, "")
-      suites[name][:stdout] += result[:collection]
-    end
-    suites.map{|name, data| data.merge(name: name) }
-  end
-
-  def write_suite( suite, stream )
-    suite[:time] = @time_result.shift
-    stream.puts('  <testsuite name="%<name>s" tests="%<total>d" failures="%<failed>d" skipped="%<ignored>d" time="%<time>f">' % suite)
-
-    suite[:collection].each do |test|
-      write_test( test, stream )
-    end
-
-    unless suite[:stdout].empty?
-      stream.puts('    <system-out>')
-      suite[:stdout].each do |line|
-        line.gsub!(/&/, '&amp;')
-        line.gsub!(/</, '&lt;')
-        line.gsub!(/>/, '&gt;')
-        line.gsub!(/"/, '&quot;')
-        line.gsub!(/'/, '&apos;')
-        stream.puts(line)
-      end
-      stream.puts('    </system-out>')
-    end
-
-    stream.puts('  </testsuite>')
-  end
-
-  def write_test( test, stream )
-    test[:test].gsub!('"', '&quot;')
-    case test[:result]
-    when :success
-      stream.puts('    <testcase name="%<test>s" />' % test)
-    when :failed
-      stream.puts('    <testcase name="%<test>s">' % test)
-      if test[:message].empty?
-        stream.puts('      <failure />')
-      else
-        stream.puts('      <failure message="%s" />' % test[:message])
-      end
-      stream.puts('    </testcase>')
-    when :ignored
-      stream.puts('    <testcase name="%<test>s">' % test)
-      stream.puts('      <skipped />')
-      stream.puts('    </testcase>')
-    end
-  end
-end
diff --git a/test/vendor/ceedling/plugins/module_generator/config/module_generator.yml b/test/vendor/ceedling/plugins/module_generator/config/module_generator.yml
deleted file mode 100644
index cdb2da2eb..000000000
--- a/test/vendor/ceedling/plugins/module_generator/config/module_generator.yml
+++ /dev/null
@@ -1,4 +0,0 @@
-:module_generator:
-  :project_root: ./
-  :source_root: src/
-  :test_root: test/
\ No newline at end of file
diff --git a/test/vendor/ceedling/plugins/module_generator/lib/module_generator.rb b/test/vendor/ceedling/plugins/module_generator/lib/module_generator.rb
deleted file mode 100644
index b2fac006d..000000000
--- a/test/vendor/ceedling/plugins/module_generator/lib/module_generator.rb
+++ /dev/null
@@ -1,70 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-require 'erb'
-require 'fileutils'
-
-class ModuleGenerator < Plugin
-
-  attr_reader :config
-
-  def create(module_name, optz={})
-
-    require "generate_module.rb" #From Unity Scripts
-
-    if ((!optz.nil?) && (optz[:destroy]))
-      UnityModuleGenerator.new( divine_options(optz) ).destroy(module_name)
-    else
-      UnityModuleGenerator.new( divine_options(optz) ).generate(module_name)
-    end
-  end
-
-  private
-
-  def divine_options(optz={})
-    unity_generator_options =
-    {
-      :path_src     => ((defined? MODULE_GENERATOR_SOURCE_ROOT ) ? MODULE_GENERATOR_SOURCE_ROOT.gsub('\\', '/').sub(/^\//, '').sub(/\/$/, '') : "src" ),
-      :path_inc     => ((defined? MODULE_GENERATOR_INC_ROOT ) ?
-                                 MODULE_GENERATOR_INC_ROOT.gsub('\\', '/').sub(/^\//, '').sub(/\/$/, '')
-                                 : (defined? MODULE_GENERATOR_SOURCE_ROOT ) ?
-                                 MODULE_GENERATOR_SOURCE_ROOT.gsub('\\', '/').sub(/^\//, '').sub(/\/$/, '')
-                                 : "src" ),
-      :path_tst     => ((defined? MODULE_GENERATOR_TEST_ROOT   ) ? MODULE_GENERATOR_TEST_ROOT.gsub(  '\\', '/').sub(/^\//, '').sub(/\/$/, '') : "test" ),
-      :pattern      => optz[:pattern],
-      :test_prefix  => ((defined? PROJECT_TEST_FILE_PREFIX     ) ? PROJECT_TEST_FILE_PREFIX : "Test" ),
-      :mock_prefix  => ((defined? CMOCK_MOCK_PREFIX            ) ? CMOCK_MOCK_PREFIX : "Mock" ),
-      :includes     => ((defined? MODULE_GENERATOR_INCLUDES    ) ? MODULE_GENERATOR_INCLUDES : {} ),
-      :boilerplates => ((defined? MODULE_GENERATOR_BOILERPLATES) ? MODULE_GENERATOR_BOILERPLATES : {} ),
-      :naming       => ((defined? MODULE_GENERATOR_NAMING      ) ? MODULE_GENERATOR_NAMING : nil ),
-      :update_svn   => ((defined? MODULE_GENERATOR_UPDATE_SVN  ) ? MODULE_GENERATOR_UPDATE_SVN : false ),
-    }
-
-    # Read Boilerplate template file.
-    if (defined? MODULE_GENERATOR_BOILERPLATE_FILES)
-
-      bf = MODULE_GENERATOR_BOILERPLATE_FILES
-
-      if !bf[:src].nil? && File.exists?(bf[:src]) 
-        unity_generator_options[:boilerplates][:src] = File.read(bf[:src])
-      end
-
-      if !bf[:inc].nil? && File.exists?(bf[:inc]) 
-        unity_generator_options[:boilerplates][:inc] = File.read(bf[:inc])
-      end
-
-      if !bf[:tst].nil? && File.exists?(bf[:tst]) 
-        unity_generator_options[:boilerplates][:tst] = File.read(bf[:tst])
-      end
-    end
-
-    # If using "create[<module_root>:<module_name>]" option from command line.
-    unless optz[:module_root_path].to_s.empty?
-      unity_generator_options[:path_src] = File.join(optz[:module_root_path], unity_generator_options[:path_src])
-      unity_generator_options[:path_inc] = File.join(optz[:module_root_path], unity_generator_options[:path_inc])
-      unity_generator_options[:path_tst] = File.join(optz[:module_root_path], unity_generator_options[:path_tst])
-    end
-
-    return unity_generator_options
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/module_generator/module_generator.rake b/test/vendor/ceedling/plugins/module_generator/module_generator.rake
deleted file mode 100644
index e88e346aa..000000000
--- a/test/vendor/ceedling/plugins/module_generator/module_generator.rake
+++ /dev/null
@@ -1,47 +0,0 @@
-
-namespace :module do
-  module_root_separator = ":"
-
-  desc "Generate module (source, header and test files)"
-  task :create, :module_path do |t, args|
-    files = [args[:module_path]] + (args.extras || [])
-    optz = { :module_root_path => "" }
-    ["dh", "dih", "mch", "mvp", "src", "test"].each do |pat|
-      p = files.delete(pat)
-      optz[:pattern] = p unless p.nil?
-    end
-    files.each do |v|
-      module_root_path, module_name = v.split(module_root_separator, 2)
-      if module_name
-        optz[:module_root_path] = module_root_path
-        v = module_name
-      end
-      if (v =~ /^test_?/i)
-        # If the name of the file starts with test, automatically treat it as one
-        @ceedling[:module_generator].create(v.sub(/^test_?/i,''), optz.merge({:pattern => 'test'}))
-      else
-        # Otherwise, go through the normal procedure
-        @ceedling[:module_generator].create(v, optz)
-      end
-    end
-  end
-
-  desc "Destroy module (source, header and test files)"
-  task :destroy, :module_path do |t, args|
-    files = [args[:module_path]] + (args.extras || [])
-    optz = { :destroy => true, :module_root_path => "" }
-    ["dh", "dih", "mch", "mvp", "src", "test"].each do |pat|
-      p = files.delete(pat)
-      optz[:pattern] = p unless p.nil?
-    end
-    files.each do |v|
-      module_root_path, module_name = v.split(module_root_separator, 2)
-      if module_name
-        optz[:module_root_path] = module_root_path
-        v = module_name
-      end
-      @ceedling[:module_generator].create(v, optz)
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/raw_output_report/lib/raw_output_report.rb b/test/vendor/ceedling/plugins/raw_output_report/lib/raw_output_report.rb
deleted file mode 100644
index 014e67714..000000000
--- a/test/vendor/ceedling/plugins/raw_output_report/lib/raw_output_report.rb
+++ /dev/null
@@ -1,41 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-
-class RawOutputReport < Plugin
-  def setup
-    @log_paths = {}
-  end
-
-  def post_test_fixture_execute(arg_hash)
-    output = strip_output(arg_hash[:shell_result][:output])
-    write_raw_output_log(arg_hash, output)
-  end
-
-  private
-
-  def strip_output(raw_output)
-    output = ""
-    raw_output.each_line do |line|
-      next if line =~ /^\n$/
-      next if line =~ /^.*:\d+:.*:(IGNORE|PASS|FAIL)/
-      return output if line =~/^-----------------------\n$/
-      output << line
-    end
-  end
-  def write_raw_output_log(arg_hash, output)
-    logging = generate_log_path(arg_hash)
-    @ceedling[:file_wrapper].write(logging[:path], output , logging[:flags]) unless logging.nil?
-  end
-
-  def generate_log_path(arg_hash)
-    f_name = File.basename(arg_hash[:result_file], '.pass')
-    base_path = File.join(PROJECT_BUILD_ARTIFACTS_ROOT, arg_hash[:context].to_s)
-    file_path = File.join(base_path, f_name + '.log')
-
-    if @ceedling[:file_wrapper].exist?(base_path)
-      return { path: file_path, flags: 'w' }
-    end
-
-    nil
-  end
-end
diff --git a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/assets/template.erb b/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/assets/template.erb
deleted file mode 100644
index fb8e3b13a..000000000
--- a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/assets/template.erb
+++ /dev/null
@@ -1,84 +0,0 @@
-% ignored        = hash[:results][:counts][:ignored]
-% failed         = hash[:results][:counts][:failed]
-% stdout_count   = hash[:results][:counts][:stdout]
-% header_prepend = ((hash[:header].length > 0) ? "#{hash[:header]}: " : '')
-% banner_width   = 25 + header_prepend.length # widest message
-% results = {}
-% hash[:results][:successes].each do |testresult|
-%   results[ testresult[:source][:file] ] = testresult[:collection]
-%   results[ testresult[:source][:file] ].length.times do |i|
-%     results[ testresult[:source][:file] ][i][:pass] = true
-%   end
-% end
-% hash[:results][:ignores].each do |testresult|
-%   if (results[ testresult[:source][:file] ].nil?)
-%     results[ testresult[:source][:file] ] = testresult[:collection]
-%   else
-%     results[ testresult[:source][:file] ] += testresult[:collection]
-%   end
-%   results[ testresult[:source][:file] ].length.times do |i|
-%     results[ testresult[:source][:file] ][i][:pass] = true
-%   end
-% end
-% hash[:results][:failures].each do |testresult|
-%   if (results[ testresult[:source][:file] ].nil?)
-%     results[ testresult[:source][:file] ] = testresult[:collection]
-%   else
-%     results[ testresult[:source][:file] ] += testresult[:collection]
-%   end
-% end
-
-
-[==========] Running <%=hash[:results][:counts][:total].to_s%> tests from <%=results.length.to_s%> test cases.
-[----------] Global test environment set-up.
-% results.each_pair do |modulename, moduledetails|
-[----------] <%=moduledetails.length.to_s%> tests from <%=modulename%>
-%   moduledetails.each do |item|
-[ RUN      ] <%=modulename%>.<%=item[:test]%>
-%     if (not item[:pass])
-%       if (not item[:message].empty?)
-<%=modulename%>(<%=item[:line]%>): error: <%=item[:message]%>
-
-%         m = item[:message].match(/Expected\s+(.*)\s+Was\s+([^\.]*)\./)
-%         if m.nil?
- Actual:   FALSE
- Expected: TRUE
-%         else
- Actual:   <%=m[2]%>
- Expected: <%=m[1]%>
-%         end
-%       else
-<%=modulename%>(<%=item[:line]%>): fail: <%=item[:message]%>
- Actual:   FALSE
- Expected: TRUE
-%       end
-[  FAILED  ] <%=modulename%>.<%=item[:test]%> (0 ms)
-%     else
-[       OK ] <%=modulename%>.<%=item[:test]%> (0 ms)
-%     end
-%   end
-[----------] <%=moduledetails.length.to_s%> tests from <%=modulename%> (0 ms total)
-% end
-
-% if (hash[:results][:counts][:total] > 0)
-[----------] Global test environment tear-down.
-[==========] <%=hash[:results][:counts][:total].to_s%> tests from <%=hash[:results][:stdout].length.to_s%> test cases ran.
-[  PASSED  ] <%=hash[:results][:counts][:passed].to_s%> tests.
-%   if (failed == 0)
-[  FAILED  ] 0 tests.
-
- 0 FAILED TESTS
-%   else
-[  FAILED  ] <%=failed.to_s%> tests, listed below:
-%     hash[:results][:failures].each do |failure|
-%       failure[:collection].each do |item|
-[  FAILED  ] <%=failure[:source][:file]%>.<%=item[:test]%>
-%       end
-%     end
-%   end
-
- <%=failed.to_s%> FAILED TESTS
-% else
-
-No tests executed.
-% end
diff --git a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/assets/template.erb copy b/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/assets/template.erb copy
deleted file mode 100644
index a90f495e2..000000000
--- a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/assets/template.erb copy	
+++ /dev/null
@@ -1,59 +0,0 @@
-% ignored        = hash[:results][:counts][:ignored]
-% failed         = hash[:results][:counts][:failed]
-% stdout_count   = hash[:results][:counts][:stdout]
-% header_prepend = ((hash[:header].length > 0) ? "#{hash[:header]}: " : '')
-% banner_width   = 25 + header_prepend.length # widest message
-
-
-% if (stdout_count > 0)
-[==========] Running <%=hash[:results][:counts][:total].to_s%> tests from <%=hash[:results][:stdout].length.to_s%> test cases.
-[----------] Global test environment set-up.
-% end
-% if (failed > 0)
-%   hash[:results][:failures].each do |failure|
-[----------] <%=failure[:collection].length.to_s%> tests from <%=failure[:source][:file]%>
-%     failure[:collection].each do |item|
-[ RUN      ] <%=failure[:source][:file]%>.<%=item[:test]%>
-% if (not item[:message].empty?)
-<%=failure[:source][:file]%>(<%=item[:line]%>): error: <%=item[:message]%>
-
-%   m = item[:message].match(/Expected\s+(.*)\s+Was\s+([^\.]*)\./)
-%    if m.nil?
- Actual:   FALSE
- Expected: TRUE
-%    else
- Actual:   <%=m[2]%>
- Expected: <%=m[1]%>
-%    end
-% else
-<%=failure[:source][:file]%>(<%=item[:line]%>): fail: <%=item[:message]%>
- Actual:   FALSE
- Expected: TRUE
-% end
-[  FAILED  ] <%=failure[:source][:file]%>.<%=item[:test]%> (0 ms)
-%     end
-[----------] <%=failure[:collection].length.to_s%> tests from <%=failure[:source][:file]%> (0 ms total)
-%   end
-% end
-% if (hash[:results][:counts][:total] > 0)
-[----------] Global test environment tear-down.
-[==========] <%=hash[:results][:counts][:total].to_s%> tests from <%=hash[:results][:stdout].length.to_s%> test cases ran.
-[  PASSED  ] <%=hash[:results][:counts][:passed].to_s%> tests.
-% if (failed == 0)
-[  FAILED  ] 0 tests.
-
- 0 FAILED TESTS
-% else
-[  FAILED  ] <%=failed.to_s%> tests, listed below:
-%   hash[:results][:failures].each do |failure|
-%     failure[:collection].each do |item|
-[  FAILED  ] <%=failure[:source][:file]%>.<%=item[:test]%>
-%     end
-%   end
-
- <%=failed.to_s%> FAILED TESTS
-% end
-% else
-
-No tests executed.
-% end
diff --git a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/config/stdout_gtestlike_tests_report.yml b/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/config/stdout_gtestlike_tests_report.yml
deleted file mode 100644
index c25acf511..000000000
--- a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/config/stdout_gtestlike_tests_report.yml
+++ /dev/null
@@ -1,4 +0,0 @@
----
-:plugins:
-  # tell Ceedling we got results display taken care of
-  :display_raw_test_results: FALSE
diff --git a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/lib/stdout_gtestlike_tests_report.rb b/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/lib/stdout_gtestlike_tests_report.rb
deleted file mode 100644
index a51438a38..000000000
--- a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/lib/stdout_gtestlike_tests_report.rb
+++ /dev/null
@@ -1,43 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/defaults'
-
-class StdoutGtestlikeTestsReport < Plugin
-
-  def setup
-    @result_list = []
-    @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..'))
-    template = @ceedling[:file_wrapper].read(File.join(@plugin_root, 'assets/template.erb'))
-    @ceedling[:plugin_reportinator].register_test_results_template( template )
-  end
-
-  def post_test_fixture_execute(arg_hash)
-    return if not (arg_hash[:context] == TEST_SYM)
-
-    @result_list << arg_hash[:result_file]
-  end
-
-  def post_build
-    return if not (@ceedling[:task_invoker].test_invoked?)
-
-    results = @ceedling[:plugin_reportinator].assemble_test_results(@result_list)
-    hash = {
-      :header => '',
-      :results => results
-    }
-
-    @ceedling[:plugin_reportinator].run_test_results_report(hash)
-  end
-
-  def summary
-    result_list = @ceedling[:file_path_utils].form_pass_results_filelist( PROJECT_TEST_RESULTS_PATH, COLLECTION_ALL_TESTS )
-
-    # get test results for only those tests in our configuration and of those only tests with results on disk
-    hash = {
-      :header => '',
-      :results => @ceedling[:plugin_reportinator].assemble_test_results(result_list, {:boom => false})
-    }
-
-    @ceedling[:plugin_reportinator].run_test_results_report(hash)
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/stdout_ide_tests_report/config/stdout_ide_tests_report.yml b/test/vendor/ceedling/plugins/stdout_ide_tests_report/config/stdout_ide_tests_report.yml
deleted file mode 100644
index c25acf511..000000000
--- a/test/vendor/ceedling/plugins/stdout_ide_tests_report/config/stdout_ide_tests_report.yml
+++ /dev/null
@@ -1,4 +0,0 @@
----
-:plugins:
-  # tell Ceedling we got results display taken care of
-  :display_raw_test_results: FALSE
diff --git a/test/vendor/ceedling/plugins/stdout_ide_tests_report/lib/stdout_ide_tests_report.rb b/test/vendor/ceedling/plugins/stdout_ide_tests_report/lib/stdout_ide_tests_report.rb
deleted file mode 100644
index 48b3e819c..000000000
--- a/test/vendor/ceedling/plugins/stdout_ide_tests_report/lib/stdout_ide_tests_report.rb
+++ /dev/null
@@ -1,44 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/defaults'
-
-class StdoutIdeTestsReport < Plugin
-
-  def setup
-    @result_list = []
-  end
-
-  def post_test_fixture_execute(arg_hash)
-    return if not (arg_hash[:context] == TEST_SYM)
-
-    @result_list << arg_hash[:result_file]
-  end
-
-  def post_build
-    return if (not @ceedling[:task_invoker].test_invoked?)
-
-    results = @ceedling[:plugin_reportinator].assemble_test_results(@result_list)
-    hash = {
-      :header => '',
-      :results => results
-    }
-
-    @ceedling[:plugin_reportinator].run_test_results_report(hash) do
-      message = ''
-      message = 'Unit test failures.' if (hash[:results][:counts][:failed] > 0)
-      message
-    end
-  end
-
-  def summary
-    result_list = @ceedling[:file_path_utils].form_pass_results_filelist( PROJECT_TEST_RESULTS_PATH, COLLECTION_ALL_TESTS )
-
-    # get test results for only those tests in our configuration and of those only tests with results on disk
-    hash = {
-      :header => '',
-      :results => @ceedling[:plugin_reportinator].assemble_test_results(result_list, {:boom => false})
-    }
-
-    @ceedling[:plugin_reportinator].run_test_results_report(hash)
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb b/test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb
deleted file mode 100644
index 52b29f7f0..000000000
--- a/test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb
+++ /dev/null
@@ -1,59 +0,0 @@
-% ignored        = hash[:results][:counts][:ignored]
-% failed         = hash[:results][:counts][:failed]
-% stdout_count   = hash[:results][:counts][:stdout]
-% header_prepend = ((hash[:header].length > 0) ? "#{hash[:header]}: " : '')
-% banner_width   = 25 + header_prepend.length # widest message
-
-% if (stdout_count > 0)
-<%=@ceedling[:plugin_reportinator].generate_banner(header_prepend + 'TEST OUTPUT')%>
-%   hash[:results][:stdout].each do |string|
-[<%=string[:source][:file]%>]
-%     string[:collection].each do |item|
-  - "<%=item%>"
-%     end
-
-%   end
-% end
-% if (ignored > 0)
-<%=@ceedling[:plugin_reportinator].generate_banner(header_prepend + 'IGNORED TEST SUMMARY')%>
-%   hash[:results][:ignores].each do |ignore|
-[<%=ignore[:source][:file]%>]
-%     ignore[:collection].each do |item|
-  Test: <%=item[:test]%>
-% if (not item[:message].empty?)
-  At line (<%=item[:line]%>): "<%=item[:message]%>"
-% else
-  At line (<%=item[:line]%>)
-% end
-
-%     end
-%   end
-% end
-% if (failed > 0)
-<%=@ceedling[:plugin_reportinator].generate_banner(header_prepend + 'FAILED TEST SUMMARY')%>
-%   hash[:results][:failures].each do |failure|
-[<%=failure[:source][:file]%>]
-%     failure[:collection].each do |item|
-  Test: <%=item[:test]%>
-% if (not item[:message].empty?)
-  At line (<%=item[:line]%>): "<%=item[:message]%>"
-% else
-  At line (<%=item[:line]%>)
-% end
-
-%     end
-%   end
-% end
-% total_string = hash[:results][:counts][:total].to_s
-% format_string = "%#{total_string.length}i"
-<%=@ceedling[:plugin_reportinator].generate_banner(header_prepend + 'OVERALL TEST SUMMARY')%>
-% if (hash[:results][:counts][:total] > 0)
-TESTED:  <%=hash[:results][:counts][:total].to_s%>
-PASSED:  <%=sprintf(format_string, hash[:results][:counts][:passed])%>
-FAILED:  <%=sprintf(format_string, failed)%>
-IGNORED: <%=sprintf(format_string, ignored)%>
-% else
-
-No tests executed.
-% end
-
diff --git a/test/vendor/ceedling/plugins/stdout_pretty_tests_report/config/stdout_pretty_tests_report.yml b/test/vendor/ceedling/plugins/stdout_pretty_tests_report/config/stdout_pretty_tests_report.yml
deleted file mode 100644
index c25acf511..000000000
--- a/test/vendor/ceedling/plugins/stdout_pretty_tests_report/config/stdout_pretty_tests_report.yml
+++ /dev/null
@@ -1,4 +0,0 @@
----
-:plugins:
-  # tell Ceedling we got results display taken care of
-  :display_raw_test_results: FALSE
diff --git a/test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb b/test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb
deleted file mode 100644
index 018388fc1..000000000
--- a/test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb
+++ /dev/null
@@ -1,47 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/defaults'
-
-class StdoutPrettyTestsReport < Plugin
-  
-  def setup
-    @result_list = []
-    @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..'))
-    template = @ceedling[:file_wrapper].read(File.join(@plugin_root, 'assets/template.erb'))
-    @ceedling[:plugin_reportinator].register_test_results_template( template )
-  end
-  
-  def post_test_fixture_execute(arg_hash)
-    return if not (arg_hash[:context] == TEST_SYM)
-  
-    @result_list << arg_hash[:result_file]
-  end
-  
-  def post_build
-    return if not (@ceedling[:task_invoker].test_invoked?)
-
-    results = @ceedling[:plugin_reportinator].assemble_test_results(@result_list)
-    hash = {
-      :header => '',
-      :results => results
-    }
-
-    @ceedling[:plugin_reportinator].run_test_results_report(hash) do
-      message = ''
-      message = 'Unit test failures.' if (results[:counts][:failed] > 0)
-      message
-    end
-  end
-
-  def summary
-    result_list = @ceedling[:file_path_utils].form_pass_results_filelist( PROJECT_TEST_RESULTS_PATH, COLLECTION_ALL_TESTS )
-
-    # get test results for only those tests in our configuration and of those only tests with results on disk
-    hash = {
-      :header => '',
-      :results => @ceedling[:plugin_reportinator].assemble_test_results(result_list, {:boom => false})
-    }
-
-    @ceedling[:plugin_reportinator].run_test_results_report(hash)
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/subprojects/README.md b/test/vendor/ceedling/plugins/subprojects/README.md
deleted file mode 100644
index e51a4e60e..000000000
--- a/test/vendor/ceedling/plugins/subprojects/README.md
+++ /dev/null
@@ -1,63 +0,0 @@
-ceedling-subprojects
-====================
-
-Plugin for supporting subprojects that are built as static libraries. It continues to support  
-dependency tracking, without getting confused between your main project files and your   
-subproject files. It accepts different compiler flags and linker flags, allowing you to   
-optimize for your situation.
-
-First, you're going to want to add the extension to your list of known extensions:
-
-```
-:extension:
-  :subprojects: '.a'
-```
-
-Define a new section called :subprojects. There, you can list as many subprojects  
-as you may need under the :paths key. For each, you specify a unique place to build  
-and a unique name.
-
-```
-:subprojects:  
-  :paths:
-   - :name: libprojectA
-     :source:
-       - ./subprojectA/first/dir
-       - ./subprojectA/second/dir
-     :include:
-       - ./subprojectA/include/dir
-     :build_root: ./subprojectA/build/dir
-     :defines: 
-       - DEFINE_JUST_FOR_THIS_FILE
-       - AND_ANOTHER
-   - :name: libprojectB
-     :source:
-       - ./subprojectB/only/dir
-     :include:
-       - ./subprojectB/first/include/dir
-       - ./subprojectB/second/include/dir
-     :build_root: ./subprojectB/build/dir
-     :defines: [] #none for this one
-```
-
-You can specify the compiler and linker, just as you would a release build:
-
-```
-:tools:
-  :subprojects_compiler:
-    :executable: gcc
-    :arguments:
-      - -g
-      - -I"$": COLLECTION_PATHS_SUBPROJECTS
-      - -D$: COLLECTION_DEFINES_SUBPROJECTS
-      - -c "${1}"
-      - -o "${2}"
-  :subprojects_linker:
-    :executable: ar
-    :arguments:
-      - rcs
-      - ${2}
-      - ${1}
-```
-
-That's all there is to it! Happy Hacking!
diff --git a/test/vendor/ceedling/plugins/subprojects/config/defaults.yml b/test/vendor/ceedling/plugins/subprojects/config/defaults.yml
deleted file mode 100644
index 1045a595f..000000000
--- a/test/vendor/ceedling/plugins/subprojects/config/defaults.yml
+++ /dev/null
@@ -1,33 +0,0 @@
----
-#:extension:
-#  :subprojects: '.a'
-
-:subprojects:
-  :paths: []
-#   - :name: subprojectA
-#     :source:
-#       - ./first/subproject/dir
-#       - ./second/subproject/dir
-#     :include:
-#       - ./first/include/dir
-#     :build_root: ./subproject/build/dir
-#     :defines:
-#       - FIRST_DEFINE
-
-:tools:
-  :subprojects_compiler:
-    :executable: gcc
-    :arguments:
-      - -g
-      - -I"$": COLLECTION_PATHS_SUBPROJECTS
-      - -D$: COLLECTION_DEFINES_SUBPROJECTS
-      - -c "${1}"
-      - -o "${2}"
-  :subprojects_linker:
-    :executable: ar
-    :arguments:
-      - rcs
-      - ${2}
-      - ${1}
-
-...
diff --git a/test/vendor/ceedling/plugins/subprojects/lib/subprojects.rb b/test/vendor/ceedling/plugins/subprojects/lib/subprojects.rb
deleted file mode 100644
index 1f5d4c2f7..000000000
--- a/test/vendor/ceedling/plugins/subprojects/lib/subprojects.rb
+++ /dev/null
@@ -1,92 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-
-SUBPROJECTS_ROOT_NAME         = 'subprojects'
-SUBPROJECTS_TASK_ROOT         = SUBPROJECTS_ROOT_NAME + ':'
-SUBPROJECTS_SYM               = SUBPROJECTS_ROOT_NAME.to_sym
-
-class Subprojects < Plugin
-
-  def setup
-    @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..'))
-
-    # Add to the test paths
-    SUBPROJECTS_PATHS.each do |subproj|
-      subproj[:source].each do |path|
-        COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR << path
-      end
-      subproj[:include].each do |path|
-        COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR << path
-      end
-    end
-
-    #gather information about the subprojects
-    @subprojects = {}
-    @subproject_lookup_by_path = {}
-    SUBPROJECTS_PATHS.each do |subproj|
-      @subprojects[ subproj[:name] ] = subproj.clone
-      @subprojects[ subproj[:name] ][:c] = []
-      @subprojects[ subproj[:name] ][:asm] = []
-      subproj[:source].each do |path|
-        search_path = "#{path[-1].match(/\\|\//) ? path : "#{path}/"}*#{EXTENSION_SOURCE}"
-        @subprojects[ subproj[:name] ][:c] += Dir[search_path]
-        if (EXTENSION_ASSEMBLY && !EXTENSION_ASSEMBLY.empty?)
-          search_path = "#{path[-1].match(/\\|\//) ? path : "#{path}/"}*#{EXTENSION_ASSEMBLY}"
-          @subprojects[ subproj[:name] ][:asm] += Dir[search_path]
-        end
-      end
-      @subproject_lookup_by_path[ subproj[:build_root] ] = subproj[:name]
-    end
-  end
-
-  def find_my_project( c_file, file_type = :c )
-    @subprojects.each_pair do |subprojname, subproj|
-      return subprojname if (subproj[file_type].include?(c_file))
-    end
-  end
-
-  def find_my_paths( c_file, file_type = :c )
-    @subprojects.each_pair do |subprojname, subproj|
-      return (subproj[:source] + (subproj[:include] || [])) if (subproj[file_type].include?(c_file))
-    end
-    return []
-  end
-
-  def find_my_defines( c_file, file_type = :c )
-    @subprojects.each_pair do |subprojname, subproj|
-      return (subproj[:defines] || []) if (subproj[file_type].include?(c_file))
-    end
-    return []
-  end
-
-  def list_all_object_files_for_subproject( lib_name )
-    subproj = File.basename(lib_name, EXTENSION_SUBPROJECTS)
-    objpath = "#{@subprojects[subproj][:build_root]}/out/c"
-    bbb = @subprojects[subproj][:c].map{|f| "#{objpath}/#{File.basename(f,EXTENSION_SOURCE)}#{EXTENSION_OBJECT}" }
-    bbb
-  end
-
-  def find_library_source_file_for_object( obj_name )
-    cname = "#{File.basename(obj_name, EXTENSION_OBJECT)}#{EXTENSION_SOURCE}"
-    dname = File.dirname(obj_name)[0..-7]
-    pname = @subproject_lookup_by_path[dname]
-    return @ceedling[:file_finder].find_file_from_list(cname, @subprojects[pname][:c], :error)
-  end
-
-  def find_library_assembly_file_for_object( obj_name )
-    cname = "#{File.basename(obj_name, EXTENSION_OBJECT)}#{EXTENSION_ASEMBLY}"
-    dname = File.dirname(obj_name)[0..-7]
-    pname = @subproject_lookup_by_path[dname]
-    return @ceedling[:file_finder].find_file_from_list(cname, @subprojects[pname][:asm], :error)
-  end
-
-  def replace_constant(constant, new_value)
-    Object.send(:remove_const, constant.to_sym) if (Object.const_defined? constant)
-    Object.const_set(constant, new_value)
-  end
- 
-end
-
-# end blocks always executed following rake run
-END {
-}
diff --git a/test/vendor/ceedling/plugins/subprojects/subprojects.rake b/test/vendor/ceedling/plugins/subprojects/subprojects.rake
deleted file mode 100644
index 0025c3ecd..000000000
--- a/test/vendor/ceedling/plugins/subprojects/subprojects.rake
+++ /dev/null
@@ -1,78 +0,0 @@
-
-
-SUBPROJECTS_PATHS.each do |subproj|
-
-  subproj_source     = subproj[:source]
-  subproj_include    = subproj[:include]
-  subproj_name       = subproj[:name]
-  subproj_build_root = subproj[:build_root]
-  subproj_build_out  = "#{subproj[:build_root]}/out"
-  subproj_build_c    = "#{subproj[:build_root]}/out/c"
-  subproj_build_asm  = "#{subproj[:build_root]}/out/asm"
-  subproj_directories = [ subproj_build_root, subproj_build_out, subproj_build_c, subproj_build_asm ]
-
-  subproj_directories.each do |subdir|
-    directory(subdir)
-  end
-
-  CLEAN.include(File.join(subproj_build_root, '*'))
-  CLEAN.include(File.join(subproj_build_out, '*'))
-
-  CLOBBER.include(File.join(subproj_build_root, '**/*'))
-
-  # Add a rule for building the actual static library from our object files
-  rule(/#{subproj_build_root}#{'.+\\'+EXTENSION_SUBPROJECTS}$/ => [
-      proc do |task_name|
-        @ceedling[SUBPROJECTS_SYM].list_all_object_files_for_subproject(task_name)
-      end
-    ]) do |bin_file|
-    @ceedling[:generator].generate_executable_file(
-      TOOLS_SUBPROJECTS_LINKER,
-      SUBPROJECTS_SYM,
-      bin_file.prerequisites,
-      bin_file.name,
-      @ceedling[:file_path_utils].form_test_build_map_filepath(bin_file.name))
-  end
-
-  # Add a rule for building object files from assembly files to link into a library
-  if (RELEASE_BUILD_USE_ASSEMBLY)
-    rule(/#{subproj_build_asm}#{'.+\\'+EXTENSION_OBJECT}$/ => [
-        proc do |task_name|
-          @ceedling[SUBPROJECTS_SYM].find_library_assembly_file_for_object(task_name)
-        end
-      ]) do |object|
-      @ceedling[SUBPROJECTS_SYM].replace_constant(:COLLECTION_PATHS_SUBPROJECTS, @ceedling[SUBPROJECTS_SYM].find_my_paths(object.source, :asm))
-      @ceedling[SUBPROJECTS_SYM].replace_constant(:COLLECTION_DEFINES_SUBPROJECTS, @ceedling[SUBPROJECTS_SYM].find_my_defines(object.source, :asm))
-      @ceedling[:generator].generate_object_file(
-        TOOLS_SUBPROJECTS_ASSEMBLER,
-        OPERATION_ASSEMBLE_SYM,
-        SUBPROJECTS_SYM,
-        object.source,
-        object.name )
-    end
-  end
-
-  # Add a rule for building object files from C files to link into a library
-  rule(/#{subproj_build_c}#{'.+\\'+EXTENSION_OBJECT}$/ => [
-      proc do |task_name|
-        @ceedling[SUBPROJECTS_SYM].find_library_source_file_for_object(task_name)
-      end
-    ]) do |object|
-    @ceedling[SUBPROJECTS_SYM].replace_constant(:COLLECTION_PATHS_SUBPROJECTS, @ceedling[SUBPROJECTS_SYM].find_my_paths(object.source, :c))
-    @ceedling[SUBPROJECTS_SYM].replace_constant(:COLLECTION_DEFINES_SUBPROJECTS, @ceedling[SUBPROJECTS_SYM].find_my_defines(object.source, :c))
-    @ceedling[:generator].generate_object_file(
-      TOOLS_SUBPROJECTS_COMPILER,
-      OPERATION_COMPILE_SYM,
-      SUBPROJECTS_SYM,
-      object.source,
-      object.name,
-      @ceedling[:file_path_utils].form_release_build_c_list_filepath( object.name ) )
-  end
-
-  # Add the subdirectories involved to our list of those that should be autogenerated
-  task :directories => subproj_directories.clone
-
-  # Finally, add the static library to our RELEASE build dependency list
-  task RELEASE_SYM => ["#{subproj_build_root}/#{subproj_name}#{EXTENSION_SUBPROJECTS}"] 
-end
-
diff --git a/test/vendor/ceedling/plugins/teamcity_tests_report/config/teamcity_tests_report.yml b/test/vendor/ceedling/plugins/teamcity_tests_report/config/teamcity_tests_report.yml
deleted file mode 100644
index c25acf511..000000000
--- a/test/vendor/ceedling/plugins/teamcity_tests_report/config/teamcity_tests_report.yml
+++ /dev/null
@@ -1,4 +0,0 @@
----
-:plugins:
-  # tell Ceedling we got results display taken care of
-  :display_raw_test_results: FALSE
diff --git a/test/vendor/ceedling/plugins/teamcity_tests_report/lib/teamcity_tests_report.rb b/test/vendor/ceedling/plugins/teamcity_tests_report/lib/teamcity_tests_report.rb
deleted file mode 100644
index 33d8548f3..000000000
--- a/test/vendor/ceedling/plugins/teamcity_tests_report/lib/teamcity_tests_report.rb
+++ /dev/null
@@ -1,57 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/defaults'
-
-class TeamcityTestsReport < Plugin
-
-  def setup
-    @suite_started = nil
-    @output_enabled = !defined?(TEAMCITY_BUILD) || TEAMCITY_BUILD
-  end
-
-  def escape(string)
-    string.gsub(/['|\[\]]/, '|\0').gsub('\r', '|r').gsub('\n', '|n')
-  end
-
-  def pre_test(test)
-    teamcity_message "testSuiteStarted name='#{File.basename(test, '.c')}'"
-    @suite_started = Time.now
-  end
-
-  def post_test(test)
-    teamcity_message "testSuiteFinished name='#{File.basename(test, '.c')}'"
-  end
-
-  def post_test_fixture_execute(arg_hash)
-    duration = (Time.now - @suite_started) * 1000
-    results = @ceedling[:plugin_reportinator].assemble_test_results([arg_hash[:result_file]])
-    avg_duration = (duration / [1, results[:counts][:passed] + results[:counts][:failed]].max).round
-
-    results[:successes].each do |success|
-      success[:collection].each do |test|
-        teamcity_message "testStarted name='#{test[:test]}'"
-        teamcity_message "testFinished name='#{test[:test]}' duration='#{avg_duration}'"
-      end
-    end
-
-    results[:failures].each do |failure|
-      failure[:collection].each do |test|
-        teamcity_message "testStarted name='#{test[:test]}'"
-        teamcity_message "testFailed name='#{test[:test]}' message='#{escape(test[:message])}' details='File: #{failure[:source][:path]}/#{failure[:source][:file]} Line: #{test[:line]}'"
-        teamcity_message "testFinished name='#{test[:test]}' duration='#{avg_duration}'"
-      end
-    end
-
-    results[:ignores].each do |failure|
-      failure[:collection].each do |test|
-        teamcity_message "testIgnored name='#{test[:test]}' message='#{escape(test[:message])}'"
-      end
-    end
-
-    # We ignore stdout
-  end
-
-  def teamcity_message(content)
-    puts "##teamcity[#{content}]" unless !@output_enabled
-  end
-
-end
diff --git a/test/vendor/ceedling/plugins/warnings_report/lib/warnings_report.rb b/test/vendor/ceedling/plugins/warnings_report/lib/warnings_report.rb
deleted file mode 100644
index d4f43fb57..000000000
--- a/test/vendor/ceedling/plugins/warnings_report/lib/warnings_report.rb
+++ /dev/null
@@ -1,69 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-
-class WarningsReport < Plugin
-  def setup
-    @stderr_redirect = nil
-    @log_paths = {}
-  end
-
-  def pre_compile_execute(arg_hash)
-    # at beginning of compile, override tool's stderr_redirect so we can parse $stderr + $stdout
-    set_stderr_redirect(arg_hash)
-  end
-
-  def post_compile_execute(arg_hash)
-    # after compilation, grab output for parsing/logging, restore stderr_redirect, log warning if it exists
-    output = arg_hash[:shell_result][:output]
-    restore_stderr_redirect(arg_hash)
-    write_warning_log(arg_hash[:context], output)
-  end
-
-  def pre_link_execute(arg_hash)
-    # at beginning of link, override tool's stderr_redirect so we can parse $stderr + $stdout
-    set_stderr_redirect(arg_hash)
-  end
-
-  def post_link_execute(arg_hash)
-    # after linking, grab output for parsing/logging, restore stderr_redirect, log warning if it exists
-    output = arg_hash[:shell_result][:output]
-    restore_stderr_redirect(arg_hash)
-    write_warning_log(arg_hash[:context], output)
-  end
-
-  private
-
-  def set_stderr_redirect(hash)
-    @stderr_redirect = hash[:tool][:stderr_redirect]
-    hash[:tool][:stderr_redirect] = StdErrRedirect::AUTO
-  end
-
-  def restore_stderr_redirect(hash)
-    hash[:tool][:stderr_redirect] = @stderr_redirect
-  end
-
-  def write_warning_log(context, output)
-    # if $stderr/$stdout contain "warning", log it
-    if output =~ /warning/i
-      # generate a log path & file io write flags
-      logging = generate_log_path(context)
-      @ceedling[:file_wrapper].write(logging[:path], output + "\n", logging[:flags]) unless logging.nil?
-    end
-  end
-
-  def generate_log_path(context)
-    # if path has already been generated, return it & 'append' file io flags (append to log)
-    return { path: @log_paths[context], flags: 'a' } unless @log_paths[context].nil?
-
-    # first time through, generate path & 'write' file io flags (create new log)
-    base_path = File.join(PROJECT_BUILD_ARTIFACTS_ROOT, context.to_s)
-    file_path = File.join(base_path, 'warnings.log')
-
-    if @ceedling[:file_wrapper].exist?(base_path)
-      @log_paths[context] = file_path
-      return { path: file_path, flags: 'w' }
-    end
-
-    nil
-  end
-end
diff --git a/test/vendor/ceedling/plugins/xml_tests_report/README.md b/test/vendor/ceedling/plugins/xml_tests_report/README.md
deleted file mode 100644
index ce81eadf3..000000000
--- a/test/vendor/ceedling/plugins/xml_tests_report/README.md
+++ /dev/null
@@ -1,36 +0,0 @@
-xml_tests_report
-====================
-
-## Overview
-
-The xml_tests_report plugin creates an XML file of test results in xUnit
-format, which is handy for Continuous Integration build servers or as input
-into other reporting tools. The XML file is output to the appropriate
-`<build_root>/artifacts/` directory (e.g. `artifacts/test/` for test tasks,
-`artifacts/gcov/` for gcov, or `artifacts/bullseye/` for bullseye runs).
-
-## Setup
-
-Enable the plugin in your project.yml by adding `xml_tests_report` to the list
-of enabled plugins.
-
-``` YAML
-:plugins:
-  :enabled:
-    - xml_tests_report
-```
-
-## Configuration
-
-Optionally configure the output / artifact filename in your project.yml with
-the `artifact_filename` configuration option. The default filename is
-`report.xml`.
-
-You can also configure the path that this artifact is stored. This can be done
-by setting `path`. The default is that it will be placed in a subfolder under
-the `build` directory.
-
-``` YAML
-:xml_tests_report:
-  :artifact_filename: report_xunit.xml
-```
diff --git a/test/vendor/ceedling/plugins/xml_tests_report/lib/xml_tests_report.rb b/test/vendor/ceedling/plugins/xml_tests_report/lib/xml_tests_report.rb
deleted file mode 100644
index ed4e99603..000000000
--- a/test/vendor/ceedling/plugins/xml_tests_report/lib/xml_tests_report.rb
+++ /dev/null
@@ -1,110 +0,0 @@
-require 'ceedling/plugin'
-require 'ceedling/constants'
-
-class XmlTestsReport < Plugin
-  def setup
-    @results_list = {}
-    @test_counter = 0
-  end
-
-  def post_test_fixture_execute(arg_hash)
-    context = arg_hash[:context]
-
-    @results_list[context] = [] if @results_list[context].nil?
-
-    @results_list[context] << arg_hash[:result_file]
-  end
-
-  def post_build
-    @results_list.each_key do |context|
-      results = @ceedling[:plugin_reportinator].assemble_test_results(@results_list[context])
-
-      artifact_filename = @ceedling[:configurator].project_config_hash[:xml_tests_report_artifact_filename] || 'report.xml'
-      artifact_fullpath = @ceedling[:configurator].project_config_hash[:xml_tests_report_path] || File.join(PROJECT_BUILD_ARTIFACTS_ROOT, context.to_s)
-      file_path = File.join(artifact_fullpath, artifact_filename)
-
-      @ceedling[:file_wrapper].open(file_path, 'w') do |f|
-        @test_counter = 1
-        write_results(results, f)
-      end
-    end
-  end
-
-  private
-
-  def write_results(results, stream)
-    write_header(stream)
-    write_failures(results[:failures], stream)
-    write_tests(results[:successes], stream, 'SuccessfulTests')
-    write_tests(results[:ignores], stream, 'IgnoredTests')
-    write_statistics(results[:counts], stream)
-    write_footer(stream)
-  end
-
-  def write_header(stream)
-    stream.puts "<?xml version='1.0' encoding='utf-8' ?>"
-    stream.puts '<TestRun>'
-  end
-
-  def write_failures(results, stream)
-    if results.size.zero?
-      stream.puts "\t<FailedTests/>"
-      return
-    end
-
-    stream.puts "\t<FailedTests>"
-
-    results.each do |result|
-      result[:collection].each do |item|
-        filename = File.join(result[:source][:path], result[:source][:file])
-
-        stream.puts "\t\t<Test id=\"#{@test_counter}\">"
-        stream.puts "\t\t\t<Name>#{filename}::#{item[:test]}</Name>"
-        stream.puts "\t\t\t<FailureType>Assertion</FailureType>"
-        stream.puts "\t\t\t<Location>"
-        stream.puts "\t\t\t\t<File>#{filename}</File>"
-        stream.puts "\t\t\t\t<Line>#{item[:line]}</Line>"
-        stream.puts "\t\t\t</Location>"
-        stream.puts "\t\t\t<Message>#{item[:message]}</Message>"
-        stream.puts "\t\t</Test>"
-        @test_counter += 1
-      end
-    end
-
-    stream.puts "\t</FailedTests>"
-  end
-
-  def write_tests(results, stream, tag)
-    if results.size.zero?
-      stream.puts "\t<#{tag}/>"
-      return
-    end
-
-    stream.puts "\t<#{tag}>"
-
-    results.each do |result|
-      result[:collection].each do |item|
-        stream.puts "\t\t<Test id=\"#{@test_counter}\">"
-        stream.puts "\t\t\t<Name>#{File.join(result[:source][:path], result[:source][:file])}::#{item[:test]}</Name>"
-        stream.puts "\t\t</Test>"
-        @test_counter += 1
-      end
-    end
-
-    stream.puts "\t</#{tag}>"
-  end
-
-  def write_statistics(counts, stream)
-    stream.puts "\t<Statistics>"
-    stream.puts "\t\t<Tests>#{counts[:total]}</Tests>"
-    stream.puts "\t\t<Ignores>#{counts[:ignored]}</Ignores>"
-    stream.puts "\t\t<FailuresTotal>#{counts[:failed]}</FailuresTotal>"
-    stream.puts "\t\t<Errors>0</Errors>"
-    stream.puts "\t\t<Failures>#{counts[:failed]}</Failures>"
-    stream.puts "\t</Statistics>"
-  end
-
-  def write_footer(stream)
-    stream.puts '</TestRun>'
-  end
-end
diff --git a/test/vendor/ceedling/vendor/c_exception/lib/CException.c b/test/vendor/ceedling/vendor/c_exception/lib/CException.c
deleted file mode 100644
index fdff8f475..000000000
--- a/test/vendor/ceedling/vendor/c_exception/lib/CException.c
+++ /dev/null
@@ -1,46 +0,0 @@
-#include "CException.h"
-
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
-volatile CEXCEPTION_FRAME_T CExceptionFrames[CEXCEPTION_NUM_ID] = {{ 0 }};
-#pragma GCC diagnostic pop
-
-//------------------------------------------------------------------------------------------
-//  Throw
-//------------------------------------------------------------------------------------------
-void Throw(CEXCEPTION_T ExceptionID)
-{
-    unsigned int MY_ID = CEXCEPTION_GET_ID;
-    CExceptionFrames[MY_ID].Exception = ExceptionID;
-    if (CExceptionFrames[MY_ID].pFrame)
-    {
-        longjmp(*CExceptionFrames[MY_ID].pFrame, 1);
-    }
-    CEXCEPTION_NO_CATCH_HANDLER(ExceptionID);
-}
-
-//------------------------------------------------------------------------------------------
-//  Explanation of what it's all for:
-//------------------------------------------------------------------------------------------
-/*
-#define Try
-    {                                                                   <- give us some local scope.  most compilers are happy with this
-        jmp_buf *PrevFrame, NewFrame;                                   <- prev frame points to the last try block's frame.  new frame gets created on stack for this Try block
-        unsigned int MY_ID = CEXCEPTION_GET_ID;                         <- look up this task's id for use in frame array.  always 0 if single-tasking
-        PrevFrame = CExceptionFrames[CEXCEPTION_GET_ID].pFrame;         <- set pointer to point at old frame (which array is currently pointing at)
-        CExceptionFrames[MY_ID].pFrame = &NewFrame;                     <- set array to point at my new frame instead, now
-        CExceptionFrames[MY_ID].Exception = CEXCEPTION_NONE;            <- initialize my exception id to be NONE
-        if (setjmp(NewFrame) == 0) {                                    <- do setjmp.  it returns 1 if longjump called, otherwise 0
-            if (&PrevFrame)                                             <- this is here to force proper scoping.  it requires braces or a single line to be but after Try, otherwise won't compile.  This is always true at this point.
-
-#define Catch(e)
-            else { }                                                    <- this also forces proper scoping.  Without this they could stick their own 'else' in and it would get ugly
-            CExceptionFrames[MY_ID].Exception = CEXCEPTION_NONE;        <- no errors happened, so just set the exception id to NONE (in case it was corrupted)
-        }
-        else                                                            <- an exception occurred
-        { e = CExceptionFrames[MY_ID].Exception; e=e;}                  <- assign the caught exception id to the variable passed in.
-        CExceptionFrames[MY_ID].pFrame = PrevFrame;                     <- make the pointer in the array point at the previous frame again, as if NewFrame never existed.
-    }                                                                   <- finish off that local scope we created to have our own variables
-    if (CExceptionFrames[CEXCEPTION_GET_ID].Exception != CEXCEPTION_NONE)  <- start the actual 'catch' processing if we have an exception id saved away
- */
-
diff --git a/test/vendor/ceedling/vendor/c_exception/lib/CException.h b/test/vendor/ceedling/vendor/c_exception/lib/CException.h
deleted file mode 100644
index 78f2f940c..000000000
--- a/test/vendor/ceedling/vendor/c_exception/lib/CException.h
+++ /dev/null
@@ -1,115 +0,0 @@
-#ifndef _CEXCEPTION_H
-#define _CEXCEPTION_H
-
-#include <setjmp.h>
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-#define CEXCEPTION_VERSION_MAJOR    1
-#define CEXCEPTION_VERSION_MINOR    3
-#define CEXCEPTION_VERSION_BUILD    2
-#define CEXCEPTION_VERSION          ((CEXCEPTION_VERSION_MAJOR << 16) | (CEXCEPTION_VERSION_MINOR << 8) | CEXCEPTION_VERSION_BUILD)
-
-//To Use CException, you have a number of options:
-//1. Just include it and run with the defaults
-//2. Define any of the following symbols at the command line to override them
-//3. Include a header file before CException.h everywhere which defines any of these
-//4. Create an Exception.h in your path, and just define EXCEPTION_USE_CONFIG_FILE first
-
-#ifdef CEXCEPTION_USE_CONFIG_FILE
-#include "CExceptionConfig.h"
-#endif
-
-//This is the value to assign when there isn't an exception
-#ifndef CEXCEPTION_NONE
-#define CEXCEPTION_NONE      (0x5A5A5A5A)
-#endif
-
-//This is number of exception stacks to keep track of (one per task)
-#ifndef CEXCEPTION_NUM_ID
-#define CEXCEPTION_NUM_ID    (1) //there is only the one stack by default
-#endif
-
-//This is the method of getting the current exception stack index (0 if only one stack)
-#ifndef CEXCEPTION_GET_ID
-#define CEXCEPTION_GET_ID    (0) //use the first index always because there is only one anyway
-#endif
-
-//The type to use to store the exception values.
-#ifndef CEXCEPTION_T
-#define CEXCEPTION_T         unsigned int
-#endif
-
-//This is an optional special handler for when there is no global Catch
-#ifndef CEXCEPTION_NO_CATCH_HANDLER
-#define CEXCEPTION_NO_CATCH_HANDLER(id)
-#endif
-
-//These hooks allow you to inject custom code into places, particularly useful for saving and restoring additional state
-#ifndef CEXCEPTION_HOOK_START_TRY
-#define CEXCEPTION_HOOK_START_TRY
-#endif
-#ifndef CEXCEPTION_HOOK_HAPPY_TRY
-#define CEXCEPTION_HOOK_HAPPY_TRY
-#endif
-#ifndef CEXCEPTION_HOOK_AFTER_TRY
-#define CEXCEPTION_HOOK_AFTER_TRY
-#endif
-#ifndef CEXCEPTION_HOOK_START_CATCH
-#define CEXCEPTION_HOOK_START_CATCH
-#endif
-
-//exception frame structures
-typedef struct {
-  jmp_buf* pFrame;
-  CEXCEPTION_T volatile Exception;
-} CEXCEPTION_FRAME_T;
-
-//actual root frame storage (only one if single-tasking)
-extern volatile CEXCEPTION_FRAME_T CExceptionFrames[];
-
-//Try (see C file for explanation)
-#define Try                                                         \
-    {                                                               \
-        jmp_buf *PrevFrame, NewFrame;                               \
-        unsigned int MY_ID = CEXCEPTION_GET_ID;                     \
-        PrevFrame = CExceptionFrames[MY_ID].pFrame;                 \
-        CExceptionFrames[MY_ID].pFrame = (jmp_buf*)(&NewFrame);     \
-        CExceptionFrames[MY_ID].Exception = CEXCEPTION_NONE;        \
-        CEXCEPTION_HOOK_START_TRY;                                  \
-        if (setjmp(NewFrame) == 0) {                                \
-            if (1)
-
-//Catch (see C file for explanation)
-#define Catch(e)                                                    \
-            else { }                                                \
-            CExceptionFrames[MY_ID].Exception = CEXCEPTION_NONE;    \
-            CEXCEPTION_HOOK_HAPPY_TRY;                              \
-        }                                                           \
-        else                                                        \
-        {                                                           \
-            e = CExceptionFrames[MY_ID].Exception;                  \
-            (void)e;                                                \
-            CEXCEPTION_HOOK_START_CATCH;                            \
-        }                                                           \
-        CExceptionFrames[MY_ID].pFrame = PrevFrame;                 \
-        CEXCEPTION_HOOK_AFTER_TRY;                                  \
-    }                                                               \
-    if (CExceptionFrames[CEXCEPTION_GET_ID].Exception != CEXCEPTION_NONE)
-
-//Throw an Error
-void Throw(CEXCEPTION_T ExceptionID);
-
-//Just exit the Try block and skip the Catch.
-#define ExitTry() Throw(CEXCEPTION_NONE)
-
-#ifdef __cplusplus
-}   // extern "C"
-#endif
-
-
-#endif // _CEXCEPTION_H
diff --git a/test/vendor/ceedling/vendor/c_exception/release/build.info b/test/vendor/ceedling/vendor/c_exception/release/build.info
deleted file mode 100644
index 0cd525d8c..000000000
--- a/test/vendor/ceedling/vendor/c_exception/release/build.info
+++ /dev/null
@@ -1,2 +0,0 @@
-18
-
diff --git a/test/vendor/ceedling/vendor/c_exception/release/version.info b/test/vendor/ceedling/vendor/c_exception/release/version.info
deleted file mode 100644
index 1527a8de2..000000000
--- a/test/vendor/ceedling/vendor/c_exception/release/version.info
+++ /dev/null
@@ -1,2 +0,0 @@
-1.3.1
-
diff --git a/test/vendor/ceedling/vendor/cmock/config/production_environment.rb b/test/vendor/ceedling/vendor/cmock/config/production_environment.rb
deleted file mode 100644
index 915582b79..000000000
--- a/test/vendor/ceedling/vendor/cmock/config/production_environment.rb
+++ /dev/null
@@ -1,14 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ========================================== 
- 
-# Setup our load path:
-[ 
- 'lib',
-].each do |dir|
-  $LOAD_PATH.unshift( File.join( File.expand_path(File.dirname(__FILE__)) + '/../', dir) )
-end
-
-
diff --git a/test/vendor/ceedling/vendor/cmock/config/test_environment.rb b/test/vendor/ceedling/vendor/cmock/config/test_environment.rb
deleted file mode 100644
index fe1ed817a..000000000
--- a/test/vendor/ceedling/vendor/cmock/config/test_environment.rb
+++ /dev/null
@@ -1,16 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-# Setup our load path:
-[
-  './lib',
-  './vendor/behaviors/lib',
-  './vendor/hardmock/lib',
-  './vendor/unity/auto/',
-  './test/system/'
-].each do |dir|
-  $LOAD_PATH.unshift( File.join( File.expand_path(File.dirname(__FILE__) + "/../"), dir) )
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock.rb
deleted file mode 100644
index 8243ce58a..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock.rb
+++ /dev/null
@@ -1,86 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-[ "../config/production_environment",
-  "cmock_header_parser",
-  "cmock_generator",
-  "cmock_file_writer",
-  "cmock_config",
-  "cmock_plugin_manager",
-  "cmock_generator_utils",
-  "cmock_unityhelper_parser"].each {|req| require "#{File.expand_path(File.dirname(__FILE__))}/#{req}"}
-
-class CMock
-
-  def initialize(options=nil)
-    cm_config      = CMockConfig.new(options)
-    cm_unityhelper = CMockUnityHelperParser.new(cm_config)
-    cm_writer      = CMockFileWriter.new(cm_config)
-    cm_gen_utils   = CMockGeneratorUtils.new(cm_config, {:unity_helper => cm_unityhelper})
-    cm_gen_plugins = CMockPluginManager.new(cm_config, cm_gen_utils)
-    @cm_parser     = CMockHeaderParser.new(cm_config)
-    @cm_generator  = CMockGenerator.new(cm_config, cm_writer, cm_gen_utils, cm_gen_plugins)
-    @silent        = (cm_config.verbosity < 2)
-  end
-
-  def setup_mocks(files)
-    [files].flatten.each do |src|
-      generate_mock src
-    end
-  end
-
-  private ###############################
-
-  def generate_mock(src)
-    name = File.basename(src, '.h')
-    puts "Creating mock for #{name}..." unless @silent
-    @cm_generator.create_mock(name, @cm_parser.parse(name, File.read(src)))
-  end
-end
-
-def option_maker(options, key, val)
-  options = options || {}
-  options[key.to_sym] =
-    if val.chr == ":"
-      val[1..-1].to_sym
-    elsif val.include? ";"
-      val.split(';')
-    elsif val == 'true'
-      true
-    elsif val == 'false'
-      false
-    elsif val =~ /^\d+$/
-      val.to_i
-    else
-      val
-    end
-  options
-end
-
-  # Command Line Support ###############################
-
-if ($0 == __FILE__)
-  usage = "usage: ruby #{__FILE__} (-oOptionsFile) File(s)ToMock"
-
-  if (!ARGV[0])
-    puts usage
-    exit 1
-  end
-
-  options = {}
-  filelist = []
-  ARGV.each do |arg|
-    if (arg =~ /^-o\"?([a-zA-Z0-9._\\\/:\s]+)\"?/)
-      options.merge! CMockConfig.load_config_file_from_yaml( arg.gsub(/^-o/,'') )
-    elsif (arg =~ /^--([a-zA-Z0-9._\\\/:\s]+)=\"?([a-zA-Z0-9._\-\\\/:\s\;]+)\"?/)
-      options = option_maker(options, $1, $2)
-    else
-      filelist << arg
-    end
-  end
-
-  CMock.new(options).setup_mocks(filelist)
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_config.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_config.rb
deleted file mode 100644
index b21b61ed2..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_config.rb
+++ /dev/null
@@ -1,153 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockConfig
-
-  CMockDefaultOptions =
-  {
-    :framework                   => :unity,
-    :mock_path                   => 'mocks',
-    :mock_prefix                 => 'Mock',
-    :mock_suffix                 => '',
-    :weak                        => '',
-    :subdir                      => nil,
-    :plugins                     => [],
-    :strippables                 => ['(?:__attribute__\s*\(+.*?\)+)'],
-    :attributes                  => ['__ramfunc', '__irq', '__fiq', 'register', 'extern'],
-    :c_calling_conventions       => ['__stdcall', '__cdecl', '__fastcall'],
-    :enforce_strict_ordering     => false,
-    :fail_on_unexpected_calls    => true,
-    :unity_helper_path           => false,
-    :treat_as                    => {},
-    :treat_as_array              => {},
-    :treat_as_void               => [],
-    :memcmp_if_unknown           => true,
-    :when_no_prototypes          => :warn,           #the options being :ignore, :warn, or :error
-    :when_ptr                    => :compare_data,   #the options being :compare_ptr, :compare_data, or :smart
-    :verbosity                   => 2,               #the options being 0 errors only, 1 warnings and errors, 2 normal info, 3 verbose
-    :treat_externs               => :exclude,        #the options being :include or :exclude
-    :callback_include_count      => true,
-    :callback_after_arg_check    => false,
-    :includes                    => nil,
-    :includes_h_pre_orig_header  => nil,
-    :includes_h_post_orig_header => nil,
-    :includes_c_pre_header       => nil,
-    :includes_c_post_header      => nil,
-    :orig_header_include_fmt     => "#include \"%s\"",
-    :array_size_type             => [],
-    :array_size_name             => 'size|len',
-  }
-
-  def initialize(options=nil)
-    case(options)
-      when NilClass then options = CMockDefaultOptions.clone
-      when String   then options = CMockDefaultOptions.clone.merge(load_config_file_from_yaml(options))
-      when Hash     then options = CMockDefaultOptions.clone.merge(options)
-      else          raise "If you specify arguments, it should be a filename or a hash of options"
-    end
-
-    #do some quick type verification
-    [:plugins, :attributes, :treat_as_void].each do |opt|
-      unless (options[opt].class == Array)
-        options[opt] = []
-        puts "WARNING: :#{opt.to_s} should be an array." unless (options[:verbosity] < 1)
-      end
-    end
-    [:includes, :includes_h_pre_orig_header, :includes_h_post_orig_header, :includes_c_pre_header, :includes_c_post_header].each do |opt|
-      unless (options[opt].nil? or (options[opt].class == Array))
-        options[opt] = []
-        puts "WARNING: :#{opt.to_s} should be an array." unless (options[:verbosity] < 1)
-      end
-    end
-    options[:unity_helper_path] ||= options[:unity_helper]
-    options[:unity_helper_path] = [options[:unity_helper_path]] if options[:unity_helper_path].is_a? String
-    options[:includes_c_post_header] = ((options[:includes_c_post_header] || []) + (options[:unity_helper_path] || [])).uniq
-    options[:plugins].compact!
-    options[:plugins].map! {|p| p.to_sym}
-    @options = options
-
-    treat_as_map = standard_treat_as_map()#.clone
-    treat_as_map.merge!(@options[:treat_as])
-    @options[:treat_as] = treat_as_map
-
-    @options.each_key do |key|
-      unless methods.include?(key)
-        eval("def #{key.to_s}() return @options[:#{key.to_s}] end")
-      end
-    end
-  end
-
-  def load_config_file_from_yaml yaml_filename
-    self.class.load_config_file_from_yaml yaml_filename
-  end
-
-  def self.load_config_file_from_yaml yaml_filename
-    require 'yaml'
-    require 'fileutils'
-    YAML.load_file(yaml_filename)[:cmock]
-  end
-
-  def set_path(path)
-    @src_path = path
-  end
-
-  def load_unity_helper
-    return nil unless (@options[:unity_helper_path])
-
-    return @options[:unity_helper_path].inject("") do |unity_helper, filename|
-      unity_helper + "\n" + File.new(filename).read
-    end
-  end
-
-  def standard_treat_as_map
-    {
-      'int'             => 'INT',
-      'char'            => 'INT8',
-      'short'           => 'INT16',
-      'long'            => 'INT',
-      'int8'            => 'INT8',
-      'int16'           => 'INT16',
-      'int32'           => 'INT',
-      'int8_t'          => 'INT8',
-      'int16_t'         => 'INT16',
-      'int32_t'         => 'INT',
-      'INT8_T'          => 'INT8',
-      'INT16_T'         => 'INT16',
-      'INT32_T'         => 'INT',
-      'bool'            => 'INT',
-      'bool_t'          => 'INT',
-      'BOOL'            => 'INT',
-      'BOOL_T'          => 'INT',
-      'unsigned int'    => 'HEX32',
-      'unsigned long'   => 'HEX32',
-      'uint32'          => 'HEX32',
-      'uint32_t'        => 'HEX32',
-      'UINT32'          => 'HEX32',
-      'UINT32_T'        => 'HEX32',
-      'void*'           => 'HEX8_ARRAY',
-      'void const*'     => 'HEX8_ARRAY',
-      'const void*'     => 'HEX8_ARRAY',
-      'unsigned short'  => 'HEX16',
-      'uint16'          => 'HEX16',
-      'uint16_t'        => 'HEX16',
-      'UINT16'          => 'HEX16',
-      'UINT16_T'        => 'HEX16',
-      'unsigned char'   => 'HEX8',
-      'uint8'           => 'HEX8',
-      'uint8_t'         => 'HEX8',
-      'UINT8'           => 'HEX8',
-      'UINT8_T'         => 'HEX8',
-      'char*'           => 'STRING',
-      'char const*'     => 'STRING',
-      'const char*'     => 'STRING',
-      'pCHAR'           => 'STRING',
-      'cstring'         => 'STRING',
-      'CSTRING'         => 'STRING',
-      'float'           => 'FLOAT',
-      'double'          => 'FLOAT'
-    }
-  end
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb
deleted file mode 100644
index d2d954cbc..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb
+++ /dev/null
@@ -1,44 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockFileWriter
-
-  attr_reader :config
-
-  def initialize(config)
-    @config = config
-  end
-
-  def create_subdir(subdir)
-    if !Dir.exists?("#{@config.mock_path}/")
-      require 'fileutils'
-      FileUtils.mkdir_p "#{@config.mock_path}/"
-    end
-    if subdir && !Dir.exists?("#{@config.mock_path}/#{subdir+'/' if subdir}")
-      require 'fileutils'
-      FileUtils.mkdir_p "#{@config.mock_path}/#{subdir+'/' if subdir}"
-    end
-  end
-
-  def create_file(filename, subdir)
-    raise "Where's the block of data to create?" unless block_given?
-    full_file_name_temp = "#{@config.mock_path}/#{subdir+'/' if subdir}#{filename}.new"
-    full_file_name_done = "#{@config.mock_path}/#{subdir+'/' if subdir}#{filename}"
-    File.open(full_file_name_temp, 'w') do |file|
-      yield(file, filename)
-    end
-    update_file(full_file_name_done, full_file_name_temp)
-  end
-
-  private ###################################
-
-  def update_file(dest, src)
-    require 'fileutils'
-    FileUtils.rm(dest) if (File.exist?(dest))
-    FileUtils.cp(src, dest)
-    FileUtils.rm(src)
-  end
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator.rb
deleted file mode 100644
index 42725a60d..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator.rb
+++ /dev/null
@@ -1,268 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockGenerator
-
-  attr_accessor :config, :file_writer, :module_name, :clean_mock_name, :mock_name, :utils, :plugins, :weak, :ordered
-
-  def initialize(config, file_writer, utils, plugins)
-    @file_writer = file_writer
-    @utils       = utils
-    @plugins     = plugins
-    @config      = config
-    @prefix      = @config.mock_prefix
-    @suffix      = @config.mock_suffix
-    @weak        = @config.weak
-    @ordered     = @config.enforce_strict_ordering
-    @framework   = @config.framework.to_s
-    @fail_on_unexpected_calls = @config.fail_on_unexpected_calls
-
-    @subdir      = @config.subdir
-
-    @includes_h_pre_orig_header  = (@config.includes || @config.includes_h_pre_orig_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-    @includes_h_post_orig_header = (@config.includes_h_post_orig_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-    @includes_c_pre_header       = (@config.includes_c_pre_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-    @includes_c_post_header      = (@config.includes_c_post_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-
-    here = File.dirname __FILE__
-    unity_path_in_ceedling = "#{here}/../../unity" # path to Unity from within Ceedling
-    unity_path_in_cmock = "#{here}/../vendor/unity" # path to Unity from within CMock
-    # path to Unity as specified by env var
-    unity_path_in_env = ENV.has_key?("UNITY_DIR") ? File.expand_path(ENV.fetch("UNITY_DIR")) : nil
-
-    if unity_path_in_env and File.exist? unity_path_in_env
-      require "#{unity_path_in_env}/auto/type_sanitizer"
-    elsif File.exist? unity_path_in_ceedling
-      require "#{unity_path_in_ceedling}/auto/type_sanitizer"
-    elsif File.exist? unity_path_in_cmock
-      require "#{unity_path_in_cmock}/auto/type_sanitizer"
-    else
-      raise "Failed to find an instance of Unity to pull in type_sanitizer module!"
-    end
-
-  end
-
-  def create_mock(module_name, parsed_stuff)
-    @module_name = module_name
-    @mock_name   = @prefix + @module_name + @suffix
-    @clean_mock_name = TypeSanitizer.sanitize_c_identifier(@mock_name)
-    create_mock_subdir()
-    create_mock_header_file(parsed_stuff)
-    create_mock_source_file(parsed_stuff)
-  end
-
-  private if $ThisIsOnlyATest.nil? ##############################
-
-  def create_mock_subdir()
-    @file_writer.create_subdir(@subdir)
-  end
-
-  def create_mock_header_file(parsed_stuff)
-    @file_writer.create_file(@mock_name + ".h", @subdir) do |file, filename|
-      create_mock_header_header(file, filename)
-      create_mock_header_service_call_declarations(file)
-      create_typedefs(file, parsed_stuff[:typedefs])
-      parsed_stuff[:functions].each do |function|
-        file << @plugins.run(:mock_function_declarations, function)
-      end
-      create_mock_header_footer(file)
-    end
-  end
-
-  def create_mock_source_file(parsed_stuff)
-    @file_writer.create_file(@mock_name + ".c", @subdir) do |file, filename|
-      create_source_header_section(file, filename, parsed_stuff[:functions])
-      create_instance_structure(file, parsed_stuff[:functions])
-      create_extern_declarations(file)
-      create_mock_verify_function(file, parsed_stuff[:functions])
-      create_mock_init_function(file)
-      create_mock_destroy_function(file, parsed_stuff[:functions])
-      parsed_stuff[:functions].each do |function|
-        create_mock_implementation(file, function)
-        create_mock_interfaces(file, function)
-      end
-    end
-  end
-
-  def create_mock_header_header(file, filename)
-    define_name   = @clean_mock_name.upcase
-    orig_filename = (@subdir ? @subdir + "/" : "") + @module_name + ".h"
-    file << "/* AUTOGENERATED FILE. DO NOT EDIT. */\n"
-    file << "#ifndef _#{define_name}_H\n"
-    file << "#define _#{define_name}_H\n\n"
-    file << "#include \"#{@framework}.h\"\n"
-    @includes_h_pre_orig_header.each {|inc| file << "#include #{inc}\n"}
-    file << @config.orig_header_include_fmt.gsub(/%s/, "#{orig_filename}") + "\n"
-    @includes_h_post_orig_header.each {|inc| file << "#include #{inc}\n"}
-    plugin_includes = @plugins.run(:include_files)
-    file << plugin_includes if (!plugin_includes.empty?)
-    file << "\n"
-    file << "/* Ignore the following warnings, since we are copying code */\n"
-    file << "#if defined(__GNUC__) && !defined(__ICC) && !defined(__TMS470__)\n"
-    file << "#if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ > 6 || (__GNUC_MINOR__ == 6 && __GNUC_PATCHLEVEL__ > 0)))\n"
-    file << "#pragma GCC diagnostic push\n"
-    file << "#endif\n"
-    file << "#if !defined(__clang__)\n"
-    file << "#pragma GCC diagnostic ignored \"-Wpragmas\"\n"
-    file << "#endif\n"
-    file << "#pragma GCC diagnostic ignored \"-Wunknown-pragmas\"\n"
-    file << "#pragma GCC diagnostic ignored \"-Wduplicate-decl-specifier\"\n"
-    file << "#endif\n"
-    file << "\n"
-  end
-
-  def create_typedefs(file, typedefs)
-    file << "\n"
-    typedefs.each {|typedef| file << "#{typedef}\n" }
-    file << "\n\n"
-  end
-
-  def create_mock_header_service_call_declarations(file)
-    file << "void #{@clean_mock_name}_Init(void);\n"
-    file << "void #{@clean_mock_name}_Destroy(void);\n"
-    file << "void #{@clean_mock_name}_Verify(void);\n\n"
-  end
-
-  def create_mock_header_footer(header)
-    header << "\n"
-    header << "#if defined(__GNUC__) && !defined(__ICC) && !defined(__TMS470__)\n"
-    header << "#if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ > 6 || (__GNUC_MINOR__ == 6 && __GNUC_PATCHLEVEL__ > 0)))\n"
-    header << "#pragma GCC diagnostic pop\n"
-    header << "#endif\n"
-    header << "#endif\n"
-    header << "\n"
-    header << "#endif\n"
-  end
-
-  def create_source_header_section(file, filename, functions)
-    header_file = (@subdir ? @subdir + '/' : '') + filename.gsub(".c",".h")
-    file << "/* AUTOGENERATED FILE. DO NOT EDIT. */\n"
-    file << "#include <string.h>\n"
-    file << "#include <stdlib.h>\n"
-    file << "#include <setjmp.h>\n"
-    file << "#include \"cmock.h\"\n"
-    @includes_c_pre_header.each {|inc| file << "#include #{inc}\n"}
-    file << "#include \"#{header_file}\"\n"
-    @includes_c_post_header.each {|inc| file << "#include #{inc}\n"}
-    file << "\n"
-    strs = []
-    functions.each do |func|
-      strs << func[:name]
-      func[:args].each {|arg| strs << arg[:name] }
-    end
-    strs.uniq.sort.each do |str|
-      file << "static const char* CMockString_#{str} = \"#{str}\";\n"
-    end
-    file << "\n"
-  end
-
-  def create_instance_structure(file, functions)
-    functions.each do |function|
-      file << "typedef struct _CMOCK_#{function[:name]}_CALL_INSTANCE\n{\n"
-      file << "  UNITY_LINE_TYPE LineNumber;\n"
-      file << @plugins.run(:instance_typedefs, function)
-      file << "\n} CMOCK_#{function[:name]}_CALL_INSTANCE;\n\n"
-    end
-    file << "static struct #{@clean_mock_name}Instance\n{\n"
-    if (functions.size == 0)
-      file << "  unsigned char placeHolder;\n"
-    end
-    functions.each do |function|
-      file << @plugins.run(:instance_structure, function)
-      file << "  CMOCK_MEM_INDEX_TYPE #{function[:name]}_CallInstance;\n"
-    end
-    file << "} Mock;\n\n"
-  end
-
-  def create_extern_declarations(file)
-    file << "extern jmp_buf AbortFrame;\n"
-    if (@ordered)
-      file << "extern int GlobalExpectCount;\n"
-      file << "extern int GlobalVerifyOrder;\n"
-    end
-    file << "\n"
-  end
-
-  def create_mock_verify_function(file, functions)
-    file << "void #{@clean_mock_name}_Verify(void)\n{\n"
-    verifications = functions.collect do |function|
-      v = @plugins.run(:mock_verify, function)
-      v.empty? ? v : ["  call_instance = Mock.#{function[:name]}_CallInstance;\n", v]
-    end.join
-    unless verifications.empty?
-      file << "  UNITY_LINE_TYPE cmock_line = TEST_LINE_NUM;\n"
-      file << "  CMOCK_MEM_INDEX_TYPE call_instance;\n"
-      file << verifications
-    end
-    file << "}\n\n"
-  end
-
-  def create_mock_init_function(file)
-    file << "void #{@clean_mock_name}_Init(void)\n{\n"
-    file << "  #{@clean_mock_name}_Destroy();\n"
-    file << "}\n\n"
-  end
-
-  def create_mock_destroy_function(file, functions)
-    file << "void #{@clean_mock_name}_Destroy(void)\n{\n"
-    file << "  CMock_Guts_MemFreeAll();\n"
-    file << "  memset(&Mock, 0, sizeof(Mock));\n"
-    file << functions.collect {|function| @plugins.run(:mock_destroy, function)}.join
-
-    unless (@fail_on_unexpected_calls)
-      file << functions.collect {|function| @plugins.run(:mock_ignore, function)}.join
-    end
-
-    if (@ordered)
-      file << "  GlobalExpectCount = 0;\n"
-      file << "  GlobalVerifyOrder = 0;\n"
-    end
-    file << "}\n\n"
-  end
-
-  def create_mock_implementation(file, function)
-    # prepare return value and arguments
-    function_mod_and_rettype = (function[:modifier].empty? ? '' : "#{function[:modifier]} ") +
-                               (function[:return][:type]) +
-                               (function[:c_calling_convention] ? " #{function[:c_calling_convention]}" : '')
-    args_string = function[:args_string]
-    args_string += (", " + function[:var_arg]) unless (function[:var_arg].nil?)
-
-    # Create mock function
-    if (not @weak.empty?)
-        file << "#if defined (__IAR_SYSTEMS_ICC__)\n"
-        file << "#pragma weak #{function[:name]}\n"
-        file << "#else\n"
-        file << "#{function_mod_and_rettype} #{function[:name]}(#{args_string}) #{weak};\n"
-        file << "#endif\n\n"
-    end
-    file << "#{function_mod_and_rettype} #{function[:name]}(#{args_string})\n"
-    file << "{\n"
-    file << "  UNITY_LINE_TYPE cmock_line = TEST_LINE_NUM;\n"
-    file << "  CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance;\n"
-    file << "  UNITY_SET_DETAIL(CMockString_#{function[:name]});\n"
-    file << "  cmock_call_instance = (CMOCK_#{function[:name]}_CALL_INSTANCE*)CMock_Guts_GetAddressFor(Mock.#{function[:name]}_CallInstance);\n"
-    file << "  Mock.#{function[:name]}_CallInstance = CMock_Guts_MemNext(Mock.#{function[:name]}_CallInstance);\n"
-    file << @plugins.run(:mock_implementation_precheck, function)
-    file << "  UNITY_TEST_ASSERT_NOT_NULL(cmock_call_instance, cmock_line, CMockStringCalledMore);\n"
-    file << "  cmock_line = cmock_call_instance->LineNumber;\n"
-    if (@ordered)
-      file << "  if (cmock_call_instance->CallOrder > ++GlobalVerifyOrder)\n"
-      file << "    UNITY_TEST_FAIL(cmock_line, CMockStringCalledEarly);\n"
-      file << "  if (cmock_call_instance->CallOrder < GlobalVerifyOrder)\n"
-      file << "    UNITY_TEST_FAIL(cmock_line, CMockStringCalledLate);\n"
-    end
-    file << @plugins.run(:mock_implementation, function)
-    file << "  UNITY_CLR_DETAILS();\n"
-    file << "  return cmock_call_instance->ReturnVal;\n" unless (function[:return][:void?])
-    file << "}\n\n"
-  end
-
-  def create_mock_interfaces(file, function)
-    file << @utils.code_add_argument_loader(function)
-    file << @plugins.run(:mock_interfaces, function)
-  end
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb
deleted file mode 100644
index 3b73708e7..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb
+++ /dev/null
@@ -1,63 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockGeneratorPluginArray
-
-  attr_reader :priority
-  attr_accessor :config, :utils, :unity_helper, :ordered
-  def initialize(config, utils)
-    @config       = config
-    @ptr_handling = @config.when_ptr
-    @ordered      = @config.enforce_strict_ordering
-    @utils        = utils
-    @unity_helper = @utils.helpers[:unity_helper]
-    @priority     = 8
-  end
-
-  def instance_typedefs(function)
-    function[:args].inject("") do |all, arg|
-      (arg[:ptr?]) ? all + "  int Expected_#{arg[:name]}_Depth;\n" : all
-    end
-  end
-
-  def mock_function_declarations(function)
-    return nil unless function[:contains_ptr?]
-    args_call   = function[:args].map{|m| m[:ptr?] ? "#{m[:name]}, #{m[:name]}_Depth" : "#{m[:name]}"}.join(', ')
-    args_string = function[:args].map do |m|
-      type = @utils.arg_type_with_const(m)
-      m[:ptr?] ? "#{type} #{m[:name]}, int #{m[:name]}_Depth" : "#{type} #{m[:name]}"
-    end.join(', ')
-    if (function[:return][:void?])
-      return "#define #{function[:name]}_ExpectWithArray(#{args_call}) #{function[:name]}_CMockExpectWithArray(__LINE__, #{args_call})\n" +
-             "void #{function[:name]}_CMockExpectWithArray(UNITY_LINE_TYPE cmock_line, #{args_string});\n"
-    else
-      return "#define #{function[:name]}_ExpectWithArrayAndReturn(#{args_call}, cmock_retval) #{function[:name]}_CMockExpectWithArrayAndReturn(__LINE__, #{args_call}, cmock_retval)\n" +
-             "void #{function[:name]}_CMockExpectWithArrayAndReturn(UNITY_LINE_TYPE cmock_line, #{args_string}, #{function[:return][:str]});\n"
-    end
-  end
-
-  def mock_interfaces(function)
-    return nil unless function[:contains_ptr?]
-    lines = []
-    func_name = function[:name]
-    args_string = function[:args].map do |m|
-      type = @utils.arg_type_with_const(m)
-      m[:ptr?] ? "#{type} #{m[:name]}, int #{m[:name]}_Depth" : "#{type} #{m[:name]}"
-    end.join(', ')
-    call_string = function[:args].map{|m| m[:ptr?] ? "#{m[:name]}, #{m[:name]}_Depth" : m[:name]}.join(', ')
-    if (function[:return][:void?])
-      lines << "void #{func_name}_CMockExpectWithArray(UNITY_LINE_TYPE cmock_line, #{args_string})\n"
-    else
-      lines << "void #{func_name}_CMockExpectWithArrayAndReturn(UNITY_LINE_TYPE cmock_line, #{args_string}, #{function[:return][:str]})\n"
-    end
-    lines << "{\n"
-    lines << @utils.code_add_base_expectation(func_name)
-    lines << "  CMockExpectParameters_#{func_name}(cmock_call_instance, #{call_string});\n"
-    lines << "  cmock_call_instance->ReturnVal = cmock_to_return;\n" unless (function[:return][:void?])
-    lines << "}\n\n"
-  end
-
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_callback.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_callback.rb
deleted file mode 100644
index 564e0ac2b..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_callback.rb
+++ /dev/null
@@ -1,88 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockGeneratorPluginCallback
-
-  attr_accessor :include_count
-  attr_reader :priority
-  attr_reader :config, :utils
-
-  def initialize(config, utils)
-    @config = config
-    @utils = utils
-    @priority = 6
-
-    @include_count = @config.callback_include_count
-  end
-
-  def instance_structure(function)
-    func_name = function[:name]
-    "  int #{func_name}_CallbackBool;\n" \
-    "  CMOCK_#{func_name}_CALLBACK #{func_name}_CallbackFunctionPointer;\n" \
-    "  int #{func_name}_CallbackCalls;\n"
-  end
-
-  def mock_function_declarations(function)
-    func_name = function[:name]
-    return_type = function[:return][:type]
-    action = @config.callback_after_arg_check ? 'AddCallback' : 'Stub'
-    style  = (@include_count ? 1 : 0) | (function[:args].empty? ? 0 : 2)
-    styles = [ "void", "int cmock_num_calls", function[:args_string], "#{function[:args_string]}, int cmock_num_calls" ]
-    "typedef #{return_type} (* CMOCK_#{func_name}_CALLBACK)(#{styles[style]});\n" \
-    "void #{func_name}_AddCallback(CMOCK_#{func_name}_CALLBACK Callback);\n" \
-    "void #{func_name}_Stub(CMOCK_#{func_name}_CALLBACK Callback);\n" \
-    "#define #{func_name}_StubWithCallback #{func_name}_#{action}\n"
-  end
-
-  def generate_call(function)
-    args = function[:args].map { |m| m[:name] }
-    args << "Mock.#{function[:name]}_CallbackCalls++" if @include_count
-    "Mock.#{function[:name]}_CallbackFunctionPointer(#{args.join(', ')})"
-  end
-
-  def mock_implementation(function)
-    "  if (Mock.#{function[:name]}_CallbackFunctionPointer != NULL)\n  {\n" +
-      if function[:return][:void?]
-        "    #{generate_call(function)};\n  }\n"
-      else
-        "    cmock_call_instance->ReturnVal = #{generate_call(function)};\n  }\n"
-      end
-  end
-
-  def mock_implementation_precheck(function)
-    "  if (!Mock.#{function[:name]}_CallbackBool &&\n" \
-    "      Mock.#{function[:name]}_CallbackFunctionPointer != NULL)\n  {\n" +
-      if function[:return][:void?]
-        "    #{generate_call(function)};\n" \
-        "    UNITY_CLR_DETAILS();\n" \
-        "    return;\n  }\n"
-      else
-        "    #{function[:return][:type]} ret = #{generate_call(function)};\n" \
-        "    UNITY_CLR_DETAILS();\n" \
-        "    return ret;\n  }\n"
-      end
-  end
-
-  def mock_interfaces(function)
-    func_name = function[:name]
-    has_ignore = @config.plugins.include? :ignore
-    lines = ""
-    lines << "void #{func_name}_AddCallback(CMOCK_#{func_name}_CALLBACK Callback)\n{\n"
-    lines << "  Mock.#{func_name}_IgnoreBool = (int)0;\n" if has_ignore
-    lines << "  Mock.#{func_name}_CallbackBool = (int)1;\n"
-    lines << "  Mock.#{func_name}_CallbackFunctionPointer = Callback;\n}\n\n"
-    lines << "void #{func_name}_Stub(CMOCK_#{func_name}_CALLBACK Callback)\n{\n"
-    lines << "  Mock.#{func_name}_IgnoreBool = (int)0;\n" if has_ignore
-    lines << "  Mock.#{func_name}_CallbackBool = (int)0;\n"
-    lines << "  Mock.#{func_name}_CallbackFunctionPointer = Callback;\n}\n\n"
-  end
-
-  def mock_verify(function)
-    func_name = function[:name]
-    "  if (Mock.#{func_name}_CallbackFunctionPointer != NULL)\n    call_instance = CMOCK_GUTS_NONE;\n"
-  end
-
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_cexception.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_cexception.rb
deleted file mode 100644
index 39d36d64c..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_cexception.rb
+++ /dev/null
@@ -1,51 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockGeneratorPluginCexception
-
-  attr_reader :priority
-  attr_reader :config, :utils
-
-  def initialize(config, utils)
-    @config = config
-    @utils = utils
-    @priority = 7
-  end
-
-  def include_files
-    return "#include \"CException.h\"\n"
-  end
-
-  def instance_typedefs(function)
-    "  CEXCEPTION_T ExceptionToThrow;\n"
-  end
-
-  def mock_function_declarations(function)
-    if (function[:args_string] == "void")
-      return "#define #{function[:name]}_ExpectAndThrow(cmock_to_throw) #{function[:name]}_CMockExpectAndThrow(__LINE__, cmock_to_throw)\n" +
-             "void #{function[:name]}_CMockExpectAndThrow(UNITY_LINE_TYPE cmock_line, CEXCEPTION_T cmock_to_throw);\n"
-    else
-      return "#define #{function[:name]}_ExpectAndThrow(#{function[:args_call]}, cmock_to_throw) #{function[:name]}_CMockExpectAndThrow(__LINE__, #{function[:args_call]}, cmock_to_throw)\n" +
-             "void #{function[:name]}_CMockExpectAndThrow(UNITY_LINE_TYPE cmock_line, #{function[:args_string]}, CEXCEPTION_T cmock_to_throw);\n"
-    end
-  end
-
-  def mock_implementation(function)
-    "  if (cmock_call_instance->ExceptionToThrow != CEXCEPTION_NONE)\n  {\n" +
-    "    UNITY_CLR_DETAILS();\n" +
-    "    Throw(cmock_call_instance->ExceptionToThrow);\n  }\n"
-  end
-
-  def mock_interfaces(function)
-    arg_insert = (function[:args_string] == "void") ? "" : "#{function[:args_string]}, "
-    [ "void #{function[:name]}_CMockExpectAndThrow(UNITY_LINE_TYPE cmock_line, #{arg_insert}CEXCEPTION_T cmock_to_throw)\n{\n",
-      @utils.code_add_base_expectation(function[:name]),
-      @utils.code_call_argument_loader(function),
-      "  cmock_call_instance->ExceptionToThrow = cmock_to_throw;\n",
-      "}\n\n" ].join
-  end
-
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb
deleted file mode 100644
index dcf96f2ed..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb
+++ /dev/null
@@ -1,103 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockGeneratorPluginExpect
-
-  attr_reader :priority
-  attr_accessor :config, :utils, :unity_helper, :ordered
-
-  def initialize(config, utils)
-    @config       = config
-    @ptr_handling = @config.when_ptr
-    @ordered      = @config.enforce_strict_ordering
-    @utils        = utils
-    @unity_helper = @utils.helpers[:unity_helper]
-    @priority     = 5
-
-    if (@config.plugins.include? :expect_any_args)
-      alias :mock_implementation :mock_implementation_might_check_args
-    else
-      alias :mock_implementation :mock_implementation_always_check_args
-    end
-  end
-
-  def instance_typedefs(function)
-    lines = ""
-    lines << "  #{function[:return][:type]} ReturnVal;\n"  unless (function[:return][:void?])
-    lines << "  int CallOrder;\n"                          if (@ordered)
-    function[:args].each do |arg|
-      lines << "  #{arg[:type]} Expected_#{arg[:name]};\n"
-    end
-    lines
-  end
-
-  def mock_function_declarations(function)
-    if (function[:args].empty?)
-      if (function[:return][:void?])
-        return "#define #{function[:name]}_Expect() #{function[:name]}_CMockExpect(__LINE__)\n" +
-               "void #{function[:name]}_CMockExpect(UNITY_LINE_TYPE cmock_line);\n"
-      else
-        return "#define #{function[:name]}_ExpectAndReturn(cmock_retval) #{function[:name]}_CMockExpectAndReturn(__LINE__, cmock_retval)\n" +
-               "void #{function[:name]}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]});\n"
-      end
-    else
-      if (function[:return][:void?])
-        return "#define #{function[:name]}_Expect(#{function[:args_call]}) #{function[:name]}_CMockExpect(__LINE__, #{function[:args_call]})\n" +
-               "void #{function[:name]}_CMockExpect(UNITY_LINE_TYPE cmock_line, #{function[:args_string]});\n"
-      else
-        return "#define #{function[:name]}_ExpectAndReturn(#{function[:args_call]}, cmock_retval) #{function[:name]}_CMockExpectAndReturn(__LINE__, #{function[:args_call]}, cmock_retval)\n" +
-               "void #{function[:name]}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:args_string]}, #{function[:return][:str]});\n"
-      end
-    end
-  end
-
-  def mock_implementation_always_check_args(function)
-    lines = ""
-    function[:args].each do |arg|
-      lines << @utils.code_verify_an_arg_expectation(function, arg)
-    end
-    lines
-  end
-
-  def mock_implementation_might_check_args(function)
-    return "" if (function[:args].empty?)
-    lines = "  if (!cmock_call_instance->ExpectAnyArgsBool)\n  {\n"
-    function[:args].each do |arg|
-      lines << @utils.code_verify_an_arg_expectation(function, arg)
-    end
-    lines << "  }\n"
-    lines
-  end
-
-  def mock_interfaces(function)
-    lines = ""
-    func_name = function[:name]
-    if (function[:return][:void?])
-      if (function[:args_string] == "void")
-        lines << "void #{func_name}_CMockExpect(UNITY_LINE_TYPE cmock_line)\n{\n"
-      else
-        lines << "void #{func_name}_CMockExpect(UNITY_LINE_TYPE cmock_line, #{function[:args_string]})\n{\n"
-      end
-    else
-      if (function[:args_string] == "void")
-        lines << "void #{func_name}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]})\n{\n"
-      else
-        lines << "void #{func_name}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:args_string]}, #{function[:return][:str]})\n{\n"
-      end
-    end
-    lines << @utils.code_add_base_expectation(func_name)
-    lines << @utils.code_call_argument_loader(function)
-    lines << @utils.code_assign_argument_quickly("cmock_call_instance->ReturnVal", function[:return]) unless (function[:return][:void?])
-    lines << "}\n\n"
-  end
-
-  def mock_verify(function)
-    "  UNITY_SET_DETAIL(CMockString_#{function[:name]});\n" +
-    "  UNITY_TEST_ASSERT(CMOCK_GUTS_NONE == call_instance, cmock_line, CMockStringCalledLess);\n" +
-    "  UNITY_CLR_DETAILS();\n"
-  end
-
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect_any_args.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect_any_args.rb
deleted file mode 100644
index 0c1c74e95..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect_any_args.rb
+++ /dev/null
@@ -1,53 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockGeneratorPluginExpectAnyArgs
-
-  attr_reader :priority
-  attr_reader :config, :utils
-
-  def initialize(config, utils)
-    @config = config
-    @utils = utils
-    @priority = 3
-  end
-
-  def instance_typedefs(function)
-    "  int ExpectAnyArgsBool;\n"
-  end
-
-  def mock_function_declarations(function)
-    unless (function[:args].empty?)
-      if (function[:return][:void?])
-        return "#define #{function[:name]}_ExpectAnyArgs() #{function[:name]}_CMockExpectAnyArgs(__LINE__)\n" +
-               "void #{function[:name]}_CMockExpectAnyArgs(UNITY_LINE_TYPE cmock_line);\n"
-      else
-        return "#define #{function[:name]}_ExpectAnyArgsAndReturn(cmock_retval) #{function[:name]}_CMockExpectAnyArgsAndReturn(__LINE__, cmock_retval)\n" +
-               "void #{function[:name]}_CMockExpectAnyArgsAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]});\n"
-      end
-    else
-      ""
-    end
-  end
-
-  def mock_interfaces(function)
-    lines = ""
-    unless (function[:args].empty?)
-      if (function[:return][:void?])
-        lines << "void #{function[:name]}_CMockExpectAnyArgs(UNITY_LINE_TYPE cmock_line)\n{\n"
-      else
-        lines << "void #{function[:name]}_CMockExpectAnyArgsAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]})\n{\n"
-      end
-      lines << @utils.code_add_base_expectation(function[:name], true)
-      unless (function[:return][:void?])
-        lines << "  cmock_call_instance->ReturnVal = cmock_to_return;\n"
-      end
-      lines << "  cmock_call_instance->ExpectAnyArgsBool = (int)1;\n"
-      lines << "}\n\n"
-    end
-    return lines
-  end
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb
deleted file mode 100644
index 8f31967a1..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb
+++ /dev/null
@@ -1,75 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockGeneratorPluginIgnore
-
-  attr_reader :priority
-  attr_reader :config, :utils
-
-  def initialize(config, utils)
-    @config = config
-    @utils = utils
-    @priority = 2
-  end
-
-  def instance_structure(function)
-    if (function[:return][:void?])
-      "  int #{function[:name]}_IgnoreBool;\n"
-    else
-      "  int #{function[:name]}_IgnoreBool;\n  #{function[:return][:type]} #{function[:name]}_FinalReturn;\n"
-    end
-  end
-
-  def mock_function_declarations(function)
-    if (function[:return][:void?])
-      return "#define #{function[:name]}_Ignore() #{function[:name]}_CMockIgnore()\n" +
-             "void #{function[:name]}_CMockIgnore(void);\n"
-    else
-      return "#define #{function[:name]}_IgnoreAndReturn(cmock_retval) #{function[:name]}_CMockIgnoreAndReturn(__LINE__, cmock_retval)\n" +
-             "void #{function[:name]}_CMockIgnoreAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]});\n"
-    end
-  end
-
-  def mock_implementation_precheck(function)
-    lines = "  if (Mock.#{function[:name]}_IgnoreBool)\n  {\n"
-    lines << "    UNITY_CLR_DETAILS();\n"
-    if (function[:return][:void?])
-      lines << "    return;\n  }\n"
-    else
-      retval = function[:return].merge( { :name => "cmock_call_instance->ReturnVal"} )
-      lines << "    if (cmock_call_instance == NULL)\n      return Mock.#{function[:name]}_FinalReturn;\n"
-      lines << "  " + @utils.code_assign_argument_quickly("Mock.#{function[:name]}_FinalReturn", retval) unless (retval[:void?])
-      lines << "    return cmock_call_instance->ReturnVal;\n  }\n"
-    end
-    lines
-  end
-
-  def mock_interfaces(function)
-    lines = ""
-    if (function[:return][:void?])
-      lines << "void #{function[:name]}_CMockIgnore(void)\n{\n"
-    else
-      lines << "void #{function[:name]}_CMockIgnoreAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]})\n{\n"
-    end
-    if (!function[:return][:void?])
-      lines << @utils.code_add_base_expectation(function[:name], false)
-    end
-    unless (function[:return][:void?])
-      lines << "  cmock_call_instance->ReturnVal = cmock_to_return;\n"
-    end
-    lines << "  Mock.#{function[:name]}_IgnoreBool = (int)1;\n"
-    lines << "}\n\n"
-  end
-
-  def mock_ignore(function)
-    "  Mock.#{function[:name]}_IgnoreBool = (int) 1;\n"
-  end
-
-  def mock_verify(function)
-    func_name = function[:name]
-    "  if (Mock.#{func_name}_IgnoreBool)\n    call_instance = CMOCK_GUTS_NONE;\n"
-  end
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_arg.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_arg.rb
deleted file mode 100644
index ef40e503d..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_arg.rb
+++ /dev/null
@@ -1,42 +0,0 @@
-class CMockGeneratorPluginIgnoreArg
-  attr_reader :priority
-  attr_accessor :utils
-
-  def initialize(config, utils)
-    @utils        = utils
-    @priority     = 10
-  end
-
-  def instance_typedefs(function)
-    lines = ""
-    function[:args].each do |arg|
-      lines << "  int IgnoreArg_#{arg[:name]};\n"
-    end
-    lines
-  end
-
-  def mock_function_declarations(function)
-    lines = ""
-    function[:args].each do |arg|
-      lines << "#define #{function[:name]}_IgnoreArg_#{arg[:name]}()"
-      lines << " #{function[:name]}_CMockIgnoreArg_#{arg[:name]}(__LINE__)\n"
-      lines << "void #{function[:name]}_CMockIgnoreArg_#{arg[:name]}(UNITY_LINE_TYPE cmock_line);\n"
-    end
-    lines
-  end
-
-  def mock_interfaces(function)
-    lines = []
-    func_name = function[:name]
-    function[:args].each do |arg|
-      lines << "void #{func_name}_CMockIgnoreArg_#{arg[:name]}(UNITY_LINE_TYPE cmock_line)\n"
-      lines << "{\n"
-      lines << "  CMOCK_#{func_name}_CALL_INSTANCE* cmock_call_instance = " +
-        "(CMOCK_#{func_name}_CALL_INSTANCE*)CMock_Guts_GetAddressFor(CMock_Guts_MemEndOfChain(Mock.#{func_name}_CallInstance));\n"
-      lines << "  UNITY_TEST_ASSERT_NOT_NULL(cmock_call_instance, cmock_line, CMockStringIgnPreExp);\n"
-      lines << "  cmock_call_instance->IgnoreArg_#{arg[:name]} = 1;\n"
-      lines << "}\n\n"
-    end
-    lines
-  end
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb
deleted file mode 100644
index 1c1af0610..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb
+++ /dev/null
@@ -1,79 +0,0 @@
-class CMockGeneratorPluginReturnThruPtr
-  attr_reader :priority
-  attr_accessor :utils
-
-  def initialize(config, utils)
-    @utils        = utils
-    @priority     = 9
-  end
-
-  def instance_typedefs(function)
-    lines = ""
-    function[:args].each do |arg|
-      if (@utils.ptr_or_str?(arg[:type]) and not arg[:const?])
-        lines << "  int ReturnThruPtr_#{arg[:name]}_Used;\n"
-        lines << "  #{arg[:type]} ReturnThruPtr_#{arg[:name]}_Val;\n"
-        lines << "  int ReturnThruPtr_#{arg[:name]}_Size;\n"
-      end
-    end
-    lines
-  end
-
-  def mock_function_declarations(function)
-    lines = ""
-    function[:args].each do |arg|
-      if (@utils.ptr_or_str?(arg[:type]) and not arg[:const?])
-        lines << "#define #{function[:name]}_ReturnThruPtr_#{arg[:name]}(#{arg[:name]})"
-        # If the pointer type actually contains an asterisk, we can do sizeof the type (super safe), otherwise
-        # we need to do a sizeof the dereferenced pointer (which could be a problem if give the wrong size
-        if (arg[:type][-1] == '*')
-          lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, sizeof(#{arg[:type][0..-2]}))\n"
-        else
-          lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, sizeof(*#{arg[:name]}))\n"
-        end
-        lines << "#define #{function[:name]}_ReturnArrayThruPtr_#{arg[:name]}(#{arg[:name]}, cmock_len)"
-        lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, (int)(cmock_len * (int)sizeof(*#{arg[:name]})))\n"
-        lines << "#define #{function[:name]}_ReturnMemThruPtr_#{arg[:name]}(#{arg[:name]}, cmock_size)"
-        lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, cmock_size)\n"
-        lines << "void #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(UNITY_LINE_TYPE cmock_line, #{arg[:type]} #{arg[:name]}, int cmock_size);\n"
-      end
-    end
-    lines
-  end
-
-  def mock_interfaces(function)
-    lines = []
-    func_name = function[:name]
-    function[:args].each do |arg|
-      arg_name = arg[:name]
-      if (@utils.ptr_or_str?(arg[:type]) and not arg[:const?])
-        lines << "void #{func_name}_CMockReturnMemThruPtr_#{arg_name}(UNITY_LINE_TYPE cmock_line, #{arg[:type]} #{arg_name}, int cmock_size)\n"
-        lines << "{\n"
-        lines << "  CMOCK_#{func_name}_CALL_INSTANCE* cmock_call_instance = " +
-          "(CMOCK_#{func_name}_CALL_INSTANCE*)CMock_Guts_GetAddressFor(CMock_Guts_MemEndOfChain(Mock.#{func_name}_CallInstance));\n"
-        lines << "  UNITY_TEST_ASSERT_NOT_NULL(cmock_call_instance, cmock_line, CMockStringPtrPreExp);\n"
-        lines << "  cmock_call_instance->ReturnThruPtr_#{arg_name}_Used = 1;\n"
-        lines << "  cmock_call_instance->ReturnThruPtr_#{arg_name}_Val = #{arg_name};\n"
-        lines << "  cmock_call_instance->ReturnThruPtr_#{arg_name}_Size = cmock_size;\n"
-        lines << "}\n\n"
-      end
-    end
-    lines
-  end
-
-  def mock_implementation(function)
-    lines = []
-    function[:args].each do |arg|
-      arg_name = arg[:name]
-      if (@utils.ptr_or_str?(arg[:type]) and not arg[:const?])
-        lines << "  if (cmock_call_instance->ReturnThruPtr_#{arg_name}_Used)\n"
-        lines << "  {\n"
-        lines << "    UNITY_TEST_ASSERT_NOT_NULL(#{arg_name}, cmock_line, CMockStringPtrIsNULL);\n"
-        lines << "    memcpy((void*)#{arg_name}, (void*)cmock_call_instance->ReturnThruPtr_#{arg_name}_Val,\n"
-        lines << "      cmock_call_instance->ReturnThruPtr_#{arg_name}_Size);\n"
-        lines << "  }\n"
-      end
-    end
-    lines
-  end
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb
deleted file mode 100644
index 994e85c5d..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb
+++ /dev/null
@@ -1,253 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockGeneratorUtils
-
-  attr_accessor :config, :helpers, :ordered, :ptr_handling, :arrays, :cexception
-
-  def initialize(config, helpers={})
-    @config = config
-    @ptr_handling = @config.when_ptr
-    @ordered      = @config.enforce_strict_ordering
-    @arrays       = @config.plugins.include? :array
-    @cexception   = @config.plugins.include? :cexception
-    @expect_any   = @config.plugins.include? :expect_any_args
-    @return_thru_ptr = @config.plugins.include? :return_thru_ptr
-    @ignore_arg   = @config.plugins.include? :ignore_arg
-    @ignore       = @config.plugins.include? :ignore
-    @treat_as     = @config.treat_as
-    @helpers = helpers
-  end
-
-  def self.arg_type_with_const(arg)
-    # Restore any "const" that was removed in header parsing
-    if arg[:type].include?('*')
-      arg[:const_ptr?] ? "#{arg[:type]} const" : arg[:type]
-    else
-      arg[:const?] ? "const #{arg[:type]}" : arg[:type]
-    end
-  end
-
-  def arg_type_with_const(arg)
-    self.class.arg_type_with_const(arg)
-  end
-
-  def code_verify_an_arg_expectation(function, arg)
-    if (@arrays)
-      case(@ptr_handling)
-        when :smart        then code_verify_an_arg_expectation_with_smart_arrays(function, arg)
-        when :compare_data then code_verify_an_arg_expectation_with_normal_arrays(function, arg)
-        when :compare_ptr  then raise "ERROR: the array plugin doesn't enjoy working with :compare_ptr only.  Disable one option."
-      end
-    else
-      code_verify_an_arg_expectation_with_no_arrays(function, arg)
-    end
-  end
-
-  def code_add_base_expectation(func_name, global_ordering_supported=true)
-    lines =  "  CMOCK_MEM_INDEX_TYPE cmock_guts_index = CMock_Guts_MemNew(sizeof(CMOCK_#{func_name}_CALL_INSTANCE));\n"
-    lines << "  CMOCK_#{func_name}_CALL_INSTANCE* cmock_call_instance = (CMOCK_#{func_name}_CALL_INSTANCE*)CMock_Guts_GetAddressFor(cmock_guts_index);\n"
-    lines << "  UNITY_TEST_ASSERT_NOT_NULL(cmock_call_instance, cmock_line, CMockStringOutOfMemory);\n"
-    lines << "  memset(cmock_call_instance, 0, sizeof(*cmock_call_instance));\n"
-    lines << "  Mock.#{func_name}_CallInstance = CMock_Guts_MemChain(Mock.#{func_name}_CallInstance, cmock_guts_index);\n"
-    lines << "  Mock.#{func_name}_IgnoreBool = (int)0;\n" if (@ignore)
-    lines << "  cmock_call_instance->LineNumber = cmock_line;\n"
-    lines << "  cmock_call_instance->CallOrder = ++GlobalExpectCount;\n" if (@ordered and global_ordering_supported)
-    lines << "  cmock_call_instance->ExceptionToThrow = CEXCEPTION_NONE;\n" if (@cexception)
-    lines << "  cmock_call_instance->ExpectAnyArgsBool = (int)0;\n" if (@expect_any)
-    lines
-  end
-
-  def code_add_an_arg_expectation(arg, depth=1)
-    lines =  code_assign_argument_quickly("cmock_call_instance->Expected_#{arg[:name]}", arg)
-    lines << "  cmock_call_instance->Expected_#{arg[:name]}_Depth = #{arg[:name]}_Depth;\n" if (@arrays and (depth.class == String))
-    lines << "  cmock_call_instance->IgnoreArg_#{arg[:name]} = 0;\n" if (@ignore_arg)
-    lines << "  cmock_call_instance->ReturnThruPtr_#{arg[:name]}_Used = 0;\n" if (@return_thru_ptr and ptr_or_str?(arg[:type]) and not arg[:const?])
-    lines
-  end
-
-  def code_assign_argument_quickly(dest, arg)
-    if (arg[:ptr?] or @treat_as.include?(arg[:type]))
-      "  #{dest} = #{arg[:name]};\n"
-    else
-      assert_expr = "sizeof(#{arg[:name]}) == sizeof(#{arg[:type]}) ? 1 : -1"
-      comment = "/* add #{arg[:type]} to :treat_as_array if this causes an error */"
-      "  memcpy((void*)(&#{dest}), (void*)(&#{arg[:name]}),\n" +
-      "         sizeof(#{arg[:type]}[#{assert_expr}])); #{comment}\n"
-    end
-  end
-
-  def code_add_argument_loader(function)
-    if (function[:args_string] != "void")
-      if (@arrays)
-        args_string = function[:args].map do |m|
-          type = arg_type_with_const(m)
-          m[:ptr?] ? "#{type} #{m[:name]}, int #{m[:name]}_Depth" : "#{type} #{m[:name]}"
-        end.join(', ')
-        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{args_string});\n" +
-        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{args_string})\n{\n" +
-        function[:args].inject("") { |all, arg| all + code_add_an_arg_expectation(arg, (arg[:ptr?] ? "#{arg[:name]}_Depth" : 1) ) } +
-        "}\n\n"
-      else
-        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{function[:args_string]});\n" +
-        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{function[:args_string]})\n{\n" +
-        function[:args].inject("") { |all, arg| all + code_add_an_arg_expectation(arg) } +
-        "}\n\n"
-      end
-    else
-      ""
-    end
-  end
-
-  def code_call_argument_loader(function)
-    if (function[:args_string] != "void")
-      args = function[:args].map do |m|
-        if (@arrays and m[:ptr?] and not m[:array_data?])
-          "#{m[:name]}, 1"
-        elsif (@arrays and m[:array_size?])
-          "#{m[:name]}, #{m[:name]}"
-        else
-          m[:name]
-        end
-      end
-      "  CMockExpectParameters_#{function[:name]}(cmock_call_instance, #{args.join(', ')});\n"
-    else
-      ""
-    end
-  end
-
-  def ptr_or_str?(arg_type)
-    return (arg_type.include? '*' or
-            @treat_as.fetch(arg_type, "").include? '*')
-  end
-
-  #private ######################
-
-  def lookup_expect_type(function, arg)
-    c_type     = arg[:type]
-    arg_name   = arg[:name]
-    expected   = "cmock_call_instance->Expected_#{arg_name}"
-    ignore     = "cmock_call_instance->IgnoreArg_#{arg_name}"
-    unity_func = if ((arg[:ptr?]) and ((c_type =~ /\*\*/) or (@ptr_handling == :compare_ptr)))
-                   ['UNITY_TEST_ASSERT_EQUAL_PTR', '']
-                 else
-                   (@helpers.nil? or @helpers[:unity_helper].nil?) ? ["UNITY_TEST_ASSERT_EQUAL",''] : @helpers[:unity_helper].get_helper(c_type)
-                 end
-    return c_type, arg_name, expected, ignore, unity_func[0], unity_func[1]
-  end
-
-  def code_verify_an_arg_expectation_with_no_arrays(function, arg)
-    c_type, arg_name, expected, ignore, unity_func, pre = lookup_expect_type(function, arg)
-    lines = ""
-    lines << "  if (!#{ignore})\n" if @ignore_arg
-    lines << "  {\n"
-    lines << "    UNITY_SET_DETAILS(CMockString_#{function[:name]},CMockString_#{arg_name});\n"
-    case(unity_func)
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY"
-        c_type_local = c_type.gsub(/\*$/,'')
-        lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type_local}), cmock_line, CMockStringMismatch);\n"
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY"
-        if (pre == '&')
-          lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << "    else\n"
-          lines << "      { UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), cmock_line, CMockStringMismatch); }\n"
-        end
-      when /_ARRAY/
-        if (pre == '&')
-          lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, 1, cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << "    else\n"
-          lines << "      { #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, 1, cmock_line, CMockStringMismatch); }\n"
-        end
-      else
-        lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch);\n"
-    end
-    lines << "  }\n"
-    lines
-  end
-
-  def code_verify_an_arg_expectation_with_normal_arrays(function, arg)
-    c_type, arg_name, expected, ignore, unity_func, pre = lookup_expect_type(function, arg)
-    depth_name = (arg[:ptr?]) ? "cmock_call_instance->Expected_#{arg_name}_Depth" : 1
-    lines = ""
-    lines << "  if (!#{ignore})\n" if @ignore_arg
-    lines << "  {\n"
-    lines << "    UNITY_SET_DETAILS(CMockString_#{function[:name]},CMockString_#{arg_name});\n"
-    lines << "    if (#{pre}#{expected} != #{pre}#{arg_name}) {\n"
-    case(unity_func)
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY"
-        c_type_local = c_type.gsub(/\*$/,'')
-        lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type_local}), cmock_line, CMockStringMismatch);\n"
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY"
-        if (pre == '&')
-          lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << "    else\n"
-          lines << "      { UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), #{depth_name}, cmock_line, CMockStringMismatch); }\n"
-        end
-      when /_ARRAY/
-        if (pre == '&')
-          lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << "    else\n"
-          lines << "      { #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch); }\n"
-        end
-      else
-        lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch);\n"
-    end
-    lines << "      }\n  }\n"
-    lines
-  end
-
-  def code_verify_an_arg_expectation_with_smart_arrays(function, arg)
-    c_type, arg_name, expected, ignore, unity_func, pre = lookup_expect_type(function, arg)
-    depth_name = (arg[:ptr?]) ? "cmock_call_instance->Expected_#{arg_name}_Depth" : 1
-    lines = ""
-    lines << "  if (!#{ignore})\n" if @ignore_arg
-    lines << "  {\n"
-    lines << "    UNITY_SET_DETAILS(CMockString_#{function[:name]},CMockString_#{arg_name});\n"
-    lines << "    if (#{pre}#{expected} != #{pre}#{arg_name}) {\n"
-    case(unity_func)
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY"
-        c_type_local = c_type.gsub(/\*$/,'')
-        lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type_local}), cmock_line, CMockStringMismatch);\n"
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY"
-        if (pre == '&')
-          lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), #{depth_name}, cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << ((depth_name != 1) ? "    else if (#{depth_name} == 0)\n      { UNITY_TEST_ASSERT_EQUAL_PTR(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch); }\n" : "")
-          lines << "    else\n"
-          lines << "      { UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), #{depth_name}, cmock_line, CMockStringMismatch); }\n"
-        end
-      when /_ARRAY/
-        if (pre == '&')
-          lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << ((depth_name != 1) ? "    else if (#{depth_name} == 0)\n      { UNITY_TEST_ASSERT_EQUAL_PTR(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch); }\n" : "")
-          lines << "    else\n"
-          lines << "      { #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch); }\n"
-        end
-      else
-        lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch);\n"
-    end
-    lines << "    }\n  }\n"
-    lines
-  end
-
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb
deleted file mode 100644
index 0cf19478d..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb
+++ /dev/null
@@ -1,364 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class CMockHeaderParser
-
-  attr_accessor :funcs, :c_attr_noconst, :c_attributes, :treat_as_void, :treat_externs
-
-  def initialize(cfg)
-    @funcs = []
-    @c_strippables = cfg.strippables
-    @c_attr_noconst = cfg.attributes.uniq - ['const']
-    @c_attributes = ['const'] + c_attr_noconst
-    @c_calling_conventions = cfg.c_calling_conventions.uniq
-    @treat_as_array = cfg.treat_as_array
-    @treat_as_void = (['void'] + cfg.treat_as_void).uniq
-    @declaration_parse_matcher = /([\w\s\*\(\),\[\]]+??)\(([\w\s\*\(\),\.\[\]+-]*)\)$/m
-    @standards = (['int','short','char','long','unsigned','signed'] + cfg.treat_as.keys).uniq
-    @array_size_name = cfg.array_size_name
-    @array_size_type = (['int', 'size_t'] + cfg.array_size_type).uniq
-    @when_no_prototypes = cfg.when_no_prototypes
-    @local_as_void = @treat_as_void
-    @verbosity = cfg.verbosity
-    @treat_externs = cfg.treat_externs
-    @c_strippables += ['extern'] if (@treat_externs == :include) #we'll need to remove the attribute if we're allowing externs
-  end
-
-  def parse(name, source)
-    @module_name = name.gsub(/\W/,'')
-    @typedefs = []
-    @funcs = []
-    function_names = []
-
-    parse_functions( import_source(source) ).map do |decl|
-      func = parse_declaration(decl)
-      unless (function_names.include? func[:name])
-        @funcs << func
-        function_names << func[:name]
-      end
-    end
-
-    { :includes  => nil,
-      :functions => @funcs,
-      :typedefs  => @typedefs
-    }
-  end
-
-  private if $ThisIsOnlyATest.nil? ################
-
-  def import_source(source)
-
-    # let's clean up the encoding in case they've done anything weird with the characters we might find
-    source = source.force_encoding("ISO-8859-1").encode("utf-8", :replace => nil)
-
-    # void must be void for cmock _ExpectAndReturn calls to process properly, not some weird typedef which equates to void
-    # to a certain extent, this action assumes we're chewing on pre-processed header files, otherwise we'll most likely just get stuff from @treat_as_void
-    @local_as_void = @treat_as_void
-    void_types = source.scan(/typedef\s+(?:\(\s*)?void(?:\s*\))?\s+([\w]+)\s*;/)
-    if void_types
-      @local_as_void += void_types.flatten.uniq.compact
-    end
-
-    # smush multiline macros into single line (checking for continuation character at end of line '\')
-    source.gsub!(/\s*\\\s*/m, ' ')
-
-    #remove comments (block and line, in three steps to ensure correct precedence)
-    source.gsub!(/(?<!\*)\/\/(?:.+\/\*|\*(?:$|[^\/])).*$/, '')  # remove line comments that comment out the start of blocks
-    source.gsub!(/\/\*.*?\*\//m, '')                            # remove block comments
-    source.gsub!(/\/\/.*$/, '')                                 # remove line comments (all that remain)
-
-    # remove assembler pragma sections
-    source.gsub!(/^\s*#\s*pragma\s+asm\s+.*?#\s*pragma\s+endasm/m, '')
-
-    # remove gcc's __attribute__ tags
-    source.gsub!(/__attribute(?:__)?\s*\(\(+.*\)\)+/, '')
-
-    # remove preprocessor statements and extern "C"
-    source.gsub!(/^\s*#.*/, '')
-    source.gsub!(/extern\s+\"C\"\s*\{/, '')
-
-    # enums, unions, structs, and typedefs can all contain things (e.g. function pointers) that parse like function prototypes, so yank them
-    # forward declared structs are removed before struct definitions so they don't mess up real thing later. we leave structs keywords in function prototypes
-    source.gsub!(/^[\w\s]*struct[^;\{\}\(\)]+;/m, '')                                      # remove forward declared structs
-    source.gsub!(/^[\w\s]*(enum|union|struct|typedef)[\w\s]*\{[^\}]+\}[\w\s\*\,]*;/m, '')  # remove struct, union, and enum definitions and typedefs with braces
-    source.gsub!(/(\W)(?:register|auto|static|restrict)(\W)/, '\1\2')                      # remove problem keywords
-    source.gsub!(/\s*=\s*['"a-zA-Z0-9_\.]+\s*/, '')                                        # remove default value statements from argument lists
-    source.gsub!(/^(?:[\w\s]*\W)?typedef\W[^;]*/m, '')                                     # remove typedef statements
-    source.gsub!(/\)(\w)/, ') \1')                                                         # add space between parenthese and alphanumeric
-    source.gsub!(/(^|\W+)(?:#{@c_strippables.join('|')})(?=$|\W+)/,'\1') unless @c_strippables.empty? # remove known attributes slated to be stripped
-
-    #scan standalone function pointers and remove them, because they can just be ignored
-    source.gsub!(/\w+\s*\(\s*\*\s*\w+\s*\)\s*\([^)]*\)\s*;/,';')
-
-    #scan for functions which return function pointers, because they are a pain
-    source.gsub!(/([\w\s\*]+)\(*\(\s*\*([\w\s\*]+)\s*\(([\w\s\*,]*)\)\)\s*\(([\w\s\*,]*)\)\)*/) do |m|
-      functype = "cmock_#{@module_name}_func_ptr#{@typedefs.size + 1}"
-      @typedefs << "typedef #{$1.strip}(*#{functype})(#{$4});"
-      "#{functype} #{$2.strip}(#{$3});"
-    end
-
-    # remove nested pairs of braces because no function declarations will be inside of them (leave outer pair for function definition detection)
-    if (RUBY_VERSION.split('.')[0].to_i > 1)
-      #we assign a string first because (no joke) if Ruby 1.9.3 sees this line as a regex, it will crash.
-      r = "\\{([^\\{\\}]*|\\g<0>)*\\}"
-      source.gsub!(/#{r}/m, '{ }')
-    else
-      while source.gsub!(/\{[^\{\}]*\{[^\{\}]*\}[^\{\}]*\}/m, '{ }')
-      end
-    end
-
-    # remove function definitions by stripping off the arguments right now
-    source.gsub!(/\([^\)]*\)\s*\{[^\}]*\}/m, ";")
-
-    #drop extra white space to make the rest go faster
-    source.gsub!(/^\s+/, '')          # remove extra white space from beginning of line
-    source.gsub!(/\s+$/, '')          # remove extra white space from end of line
-    source.gsub!(/\s*\(\s*/, '(')     # remove extra white space from before left parens
-    source.gsub!(/\s*\)\s*/, ')')     # remove extra white space from before right parens
-    source.gsub!(/\s+/, ' ')          # remove remaining extra white space
-
-    #split lines on semicolons and remove things that are obviously not what we are looking for
-    src_lines = source.split(/\s*;\s*/).uniq
-    src_lines.delete_if {|line| line.strip.length == 0}                            # remove blank lines
-    src_lines.delete_if {|line| !(line =~ /[\w\s\*]+\(+\s*\*[\*\s]*[\w\s]+(?:\[[\w\s]*\]\s*)+\)+\s*\((?:[\w\s\*]*,?)*\s*\)/).nil?}     #remove function pointer arrays
-    if (@treat_externs == :include)
-      src_lines.delete_if {|line| !(line =~ /(?:^|\s+)(?:inline)\s+/).nil?}        # remove inline functions
-    else
-      src_lines.delete_if {|line| !(line =~ /(?:^|\s+)(?:extern|inline)\s+/).nil?} # remove inline and extern functions
-    end
-    src_lines.delete_if {|line| line.empty? } #drop empty lines
-  end
-
-  def parse_functions(source)
-    funcs = []
-    source.each {|line| funcs << line.strip.gsub(/\s+/, ' ') if (line =~ @declaration_parse_matcher)}
-    if funcs.empty?
-      case @when_no_prototypes
-        when :error
-          raise "ERROR: No function prototypes found!"
-        when :warn
-          puts "WARNING: No function prototypes found!" unless (@verbosity < 1)
-      end
-    end
-    return funcs
-  end
-
-  def parse_type_and_name(arg)
-    # Split up words and remove known attributes.  For pointer types, make sure
-    # to remove 'const' only when it applies to the pointer itself, not when it
-    # applies to the type pointed to.  For non-pointer types, remove any
-    # occurrence of 'const'.
-    arg.gsub!(/(\w)\*/,'\1 *') # pull asterisks away from preceding word
-    arg.gsub!(/\*(\w)/,'* \1') # pull asterisks away from following word
-    arg_array = arg.split
-    arg_info = divine_ptr_and_const(arg)
-    arg_info[:name] = arg_array[-1]
-
-    attributes = arg.include?('*') ? @c_attr_noconst : @c_attributes
-    attr_array = []
-    type_array = []
-
-    arg_array[0..-2].each do |word|
-      if attributes.include?(word)
-        attr_array << word
-      elsif @c_calling_conventions.include?(word)
-        arg_info[:c_calling_convention] = word
-      else
-        type_array << word
-      end
-    end
-
-    if arg_info[:const_ptr?]
-      attr_array << 'const'
-      type_array.delete_at(type_array.rindex('const'))
-    end
-
-    arg_info[:modifier] = attr_array.join(' ')
-    arg_info[:type] = type_array.join(' ').gsub(/\s+\*/,'*') # remove space before asterisks
-    return arg_info
-  end
-
-  def parse_args(arg_list)
-    args = []
-    arg_list.split(',').each do |arg|
-      arg.strip!
-      return args if (arg =~ /^\s*((\.\.\.)|(void))\s*$/)   # we're done if we reach void by itself or ...
-
-      arg_info = parse_type_and_name(arg)
-      arg_info.delete(:modifier)             # don't care about this
-      arg_info.delete(:c_calling_convention) # don't care about this
-
-      # in C, array arguments implicitly degrade to pointers
-      # make the translation explicit here to simplify later logic
-      if @treat_as_array[arg_info[:type]] and not arg_info[:ptr?] then
-        arg_info[:type] = "#{@treat_as_array[arg_info[:type]]}*"
-        arg_info[:type] = "const #{arg_info[:type]}" if arg_info[:const?]
-        arg_info[:ptr?] = true
-      end
-
-      args << arg_info
-    end
-
-    # Try to find array pair in parameters following this pattern : <type> * <name>, <@array_size_type> <@array_size_name>
-    args.each_with_index {|val, index|
-      next_index = index + 1
-      if (args.length > next_index)
-        if (val[:ptr?] == true and args[next_index][:name].match(@array_size_name) and @array_size_type.include?(args[next_index][:type]))
-          val[:array_data?] = true
-          args[next_index][:array_size?] = true
-        end
-      end
-    }
-
-    return args
-  end
-
-  def divine_ptr(arg)
-    return false unless arg.include? '*'
-    # treat "const char *" and similar as a string, not a pointer
-    return false if /(^|\s)(const\s+)?char(\s+const)?\s*\*(?!.*\*)/ =~ arg
-    return true
-  end
-
-  def divine_const(arg)
-    # a non-pointer arg containing "const" is a constant
-    # an arg containing "const" before the last * is a pointer to a constant
-    return ( arg.include?('*') ? (/(^|\s|\*)const(\s(\w|\s)*)?\*(?!.*\*)/ =~ arg)
-                               : (/(^|\s)const(\s|$)/ =~ arg) ) ? true : false
-  end
-
-  def divine_ptr_and_const(arg)
-    divination = {}
-
-    divination[:ptr?] = divine_ptr(arg)
-    divination[:const?] = divine_const(arg)
-
-    # an arg containing "const" after the last * is a constant pointer
-    divination[:const_ptr?] = (/\*(?!.*\*)\s*const(\s|$)/ =~ arg) ? true : false
-
-    return divination
-  end
-
-  def clean_args(arg_list)
-    if ((@local_as_void.include?(arg_list.strip)) or (arg_list.empty?))
-      return 'void'
-    else
-      c=0
-      arg_list.gsub!(/(\w+)(?:\s*\[\s*\(*[\s\w+-]*\)*\s*\])+/,'*\1')  # magically turn brackets into asterisks, also match for parentheses that come from macros
-      arg_list.gsub!(/\s+\*/,'*')                                       # remove space to place asterisks with type (where they belong)
-      arg_list.gsub!(/\*(\w)/,'* \1')                                   # pull asterisks away from arg to place asterisks with type (where they belong)
-
-      #scan argument list for function pointers and replace them with custom types
-      arg_list.gsub!(/([\w\s\*]+)\(+\s*\*[\*\s]*([\w\s]*)\s*\)+\s*\(((?:[\w\s\*]*,?)*)\s*\)*/) do |m|
-
-        functype = "cmock_#{@module_name}_func_ptr#{@typedefs.size + 1}"
-        funcret  = $1.strip
-        funcname = $2.strip
-        funcargs = $3.strip
-        funconst = ''
-        if (funcname.include? 'const')
-          funcname.gsub!('const','').strip!
-          funconst = 'const '
-        end
-        @typedefs << "typedef #{funcret}(*#{functype})(#{funcargs});"
-        funcname = "cmock_arg#{c+=1}" if (funcname.empty?)
-        "#{functype} #{funconst}#{funcname}"
-      end
-
-      #automatically name unnamed arguments (those that only had a type)
-      arg_list.split(/\s*,\s*/).map { |arg|
-        parts = (arg.split - ['struct', 'union', 'enum', 'const', 'const*'])
-        if ((parts.size < 2) or (parts[-1][-1].chr == '*') or (@standards.include?(parts[-1])))
-          "#{arg} cmock_arg#{c+=1}"
-        else
-          arg
-        end
-      }.join(', ')
-    end
-  end
-
-  def parse_declaration(declaration)
-    decl = {}
-
-    regex_match = @declaration_parse_matcher.match(declaration)
-    raise "Failed parsing function declaration: '#{declaration}'" if regex_match.nil?
-
-    #grab argument list
-    args = regex_match[2].strip
-
-    #process function attributes, return type, and name
-    parsed = parse_type_and_name(regex_match[1])
-
-    decl[:name] = parsed[:name]
-    decl[:modifier] = parsed[:modifier]
-    unless parsed[:c_calling_convention].nil?
-      decl[:c_calling_convention] = parsed[:c_calling_convention]
-    end
-
-    rettype = parsed[:type]
-    rettype = 'void' if (@local_as_void.include?(rettype.strip))
-    decl[:return] = { :type       => rettype,
-                      :name       => 'cmock_to_return',
-                      :str        => "#{rettype} cmock_to_return",
-                      :void?      => (rettype == 'void'),
-                      :ptr?       => parsed[:ptr?],
-                      :const?     => parsed[:const?],
-                      :const_ptr? => parsed[:const_ptr?]
-                    }
-
-    #remove default argument statements from mock definitions
-    args.gsub!(/=\s*[a-zA-Z0-9_\.]+\s*/, ' ')
-
-    #check for var args
-    if (args =~ /\.\.\./)
-      decl[:var_arg] = args.match( /[\w\s]*\.\.\./ ).to_s.strip
-      if (args =~ /\,[\w\s]*\.\.\./)
-        args = args.gsub!(/\,[\w\s]*\.\.\./,'')
-      else
-        args = 'void'
-      end
-    else
-      decl[:var_arg] = nil
-    end
-    args = clean_args(args)
-    decl[:args_string] = args
-    decl[:args] = parse_args(args)
-    decl[:args_call] = decl[:args].map{|a| a[:name]}.join(', ')
-    decl[:contains_ptr?] = decl[:args].inject(false) {|ptr, arg| arg[:ptr?] ? true : ptr }
-
-    if (decl[:return][:type].nil?   or decl[:name].nil?   or decl[:args].nil? or
-        decl[:return][:type].empty? or decl[:name].empty?)
-      raise "Failed Parsing Declaration Prototype!\n" +
-        "  declaration: '#{declaration}'\n" +
-        "  modifier: '#{decl[:modifier]}'\n" +
-        "  return: #{prototype_inspect_hash(decl[:return])}\n" +
-        "  function: '#{decl[:name]}'\n" +
-        "  args: #{prototype_inspect_array_of_hashes(decl[:args])}\n"
-    end
-
-    return decl
-  end
-
-  def prototype_inspect_hash(hash)
-    pairs = []
-    hash.each_pair { |name, value| pairs << ":#{name} => #{"'" if (value.class == String)}#{value}#{"'" if (value.class == String)}" }
-    return "{#{pairs.join(', ')}}"
-  end
-
-  def prototype_inspect_array_of_hashes(array)
-    hashes = []
-    array.each { |hash| hashes << prototype_inspect_hash(hash) }
-    case (array.size)
-    when 0
-      return "[]"
-    when 1
-      return "[#{hashes[0]}]"
-    else
-      return "[\n    #{hashes.join("\n    ")}\n  ]\n"
-    end
-  end
-
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb
deleted file mode 100644
index cc5ced2ad..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb
+++ /dev/null
@@ -1,55 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-require 'thread'
-
-class CMockPluginManager
-
-  attr_accessor :plugins
-
-  def initialize(config, utils)
-    @plugins = []
-    plugins_to_load = [:expect, config.plugins].flatten.uniq.compact
-    plugins_to_load.each do |plugin|
-      plugin_name = plugin.to_s
-      object_name = "CMockGeneratorPlugin" + camelize(plugin_name)
-      self.class.plugin_require_mutex.synchronize { load_plugin(plugin_name, object_name, config, utils) }
-    end
-    @plugins.sort! {|a,b| a.priority <=> b.priority }
-  end
-
-  def run(method, args=nil)
-    if args.nil?
-      return @plugins.collect{ |plugin| plugin.send(method) if plugin.respond_to?(method) }.flatten.join
-    else
-      return @plugins.collect{ |plugin| plugin.send(method, args) if plugin.respond_to?(method) }.flatten.join
-    end
-  end
-
-  def camelize(lower_case_and_underscored_word)
-    lower_case_and_underscored_word.gsub(/\/(.?)/) { "::" + $1.upcase }.gsub(/(^|_)(.)/) { $2.upcase }
-  end
-  
-  private
-  
-  def self.plugin_require_mutex
-    @mutex ||= Mutex.new
-  end
-  
-  def load_plugin(plugin_name, object_name, config, utils)
-    begin
-      unless (Object.const_defined? object_name)
-        file_name = "#{File.expand_path(File.dirname(__FILE__))}/cmock_generator_plugin_#{plugin_name.downcase}.rb"
-        require file_name
-      end
-      class_name = Object.const_get(object_name)
-      @plugins << class_name.new(config, utils)
-    rescue
-      file_name = "#{File.expand_path(File.dirname(__FILE__))}/cmock_generator_plugin_#{plugin_name.downcase}.rb"
-      raise "ERROR: CMock unable to load plugin '#{plugin_name}' '#{object_name}' #{file_name}"
-    end
-  end
-end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb
deleted file mode 100644
index c22db7aa9..000000000
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb
+++ /dev/null
@@ -1,75 +0,0 @@
-# ==========================================
-#   CMock Project - Automatic Mock Generation for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ========================================== 
-
-class CMockUnityHelperParser
-  
-  attr_accessor :c_types
-  
-  def initialize(config)
-    @config = config
-    @fallback = @config.plugins.include?(:array) ? 'UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY' : 'UNITY_TEST_ASSERT_EQUAL_MEMORY'
-    @c_types = map_C_types.merge(import_source)
-  end
-
-  def get_helper(ctype)
-    lookup = ctype.gsub(/(?:^|(\S?)(\s*)|(\W))const(?:$|(\s*)(\S)|(\W))/,'\1\3\5\6').strip.gsub(/\s+/,'_')
-    return [@c_types[lookup], ''] if (@c_types[lookup])
-    if (lookup =~ /\*$/)
-      lookup = lookup.gsub(/\*$/,'')
-      return [@c_types[lookup], '*'] if (@c_types[lookup])
-    else
-      lookup = lookup + '*'
-      return [@c_types[lookup], '&'] if (@c_types[lookup])
-    end
-    return ['UNITY_TEST_ASSERT_EQUAL_PTR', ''] if (ctype =~ /cmock_\w+_ptr\d+/)
-    raise("Don't know how to test #{ctype} and memory tests are disabled!") unless @config.memcmp_if_unknown
-    return (lookup =~ /\*$/) ? [@fallback, '&'] : [@fallback, '']
-  end
-  
-  private ###########################
-  
-  def map_C_types
-    c_types = {}
-    @config.treat_as.each_pair do |ctype, expecttype|
-      c_type = ctype.gsub(/\s+/,'_')
-      if (expecttype =~ /\*/)
-        c_types[c_type] = "UNITY_TEST_ASSERT_EQUAL_#{expecttype.gsub(/\*/,'')}_ARRAY"
-      else
-        c_types[c_type] = "UNITY_TEST_ASSERT_EQUAL_#{expecttype}"
-        c_types[c_type+'*'] ||= "UNITY_TEST_ASSERT_EQUAL_#{expecttype}_ARRAY"
-      end
-    end
-    c_types
-  end
-  
-  def import_source
-    source = @config.load_unity_helper
-    return {} if source.nil?
-    c_types = {}
-    source = source.gsub(/\/\/.*$/, '') #remove line comments
-    source = source.gsub(/\/\*.*?\*\//m, '') #remove block comments
-     
-    #scan for comparison helpers
-    match_regex = Regexp.new('^\s*#define\s+(UNITY_TEST_ASSERT_EQUAL_(\w+))\s*\(' + Array.new(4,'\s*\w+\s*').join(',') + '\)')
-    pairs = source.scan(match_regex).flatten.compact
-    (pairs.size/2).times do |i|
-      expect = pairs[i*2]
-      ctype = pairs[(i*2)+1]
-      c_types[ctype] = expect unless expect.include?("_ARRAY")
-    end
-      
-    #scan for array variants of those helpers
-    match_regex = Regexp.new('^\s*#define\s+(UNITY_TEST_ASSERT_EQUAL_(\w+_ARRAY))\s*\(' + Array.new(5,'\s*\w+\s*').join(',') + '\)')
-    pairs = source.scan(match_regex).flatten.compact
-    (pairs.size/2).times do |i|
-      expect = pairs[i*2]
-      ctype = pairs[(i*2)+1]
-      c_types[ctype.gsub('_ARRAY','*')] = expect
-    end
-    
-    c_types
-  end
-end
diff --git a/test/vendor/ceedling/vendor/cmock/release/build.info b/test/vendor/ceedling/vendor/cmock/release/build.info
deleted file mode 100644
index a62fe1172..000000000
--- a/test/vendor/ceedling/vendor/cmock/release/build.info
+++ /dev/null
@@ -1,2 +0,0 @@
-217
-
diff --git a/test/vendor/ceedling/vendor/cmock/release/version.info b/test/vendor/ceedling/vendor/cmock/release/version.info
deleted file mode 100644
index 1b6799f80..000000000
--- a/test/vendor/ceedling/vendor/cmock/release/version.info
+++ /dev/null
@@ -1,2 +0,0 @@
-2.4.6
-
diff --git a/test/vendor/ceedling/vendor/cmock/src/cmock.c b/test/vendor/ceedling/vendor/cmock/src/cmock.c
deleted file mode 100644
index 5e5cb6c72..000000000
--- a/test/vendor/ceedling/vendor/cmock/src/cmock.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/* ==========================================
-    CMock Project - Automatic Mock Generation for C
-    Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-========================================== */
-
-#include "cmock.h"
-
-//public constants to be used by mocks
-const char* CMockStringOutOfMemory = "CMock has run out of memory. Please allocate more.";
-const char* CMockStringCalledMore  = "Called more times than expected.";
-const char* CMockStringCalledLess  = "Called fewer times than expected.";
-const char* CMockStringCalledEarly = "Called earlier than expected.";
-const char* CMockStringCalledLate  = "Called later than expected.";
-const char* CMockStringCallOrder   = "Called out of order.";
-const char* CMockStringIgnPreExp   = "IgnoreArg called before Expect.";
-const char* CMockStringPtrPreExp   = "ReturnThruPtr called before Expect.";
-const char* CMockStringPtrIsNULL   = "Pointer is NULL.";
-const char* CMockStringExpNULL     = "Expected NULL.";
-const char* CMockStringMismatch    = "Function called with unexpected argument value.";
-
-//private variables
-#ifdef CMOCK_MEM_DYNAMIC
-static unsigned char*         CMock_Guts_Buffer = NULL;
-static CMOCK_MEM_INDEX_TYPE   CMock_Guts_BufferSize = CMOCK_MEM_ALIGN_SIZE;
-static CMOCK_MEM_INDEX_TYPE   CMock_Guts_FreePtr = CMOCK_MEM_ALIGN_SIZE;
-#else
-static unsigned char          CMock_Guts_Buffer[CMOCK_MEM_SIZE + CMOCK_MEM_ALIGN_SIZE];
-static CMOCK_MEM_INDEX_TYPE   CMock_Guts_BufferSize = CMOCK_MEM_SIZE + CMOCK_MEM_ALIGN_SIZE;
-static CMOCK_MEM_INDEX_TYPE   CMock_Guts_FreePtr = CMOCK_MEM_ALIGN_SIZE;
-#endif
-
-//-------------------------------------------------------
-// CMock_Guts_MemNew
-//-------------------------------------------------------
-CMOCK_MEM_INDEX_TYPE CMock_Guts_MemNew(CMOCK_MEM_INDEX_TYPE size)
-{
-  CMOCK_MEM_INDEX_TYPE index;
-
-  //verify arguments valid (we must be allocating space for at least 1 byte, and the existing chain must be in memory somewhere)
-  if (size < 1)
-    return CMOCK_GUTS_NONE;
-
-  //verify we have enough room
-  size = size + CMOCK_MEM_INDEX_SIZE;
-  if (size & CMOCK_MEM_ALIGN_MASK)
-    size = (size + CMOCK_MEM_ALIGN_MASK) & ~CMOCK_MEM_ALIGN_MASK;
-  if ((CMock_Guts_BufferSize - CMock_Guts_FreePtr) < size)
-  {
-#ifndef CMOCK_MEM_DYNAMIC
-    return CMOCK_GUTS_NONE; // nothing we can do; our static buffer is out of memory
-#else
-    // our dynamic buffer does not have enough room; request more via realloc()
-    CMOCK_MEM_INDEX_TYPE new_buffersize = CMock_Guts_BufferSize + CMOCK_MEM_SIZE + size;
-    unsigned char* new_buffer = realloc(CMock_Guts_Buffer, (size_t)new_buffersize);
-    if (new_buffer == NULL)
-      return CMOCK_GUTS_NONE; // realloc() failed; out of memory
-    CMock_Guts_Buffer = new_buffer;
-    CMock_Guts_BufferSize = new_buffersize;
-#endif
-  }
-
-  //determine where we're putting this new block, and init its pointer to be the end of the line
-  index = CMock_Guts_FreePtr + CMOCK_MEM_INDEX_SIZE;
-  *(CMOCK_MEM_INDEX_TYPE*)(&CMock_Guts_Buffer[CMock_Guts_FreePtr]) = CMOCK_GUTS_NONE;
-  CMock_Guts_FreePtr += size;
-
-  return index;
-}
-
-//-------------------------------------------------------
-// CMock_Guts_MemChain
-//-------------------------------------------------------
-CMOCK_MEM_INDEX_TYPE CMock_Guts_MemChain(CMOCK_MEM_INDEX_TYPE root_index, CMOCK_MEM_INDEX_TYPE obj_index)
-{
-  CMOCK_MEM_INDEX_TYPE index;
-  void* root;
-  void* obj;
-  void* next;
-
-  if (root_index == CMOCK_GUTS_NONE)
-  {
-    //if there is no root currently, we return this object as the root of the chain
-    return obj_index;
-  }
-  else
-  {
-    //reject illegal nodes
-    if ((root_index < CMOCK_MEM_ALIGN_SIZE) || (root_index >= CMock_Guts_FreePtr))
-    {
-      return CMOCK_GUTS_NONE;
-    }
-    if ((obj_index < CMOCK_MEM_ALIGN_SIZE) || (obj_index >= CMock_Guts_FreePtr))
-    {
-      return CMOCK_GUTS_NONE;
-    }
-
-    root = (void*)(&CMock_Guts_Buffer[root_index]);
-    obj  = (void*)(&CMock_Guts_Buffer[obj_index]);
-
-    //find the end of the existing chain and add us
-    next = root;
-    do {
-      index = *(CMOCK_MEM_INDEX_TYPE*)((CMOCK_MEM_PTR_AS_INT)next - CMOCK_MEM_INDEX_SIZE);
-      if (index >= CMock_Guts_FreePtr)
-        return CMOCK_GUTS_NONE;
-      if (index > 0)
-        next = (void*)(&CMock_Guts_Buffer[index]);
-    } while (index > 0);
-    *(CMOCK_MEM_INDEX_TYPE*)((CMOCK_MEM_PTR_AS_INT)next - CMOCK_MEM_INDEX_SIZE) = (CMOCK_MEM_INDEX_TYPE)((CMOCK_MEM_PTR_AS_INT)obj - (CMOCK_MEM_PTR_AS_INT)CMock_Guts_Buffer);
-    return root_index;
-  }
-}
-
-//-------------------------------------------------------
-// CMock_Guts_MemNext
-//-------------------------------------------------------
-CMOCK_MEM_INDEX_TYPE CMock_Guts_MemNext(CMOCK_MEM_INDEX_TYPE previous_item_index)
-{
-  CMOCK_MEM_INDEX_TYPE index;
-  void* previous_item;
-
-  //There is nothing "next" if the pointer isn't from our buffer
-  if ((previous_item_index < CMOCK_MEM_ALIGN_SIZE) || (previous_item_index  >= CMock_Guts_FreePtr))
-    return CMOCK_GUTS_NONE;
-  previous_item = (void*)(&CMock_Guts_Buffer[previous_item_index]);
-
-  //if the pointer is good, then use it to look up the next index
-  //(we know the first element always goes in zero, so NEXT must always be > 1)
-  index = *(CMOCK_MEM_INDEX_TYPE*)((CMOCK_MEM_PTR_AS_INT)previous_item - CMOCK_MEM_INDEX_SIZE);
-  if ((index > 1) && (index < CMock_Guts_FreePtr))
-    return index;
-  else
-    return CMOCK_GUTS_NONE;
-}
-
-//-------------------------------------------------------
-// CMock_Guts_MemEndOfChain
-//-------------------------------------------------------
-CMOCK_MEM_INDEX_TYPE CMock_Guts_MemEndOfChain(CMOCK_MEM_INDEX_TYPE root_index)
-{
-  CMOCK_MEM_INDEX_TYPE index = root_index;
-  CMOCK_MEM_INDEX_TYPE next_index;
-
-  for (next_index = root_index;
-       next_index != CMOCK_GUTS_NONE;
-       next_index = CMock_Guts_MemNext(index))
-  {
-    index = next_index;
-  }
-
-  return index;
-}
-
-//-------------------------------------------------------
-// CMock_GetAddressFor
-//-------------------------------------------------------
-void* CMock_Guts_GetAddressFor(CMOCK_MEM_INDEX_TYPE index)
-{
-  if ((index >= CMOCK_MEM_ALIGN_SIZE) && (index < CMock_Guts_FreePtr))
-  {
-    return (void*)(&CMock_Guts_Buffer[index]);
-  }
-  else
-  {
-    return NULL;
-  }
-}
-
-//-------------------------------------------------------
-// CMock_Guts_MemBytesCapacity
-//-------------------------------------------------------
-CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesCapacity(void)
-{
-  return (sizeof(CMock_Guts_Buffer) - CMOCK_MEM_ALIGN_SIZE);
-}
-
-//-------------------------------------------------------
-// CMock_Guts_MemBytesFree
-//-------------------------------------------------------
-CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesFree(void)
-{
-  return CMock_Guts_BufferSize - CMock_Guts_FreePtr;
-}
-
-//-------------------------------------------------------
-// CMock_Guts_MemBytesUsed
-//-------------------------------------------------------
-CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesUsed(void)
-{
-  return CMock_Guts_FreePtr - CMOCK_MEM_ALIGN_SIZE;
-}
-
-//-------------------------------------------------------
-// CMock_Guts_MemFreeAll
-//-------------------------------------------------------
-void CMock_Guts_MemFreeAll(void)
-{
-  CMock_Guts_FreePtr = CMOCK_MEM_ALIGN_SIZE; //skip the very beginning
-}
-
-//-------------------------------------------------------
-// CMock_Guts_MemFreeFinal
-//-------------------------------------------------------
-void CMock_Guts_MemFreeFinal(void)
-{
-  CMock_Guts_FreePtr = CMOCK_MEM_ALIGN_SIZE;
-#ifdef CMOCK_MEM_DYNAMIC
-  if (CMock_Guts_Buffer)
-  {
-    free(CMock_Guts_Buffer);
-    CMock_Guts_Buffer = NULL;
-  }
-#endif
-}
-
diff --git a/test/vendor/ceedling/vendor/cmock/src/cmock.h b/test/vendor/ceedling/vendor/cmock/src/cmock.h
deleted file mode 100644
index e96546dab..000000000
--- a/test/vendor/ceedling/vendor/cmock/src/cmock.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* ==========================================
-    CMock Project - Automatic Mock Generation for C
-    Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-========================================== */
-
-#ifndef CMOCK_FRAMEWORK_H
-#define CMOCK_FRAMEWORK_H
-
-#include "cmock_internals.h"
-
-#define CMOCK_VERSION_MAJOR    2
-#define CMOCK_VERSION_MINOR    5
-#define CMOCK_VERSION_BUILD    0
-#define CMOCK_VERSION          ((CMOCK_VERSION_MAJOR << 16) | (CMOCK_VERSION_MINOR << 8) | CMOCK_VERSION_BUILD)
-
-//should be big enough to index full range of CMOCK_MEM_MAX
-#ifndef CMOCK_MEM_INDEX_TYPE
-#define CMOCK_MEM_INDEX_TYPE  unsigned int
-#endif
-
-#define CMOCK_GUTS_NONE   (0)
-
-//-------------------------------------------------------
-// Memory API
-//-------------------------------------------------------
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemNew(CMOCK_MEM_INDEX_TYPE size);
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemChain(CMOCK_MEM_INDEX_TYPE root_index, CMOCK_MEM_INDEX_TYPE obj_index);
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemNext(CMOCK_MEM_INDEX_TYPE previous_item_index);
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemEndOfChain(CMOCK_MEM_INDEX_TYPE root_index);
-
-void*                 CMock_Guts_GetAddressFor(CMOCK_MEM_INDEX_TYPE index);
-
-CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesCapacity(void);
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemBytesFree(void);
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemBytesUsed(void);
-void                  CMock_Guts_MemFreeAll(void);
-void                  CMock_Guts_MemFreeFinal(void);
-
-#endif //CMOCK_FRAMEWORK
diff --git a/test/vendor/ceedling/vendor/cmock/src/cmock_internals.h b/test/vendor/ceedling/vendor/cmock/src/cmock_internals.h
deleted file mode 100644
index ae2e4962f..000000000
--- a/test/vendor/ceedling/vendor/cmock/src/cmock_internals.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* ==========================================
-    CMock Project - Automatic Mock Generation for C
-    Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-========================================== */
-
-#ifndef CMOCK_FRAMEWORK_INTERNALS_H
-#define CMOCK_FRAMEWORK_INTERNALS_H
-
-#include "unity.h"
-
-//These are constants that the generated mocks have access to
-extern const char* CMockStringOutOfMemory;
-extern const char* CMockStringCalledMore;
-extern const char* CMockStringCalledLess;
-extern const char* CMockStringCalledEarly;
-extern const char* CMockStringCalledLate;
-extern const char* CMockStringCallOrder;
-extern const char* CMockStringIgnPreExp;
-extern const char* CMockStringPtrPreExp;
-extern const char* CMockStringPtrIsNULL;
-extern const char* CMockStringExpNULL;
-extern const char* CMockStringMismatch;
-
-//define CMOCK_MEM_DYNAMIC to grab memory as needed with malloc
-//when you do that, CMOCK_MEM_SIZE is used for incremental size instead of total
-#ifdef CMOCK_MEM_STATIC
-#undef CMOCK_MEM_DYNAMIC
-#endif
-
-#ifdef CMOCK_MEM_DYNAMIC
-#include <stdlib.h>
-#endif
-
-//this is used internally during pointer arithmetic. make sure this type is the same size as the target's pointer type
-#ifndef CMOCK_MEM_PTR_AS_INT
-#ifdef UNITY_POINTER_WIDTH
-#ifdef UNITY_INT_WIDTH
-#if UNITY_POINTER_WIDTH == UNITY_INT_WIDTH
-#define CMOCK_MEM_PTR_AS_INT unsigned int
-#endif
-#endif
-#endif
-#endif
-
-#ifndef CMOCK_MEM_PTR_AS_INT
-#ifdef UNITY_POINTER_WIDTH
-#ifdef UNITY_LONG_WIDTH
-#if UNITY_POINTER_WIDTH == UNITY_LONG_WIDTH
-#define CMOCK_MEM_PTR_AS_INT unsigned long
-#endif
-#if UNITY_POINTER_WIDTH > UNITY_LONG_WIDTH
-#define CMOCK_MEM_PTR_AS_INT unsigned long long
-#endif
-#endif
-#endif
-#endif
-
-#ifndef CMOCK_MEM_PTR_AS_INT
-#define CMOCK_MEM_PTR_AS_INT unsigned long
-#endif
-
-//0 for no alignment, 1 for 16-bit, 2 for 32-bit, 3 for 64-bit
-#ifndef CMOCK_MEM_ALIGN
-  #ifdef UNITY_LONG_WIDTH
-    #if (UNITY_LONG_WIDTH == 16)
-      #define CMOCK_MEM_ALIGN (1)
-    #elif (UNITY_LONG_WIDTH == 32)
-      #define CMOCK_MEM_ALIGN (2)
-    #elif (UNITY_LONG_WIDTH == 64)
-      #define CMOCK_MEM_ALIGN (3)
-    #else
-      #define CMOCK_MEM_ALIGN (2)
-    #endif
-  #else
-    #define CMOCK_MEM_ALIGN (2)
-  #endif
-#endif
-
-//amount of memory to allow cmock to use in its internal heap
-#ifndef CMOCK_MEM_SIZE
-#define CMOCK_MEM_SIZE (32768)
-#endif
-
-//automatically calculated defs for easier reading
-#define CMOCK_MEM_ALIGN_SIZE  (CMOCK_MEM_INDEX_TYPE)(1u << CMOCK_MEM_ALIGN)
-#define CMOCK_MEM_ALIGN_MASK  (CMOCK_MEM_INDEX_TYPE)(CMOCK_MEM_ALIGN_SIZE - 1)
-#define CMOCK_MEM_INDEX_SIZE  (CMOCK_MEM_INDEX_TYPE)(CMOCK_MEM_PTR_AS_INT)((sizeof(CMOCK_MEM_INDEX_TYPE) > CMOCK_MEM_ALIGN_SIZE) ? sizeof(CMOCK_MEM_INDEX_TYPE) : CMOCK_MEM_ALIGN_SIZE)
-
-
-#endif //CMOCK_FRAMEWORK_INTERNALS
diff --git a/test/vendor/ceedling/vendor/cmock/src/meson.build b/test/vendor/ceedling/vendor/cmock/src/meson.build
deleted file mode 100644
index e375e81a1..000000000
--- a/test/vendor/ceedling/vendor/cmock/src/meson.build
+++ /dev/null
@@ -1,17 +0,0 @@
-###################################################################################
-#                                                                                 #
-# NAME: meson.build                                                               #
-#                                                                                 #
-# AUTHOR: Mike Karlesky, Mark VanderVoord, Greg Williams.                         #
-# WRITTEN BY: Michael Brockus.                                                    #
-#                                                                                 #
-# License: MIT                                                                    #
-#                                                                                 #
-###################################################################################
-
-cmock_dir = include_directories('.')
-
-cmock_lib = static_library(meson.project_name(), 
-    sources: ['cmock.c'],
-    dependencies: [unity_dep],
-    include_directories: cmock_dir)
diff --git a/test/vendor/ceedling/vendor/deep_merge/lib/deep_merge.rb b/test/vendor/ceedling/vendor/deep_merge/lib/deep_merge.rb
deleted file mode 100644
index 4c4b7610b..000000000
--- a/test/vendor/ceedling/vendor/deep_merge/lib/deep_merge.rb
+++ /dev/null
@@ -1,211 +0,0 @@
-module DeepMerge
-
-  MAJOR_VERSION = 0
-  MINOR_VERSION = 1
-  FIX_VERSION = 0
-  VERSION = "#{MAJOR_VERSION}.#{MINOR_VERSION}.#{FIX_VERSION}"
-
-  class InvalidParameter < StandardError; end
-  
-  DEFAULT_FIELD_KNOCKOUT_PREFIX = '--'
-
-  module DeepMergeHash
-    # ko_hash_merge! will merge and knockout elements prefixed with DEFAULT_FIELD_KNOCKOUT_PREFIX
-    def ko_deep_merge!(source, options = {})
-      default_opts = {:knockout_prefix => "--", :preserve_unmergeables => false}
-      DeepMerge::deep_merge!(source, self, default_opts.merge(options))
-    end
-
-    # deep_merge! will merge and overwrite any unmergeables in destination hash
-    def deep_merge!(source, options = {})
-      default_opts = {:preserve_unmergeables => false}
-      DeepMerge::deep_merge!(source, self, default_opts.merge(options))
-    end
-
-    # deep_merge will merge and skip any unmergeables in destination hash
-    def deep_merge(source, options = {})
-      default_opts = {:preserve_unmergeables => true}
-      DeepMerge::deep_merge!(source, self, default_opts.merge(options))
-    end
-
-  end # DeepMergeHashExt
-  
-  # Deep Merge core documentation.
-  # deep_merge! method permits merging of arbitrary child elements. The two top level
-  # elements must be hashes. These hashes can contain unlimited (to stack limit) levels
-  # of child elements. These child elements to not have to be of the same types.
-  # Where child elements are of the same type, deep_merge will attempt to merge them together.
-  # Where child elements are not of the same type, deep_merge will skip or optionally overwrite
-  # the destination element with the contents of the source element at that level.
-  # So if you have two hashes like this:
-  #   source = {:x => [1,2,3], :y => 2}
-  #   dest =   {:x => [4,5,'6'], :y => [7,8,9]}
-  #   dest.deep_merge!(source)
-  #   Results: {:x => [1,2,3,4,5,'6'], :y => 2}
-  # By default, "deep_merge!" will overwrite any unmergeables and merge everything else.
-  # To avoid this, use "deep_merge" (no bang/exclamation mark)
-  # 
-  # Options:
-  #   Options are specified in the last parameter passed, which should be in hash format:
-  #   hash.deep_merge!({:x => [1,2]}, {:knockout_prefix => '--'})
-  #   :preserve_unmergeables  DEFAULT: false
-  #      Set to true to skip any unmergeable elements from source
-  #   :knockout_prefix        DEFAULT: nil
-  #      Set to string value to signify prefix which deletes elements from existing element
-  #   :sort_merged_arrays     DEFAULT: false
-  #      Set to true to sort all arrays that are merged together
-  #   :unpack_arrays          DEFAULT: nil
-  #      Set to string value to run "Array::join" then "String::split" against all arrays
-  #   :merge_debug            DEFAULT: false
-  #      Set to true to get console output of merge process for debugging
-  #
-  # Selected Options Details:
-  # :knockout_prefix => The purpose of this is to provide a way to remove elements 
-  #   from existing Hash by specifying them in a special way in incoming hash
-  #    source = {:x => ['--1', '2']}
-  #    dest   = {:x => ['1', '3']}
-  #    dest.ko_deep_merge!(source)
-  #    Results: {:x => ['2','3']}
-  #   Additionally, if the knockout_prefix is passed alone as a string, it will cause
-  #   the entire element to be removed:
-  #    source = {:x => '--'}
-  #    dest   = {:x => [1,2,3]}
-  #    dest.ko_deep_merge!(source)
-  #    Results: {:x => ""}
-  # :unpack_arrays => The purpose of this is to permit compound elements to be passed
-  #   in as strings and to be converted into discrete array elements
-  #   irsource = {:x => ['1,2,3', '4']}
-  #   dest   = {:x => ['5','6','7,8']}
-  #   dest.deep_merge!(source, {:unpack_arrays => ','})
-  #   Results: {:x => ['1','2','3','4','5','6','7','8'}
-  #   Why: If receiving data from an HTML form, this makes it easy for a checkbox 
-  #    to pass multiple values from within a single HTML element
-  # 
-  # There are many tests for this library - and you can learn more about the features
-  # and usages of deep_merge! by just browsing the test examples
-  def DeepMerge.deep_merge!(source, dest, options = {})
-    # turn on this line for stdout debugging text
-    merge_debug = options[:merge_debug] || false
-    overwrite_unmergeable = !options[:preserve_unmergeables]
-    knockout_prefix = options[:knockout_prefix] || nil
-    if knockout_prefix == "" then raise InvalidParameter, "knockout_prefix cannot be an empty string in deep_merge!"; end
-    if knockout_prefix && !overwrite_unmergeable then raise InvalidParameter, "overwrite_unmergeable must be true if knockout_prefix is specified in deep_merge!"; end
-    # if present: we will split and join arrays on this char before merging
-    array_split_char = options[:unpack_arrays] || false
-    # request that we sort together any arrays when they are merged
-    sort_merged_arrays = options[:sort_merged_arrays] || false
-    di = options[:debug_indent] || ''
-    # do nothing if source is nil
-    if source.nil? || (source.respond_to?(:blank?) && source.blank?) then return dest; end
-    # if dest doesn't exist, then simply copy source to it
-    if dest.nil? && overwrite_unmergeable then dest = source; return dest; end
-
-    puts "#{di}Source class: #{source.class.inspect} :: Dest class: #{dest.class.inspect}" if merge_debug
-    if source.kind_of?(Hash)
-      puts "#{di}Hashes: #{source.inspect} :: #{dest.inspect}" if merge_debug
-      source.each do |src_key, src_value|
-        if dest.kind_of?(Hash)
-          puts "#{di} looping: #{src_key.inspect} => #{src_value.inspect} :: #{dest.inspect}" if merge_debug
-          if not dest[src_key].nil?
-            puts "#{di} ==>merging: #{src_key.inspect} => #{src_value.inspect} :: #{dest[src_key].inspect}" if merge_debug
-            dest[src_key] = deep_merge!(src_value, dest[src_key], options.merge(:debug_indent => di + '  '))
-          else # dest[src_key] doesn't exist so we want to create and overwrite it (but we do this via deep_merge!)
-            puts "#{di} ==>merging over: #{src_key.inspect} => #{src_value.inspect}" if merge_debug
-            # note: we rescue here b/c some classes respond to "dup" but don't implement it (Numeric, TrueClass, FalseClass, NilClass among maybe others)
-            begin
-              src_dup = src_value.dup # we dup src_value if possible because we're going to merge into it (since dest is empty)
-            rescue TypeError
-              src_dup = src_value
-            end
-            dest[src_key] = deep_merge!(src_value, src_dup, options.merge(:debug_indent => di + '  '))
-          end
-        else # dest isn't a hash, so we overwrite it completely (if permitted)
-          if overwrite_unmergeable
-            puts "#{di}  overwriting dest: #{src_key.inspect} => #{src_value.inspect} -over->  #{dest.inspect}" if merge_debug
-            dest = overwrite_unmergeables(source, dest, options)
-          end
-        end
-      end
-    elsif source.kind_of?(Array)
-      puts "#{di}Arrays: #{source.inspect} :: #{dest.inspect}" if merge_debug
-      # if we are instructed, join/split any source arrays before processing
-      if array_split_char
-        puts "#{di} split/join on source: #{source.inspect}" if merge_debug
-        source = source.join(array_split_char).split(array_split_char)
-        if dest.kind_of?(Array) then dest = dest.join(array_split_char).split(array_split_char); end
-      end
-      # if there's a naked knockout_prefix in source, that means we are to truncate dest
-      if source.index(knockout_prefix) then dest = clear_or_nil(dest); source.delete(knockout_prefix); end
-      if dest.kind_of?(Array)
-        if knockout_prefix
-          print "#{di} knocking out: " if merge_debug
-          # remove knockout prefix items from both source and dest
-          source.delete_if do |ko_item|
-            retval = false
-            item = ko_item.respond_to?(:gsub) ? ko_item.gsub(%r{^#{knockout_prefix}}, "") : ko_item
-            if item != ko_item
-              print "#{ko_item} - " if merge_debug
-              dest.delete(item)
-              dest.delete(ko_item)
-              retval = true
-            end
-            retval
-          end
-          puts if merge_debug
-        end
-        puts "#{di} merging arrays: #{source.inspect} :: #{dest.inspect}" if merge_debug
-        dest = dest | source
-        if sort_merged_arrays then dest.sort!; end
-      elsif overwrite_unmergeable
-        puts "#{di} overwriting dest: #{source.inspect} -over-> #{dest.inspect}" if merge_debug
-        dest = overwrite_unmergeables(source, dest, options)
-      end
-    else # src_hash is not an array or hash, so we'll have to overwrite dest
-      puts "#{di}Others: #{source.inspect} :: #{dest.inspect}" if merge_debug
-      dest = overwrite_unmergeables(source, dest, options)
-    end
-    puts "#{di}Returning #{dest.inspect}" if merge_debug
-    dest
-  end # deep_merge!
-
-  # allows deep_merge! to uniformly handle overwriting of unmergeable entities
-  def DeepMerge::overwrite_unmergeables(source, dest, options)
-    merge_debug = options[:merge_debug] || false
-    overwrite_unmergeable = !options[:preserve_unmergeables]
-    knockout_prefix = options[:knockout_prefix] || false
-    di = options[:debug_indent] || ''
-    if knockout_prefix && overwrite_unmergeable
-      if source.kind_of?(String) # remove knockout string from source before overwriting dest
-        src_tmp = source.gsub(%r{^#{knockout_prefix}},"")
-      elsif source.kind_of?(Array) # remove all knockout elements before overwriting dest
-        src_tmp = source.delete_if {|ko_item| ko_item.kind_of?(String) && ko_item.match(%r{^#{knockout_prefix}}) }
-      else
-        src_tmp = source
-      end
-      if src_tmp == source # if we didn't find a knockout_prefix then we just overwrite dest
-        puts "#{di}#{src_tmp.inspect} -over-> #{dest.inspect}" if merge_debug
-        dest = src_tmp
-      else # if we do find a knockout_prefix, then we just delete dest
-        puts "#{di}\"\" -over-> #{dest.inspect}" if merge_debug
-        dest = ""
-      end
-    elsif overwrite_unmergeable
-      dest = source
-    end
-    dest
-  end
-
-  def DeepMerge::clear_or_nil(obj)
-    if obj.respond_to?(:clear)
-      obj.clear
-    else
-      obj = nil
-    end
-    obj
-  end
-
-end # module DeepMerge
-
-class Hash
-  include DeepMerge::DeepMergeHash
-end
diff --git a/test/vendor/ceedling/vendor/diy/lib/diy.rb b/test/vendor/ceedling/vendor/diy/lib/diy.rb
deleted file mode 100644
index 581afc7e6..000000000
--- a/test/vendor/ceedling/vendor/diy/lib/diy.rb
+++ /dev/null
@@ -1,403 +0,0 @@
-require 'diy/factory.rb'
-require 'yaml'
-require 'set'
-
-module DIY #:nodoc:#
-  VERSION = '1.1.2'
-  class Context
-
-    class << self
-      # Enable / disable automatic requiring of libraries. Default: true
-      attr_accessor :auto_require
-    end
-    @auto_require = true
-
-    # Accepts a Hash defining the object context (usually loaded from objects.yml), and an additional
-    # Hash containing objects to inject into the context.
-    def initialize(context_hash, extra_inputs={})
-      raise "Nil context hash" unless context_hash
-      raise "Need a hash" unless context_hash.kind_of?(Hash)
-      [ "[]", "keys" ].each do |mname|
-        unless extra_inputs.respond_to?(mname) 
-          raise "Extra inputs must respond to hash-like [] operator and methods #keys and #each" 
-        end
-      end
-
-      # store extra inputs
-      if extra_inputs.kind_of?(Hash)
-        @extra_inputs= {}
-        extra_inputs.each { |k,v| @extra_inputs[k.to_s] = v } # smooth out the names
-      else
-        @extra_inputs = extra_inputs
-      end
-
-      collect_object_and_subcontext_defs context_hash
-
-      # init the cache
-      @cache = {}
-      @cache['this_context'] = self
-    end
-   
-
-    # Convenience: create a new DIY::Context by loading from a String (or open file handle.)
-    def self.from_yaml(io_or_string, extra_inputs={})
-      raise "nil input to YAML" unless io_or_string
-      Context.new(YAML.load(io_or_string), extra_inputs)
-    end
-
-    # Convenience: create a new DIY::Context by loading from the named file.
-    def self.from_file(fname, extra_inputs={})
-      raise "nil file name" unless fname
-      self.from_yaml(File.read(fname), extra_inputs)
-    end
-
-    # Return a reference to the object named.  If necessary, the object will 
-    # be instantiated on first use.  If the object is non-singleton, a new
-    # object will be produced each time.
-    def get_object(obj_name)
-      key = obj_name.to_s
-      obj = @cache[key]
-      unless obj
-        if extra_inputs_has(key)
-          obj = @extra_inputs[key]
-        else
-          case @defs[key]
-          when MethodDef
-            obj = construct_method(key)
-          when FactoryDef
-            obj = construct_factory(key)
-            @cache[key] = obj
-          else
-            obj = construct_object(key)
-            @cache[key] = obj if @defs[key].singleton?
-          end
-        end
-      end
-      obj
-    end
-    alias :[] :get_object
-
-    # Inject a named object into the Context.  This must be done before the Context has instantiated the 
-    # object in question.
-    def set_object(obj_name,obj)
-      key = obj_name.to_s
-      raise "object '#{key}' already exists in context" if @cache.keys.include?(key)
-      @cache[key] = obj
-    end
-    alias :[]= :set_object
-
-    # Provide a listing of object names
-    def keys
-      (@defs.keys.to_set + @extra_inputs.keys.to_set).to_a
-    end
-
-    # Instantiate and yield the named subcontext
-    def within(sub_context_name)
-      # Find the subcontext definitaion:
-      context_def = @sub_context_defs[sub_context_name.to_s]
-      raise "No sub-context named #{sub_context_name}" unless context_def
-      # Instantiate a new context using self as parent:
-      context = Context.new( context_def, self )
-
-      yield context
-    end
-
-    # Returns true if the context contains an object with the given name
-    def contains_object(obj_name)
-      key = obj_name.to_s
-      @defs.keys.member?(key) or extra_inputs_has(key)
-    end
-
-    # Every top level object in the Context is instantiated.  This is especially useful for 
-    # systems that have "floating observers"... objects that are never directly accessed, who
-    # would thus never be instantiated by coincedence.  This does not build any subcontexts 
-    # that may exist.
-    def build_everything
-      @defs.keys.each { |k| self[k] }
-    end
-    alias :build_all :build_everything
-    alias :preinstantiate_singletons :build_everything
-
-    private
-
-    def collect_object_and_subcontext_defs(context_hash)
-      @defs = {}
-      @sub_context_defs = {}
-      get_defs_from context_hash
-    end
-
-    def get_defs_from(hash, namespace=nil)
-      hash.each do |name,info|
-        # we modify the info hash below so it's important to have a new
-        # instance to play with
-        info = info.dup if info
-        
-        # see if we are building a factory
-        if info and info.has_key?('builds')
-          unless info.has_key?('auto_require')
-            info['auto_require'] = self.class.auto_require
-          end
-
-          if namespace
-            info['builds'] = namespace.build_classname(info['builds'])
-          end
-          @defs[name] = FactoryDef.new({:name => name,
-                                       :target => info['builds'],
-                                       :library => info['library'],
-                                       :auto_require => info['auto_require']})
-          next
-        end
-
-        name = name.to_s
-        case name
-        when /^\+/ 
-          # subcontext
-          @sub_context_defs[name.gsub(/^\+/,'')] = info
-          
-        when /^using_namespace/
-          # namespace: use a module(s) prefix for the classname of contained object defs
-          # NOTE: namespacing is NOT scope... it's just a convenient way to setup class names for a group of objects.
-          get_defs_from info, parse_namespace(name)
-        when /^method\s/
-          key_name = name.gsub(/^method\s/, "")
-          @defs[key_name] = MethodDef.new(:name => key_name, 
-                                      :object => info['object'], 
-                                      :method => info['method'],
-                                      :attach => info['attach'])
-        else 
-          # Normal object def
-          info ||= {}
-          if extra_inputs_has(name)
-            raise ConstructionError.new(name, "Object definition conflicts with parent context")
-          end
-          unless info.has_key?('auto_require')
-            info['auto_require'] = self.class.auto_require
-          end
-          if namespace 
-            if info['class']
-              info['class'] = namespace.build_classname(info['class'])
-            else
-              info['class'] = namespace.build_classname(name)
-            end
-          end
-            
-          @defs[name] = ObjectDef.new(:name => name, :info => info)
-
-        end
-      end
-    end
-
-    def construct_method(key)
-      method_definition = @defs[key]
-      object = get_object(method_definition.object)
-      method = object.method(method_definition.method)
-      
-      unless method_definition.attach.nil?
-        instance_var_name = "@__diy_#{method_definition.object}"
-        
-        method_definition.attach.each do |object_key|
-          get_object(object_key).instance_eval do
-            instance_variable_set(instance_var_name, object)
-            eval %|def #{key}(*args)
-              #{instance_var_name}.#{method_definition.method}(*args)
-            end|
-          end
-        end      
-      end
-      
-      return method
-    rescue Exception => oops
-      build_and_raise_construction_error(key, oops)
-    end
-    
-    def construct_object(key)
-      # Find the object definition
-      obj_def = @defs[key]
-      raise "No object definition for '#{key}'" unless obj_def
-      # If object def mentions a library, load it
-      require obj_def.library if obj_def.library
-
-      # Resolve all components for the object
-      arg_hash = {}
-      obj_def.components.each do |name,value|
-        case value
-        when Lookup
-          arg_hash[name.to_sym] = get_object(value.name)
-        when StringValue
-          arg_hash[name.to_sym] = value.literal_value
-        else
-          raise "Cannot cope with component definition '#{value.inspect}'"
-        end
-      end
-      # Get a reference to the class for the object
-      big_c = get_class_for_name_with_module_delimeters(obj_def.class_name)
-      # Make and return the instance
-      if obj_def.use_class_directly?
-        return big_c
-      elsif arg_hash.keys.size > 0
-        return big_c.new(arg_hash)
-      else
-        return big_c.new
-      end
-    rescue Exception => oops
-      build_and_raise_construction_error(key, oops)
-    end
-    
-    def build_and_raise_construction_error(key, oops)
-      cerr = ConstructionError.new(key,oops)
-      cerr.set_backtrace(oops.backtrace)
-      raise cerr
-    end
-      
-    def get_class_for_name_with_module_delimeters(class_name)
-      class_name.split(/::/).inject(Object) do |mod,const_name| mod.const_get(const_name) end
-    end
-
-    def extra_inputs_has(key)
-      if key.nil? or key.strip == ''
-        raise ArgumentError.new("Cannot lookup objects with nil keys")
-      end
-      @extra_inputs.keys.member?(key) or @extra_inputs.keys.member?(key.to_sym)
-    end
-
-    def parse_namespace(str)
-      Namespace.new(str)
-    end
-  end
-  
-  class Namespace #:nodoc:#
-    def initialize(str)
-      # 'using_namespace Animal Reptile'
-      parts = str.split(/\s+/)
-      raise "Namespace definitions must begin with 'using_namespace'" unless parts[0] == 'using_namespace'
-      parts.shift
-
-      if parts.length > 0 and parts[0] =~ /::/
-        parts = parts[0].split(/::/)
-      end
-
-      raise NamespaceError, "Namespace needs to indicate a module" if parts.empty?
-
-      @module_nest = parts
-    end
-
-    def build_classname(name)
-      [ @module_nest, Infl.camelize(name) ].flatten.join("::")
-    end
-  end
-
-  class Lookup #:nodoc:
-    attr_reader :name
-    def initialize(obj_name)
-      @name = obj_name
-    end
-  end
-  
-  class MethodDef #:nodoc:
-    attr_accessor :name, :object, :method, :attach
-    
-    def initialize(opts)
-      @name, @object, @method, @attach = opts[:name], opts[:object], opts[:method], opts[:attach]
-    end
-  end
-  
-  class ObjectDef #:nodoc:
-    attr_accessor :name, :class_name, :library, :components
-    def initialize(opts)
-      name = opts[:name]
-      raise "Can't make an ObjectDef without a name" if name.nil?
-
-      info = opts[:info] || {}
-      info = info.clone
-
-      @components = {}
-
-      # Object name
-      @name = name
-
-      # Class name
-      @class_name = info.delete 'class'
-      @class_name ||= info.delete 'type'
-      @class_name ||= Infl.camelize(@name)
-
-      # Auto Require
-      @auto_require = info.delete 'auto_require'
-
-      # Library
-      @library = info.delete 'library'
-      @library ||= info.delete 'lib'
-      @library ||= Infl.underscore(@class_name) if @auto_require
-
-      # Use Class Directly
-      @use_class_directly = info.delete 'use_class_directly'
-      
-      # Auto-compose
-      compose = info.delete 'compose'
-      if compose
-        case compose
-        when Array
-          auto_names = compose.map { |x| x.to_s }
-        when String
-          auto_names = compose.split(',').map { |x| x.to_s.strip }
-        when Symbol
-          auto_names = [ compose.to_s ]
-        else
-          raise "Cannot auto compose object #{@name}, bad 'compose' format: #{compose.inspect}"
-        end
-      end
-      auto_names ||= []
-      auto_names.each do |cname|
-        @components[cname] = Lookup.new(cname)
-      end
-
-      # Singleton status
-      if info['singleton'].nil?
-        @singleton = true
-      else
-        @singleton = info['singleton']
-      end
-      info.delete 'singleton'
-
-      # Remaining keys
-      info.each do |key,val|
-        @components[key.to_s] = Lookup.new(val.to_s)
-      end
-
-    end
-
-    def singleton?
-      @singleton
-    end
-
-    def use_class_directly?
-      @use_class_directly == true
-    end
-
-  end
-
-  class ConstructionError < RuntimeError #:nodoc:#
-    def initialize(object_name, cause=nil)
-      object_name = object_name
-      cause = cause
-      m = "Failed to construct '#{object_name}'"
-      if cause 
-        m << "\n  ...caused by:\n  >>> #{cause}"
-      end
-      super m
-    end
-  end
-
-  class NamespaceError < RuntimeError #:nodoc:#
-  end 
-
-  module Infl #:nodoc:#
-    # Ganked this from Inflector:
-    def self.camelize(lower_case_and_underscored_word) 
-      lower_case_and_underscored_word.to_s.gsub(/\/(.?)/) { "::" + $1.upcase }.gsub(/(^|_)(.)/) { $2.upcase }
-    end
-    # Ganked this from Inflector:
-    def self.underscore(camel_cased_word)
-      camel_cased_word.to_s.gsub(/::/, '/').gsub(/([A-Z]+)([A-Z])/,'\1_\2').gsub(/([a-z\d])([A-Z])/,'\1_\2').downcase
-    end
-  end
-end
diff --git a/test/vendor/ceedling/vendor/diy/lib/diy/factory.rb b/test/vendor/ceedling/vendor/diy/lib/diy/factory.rb
deleted file mode 100644
index d2566c5d1..000000000
--- a/test/vendor/ceedling/vendor/diy/lib/diy/factory.rb
+++ /dev/null
@@ -1,36 +0,0 @@
-module DIY #:nodoc:#
-  class FactoryDef #:nodoc:
-    attr_accessor :name, :target, :class_name, :library
-    
-    def initialize(opts)
-      @name, @target, @library, @auto_require =
-        opts[:name], opts[:target], opts[:library], opts[:auto_require]
-
-			@class_name = Infl.camelize(@target)
-			@library ||= Infl.underscore(@class_name) if @auto_require
-    end
-  end
-  
-	class Context
-    def construct_factory(key)
-      factory_def = @defs[key]
-#      puts "requiring #{factory_def.library}"
-      require factory_def.library	if factory_def.library
-
-			big_c = get_class_for_name_with_module_delimeters(factory_def.class_name)
-
-      FactoryFactory.new(big_c)
-    end
-  end
-
-  class FactoryFactory
-    def initialize(clazz)
-      @class_to_create = clazz
-    end
-
-    def create(*args)
-      @class_to_create.new(*args)
-    end
-  end
-end
-
diff --git a/test/vendor/ceedling/vendor/unity/auto/colour_prompt.rb b/test/vendor/ceedling/vendor/unity/auto/colour_prompt.rb
deleted file mode 100644
index 85cbfd80c..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/colour_prompt.rb
+++ /dev/null
@@ -1,119 +0,0 @@
-# ==========================================
-#   Unity Project - A Test Framework for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-if RUBY_PLATFORM =~ /(win|w)32$/
-  begin
-    require 'Win32API'
-  rescue LoadError
-    puts 'ERROR! "Win32API" library not found'
-    puts '"Win32API" is required for colour on a windows machine'
-    puts '  try => "gem install Win32API" on the command line'
-    puts
-  end
-  # puts
-  # puts 'Windows Environment Detected...'
-  # puts 'Win32API Library Found.'
-  # puts
-end
-
-class ColourCommandLine
-  def initialize
-    return unless RUBY_PLATFORM =~ /(win|w)32$/
-
-    get_std_handle = Win32API.new('kernel32', 'GetStdHandle', ['L'], 'L')
-    @set_console_txt_attrb =
-      Win32API.new('kernel32', 'SetConsoleTextAttribute', %w[L N], 'I')
-    @hout = get_std_handle.call(-11)
-  end
-
-  def change_to(new_colour)
-    if RUBY_PLATFORM =~ /(win|w)32$/
-      @set_console_txt_attrb.call(@hout, win32_colour(new_colour))
-    else
-      "\033[30;#{posix_colour(new_colour)};22m"
-    end
-  end
-
-  def win32_colour(colour)
-    case colour
-    when :black then 0
-    when :dark_blue then 1
-    when :dark_green then 2
-    when :dark_cyan then 3
-    when :dark_red then 4
-    when :dark_purple then 5
-    when :dark_yellow, :narrative then 6
-    when :default_white, :default, :dark_white then 7
-    when :silver then 8
-    when :blue then 9
-    when :green, :success then 10
-    when :cyan, :output then 11
-    when :red, :failure then 12
-    when :purple then 13
-    when :yellow then 14
-    when :white then 15
-    else
-      0
-    end
-  end
-
-  def posix_colour(colour)
-    # ANSI Escape Codes - Foreground colors
-    # | Code | Color                     |
-    # | 39   | Default foreground color  |
-    # | 30   | Black                     |
-    # | 31   | Red                       |
-    # | 32   | Green                     |
-    # | 33   | Yellow                    |
-    # | 34   | Blue                      |
-    # | 35   | Magenta                   |
-    # | 36   | Cyan                      |
-    # | 37   | Light gray                |
-    # | 90   | Dark gray                 |
-    # | 91   | Light red                 |
-    # | 92   | Light green               |
-    # | 93   | Light yellow              |
-    # | 94   | Light blue                |
-    # | 95   | Light magenta             |
-    # | 96   | Light cyan                |
-    # | 97   | White                     |
-
-    case colour
-    when :black then 30
-    when :red, :failure then 31
-    when :green, :success then 32
-    when :yellow then 33
-    when :blue, :narrative then 34
-    when :purple, :magenta then 35
-    when :cyan, :output then 36
-    when :white, :default_white then 37
-    when :default then 39
-    else
-      39
-    end
-  end
-
-  def out_c(mode, colour, str)
-    case RUBY_PLATFORM
-    when /(win|w)32$/
-      change_to(colour)
-      $stdout.puts str if mode == :puts
-      $stdout.print str if mode == :print
-      change_to(:default_white)
-    else
-      $stdout.puts("#{change_to(colour)}#{str}\033[0m") if mode == :puts
-      $stdout.print("#{change_to(colour)}#{str}\033[0m") if mode == :print
-    end
-  end
-end
-
-def colour_puts(role, str)
-  ColourCommandLine.new.out_c(:puts, role, str)
-end
-
-def colour_print(role, str)
-  ColourCommandLine.new.out_c(:print, role, str)
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/colour_reporter.rb b/test/vendor/ceedling/vendor/unity/auto/colour_reporter.rb
deleted file mode 100644
index 1c3bc2162..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/colour_reporter.rb
+++ /dev/null
@@ -1,39 +0,0 @@
-# ==========================================
-#   Unity Project - A Test Framework for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-require_relative 'colour_prompt'
-
-$colour_output = true
-
-def report(message)
-  if !$colour_output
-    $stdout.puts(message)
-  else
-    message = message.join('\n') if message.class == Array
-    message.each_line do |line|
-      line.chomp!
-      colour = case line
-               when /(?:total\s+)?tests:?\s+(\d+)\s+(?:total\s+)?failures:?\s+\d+\s+Ignored:?/i
-                 Regexp.last_match(1).to_i.zero? ? :green : :red
-               when /PASS/
-                 :green
-               when /^OK$/
-                 :green
-               when /(?:FAIL|ERROR)/
-                 :red
-               when /IGNORE/
-                 :yellow
-               when /^(?:Creating|Compiling|Linking)/
-                 :white
-               else
-                 :silver
-               end
-      colour_puts(colour, line)
-    end
-  end
-  $stdout.flush
-  $stderr.flush
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/generate_config.yml b/test/vendor/ceedling/vendor/unity/auto/generate_config.yml
deleted file mode 100644
index 4a5e47424..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/generate_config.yml
+++ /dev/null
@@ -1,36 +0,0 @@
-#this is a sample configuration file for generate_module
-#you would use it by calling generate_module with the -ygenerate_config.yml option
-#files like this are useful for customizing generate_module to your environment
-:generate_module:
-  :defaults:
-    #these defaults are used in place of any missing options at the command line
-    :path_src: ../src/
-    :path_inc: ../src/
-    :path_tst: ../test/
-    :update_svn: true
-  :includes:
-    #use [] for no additional includes, otherwise list the includes on separate lines
-    :src:
-      - Defs.h
-      - Board.h
-    :inc: []
-    :tst:
-      - Defs.h
-      - Board.h
-      - Exception.h
-  :boilerplates: 
-    #these are inserted at the top of generated files.
-    #just comment out or remove if not desired.
-    #use %1$s where you would like the file name to appear (path/extension not included)
-    :src: |
-      //-------------------------------------------
-      // %1$s.c
-      //-------------------------------------------
-    :inc: |
-      //-------------------------------------------
-      // %1$s.h
-      //-------------------------------------------
-    :tst: |
-      //-------------------------------------------
-      // Test%1$s.c : Units tests for %1$s.c
-      //-------------------------------------------
diff --git a/test/vendor/ceedling/vendor/unity/auto/generate_module.rb b/test/vendor/ceedling/vendor/unity/auto/generate_module.rb
deleted file mode 100644
index eb2cebd47..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/generate_module.rb
+++ /dev/null
@@ -1,309 +0,0 @@
-# ==========================================
-#   Unity Project - A Test Framework for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-# This script creates all the files with start code necessary for a new module.
-# A simple module only requires a source file, header file, and test file.
-# Triad modules require a source, header, and test file for each triad type (like model, conductor, and hardware).
-
-require 'rubygems'
-require 'fileutils'
-require 'pathname'
-
-# TEMPLATE_TST
-TEMPLATE_TST ||= '#include "unity.h"
-
-%2$s#include "%1$s.h"
-
-void setUp(void)
-{
-}
-
-void tearDown(void)
-{
-}
-
-void test_%1$s_NeedToImplement(void)
-{
-    TEST_IGNORE_MESSAGE("Need to Implement %1$s");
-}
-'.freeze
-
-# TEMPLATE_SRC
-TEMPLATE_SRC ||= '%2$s#include "%1$s.h"
-'.freeze
-
-# TEMPLATE_INC
-TEMPLATE_INC ||= '#ifndef %3$s_H
-#define %3$s_H
-%2$s
-
-#endif // %3$s_H
-'.freeze
-
-class UnityModuleGenerator
-  ############################
-  def initialize(options = nil)
-    @options = UnityModuleGenerator.default_options
-    case options
-    when NilClass then @options
-    when String   then @options.merge!(UnityModuleGenerator.grab_config(options))
-    when Hash     then @options.merge!(options)
-    else raise 'If you specify arguments, it should be a filename or a hash of options'
-    end
-
-    # Create default file paths if none were provided
-    @options[:path_src] = "#{__dir__}/../src/"   if @options[:path_src].nil?
-    @options[:path_inc] = @options[:path_src]    if @options[:path_inc].nil?
-    @options[:path_tst] = "#{__dir__}/../test/"  if @options[:path_tst].nil?
-    @options[:path_src] += '/'                unless @options[:path_src][-1] == 47
-    @options[:path_inc] += '/'                unless @options[:path_inc][-1] == 47
-    @options[:path_tst] += '/'                unless @options[:path_tst][-1] == 47
-
-    # Built in patterns
-    @patterns = {
-      'src'  =>  {
-        '' =>  { inc: [] }
-      },
-      'test' =>  {
-        '' =>  { inc: [] }
-      },
-      'dh'   =>  {
-        'Driver'    =>  { inc: [create_filename('%1$s', 'Hardware.h')] },
-        'Hardware'  =>  { inc: [] }
-      },
-      'dih'  =>  {
-        'Driver'    =>  { inc: [create_filename('%1$s', 'Hardware.h'), create_filename('%1$s', 'Interrupt.h')] },
-        'Interrupt' =>  { inc: [create_filename('%1$s', 'Hardware.h')] },
-        'Hardware'  =>  { inc: [] }
-      },
-      'mch'  =>  {
-        'Model'     =>  { inc: [] },
-        'Conductor' =>  { inc: [create_filename('%1$s', 'Model.h'), create_filename('%1$s', 'Hardware.h')] },
-        'Hardware'  =>  { inc: [] }
-      },
-      'mvp'  =>  {
-        'Model'     =>  { inc: [] },
-        'Presenter' =>  { inc: [create_filename('%1$s', 'Model.h'), create_filename('%1$s', 'View.h')] },
-        'View'      =>  { inc: [] }
-      }
-    }
-  end
-
-  ############################
-  def self.default_options
-    {
-      pattern: 'src',
-      includes: {
-        src: [],
-        inc: [],
-        tst: []
-      },
-      update_svn: false,
-      boilerplates: {},
-      test_prefix: 'Test',
-      mock_prefix: 'Mock'
-    }
-  end
-
-  ############################
-  def self.grab_config(config_file)
-    options = default_options
-    unless config_file.nil? || config_file.empty?
-      require 'yaml'
-      yaml_guts = YAML.load_file(config_file)
-      options.merge!(yaml_guts[:unity] || yaml_guts[:cmock])
-      raise "No :unity or :cmock section found in #{config_file}" unless options
-    end
-    options
-  end
-
-  ############################
-  def files_to_operate_on(module_name, pattern = nil)
-    # strip any leading path information from the module name and save for later
-    subfolder = File.dirname(module_name)
-    module_name = File.basename(module_name)
-
-    # create triad definition
-    prefix = @options[:test_prefix] || 'Test'
-    triad = [{ ext: '.c', path: @options[:path_src], prefix: '', template: TEMPLATE_SRC, inc: :src, boilerplate: @options[:boilerplates][:src] },
-             { ext: '.h', path: @options[:path_inc], prefix: '',     template: TEMPLATE_INC, inc: :inc, boilerplate: @options[:boilerplates][:inc] },
-             { ext: '.c', path: @options[:path_tst], prefix: prefix, template: TEMPLATE_TST, inc: :tst, boilerplate: @options[:boilerplates][:tst] }]
-
-    # prepare the pattern for use
-    pattern = (pattern || @options[:pattern] || 'src').downcase
-    patterns = @patterns[pattern]
-    raise "ERROR: The design pattern '#{pattern}' specified isn't one that I recognize!" if patterns.nil?
-
-    # single file patterns (currently just 'test') can reject the other parts of the triad
-    triad.select! { |v| v[:inc] == :tst } if pattern == 'test'
-
-    # Assemble the path/names of the files we need to work with.
-    files = []
-    triad.each do |cfg|
-      patterns.each_pair do |pattern_file, pattern_traits|
-        submodule_name = create_filename(module_name, pattern_file)
-        filename = cfg[:prefix] + submodule_name + cfg[:ext]
-        files << {
-          path: (Pathname.new("#{cfg[:path]}#{subfolder}") + filename).cleanpath,
-          name: submodule_name,
-          template: cfg[:template],
-          boilerplate: cfg[:boilerplate],
-          includes: case (cfg[:inc])
-                    when :src then (@options[:includes][:src] || []) | (pattern_traits[:inc].map { |f| format(f, module_name) })
-                    when :inc then (@options[:includes][:inc] || [])
-                    when :tst then (@options[:includes][:tst] || []) | (pattern_traits[:inc].map { |f| format("#{@options[:mock_prefix]}#{f}", module_name) })
-                    end
-        }
-      end
-    end
-
-    files
-  end
-
-  ############################
-  def create_filename(part1, part2 = '')
-    if part2.empty?
-      case (@options[:naming])
-      when 'bumpy' then part1
-      when 'camel' then part1
-      when 'snake' then part1.downcase
-      when 'caps'  then part1.upcase
-      else              part1
-      end
-    else
-      case (@options[:naming])
-      when 'bumpy' then part1 + part2
-      when 'camel' then part1 + part2
-      when 'snake' then part1.downcase + '_' + part2.downcase
-      when 'caps'  then part1.upcase + '_' + part2.upcase
-      else              part1 + '_' + part2
-      end
-    end
-  end
-
-  ############################
-  def generate(module_name, pattern = nil)
-    files = files_to_operate_on(module_name, pattern)
-
-    # Abort if all of the module files already exist
-    all_files_exist = true
-    files.each do |file|
-      all_files_exist = false unless File.exist?(file[:path])
-    end
-    raise "ERROR: File #{files[0][:name]} already exists. Exiting." if all_files_exist
-
-    # Create Source Modules
-    files.each_with_index do |file, _i|
-      # If this file already exists, don't overwrite it.
-      if File.exist?(file[:path])
-        puts "File #{file[:path]} already exists!"
-        next
-      end
-      # Create the path first if necessary.
-      FileUtils.mkdir_p(File.dirname(file[:path]), verbose: false)
-      File.open(file[:path], 'w') do |f|
-        f.write("#{file[:boilerplate]}\n" % [file[:name]]) unless file[:boilerplate].nil?
-        f.write(file[:template] % [file[:name],
-                                   file[:includes].map { |ff| "#include \"#{ff}\"\n" }.join,
-                                   file[:name].upcase])
-      end
-      if @options[:update_svn]
-        `svn add \"#{file[:path]}\"`
-        if $!.exitstatus.zero?
-          puts "File #{file[:path]} created and added to source control"
-        else
-          puts "File #{file[:path]} created but FAILED adding to source control!"
-        end
-      else
-        puts "File #{file[:path]} created"
-      end
-    end
-    puts 'Generate Complete'
-  end
-
-  ############################
-  def destroy(module_name, pattern = nil)
-    files_to_operate_on(module_name, pattern).each do |filespec|
-      file = filespec[:path]
-      if File.exist?(file)
-        if @options[:update_svn]
-          `svn delete \"#{file}\" --force`
-          puts "File #{file} deleted and removed from source control"
-        else
-          FileUtils.remove(file)
-          puts "File #{file} deleted"
-        end
-      else
-        puts "File #{file} does not exist so cannot be removed."
-      end
-    end
-    puts 'Destroy Complete'
-  end
-end
-
-############################
-# Handle As Command Line If Called That Way
-if $0 == __FILE__
-  destroy = false
-  options = {}
-  module_name = nil
-
-  # Parse the command line parameters.
-  ARGV.each do |arg|
-    case arg
-    when /^-d/            then destroy = true
-    when /^-u/            then options[:update_svn] = true
-    when /^-p\"?(\w+)\"?/ then options[:pattern] = Regexp.last_match(1)
-    when /^-s\"?(.+)\"?/  then options[:path_src] = Regexp.last_match(1)
-    when /^-i\"?(.+)\"?/  then options[:path_inc] = Regexp.last_match(1)
-    when /^-t\"?(.+)\"?/  then options[:path_tst] = Regexp.last_match(1)
-    when /^-n\"?(.+)\"?/  then options[:naming] = Regexp.last_match(1)
-    when /^-y\"?(.+)\"?/  then options = UnityModuleGenerator.grab_config(Regexp.last_match(1))
-    when /^(\w+)/
-      raise "ERROR: You can't have more than one Module name specified!" unless module_name.nil?
-
-      module_name = arg
-    when /^-(h|-help)/
-      ARGV = [].freeze
-    else
-      raise "ERROR: Unknown option specified '#{arg}'"
-    end
-  end
-
-  unless ARGV[0]
-    puts ["\nGENERATE MODULE\n-------- ------",
-          "\nUsage: ruby generate_module [options] module_name",
-          "  -i\"include\" sets the path to output headers to 'include' (DEFAULT ../src)",
-          "  -s\"../src\"  sets the path to output source to '../src'   (DEFAULT ../src)",
-          "  -t\"C:/test\" sets the path to output source to 'C:/test'  (DEFAULT ../test)",
-          '  -p"MCH"     sets the output pattern to MCH.',
-          '              dh   - driver hardware.',
-          '              dih  - driver interrupt hardware.',
-          '              mch  - model conductor hardware.',
-          '              mvp  - model view presenter.',
-          '              src  - just a source module, header and test. (DEFAULT)',
-          '              test - just a test file.',
-          '  -d          destroy module instead of creating it.',
-          '  -n"camel"   sets the file naming convention.',
-          '              bumpy - BumpyCaseFilenames.',
-          '              camel - camelCaseFilenames.',
-          '              snake - snake_case_filenames.',
-          '              caps  - CAPS_CASE_FILENAMES.',
-          '  -u          update subversion too (requires subversion command line)',
-          '  -y"my.yml"  selects a different yaml config file for module generation',
-          ''].join("\n")
-    exit
-  end
-
-  raise 'ERROR: You must have a Module name specified! (use option -h for help)' if module_name.nil?
-
-  if destroy
-    UnityModuleGenerator.new(options).destroy(module_name)
-  else
-    UnityModuleGenerator.new(options).generate(module_name)
-  end
-
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb b/test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
deleted file mode 100644
index 5053210d0..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
+++ /dev/null
@@ -1,495 +0,0 @@
-# ==========================================
-#   Unity Project - A Test Framework for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-class UnityTestRunnerGenerator
-  def initialize(options = nil)
-    @options = UnityTestRunnerGenerator.default_options
-    case options
-    when NilClass
-      @options
-    when String
-      @options.merge!(UnityTestRunnerGenerator.grab_config(options))
-    when Hash
-      # Check if some of these have been specified
-      @options[:has_setup] = !options[:setup_name].nil?
-      @options[:has_teardown] = !options[:teardown_name].nil?
-      @options[:has_suite_setup] = !options[:suite_setup].nil?
-      @options[:has_suite_teardown] = !options[:suite_teardown].nil?
-      @options.merge!(options)
-    else
-      raise 'If you specify arguments, it should be a filename or a hash of options'
-    end
-    require_relative 'type_sanitizer'
-  end
-
-  def self.default_options
-    {
-      includes: [],
-      defines: [],
-      plugins: [],
-      framework: :unity,
-      test_prefix: 'test|spec|should',
-      mock_prefix: 'Mock',
-      mock_suffix: '',
-      setup_name: 'setUp',
-      teardown_name: 'tearDown',
-      test_reset_name: 'resetTest',
-      test_verify_name: 'verifyTest',
-      main_name: 'main', # set to :auto to automatically generate each time
-      main_export_decl: '',
-      cmdline_args: false,
-      omit_begin_end: false,
-      use_param_tests: false
-    }
-  end
-
-  def self.grab_config(config_file)
-    options = default_options
-    unless config_file.nil? || config_file.empty?
-      require 'yaml'
-      yaml_guts = YAML.load_file(config_file)
-      options.merge!(yaml_guts[:unity] || yaml_guts[:cmock])
-      raise "No :unity or :cmock section found in #{config_file}" unless options
-    end
-    options
-  end
-
-  def run(input_file, output_file, options = nil)
-    @options.merge!(options) unless options.nil?
-
-    # pull required data from source file
-    source = File.read(input_file)
-    source = source.force_encoding('ISO-8859-1').encode('utf-8', replace: nil)
-    tests = find_tests(source)
-    headers = find_includes(source)
-    testfile_includes = (headers[:local] + headers[:system])
-    used_mocks = find_mocks(testfile_includes)
-    testfile_includes = (testfile_includes - used_mocks)
-    testfile_includes.delete_if { |inc| inc =~ /(unity|cmock)/ }
-    find_setup_and_teardown(source)
-
-    # build runner file
-    generate(input_file, output_file, tests, used_mocks, testfile_includes)
-
-    # determine which files were used to return them
-    all_files_used = [input_file, output_file]
-    all_files_used += testfile_includes.map { |filename| filename + '.c' } unless testfile_includes.empty?
-    all_files_used += @options[:includes] unless @options[:includes].empty?
-    all_files_used += headers[:linkonly] unless headers[:linkonly].empty?
-    all_files_used.uniq
-  end
-
-  def generate(input_file, output_file, tests, used_mocks, testfile_includes)
-    File.open(output_file, 'w') do |output|
-      create_header(output, used_mocks, testfile_includes)
-      create_externs(output, tests, used_mocks)
-      create_mock_management(output, used_mocks)
-      create_setup(output)
-      create_teardown(output)
-      create_suite_setup(output)
-      create_suite_teardown(output)
-      create_reset(output)
-      create_run_test(output)
-      create_args_wrappers(output, tests)
-      create_main(output, input_file, tests, used_mocks)
-    end
-
-    return unless @options[:header_file] && !@options[:header_file].empty?
-
-    File.open(@options[:header_file], 'w') do |output|
-      create_h_file(output, @options[:header_file], tests, testfile_includes, used_mocks)
-    end
-  end
-
-  def find_tests(source)
-    tests_and_line_numbers = []
-
-    # contains characters which will be substituted from within strings, doing
-    # this prevents these characters from interferring with scrubbers
-    # @ is not a valid C character, so there should be no clashes with files genuinely containing these markers
-    substring_subs = { '{' => '@co@', '}' => '@cc@', ';' => '@ss@', '/' => '@fs@' }
-    substring_re = Regexp.union(substring_subs.keys)
-    substring_unsubs = substring_subs.invert                   # the inverse map will be used to fix the strings afterwords
-    substring_unsubs['@quote@'] = '\\"'
-    substring_unsubs['@apos@'] = '\\\''
-    substring_unre = Regexp.union(substring_unsubs.keys)
-    source_scrubbed = source.clone
-    source_scrubbed = source_scrubbed.gsub(/\\"/, '@quote@')   # hide escaped quotes to allow capture of the full string/char
-    source_scrubbed = source_scrubbed.gsub(/\\'/, '@apos@')    # hide escaped apostrophes to allow capture of the full string/char
-    source_scrubbed = source_scrubbed.gsub(/("[^"\n]*")|('[^'\n]*')/) { |s| s.gsub(substring_re, substring_subs) } # temporarily hide problematic characters within strings
-    source_scrubbed = source_scrubbed.gsub(/\/\/(?:.+\/\*|\*(?:$|[^\/])).*$/, '')  # remove line comments that comment out the start of blocks
-    source_scrubbed = source_scrubbed.gsub(/\/\*.*?\*\//m, '')                     # remove block comments
-    source_scrubbed = source_scrubbed.gsub(/\/\/.*$/, '')                          # remove line comments (all that remain)
-    lines = source_scrubbed.split(/(^\s*\#.*$) | (;|\{|\}) /x)                     # Treat preprocessor directives as a logical line. Match ;, {, and } as end of lines
-                           .map { |line| line.gsub(substring_unre, substring_unsubs) } # unhide the problematic characters previously removed
-
-    lines.each_with_index do |line, _index|
-      # find tests
-      next unless line =~ /^((?:\s*TEST_CASE\s*\(.*?\)\s*)*)\s*void\s+((?:#{@options[:test_prefix]}).*)\s*\(\s*(.*)\s*\)/m
-
-      arguments = Regexp.last_match(1)
-      name = Regexp.last_match(2)
-      call = Regexp.last_match(3)
-      params = Regexp.last_match(4)
-      args = nil
-
-      if @options[:use_param_tests] && !arguments.empty?
-        args = []
-        arguments.scan(/\s*TEST_CASE\s*\((.*)\)\s*$/) { |a| args << a[0] }
-      end
-
-      tests_and_line_numbers << { test: name, args: args, call: call, params: params, line_number: 0 }
-    end
-
-    tests_and_line_numbers.uniq! { |v| v[:test] }
-
-    # determine line numbers and create tests to run
-    source_lines = source.split("\n")
-    source_index = 0
-    tests_and_line_numbers.size.times do |i|
-      source_lines[source_index..-1].each_with_index do |line, index|
-        next unless line =~ /\s+#{tests_and_line_numbers[i][:test]}(?:\s|\()/
-
-        source_index += index
-        tests_and_line_numbers[i][:line_number] = source_index + 1
-        break
-      end
-    end
-
-    tests_and_line_numbers
-  end
-
-  def find_includes(source)
-    # remove comments (block and line, in three steps to ensure correct precedence)
-    source.gsub!(/\/\/(?:.+\/\*|\*(?:$|[^\/])).*$/, '')  # remove line comments that comment out the start of blocks
-    source.gsub!(/\/\*.*?\*\//m, '')                     # remove block comments
-    source.gsub!(/\/\/.*$/, '')                          # remove line comments (all that remain)
-
-    # parse out includes
-    includes = {
-      local: source.scan(/^\s*#include\s+\"\s*(.+)\.[hH]\s*\"/).flatten,
-      system: source.scan(/^\s*#include\s+<\s*(.+)\s*>/).flatten.map { |inc| "<#{inc}>" },
-      linkonly: source.scan(/^TEST_FILE\(\s*\"\s*(.+)\.[cC]\w*\s*\"/).flatten
-    }
-    includes
-  end
-
-  def find_mocks(includes)
-    mock_headers = []
-    includes.each do |include_path|
-      include_file = File.basename(include_path)
-      mock_headers << include_path if include_file =~ /^#{@options[:mock_prefix]}.*#{@options[:mock_suffix]}$/i
-    end
-    mock_headers
-  end
-
-  def find_setup_and_teardown(source)
-    @options[:has_setup] = source =~ /void\s+#{@options[:setup_name]}\s*\(/
-    @options[:has_teardown] = source =~ /void\s+#{@options[:teardown_name]}\s*\(/
-    @options[:has_suite_setup] ||= (source =~ /void\s+suiteSetUp\s*\(/)
-    @options[:has_suite_teardown] ||= (source =~ /void\s+suiteTearDown\s*\(/)
-  end
-
-  def create_header(output, mocks, testfile_includes = [])
-    output.puts('/* AUTOGENERATED FILE. DO NOT EDIT. */')
-    output.puts("\n/*=======Automagically Detected Files To Include=====*/")
-    output.puts("#include \"#{@options[:framework]}.h\"")
-    output.puts('#include "cmock.h"') unless mocks.empty?
-    if @options[:defines] && !@options[:defines].empty?
-      @options[:defines].each { |d| output.puts("#ifndef #{d}\n#define #{d}\n#endif /* #{d} */") }
-    end
-    if @options[:header_file] && !@options[:header_file].empty?
-      output.puts("#include \"#{File.basename(@options[:header_file])}\"")
-    else
-      @options[:includes].flatten.uniq.compact.each do |inc|
-        output.puts("#include #{inc.include?('<') ? inc : "\"#{inc.gsub('.h', '')}.h\""}")
-      end
-      testfile_includes.each do |inc|
-        output.puts("#include #{inc.include?('<') ? inc : "\"#{inc.gsub('.h', '')}.h\""}")
-      end
-    end
-    mocks.each do |mock|
-      output.puts("#include \"#{mock.gsub('.h', '')}.h\"")
-    end
-    output.puts('#include "CException.h"') if @options[:plugins].include?(:cexception)
-
-    return unless @options[:enforce_strict_ordering]
-
-    output.puts('')
-    output.puts('int GlobalExpectCount;')
-    output.puts('int GlobalVerifyOrder;')
-    output.puts('char* GlobalOrderError;')
-  end
-
-  def create_externs(output, tests, _mocks)
-    output.puts("\n/*=======External Functions This Runner Calls=====*/")
-    output.puts("extern void #{@options[:setup_name]}(void);")
-    output.puts("extern void #{@options[:teardown_name]}(void);")
-    output.puts("\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif") if @options[:externc]
-    tests.each do |test|
-      output.puts("extern void #{test[:test]}(#{test[:call] || 'void'});")
-    end
-    output.puts("#ifdef __cplusplus\n}\n#endif") if @options[:externc]
-    output.puts('')
-  end
-
-  def create_mock_management(output, mock_headers)
-    output.puts("\n/*=======Mock Management=====*/")
-    output.puts('static void CMock_Init(void)')
-    output.puts('{')
-
-    if @options[:enforce_strict_ordering]
-      output.puts('  GlobalExpectCount = 0;')
-      output.puts('  GlobalVerifyOrder = 0;')
-      output.puts('  GlobalOrderError = NULL;')
-    end
-
-    mocks = mock_headers.map { |mock| File.basename(mock) }
-    mocks.each do |mock|
-      mock_clean = TypeSanitizer.sanitize_c_identifier(mock)
-      output.puts("  #{mock_clean}_Init();")
-    end
-    output.puts("}\n")
-
-    output.puts('static void CMock_Verify(void)')
-    output.puts('{')
-    mocks.each do |mock|
-      mock_clean = TypeSanitizer.sanitize_c_identifier(mock)
-      output.puts("  #{mock_clean}_Verify();")
-    end
-    output.puts("}\n")
-
-    output.puts('static void CMock_Destroy(void)')
-    output.puts('{')
-    mocks.each do |mock|
-      mock_clean = TypeSanitizer.sanitize_c_identifier(mock)
-      output.puts("  #{mock_clean}_Destroy();")
-    end
-    output.puts("}\n")
-  end
-
-  def create_setup(output)
-    return if @options[:has_setup]
-
-    output.puts("\n/*=======Setup (stub)=====*/")
-    output.puts("void #{@options[:setup_name]}(void) {}")
-  end
-
-  def create_teardown(output)
-    return if @options[:has_teardown]
-
-    output.puts("\n/*=======Teardown (stub)=====*/")
-    output.puts("void #{@options[:teardown_name]}(void) {}")
-  end
-
-  def create_suite_setup(output)
-    return if @options[:suite_setup].nil?
-
-    output.puts("\n/*=======Suite Setup=====*/")
-    output.puts('void suiteSetUp(void)')
-    output.puts('{')
-    output.puts(@options[:suite_setup])
-    output.puts('}')
-  end
-
-  def create_suite_teardown(output)
-    return if @options[:suite_teardown].nil?
-
-    output.puts("\n/*=======Suite Teardown=====*/")
-    output.puts('int suiteTearDown(int num_failures)')
-    output.puts('{')
-    output.puts(@options[:suite_teardown])
-    output.puts('}')
-  end
-
-  def create_reset(output)
-    output.puts("\n/*=======Test Reset Options=====*/")
-    output.puts("void #{@options[:test_reset_name]}(void);")
-    output.puts("void #{@options[:test_reset_name]}(void)")
-    output.puts('{')
-    output.puts("  #{@options[:teardown_name]}();")
-    output.puts('  CMock_Verify();')
-    output.puts('  CMock_Destroy();')
-    output.puts('  CMock_Init();')
-    output.puts("  #{@options[:setup_name]}();")
-    output.puts('}')
-    output.puts("void #{@options[:test_verify_name]}(void);")
-    output.puts("void #{@options[:test_verify_name]}(void)")
-    output.puts('{')
-    output.puts('  CMock_Verify();')
-    output.puts('}')
-  end
-
-  def create_run_test(output)
-    require 'erb'
-    template = ERB.new(File.read(File.join(__dir__, 'run_test.erb')))
-    output.puts(template.result(binding))
-  end
-
-  def create_args_wrappers(output, tests)
-    return unless @options[:use_param_tests]
-
-    output.puts("\n/*=======Parameterized Test Wrappers=====*/")
-    tests.each do |test|
-      next if test[:args].nil? || test[:args].empty?
-
-      test[:args].each.with_index(1) do |args, idx|
-        output.puts("static void runner_args#{idx}_#{test[:test]}(void)")
-        output.puts('{')
-        output.puts("    #{test[:test]}(#{args});")
-        output.puts("}\n")
-      end
-    end
-  end
-
-  def create_main(output, filename, tests, used_mocks)
-    output.puts("\n\n/*=======MAIN=====*/")
-    main_name = @options[:main_name].to_sym == :auto ? "main_#{filename.gsub('.c', '')}" : (@options[:main_name]).to_s
-    if @options[:cmdline_args]
-      if main_name != 'main'
-        output.puts("#{@options[:main_export_decl]} int #{main_name}(int argc, char** argv);")
-      end
-      output.puts("#{@options[:main_export_decl]} int #{main_name}(int argc, char** argv)")
-      output.puts('{')
-      output.puts('  int parse_status = UnityParseOptions(argc, argv);')
-      output.puts('  if (parse_status != 0)')
-      output.puts('  {')
-      output.puts('    if (parse_status < 0)')
-      output.puts('    {')
-      output.puts("      UnityPrint(\"#{filename.gsub('.c', '')}.\");")
-      output.puts('      UNITY_PRINT_EOL();')
-      tests.each do |test|
-        if (!@options[:use_param_tests]) || test[:args].nil? || test[:args].empty?
-          output.puts("      UnityPrint(\"  #{test[:test]}\");")
-          output.puts('      UNITY_PRINT_EOL();')
-        else
-          test[:args].each do |args|
-            output.puts("      UnityPrint(\"  #{test[:test]}(#{args})\");")
-            output.puts('      UNITY_PRINT_EOL();')
-          end
-        end
-      end
-      output.puts('      return 0;')
-      output.puts('    }')
-      output.puts('    return parse_status;')
-      output.puts('  }')
-    else
-      main_return = @options[:omit_begin_end] ? 'void' : 'int'
-      if main_name != 'main'
-        output.puts("#{@options[:main_export_decl]} #{main_return} #{main_name}(void);")
-      end
-      output.puts("#{main_return} #{main_name}(void)")
-      output.puts('{')
-    end
-    output.puts('  suiteSetUp();') if @options[:has_suite_setup]
-    if @options[:omit_begin_end]
-      output.puts("  UnitySetTestFile(\"#{filename.gsub(/\\/, '\\\\\\')}\");")
-    else
-      output.puts("  UnityBegin(\"#{filename.gsub(/\\/, '\\\\\\')}\");")
-    end
-    tests.each do |test|
-      if (!@options[:use_param_tests]) || test[:args].nil? || test[:args].empty?
-        output.puts("  run_test(#{test[:test]}, \"#{test[:test]}\", #{test[:line_number]});")
-      else
-        test[:args].each.with_index(1) do |args, idx|
-          wrapper = "runner_args#{idx}_#{test[:test]}"
-          testname = "#{test[:test]}(#{args})".dump
-          output.puts("  run_test(#{wrapper}, #{testname}, #{test[:line_number]});")
-        end
-      end
-    end
-    output.puts
-    output.puts('  CMock_Guts_MemFreeFinal();') unless used_mocks.empty?
-    if @options[:has_suite_teardown]
-      if @options[:omit_begin_end]
-        output.puts('  (void) suite_teardown(0);')
-      else
-        output.puts('  return suiteTearDown(UnityEnd());')
-      end
-    else
-      output.puts('  return UnityEnd();') if not @options[:omit_begin_end]
-    end
-    output.puts('}')
-  end
-
-  def create_h_file(output, filename, tests, testfile_includes, used_mocks)
-    filename = File.basename(filename).gsub(/[-\/\\\.\,\s]/, '_').upcase
-    output.puts('/* AUTOGENERATED FILE. DO NOT EDIT. */')
-    output.puts("#ifndef _#{filename}")
-    output.puts("#define _#{filename}\n\n")
-    output.puts("#include \"#{@options[:framework]}.h\"")
-    output.puts('#include "cmock.h"') unless used_mocks.empty?
-    @options[:includes].flatten.uniq.compact.each do |inc|
-      output.puts("#include #{inc.include?('<') ? inc : "\"#{inc.gsub('.h', '')}.h\""}")
-    end
-    testfile_includes.each do |inc|
-      output.puts("#include #{inc.include?('<') ? inc : "\"#{inc.gsub('.h', '')}.h\""}")
-    end
-    output.puts "\n"
-    tests.each do |test|
-      if test[:params].nil? || test[:params].empty?
-        output.puts("void #{test[:test]}(void);")
-      else
-        output.puts("void #{test[:test]}(#{test[:params]});")
-      end
-    end
-    output.puts("#endif\n\n")
-  end
-end
-
-if $0 == __FILE__
-  options = { includes: [] }
-
-  # parse out all the options first (these will all be removed as we go)
-  ARGV.reject! do |arg|
-    case arg
-    when '-cexception'
-      options[:plugins] = [:cexception]
-      true
-    when /\.*\.ya?ml/
-      options = UnityTestRunnerGenerator.grab_config(arg)
-      true
-    when /--(\w+)=\"?(.*)\"?/
-      options[Regexp.last_match(1).to_sym] = Regexp.last_match(2)
-      true
-    when /\.*\.h/
-      options[:includes] << arg
-      true
-    else false
-    end
-  end
-
-  # make sure there is at least one parameter left (the input file)
-  unless ARGV[0]
-    puts ["\nusage: ruby #{__FILE__} (files) (options) input_test_file (output)",
-          "\n  input_test_file         - this is the C file you want to create a runner for",
-          '  output                  - this is the name of the runner file to generate',
-          '                            defaults to (input_test_file)_Runner',
-          '  files:',
-          '    *.yml / *.yaml        - loads configuration from here in :unity or :cmock',
-          '    *.h                   - header files are added as #includes in runner',
-          '  options:',
-          '    -cexception           - include cexception support',
-          '    -externc              - add extern "C" for cpp support',
-          '    --setup_name=""       - redefine setUp func name to something else',
-          '    --teardown_name=""    - redefine tearDown func name to something else',
-          '    --main_name=""        - redefine main func name to something else',
-          '    --test_prefix=""      - redefine test prefix from default test|spec|should',
-          '    --test_reset_name=""  - redefine resetTest func name to something else',
-          '    --test_verify_name="" - redefine verifyTest func name to something else',
-          '    --suite_setup=""      - code to execute for setup of entire suite',
-          '    --suite_teardown=""   - code to execute for teardown of entire suite',
-          '    --use_param_tests=1   - enable parameterized tests (disabled by default)',
-          '    --omit_begin_end=1    - omit calls to UnityBegin and UnityEnd (disabled by default)',
-          '    --header_file=""      - path/name of test header file to generate too'].join("\n")
-    exit 1
-  end
-
-  # create the default test runner name if not specified
-  ARGV[1] = ARGV[0].gsub('.c', '_Runner.c') unless ARGV[1]
-
-  UnityTestRunnerGenerator.new(options).run(ARGV[0], ARGV[1])
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/parse_output.rb b/test/vendor/ceedling/vendor/unity/auto/parse_output.rb
deleted file mode 100644
index d72c6e8b2..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/parse_output.rb
+++ /dev/null
@@ -1,322 +0,0 @@
-#============================================================
-#  Author: John Theofanopoulos
-#  A simple parser. Takes the output files generated during the
-#  build process and extracts information relating to the tests.
-#
-#  Notes:
-#    To capture an output file under VS builds use the following:
-#      devenv [build instructions] > Output.txt & type Output.txt
-#
-#    To capture an output file under Linux builds use the following:
-#      make | tee Output.txt
-#
-#    This script can handle the following output formats:
-#    - normal output (raw unity)
-#    - fixture output (unity_fixture.h/.c)
-#    - fixture output with verbose flag set ("-v")
-#
-#    To use this parser use the following command
-#    ruby parseOutput.rb [options] [file]
-#        options: -xml  : produce a JUnit compatible XML file
-#           file: file to scan for results
-#============================================================
-
-# Parser class for handling the input file
-class ParseOutput
-  def initialize
-    # internal data
-    @class_name_idx = 0
-    @path_delim = nil
-
-    # xml output related
-    @xml_out = false
-    @array_list = false
-
-    # current suite name and statistics
-    @test_suite = nil
-    @total_tests = 0
-    @test_passed = 0
-    @test_failed = 0
-    @test_ignored = 0
-  end
-
-  # Set the flag to indicate if there will be an XML output file or not
-  def set_xml_output
-    @xml_out = true
-  end
-
-  # If write our output to XML
-  def write_xml_output
-    output = File.open('report.xml', 'w')
-    output << "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n"
-    @array_list.each do |item|
-      output << item << "\n"
-    end
-  end
-
-  # Pushes the suite info as xml to the array list, which will be written later
-  def push_xml_output_suite_info
-    # Insert opening tag at front
-    heading = '<testsuite name="Unity" tests="' + @total_tests.to_s + '" failures="' + @test_failed.to_s + '"' + ' skips="' + @test_ignored.to_s + '">'
-    @array_list.insert(0, heading)
-    # Push back the closing tag
-    @array_list.push '</testsuite>'
-  end
-
-  # Pushes xml output data to the array list, which will be written later
-  def push_xml_output_passed(test_name)
-    @array_list.push '    <testcase classname="' + @test_suite + '" name="' + test_name + '"/>'
-  end
-
-  # Pushes xml output data to the array list, which will be written later
-  def push_xml_output_failed(test_name, reason)
-    @array_list.push '    <testcase classname="' + @test_suite + '" name="' + test_name + '">'
-    @array_list.push '        <failure type="ASSERT FAILED">' + reason + '</failure>'
-    @array_list.push '    </testcase>'
-  end
-
-  # Pushes xml output data to the array list, which will be written later
-  def push_xml_output_ignored(test_name, reason)
-    @array_list.push '    <testcase classname="' + @test_suite + '" name="' + test_name + '">'
-    @array_list.push '        <skipped type="TEST IGNORED">' + reason + '</skipped>'
-    @array_list.push '    </testcase>'
-  end
-
-  # This function will try and determine when the suite is changed. This is
-  # is the name that gets added to the classname parameter.
-  def test_suite_verify(test_suite_name)
-    # Split the path name
-    test_name = test_suite_name.split(@path_delim)
-
-    # Remove the extension and extract the base_name
-    base_name = test_name[test_name.size - 1].split('.')[0]
-
-    # Return if the test suite hasn't changed
-    return unless base_name.to_s != @test_suite.to_s
-
-    @test_suite = base_name
-    printf "New Test: %s\n", @test_suite
-  end
-
-  # Prepares the line for verbose fixture output ("-v")
-  def prepare_fixture_line(line)
-    line = line.sub('IGNORE_TEST(', '')
-    line = line.sub('TEST(', '')
-    line = line.sub(')', ',')
-    line = line.chomp
-    array = line.split(',')
-    array.map { |x| x.to_s.lstrip.chomp }
-  end
-
-  # Test was flagged as having passed so format the output.
-  # This is using the Unity fixture output and not the original Unity output.
-  def test_passed_unity_fixture(array)
-    class_name = array[0]
-    test_name  = array[1]
-    test_suite_verify(class_name)
-    printf "%-40s PASS\n", test_name
-
-    push_xml_output_passed(test_name) if @xml_out
-  end
-
-  # Test was flagged as having failed so format the output.
-  # This is using the Unity fixture output and not the original Unity output.
-  def test_failed_unity_fixture(array)
-    class_name = array[0]
-    test_name  = array[1]
-    test_suite_verify(class_name)
-    reason_array = array[2].split(':')
-    reason = reason_array[-1].lstrip.chomp + ' at line: ' + reason_array[-4]
-
-    printf "%-40s FAILED\n", test_name
-
-    push_xml_output_failed(test_name, reason) if @xml_out
-  end
-
-  # Test was flagged as being ignored so format the output.
-  # This is using the Unity fixture output and not the original Unity output.
-  def test_ignored_unity_fixture(array)
-    class_name = array[0]
-    test_name  = array[1]
-    reason = 'No reason given'
-    if array.size > 2
-      reason_array = array[2].split(':')
-      tmp_reason = reason_array[-1].lstrip.chomp
-      reason = tmp_reason == 'IGNORE' ? 'No reason given' : tmp_reason
-    end
-    test_suite_verify(class_name)
-    printf "%-40s IGNORED\n", test_name
-
-    push_xml_output_ignored(test_name, reason) if @xml_out
-  end
-
-  # Test was flagged as having passed so format the output
-  def test_passed(array)
-    last_item = array.length - 1
-    test_name = array[last_item - 1]
-    test_suite_verify(array[@class_name_idx])
-    printf "%-40s PASS\n", test_name
-
-    return unless @xml_out
-
-    push_xml_output_passed(test_name) if @xml_out
-  end
-
-  # Test was flagged as having failed so format the line
-  def test_failed(array)
-    last_item = array.length - 1
-    test_name = array[last_item - 2]
-    reason = array[last_item].chomp.lstrip + ' at line: ' + array[last_item - 3]
-    class_name = array[@class_name_idx]
-
-    if test_name.start_with? 'TEST('
-      array2 = test_name.split(' ')
-
-      test_suite = array2[0].sub('TEST(', '')
-      test_suite = test_suite.sub(',', '')
-      class_name = test_suite
-
-      test_name = array2[1].sub(')', '')
-    end
-
-    test_suite_verify(class_name)
-    printf "%-40s FAILED\n", test_name
-
-    push_xml_output_failed(test_name, reason) if @xml_out
-  end
-
-  # Test was flagged as being ignored so format the output
-  def test_ignored(array)
-    last_item = array.length - 1
-    test_name = array[last_item - 2]
-    reason = array[last_item].chomp.lstrip
-    class_name = array[@class_name_idx]
-
-    if test_name.start_with? 'TEST('
-      array2 = test_name.split(' ')
-
-      test_suite = array2[0].sub('TEST(', '')
-      test_suite = test_suite.sub(',', '')
-      class_name = test_suite
-
-      test_name = array2[1].sub(')', '')
-    end
-
-    test_suite_verify(class_name)
-    printf "%-40s IGNORED\n", test_name
-
-    push_xml_output_ignored(test_name, reason) if @xml_out
-  end
-
-  # Adjusts the os specific members according to the current path style
-  # (Windows or Unix based)
-  def detect_os_specifics(line)
-    if line.include? '\\'
-      # Windows X:\Y\Z
-      @class_name_idx = 1
-      @path_delim = '\\'
-    else
-      # Unix Based /X/Y/Z
-      @class_name_idx = 0
-      @path_delim = '/'
-    end
-  end
-
-  # Main function used to parse the file that was captured.
-  def process(file_name)
-    @array_list = []
-
-    puts 'Parsing file: ' + file_name
-
-    @test_passed = 0
-    @test_failed = 0
-    @test_ignored = 0
-    puts ''
-    puts '=================== RESULTS ====================='
-    puts ''
-    File.open(file_name).each do |line|
-      # Typical test lines look like these:
-      # ----------------------------------------------------
-      # 1. normal output:
-      # <path>/<test_file>.c:36:test_tc1000_opsys:FAIL: Expected 1 Was 0
-      # <path>/<test_file>.c:112:test_tc5004_initCanChannel:IGNORE: Not Yet Implemented
-      # <path>/<test_file>.c:115:test_tc5100_initCanVoidPtrs:PASS
-      #
-      # 2. fixture output
-      # <path>/<test_file>.c:63:TEST(<test_group>, <test_function>):FAIL: Expected 0x00001234 Was 0x00005A5A
-      # <path>/<test_file>.c:36:TEST(<test_group>, <test_function>):IGNORE
-      # Note: "PASS" information won't be generated in this mode
-      #
-      # 3. fixture output with verbose information ("-v")
-      # TEST(<test_group, <test_file>)<path>/<test_file>:168::FAIL: Expected 0x8D Was 0x8C
-      # TEST(<test_group>, <test_file>)<path>/<test_file>:22::IGNORE: This Test Was Ignored On Purpose
-      # IGNORE_TEST(<test_group, <test_file>)
-      # TEST(<test_group, <test_file>) PASS
-      #
-      # Note: Where path is different on Unix vs Windows devices (Windows leads with a drive letter)!
-      detect_os_specifics(line)
-      line_array = line.split(':')
-
-      # If we were able to split the line then we can look to see if any of our target words
-      # were found. Case is important.
-      next unless (line_array.size >= 4) || (line.start_with? 'TEST(') || (line.start_with? 'IGNORE_TEST(')
-
-      # check if the output is fixture output (with verbose flag "-v")
-      if (line.start_with? 'TEST(') || (line.start_with? 'IGNORE_TEST(')
-        line_array = prepare_fixture_line(line)
-        if line.include? ' PASS'
-          test_passed_unity_fixture(line_array)
-          @test_passed += 1
-        elsif line.include? 'FAIL'
-          test_failed_unity_fixture(line_array)
-          @test_failed += 1
-        elsif line.include? 'IGNORE'
-          test_ignored_unity_fixture(line_array)
-          @test_ignored += 1
-        end
-      # normal output / fixture output (without verbose "-v")
-      elsif line.include? ':PASS'
-        test_passed(line_array)
-        @test_passed += 1
-      elsif line.include? ':FAIL'
-        test_failed(line_array)
-        @test_failed += 1
-      elsif line.include? ':IGNORE:'
-        test_ignored(line_array)
-        @test_ignored += 1
-      elsif line.include? ':IGNORE'
-        line_array.push('No reason given')
-        test_ignored(line_array)
-        @test_ignored += 1
-      end
-      @total_tests = @test_passed + @test_failed + @test_ignored
-    end
-    puts ''
-    puts '=================== SUMMARY ====================='
-    puts ''
-    puts 'Tests Passed  : ' + @test_passed.to_s
-    puts 'Tests Failed  : ' + @test_failed.to_s
-    puts 'Tests Ignored : ' + @test_ignored.to_s
-
-    return unless @xml_out
-
-    # push information about the suite
-    push_xml_output_suite_info
-    # write xml output file
-    write_xml_output
-  end
-end
-
-# If the command line has no values in, used a default value of Output.txt
-parse_my_file = ParseOutput.new
-
-if ARGV.size >= 1
-  ARGV.each do |arg|
-    if arg == '-xml'
-      parse_my_file.set_xml_output
-    else
-      parse_my_file.process(arg)
-      break
-    end
-  end
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/run_test.erb b/test/vendor/ceedling/vendor/unity/auto/run_test.erb
deleted file mode 100644
index 3d3b6d1e8..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/run_test.erb
+++ /dev/null
@@ -1,36 +0,0 @@
-/*=======Test Runner Used To Run Each Test=====*/
-static void run_test(UnityTestFunction func, const char* name, int line_num)
-{
-    Unity.CurrentTestName = name;
-    Unity.CurrentTestLineNumber = line_num;
-#ifdef UNITY_USE_COMMAND_LINE_ARGS
-    if (!UnityTestMatches())
-        return;
-#endif
-    Unity.NumberOfTests++;
-    UNITY_CLR_DETAILS();
-    UNITY_EXEC_TIME_START();
-    CMock_Init();
-    if (TEST_PROTECT())
-    {
-<% if @options[:plugins].include?(:cexception) %>
-        CEXCEPTION_T e;
-        Try {
-<% end %>
-            <%= @options[:setup_name] %>();
-            func();
-<% if @options[:plugins].include?(:cexception) %>
-        } Catch(e) {
-            TEST_ASSERT_EQUAL_HEX32_MESSAGE(CEXCEPTION_NONE, e, "Unhandled Exception!");
-        }
-<% end %>
-    }
-    if (TEST_PROTECT())
-    {
-        <%= @options[:teardown_name] %>();
-        CMock_Verify();
-    }
-    CMock_Destroy();
-    UNITY_EXEC_TIME_STOP();
-    UnityConcludeTest();
-}
diff --git a/test/vendor/ceedling/vendor/unity/auto/stylize_as_junit.rb b/test/vendor/ceedling/vendor/unity/auto/stylize_as_junit.rb
deleted file mode 100644
index e01f7912a..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/stylize_as_junit.rb
+++ /dev/null
@@ -1,251 +0,0 @@
-#!/usr/bin/ruby
-#
-# unity_to_junit.rb
-#
-require 'fileutils'
-require 'optparse'
-require 'ostruct'
-require 'set'
-
-require 'pp'
-
-VERSION = 1.0
-
-class ArgvParser
-  #
-  # Return a structure describing the options.
-  #
-  def self.parse(args)
-    # The options specified on the command line will be collected in *options*.
-    # We set default values here.
-    options = OpenStruct.new
-    options.results_dir = '.'
-    options.root_path = '.'
-    options.out_file = 'results.xml'
-
-    opts = OptionParser.new do |o|
-      o.banner = 'Usage: unity_to_junit.rb [options]'
-
-      o.separator ''
-      o.separator 'Specific options:'
-
-      o.on('-r', '--results <dir>', 'Look for Unity Results files here.') do |results|
-        # puts "results #{results}"
-        options.results_dir = results
-      end
-
-      o.on('-p', '--root_path <path>', 'Prepend this path to files in results.') do |root_path|
-        options.root_path = root_path
-      end
-
-      o.on('-o', '--output <filename>', 'XML file to generate.') do |out_file|
-        # puts "out_file: #{out_file}"
-        options.out_file = out_file
-      end
-
-      o.separator ''
-      o.separator 'Common options:'
-
-      # No argument, shows at tail.  This will print an options summary.
-      o.on_tail('-h', '--help', 'Show this message') do
-        puts o
-        exit
-      end
-
-      # Another typical switch to print the version.
-      o.on_tail('--version', 'Show version') do
-        puts "unity_to_junit.rb version #{VERSION}"
-        exit
-      end
-    end
-
-    opts.parse!(args)
-    options
-  end
-end
-
-class UnityToJUnit
-  include FileUtils::Verbose
-  attr_reader :report, :total_tests, :failures, :ignored
-  attr_writer :targets, :root, :out_file
-
-  def initialize
-    @report = ''
-    @unit_name = ''
-  end
-
-  def run
-    # Clean up result file names
-    results = @targets.map { |target| target.tr('\\', '/') }
-    # puts "Output File: #{@out_file}"
-    f = File.new(@out_file, 'w')
-    write_xml_header(f)
-    write_suites_header(f)
-    results.each do |result_file|
-      lines = File.readlines(result_file).map(&:chomp)
-
-      raise "Empty test result file: #{result_file}" if lines.empty?
-
-      result_output = get_details(result_file, lines)
-      tests, failures, ignored = parse_test_summary(lines)
-      result_output[:counts][:total] = tests
-      result_output[:counts][:failed] = failures
-      result_output[:counts][:ignored] = ignored
-      result_output[:counts][:passed] = (result_output[:counts][:total] - result_output[:counts][:failed] - result_output[:counts][:ignored])
-
-      # use line[0] from the test output to get the test_file path and name
-      test_file_str = lines[0].tr('\\', '/')
-      test_file_str = test_file_str.split(':')
-      test_file = if test_file_str.length < 2
-                    result_file
-                  else
-                    test_file_str[0] + ':' + test_file_str[1]
-                  end
-      result_output[:source][:path] = File.dirname(test_file)
-      result_output[:source][:file] = File.basename(test_file)
-
-      # save result_output
-      @unit_name = File.basename(test_file, '.*')
-
-      write_suite_header(result_output[:counts], f)
-      write_failures(result_output, f)
-      write_tests(result_output, f)
-      write_ignored(result_output, f)
-      write_suite_footer(f)
-    end
-    write_suites_footer(f)
-    f.close
-  end
-
-  def usage(err_msg = nil)
-    puts "\nERROR: "
-    puts err_msg if err_msg
-    puts 'Usage: unity_to_junit.rb [options]'
-    puts ''
-    puts 'Specific options:'
-    puts '    -r, --results <dir>              Look for Unity Results files here.'
-    puts '    -p, --root_path <path>           Prepend this path to files in results.'
-    puts '    -o, --output <filename>          XML file to generate.'
-    puts ''
-    puts 'Common options:'
-    puts '    -h, --help                       Show this message'
-    puts '        --version                    Show version'
-
-    exit 1
-  end
-
-  protected
-
-  def get_details(_result_file, lines)
-    results = results_structure
-    lines.each do |line|
-      line = line.tr('\\', '/')
-      _src_file, src_line, test_name, status, msg = line.split(/:/)
-      case status
-      when 'IGNORE' then results[:ignores] << { test: test_name, line: src_line, message: msg }
-      when 'FAIL'   then results[:failures] << { test: test_name, line: src_line, message: msg }
-      when 'PASS'   then results[:successes] << { test: test_name, line: src_line, message: msg }
-      end
-    end
-    results
-  end
-
-  def parse_test_summary(summary)
-    raise "Couldn't parse test results: #{summary}" unless summary.find { |v| v =~ /(\d+) Tests (\d+) Failures (\d+) Ignored/ }
-
-    [Regexp.last_match(1).to_i, Regexp.last_match(2).to_i, Regexp.last_match(3).to_i]
-  end
-
-  private
-
-  def results_structure
-    {
-      source: { path: '', file: '' },
-      successes: [],
-      failures: [],
-      ignores: [],
-      counts: { total: 0, passed: 0, failed: 0, ignored: 0 },
-      stdout: []
-    }
-  end
-
-  def write_xml_header(stream)
-    stream.puts "<?xml version='1.0' encoding='utf-8' ?>"
-  end
-
-  def write_suites_header(stream)
-    stream.puts '<testsuites>'
-  end
-
-  def write_suite_header(counts, stream)
-    stream.puts "\t<testsuite errors=\"0\" skipped=\"#{counts[:ignored]}\" failures=\"#{counts[:failed]}\" tests=\"#{counts[:total]}\" name=\"unity\">"
-  end
-
-  def write_failures(results, stream)
-    result = results[:failures]
-    result.each do |item|
-      filename = File.join(results[:source][:path], File.basename(results[:source][:file], '.*'))
-      stream.puts "\t\t<testcase classname=\"#{@unit_name}\" name=\"#{item[:test]}\" time=\"0\">"
-      stream.puts "\t\t\t<failure message=\"#{item[:message]}\" type=\"Assertion\"/>"
-      stream.puts "\t\t\t<system-err>&#xD;[File] #{filename}&#xD;[Line] #{item[:line]}&#xD;</system-err>"
-      stream.puts "\t\t</testcase>"
-    end
-  end
-
-  def write_tests(results, stream)
-    result = results[:successes]
-    result.each do |item|
-      stream.puts "\t\t<testcase classname=\"#{@unit_name}\" name=\"#{item[:test]}\" time=\"0\" />"
-    end
-  end
-
-  def write_ignored(results, stream)
-    result = results[:ignores]
-    result.each do |item|
-      filename = File.join(results[:source][:path], File.basename(results[:source][:file], '.*'))
-      puts "Writing ignored tests for test harness: #{filename}"
-      stream.puts "\t\t<testcase classname=\"#{@unit_name}\" name=\"#{item[:test]}\" time=\"0\">"
-      stream.puts "\t\t\t<skipped message=\"#{item[:message]}\" type=\"Assertion\"/>"
-      stream.puts "\t\t\t<system-err>&#xD;[File] #{filename}&#xD;[Line] #{item[:line]}&#xD;</system-err>"
-      stream.puts "\t\t</testcase>"
-    end
-  end
-
-  def write_suite_footer(stream)
-    stream.puts "\t</testsuite>"
-  end
-
-  def write_suites_footer(stream)
-    stream.puts '</testsuites>'
-  end
-end
-
-if $0 == __FILE__
-  # parse out the command options
-  options = ArgvParser.parse(ARGV)
-
-  # create an instance to work with
-  utj = UnityToJUnit.new
-  begin
-    # look in the specified or current directory for result files
-    targets = "#{options.results_dir.tr('\\', '/')}**/*.test*"
-
-    results = Dir[targets]
-
-    raise "No *.testpass, *.testfail, or *.testresults files found in '#{targets}'" if results.empty?
-
-    utj.targets = results
-
-    # set the root path
-    utj.root = options.root_path
-
-    # set the output XML file name
-    # puts "Output File from options: #{options.out_file}"
-    utj.out_file = options.out_file
-
-    # run the summarizer
-    puts utj.run
-  rescue StandardError => e
-    utj.usage e.message
-  end
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/test_file_filter.rb b/test/vendor/ceedling/vendor/unity/auto/test_file_filter.rb
deleted file mode 100644
index 5c3a79fc6..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/test_file_filter.rb
+++ /dev/null
@@ -1,25 +0,0 @@
-# ==========================================
-#   Unity Project - A Test Framework for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-require'yaml'
-
-module RakefileHelpers
-  class TestFileFilter
-    def initialize(all_files = false)
-      @all_files = all_files
-
-      return unless @all_files
-      return unless File.exist?('test_file_filter.yml')
-
-      filters = YAML.load_file('test_file_filter.yml')
-      @all_files = filters[:all_files]
-      @only_files = filters[:only_files]
-      @exclude_files = filters[:exclude_files]
-    end
-
-    attr_accessor :all_files, :only_files, :exclude_files
-  end
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/type_sanitizer.rb b/test/vendor/ceedling/vendor/unity/auto/type_sanitizer.rb
deleted file mode 100644
index dafb8826e..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/type_sanitizer.rb
+++ /dev/null
@@ -1,6 +0,0 @@
-module TypeSanitizer
-  def self.sanitize_c_identifier(unsanitized)
-    # convert filename to valid C identifier by replacing invalid chars with '_'
-    unsanitized.gsub(/[-\/\\\.\,\s]/, '_')
-  end
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py b/test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py
deleted file mode 100644
index 00c0da8cc..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py
+++ /dev/null
@@ -1,139 +0,0 @@
-#! python3
-# ==========================================
-#   Unity Project - A Test Framework for C
-#   Copyright (c) 2015 Alexander Mueller / XelaRellum@web.de
-#   [Released under MIT License. Please refer to license.txt for details]
-#   Based on the ruby script by  Mike Karlesky, Mark VanderVoord, Greg Williams
-# ==========================================
-import sys
-import os
-import re
-from glob import glob
-
-class UnityTestSummary:
-    def __init__(self):
-        self.report = ''
-        self.total_tests = 0
-        self.failures = 0
-        self.ignored = 0
-
-    def run(self):
-        # Clean up result file names
-        results = []
-        for target in self.targets:
-            results.append(target.replace('\\', '/'))
-
-        # Dig through each result file, looking for details on pass/fail:
-        failure_output = []
-        ignore_output = []
-
-        for result_file in results:
-            lines = list(map(lambda line: line.rstrip(), open(result_file, "r").read().split('\n')))
-            if len(lines) == 0:
-                raise Exception("Empty test result file: %s" % result_file)
-
-            details = self.get_details(result_file, lines)
-            failures = details['failures']
-            ignores = details['ignores']
-            if len(failures) > 0: failure_output.append('\n'.join(failures))
-            if len(ignores) > 0: ignore_output.append('n'.join(ignores))
-            tests,failures,ignored = self.parse_test_summary('\n'.join(lines))
-            self.total_tests += tests
-            self.failures += failures
-            self.ignored += ignored
-
-        if self.ignored > 0:
-            self.report += "\n"
-            self.report += "--------------------------\n"
-            self.report += "UNITY IGNORED TEST SUMMARY\n"
-            self.report += "--------------------------\n"
-            self.report += "\n".join(ignore_output)
-
-        if self.failures > 0:
-            self.report += "\n"
-            self.report += "--------------------------\n"
-            self.report += "UNITY FAILED TEST SUMMARY\n"
-            self.report += "--------------------------\n"
-            self.report += '\n'.join(failure_output)
-
-        self.report += "\n"
-        self.report += "--------------------------\n"
-        self.report += "OVERALL UNITY TEST SUMMARY\n"
-        self.report += "--------------------------\n"
-        self.report += "{total_tests} TOTAL TESTS {failures} TOTAL FAILURES {ignored} IGNORED\n".format(total_tests = self.total_tests, failures=self.failures, ignored=self.ignored)
-        self.report += "\n"
-
-        return self.report
-
-    def set_targets(self, target_array):
-            self.targets = target_array
-
-    def set_root_path(self, path):
-        self.root = path
-
-    def usage(self, err_msg=None):
-        print("\nERROR: ")
-        if err_msg:
-            print(err_msg)
-        print("\nUsage: unity_test_summary.py result_file_directory/ root_path/")
-        print("     result_file_directory - The location of your results files.")
-        print("                             Defaults to current directory if not specified.")
-        print("                             Should end in / if specified.")
-        print("     root_path - Helpful for producing more verbose output if using relative paths.")
-        sys.exit(1)
-
-    def get_details(self, result_file, lines):
-        results = { 'failures': [], 'ignores': [], 'successes': [] }
-        for line in lines:
-            parts = line.split(':')
-            if len(parts) == 5:
-                src_file,src_line,test_name,status,msg = parts
-            elif len(parts) == 4:
-                src_file,src_line,test_name,status = parts
-                msg = ''
-            else:
-                continue
-            if len(self.root) > 0:
-                line_out = "%s%s" % (self.root, line)
-            else:
-                line_out = line
-            if status == 'IGNORE':
-                results['ignores'].append(line_out)
-            elif status == 'FAIL':
-                results['failures'].append(line_out)
-            elif status == 'PASS':
-                results['successes'].append(line_out)
-        return results
-
-    def parse_test_summary(self, summary):
-        m = re.search(r"([0-9]+) Tests ([0-9]+) Failures ([0-9]+) Ignored", summary)
-        if not m:
-            raise Exception("Couldn't parse test results: %s" % summary)
-
-        return int(m.group(1)), int(m.group(2)), int(m.group(3))
-
-
-if __name__ == '__main__':
-  uts = UnityTestSummary()
-  try:
-    #look in the specified or current directory for result files
-    if len(sys.argv) > 1:
-        targets_dir = sys.argv[1]
-    else:
-        targets_dir = './'
-    targets = list(map(lambda x: x.replace('\\', '/'), glob(targets_dir + '**/*.test*', recursive=True)))
-    if len(targets) == 0:
-        raise Exception("No *.testpass or *.testfail files found in '%s'" % targets_dir)
-    uts.set_targets(targets)
-
-    #set the root path
-    if len(sys.argv) > 2:
-        root_path = sys.argv[2]
-    else:
-        root_path = os.path.split(__file__)[0]
-    uts.set_root_path(root_path)
-
-    #run the summarizer
-    print(uts.run())
-  except Exception as e:
-    uts.usage(e)
diff --git a/test/vendor/ceedling/vendor/unity/auto/unity_test_summary.rb b/test/vendor/ceedling/vendor/unity/auto/unity_test_summary.rb
deleted file mode 100644
index b3fe8a699..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/unity_test_summary.rb
+++ /dev/null
@@ -1,135 +0,0 @@
-# ==========================================
-#   Unity Project - A Test Framework for C
-#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
-#   [Released under MIT License. Please refer to license.txt for details]
-# ==========================================
-
-# !/usr/bin/ruby
-#
-# unity_test_summary.rb
-#
-require 'fileutils'
-require 'set'
-
-class UnityTestSummary
-  include FileUtils::Verbose
-
-  attr_reader :report, :total_tests, :failures, :ignored
-  attr_writer :targets, :root
-
-  def initialize(_opts = {})
-    @report = ''
-    @total_tests = 0
-    @failures = 0
-    @ignored = 0
-  end
-
-  def run
-    # Clean up result file names
-    results = @targets.map { |target| target.tr('\\', '/') }
-
-    # Dig through each result file, looking for details on pass/fail:
-    failure_output = []
-    ignore_output = []
-
-    results.each do |result_file|
-      lines = File.readlines(result_file).map(&:chomp)
-
-      raise "Empty test result file: #{result_file}" if lines.empty?
-
-      output = get_details(result_file, lines)
-      failure_output << output[:failures] unless output[:failures].empty?
-      ignore_output  << output[:ignores]  unless output[:ignores].empty?
-      tests, failures, ignored = parse_test_summary(lines)
-      @total_tests += tests
-      @failures += failures
-      @ignored += ignored
-    end
-
-    if @ignored > 0
-      @report += "\n"
-      @report += "--------------------------\n"
-      @report += "UNITY IGNORED TEST SUMMARY\n"
-      @report += "--------------------------\n"
-      @report += ignore_output.flatten.join("\n")
-    end
-
-    if @failures > 0
-      @report += "\n"
-      @report += "--------------------------\n"
-      @report += "UNITY FAILED TEST SUMMARY\n"
-      @report += "--------------------------\n"
-      @report += failure_output.flatten.join("\n")
-    end
-
-    @report += "\n"
-    @report += "--------------------------\n"
-    @report += "OVERALL UNITY TEST SUMMARY\n"
-    @report += "--------------------------\n"
-    @report += "#{@total_tests} TOTAL TESTS #{@failures} TOTAL FAILURES #{@ignored} IGNORED\n"
-    @report += "\n"
-  end
-
-  def usage(err_msg = nil)
-    puts "\nERROR: "
-    puts err_msg if err_msg
-    puts "\nUsage: unity_test_summary.rb result_file_directory/ root_path/"
-    puts '     result_file_directory - The location of your results files.'
-    puts '                             Defaults to current directory if not specified.'
-    puts '                             Should end in / if specified.'
-    puts '     root_path - Helpful for producing more verbose output if using relative paths.'
-    exit 1
-  end
-
-  protected
-
-  def get_details(_result_file, lines)
-    results = { failures: [], ignores: [], successes: [] }
-    lines.each do |line|
-      _src_file, _src_line, _test_name, status, _msg = line.split(/:/)
-      line_out = (@root && (@root != 0) ? "#{@root}#{line}" : line).gsub(/\//, '\\')
-      case status
-      when 'IGNORE' then results[:ignores]   << line_out
-      when 'FAIL'   then results[:failures]  << line_out
-      when 'PASS'   then results[:successes] << line_out
-      end
-    end
-    results
-  end
-
-  def parse_test_summary(summary)
-    raise "Couldn't parse test results: #{summary}" unless summary.find { |v| v =~ /(\d+) Tests (\d+) Failures (\d+) Ignored/ }
-
-    [Regexp.last_match(1).to_i, Regexp.last_match(2).to_i, Regexp.last_match(3).to_i]
-  end
-end
-
-if $0 == __FILE__
-
-  # parse out the command options
-  opts, args = ARGV.partition { |v| v =~ /^--\w+/ }
-  opts.map! { |v| v[2..-1].to_sym }
-
-  # create an instance to work with
-  uts = UnityTestSummary.new(opts)
-
-  begin
-    # look in the specified or current directory for result files
-    args[0] ||= './'
-    targets = "#{ARGV[0].tr('\\', '/')}**/*.test*"
-    results = Dir[targets]
-
-    raise "No *.testpass, *.testfail, or *.testresults files found in '#{targets}'" if results.empty?
-
-    uts.targets = results
-
-    # set the root path
-    args[1] ||= Dir.pwd + '/'
-    uts.root = ARGV[1]
-
-    # run the summarizer
-    puts uts.run
-  rescue StandardError => e
-    uts.usage e.message
-  end
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py b/test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py
deleted file mode 100644
index 71dd56888..000000000
--- a/test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py
+++ /dev/null
@@ -1,146 +0,0 @@
-import sys
-import os
-from glob import glob
-
-from pyparsing import *
-from junit_xml import TestSuite, TestCase
-
-
-class UnityTestSummary:
-    def __init__(self):
-        self.report = ''
-        self.total_tests = 0
-        self.failures = 0
-        self.ignored = 0
-        self.targets = 0
-        self.root = None
-        self.test_suites = dict()
-
-    def run(self):
-        # Clean up result file names
-        results = []
-        for target in self.targets:
-            results.append(target.replace('\\', '/'))
-
-        # Dig through each result file, looking for details on pass/fail:
-        for result_file in results:
-            lines = list(map(lambda line: line.rstrip(), open(result_file, "r").read().split('\n')))
-            if len(lines) == 0:
-                raise Exception("Empty test result file: %s" % result_file)
-
-            # define an expression for your file reference
-            entry_one = Combine(
-                oneOf(list(alphas)) + ':/' +
-                Word(alphanums + '_-./'))
-
-            entry_two = Word(printables + ' ', excludeChars=':')
-            entry = entry_one | entry_two
-
-            delimiter = Literal(':').suppress()
-            tc_result_line = Group(entry.setResultsName('tc_file_name') + delimiter + entry.setResultsName(
-                'tc_line_nr') + delimiter + entry.setResultsName('tc_name') + delimiter + entry.setResultsName(
-                'tc_status') + Optional(
-                delimiter + entry.setResultsName('tc_msg'))).setResultsName("tc_line")
-
-            eol = LineEnd().suppress()
-            sol = LineStart().suppress()
-            blank_line = sol + eol
-
-            tc_summary_line = Group(Word(nums).setResultsName("num_of_tests") + "Tests" + Word(nums).setResultsName(
-                "num_of_fail") + "Failures" + Word(nums).setResultsName("num_of_ignore") + "Ignored").setResultsName(
-                "tc_summary")
-            tc_end_line = Or(Literal("FAIL"), Literal('Ok')).setResultsName("tc_result")
-
-            # run it and see...
-            pp1 = tc_result_line | Optional(tc_summary_line | tc_end_line)
-            pp1.ignore(blank_line | OneOrMore("-"))
-
-            result = list()
-            for l in lines:
-                result.append((pp1.parseString(l)).asDict())
-            # delete empty results
-            result = filter(None, result)
-
-            tc_list = list()
-            for r in result:
-                if 'tc_line' in r:
-                    tmp_tc_line = r['tc_line']
-
-                    # get only the file name which will be used as the classname
-                    file_name = tmp_tc_line['tc_file_name'].split('\\').pop().split('/').pop().rsplit('.', 1)[0]
-                    tmp_tc = TestCase(name=tmp_tc_line['tc_name'], classname=file_name)
-                    if 'tc_status' in tmp_tc_line:
-                        if str(tmp_tc_line['tc_status']) == 'IGNORE':
-                            if 'tc_msg' in tmp_tc_line:
-                                tmp_tc.add_skipped_info(message=tmp_tc_line['tc_msg'],
-                                                        output=r'[File]={0}, [Line]={1}'.format(
-                                                            tmp_tc_line['tc_file_name'], tmp_tc_line['tc_line_nr']))
-                            else:
-                                tmp_tc.add_skipped_info(message=" ")
-                        elif str(tmp_tc_line['tc_status']) == 'FAIL':
-                            if 'tc_msg' in tmp_tc_line:
-                                tmp_tc.add_failure_info(message=tmp_tc_line['tc_msg'],
-                                                        output=r'[File]={0}, [Line]={1}'.format(
-                                                            tmp_tc_line['tc_file_name'], tmp_tc_line['tc_line_nr']))
-                            else:
-                                tmp_tc.add_failure_info(message=" ")
-
-                    tc_list.append((str(result_file), tmp_tc))
-
-            for k, v in tc_list:
-                try:
-                    self.test_suites[k].append(v)
-                except KeyError:
-                    self.test_suites[k] = [v]
-        ts = []
-        for suite_name in self.test_suites:
-            ts.append(TestSuite(suite_name, self.test_suites[suite_name]))
-
-        with open('result.xml', 'w') as f:
-            TestSuite.to_file(f, ts, prettyprint='True', encoding='utf-8')
-
-        return self.report
-
-    def set_targets(self, target_array):
-        self.targets = target_array
-
-    def set_root_path(self, path):
-        self.root = path
-
-    @staticmethod
-    def usage(err_msg=None):
-        print("\nERROR: ")
-        if err_msg:
-            print(err_msg)
-        print("\nUsage: unity_test_summary.py result_file_directory/ root_path/")
-        print("     result_file_directory - The location of your results files.")
-        print("                             Defaults to current directory if not specified.")
-        print("                             Should end in / if specified.")
-        print("     root_path - Helpful for producing more verbose output if using relative paths.")
-        sys.exit(1)
-
-
-if __name__ == '__main__':
-    uts = UnityTestSummary()
-    try:
-        # look in the specified or current directory for result files
-        if len(sys.argv) > 1:
-            targets_dir = sys.argv[1]
-        else:
-            targets_dir = './'
-        targets = list(map(lambda x: x.replace('\\', '/'), glob(targets_dir + '*.test*')))
-        if len(targets) == 0:
-            raise Exception("No *.testpass or *.testfail files found in '%s'" % targets_dir)
-        uts.set_targets(targets)
-
-        # set the root path
-        if len(sys.argv) > 2:
-            root_path = sys.argv[2]
-        else:
-            root_path = os.path.split(__file__)[0]
-        uts.set_root_path(root_path)
-
-        # run the summarizer
-        print(uts.run())
-    except Exception as e:
-        UnityTestSummary.usage(e)
diff --git a/test/vendor/ceedling/vendor/unity/release/build.info b/test/vendor/ceedling/vendor/unity/release/build.info
deleted file mode 100644
index 56d591286..000000000
--- a/test/vendor/ceedling/vendor/unity/release/build.info
+++ /dev/null
@@ -1,2 +0,0 @@
-122
-
diff --git a/test/vendor/ceedling/vendor/unity/release/version.info b/test/vendor/ceedling/vendor/unity/release/version.info
deleted file mode 100644
index cf12b30d2..000000000
--- a/test/vendor/ceedling/vendor/unity/release/version.info
+++ /dev/null
@@ -1,2 +0,0 @@
-2.4.3
-
diff --git a/test/vendor/ceedling/vendor/unity/src/CMakeLists.txt b/test/vendor/ceedling/vendor/unity/src/CMakeLists.txt
deleted file mode 100644
index c747cb0ae..000000000
--- a/test/vendor/ceedling/vendor/unity/src/CMakeLists.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-###################################################################################
-#                                                                                 #
-# NAME: CMakeLists.txt                                                            #
-#                                                                                 #
-# AUTHOR: Mike Karlesky, Mark VanderVoord, Greg Williams.                         #
-# WRITTEN BY: Michael Brockus.                                                    #
-#                                                                                 #
-# License: MIT                                                                    #
-#                                                                                 #
-###################################################################################
-cmake_minimum_required(VERSION 3.0 FATAL_ERROR)
-
-
-add_library(unity STATIC "unity.c")
-
-install(TARGETS unity EXPORT unityConfig
-    ARCHIVE  DESTINATION "${CMAKE_CURRENT_SOURCE_DIR}/${CMAKE_INSTALL_LIBDIR}"
-    LIBRARY  DESTINATION "${CMAKE_CURRENT_SOURCE_DIR}/${CMAKE_INSTALL_LIBDIR}"
-    RUNTIME  DESTINATION "${CMAKE_CURRENT_SOURCE_DIR}/${CMAKE_INSTALL_BINDIR}"
-    INCLUDES DESTINATION "${CMAKE_INSTALL_LIBDIR}")
-
-
diff --git a/test/vendor/ceedling/vendor/unity/src/meson.build b/test/vendor/ceedling/vendor/unity/src/meson.build
deleted file mode 100644
index f5e014653..000000000
--- a/test/vendor/ceedling/vendor/unity/src/meson.build
+++ /dev/null
@@ -1,16 +0,0 @@
-###################################################################################
-#                                                                                 #
-# NAME: meson.build                                                               #
-#                                                                                 #
-# AUTHOR: Mike Karlesky, Mark VanderVoord, Greg Williams.                         #
-# WRITTEN BY: Michael Brockus.                                                    #
-#                                                                                 #
-# License: MIT                                                                    #
-#                                                                                 #
-###################################################################################
-
-unity_dir = include_directories('.')
-
-unity_lib = static_library(meson.project_name(), 
-    sources: ['unity.c'],
-    include_directories: unity_dir)
diff --git a/test/vendor/ceedling/vendor/unity/src/unity.c b/test/vendor/ceedling/vendor/unity/src/unity.c
deleted file mode 100644
index c7be02cc6..000000000
--- a/test/vendor/ceedling/vendor/unity/src/unity.c
+++ /dev/null
@@ -1,2085 +0,0 @@
-/* =========================================================================
-    Unity Project - A Test Framework for C
-    Copyright (c) 2007-19 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-============================================================================ */
-
-#include "unity.h"
-#include <stddef.h>
-
-#ifdef AVR
-#include <avr/pgmspace.h>
-#else
-#define PROGMEM
-#endif
-
-/* If omitted from header, declare overrideable prototypes here so they're ready for use */
-#ifdef UNITY_OMIT_OUTPUT_CHAR_HEADER_DECLARATION
-void UNITY_OUTPUT_CHAR(int);
-#endif
-
-/* Helpful macros for us to use here in Assert functions */
-#define UNITY_FAIL_AND_BAIL   { Unity.CurrentTestFailed  = 1; UNITY_OUTPUT_FLUSH(); TEST_ABORT(); }
-#define UNITY_IGNORE_AND_BAIL { Unity.CurrentTestIgnored = 1; UNITY_OUTPUT_FLUSH(); TEST_ABORT(); }
-#define RETURN_IF_FAIL_OR_IGNORE if (Unity.CurrentTestFailed || Unity.CurrentTestIgnored) return
-
-struct UNITY_STORAGE_T Unity;
-
-#ifdef UNITY_OUTPUT_COLOR
-const char PROGMEM UnityStrOk[]                            = "\033[42mOK\033[00m";
-const char PROGMEM UnityStrPass[]                          = "\033[42mPASS\033[00m";
-const char PROGMEM UnityStrFail[]                          = "\033[41mFAIL\033[00m";
-const char PROGMEM UnityStrIgnore[]                        = "\033[43mIGNORE\033[00m";
-#else
-const char PROGMEM UnityStrOk[]                            = "OK";
-const char PROGMEM UnityStrPass[]                          = "PASS";
-const char PROGMEM UnityStrFail[]                          = "FAIL";
-const char PROGMEM UnityStrIgnore[]                        = "IGNORE";
-#endif
-static const char PROGMEM UnityStrNull[]                   = "NULL";
-static const char PROGMEM UnityStrSpacer[]                 = ". ";
-static const char PROGMEM UnityStrExpected[]               = " Expected ";
-static const char PROGMEM UnityStrWas[]                    = " Was ";
-static const char PROGMEM UnityStrGt[]                     = " to be greater than ";
-static const char PROGMEM UnityStrLt[]                     = " to be less than ";
-static const char PROGMEM UnityStrOrEqual[]                = "or equal to ";
-static const char PROGMEM UnityStrElement[]                = " Element ";
-static const char PROGMEM UnityStrByte[]                   = " Byte ";
-static const char PROGMEM UnityStrMemory[]                 = " Memory Mismatch.";
-static const char PROGMEM UnityStrDelta[]                  = " Values Not Within Delta ";
-static const char PROGMEM UnityStrPointless[]              = " You Asked Me To Compare Nothing, Which Was Pointless.";
-static const char PROGMEM UnityStrNullPointerForExpected[] = " Expected pointer to be NULL";
-static const char PROGMEM UnityStrNullPointerForActual[]   = " Actual pointer was NULL";
-#ifndef UNITY_EXCLUDE_FLOAT
-static const char PROGMEM UnityStrNot[]                    = "Not ";
-static const char PROGMEM UnityStrInf[]                    = "Infinity";
-static const char PROGMEM UnityStrNegInf[]                 = "Negative Infinity";
-static const char PROGMEM UnityStrNaN[]                    = "NaN";
-static const char PROGMEM UnityStrDet[]                    = "Determinate";
-static const char PROGMEM UnityStrInvalidFloatTrait[]      = "Invalid Float Trait";
-#endif
-const char PROGMEM UnityStrErrShorthand[]                  = "Unity Shorthand Support Disabled";
-const char PROGMEM UnityStrErrFloat[]                      = "Unity Floating Point Disabled";
-const char PROGMEM UnityStrErrDouble[]                     = "Unity Double Precision Disabled";
-const char PROGMEM UnityStrErr64[]                         = "Unity 64-bit Support Disabled";
-static const char PROGMEM UnityStrBreaker[]                = "-----------------------";
-static const char PROGMEM UnityStrResultsTests[]           = " Tests ";
-static const char PROGMEM UnityStrResultsFailures[]        = " Failures ";
-static const char PROGMEM UnityStrResultsIgnored[]         = " Ignored ";
-static const char PROGMEM UnityStrDetail1Name[]            = UNITY_DETAIL1_NAME " ";
-static const char PROGMEM UnityStrDetail2Name[]            = " " UNITY_DETAIL2_NAME " ";
-
-/*-----------------------------------------------
- * Pretty Printers & Test Result Output Handlers
- *-----------------------------------------------*/
-
-/*-----------------------------------------------*/
-/* Local helper function to print characters. */
-static void UnityPrintChar(const char* pch)
-{
-    /* printable characters plus CR & LF are printed */
-    if ((*pch <= 126) && (*pch >= 32))
-    {
-        UNITY_OUTPUT_CHAR(*pch);
-    }
-    /* write escaped carriage returns */
-    else if (*pch == 13)
-    {
-        UNITY_OUTPUT_CHAR('\\');
-        UNITY_OUTPUT_CHAR('r');
-    }
-    /* write escaped line feeds */
-    else if (*pch == 10)
-    {
-        UNITY_OUTPUT_CHAR('\\');
-        UNITY_OUTPUT_CHAR('n');
-    }
-    /* unprintable characters are shown as codes */
-    else
-    {
-        UNITY_OUTPUT_CHAR('\\');
-        UNITY_OUTPUT_CHAR('x');
-        UnityPrintNumberHex((UNITY_UINT)*pch, 2);
-    }
-}
-
-/*-----------------------------------------------*/
-/* Local helper function to print ANSI escape strings e.g. "\033[42m". */
-#ifdef UNITY_OUTPUT_COLOR
-static UNITY_UINT UnityPrintAnsiEscapeString(const char* string)
-{
-    const char* pch = string;
-    UNITY_UINT count = 0;
-
-    while (*pch && (*pch != 'm'))
-    {
-        UNITY_OUTPUT_CHAR(*pch);
-        pch++;
-        count++;
-    }
-    UNITY_OUTPUT_CHAR('m');
-    count++;
-
-    return count;
-}
-#endif
-
-/*-----------------------------------------------*/
-void UnityPrint(const char* string)
-{
-    const char* pch = string;
-
-    if (pch != NULL)
-    {
-        while (*pch)
-        {
-#ifdef UNITY_OUTPUT_COLOR
-            /* print ANSI escape code */
-            if ((*pch == 27) && (*(pch + 1) == '['))
-            {
-                pch += UnityPrintAnsiEscapeString(pch);
-                continue;
-            }
-#endif
-            UnityPrintChar(pch);
-            pch++;
-        }
-    }
-}
-
-/*-----------------------------------------------*/
-#ifdef UNITY_INCLUDE_PRINT_FORMATTED
-void UnityPrintFormatted(const char* format, ...)
-{
-    const char* pch = format;
-    va_list va;
-    va_start(va, format);
-
-    if (pch != NULL)
-    {
-        while (*pch)
-        {
-            /* format identification character */
-            if (*pch == '%')
-            {
-                pch++;
-
-                if (pch != NULL)
-                {
-                    switch (*pch)
-                    {
-                        case 'd':
-                        case 'i':
-                            {
-                                const int number = va_arg(va, int);
-                                UnityPrintNumber((UNITY_INT)number);
-                                break;
-                            }
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-                        case 'f':
-                        case 'g':
-                            {
-                                const double number = va_arg(va, double);
-                                UnityPrintFloat((UNITY_DOUBLE)number);
-                                break;
-                            }
-#endif
-                        case 'u':
-                            {
-                                const unsigned int number = va_arg(va, unsigned int);
-                                UnityPrintNumberUnsigned((UNITY_UINT)number);
-                                break;
-                            }
-                        case 'b':
-                            {
-                                const unsigned int number = va_arg(va, unsigned int);
-                                const UNITY_UINT mask = (UNITY_UINT)0 - (UNITY_UINT)1;
-                                UNITY_OUTPUT_CHAR('0');
-                                UNITY_OUTPUT_CHAR('b');
-                                UnityPrintMask(mask, (UNITY_UINT)number);
-                                break;
-                            }
-                        case 'x':
-                        case 'X':
-                        case 'p':
-                            {
-                                const unsigned int number = va_arg(va, unsigned int);
-                                UNITY_OUTPUT_CHAR('0');
-                                UNITY_OUTPUT_CHAR('x');
-                                UnityPrintNumberHex((UNITY_UINT)number, 8);
-                                break;
-                            }
-                        case 'c':
-                            {
-                                const int ch = va_arg(va, int);
-                                UnityPrintChar((const char *)&ch);
-                                break;
-                            }
-                        case 's':
-                            {
-                                const char * string = va_arg(va, const char *);
-                                UnityPrint(string);
-                                break;
-                            }
-                        case '%':
-                            {
-                                UnityPrintChar(pch);
-                                break;
-                            }
-                        default:
-                            {
-                                /* print the unknown format character */
-                                UNITY_OUTPUT_CHAR('%');
-                                UnityPrintChar(pch);
-                                break;
-                            }
-                    }
-                }
-            }
-#ifdef UNITY_OUTPUT_COLOR
-            /* print ANSI escape code */
-            else if ((*pch == 27) && (*(pch + 1) == '['))
-            {
-                pch += UnityPrintAnsiEscapeString(pch);
-                continue;
-            }
-#endif
-            else if (*pch == '\n')
-            {
-                UNITY_PRINT_EOL();
-            }
-            else
-            {
-                UnityPrintChar(pch);
-            }
-
-            pch++;
-        }
-    }
-
-    va_end(va);
-}
-#endif /* ! UNITY_INCLUDE_PRINT_FORMATTED */
-
-/*-----------------------------------------------*/
-void UnityPrintLen(const char* string, const UNITY_UINT32 length)
-{
-    const char* pch = string;
-
-    if (pch != NULL)
-    {
-        while (*pch && ((UNITY_UINT32)(pch - string) < length))
-        {
-            /* printable characters plus CR & LF are printed */
-            if ((*pch <= 126) && (*pch >= 32))
-            {
-                UNITY_OUTPUT_CHAR(*pch);
-            }
-            /* write escaped carriage returns */
-            else if (*pch == 13)
-            {
-                UNITY_OUTPUT_CHAR('\\');
-                UNITY_OUTPUT_CHAR('r');
-            }
-            /* write escaped line feeds */
-            else if (*pch == 10)
-            {
-                UNITY_OUTPUT_CHAR('\\');
-                UNITY_OUTPUT_CHAR('n');
-            }
-            /* unprintable characters are shown as codes */
-            else
-            {
-                UNITY_OUTPUT_CHAR('\\');
-                UNITY_OUTPUT_CHAR('x');
-                UnityPrintNumberHex((UNITY_UINT)*pch, 2);
-            }
-            pch++;
-        }
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityPrintNumberByStyle(const UNITY_INT number, const UNITY_DISPLAY_STYLE_T style)
-{
-    if ((style & UNITY_DISPLAY_RANGE_INT) == UNITY_DISPLAY_RANGE_INT)
-    {
-        if (style == UNITY_DISPLAY_STYLE_CHAR)
-        {
-            /* printable characters plus CR & LF are printed */
-            UNITY_OUTPUT_CHAR('\'');
-            if ((number <= 126) && (number >= 32))
-            {
-                UNITY_OUTPUT_CHAR((int)number);
-            }
-            /* write escaped carriage returns */
-            else if (number == 13)
-            {
-                UNITY_OUTPUT_CHAR('\\');
-                UNITY_OUTPUT_CHAR('r');
-            }
-            /* write escaped line feeds */
-            else if (number == 10)
-            {
-                UNITY_OUTPUT_CHAR('\\');
-                UNITY_OUTPUT_CHAR('n');
-            }
-            /* unprintable characters are shown as codes */
-            else
-            {
-                UNITY_OUTPUT_CHAR('\\');
-                UNITY_OUTPUT_CHAR('x');
-                UnityPrintNumberHex((UNITY_UINT)number, 2);
-            }
-            UNITY_OUTPUT_CHAR('\'');
-        }
-        else
-        {
-            UnityPrintNumber(number);
-        }
-    }
-    else if ((style & UNITY_DISPLAY_RANGE_UINT) == UNITY_DISPLAY_RANGE_UINT)
-    {
-        UnityPrintNumberUnsigned((UNITY_UINT)number);
-    }
-    else
-    {
-        UNITY_OUTPUT_CHAR('0');
-        UNITY_OUTPUT_CHAR('x');
-        UnityPrintNumberHex((UNITY_UINT)number, (char)((style & 0xF) * 2));
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityPrintNumber(const UNITY_INT number_to_print)
-{
-    UNITY_UINT number = (UNITY_UINT)number_to_print;
-
-    if (number_to_print < 0)
-    {
-        /* A negative number, including MIN negative */
-        UNITY_OUTPUT_CHAR('-');
-        number = (~number) + 1;
-    }
-    UnityPrintNumberUnsigned(number);
-}
-
-/*-----------------------------------------------
- * basically do an itoa using as little ram as possible */
-void UnityPrintNumberUnsigned(const UNITY_UINT number)
-{
-    UNITY_UINT divisor = 1;
-
-    /* figure out initial divisor */
-    while (number / divisor > 9)
-    {
-        divisor *= 10;
-    }
-
-    /* now mod and print, then divide divisor */
-    do
-    {
-        UNITY_OUTPUT_CHAR((char)('0' + (number / divisor % 10)));
-        divisor /= 10;
-    } while (divisor > 0);
-}
-
-/*-----------------------------------------------*/
-void UnityPrintNumberHex(const UNITY_UINT number, const char nibbles_to_print)
-{
-    int nibble;
-    char nibbles = nibbles_to_print;
-
-    if ((unsigned)nibbles > UNITY_MAX_NIBBLES)
-    {
-        nibbles = UNITY_MAX_NIBBLES;
-    }
-
-    while (nibbles > 0)
-    {
-        nibbles--;
-        nibble = (int)(number >> (nibbles * 4)) & 0x0F;
-        if (nibble <= 9)
-        {
-            UNITY_OUTPUT_CHAR((char)('0' + nibble));
-        }
-        else
-        {
-            UNITY_OUTPUT_CHAR((char)('A' - 10 + nibble));
-        }
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityPrintMask(const UNITY_UINT mask, const UNITY_UINT number)
-{
-    UNITY_UINT current_bit = (UNITY_UINT)1 << (UNITY_INT_WIDTH - 1);
-    UNITY_INT32 i;
-
-    for (i = 0; i < UNITY_INT_WIDTH; i++)
-    {
-        if (current_bit & mask)
-        {
-            if (current_bit & number)
-            {
-                UNITY_OUTPUT_CHAR('1');
-            }
-            else
-            {
-                UNITY_OUTPUT_CHAR('0');
-            }
-        }
-        else
-        {
-            UNITY_OUTPUT_CHAR('X');
-        }
-        current_bit = current_bit >> 1;
-    }
-}
-
-/*-----------------------------------------------*/
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-/*
- * This function prints a floating-point value in a format similar to
- * printf("%.7g") on a single-precision machine or printf("%.9g") on a
- * double-precision machine.  The 7th digit won't always be totally correct
- * in single-precision operation (for that level of accuracy, a more
- * complicated algorithm would be needed).
- */
-void UnityPrintFloat(const UNITY_DOUBLE input_number)
-{
-#ifdef UNITY_INCLUDE_DOUBLE
-    static const int sig_digits = 9;
-    static const UNITY_INT32 min_scaled = 100000000;
-    static const UNITY_INT32 max_scaled = 1000000000;
-#else
-    static const int sig_digits = 7;
-    static const UNITY_INT32 min_scaled = 1000000;
-    static const UNITY_INT32 max_scaled = 10000000;
-#endif
-
-    UNITY_DOUBLE number = input_number;
-
-    /* print minus sign (does not handle negative zero) */
-    if (number < 0.0f)
-    {
-        UNITY_OUTPUT_CHAR('-');
-        number = -number;
-    }
-
-    /* handle zero, NaN, and +/- infinity */
-    if (number == 0.0f)
-    {
-        UnityPrint("0");
-    }
-    else if (isnan(number))
-    {
-        UnityPrint("nan");
-    }
-    else if (isinf(number))
-    {
-        UnityPrint("inf");
-    }
-    else
-    {
-        UNITY_INT32 n_int = 0, n;
-        int exponent = 0;
-        int decimals, digits;
-        char buf[16] = {0};
-
-        /*
-         * Scale up or down by powers of 10.  To minimize rounding error,
-         * start with a factor/divisor of 10^10, which is the largest
-         * power of 10 that can be represented exactly.  Finally, compute
-         * (exactly) the remaining power of 10 and perform one more
-         * multiplication or division.
-         */
-        if (number < 1.0f)
-        {
-            UNITY_DOUBLE factor = 1.0f;
-
-            while (number < (UNITY_DOUBLE)max_scaled / 1e10f)  { number *= 1e10f; exponent -= 10; }
-            while (number * factor < (UNITY_DOUBLE)min_scaled) { factor *= 10.0f; exponent--; }
-
-            number *= factor;
-        }
-        else if (number > (UNITY_DOUBLE)max_scaled)
-        {
-            UNITY_DOUBLE divisor = 1.0f;
-
-            while (number > (UNITY_DOUBLE)min_scaled * 1e10f)   { number  /= 1e10f; exponent += 10; }
-            while (number / divisor > (UNITY_DOUBLE)max_scaled) { divisor *= 10.0f; exponent++; }
-
-            number /= divisor;
-        }
-        else
-        {
-            /*
-             * In this range, we can split off the integer part before
-             * doing any multiplications.  This reduces rounding error by
-             * freeing up significant bits in the fractional part.
-             */
-            UNITY_DOUBLE factor = 1.0f;
-            n_int = (UNITY_INT32)number;
-            number -= (UNITY_DOUBLE)n_int;
-
-            while (n_int < min_scaled) { n_int *= 10; factor *= 10.0f; exponent--; }
-
-            number *= factor;
-        }
-
-        /* round to nearest integer */
-        n = ((UNITY_INT32)(number + number) + 1) / 2;
-
-#ifndef UNITY_ROUND_TIES_AWAY_FROM_ZERO
-        /* round to even if exactly between two integers */
-        if ((n & 1) && (((UNITY_DOUBLE)n - number) == 0.5f))
-            n--;
-#endif
-
-        n += n_int;
-
-        if (n >= max_scaled)
-        {
-            n = min_scaled;
-            exponent++;
-        }
-
-        /* determine where to place decimal point */
-        decimals = ((exponent <= 0) && (exponent >= -(sig_digits + 3))) ? (-exponent) : (sig_digits - 1);
-        exponent += decimals;
-
-        /* truncate trailing zeroes after decimal point */
-        while ((decimals > 0) && ((n % 10) == 0))
-        {
-            n /= 10;
-            decimals--;
-        }
-
-        /* build up buffer in reverse order */
-        digits = 0;
-        while ((n != 0) || (digits < (decimals + 1)))
-        {
-            buf[digits++] = (char)('0' + n % 10);
-            n /= 10;
-        }
-        while (digits > 0)
-        {
-            if (digits == decimals) { UNITY_OUTPUT_CHAR('.'); }
-            UNITY_OUTPUT_CHAR(buf[--digits]);
-        }
-
-        /* print exponent if needed */
-        if (exponent != 0)
-        {
-            UNITY_OUTPUT_CHAR('e');
-
-            if (exponent < 0)
-            {
-                UNITY_OUTPUT_CHAR('-');
-                exponent = -exponent;
-            }
-            else
-            {
-                UNITY_OUTPUT_CHAR('+');
-            }
-
-            digits = 0;
-            while ((exponent != 0) || (digits < 2))
-            {
-                buf[digits++] = (char)('0' + exponent % 10);
-                exponent /= 10;
-            }
-            while (digits > 0)
-            {
-                UNITY_OUTPUT_CHAR(buf[--digits]);
-            }
-        }
-    }
-}
-#endif /* ! UNITY_EXCLUDE_FLOAT_PRINT */
-
-/*-----------------------------------------------*/
-static void UnityTestResultsBegin(const char* file, const UNITY_LINE_TYPE line)
-{
-#ifdef UNITY_OUTPUT_FOR_ECLIPSE
-    UNITY_OUTPUT_CHAR('(');
-    UnityPrint(file);
-    UNITY_OUTPUT_CHAR(':');
-    UnityPrintNumber((UNITY_INT)line);
-    UNITY_OUTPUT_CHAR(')');
-    UNITY_OUTPUT_CHAR(' ');
-    UnityPrint(Unity.CurrentTestName);
-    UNITY_OUTPUT_CHAR(':');
-#else
-#ifdef UNITY_OUTPUT_FOR_IAR_WORKBENCH
-    UnityPrint("<SRCREF line=");
-    UnityPrintNumber((UNITY_INT)line);
-    UnityPrint(" file=\"");
-    UnityPrint(file);
-    UNITY_OUTPUT_CHAR('"');
-    UNITY_OUTPUT_CHAR('>');
-    UnityPrint(Unity.CurrentTestName);
-    UnityPrint("</SRCREF> ");
-#else
-#ifdef UNITY_OUTPUT_FOR_QT_CREATOR
-    UnityPrint("file://");
-    UnityPrint(file);
-    UNITY_OUTPUT_CHAR(':');
-    UnityPrintNumber((UNITY_INT)line);
-    UNITY_OUTPUT_CHAR(' ');
-    UnityPrint(Unity.CurrentTestName);
-    UNITY_OUTPUT_CHAR(':');
-#else
-    UnityPrint(file);
-    UNITY_OUTPUT_CHAR(':');
-    UnityPrintNumber((UNITY_INT)line);
-    UNITY_OUTPUT_CHAR(':');
-    UnityPrint(Unity.CurrentTestName);
-    UNITY_OUTPUT_CHAR(':');
-#endif
-#endif
-#endif
-}
-
-/*-----------------------------------------------*/
-static void UnityTestResultsFailBegin(const UNITY_LINE_TYPE line)
-{
-    UnityTestResultsBegin(Unity.TestFile, line);
-    UnityPrint(UnityStrFail);
-    UNITY_OUTPUT_CHAR(':');
-}
-
-/*-----------------------------------------------*/
-void UnityConcludeTest(void)
-{
-    if (Unity.CurrentTestIgnored)
-    {
-        Unity.TestIgnores++;
-    }
-    else if (!Unity.CurrentTestFailed)
-    {
-        UnityTestResultsBegin(Unity.TestFile, Unity.CurrentTestLineNumber);
-        UnityPrint(UnityStrPass);
-    }
-    else
-    {
-        Unity.TestFailures++;
-    }
-
-    Unity.CurrentTestFailed = 0;
-    Unity.CurrentTestIgnored = 0;
-    UNITY_PRINT_EXEC_TIME();
-    UNITY_PRINT_EOL();
-    UNITY_FLUSH_CALL();
-}
-
-/*-----------------------------------------------*/
-static void UnityAddMsgIfSpecified(const char* msg)
-{
-    if (msg)
-    {
-        UnityPrint(UnityStrSpacer);
-#ifndef UNITY_EXCLUDE_DETAILS
-        if (Unity.CurrentDetail1)
-        {
-            UnityPrint(UnityStrDetail1Name);
-            UnityPrint(Unity.CurrentDetail1);
-            if (Unity.CurrentDetail2)
-            {
-                UnityPrint(UnityStrDetail2Name);
-                UnityPrint(Unity.CurrentDetail2);
-            }
-            UnityPrint(UnityStrSpacer);
-        }
-#endif
-        UnityPrint(msg);
-    }
-}
-
-/*-----------------------------------------------*/
-static void UnityPrintExpectedAndActualStrings(const char* expected, const char* actual)
-{
-    UnityPrint(UnityStrExpected);
-    if (expected != NULL)
-    {
-        UNITY_OUTPUT_CHAR('\'');
-        UnityPrint(expected);
-        UNITY_OUTPUT_CHAR('\'');
-    }
-    else
-    {
-        UnityPrint(UnityStrNull);
-    }
-    UnityPrint(UnityStrWas);
-    if (actual != NULL)
-    {
-        UNITY_OUTPUT_CHAR('\'');
-        UnityPrint(actual);
-        UNITY_OUTPUT_CHAR('\'');
-    }
-    else
-    {
-        UnityPrint(UnityStrNull);
-    }
-}
-
-/*-----------------------------------------------*/
-static void UnityPrintExpectedAndActualStringsLen(const char* expected,
-                                                  const char* actual,
-                                                  const UNITY_UINT32 length)
-{
-    UnityPrint(UnityStrExpected);
-    if (expected != NULL)
-    {
-        UNITY_OUTPUT_CHAR('\'');
-        UnityPrintLen(expected, length);
-        UNITY_OUTPUT_CHAR('\'');
-    }
-    else
-    {
-        UnityPrint(UnityStrNull);
-    }
-    UnityPrint(UnityStrWas);
-    if (actual != NULL)
-    {
-        UNITY_OUTPUT_CHAR('\'');
-        UnityPrintLen(actual, length);
-        UNITY_OUTPUT_CHAR('\'');
-    }
-    else
-    {
-        UnityPrint(UnityStrNull);
-    }
-}
-
-/*-----------------------------------------------
- * Assertion & Control Helpers
- *-----------------------------------------------*/
-
-/*-----------------------------------------------*/
-static int UnityIsOneArrayNull(UNITY_INTERNAL_PTR expected,
-                               UNITY_INTERNAL_PTR actual,
-                               const UNITY_LINE_TYPE lineNumber,
-                               const char* msg)
-{
-    /* Both are NULL or same pointer */
-    if (expected == actual) { return 0; }
-
-    /* print and return true if just expected is NULL */
-    if (expected == NULL)
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrint(UnityStrNullPointerForExpected);
-        UnityAddMsgIfSpecified(msg);
-        return 1;
-    }
-
-    /* print and return true if just actual is NULL */
-    if (actual == NULL)
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrint(UnityStrNullPointerForActual);
-        UnityAddMsgIfSpecified(msg);
-        return 1;
-    }
-
-    return 0; /* return false if neither is NULL */
-}
-
-/*-----------------------------------------------
- * Assertion Functions
- *-----------------------------------------------*/
-
-/*-----------------------------------------------*/
-void UnityAssertBits(const UNITY_INT mask,
-                     const UNITY_INT expected,
-                     const UNITY_INT actual,
-                     const char* msg,
-                     const UNITY_LINE_TYPE lineNumber)
-{
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if ((mask & expected) != (mask & actual))
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrint(UnityStrExpected);
-        UnityPrintMask((UNITY_UINT)mask, (UNITY_UINT)expected);
-        UnityPrint(UnityStrWas);
-        UnityPrintMask((UNITY_UINT)mask, (UNITY_UINT)actual);
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertEqualNumber(const UNITY_INT expected,
-                            const UNITY_INT actual,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber,
-                            const UNITY_DISPLAY_STYLE_T style)
-{
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if (expected != actual)
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrint(UnityStrExpected);
-        UnityPrintNumberByStyle(expected, style);
-        UnityPrint(UnityStrWas);
-        UnityPrintNumberByStyle(actual, style);
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertGreaterOrLessOrEqualNumber(const UNITY_INT threshold,
-                                           const UNITY_INT actual,
-                                           const UNITY_COMPARISON_T compare,
-                                           const char *msg,
-                                           const UNITY_LINE_TYPE lineNumber,
-                                           const UNITY_DISPLAY_STYLE_T style)
-{
-    int failed = 0;
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if ((threshold == actual) && (compare & UNITY_EQUAL_TO)) { return; }
-    if ((threshold == actual))                               { failed = 1; }
-
-    if ((style & UNITY_DISPLAY_RANGE_INT) == UNITY_DISPLAY_RANGE_INT)
-    {
-        if ((actual > threshold) && (compare & UNITY_SMALLER_THAN)) { failed = 1; }
-        if ((actual < threshold) && (compare & UNITY_GREATER_THAN)) { failed = 1; }
-    }
-    else /* UINT or HEX */
-    {
-        if (((UNITY_UINT)actual > (UNITY_UINT)threshold) && (compare & UNITY_SMALLER_THAN)) { failed = 1; }
-        if (((UNITY_UINT)actual < (UNITY_UINT)threshold) && (compare & UNITY_GREATER_THAN)) { failed = 1; }
-    }
-
-    if (failed)
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrint(UnityStrExpected);
-        UnityPrintNumberByStyle(actual, style);
-        if (compare & UNITY_GREATER_THAN) { UnityPrint(UnityStrGt);      }
-        if (compare & UNITY_SMALLER_THAN) { UnityPrint(UnityStrLt);      }
-        if (compare & UNITY_EQUAL_TO)     { UnityPrint(UnityStrOrEqual); }
-        UnityPrintNumberByStyle(threshold, style);
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-#define UnityPrintPointlessAndBail()       \
-{                                          \
-    UnityTestResultsFailBegin(lineNumber); \
-    UnityPrint(UnityStrPointless);         \
-    UnityAddMsgIfSpecified(msg);           \
-    UNITY_FAIL_AND_BAIL; }
-
-/*-----------------------------------------------*/
-void UnityAssertEqualIntArray(UNITY_INTERNAL_PTR expected,
-                              UNITY_INTERNAL_PTR actual,
-                              const UNITY_UINT32 num_elements,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_DISPLAY_STYLE_T style,
-                              const UNITY_FLAGS_T flags)
-{
-    UNITY_UINT32 elements  = num_elements;
-    unsigned int length    = style & 0xF;
-    unsigned int increment = 0;
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if (num_elements == 0)
-    {
-        UnityPrintPointlessAndBail();
-    }
-
-    if (expected == actual)
-    {
-        return; /* Both are NULL or same pointer */
-    }
-
-    if (UnityIsOneArrayNull(expected, actual, lineNumber, msg))
-    {
-        UNITY_FAIL_AND_BAIL;
-    }
-
-    while ((elements > 0) && (elements--))
-    {
-        UNITY_INT expect_val;
-        UNITY_INT actual_val;
-
-        switch (length)
-        {
-            case 1:
-                expect_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT8*)expected;
-                actual_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT8*)actual;
-                increment  = sizeof(UNITY_INT8);
-                break;
-
-            case 2:
-                expect_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT16*)expected;
-                actual_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT16*)actual;
-                increment  = sizeof(UNITY_INT16);
-                break;
-
-#ifdef UNITY_SUPPORT_64
-            case 8:
-                expect_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT64*)expected;
-                actual_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT64*)actual;
-                increment  = sizeof(UNITY_INT64);
-                break;
-#endif
-
-            default: /* default is length 4 bytes */
-            case 4:
-                expect_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT32*)expected;
-                actual_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT32*)actual;
-                increment  = sizeof(UNITY_INT32);
-                length = 4;
-                break;
-        }
-
-        if (expect_val != actual_val)
-        {
-            if ((style & UNITY_DISPLAY_RANGE_UINT) && (length < (UNITY_INT_WIDTH / 8)))
-            {   /* For UINT, remove sign extension (padding 1's) from signed type casts above */
-                UNITY_INT mask = 1;
-                mask = (mask << 8 * length) - 1;
-                expect_val &= mask;
-                actual_val &= mask;
-            }
-            UnityTestResultsFailBegin(lineNumber);
-            UnityPrint(UnityStrElement);
-            UnityPrintNumberUnsigned(num_elements - elements - 1);
-            UnityPrint(UnityStrExpected);
-            UnityPrintNumberByStyle(expect_val, style);
-            UnityPrint(UnityStrWas);
-            UnityPrintNumberByStyle(actual_val, style);
-            UnityAddMsgIfSpecified(msg);
-            UNITY_FAIL_AND_BAIL;
-        }
-        /* Walk through array by incrementing the pointers */
-        if (flags == UNITY_ARRAY_TO_ARRAY)
-        {
-            expected = (UNITY_INTERNAL_PTR)((const char*)expected + increment);
-        }
-        actual = (UNITY_INTERNAL_PTR)((const char*)actual + increment);
-    }
-}
-
-/*-----------------------------------------------*/
-#ifndef UNITY_EXCLUDE_FLOAT
-/* Wrap this define in a function with variable types as float or double */
-#define UNITY_FLOAT_OR_DOUBLE_WITHIN(delta, expected, actual, diff)                           \
-    if (isinf(expected) && isinf(actual) && (((expected) < 0) == ((actual) < 0))) return 1;   \
-    if (UNITY_NAN_CHECK) return 1;                                                            \
-    (diff) = (actual) - (expected);                                                           \
-    if ((diff) < 0) (diff) = -(diff);                                                         \
-    if ((delta) < 0) (delta) = -(delta);                                                      \
-    return !(isnan(diff) || isinf(diff) || ((diff) > (delta)))
-    /* This first part of this condition will catch any NaN or Infinite values */
-#ifndef UNITY_NAN_NOT_EQUAL_NAN
-  #define UNITY_NAN_CHECK isnan(expected) && isnan(actual)
-#else
-  #define UNITY_NAN_CHECK 0
-#endif
-
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-  #define UNITY_PRINT_EXPECTED_AND_ACTUAL_FLOAT(expected, actual) \
-  {                                                               \
-    UnityPrint(UnityStrExpected);                                 \
-    UnityPrintFloat(expected);                                    \
-    UnityPrint(UnityStrWas);                                      \
-    UnityPrintFloat(actual); }
-#else
-  #define UNITY_PRINT_EXPECTED_AND_ACTUAL_FLOAT(expected, actual) \
-    UnityPrint(UnityStrDelta)
-#endif /* UNITY_EXCLUDE_FLOAT_PRINT */
-
-/*-----------------------------------------------*/
-static int UnityFloatsWithin(UNITY_FLOAT delta, UNITY_FLOAT expected, UNITY_FLOAT actual)
-{
-    UNITY_FLOAT diff;
-    UNITY_FLOAT_OR_DOUBLE_WITHIN(delta, expected, actual, diff);
-}
-
-/*-----------------------------------------------*/
-void UnityAssertEqualFloatArray(UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* expected,
-                                UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* actual,
-                                const UNITY_UINT32 num_elements,
-                                const char* msg,
-                                const UNITY_LINE_TYPE lineNumber,
-                                const UNITY_FLAGS_T flags)
-{
-    UNITY_UINT32 elements = num_elements;
-    UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* ptr_expected = expected;
-    UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* ptr_actual = actual;
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if (elements == 0)
-    {
-        UnityPrintPointlessAndBail();
-    }
-
-    if (expected == actual)
-    {
-        return; /* Both are NULL or same pointer */
-    }
-
-    if (UnityIsOneArrayNull((UNITY_INTERNAL_PTR)expected, (UNITY_INTERNAL_PTR)actual, lineNumber, msg))
-    {
-        UNITY_FAIL_AND_BAIL;
-    }
-
-    while (elements--)
-    {
-        if (!UnityFloatsWithin(*ptr_expected * UNITY_FLOAT_PRECISION, *ptr_expected, *ptr_actual))
-        {
-            UnityTestResultsFailBegin(lineNumber);
-            UnityPrint(UnityStrElement);
-            UnityPrintNumberUnsigned(num_elements - elements - 1);
-            UNITY_PRINT_EXPECTED_AND_ACTUAL_FLOAT((UNITY_DOUBLE)*ptr_expected, (UNITY_DOUBLE)*ptr_actual);
-            UnityAddMsgIfSpecified(msg);
-            UNITY_FAIL_AND_BAIL;
-        }
-        if (flags == UNITY_ARRAY_TO_ARRAY)
-        {
-            ptr_expected++;
-        }
-        ptr_actual++;
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertFloatsWithin(const UNITY_FLOAT delta,
-                             const UNITY_FLOAT expected,
-                             const UNITY_FLOAT actual,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber)
-{
-    RETURN_IF_FAIL_OR_IGNORE;
-
-
-    if (!UnityFloatsWithin(delta, expected, actual))
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UNITY_PRINT_EXPECTED_AND_ACTUAL_FLOAT((UNITY_DOUBLE)expected, (UNITY_DOUBLE)actual);
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertFloatSpecial(const UNITY_FLOAT actual,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber,
-                             const UNITY_FLOAT_TRAIT_T style)
-{
-    const char* trait_names[] = {UnityStrInf, UnityStrNegInf, UnityStrNaN, UnityStrDet};
-    UNITY_INT should_be_trait = ((UNITY_INT)style & 1);
-    UNITY_INT is_trait        = !should_be_trait;
-    UNITY_INT trait_index     = (UNITY_INT)(style >> 1);
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    switch (style)
-    {
-        case UNITY_FLOAT_IS_INF:
-        case UNITY_FLOAT_IS_NOT_INF:
-            is_trait = isinf(actual) && (actual > 0);
-            break;
-        case UNITY_FLOAT_IS_NEG_INF:
-        case UNITY_FLOAT_IS_NOT_NEG_INF:
-            is_trait = isinf(actual) && (actual < 0);
-            break;
-
-        case UNITY_FLOAT_IS_NAN:
-        case UNITY_FLOAT_IS_NOT_NAN:
-            is_trait = isnan(actual) ? 1 : 0;
-            break;
-
-        case UNITY_FLOAT_IS_DET: /* A determinate number is non infinite and not NaN. */
-        case UNITY_FLOAT_IS_NOT_DET:
-            is_trait = !isinf(actual) && !isnan(actual);
-            break;
-
-        default:
-            trait_index = 0;
-            trait_names[0] = UnityStrInvalidFloatTrait;
-            break;
-    }
-
-    if (is_trait != should_be_trait)
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrint(UnityStrExpected);
-        if (!should_be_trait)
-        {
-            UnityPrint(UnityStrNot);
-        }
-        UnityPrint(trait_names[trait_index]);
-        UnityPrint(UnityStrWas);
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-        UnityPrintFloat((UNITY_DOUBLE)actual);
-#else
-        if (should_be_trait)
-        {
-            UnityPrint(UnityStrNot);
-        }
-        UnityPrint(trait_names[trait_index]);
-#endif
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-#endif /* not UNITY_EXCLUDE_FLOAT */
-
-/*-----------------------------------------------*/
-#ifndef UNITY_EXCLUDE_DOUBLE
-static int UnityDoublesWithin(UNITY_DOUBLE delta, UNITY_DOUBLE expected, UNITY_DOUBLE actual)
-{
-    UNITY_DOUBLE diff;
-    UNITY_FLOAT_OR_DOUBLE_WITHIN(delta, expected, actual, diff);
-}
-
-/*-----------------------------------------------*/
-void UnityAssertEqualDoubleArray(UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* expected,
-                                 UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* actual,
-                                 const UNITY_UINT32 num_elements,
-                                 const char* msg,
-                                 const UNITY_LINE_TYPE lineNumber,
-                                 const UNITY_FLAGS_T flags)
-{
-    UNITY_UINT32 elements = num_elements;
-    UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* ptr_expected = expected;
-    UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* ptr_actual = actual;
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if (elements == 0)
-    {
-        UnityPrintPointlessAndBail();
-    }
-
-    if (expected == actual)
-    {
-        return; /* Both are NULL or same pointer */
-    }
-
-    if (UnityIsOneArrayNull((UNITY_INTERNAL_PTR)expected, (UNITY_INTERNAL_PTR)actual, lineNumber, msg))
-    {
-        UNITY_FAIL_AND_BAIL;
-    }
-
-    while (elements--)
-    {
-        if (!UnityDoublesWithin(*ptr_expected * UNITY_DOUBLE_PRECISION, *ptr_expected, *ptr_actual))
-        {
-            UnityTestResultsFailBegin(lineNumber);
-            UnityPrint(UnityStrElement);
-            UnityPrintNumberUnsigned(num_elements - elements - 1);
-            UNITY_PRINT_EXPECTED_AND_ACTUAL_FLOAT(*ptr_expected, *ptr_actual);
-            UnityAddMsgIfSpecified(msg);
-            UNITY_FAIL_AND_BAIL;
-        }
-        if (flags == UNITY_ARRAY_TO_ARRAY)
-        {
-            ptr_expected++;
-        }
-        ptr_actual++;
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertDoublesWithin(const UNITY_DOUBLE delta,
-                              const UNITY_DOUBLE expected,
-                              const UNITY_DOUBLE actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber)
-{
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if (!UnityDoublesWithin(delta, expected, actual))
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UNITY_PRINT_EXPECTED_AND_ACTUAL_FLOAT(expected, actual);
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertDoubleSpecial(const UNITY_DOUBLE actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_FLOAT_TRAIT_T style)
-{
-    const char* trait_names[] = {UnityStrInf, UnityStrNegInf, UnityStrNaN, UnityStrDet};
-    UNITY_INT should_be_trait = ((UNITY_INT)style & 1);
-    UNITY_INT is_trait        = !should_be_trait;
-    UNITY_INT trait_index     = (UNITY_INT)(style >> 1);
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    switch (style)
-    {
-        case UNITY_FLOAT_IS_INF:
-        case UNITY_FLOAT_IS_NOT_INF:
-            is_trait = isinf(actual) && (actual > 0);
-            break;
-        case UNITY_FLOAT_IS_NEG_INF:
-        case UNITY_FLOAT_IS_NOT_NEG_INF:
-            is_trait = isinf(actual) && (actual < 0);
-            break;
-
-        case UNITY_FLOAT_IS_NAN:
-        case UNITY_FLOAT_IS_NOT_NAN:
-            is_trait = isnan(actual) ? 1 : 0;
-            break;
-
-        case UNITY_FLOAT_IS_DET: /* A determinate number is non infinite and not NaN. */
-        case UNITY_FLOAT_IS_NOT_DET:
-            is_trait = !isinf(actual) && !isnan(actual);
-            break;
-
-        default:
-            trait_index = 0;
-            trait_names[0] = UnityStrInvalidFloatTrait;
-            break;
-    }
-
-    if (is_trait != should_be_trait)
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrint(UnityStrExpected);
-        if (!should_be_trait)
-        {
-            UnityPrint(UnityStrNot);
-        }
-        UnityPrint(trait_names[trait_index]);
-        UnityPrint(UnityStrWas);
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-        UnityPrintFloat(actual);
-#else
-        if (should_be_trait)
-        {
-            UnityPrint(UnityStrNot);
-        }
-        UnityPrint(trait_names[trait_index]);
-#endif
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-#endif /* not UNITY_EXCLUDE_DOUBLE */
-
-/*-----------------------------------------------*/
-void UnityAssertNumbersWithin(const UNITY_UINT delta,
-                              const UNITY_INT expected,
-                              const UNITY_INT actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_DISPLAY_STYLE_T style)
-{
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if ((style & UNITY_DISPLAY_RANGE_INT) == UNITY_DISPLAY_RANGE_INT)
-    {
-        if (actual > expected)
-        {
-            Unity.CurrentTestFailed = (((UNITY_UINT)actual - (UNITY_UINT)expected) > delta);
-        }
-        else
-        {
-            Unity.CurrentTestFailed = (((UNITY_UINT)expected - (UNITY_UINT)actual) > delta);
-        }
-    }
-    else
-    {
-        if ((UNITY_UINT)actual > (UNITY_UINT)expected)
-        {
-            Unity.CurrentTestFailed = (((UNITY_UINT)actual - (UNITY_UINT)expected) > delta);
-        }
-        else
-        {
-            Unity.CurrentTestFailed = (((UNITY_UINT)expected - (UNITY_UINT)actual) > delta);
-        }
-    }
-
-    if (Unity.CurrentTestFailed)
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrint(UnityStrDelta);
-        UnityPrintNumberByStyle((UNITY_INT)delta, style);
-        UnityPrint(UnityStrExpected);
-        UnityPrintNumberByStyle(expected, style);
-        UnityPrint(UnityStrWas);
-        UnityPrintNumberByStyle(actual, style);
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertNumbersArrayWithin(const UNITY_UINT delta,
-                                   UNITY_INTERNAL_PTR expected,
-                                   UNITY_INTERNAL_PTR actual,
-                                   const UNITY_UINT32 num_elements,
-                                   const char* msg,
-                                   const UNITY_LINE_TYPE lineNumber,
-                                   const UNITY_DISPLAY_STYLE_T style,
-                                   const UNITY_FLAGS_T flags)
-{
-    UNITY_UINT32 elements = num_elements;
-    unsigned int length   = style & 0xF;
-    unsigned int increment = 0;
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if (num_elements == 0)
-    {
-        UnityPrintPointlessAndBail();
-    }
-
-    if (expected == actual)
-    {
-        return; /* Both are NULL or same pointer */
-    }
-
-    if (UnityIsOneArrayNull(expected, actual, lineNumber, msg))
-    {
-        UNITY_FAIL_AND_BAIL;
-    }
-
-    while ((elements > 0) && (elements--))
-    {
-        UNITY_INT expect_val;
-        UNITY_INT actual_val;
-
-        switch (length)
-        {
-            case 1:
-                expect_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT8*)expected;
-                actual_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT8*)actual;
-                increment  = sizeof(UNITY_INT8);
-                break;
-
-            case 2:
-                expect_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT16*)expected;
-                actual_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT16*)actual;
-                increment  = sizeof(UNITY_INT16);
-                break;
-
-#ifdef UNITY_SUPPORT_64
-            case 8:
-                expect_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT64*)expected;
-                actual_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT64*)actual;
-                increment  = sizeof(UNITY_INT64);
-                break;
-#endif
-
-            default: /* default is length 4 bytes */
-            case 4:
-                expect_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT32*)expected;
-                actual_val = *(UNITY_PTR_ATTRIBUTE const UNITY_INT32*)actual;
-                increment  = sizeof(UNITY_INT32);
-                length = 4;
-                break;
-        }
-
-        if ((style & UNITY_DISPLAY_RANGE_INT) == UNITY_DISPLAY_RANGE_INT)
-        {
-            if (actual_val > expect_val)
-            {
-                Unity.CurrentTestFailed = (((UNITY_UINT)actual_val - (UNITY_UINT)expect_val) > delta);
-            }
-            else
-            {
-                Unity.CurrentTestFailed = (((UNITY_UINT)expect_val - (UNITY_UINT)actual_val) > delta);
-            }
-        }
-        else
-        {
-            if ((UNITY_UINT)actual_val > (UNITY_UINT)expect_val)
-            {
-                Unity.CurrentTestFailed = (((UNITY_UINT)actual_val - (UNITY_UINT)expect_val) > delta);
-            }
-            else
-            {
-                Unity.CurrentTestFailed = (((UNITY_UINT)expect_val - (UNITY_UINT)actual_val) > delta);
-            }
-        }
-
-        if (Unity.CurrentTestFailed)
-        {
-            if ((style & UNITY_DISPLAY_RANGE_UINT) && (length < (UNITY_INT_WIDTH / 8)))
-            {   /* For UINT, remove sign extension (padding 1's) from signed type casts above */
-                UNITY_INT mask = 1;
-                mask = (mask << 8 * length) - 1;
-                expect_val &= mask;
-                actual_val &= mask;
-            }
-            UnityTestResultsFailBegin(lineNumber);
-            UnityPrint(UnityStrDelta);
-            UnityPrintNumberByStyle((UNITY_INT)delta, style);
-            UnityPrint(UnityStrElement);
-            UnityPrintNumberUnsigned(num_elements - elements - 1);
-            UnityPrint(UnityStrExpected);
-            UnityPrintNumberByStyle(expect_val, style);
-            UnityPrint(UnityStrWas);
-            UnityPrintNumberByStyle(actual_val, style);
-            UnityAddMsgIfSpecified(msg);
-            UNITY_FAIL_AND_BAIL;
-        }
-        /* Walk through array by incrementing the pointers */
-        if (flags == UNITY_ARRAY_TO_ARRAY)
-        {
-            expected = (UNITY_INTERNAL_PTR)((const char*)expected + increment);
-        }
-        actual = (UNITY_INTERNAL_PTR)((const char*)actual + increment);
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertEqualString(const char* expected,
-                            const char* actual,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber)
-{
-    UNITY_UINT32 i;
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    /* if both pointers not null compare the strings */
-    if (expected && actual)
-    {
-        for (i = 0; expected[i] || actual[i]; i++)
-        {
-            if (expected[i] != actual[i])
-            {
-                Unity.CurrentTestFailed = 1;
-                break;
-            }
-        }
-    }
-    else
-    { /* handle case of one pointers being null (if both null, test should pass) */
-        if (expected != actual)
-        {
-            Unity.CurrentTestFailed = 1;
-        }
-    }
-
-    if (Unity.CurrentTestFailed)
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrintExpectedAndActualStrings(expected, actual);
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertEqualStringLen(const char* expected,
-                               const char* actual,
-                               const UNITY_UINT32 length,
-                               const char* msg,
-                               const UNITY_LINE_TYPE lineNumber)
-{
-    UNITY_UINT32 i;
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    /* if both pointers not null compare the strings */
-    if (expected && actual)
-    {
-        for (i = 0; (i < length) && (expected[i] || actual[i]); i++)
-        {
-            if (expected[i] != actual[i])
-            {
-                Unity.CurrentTestFailed = 1;
-                break;
-            }
-        }
-    }
-    else
-    { /* handle case of one pointers being null (if both null, test should pass) */
-        if (expected != actual)
-        {
-            Unity.CurrentTestFailed = 1;
-        }
-    }
-
-    if (Unity.CurrentTestFailed)
-    {
-        UnityTestResultsFailBegin(lineNumber);
-        UnityPrintExpectedAndActualStringsLen(expected, actual, length);
-        UnityAddMsgIfSpecified(msg);
-        UNITY_FAIL_AND_BAIL;
-    }
-}
-
-/*-----------------------------------------------*/
-void UnityAssertEqualStringArray(UNITY_INTERNAL_PTR expected,
-                                 const char** actual,
-                                 const UNITY_UINT32 num_elements,
-                                 const char* msg,
-                                 const UNITY_LINE_TYPE lineNumber,
-                                 const UNITY_FLAGS_T flags)
-{
-    UNITY_UINT32 i = 0;
-    UNITY_UINT32 j = 0;
-    const char* expd = NULL;
-    const char* act = NULL;
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    /* if no elements, it's an error */
-    if (num_elements == 0)
-    {
-        UnityPrintPointlessAndBail();
-    }
-
-    if ((const void*)expected == (const void*)actual)
-    {
-        return; /* Both are NULL or same pointer */
-    }
-
-    if (UnityIsOneArrayNull((UNITY_INTERNAL_PTR)expected, (UNITY_INTERNAL_PTR)actual, lineNumber, msg))
-    {
-        UNITY_FAIL_AND_BAIL;
-    }
-
-    if (flags != UNITY_ARRAY_TO_ARRAY)
-    {
-        expd = (const char*)expected;
-    }
-
-    do
-    {
-        act = actual[j];
-        if (flags == UNITY_ARRAY_TO_ARRAY)
-        {
-            expd = ((const char* const*)expected)[j];
-        }
-
-        /* if both pointers not null compare the strings */
-        if (expd && act)
-        {
-            for (i = 0; expd[i] || act[i]; i++)
-            {
-                if (expd[i] != act[i])
-                {
-                    Unity.CurrentTestFailed = 1;
-                    break;
-                }
-            }
-        }
-        else
-        { /* handle case of one pointers being null (if both null, test should pass) */
-            if (expd != act)
-            {
-                Unity.CurrentTestFailed = 1;
-            }
-        }
-
-        if (Unity.CurrentTestFailed)
-        {
-            UnityTestResultsFailBegin(lineNumber);
-            if (num_elements > 1)
-            {
-                UnityPrint(UnityStrElement);
-                UnityPrintNumberUnsigned(j);
-            }
-            UnityPrintExpectedAndActualStrings(expd, act);
-            UnityAddMsgIfSpecified(msg);
-            UNITY_FAIL_AND_BAIL;
-        }
-    } while (++j < num_elements);
-}
-
-/*-----------------------------------------------*/
-void UnityAssertEqualMemory(UNITY_INTERNAL_PTR expected,
-                            UNITY_INTERNAL_PTR actual,
-                            const UNITY_UINT32 length,
-                            const UNITY_UINT32 num_elements,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber,
-                            const UNITY_FLAGS_T flags)
-{
-    UNITY_PTR_ATTRIBUTE const unsigned char* ptr_exp = (UNITY_PTR_ATTRIBUTE const unsigned char*)expected;
-    UNITY_PTR_ATTRIBUTE const unsigned char* ptr_act = (UNITY_PTR_ATTRIBUTE const unsigned char*)actual;
-    UNITY_UINT32 elements = num_elements;
-    UNITY_UINT32 bytes;
-
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    if ((elements == 0) || (length == 0))
-    {
-        UnityPrintPointlessAndBail();
-    }
-
-    if (expected == actual)
-    {
-        return; /* Both are NULL or same pointer */
-    }
-
-    if (UnityIsOneArrayNull(expected, actual, lineNumber, msg))
-    {
-        UNITY_FAIL_AND_BAIL;
-    }
-
-    while (elements--)
-    {
-        bytes = length;
-        while (bytes--)
-        {
-            if (*ptr_exp != *ptr_act)
-            {
-                UnityTestResultsFailBegin(lineNumber);
-                UnityPrint(UnityStrMemory);
-                if (num_elements > 1)
-                {
-                    UnityPrint(UnityStrElement);
-                    UnityPrintNumberUnsigned(num_elements - elements - 1);
-                }
-                UnityPrint(UnityStrByte);
-                UnityPrintNumberUnsigned(length - bytes - 1);
-                UnityPrint(UnityStrExpected);
-                UnityPrintNumberByStyle(*ptr_exp, UNITY_DISPLAY_STYLE_HEX8);
-                UnityPrint(UnityStrWas);
-                UnityPrintNumberByStyle(*ptr_act, UNITY_DISPLAY_STYLE_HEX8);
-                UnityAddMsgIfSpecified(msg);
-                UNITY_FAIL_AND_BAIL;
-            }
-            ptr_exp++;
-            ptr_act++;
-        }
-        if (flags == UNITY_ARRAY_TO_VAL)
-        {
-            ptr_exp = (UNITY_PTR_ATTRIBUTE const unsigned char*)expected;
-        }
-    }
-}
-
-/*-----------------------------------------------*/
-
-static union
-{
-    UNITY_INT8 i8;
-    UNITY_INT16 i16;
-    UNITY_INT32 i32;
-#ifdef UNITY_SUPPORT_64
-    UNITY_INT64 i64;
-#endif
-#ifndef UNITY_EXCLUDE_FLOAT
-    float f;
-#endif
-#ifndef UNITY_EXCLUDE_DOUBLE
-    double d;
-#endif
-} UnityQuickCompare;
-
-UNITY_INTERNAL_PTR UnityNumToPtr(const UNITY_INT num, const UNITY_UINT8 size)
-{
-    switch(size)
-    {
-        case 1:
-            UnityQuickCompare.i8 = (UNITY_INT8)num;
-            return (UNITY_INTERNAL_PTR)(&UnityQuickCompare.i8);
-
-        case 2:
-            UnityQuickCompare.i16 = (UNITY_INT16)num;
-            return (UNITY_INTERNAL_PTR)(&UnityQuickCompare.i16);
-
-#ifdef UNITY_SUPPORT_64
-        case 8:
-            UnityQuickCompare.i64 = (UNITY_INT64)num;
-            return (UNITY_INTERNAL_PTR)(&UnityQuickCompare.i64);
-#endif
-
-        default: /* 4 bytes */
-            UnityQuickCompare.i32 = (UNITY_INT32)num;
-            return (UNITY_INTERNAL_PTR)(&UnityQuickCompare.i32);
-    }
-}
-
-#ifndef UNITY_EXCLUDE_FLOAT
-/*-----------------------------------------------*/
-UNITY_INTERNAL_PTR UnityFloatToPtr(const float num)
-{
-    UnityQuickCompare.f = num;
-    return (UNITY_INTERNAL_PTR)(&UnityQuickCompare.f);
-}
-#endif
-
-#ifndef UNITY_EXCLUDE_DOUBLE
-/*-----------------------------------------------*/
-UNITY_INTERNAL_PTR UnityDoubleToPtr(const double num)
-{
-    UnityQuickCompare.d = num;
-    return (UNITY_INTERNAL_PTR)(&UnityQuickCompare.d);
-}
-#endif
-
-/*-----------------------------------------------
- * Control Functions
- *-----------------------------------------------*/
-
-/*-----------------------------------------------*/
-void UnityFail(const char* msg, const UNITY_LINE_TYPE line)
-{
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    UnityTestResultsBegin(Unity.TestFile, line);
-    UnityPrint(UnityStrFail);
-    if (msg != NULL)
-    {
-        UNITY_OUTPUT_CHAR(':');
-
-#ifndef UNITY_EXCLUDE_DETAILS
-        if (Unity.CurrentDetail1)
-        {
-            UnityPrint(UnityStrDetail1Name);
-            UnityPrint(Unity.CurrentDetail1);
-            if (Unity.CurrentDetail2)
-            {
-                UnityPrint(UnityStrDetail2Name);
-                UnityPrint(Unity.CurrentDetail2);
-            }
-            UnityPrint(UnityStrSpacer);
-        }
-#endif
-        if (msg[0] != ' ')
-        {
-            UNITY_OUTPUT_CHAR(' ');
-        }
-        UnityPrint(msg);
-    }
-
-    UNITY_FAIL_AND_BAIL;
-}
-
-/*-----------------------------------------------*/
-void UnityIgnore(const char* msg, const UNITY_LINE_TYPE line)
-{
-    RETURN_IF_FAIL_OR_IGNORE;
-
-    UnityTestResultsBegin(Unity.TestFile, line);
-    UnityPrint(UnityStrIgnore);
-    if (msg != NULL)
-    {
-        UNITY_OUTPUT_CHAR(':');
-        UNITY_OUTPUT_CHAR(' ');
-        UnityPrint(msg);
-    }
-    UNITY_IGNORE_AND_BAIL;
-}
-
-/*-----------------------------------------------*/
-void UnityMessage(const char* msg, const UNITY_LINE_TYPE line)
-{
-    UnityTestResultsBegin(Unity.TestFile, line);
-    UnityPrint("INFO");
-    if (msg != NULL)
-    {
-      UNITY_OUTPUT_CHAR(':');
-      UNITY_OUTPUT_CHAR(' ');
-      UnityPrint(msg);
-    }
-    UNITY_PRINT_EOL();
-}
-
-/*-----------------------------------------------*/
-void UnityDefaultTestRun(UnityTestFunction Func, const char* FuncName, const int FuncLineNum)
-{
-    Unity.CurrentTestName = FuncName;
-    Unity.CurrentTestLineNumber = (UNITY_LINE_TYPE)FuncLineNum;
-    Unity.NumberOfTests++;
-    UNITY_CLR_DETAILS();
-    UNITY_EXEC_TIME_START();
-    if (TEST_PROTECT())
-    {
-        setUp();
-        Func();
-    }
-    if (TEST_PROTECT())
-    {
-        tearDown();
-    }
-    UNITY_EXEC_TIME_STOP();
-    UnityConcludeTest();
-}
-
-/*-----------------------------------------------*/
-void UnitySetTestFile(const char* filename)
-{
-	Unity.TestFile = filename;
-}
-
-/*-----------------------------------------------*/
-void UnityBegin(const char* filename)
-{
-    Unity.TestFile = filename;
-    Unity.CurrentTestName = NULL;
-    Unity.CurrentTestLineNumber = 0;
-    Unity.NumberOfTests = 0;
-    Unity.TestFailures = 0;
-    Unity.TestIgnores = 0;
-    Unity.CurrentTestFailed = 0;
-    Unity.CurrentTestIgnored = 0;
-
-    UNITY_CLR_DETAILS();
-    UNITY_OUTPUT_START();
-}
-
-/*-----------------------------------------------*/
-int UnityEnd(void)
-{
-    UNITY_PRINT_EOL();
-    UnityPrint(UnityStrBreaker);
-    UNITY_PRINT_EOL();
-    UnityPrintNumber((UNITY_INT)(Unity.NumberOfTests));
-    UnityPrint(UnityStrResultsTests);
-    UnityPrintNumber((UNITY_INT)(Unity.TestFailures));
-    UnityPrint(UnityStrResultsFailures);
-    UnityPrintNumber((UNITY_INT)(Unity.TestIgnores));
-    UnityPrint(UnityStrResultsIgnored);
-    UNITY_PRINT_EOL();
-    if (Unity.TestFailures == 0U)
-    {
-        UnityPrint(UnityStrOk);
-    }
-    else
-    {
-        UnityPrint(UnityStrFail);
-#ifdef UNITY_DIFFERENTIATE_FINAL_FAIL
-        UNITY_OUTPUT_CHAR('E'); UNITY_OUTPUT_CHAR('D');
-#endif
-    }
-    UNITY_PRINT_EOL();
-    UNITY_FLUSH_CALL();
-    UNITY_OUTPUT_COMPLETE();
-    return (int)(Unity.TestFailures);
-}
-
-/*-----------------------------------------------
- * Command Line Argument Support
- *-----------------------------------------------*/
-#ifdef UNITY_USE_COMMAND_LINE_ARGS
-
-char* UnityOptionIncludeNamed = NULL;
-char* UnityOptionExcludeNamed = NULL;
-int UnityVerbosity            = 1;
-
-/*-----------------------------------------------*/
-int UnityParseOptions(int argc, char** argv)
-{
-    int i;
-    UnityOptionIncludeNamed = NULL;
-    UnityOptionExcludeNamed = NULL;
-
-    for (i = 1; i < argc; i++)
-    {
-        if (argv[i][0] == '-')
-        {
-            switch (argv[i][1])
-            {
-                case 'l': /* list tests */
-                    return -1;
-                case 'n': /* include tests with name including this string */
-                case 'f': /* an alias for -n */
-                    if (argv[i][2] == '=')
-                    {
-                        UnityOptionIncludeNamed = &argv[i][3];
-                    }
-                    else if (++i < argc)
-                    {
-                        UnityOptionIncludeNamed = argv[i];
-                    }
-                    else
-                    {
-                        UnityPrint("ERROR: No Test String to Include Matches For");
-                        UNITY_PRINT_EOL();
-                        return 1;
-                    }
-                    break;
-                case 'q': /* quiet */
-                    UnityVerbosity = 0;
-                    break;
-                case 'v': /* verbose */
-                    UnityVerbosity = 2;
-                    break;
-                case 'x': /* exclude tests with name including this string */
-                    if (argv[i][2] == '=')
-                    {
-                        UnityOptionExcludeNamed = &argv[i][3];
-                    }
-                    else if (++i < argc)
-                    {
-                        UnityOptionExcludeNamed = argv[i];
-                    }
-                    else
-                    {
-                        UnityPrint("ERROR: No Test String to Exclude Matches For");
-                        UNITY_PRINT_EOL();
-                        return 1;
-                    }
-                    break;
-                default:
-                    UnityPrint("ERROR: Unknown Option ");
-                    UNITY_OUTPUT_CHAR(argv[i][1]);
-                    UNITY_PRINT_EOL();
-                    return 1;
-            }
-        }
-    }
-
-    return 0;
-}
-
-/*-----------------------------------------------*/
-int IsStringInBiggerString(const char* longstring, const char* shortstring)
-{
-    const char* lptr = longstring;
-    const char* sptr = shortstring;
-    const char* lnext = lptr;
-
-    if (*sptr == '*')
-    {
-        return 1;
-    }
-
-    while (*lptr)
-    {
-        lnext = lptr + 1;
-
-        /* If they current bytes match, go on to the next bytes */
-        while (*lptr && *sptr && (*lptr == *sptr))
-        {
-            lptr++;
-            sptr++;
-
-            /* We're done if we match the entire string or up to a wildcard */
-            if (*sptr == '*')
-                return 1;
-            if (*sptr == ',')
-                return 1;
-            if (*sptr == '"')
-                return 1;
-            if (*sptr == '\'')
-                return 1;
-            if (*sptr == ':')
-                return 2;
-            if (*sptr == 0)
-                return 1;
-        }
-
-        /* Otherwise we start in the long pointer 1 character further and try again */
-        lptr = lnext;
-        sptr = shortstring;
-    }
-
-    return 0;
-}
-
-/*-----------------------------------------------*/
-int UnityStringArgumentMatches(const char* str)
-{
-    int retval;
-    const char* ptr1;
-    const char* ptr2;
-    const char* ptrf;
-
-    /* Go through the options and get the substrings for matching one at a time */
-    ptr1 = str;
-    while (ptr1[0] != 0)
-    {
-        if ((ptr1[0] == '"') || (ptr1[0] == '\''))
-        {
-            ptr1++;
-        }
-
-        /* look for the start of the next partial */
-        ptr2 = ptr1;
-        ptrf = 0;
-        do
-        {
-            ptr2++;
-            if ((ptr2[0] == ':') && (ptr2[1] != 0) && (ptr2[0] != '\'') && (ptr2[0] != '"') && (ptr2[0] != ','))
-            {
-                ptrf = &ptr2[1];
-            }
-        } while ((ptr2[0] != 0) && (ptr2[0] != '\'') && (ptr2[0] != '"') && (ptr2[0] != ','));
-
-        while ((ptr2[0] != 0) && ((ptr2[0] == ':') || (ptr2[0] == '\'') || (ptr2[0] == '"') || (ptr2[0] == ',')))
-        {
-            ptr2++;
-        }
-
-        /* done if complete filename match */
-        retval = IsStringInBiggerString(Unity.TestFile, ptr1);
-        if (retval == 1)
-        {
-            return retval;
-        }
-
-        /* done if testname match after filename partial match */
-        if ((retval == 2) && (ptrf != 0))
-        {
-            if (IsStringInBiggerString(Unity.CurrentTestName, ptrf))
-            {
-                return 1;
-            }
-        }
-
-        /* done if complete testname match */
-        if (IsStringInBiggerString(Unity.CurrentTestName, ptr1) == 1)
-        {
-            return 1;
-        }
-
-        ptr1 = ptr2;
-    }
-
-    /* we couldn't find a match for any substrings */
-    return 0;
-}
-
-/*-----------------------------------------------*/
-int UnityTestMatches(void)
-{
-    /* Check if this test name matches the included test pattern */
-    int retval;
-    if (UnityOptionIncludeNamed)
-    {
-        retval = UnityStringArgumentMatches(UnityOptionIncludeNamed);
-    }
-    else
-    {
-        retval = 1;
-    }
-
-    /* Check if this test name matches the excluded test pattern */
-    if (UnityOptionExcludeNamed)
-    {
-        if (UnityStringArgumentMatches(UnityOptionExcludeNamed))
-        {
-            retval = 0;
-        }
-    }
-
-    return retval;
-}
-
-#endif /* UNITY_USE_COMMAND_LINE_ARGS */
-/*-----------------------------------------------*/
diff --git a/test/vendor/ceedling/vendor/unity/src/unity.h b/test/vendor/ceedling/vendor/unity/src/unity.h
deleted file mode 100644
index 34d7f93aa..000000000
--- a/test/vendor/ceedling/vendor/unity/src/unity.h
+++ /dev/null
@@ -1,617 +0,0 @@
-/* ==========================================
-    Unity Project - A Test Framework for C
-    Copyright (c) 2007-19 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-========================================== */
-
-#ifndef UNITY_FRAMEWORK_H
-#define UNITY_FRAMEWORK_H
-#define UNITY
-
-#define UNITY_VERSION_MAJOR    2
-#define UNITY_VERSION_MINOR    5
-#define UNITY_VERSION_BUILD    0
-#define UNITY_VERSION          ((UNITY_VERSION_MAJOR << 16) | (UNITY_VERSION_MINOR << 8) | UNITY_VERSION_BUILD)
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "unity_internals.h"
-
-/*-------------------------------------------------------
- * Test Setup / Teardown
- *-------------------------------------------------------*/
-
-/* These functions are intended to be called before and after each test.
- * If using unity directly, these will need to be provided for each test
- * executable built. If you are using the test runner generator and/or
- * Ceedling, these are optional. */
-void setUp(void);
-void tearDown(void);
-
-/* These functions are intended to be called at the beginning and end of an
- * entire test suite.  suiteTearDown() is passed the number of tests that
- * failed, and its return value becomes the exit code of main(). If using
- * Unity directly, you're in charge of calling these if they are desired.
- * If using Ceedling or the test runner generator, these will be called
- * automatically if they exist. */
-void suiteSetUp(void);
-int suiteTearDown(int num_failures);
-
-/*-------------------------------------------------------
- * Test Reset and Verify
- *-------------------------------------------------------*/
-
-/* These functions are intended to be called before during tests in order
- * to support complex test loops, etc. Both are NOT built into Unity. Instead
- * the test runner generator will create them. resetTest will run teardown and
- * setup again, verifying any end-of-test needs between. verifyTest will only
- * run the verification. */
-void resetTest(void);
-void verifyTest(void);
-
-/*-------------------------------------------------------
- * Configuration Options
- *-------------------------------------------------------
- * All options described below should be passed as a compiler flag to all files using Unity. If you must add #defines, place them BEFORE the #include above.
-
- * Integers/longs/pointers
- *     - Unity attempts to automatically discover your integer sizes
- *       - define UNITY_EXCLUDE_STDINT_H to stop attempting to look in <stdint.h>
- *       - define UNITY_EXCLUDE_LIMITS_H to stop attempting to look in <limits.h>
- *     - If you cannot use the automatic methods above, you can force Unity by using these options:
- *       - define UNITY_SUPPORT_64
- *       - set UNITY_INT_WIDTH
- *       - set UNITY_LONG_WIDTH
- *       - set UNITY_POINTER_WIDTH
-
- * Floats
- *     - define UNITY_EXCLUDE_FLOAT to disallow floating point comparisons
- *     - define UNITY_FLOAT_PRECISION to specify the precision to use when doing TEST_ASSERT_EQUAL_FLOAT
- *     - define UNITY_FLOAT_TYPE to specify doubles instead of single precision floats
- *     - define UNITY_INCLUDE_DOUBLE to allow double floating point comparisons
- *     - define UNITY_EXCLUDE_DOUBLE to disallow double floating point comparisons (default)
- *     - define UNITY_DOUBLE_PRECISION to specify the precision to use when doing TEST_ASSERT_EQUAL_DOUBLE
- *     - define UNITY_DOUBLE_TYPE to specify something other than double
- *     - define UNITY_EXCLUDE_FLOAT_PRINT to trim binary size, won't print floating point values in errors
-
- * Output
- *     - by default, Unity prints to standard out with putchar.  define UNITY_OUTPUT_CHAR(a) with a different function if desired
- *     - define UNITY_DIFFERENTIATE_FINAL_FAIL to print FAILED (vs. FAIL) at test end summary - for automated search for failure
-
- * Optimization
- *     - by default, line numbers are stored in unsigned shorts.  Define UNITY_LINE_TYPE with a different type if your files are huge
- *     - by default, test and failure counters are unsigned shorts.  Define UNITY_COUNTER_TYPE with a different type if you want to save space or have more than 65535 Tests.
-
- * Test Cases
- *     - define UNITY_SUPPORT_TEST_CASES to include the TEST_CASE macro, though really it's mostly about the runner generator script
-
- * Parameterized Tests
- *     - you'll want to create a define of TEST_CASE(...) which basically evaluates to nothing
-
- * Tests with Arguments
- *     - you'll want to define UNITY_USE_COMMAND_LINE_ARGS if you have the test runner passing arguments to Unity
-
- *-------------------------------------------------------
- * Basic Fail and Ignore
- *-------------------------------------------------------*/
-
-#define TEST_FAIL_MESSAGE(message)                                                                 UNITY_TEST_FAIL(__LINE__, (message))
-#define TEST_FAIL()                                                                                UNITY_TEST_FAIL(__LINE__, NULL)
-#define TEST_IGNORE_MESSAGE(message)                                                               UNITY_TEST_IGNORE(__LINE__, (message))
-#define TEST_IGNORE()                                                                              UNITY_TEST_IGNORE(__LINE__, NULL)
-#define TEST_MESSAGE(message)                                                                      UnityMessage((message), __LINE__)
-#define TEST_ONLY()
-
-/* It is not necessary for you to call PASS. A PASS condition is assumed if nothing fails.
- * This method allows you to abort a test immediately with a PASS state, ignoring the remainder of the test. */
-#define TEST_PASS()                                                                                TEST_ABORT()
-#define TEST_PASS_MESSAGE(message)                                                                 do { UnityMessage((message), __LINE__); TEST_ABORT(); } while(0)
-
-/* This macro does nothing, but it is useful for build tools (like Ceedling) to make use of this to figure out
- * which files should be linked to in order to perform a test. Use it like TEST_FILE("sandwiches.c") */
-#define TEST_FILE(a)
-
-/*-------------------------------------------------------
- * Test Asserts (simple)
- *-------------------------------------------------------*/
-
-/* Boolean */
-#define TEST_ASSERT(condition)                                                                     UNITY_TEST_ASSERT(       (condition), __LINE__, " Expression Evaluated To FALSE")
-#define TEST_ASSERT_TRUE(condition)                                                                UNITY_TEST_ASSERT(       (condition), __LINE__, " Expected TRUE Was FALSE")
-#define TEST_ASSERT_UNLESS(condition)                                                              UNITY_TEST_ASSERT(      !(condition), __LINE__, " Expression Evaluated To TRUE")
-#define TEST_ASSERT_FALSE(condition)                                                               UNITY_TEST_ASSERT(      !(condition), __LINE__, " Expected FALSE Was TRUE")
-#define TEST_ASSERT_NULL(pointer)                                                                  UNITY_TEST_ASSERT_NULL(    (pointer), __LINE__, " Expected NULL")
-#define TEST_ASSERT_NOT_NULL(pointer)                                                              UNITY_TEST_ASSERT_NOT_NULL((pointer), __LINE__, " Expected Non-NULL")
-
-/* Integers (of all sizes) */
-#define TEST_ASSERT_EQUAL_INT(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT8(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_INT8((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT16(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_INT16((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT32(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_INT32((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT64(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_INT64((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_UINT( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT8(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_UINT8( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT16(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT16( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT32(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT32( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT64(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT64( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_size_t(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX8(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_HEX8( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX16(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX16((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX32(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX64(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX64((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_CHAR(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_CHAR((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS(mask, expected, actual)                                                   UNITY_TEST_ASSERT_BITS((mask), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS_HIGH(mask, actual)                                                        UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(-1), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS_LOW(mask, actual)                                                         UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(0), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BIT_HIGH(bit, actual)                                                          UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(-1), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BIT_LOW(bit, actual)                                                           UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(0), (actual), __LINE__, NULL)
-
-/* Integer Greater Than/ Less Than (of all sizes) */
-#define TEST_ASSERT_GREATER_THAN(threshold, actual)                                                UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT(threshold, actual)                                            UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT8(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT16(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT32(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT64(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT8(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT16(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT32(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_size_t(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX8(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX16(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX32(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_HEX64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_CHAR(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_CHAR((threshold), (actual), __LINE__, NULL)
-
-#define TEST_ASSERT_LESS_THAN(threshold, actual)                                                   UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT(threshold, actual)                                               UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT8(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT16(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT32(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT64(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT8(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT16(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT32(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT64(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_size_t(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX8(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX16(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX32(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX64(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_CHAR(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_CHAR((threshold), (actual), __LINE__, NULL)
-
-#define TEST_ASSERT_GREATER_OR_EQUAL(threshold, actual)                                            UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT(threshold, actual)                                        UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT8(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT16(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT32(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT64(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT8(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT16(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT32(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT64(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_size_t(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX8(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX16(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX32(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX64(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_CHAR(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_CHAR((threshold), (actual), __LINE__, NULL)
-
-#define TEST_ASSERT_LESS_OR_EQUAL(threshold, actual)                                               UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT(threshold, actual)                                           UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT8(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT16(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT32(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT64(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT8(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT16(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT32(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT64(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_size_t(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX8(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX16(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX32(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX64(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_CHAR(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_CHAR((threshold), (actual), __LINE__, NULL)
-
-/* Integer Ranges (of all sizes) */
-#define TEST_ASSERT_INT_WITHIN(delta, expected, actual)                                            UNITY_TEST_ASSERT_INT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT8_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_INT8_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT16_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_INT16_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT32_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_INT32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT64_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_INT64_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_UINT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT8_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_UINT8_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT16_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT16_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT32_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT64_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT64_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_size_t_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX_WITHIN(delta, expected, actual)                                            UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX8_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_HEX8_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX16_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_HEX16_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX32_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX64_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_HEX64_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_CHAR_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_CHAR_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-
-/* Integer Array Ranges (of all sizes) */
-#define TEST_ASSERT_INT_ARRAY_WITHIN(delta, expected, actual, num_elements)                        UNITY_TEST_ASSERT_INT_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_INT8_ARRAY_WITHIN(delta, expected, actual, num_elements)                       UNITY_TEST_ASSERT_INT8_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_INT16_ARRAY_WITHIN(delta, expected, actual, num_elements)                      UNITY_TEST_ASSERT_INT16_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_INT32_ARRAY_WITHIN(delta, expected, actual, num_elements)                      UNITY_TEST_ASSERT_INT32_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_INT64_ARRAY_WITHIN(delta, expected, actual, num_elements)                      UNITY_TEST_ASSERT_INT64_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_UINT_ARRAY_WITHIN(delta, expected, actual, num_elements)                       UNITY_TEST_ASSERT_UINT_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_UINT8_ARRAY_WITHIN(delta, expected, actual, num_elements)                      UNITY_TEST_ASSERT_UINT8_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_UINT16_ARRAY_WITHIN(delta, expected, actual, num_elements)                     UNITY_TEST_ASSERT_UINT16_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_UINT32_ARRAY_WITHIN(delta, expected, actual, num_elements)                     UNITY_TEST_ASSERT_UINT32_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_UINT64_ARRAY_WITHIN(delta, expected, actual, num_elements)                     UNITY_TEST_ASSERT_UINT64_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_size_t_ARRAY_WITHIN(delta, expected, actual, num_elements)                     UNITY_TEST_ASSERT_UINT_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_HEX_ARRAY_WITHIN(delta, expected, actual, num_elements)                        UNITY_TEST_ASSERT_HEX32_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_HEX8_ARRAY_WITHIN(delta, expected, actual, num_elements)                       UNITY_TEST_ASSERT_HEX8_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_HEX16_ARRAY_WITHIN(delta, expected, actual, num_elements)                      UNITY_TEST_ASSERT_HEX16_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_HEX32_ARRAY_WITHIN(delta, expected, actual, num_elements)                      UNITY_TEST_ASSERT_HEX32_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_HEX64_ARRAY_WITHIN(delta, expected, actual, num_elements)                      UNITY_TEST_ASSERT_HEX64_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-#define TEST_ASSERT_CHAR_ARRAY_WITHIN(delta, expected, actual, num_elements)                       UNITY_TEST_ASSERT_CHAR_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, NULL)
-
-
-/* Structs and Strings */
-#define TEST_ASSERT_EQUAL_PTR(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_PTR((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_STRING(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_STRING((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_STRING_LEN(expected, actual, len)                                        UNITY_TEST_ASSERT_EQUAL_STRING_LEN((expected), (actual), (len), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_MEMORY(expected, actual, len)                                            UNITY_TEST_ASSERT_EQUAL_MEMORY((expected), (actual), (len), __LINE__, NULL)
-
-/* Arrays */
-#define TEST_ASSERT_EQUAL_INT_ARRAY(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EQUAL_INT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT8_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_INT8_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT16_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_INT16_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT32_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_INT32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT64_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT8_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_UINT8_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT16_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT16_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT32_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT64_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_size_t_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX_ARRAY(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX8_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_HEX8_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX16_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_HEX16_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX32_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX64_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_PTR_ARRAY(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EQUAL_PTR_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_STRING_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_STRING_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_MEMORY_ARRAY(expected, actual, len, num_elements)                        UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((expected), (actual), (len), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_CHAR_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_CHAR_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-
-/* Arrays Compared To Single Value */
-#define TEST_ASSERT_EACH_EQUAL_INT(expected, actual, num_elements)                                 UNITY_TEST_ASSERT_EACH_EQUAL_INT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT8(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_INT8((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT16(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_INT16((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT32(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_INT32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT64(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_INT64((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_UINT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT8(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_UINT8((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT16(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT16((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT32(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT64(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT64((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_size_t(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX(expected, actual, num_elements)                                 UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX8(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_HEX8((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX16(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_HEX16((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX32(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX64(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_HEX64((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_PTR(expected, actual, num_elements)                                 UNITY_TEST_ASSERT_EACH_EQUAL_PTR((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_STRING(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_STRING((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_MEMORY(expected, actual, len, num_elements)                         UNITY_TEST_ASSERT_EACH_EQUAL_MEMORY((expected), (actual), (len), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_CHAR(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_CHAR((expected), (actual), (num_elements), __LINE__, NULL)
-
-/* Floating Point (If Enabled) */
-#define TEST_ASSERT_FLOAT_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_FLOAT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_FLOAT(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_FLOAT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_FLOAT_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_FLOAT(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_INF(actual)                                                           UNITY_TEST_ASSERT_FLOAT_IS_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NEG_INF(actual)                                                       UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NAN(actual)                                                           UNITY_TEST_ASSERT_FLOAT_IS_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_DETERMINATE(actual)                                                   UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_INF(actual)                                                       UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_NEG_INF(actual)                                                   UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_NAN(actual)                                                       UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE(actual)                                               UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE((actual), __LINE__, NULL)
-
-/* Double (If Enabled) */
-#define TEST_ASSERT_DOUBLE_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_DOUBLE_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_DOUBLE(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_DOUBLE((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_DOUBLE_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_DOUBLE(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_INF(actual)                                                          UNITY_TEST_ASSERT_DOUBLE_IS_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NEG_INF(actual)                                                      UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NAN(actual)                                                          UNITY_TEST_ASSERT_DOUBLE_IS_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_DETERMINATE(actual)                                                  UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_INF(actual)                                                      UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF(actual)                                                  UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_NAN(actual)                                                      UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual)                                              UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE((actual), __LINE__, NULL)
-
-/* Shorthand */
-#ifdef UNITY_SHORTHAND_AS_OLD
-#define TEST_ASSERT_EQUAL(expected, actual)                                                        UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_NOT_EQUAL(expected, actual)                                                    UNITY_TEST_ASSERT(((expected) != (actual)), __LINE__, " Expected Not-Equal")
-#endif
-#ifdef UNITY_SHORTHAND_AS_INT
-#define TEST_ASSERT_EQUAL(expected, actual)                                                        UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_NOT_EQUAL(expected, actual)                                                    UNITY_TEST_FAIL(__LINE__, UnityStrErrShorthand)
-#endif
-#ifdef UNITY_SHORTHAND_AS_MEM
-#define TEST_ASSERT_EQUAL(expected, actual)                                                        UNITY_TEST_ASSERT_EQUAL_MEMORY((&expected), (&actual), sizeof(expected), __LINE__, NULL)
-#define TEST_ASSERT_NOT_EQUAL(expected, actual)                                                    UNITY_TEST_FAIL(__LINE__, UnityStrErrShorthand)
-#endif
-#ifdef UNITY_SHORTHAND_AS_RAW
-#define TEST_ASSERT_EQUAL(expected, actual)                                                        UNITY_TEST_ASSERT(((expected) == (actual)), __LINE__, " Expected Equal")
-#define TEST_ASSERT_NOT_EQUAL(expected, actual)                                                    UNITY_TEST_ASSERT(((expected) != (actual)), __LINE__, " Expected Not-Equal")
-#endif
-#ifdef UNITY_SHORTHAND_AS_NONE
-#define TEST_ASSERT_EQUAL(expected, actual)                                                        UNITY_TEST_FAIL(__LINE__, UnityStrErrShorthand)
-#define TEST_ASSERT_NOT_EQUAL(expected, actual)                                                    UNITY_TEST_FAIL(__LINE__, UnityStrErrShorthand)
-#endif
-
-/*-------------------------------------------------------
- * Test Asserts (with additional messages)
- *-------------------------------------------------------*/
-
-/* Boolean */
-#define TEST_ASSERT_MESSAGE(condition, message)                                                    UNITY_TEST_ASSERT(       (condition), __LINE__, (message))
-#define TEST_ASSERT_TRUE_MESSAGE(condition, message)                                               UNITY_TEST_ASSERT(       (condition), __LINE__, (message))
-#define TEST_ASSERT_UNLESS_MESSAGE(condition, message)                                             UNITY_TEST_ASSERT(      !(condition), __LINE__, (message))
-#define TEST_ASSERT_FALSE_MESSAGE(condition, message)                                              UNITY_TEST_ASSERT(      !(condition), __LINE__, (message))
-#define TEST_ASSERT_NULL_MESSAGE(pointer, message)                                                 UNITY_TEST_ASSERT_NULL(    (pointer), __LINE__, (message))
-#define TEST_ASSERT_NOT_NULL_MESSAGE(pointer, message)                                             UNITY_TEST_ASSERT_NOT_NULL((pointer), __LINE__, (message))
-
-/* Integers (of all sizes) */
-#define TEST_ASSERT_EQUAL_INT_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT8_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_INT8((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT16_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_INT16((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT32_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_INT32((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT64_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_INT64((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_UINT( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT8_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_UINT8( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT16_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT16( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT32_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT32( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT64_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT64( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_size_t_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX8_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_HEX8( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX16_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_HEX16((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX32_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX64_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_HEX64((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_BITS_MESSAGE(mask, expected, actual, message)                                  UNITY_TEST_ASSERT_BITS((mask), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_BITS_HIGH_MESSAGE(mask, actual, message)                                       UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(-1), (actual), __LINE__, (message))
-#define TEST_ASSERT_BITS_LOW_MESSAGE(mask, actual, message)                                        UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(0), (actual), __LINE__, (message))
-#define TEST_ASSERT_BIT_HIGH_MESSAGE(bit, actual, message)                                         UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(-1), (actual), __LINE__, (message))
-#define TEST_ASSERT_BIT_LOW_MESSAGE(bit, actual, message)                                          UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(0), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_CHAR_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_CHAR((expected), (actual), __LINE__, (message))
-
-/* Integer Greater Than/ Less Than (of all sizes) */
-#define TEST_ASSERT_GREATER_THAN_MESSAGE(threshold, actual, message)                               UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT8_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT16_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT32_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT64_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT8_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT16_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT32_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT64_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_size_t_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX8_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX16_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX32_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX64_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_HEX64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_CHAR_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_CHAR((threshold), (actual), __LINE__, (message))
-
-#define TEST_ASSERT_LESS_THAN_MESSAGE(threshold, actual, message)                                  UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT_MESSAGE(threshold, actual, message)                              UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT8_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT16_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT32_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT64_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT8_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT16_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT32_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT64_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_size_t_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX8_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX16_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX32_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX64_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_HEX64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_CHAR_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_CHAR((threshold), (actual), __LINE__, (message))
-
-#define TEST_ASSERT_GREATER_OR_EQUAL_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT8_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT16_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT32_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT64_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT8_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT16_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT32_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT64_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_size_t_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX8_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX16_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX32_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX64_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_CHAR_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_CHAR((threshold), (actual), __LINE__, (message))
-
-#define TEST_ASSERT_LESS_OR_EQUAL_MESSAGE(threshold, actual, message)                              UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT8_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT16_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT32_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT64_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT8_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT16_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT32_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT64_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_size_t_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX8_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX16_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX32_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX64_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_CHAR_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_CHAR((threshold), (actual), __LINE__, (message))
-
-/* Integer Ranges (of all sizes) */
-#define TEST_ASSERT_INT_WITHIN_MESSAGE(delta, expected, actual, message)                           UNITY_TEST_ASSERT_INT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT8_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_INT8_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT16_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_INT16_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT32_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_INT32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT64_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_INT64_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_UINT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT8_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_UINT8_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT16_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT16_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT32_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT64_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT64_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_size_t_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX_WITHIN_MESSAGE(delta, expected, actual, message)                           UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX8_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_HEX8_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX16_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_HEX16_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX32_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX64_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_HEX64_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_CHAR_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_CHAR_WITHIN((delta), (expected), (actual), __LINE__, (message))
-
-/* Integer Array Ranges (of all sizes) */
-#define TEST_ASSERT_INT_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)       UNITY_TEST_ASSERT_INT_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_INT8_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)      UNITY_TEST_ASSERT_INT8_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_INT16_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)     UNITY_TEST_ASSERT_INT16_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_INT32_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)     UNITY_TEST_ASSERT_INT32_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_INT64_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)     UNITY_TEST_ASSERT_INT64_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_UINT_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)      UNITY_TEST_ASSERT_UINT_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_UINT8_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)     UNITY_TEST_ASSERT_UINT8_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_UINT16_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)    UNITY_TEST_ASSERT_UINT16_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_UINT32_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)    UNITY_TEST_ASSERT_UINT32_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_UINT64_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)    UNITY_TEST_ASSERT_UINT64_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_size_t_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)    UNITY_TEST_ASSERT_UINT_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_HEX_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)       UNITY_TEST_ASSERT_HEX32_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_HEX8_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)      UNITY_TEST_ASSERT_HEX8_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_HEX16_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)     UNITY_TEST_ASSERT_HEX16_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_HEX32_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)     UNITY_TEST_ASSERT_HEX32_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_HEX64_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)     UNITY_TEST_ASSERT_HEX64_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-#define TEST_ASSERT_CHAR_ARRAY_WITHIN_MESSAGE(delta, expected, actual, num_elements, message)      UNITY_TEST_ASSERT_CHAR_ARRAY_WITHIN((delta), (expected), (actual), num_elements, __LINE__, (message))
-
-
-/* Structs and Strings */
-#define TEST_ASSERT_EQUAL_PTR_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_PTR((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_STRING_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_STRING((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_STRING_LEN_MESSAGE(expected, actual, len, message)                       UNITY_TEST_ASSERT_EQUAL_STRING_LEN((expected), (actual), (len), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_MEMORY_MESSAGE(expected, actual, len, message)                           UNITY_TEST_ASSERT_EQUAL_MEMORY((expected), (actual), (len), __LINE__, (message))
-
-/* Arrays */
-#define TEST_ASSERT_EQUAL_INT_ARRAY_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EQUAL_INT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT8_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_INT8_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT16_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_INT16_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT32_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_INT32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT64_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT8_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_UINT8_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT16_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT16_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT32_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT64_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_size_t_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX_ARRAY_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX8_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_HEX8_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX16_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_HEX16_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX32_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX64_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_PTR_ARRAY_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EQUAL_PTR_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_STRING_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_STRING_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_MEMORY_ARRAY_MESSAGE(expected, actual, len, num_elements, message)       UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((expected), (actual), (len), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_CHAR_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_CHAR_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-
-/* Arrays Compared To Single Value*/
-#define TEST_ASSERT_EACH_EQUAL_INT_MESSAGE(expected, actual, num_elements, message)                UNITY_TEST_ASSERT_EACH_EQUAL_INT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT8_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_INT8((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT16_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_INT16((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT32_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_INT32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT64_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_INT64((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_UINT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT8_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_UINT8((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT16_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT16((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT32_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT64_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT64((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_size_t_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX_MESSAGE(expected, actual, num_elements, message)                UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX8_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_HEX8((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX16_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_HEX16((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX32_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX64_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_HEX64((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_PTR_MESSAGE(expected, actual, num_elements, message)                UNITY_TEST_ASSERT_EACH_EQUAL_PTR((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_STRING_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_STRING((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_MEMORY_MESSAGE(expected, actual, len, num_elements, message)        UNITY_TEST_ASSERT_EACH_EQUAL_MEMORY((expected), (actual), (len), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_CHAR_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_CHAR((expected), (actual), (num_elements), __LINE__, (message))
-
-/* Floating Point (If Enabled) */
-#define TEST_ASSERT_FLOAT_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_FLOAT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_FLOAT_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_FLOAT((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_FLOAT_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_FLOAT_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_INF_MESSAGE(actual, message)                                          UNITY_TEST_ASSERT_FLOAT_IS_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NEG_INF_MESSAGE(actual, message)                                      UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NAN_MESSAGE(actual, message)                                          UNITY_TEST_ASSERT_FLOAT_IS_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_DETERMINATE_MESSAGE(actual, message)                                  UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_INF_MESSAGE(actual, message)                                      UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_NEG_INF_MESSAGE(actual, message)                                  UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_NAN_MESSAGE(actual, message)                                      UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE_MESSAGE(actual, message)                              UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE((actual), __LINE__, (message))
-
-/* Double (If Enabled) */
-#define TEST_ASSERT_DOUBLE_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_DOUBLE_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_DOUBLE_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_DOUBLE((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_DOUBLE_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_DOUBLE_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_INF_MESSAGE(actual, message)                                         UNITY_TEST_ASSERT_DOUBLE_IS_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NEG_INF_MESSAGE(actual, message)                                     UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NAN_MESSAGE(actual, message)                                         UNITY_TEST_ASSERT_DOUBLE_IS_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_DETERMINATE_MESSAGE(actual, message)                                 UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_INF_MESSAGE(actual, message)                                     UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF_MESSAGE(actual, message)                                 UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_NAN_MESSAGE(actual, message)                                     UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE_MESSAGE(actual, message)                             UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE((actual), __LINE__, (message))
-
-/* Shorthand */
-#ifdef UNITY_SHORTHAND_AS_OLD
-#define TEST_ASSERT_EQUAL_MESSAGE(expected, actual, message)                                       UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_NOT_EQUAL_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT(((expected) != (actual)), __LINE__, (message))
-#endif
-#ifdef UNITY_SHORTHAND_AS_INT
-#define TEST_ASSERT_EQUAL_MESSAGE(expected, actual, message)                                       UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, message)
-#define TEST_ASSERT_NOT_EQUAL_MESSAGE(expected, actual, message)                                   UNITY_TEST_FAIL(__LINE__, UnityStrErrShorthand)
-#endif
-#ifdef  UNITY_SHORTHAND_AS_MEM
-#define TEST_ASSERT_EQUAL_MESSAGE(expected, actual, message)                                       UNITY_TEST_ASSERT_EQUAL_MEMORY((&expected), (&actual), sizeof(expected), __LINE__, message)
-#define TEST_ASSERT_NOT_EQUAL_MESSAGE(expected, actual, message)                                   UNITY_TEST_FAIL(__LINE__, UnityStrErrShorthand)
-#endif
-#ifdef  UNITY_SHORTHAND_AS_RAW
-#define TEST_ASSERT_EQUAL_MESSAGE(expected, actual, message)                                       UNITY_TEST_ASSERT(((expected) == (actual)), __LINE__, message)
-#define TEST_ASSERT_NOT_EQUAL_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT(((expected) != (actual)), __LINE__, message)
-#endif
-#ifdef UNITY_SHORTHAND_AS_NONE
-#define TEST_ASSERT_EQUAL_MESSAGE(expected, actual, message)                                       UNITY_TEST_FAIL(__LINE__, UnityStrErrShorthand)
-#define TEST_ASSERT_NOT_EQUAL_MESSAGE(expected, actual, message)                                   UNITY_TEST_FAIL(__LINE__, UnityStrErrShorthand)
-#endif
-
-/* end of UNITY_FRAMEWORK_H */
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/test/vendor/ceedling/vendor/unity/src/unity_internals.h b/test/vendor/ceedling/vendor/unity/src/unity_internals.h
deleted file mode 100644
index a9a7ea237..000000000
--- a/test/vendor/ceedling/vendor/unity/src/unity_internals.h
+++ /dev/null
@@ -1,1002 +0,0 @@
-/* ==========================================
-    Unity Project - A Test Framework for C
-    Copyright (c) 2007-19 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-========================================== */
-
-#ifndef UNITY_INTERNALS_H
-#define UNITY_INTERNALS_H
-
-#ifdef UNITY_INCLUDE_CONFIG_H
-#include "unity_config.h"
-#endif
-
-#ifndef UNITY_EXCLUDE_SETJMP_H
-#include <setjmp.h>
-#endif
-
-#ifndef UNITY_EXCLUDE_MATH_H
-#include <math.h>
-#endif
-
-#ifndef UNITY_EXCLUDE_STDDEF_H
-#include <stddef.h>
-#endif
-
-#ifdef UNITY_INCLUDE_PRINT_FORMATTED
-#include <stdarg.h>
-#endif
-
-/* Unity Attempts to Auto-Detect Integer Types
- * Attempt 1: UINT_MAX, ULONG_MAX in <limits.h>, or default to 32 bits
- * Attempt 2: UINTPTR_MAX in <stdint.h>, or default to same size as long
- * The user may override any of these derived constants:
- * UNITY_INT_WIDTH, UNITY_LONG_WIDTH, UNITY_POINTER_WIDTH */
-#ifndef UNITY_EXCLUDE_STDINT_H
-#include <stdint.h>
-#endif
-
-#ifndef UNITY_EXCLUDE_LIMITS_H
-#include <limits.h>
-#endif
-
-/*-------------------------------------------------------
- * Guess Widths If Not Specified
- *-------------------------------------------------------*/
-
-/* Determine the size of an int, if not already specified.
- * We cannot use sizeof(int), because it is not yet defined
- * at this stage in the translation of the C program.
- * Also sizeof(int) does return the size in addressable units on all platforms,
- * which may not necessarily be the size in bytes.
- * Therefore, infer it from UINT_MAX if possible. */
-#ifndef UNITY_INT_WIDTH
-  #ifdef UINT_MAX
-    #if (UINT_MAX == 0xFFFF)
-      #define UNITY_INT_WIDTH (16)
-    #elif (UINT_MAX == 0xFFFFFFFF)
-      #define UNITY_INT_WIDTH (32)
-    #elif (UINT_MAX == 0xFFFFFFFFFFFFFFFF)
-      #define UNITY_INT_WIDTH (64)
-    #endif
-  #else /* Set to default */
-    #define UNITY_INT_WIDTH (32)
-  #endif /* UINT_MAX */
-#endif
-
-/* Determine the size of a long, if not already specified. */
-#ifndef UNITY_LONG_WIDTH
-  #ifdef ULONG_MAX
-    #if (ULONG_MAX == 0xFFFF)
-      #define UNITY_LONG_WIDTH (16)
-    #elif (ULONG_MAX == 0xFFFFFFFF)
-      #define UNITY_LONG_WIDTH (32)
-    #elif (ULONG_MAX == 0xFFFFFFFFFFFFFFFF)
-      #define UNITY_LONG_WIDTH (64)
-    #endif
-  #else /* Set to default */
-    #define UNITY_LONG_WIDTH (32)
-  #endif /* ULONG_MAX */
-#endif
-
-/* Determine the size of a pointer, if not already specified. */
-#ifndef UNITY_POINTER_WIDTH
-  #ifdef UINTPTR_MAX
-    #if (UINTPTR_MAX <= 0xFFFF)
-      #define UNITY_POINTER_WIDTH (16)
-    #elif (UINTPTR_MAX <= 0xFFFFFFFF)
-      #define UNITY_POINTER_WIDTH (32)
-    #elif (UINTPTR_MAX <= 0xFFFFFFFFFFFFFFFF)
-      #define UNITY_POINTER_WIDTH (64)
-    #endif
-  #else /* Set to default */
-    #define UNITY_POINTER_WIDTH UNITY_LONG_WIDTH
-  #endif /* UINTPTR_MAX */
-#endif
-
-/*-------------------------------------------------------
- * Int Support (Define types based on detected sizes)
- *-------------------------------------------------------*/
-
-#if (UNITY_INT_WIDTH == 32)
-    typedef unsigned char   UNITY_UINT8;
-    typedef unsigned short  UNITY_UINT16;
-    typedef unsigned int    UNITY_UINT32;
-    typedef signed char     UNITY_INT8;
-    typedef signed short    UNITY_INT16;
-    typedef signed int      UNITY_INT32;
-#elif (UNITY_INT_WIDTH == 16)
-    typedef unsigned char   UNITY_UINT8;
-    typedef unsigned int    UNITY_UINT16;
-    typedef unsigned long   UNITY_UINT32;
-    typedef signed char     UNITY_INT8;
-    typedef signed int      UNITY_INT16;
-    typedef signed long     UNITY_INT32;
-#else
-    #error Invalid UNITY_INT_WIDTH specified! (16 or 32 are supported)
-#endif
-
-/*-------------------------------------------------------
- * 64-bit Support
- *-------------------------------------------------------*/
-
-/* Auto-detect 64 Bit Support */
-#ifndef UNITY_SUPPORT_64
-  #if UNITY_LONG_WIDTH == 64 || UNITY_POINTER_WIDTH == 64
-    #define UNITY_SUPPORT_64
-  #endif
-#endif
-
-/* 64-Bit Support Dependent Configuration */
-#ifndef UNITY_SUPPORT_64
-    /* No 64-bit Support */
-    typedef UNITY_UINT32 UNITY_UINT;
-    typedef UNITY_INT32  UNITY_INT;
-    #define UNITY_MAX_NIBBLES (8)  /* Maximum number of nibbles in a UNITY_(U)INT */
-#else
-  /* 64-bit Support */
-  #if (UNITY_LONG_WIDTH == 32)
-    typedef unsigned long long UNITY_UINT64;
-    typedef signed long long   UNITY_INT64;
-  #elif (UNITY_LONG_WIDTH == 64)
-    typedef unsigned long      UNITY_UINT64;
-    typedef signed long        UNITY_INT64;
-  #else
-    #error Invalid UNITY_LONG_WIDTH specified! (32 or 64 are supported)
-  #endif
-    typedef UNITY_UINT64 UNITY_UINT;
-    typedef UNITY_INT64  UNITY_INT;
-    #define UNITY_MAX_NIBBLES (16) /* Maximum number of nibbles in a UNITY_(U)INT */
-#endif
-
-/*-------------------------------------------------------
- * Pointer Support
- *-------------------------------------------------------*/
-
-#if (UNITY_POINTER_WIDTH == 32)
-  #define UNITY_PTR_TO_INT UNITY_INT32
-  #define UNITY_DISPLAY_STYLE_POINTER UNITY_DISPLAY_STYLE_HEX32
-#elif (UNITY_POINTER_WIDTH == 64)
-  #define UNITY_PTR_TO_INT UNITY_INT64
-  #define UNITY_DISPLAY_STYLE_POINTER UNITY_DISPLAY_STYLE_HEX64
-#elif (UNITY_POINTER_WIDTH == 16)
-  #define UNITY_PTR_TO_INT UNITY_INT16
-  #define UNITY_DISPLAY_STYLE_POINTER UNITY_DISPLAY_STYLE_HEX16
-#else
-  #error Invalid UNITY_POINTER_WIDTH specified! (16, 32 or 64 are supported)
-#endif
-
-#ifndef UNITY_PTR_ATTRIBUTE
-  #define UNITY_PTR_ATTRIBUTE
-#endif
-
-#ifndef UNITY_INTERNAL_PTR
-  #define UNITY_INTERNAL_PTR UNITY_PTR_ATTRIBUTE const void*
-#endif
-
-/*-------------------------------------------------------
- * Float Support
- *-------------------------------------------------------*/
-
-#ifdef UNITY_EXCLUDE_FLOAT
-
-/* No Floating Point Support */
-#ifndef UNITY_EXCLUDE_DOUBLE
-#define UNITY_EXCLUDE_DOUBLE /* Remove double when excluding float support */
-#endif
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-#define UNITY_EXCLUDE_FLOAT_PRINT
-#endif
-
-#else
-
-/* Floating Point Support */
-#ifndef UNITY_FLOAT_PRECISION
-#define UNITY_FLOAT_PRECISION (0.00001f)
-#endif
-#ifndef UNITY_FLOAT_TYPE
-#define UNITY_FLOAT_TYPE float
-#endif
-typedef UNITY_FLOAT_TYPE UNITY_FLOAT;
-
-/* isinf & isnan macros should be provided by math.h */
-#ifndef isinf
-/* The value of Inf - Inf is NaN */
-#define isinf(n) (isnan((n) - (n)) && !isnan(n))
-#endif
-
-#ifndef isnan
-/* NaN is the only floating point value that does NOT equal itself.
- * Therefore if n != n, then it is NaN. */
-#define isnan(n) ((n != n) ? 1 : 0)
-#endif
-
-#endif
-
-/*-------------------------------------------------------
- * Double Float Support
- *-------------------------------------------------------*/
-
-/* unlike float, we DON'T include by default */
-#if defined(UNITY_EXCLUDE_DOUBLE) || !defined(UNITY_INCLUDE_DOUBLE)
-
-  /* No Floating Point Support */
-  #ifndef UNITY_EXCLUDE_DOUBLE
-  #define UNITY_EXCLUDE_DOUBLE
-  #else
-    #undef UNITY_INCLUDE_DOUBLE
-  #endif
-
-  #ifndef UNITY_EXCLUDE_FLOAT
-    #ifndef UNITY_DOUBLE_TYPE
-    #define UNITY_DOUBLE_TYPE double
-    #endif
-  typedef UNITY_FLOAT UNITY_DOUBLE;
-  /* For parameter in UnityPrintFloat(UNITY_DOUBLE), which aliases to double or float */
-  #endif
-
-#else
-
-  /* Double Floating Point Support */
-  #ifndef UNITY_DOUBLE_PRECISION
-  #define UNITY_DOUBLE_PRECISION (1e-12)
-  #endif
-
-  #ifndef UNITY_DOUBLE_TYPE
-  #define UNITY_DOUBLE_TYPE double
-  #endif
-  typedef UNITY_DOUBLE_TYPE UNITY_DOUBLE;
-
-#endif
-
-/*-------------------------------------------------------
- * Output Method: stdout (DEFAULT)
- *-------------------------------------------------------*/
-#ifndef UNITY_OUTPUT_CHAR
-  /* Default to using putchar, which is defined in stdio.h */
-  #include <stdio.h>
-  #define UNITY_OUTPUT_CHAR(a) (void)putchar(a)
-#else
-  /* If defined as something else, make sure we declare it here so it's ready for use */
-  #ifdef UNITY_OUTPUT_CHAR_HEADER_DECLARATION
-    extern void UNITY_OUTPUT_CHAR_HEADER_DECLARATION;
-  #endif
-#endif
-
-#ifndef UNITY_OUTPUT_FLUSH
-  #ifdef UNITY_USE_FLUSH_STDOUT
-    /* We want to use the stdout flush utility */
-    #include <stdio.h>
-    #define UNITY_OUTPUT_FLUSH() (void)fflush(stdout)
-  #else
-    /* We've specified nothing, therefore flush should just be ignored */
-    #define UNITY_OUTPUT_FLUSH()
-  #endif
-#else
-  /* If defined as something else, make sure we declare it here so it's ready for use */
-  #ifdef UNITY_OUTPUT_FLUSH_HEADER_DECLARATION
-    extern void UNITY_OUTPUT_FLUSH_HEADER_DECLARATION;
-  #endif
-#endif
-
-#ifndef UNITY_OUTPUT_FLUSH
-#define UNITY_FLUSH_CALL()
-#else
-#define UNITY_FLUSH_CALL() UNITY_OUTPUT_FLUSH()
-#endif
-
-#ifndef UNITY_PRINT_EOL
-#define UNITY_PRINT_EOL()    UNITY_OUTPUT_CHAR('\n')
-#endif
-
-#ifndef UNITY_OUTPUT_START
-#define UNITY_OUTPUT_START()
-#endif
-
-#ifndef UNITY_OUTPUT_COMPLETE
-#define UNITY_OUTPUT_COMPLETE()
-#endif
-
-#ifdef UNITY_INCLUDE_EXEC_TIME
-  #if !defined(UNITY_EXEC_TIME_START) && \
-      !defined(UNITY_EXEC_TIME_STOP) && \
-      !defined(UNITY_PRINT_EXEC_TIME) && \
-      !defined(UNITY_TIME_TYPE)
-      /* If none any of these macros are defined then try to provide a default implementation */
-
-    #if defined(UNITY_CLOCK_MS)
-      /* This is a simple way to get a default implementation on platforms that support getting a millisecond counter */
-      #define UNITY_TIME_TYPE UNITY_UINT
-      #define UNITY_EXEC_TIME_START() Unity.CurrentTestStartTime = UNITY_CLOCK_MS()
-      #define UNITY_EXEC_TIME_STOP() Unity.CurrentTestStopTime = UNITY_CLOCK_MS()
-      #define UNITY_PRINT_EXEC_TIME() { \
-        UNITY_UINT execTimeMs = (Unity.CurrentTestStopTime - Unity.CurrentTestStartTime); \
-        UnityPrint(" ("); \
-        UnityPrintNumberUnsigned(execTimeMs); \
-        UnityPrint(" ms)"); \
-        }
-    #elif defined(_WIN32)
-      #include <time.h>
-      #define UNITY_TIME_TYPE clock_t
-      #define UNITY_GET_TIME(t) t = (clock_t)((clock() * 1000) / CLOCKS_PER_SEC)
-      #define UNITY_EXEC_TIME_START() UNITY_GET_TIME(Unity.CurrentTestStartTime)
-      #define UNITY_EXEC_TIME_STOP() UNITY_GET_TIME(Unity.CurrentTestStopTime)
-      #define UNITY_PRINT_EXEC_TIME() { \
-        UNITY_UINT execTimeMs = (Unity.CurrentTestStopTime - Unity.CurrentTestStartTime); \
-        UnityPrint(" ("); \
-        UnityPrintNumberUnsigned(execTimeMs); \
-        UnityPrint(" ms)"); \
-        }
-    #elif defined(__unix__)
-      #include <time.h>
-      #define UNITY_TIME_TYPE struct timespec
-      #define UNITY_GET_TIME(t) clock_gettime(CLOCK_MONOTONIC, &t)
-      #define UNITY_EXEC_TIME_START() UNITY_GET_TIME(Unity.CurrentTestStartTime)
-      #define UNITY_EXEC_TIME_STOP() UNITY_GET_TIME(Unity.CurrentTestStopTime)
-      #define UNITY_PRINT_EXEC_TIME() { \
-        UNITY_UINT execTimeMs = ((Unity.CurrentTestStopTime.tv_sec - Unity.CurrentTestStartTime.tv_sec) * 1000L); \
-        execTimeMs += ((Unity.CurrentTestStopTime.tv_nsec - Unity.CurrentTestStartTime.tv_nsec) / 1000000L); \
-        UnityPrint(" ("); \
-        UnityPrintNumberUnsigned(execTimeMs); \
-        UnityPrint(" ms)"); \
-        }
-    #endif
-  #endif
-#endif
-
-#ifndef UNITY_EXEC_TIME_START
-#define UNITY_EXEC_TIME_START() do{}while(0)
-#endif
-
-#ifndef UNITY_EXEC_TIME_STOP
-#define UNITY_EXEC_TIME_STOP() do{}while(0)
-#endif
-
-#ifndef UNITY_TIME_TYPE
-#define UNITY_TIME_TYPE UNITY_UINT
-#endif
-
-#ifndef UNITY_PRINT_EXEC_TIME
-#define UNITY_PRINT_EXEC_TIME() do{}while(0)
-#endif
-
-/*-------------------------------------------------------
- * Footprint
- *-------------------------------------------------------*/
-
-#ifndef UNITY_LINE_TYPE
-#define UNITY_LINE_TYPE UNITY_UINT
-#endif
-
-#ifndef UNITY_COUNTER_TYPE
-#define UNITY_COUNTER_TYPE UNITY_UINT
-#endif
-
-/*-------------------------------------------------------
- * Internal Structs Needed
- *-------------------------------------------------------*/
-
-typedef void (*UnityTestFunction)(void);
-
-#define UNITY_DISPLAY_RANGE_INT  (0x10)
-#define UNITY_DISPLAY_RANGE_UINT (0x20)
-#define UNITY_DISPLAY_RANGE_HEX  (0x40)
-#define UNITY_DISPLAY_RANGE_CHAR (0x80)
-
-typedef enum
-{
-    UNITY_DISPLAY_STYLE_INT      = (UNITY_INT_WIDTH / 8) + UNITY_DISPLAY_RANGE_INT,
-    UNITY_DISPLAY_STYLE_INT8     = 1 + UNITY_DISPLAY_RANGE_INT,
-    UNITY_DISPLAY_STYLE_INT16    = 2 + UNITY_DISPLAY_RANGE_INT,
-    UNITY_DISPLAY_STYLE_INT32    = 4 + UNITY_DISPLAY_RANGE_INT,
-#ifdef UNITY_SUPPORT_64
-    UNITY_DISPLAY_STYLE_INT64    = 8 + UNITY_DISPLAY_RANGE_INT,
-#endif
-
-    UNITY_DISPLAY_STYLE_UINT     = (UNITY_INT_WIDTH / 8) + UNITY_DISPLAY_RANGE_UINT,
-    UNITY_DISPLAY_STYLE_UINT8    = 1 + UNITY_DISPLAY_RANGE_UINT,
-    UNITY_DISPLAY_STYLE_UINT16   = 2 + UNITY_DISPLAY_RANGE_UINT,
-    UNITY_DISPLAY_STYLE_UINT32   = 4 + UNITY_DISPLAY_RANGE_UINT,
-#ifdef UNITY_SUPPORT_64
-    UNITY_DISPLAY_STYLE_UINT64   = 8 + UNITY_DISPLAY_RANGE_UINT,
-#endif
-
-    UNITY_DISPLAY_STYLE_HEX8     = 1 + UNITY_DISPLAY_RANGE_HEX,
-    UNITY_DISPLAY_STYLE_HEX16    = 2 + UNITY_DISPLAY_RANGE_HEX,
-    UNITY_DISPLAY_STYLE_HEX32    = 4 + UNITY_DISPLAY_RANGE_HEX,
-#ifdef UNITY_SUPPORT_64
-    UNITY_DISPLAY_STYLE_HEX64    = 8 + UNITY_DISPLAY_RANGE_HEX,
-#endif
-
-    UNITY_DISPLAY_STYLE_CHAR     = 1 + UNITY_DISPLAY_RANGE_CHAR + UNITY_DISPLAY_RANGE_INT,
-
-    UNITY_DISPLAY_STYLE_UNKNOWN
-} UNITY_DISPLAY_STYLE_T;
-
-typedef enum
-{
-    UNITY_WITHIN           = 0x0,
-    UNITY_EQUAL_TO         = 0x1,
-    UNITY_GREATER_THAN     = 0x2,
-    UNITY_GREATER_OR_EQUAL = 0x2 + UNITY_EQUAL_TO,
-    UNITY_SMALLER_THAN     = 0x4,
-    UNITY_SMALLER_OR_EQUAL = 0x4 + UNITY_EQUAL_TO,
-    UNITY_UNKNOWN
-} UNITY_COMPARISON_T;
-
-#ifndef UNITY_EXCLUDE_FLOAT
-typedef enum UNITY_FLOAT_TRAIT
-{
-    UNITY_FLOAT_IS_NOT_INF       = 0,
-    UNITY_FLOAT_IS_INF,
-    UNITY_FLOAT_IS_NOT_NEG_INF,
-    UNITY_FLOAT_IS_NEG_INF,
-    UNITY_FLOAT_IS_NOT_NAN,
-    UNITY_FLOAT_IS_NAN,
-    UNITY_FLOAT_IS_NOT_DET,
-    UNITY_FLOAT_IS_DET,
-    UNITY_FLOAT_INVALID_TRAIT
-} UNITY_FLOAT_TRAIT_T;
-#endif
-
-typedef enum
-{
-    UNITY_ARRAY_TO_VAL = 0,
-    UNITY_ARRAY_TO_ARRAY,
-    UNITY_ARRAY_UNKNOWN
-} UNITY_FLAGS_T;
-
-struct UNITY_STORAGE_T
-{
-    const char* TestFile;
-    const char* CurrentTestName;
-#ifndef UNITY_EXCLUDE_DETAILS
-    const char* CurrentDetail1;
-    const char* CurrentDetail2;
-#endif
-    UNITY_LINE_TYPE CurrentTestLineNumber;
-    UNITY_COUNTER_TYPE NumberOfTests;
-    UNITY_COUNTER_TYPE TestFailures;
-    UNITY_COUNTER_TYPE TestIgnores;
-    UNITY_COUNTER_TYPE CurrentTestFailed;
-    UNITY_COUNTER_TYPE CurrentTestIgnored;
-#ifdef UNITY_INCLUDE_EXEC_TIME
-    UNITY_TIME_TYPE CurrentTestStartTime;
-    UNITY_TIME_TYPE CurrentTestStopTime;
-#endif
-#ifndef UNITY_EXCLUDE_SETJMP_H
-    jmp_buf AbortFrame;
-#endif
-};
-
-extern struct UNITY_STORAGE_T Unity;
-
-/*-------------------------------------------------------
- * Test Suite Management
- *-------------------------------------------------------*/
-
-void UnityBegin(const char* filename);
-int  UnityEnd(void);
-void UnitySetTestFile(const char* filename);
-void UnityConcludeTest(void);
-void UnityDefaultTestRun(UnityTestFunction Func, const char* FuncName, const int FuncLineNum);
-
-/*-------------------------------------------------------
- * Details Support
- *-------------------------------------------------------*/
-
-#ifdef UNITY_EXCLUDE_DETAILS
-#define UNITY_CLR_DETAILS()
-#define UNITY_SET_DETAIL(d1)
-#define UNITY_SET_DETAILS(d1,d2)
-#else
-#define UNITY_CLR_DETAILS()      { Unity.CurrentDetail1 = 0;   Unity.CurrentDetail2 = 0;  }
-#define UNITY_SET_DETAIL(d1)     { Unity.CurrentDetail1 = (d1);  Unity.CurrentDetail2 = 0;  }
-#define UNITY_SET_DETAILS(d1,d2) { Unity.CurrentDetail1 = (d1);  Unity.CurrentDetail2 = (d2); }
-
-#ifndef UNITY_DETAIL1_NAME
-#define UNITY_DETAIL1_NAME "Function"
-#endif
-
-#ifndef UNITY_DETAIL2_NAME
-#define UNITY_DETAIL2_NAME "Argument"
-#endif
-#endif
-
-/*-------------------------------------------------------
- * Test Output
- *-------------------------------------------------------*/
-
-void UnityPrint(const char* string);
-
-#ifdef UNITY_INCLUDE_PRINT_FORMATTED
-void UnityPrintFormatted(const char* format, ...);
-#endif
-
-void UnityPrintLen(const char* string, const UNITY_UINT32 length);
-void UnityPrintMask(const UNITY_UINT mask, const UNITY_UINT number);
-void UnityPrintNumberByStyle(const UNITY_INT number, const UNITY_DISPLAY_STYLE_T style);
-void UnityPrintNumber(const UNITY_INT number_to_print);
-void UnityPrintNumberUnsigned(const UNITY_UINT number);
-void UnityPrintNumberHex(const UNITY_UINT number, const char nibbles_to_print);
-
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-void UnityPrintFloat(const UNITY_DOUBLE input_number);
-#endif
-
-/*-------------------------------------------------------
- * Test Assertion Functions
- *-------------------------------------------------------
- *  Use the macros below this section instead of calling
- *  these directly. The macros have a consistent naming
- *  convention and will pull in file and line information
- *  for you. */
-
-void UnityAssertEqualNumber(const UNITY_INT expected,
-                            const UNITY_INT actual,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber,
-                            const UNITY_DISPLAY_STYLE_T style);
-
-void UnityAssertGreaterOrLessOrEqualNumber(const UNITY_INT threshold,
-                                           const UNITY_INT actual,
-                                           const UNITY_COMPARISON_T compare,
-                                           const char *msg,
-                                           const UNITY_LINE_TYPE lineNumber,
-                                           const UNITY_DISPLAY_STYLE_T style);
-
-void UnityAssertEqualIntArray(UNITY_INTERNAL_PTR expected,
-                              UNITY_INTERNAL_PTR actual,
-                              const UNITY_UINT32 num_elements,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_DISPLAY_STYLE_T style,
-                              const UNITY_FLAGS_T flags);
-
-void UnityAssertBits(const UNITY_INT mask,
-                     const UNITY_INT expected,
-                     const UNITY_INT actual,
-                     const char* msg,
-                     const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualString(const char* expected,
-                            const char* actual,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualStringLen(const char* expected,
-                            const char* actual,
-                            const UNITY_UINT32 length,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualStringArray( UNITY_INTERNAL_PTR expected,
-                                  const char** actual,
-                                  const UNITY_UINT32 num_elements,
-                                  const char* msg,
-                                  const UNITY_LINE_TYPE lineNumber,
-                                  const UNITY_FLAGS_T flags);
-
-void UnityAssertEqualMemory( UNITY_INTERNAL_PTR expected,
-                             UNITY_INTERNAL_PTR actual,
-                             const UNITY_UINT32 length,
-                             const UNITY_UINT32 num_elements,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber,
-                             const UNITY_FLAGS_T flags);
-
-void UnityAssertNumbersWithin(const UNITY_UINT delta,
-                              const UNITY_INT expected,
-                              const UNITY_INT actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_DISPLAY_STYLE_T style);
-
-void UnityAssertNumbersArrayWithin(const UNITY_UINT delta,
-                                   UNITY_INTERNAL_PTR expected,
-                                   UNITY_INTERNAL_PTR actual,
-                                   const UNITY_UINT32 num_elements,
-                                   const char* msg,
-                                   const UNITY_LINE_TYPE lineNumber,
-                                   const UNITY_DISPLAY_STYLE_T style,
-                                   const UNITY_FLAGS_T flags);
-
-void UnityFail(const char* message, const UNITY_LINE_TYPE line);
-void UnityIgnore(const char* message, const UNITY_LINE_TYPE line);
-void UnityMessage(const char* message, const UNITY_LINE_TYPE line);
-
-#ifndef UNITY_EXCLUDE_FLOAT
-void UnityAssertFloatsWithin(const UNITY_FLOAT delta,
-                             const UNITY_FLOAT expected,
-                             const UNITY_FLOAT actual,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualFloatArray(UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* expected,
-                                UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* actual,
-                                const UNITY_UINT32 num_elements,
-                                const char* msg,
-                                const UNITY_LINE_TYPE lineNumber,
-                                const UNITY_FLAGS_T flags);
-
-void UnityAssertFloatSpecial(const UNITY_FLOAT actual,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber,
-                             const UNITY_FLOAT_TRAIT_T style);
-#endif
-
-#ifndef UNITY_EXCLUDE_DOUBLE
-void UnityAssertDoublesWithin(const UNITY_DOUBLE delta,
-                              const UNITY_DOUBLE expected,
-                              const UNITY_DOUBLE actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualDoubleArray(UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* expected,
-                                 UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* actual,
-                                 const UNITY_UINT32 num_elements,
-                                 const char* msg,
-                                 const UNITY_LINE_TYPE lineNumber,
-                                 const UNITY_FLAGS_T flags);
-
-void UnityAssertDoubleSpecial(const UNITY_DOUBLE actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_FLOAT_TRAIT_T style);
-#endif
-
-/*-------------------------------------------------------
- * Helpers
- *-------------------------------------------------------*/
-
-UNITY_INTERNAL_PTR UnityNumToPtr(const UNITY_INT num, const UNITY_UINT8 size);
-#ifndef UNITY_EXCLUDE_FLOAT
-UNITY_INTERNAL_PTR UnityFloatToPtr(const float num);
-#endif
-#ifndef UNITY_EXCLUDE_DOUBLE
-UNITY_INTERNAL_PTR UnityDoubleToPtr(const double num);
-#endif
-
-/*-------------------------------------------------------
- * Error Strings We Might Need
- *-------------------------------------------------------*/
-
-extern const char UnityStrOk[];
-extern const char UnityStrPass[];
-extern const char UnityStrFail[];
-extern const char UnityStrIgnore[];
-
-extern const char UnityStrErrFloat[];
-extern const char UnityStrErrDouble[];
-extern const char UnityStrErr64[];
-extern const char UnityStrErrShorthand[];
-
-/*-------------------------------------------------------
- * Test Running Macros
- *-------------------------------------------------------*/
-
-#ifndef UNITY_EXCLUDE_SETJMP_H
-#define TEST_PROTECT() (setjmp(Unity.AbortFrame) == 0)
-#define TEST_ABORT() longjmp(Unity.AbortFrame, 1)
-#else
-#define TEST_PROTECT() 1
-#define TEST_ABORT() return
-#endif
-
-/* This tricky series of macros gives us an optional line argument to treat it as RUN_TEST(func, num=__LINE__) */
-#ifndef RUN_TEST
-#ifdef __STDC_VERSION__
-#if __STDC_VERSION__ >= 199901L
-#define UNITY_SUPPORT_VARIADIC_MACROS
-#endif
-#endif
-#ifdef UNITY_SUPPORT_VARIADIC_MACROS
-#define RUN_TEST(...) UnityDefaultTestRun(RUN_TEST_FIRST(__VA_ARGS__), RUN_TEST_SECOND(__VA_ARGS__))
-#define RUN_TEST_FIRST(...) RUN_TEST_FIRST_HELPER(__VA_ARGS__, throwaway)
-#define RUN_TEST_FIRST_HELPER(first, ...) (first), #first
-#define RUN_TEST_SECOND(...) RUN_TEST_SECOND_HELPER(__VA_ARGS__, __LINE__, throwaway)
-#define RUN_TEST_SECOND_HELPER(first, second, ...) (second)
-#endif
-#endif
-
-/* If we can't do the tricky version, we'll just have to require them to always include the line number */
-#ifndef RUN_TEST
-#ifdef CMOCK
-#define RUN_TEST(func, num) UnityDefaultTestRun(func, #func, num)
-#else
-#define RUN_TEST(func) UnityDefaultTestRun(func, #func, __LINE__)
-#endif
-#endif
-
-#define TEST_LINE_NUM (Unity.CurrentTestLineNumber)
-#define TEST_IS_IGNORED (Unity.CurrentTestIgnored)
-#define UNITY_NEW_TEST(a) \
-    Unity.CurrentTestName = (a); \
-    Unity.CurrentTestLineNumber = (UNITY_LINE_TYPE)(__LINE__); \
-    Unity.NumberOfTests++;
-
-#ifndef UNITY_BEGIN
-#define UNITY_BEGIN() UnityBegin(__FILE__)
-#endif
-
-#ifndef UNITY_END
-#define UNITY_END() UnityEnd()
-#endif
-
-#ifndef UNITY_SHORTHAND_AS_INT
-#ifndef UNITY_SHORTHAND_AS_MEM
-#ifndef UNITY_SHORTHAND_AS_NONE
-#ifndef UNITY_SHORTHAND_AS_RAW
-#define UNITY_SHORTHAND_AS_OLD
-#endif
-#endif
-#endif
-#endif
-
-/*-----------------------------------------------
- * Command Line Argument Support
- *-----------------------------------------------*/
-
-#ifdef UNITY_USE_COMMAND_LINE_ARGS
-int UnityParseOptions(int argc, char** argv);
-int UnityTestMatches(void);
-#endif
-
-/*-------------------------------------------------------
- * Basic Fail and Ignore
- *-------------------------------------------------------*/
-
-#define UNITY_TEST_FAIL(line, message)   UnityFail(   (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_IGNORE(line, message) UnityIgnore( (message), (UNITY_LINE_TYPE)(line))
-
-/*-------------------------------------------------------
- * Test Asserts
- *-------------------------------------------------------*/
-
-#define UNITY_TEST_ASSERT(condition, line, message)                                              if (condition) {} else {UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), (message));}
-#define UNITY_TEST_ASSERT_NULL(pointer, line, message)                                           UNITY_TEST_ASSERT(((pointer) == NULL),  (UNITY_LINE_TYPE)(line), (message))
-#define UNITY_TEST_ASSERT_NOT_NULL(pointer, line, message)                                       UNITY_TEST_ASSERT(((pointer) != NULL),  (UNITY_LINE_TYPE)(line), (message))
-
-#define UNITY_TEST_ASSERT_EQUAL_INT(expected, actual, line, message)                             UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_EQUAL_INT8(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_EQUAL_INT16(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT16)(expected), (UNITY_INT)(UNITY_INT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_EQUAL_INT32(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT32)(expected), (UNITY_INT)(UNITY_INT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_EQUAL_UINT(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_EQUAL_UINT8(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_UINT8 )(expected), (UNITY_INT)(UNITY_UINT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_EQUAL_UINT16(expected, actual, line, message)                          UnityAssertEqualNumber((UNITY_INT)(UNITY_UINT16)(expected), (UNITY_INT)(UNITY_UINT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_EQUAL_UINT32(expected, actual, line, message)                          UnityAssertEqualNumber((UNITY_INT)(UNITY_UINT32)(expected), (UNITY_INT)(UNITY_UINT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_EQUAL_HEX8(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_EQUAL_HEX16(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT16)(expected), (UNITY_INT)(UNITY_INT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_EQUAL_HEX32(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT32)(expected), (UNITY_INT)(UNITY_INT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-#define UNITY_TEST_ASSERT_EQUAL_CHAR(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR)
-#define UNITY_TEST_ASSERT_BITS(mask, expected, actual, line, message)                            UnityAssertBits((UNITY_INT)(mask), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line))
-
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT8(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT16(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT32(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-#define UNITY_TEST_ASSERT_GREATER_THAN_CHAR(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR)
-
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT8(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT16(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT32(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_CHAR(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR)
-
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT(threshold, actual, line, message)                 UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)              (threshold), (UNITY_INT)              (actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 ) (threshold), (UNITY_INT)(UNITY_INT8 ) (actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16) (threshold), (UNITY_INT)(UNITY_INT16) (actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32) (threshold), (UNITY_INT)(UNITY_INT32) (actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)              (threshold), (UNITY_INT)              (actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT8(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT16(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT32(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_CHAR(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 ) (threshold), (UNITY_INT)(UNITY_INT8 ) (actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR)
-
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT(threshold, actual, line, message)                 UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)             (threshold),  (UNITY_INT)              (actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold),  (UNITY_INT)(UNITY_INT8 ) (actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold),  (UNITY_INT)(UNITY_INT16) (actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold),  (UNITY_INT)(UNITY_INT32) (actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)             (threshold),  (UNITY_INT)              (actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT8(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT16(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT32(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_CHAR(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold),  (UNITY_INT)(UNITY_INT8 ) (actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR)
-
-#define UNITY_TEST_ASSERT_INT_WITHIN(delta, expected, actual, line, message)                     UnityAssertNumbersWithin(              (delta), (UNITY_INT)                          (expected), (UNITY_INT)                          (actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_INT8_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_INT8 )             (expected), (UNITY_INT)(UNITY_INT8 )             (actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_INT16_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT16)(delta), (UNITY_INT)(UNITY_INT16)             (expected), (UNITY_INT)(UNITY_INT16)             (actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_INT32_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT32)(delta), (UNITY_INT)(UNITY_INT32)             (expected), (UNITY_INT)(UNITY_INT32)             (actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_UINT_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin(              (delta), (UNITY_INT)                          (expected), (UNITY_INT)                          (actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_UINT8_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_UINT16_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((UNITY_UINT16)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_UINT32_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((UNITY_UINT32)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_HEX8_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_HEX16_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT16)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_HEX32_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT32)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-#define UNITY_TEST_ASSERT_CHAR_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_INT8 )             (expected), (UNITY_INT)(UNITY_INT8 )             (actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR)
-
-#define UNITY_TEST_ASSERT_INT_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)     UnityAssertNumbersArrayWithin(              (delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_INT8_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)    UnityAssertNumbersArrayWithin((UNITY_UINT8 )(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_INT16_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UnityAssertNumbersArrayWithin((UNITY_UINT16)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_INT32_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UnityAssertNumbersArrayWithin((UNITY_UINT32)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_UINT_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)    UnityAssertNumbersArrayWithin(              (delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_UINT8_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)  UnityAssertNumbersArrayWithin( (UNITY_UINT16)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_UINT16_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)  UnityAssertNumbersArrayWithin((UNITY_UINT16)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_UINT32_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)  UnityAssertNumbersArrayWithin((UNITY_UINT32)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_HEX8_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)    UnityAssertNumbersArrayWithin((UNITY_UINT8 )(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_HEX16_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UnityAssertNumbersArrayWithin((UNITY_UINT16)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_HEX32_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UnityAssertNumbersArrayWithin((UNITY_UINT32)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_CHAR_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)    UnityAssertNumbersArrayWithin((UNITY_UINT8 )(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR, UNITY_ARRAY_TO_ARRAY)
-
-
-#define UNITY_TEST_ASSERT_EQUAL_PTR(expected, actual, line, message)                             UnityAssertEqualNumber((UNITY_PTR_TO_INT)(expected), (UNITY_PTR_TO_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_POINTER)
-#define UNITY_TEST_ASSERT_EQUAL_STRING(expected, actual, line, message)                          UnityAssertEqualString((const char*)(expected), (const char*)(actual), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_STRING_LEN(expected, actual, len, line, message)                 UnityAssertEqualStringLen((const char*)(expected), (const char*)(actual), (UNITY_UINT32)(len), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_MEMORY(expected, actual, len, line, message)                     UnityAssertEqualMemory((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(len), 1, (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-
-#define UNITY_TEST_ASSERT_EQUAL_INT_ARRAY(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT,     UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_INT8_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8,    UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_INT16_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_INT32_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT,    UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT8_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT16_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT32_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX8_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8,    UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX16_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_PTR_ARRAY(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_POINTER, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_STRING_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualStringArray((UNITY_INTERNAL_PTR)(expected), (const char**)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY(expected, actual, len, num_elements, line, message) UnityAssertEqualMemory((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(len), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_CHAR_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR,    UNITY_ARRAY_TO_ARRAY)
-
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT(expected, actual, num_elements, line, message)          UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)              (expected), (UNITY_INT_WIDTH / 8)),          (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT,     UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT8(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT8  )(expected), 1),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8,    UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT16(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT16 )(expected), 2),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT32(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT32 )(expected), 4),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)              (expected), (UNITY_INT_WIDTH / 8)),          (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT,    UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT8(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT8 )(expected), 1),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT16(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT16)(expected), 2),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT32(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT32)(expected), 4),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX8(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT8  )(expected), 1),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8,    UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX16(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT16 )(expected), 2),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX32(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT32 )(expected), 4),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_PTR(expected, actual, num_elements, line, message)          UnityAssertEqualIntArray(UnityNumToPtr((UNITY_PTR_TO_INT)       (expected), (UNITY_POINTER_WIDTH / 8)),      (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_POINTER, UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_STRING(expected, actual, num_elements, line, message)       UnityAssertEqualStringArray((UNITY_INTERNAL_PTR)(expected), (const char**)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_MEMORY(expected, actual, len, num_elements, line, message)  UnityAssertEqualMemory((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(len), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_CHAR(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT8  )(expected), 1),                              (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR,    UNITY_ARRAY_TO_VAL)
-
-#ifdef UNITY_SUPPORT_64
-#define UNITY_TEST_ASSERT_EQUAL_INT64(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64(expected, actual, line, message)                          UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT64(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT64)(expected), 8), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT64(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT64)(expected), 8), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64, UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX64(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT64)(expected), 8), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_INT64_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_UINT64_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_HEX64_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT64(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_INT64_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UnityAssertNumbersArrayWithin((UNITY_UINT64)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_UINT64_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)  UnityAssertNumbersArrayWithin((UNITY_UINT64)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_HEX64_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UnityAssertNumbersArrayWithin((UNITY_UINT64)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64, UNITY_ARRAY_TO_ARRAY)
-#else
-#define UNITY_TEST_ASSERT_EQUAL_INT64(expected, actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64(expected, actual, line, message)                          UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64(expected, actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY(expected, actual, num_elements, line, message)      UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_INT64_WITHIN(delta, expected, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_UINT64_WITHIN(delta, expected, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_HEX64_WITHIN(delta, expected, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64(threshold, actual, line, message)              UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT64(threshold, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64(threshold, actual, line, message)              UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_INT64_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_UINT64_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_HEX64_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#endif
-
-#ifdef UNITY_EXCLUDE_FLOAT
-#define UNITY_TEST_ASSERT_FLOAT_WITHIN(delta, expected, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT(expected, actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT(expected, actual, num_elements, line, message)        UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_INF(actual, line, message)                                    UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF(actual, line, message)                                UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NAN(actual, line, message)                                    UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE(actual, line, message)                            UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF(actual, line, message)                                UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF(actual, line, message)                            UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN(actual, line, message)                                UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE(actual, line, message)                        UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#else
-#define UNITY_TEST_ASSERT_FLOAT_WITHIN(delta, expected, actual, line, message)                   UnityAssertFloatsWithin((UNITY_FLOAT)(delta), (UNITY_FLOAT)(expected), (UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT(expected, actual, line, message)                           UNITY_TEST_ASSERT_FLOAT_WITHIN((UNITY_FLOAT)(expected) * (UNITY_FLOAT)UNITY_FLOAT_PRECISION, (UNITY_FLOAT)(expected), (UNITY_FLOAT)(actual), (UNITY_LINE_TYPE)(line), (message))
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualFloatArray((UNITY_FLOAT*)(expected), (UNITY_FLOAT*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT(expected, actual, num_elements, line, message)        UnityAssertEqualFloatArray(UnityFloatToPtr(expected), (UNITY_FLOAT*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_FLOAT_IS_INF(actual, line, message)                                    UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF(actual, line, message)                                UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NEG_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NAN(actual, line, message)                                    UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NAN)
-#define UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE(actual, line, message)                            UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_DET)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF(actual, line, message)                                UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF(actual, line, message)                            UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NEG_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN(actual, line, message)                                UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NAN)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE(actual, line, message)                        UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_DET)
-#endif
-
-#ifdef UNITY_EXCLUDE_DOUBLE
-#define UNITY_TEST_ASSERT_DOUBLE_WITHIN(delta, expected, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE(expected, actual, line, message)                          UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY(expected, actual, num_elements, line, message)      UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_INF(actual, line, message)                                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF(actual, line, message)                               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NAN(actual, line, message)                                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE(actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF(actual, line, message)                               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF(actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN(actual, line, message)                               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual, line, message)                       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#else
-#define UNITY_TEST_ASSERT_DOUBLE_WITHIN(delta, expected, actual, line, message)                  UnityAssertDoublesWithin((UNITY_DOUBLE)(delta), (UNITY_DOUBLE)(expected), (UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE(expected, actual, line, message)                          UNITY_TEST_ASSERT_DOUBLE_WITHIN((UNITY_DOUBLE)(expected) * (UNITY_DOUBLE)UNITY_DOUBLE_PRECISION, (UNITY_DOUBLE)(expected), (UNITY_DOUBLE)(actual), (UNITY_LINE_TYPE)(line), (message))
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualDoubleArray((UNITY_DOUBLE*)(expected), (UNITY_DOUBLE*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE(expected, actual, num_elements, line, message)       UnityAssertEqualDoubleArray(UnityDoubleToPtr(expected), (UNITY_DOUBLE*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_INF(actual, line, message)                                   UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF(actual, line, message)                               UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NEG_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NAN(actual, line, message)                                   UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NAN)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE(actual, line, message)                           UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_DET)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF(actual, line, message)                               UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF(actual, line, message)                           UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NEG_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN(actual, line, message)                               UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NAN)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual, line, message)                       UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_DET)
-#endif
-
-/* End of UNITY_INTERNALS_H */
-#endif
diff --git a/tools/build.py b/tools/build.py
new file mode 100755
index 000000000..633d2b582
--- /dev/null
+++ b/tools/build.py
@@ -0,0 +1,268 @@
+#!/usr/bin/env python3
+import argparse
+import random
+import os
+import sys
+import time
+import subprocess
+from pathlib import Path
+from multiprocessing import Pool
+
+import build_utils
+
+STATUS_OK = "\033[32mOK\033[0m"
+STATUS_FAILED = "\033[31mFailed\033[0m"
+STATUS_SKIPPED = "\033[33mSkipped\033[0m"
+
+RET_OK = 0
+RET_FAILED = 1
+RET_SKIPPED = 2
+
+build_format = '| {:30} | {:40} | {:16} | {:5} |'
+build_separator = '-' * 95
+build_status = [STATUS_OK, STATUS_FAILED, STATUS_SKIPPED]
+
+verbose = False
+
+# -----------------------------
+# Helper
+# -----------------------------
+def run_cmd(cmd):
+    #print(cmd)
+    r = subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    title = f'Command Error: {cmd}'
+    if r.returncode != 0:
+        # print build output if failed
+        if os.getenv('GITHUB_ACTIONS'):
+            print(f"::group::{title}")
+            print(r.stdout.decode("utf-8"))
+            print(f"::endgroup::")
+        else:
+            print(title)
+            print(r.stdout.decode("utf-8"))
+    elif verbose:
+        print(cmd)
+        print(r.stdout.decode("utf-8"))
+    return r
+
+
+def find_family(board):
+    bsp_dir = Path("hw/bsp")
+    for family_dir in bsp_dir.iterdir():
+        if family_dir.is_dir():
+            board_dir = family_dir / 'boards' / board
+            if board_dir.exists():
+                return family_dir.name
+    return None
+
+
+def get_examples(family):
+    all_examples = []
+    for d in os.scandir("examples"):
+        if d.is_dir() and 'cmake' not in d.name and 'build_system' not in d.name:
+            for entry in os.scandir(d.path):
+                if entry.is_dir() and 'cmake' not in entry.name:
+                    if family != 'espressif' or 'freertos' in entry.name:
+                        all_examples.append(d.name + '/' + entry.name)
+
+    if family == 'espressif':
+        all_examples.append('device/board_test')
+        all_examples.append('device/video_capture')
+        all_examples.append('host/device_info')
+    all_examples.sort()
+    return all_examples
+
+
+def print_build_result(board, example, status, duration):
+    if isinstance(duration, (int, float)):
+        duration = "{:.2f}s".format(duration)
+    print(build_format.format(board, example, build_status[status], duration))
+
+# -----------------------------
+# CMake
+# -----------------------------
+def cmake_board(board, toolchain, build_flags_on):
+    ret = [0, 0, 0]
+    start_time = time.monotonic()
+
+    build_dir = f'cmake-build/cmake-build-{board}'
+    build_flags = ''
+    if len(build_flags_on) > 0:
+        build_flags =  ' '.join(f'-D{flag}=1' for flag in build_flags_on)
+        build_flags = f'-DCFLAGS_CLI="{build_flags}"'
+        build_dir += '-f1_' + '_'.join(build_flags_on)
+
+    family = find_family(board)
+    if family == 'espressif':
+        # for espressif, we have to build example individually
+        all_examples = get_examples(family)
+        for example in all_examples:
+            if build_utils.skip_example(example, board):
+                ret[2] += 1
+            else:
+                rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" '
+                               f'-DBOARD={board} {build_flags}')
+                if rcmd.returncode == 0:
+                    rcmd = run_cmd(f'cmake --build {build_dir}/{example}')
+                ret[0 if rcmd.returncode == 0 else 1] += 1
+    else:
+        rcmd = run_cmd(f'cmake examples -B {build_dir} -G "Ninja" -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel '
+                       f'-DTOOLCHAIN={toolchain} {build_flags}')
+        if rcmd.returncode == 0:
+            cmd = f"cmake --build {build_dir}"
+            # circleci docker return $nproc as 36 core, limit parallel according to resource class. Required for IAR, also prevent crashed/killed by docker
+            if os.getenv('CIRCLECI'):
+                resource_class = { 'small': 1, 'medium': 2, 'medium+': 3, 'large': 4 }
+                for rc in resource_class:
+                    if rc in os.getenv('CIRCLE_JOB'):
+                        cmd += f' --parallel {resource_class[rc]}'
+                        break
+            rcmd = run_cmd(cmd)
+        ret[0 if rcmd.returncode == 0 else 1] += 1
+
+    example = 'all'
+    print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time)
+    return ret
+
+
+# -----------------------------
+# Make
+# -----------------------------
+def make_one_example(example, board, make_option):
+    # Check if board is skipped
+    if build_utils.skip_example(example, board):
+        print_build_result(board, example, 2, '-')
+        r = 2
+    else:
+        start_time = time.monotonic()
+        # skip -j for circleci
+        if not os.getenv('CIRCLECI'):
+            make_option += ' -j'
+        make_cmd = f"make -C examples/{example} BOARD={board} {make_option}"
+        # run_cmd(f"{make_cmd} clean")
+        build_result = run_cmd(f"{make_cmd} all")
+        r = 0 if build_result.returncode == 0 else 1
+        print_build_result(board, example, r, time.monotonic() - start_time)
+
+    ret = [0, 0, 0]
+    ret[r] = 1
+    return ret
+
+
+def make_board(board, toolchain):
+    print(build_separator)
+    all_examples = get_examples(find_family(board))
+    start_time = time.monotonic()
+    ret = [0, 0, 0]
+    with Pool(processes=os.cpu_count()) as pool:
+        pool_args = list((map(lambda e, b=board, o=f"TOOLCHAIN={toolchain}": [e, b, o], all_examples)))
+        r = pool.starmap(make_one_example, pool_args)
+        # sum all element of same index (column sum)
+        ret = list(map(sum, list(zip(*r))))
+    example = 'all'
+    print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time)
+    return ret
+
+
+# -----------------------------
+# Build Family
+# -----------------------------
+def build_boards_list(boards, toolchain, build_system, build_flags_on):
+    ret = [0, 0, 0]
+    for b in boards:
+        r = [0, 0, 0]
+        if build_system == 'cmake':
+            r = cmake_board(b, toolchain, build_flags_on)
+        elif build_system == 'make':
+            r = make_board(b, toolchain)
+        ret[0] += r[0]
+        ret[1] += r[1]
+        ret[2] += r[2]
+    return ret
+
+
+def build_family(family, toolchain, build_system, build_flags_on, one_per_family, boards):
+    all_boards = []
+    for entry in os.scandir(f"hw/bsp/{family}/boards"):
+        if entry.is_dir() and entry.name != 'pico_sdk':
+            all_boards.append(entry.name)
+    all_boards.sort()
+
+    ret = [0, 0, 0]
+    # If only-one flag is set, select one random board
+    if one_per_family:
+        for b in boards:
+            # skip if -b already specify one in this family
+            if find_family(b) == family:
+                return ret
+        all_boards = [random.choice(all_boards)]
+
+    ret = build_boards_list(all_boards, toolchain, build_system, build_flags_on)
+    return ret
+
+
+# -----------------------------
+# Main
+# -----------------------------
+def main():
+    global verbose
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument('families', nargs='*', default=[], help='Families to build')
+    parser.add_argument('-b', '--board', action='append', default=[], help='Boards to build')
+    parser.add_argument('-t', '--toolchain', default='gcc', help='Toolchain to use, default is gcc')
+    parser.add_argument('-s', '--build-system', default='cmake', help='Build system to use, default is cmake')
+    parser.add_argument('-f1', '--build-flags-on', action='append', default=[], help='Build flag to pass to build system')
+    parser.add_argument('-1', '--one-per-family', action='store_true', default=False, help='Build only one random board inside a family')
+    parser.add_argument('-v', '--verbose', action='store_true', help='Verbose output')
+    args = parser.parse_args()
+
+    families = args.families
+    boards = args.board
+    toolchain = args.toolchain
+    build_system = args.build_system
+    build_flags_on = args.build_flags_on
+    one_per_family = args.one_per_family
+    verbose = args.verbose
+
+    if len(families) == 0 and len(boards) == 0:
+        print("Please specify families or board to build")
+        return 1
+
+    print(build_separator)
+    print(build_format.format('Board', 'Example', '\033[39mResult\033[0m', 'Time'))
+    total_time = time.monotonic()
+    result = [0, 0, 0]
+
+    # build families
+    all_families = []
+    if 'all' in families:
+        for entry in os.scandir("hw/bsp"):
+            if entry.is_dir() and entry.name != 'espressif' and os.path.isfile(entry.path + "/family.cmake"):
+                all_families.append(entry.name)
+    else:
+        all_families = list(families)
+    all_families.sort()
+
+    # succeeded, failed, skipped
+    for f in all_families:
+        r = build_family(f, toolchain, build_system, build_flags_on, one_per_family, boards)
+        result[0] += r[0]
+        result[1] += r[1]
+        result[2] += r[2]
+
+    # build boards
+    r = build_boards_list(boards, toolchain, build_system, build_flags_on)
+    result[0] += r[0]
+    result[1] += r[1]
+    result[2] += r[2]
+
+    total_time = time.monotonic() - total_time
+    print(build_separator)
+    print(f"Build Summary: {result[0]} {STATUS_OK}, {result[1]} {STATUS_FAILED} and took {total_time:.2f}s")
+    print(build_separator)
+    return result[1]
+
+
+if __name__ == '__main__':
+    sys.exit(main())
diff --git a/tools/build_board.py b/tools/build_board.py
deleted file mode 100644
index 8d10ef820..000000000
--- a/tools/build_board.py
+++ /dev/null
@@ -1,69 +0,0 @@
-import os
-import sys
-import time
-import subprocess
-from multiprocessing import Pool
-
-import build_utils
-
-SUCCEEDED = "\033[32msucceeded\033[0m"
-FAILED = "\033[31mfailed\033[0m"
-SKIPPED = "\033[33mskipped\033[0m"
-
-build_separator = '-' * 106
-
-
-def filter_with_input(mylist):
-    if len(sys.argv) > 1:
-        input_args = list(set(mylist).intersection(sys.argv))
-        if len(input_args) > 0:
-            mylist[:] = input_args
-
-
-if __name__ == '__main__':
-    # If examples are not specified in arguments, build all
-    all_examples = []
-    for dir1 in os.scandir("examples"):
-        if dir1.is_dir():
-            for entry in os.scandir(dir1.path):
-                if entry.is_dir():
-                    all_examples.append(dir1.name + '/' + entry.name)
-    filter_with_input(all_examples)
-    all_examples.sort()
-
-    # If boards are not specified in arguments, build all
-    all_boards = []
-    for entry in os.scandir("hw/bsp"):
-        if entry.is_dir() and os.path.exists(entry.path + "/board.mk"):
-            all_boards.append(entry.name)
-    filter_with_input(all_boards)
-    all_boards.sort()
-
-    # Get dependencies
-    for b in all_boards:
-        subprocess.run("make -C examples/device/board_test BOARD={} get-deps".format(b), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-
-    print(build_separator)
-    print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
-    total_time = time.monotonic()
-
-    # succeeded, failed, skipped
-    total_result = [0, 0, 0]
-    for example in all_examples:
-        print(build_separator)
-        with Pool(processes=os.cpu_count()) as pool:
-            pool_args = list((map(lambda b, e=example: [e, b], all_boards)))
-            result = pool.starmap(build_utils.build_example, pool_args)
-            # sum all element of same index (column sum)
-            result = list(map(sum, list(zip(*result))))
-            
-            # add to total result
-            total_result = list(map(lambda x, y: x + y, total_result, result))
-
-    total_time = time.monotonic() - total_time
-    print(build_separator)
-    print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1],
-                                                                       FAILED, total_result[2], SKIPPED, total_time))
-    print(build_separator)
-
-    sys.exit(total_result[1])
diff --git a/tools/build_esp32sx.py b/tools/build_esp32sx.py
deleted file mode 100644
index 2947a0a6b..000000000
--- a/tools/build_esp32sx.py
+++ /dev/null
@@ -1,101 +0,0 @@
-import os
-import glob
-import sys
-import subprocess
-import time
-
-import build_utils
-
-SUCCEEDED = "\033[32msucceeded\033[0m"
-FAILED = "\033[31mfailed\033[0m"
-SKIPPED = "\033[33mskipped\033[0m"
-
-success_count = 0
-fail_count = 0
-skip_count = 0
-exit_status = 0
-
-total_time = time.monotonic()
-
-build_format = '| {:23} | {:30} | {:18} | {:7} | {:6} | {:6} |'
-build_separator = '-' * 100
-
-def filter_with_input(mylist):
-    if len(sys.argv) > 1:
-        input_args = list(set(mylist).intersection(sys.argv))
-        if len(input_args) > 0:
-            mylist[:] = input_args
-
-# Build all examples if not specified
-all_examples = []
-for entry in os.scandir("examples/device"):
-    # Only includes example with CMakeLists.txt for esp32s, and skip board_test to speed up ci
-    if entry.is_dir() and os.path.exists(entry.path + "/sdkconfig.defaults") and entry.name != 'board_test':
-        all_examples.append(entry.name)
-filter_with_input(all_examples)
-all_examples.sort()
-
-# Build all boards if not specified
-all_boards = []
-for entry in os.scandir("hw/bsp/esp32s2/boards"):
-    if entry.is_dir():
-        all_boards.append(entry.name)
-for entry in os.scandir("hw/bsp/esp32s3/boards"):
-    if entry.is_dir():
-        all_boards.append(entry.name)
-filter_with_input(all_boards)
-all_boards.sort()
-
-def build_board(example, board):
-    global success_count, fail_count, skip_count, exit_status
-    start_time = time.monotonic()
-    flash_size = "-"
-    sram_size = "-"
-
-    # Check if board is skipped
-    if build_utils.skip_example(example, board):
-        success = SKIPPED
-        skip_count += 1
-        print(build_format.format(example, board, success, '-', flash_size, sram_size))
-    else:
-        subprocess.run("make -C examples/device/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        build_result = subprocess.run("make -j -C examples/device/{} BOARD={} all".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-
-        if build_result.returncode == 0:
-            success = SUCCEEDED
-            success_count += 1
-            (flash_size, sram_size) = build_size(example, board)
-        else:
-            exit_status = build_result.returncode
-            success = FAILED
-            fail_count += 1
-
-        build_duration = time.monotonic() - start_time
-        print(build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size))
-
-        if build_result.returncode != 0:
-            print(build_result.stdout.decode("utf-8"))
-
-def build_size(example, board):
-    #elf_file = 'examples/device/{}/_build/{}/{}-firmware.elf'.format(example, board, board)
-    elf_file = 'examples/device/{}/_build/{}/*.elf'.format(example, board)
-    size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8")
-    size_list = size_output.split('\n')[1].split('\t')
-    flash_size = int(size_list[0])
-    sram_size = int(size_list[1]) + int(size_list[2])
-    return (flash_size, sram_size)
-
-print(build_separator)
-print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
-print(build_separator)
-
-for example in all_examples:
-    for board in all_boards:
-        build_board(example, board)
-
-total_time = time.monotonic() - total_time
-print(build_separator)
-print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(success_count, SUCCEEDED, fail_count, FAILED, skip_count, SKIPPED, total_time))
-print(build_separator)
-
-sys.exit(exit_status)
diff --git a/tools/build_family.py b/tools/build_family.py
deleted file mode 100644
index c6c64d2b3..000000000
--- a/tools/build_family.py
+++ /dev/null
@@ -1,74 +0,0 @@
-import os
-import sys
-import time
-from multiprocessing import Pool
-
-import build_utils
-
-SUCCEEDED = "\033[32msucceeded\033[0m"
-FAILED = "\033[31mfailed\033[0m"
-SKIPPED = "\033[33mskipped\033[0m"
-
-build_separator = '-' * 106
-
-
-def filter_with_input(mylist):
-    if len(sys.argv) > 1:
-        input_args = list(set(mylist).intersection(sys.argv))
-        if len(input_args) > 0:
-            mylist[:] = input_args
-
-
-def build_family(example, family):
-    all_boards = []
-    for entry in os.scandir("hw/bsp/{}/boards".format(family)):
-        if entry.is_dir() and entry.name != 'pico_sdk':
-            all_boards.append(entry.name)
-    filter_with_input(all_boards)
-    all_boards.sort()
-
-    with Pool(processes=os.cpu_count()) as pool:
-        pool_args = list((map(lambda b, e=example: [e, b], all_boards)))
-        result = pool.starmap(build_utils.build_example, pool_args)
-        # sum all element of same index (column sum)
-        return list(map(sum, list(zip(*result))))
-
-
-if __name__ == '__main__':
-    # If examples are not specified in arguments, build all
-    all_examples = []
-    for dir1 in os.scandir("examples"):
-        if dir1.is_dir():
-            for entry in os.scandir(dir1.path):
-                if entry.is_dir():
-                    all_examples.append(dir1.name + '/' + entry.name)
-    filter_with_input(all_examples)
-    all_examples.sort()
-
-    # If family are not specified in arguments, build all
-    all_families = []
-    for entry in os.scandir("hw/bsp"):
-        if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name not in ("esp32s2", "esp32s3"):
-            all_families.append(entry.name)
-    filter_with_input(all_families)
-    all_families.sort()
-
-    print(build_separator)
-    print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
-    total_time = time.monotonic()
-
-    # succeeded, failed, skipped
-    total_result = [0, 0, 0]
-    for example in all_examples:
-        print(build_separator)
-        for family in all_families:
-            fret = build_family(example, family)
-            total_result = list(map(lambda x, y: x + y, total_result, fret))
-
-    total_time = time.monotonic() - total_time
-    print(build_separator)
-    print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1],
-                                                                       FAILED, total_result[2], SKIPPED, total_time))
-    print(build_separator)
-
-    sys.exit(total_result[1])
diff --git a/tools/build_utils.py b/tools/build_utils.py
old mode 100644
new mode 100755
index f457c7986..2998f940d
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -1,6 +1,7 @@
+#!/usr/bin/env python3
 import subprocess
 import pathlib
-import time
+import re
 
 build_format = '| {:29} | {:30} | {:18} | {:7} | {:6} | {:6} |'
 
@@ -13,110 +14,83 @@ def skip_example(example, board):
     ex_dir = pathlib.Path('examples/') / example
     bsp = pathlib.Path("hw/bsp")
 
-    if (bsp / board / "board.mk").exists():
-        # board without family
-        board_dir = bsp / board
-        family = ""
-        mk_contents = ""
-    else:
-        # board within family
-        board_dir = list(bsp.glob("*/boards/" + board))
-        if not board_dir:
-            # Skip unknown boards
-            return True
+    # board within family
+    board_dir = list(bsp.glob("*/boards/" + board))
+    if not board_dir:
+        # Skip unknown boards
+        return True
 
-        board_dir = list(board_dir)[0]
+    board_dir = list(board_dir)[0]
+    family_dir = board_dir.parent.parent
+    family = family_dir.name
 
-        family_dir = board_dir.parent.parent
-        family = family_dir.name
-
-        # family CMake
-        family_mk = family_dir / "family.cmake"
-
-        # family.mk
-        if not family_mk.exists():
-            family_mk = family_dir / "family.mk"
-
-        mk_contents = family_mk.read_text()
+    # family.mk
+    family_mk = family_dir / "family.mk"
+    mk_contents = family_mk.read_text()
 
     # Find the mcu, first in family mk then board mk
     if "CFG_TUSB_MCU=OPT_MCU_" not in mk_contents:
-        board_mk = board_dir / "board.cmake"
+        board_mk = board_dir / "board.mk"
         if not board_mk.exists():
-            board_mk = board_dir / "board.mk"
-
+            board_mk = board_dir / "board.cmake"
         mk_contents = board_mk.read_text()
 
-    for token in mk_contents.split():
-        if "CFG_TUSB_MCU=OPT_MCU_" in token:
-            # Strip " because cmake files has them.
-            token = token.strip("\"")
-            _, opt_mcu = token.split("=")
-            mcu = opt_mcu[len("OPT_MCU_"):]
+    mcu = "NONE"
+    if family == "espressif":
+        for line in mk_contents.splitlines():
+            match = re.search(r'set\(IDF_TARGET\s+"([^"]+)"\)', line)
+            if match:
+                mcu = match.group(1).upper()
+                break
+    else:
+        for token in mk_contents.split():
+            if "CFG_TUSB_MCU=OPT_MCU_" in token:
+                # Strip " because cmake files has them.
+                token = token.strip("\"")
+                _, opt_mcu = token.split("=")
+                mcu = opt_mcu[len("OPT_MCU_"):]
+            if mcu != "NONE":
+                break
 
     # Skip all OPT_MCU_NONE these are WIP port
     if mcu == "NONE":
         return True
 
+    max3421_enabled = False
+    for line in mk_contents.splitlines():
+        if "MAX3421_HOST=1" in line or 'MAX3421_HOST 1' in line:
+            max3421_enabled = True
+            break
+
     skip_file = ex_dir / "skip.txt"
     only_file = ex_dir / "only.txt"
 
-    if skip_file.exists() and only_file.exists():
-        raise RuntimeError("Only have a skip or only file. Not both.")
-    elif skip_file.exists():
+    if skip_file.exists():
         skips = skip_file.read_text().split()
-        return ("mcu:" + mcu in skips or
-                "board:" + board in skips or
-                "family:" + family in skips)
-    elif only_file.exists():
+        if ("mcu:" + mcu in skips or
+            "board:" + board in skips or
+            "family:" + family in skips):
+            return True
+
+    if only_file.exists():
         onlys = only_file.read_text().split()
-        return not ("mcu:" + mcu in onlys or
-                    "board:" + board in onlys or
-                    "family:" + family in onlys)
+        if not ("mcu:" + mcu in onlys or
+                ("mcu:MAX3421" in onlys and max3421_enabled) or
+                "board:" + board in onlys or
+                "family:" + family in onlys):
+            return True
 
     return False
 
 
-def build_example(example, board):
-    start_time = time.monotonic()
-    flash_size = "-"
-    sram_size = "-"
+def build_size(make_cmd):
+    size_output = subprocess.run(make_cmd + ' size', shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8").splitlines()
+    for i, l in enumerate(size_output):
+        text_title = 'text	   data	    bss	    dec'
+        if text_title in l:
+            size_list = size_output[i+1].split('\t')
+            flash_size = int(size_list[0])
+            sram_size = int(size_list[1]) + int(size_list[2])
+            return (flash_size, sram_size)
 
-    # succeeded, failed, skipped
-    ret = [0, 0, 0]
-
-    # Check if board is skipped
-    if skip_example(example, board):
-        status = SKIPPED
-        ret[2] = 1
-        print(build_format.format(example, board, status, '-', flash_size, sram_size))
-    else:
-        build_result = subprocess.run("make -j -C examples/{} BOARD={} all".format(example, board), shell=True,
-                                      stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-
-        if build_result.returncode == 0:
-            status = SUCCEEDED
-            ret[0] = 1
-            (flash_size, sram_size) = build_size(example, board)
-            subprocess.run("make -j -C examples/{} BOARD={} copy-artifact".format(example, board), shell=True,
-                           stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        else:
-            status = FAILED
-            ret[1] = 1
-
-        build_duration = time.monotonic() - start_time
-        print(build_format.format(example, board, status, "{:.2f}s".format(build_duration), flash_size, sram_size))
-
-        if build_result.returncode != 0:
-            print(build_result.stdout.decode("utf-8"))
-
-    return ret
-
-
-def build_size(example, board):
-    elf_file = 'examples/{}/_build/{}/*.elf'.format(example, board)
-    size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8")
-    size_list = size_output.split('\n')[1].split('\t')
-    flash_size = int(size_list[0])
-    sram_size = int(size_list[1]) + int(size_list[2])
-    return (flash_size, sram_size)
+    return (0, 0)
diff --git a/test/vendor/ceedling/plugins/bullseye/readme.txt b/tools/codespell/exclude-file.txt
similarity index 100%
rename from test/vendor/ceedling/plugins/bullseye/readme.txt
rename to tools/codespell/exclude-file.txt
diff --git a/tools/codespell/ignore-words.txt b/tools/codespell/ignore-words.txt
new file mode 100644
index 000000000..957cbd86b
--- /dev/null
+++ b/tools/codespell/ignore-words.txt
@@ -0,0 +1,14 @@
+synopsys
+sie
+tre
+thre
+hsi
+fro
+dout
+mot
+te
+attch
+endianess
+pris
+busses
+ser
diff --git a/tools/gen_doc.py b/tools/gen_doc.py
new file mode 100755
index 000000000..ab07bc116
--- /dev/null
+++ b/tools/gen_doc.py
@@ -0,0 +1,117 @@
+#!/usr/bin/env python3
+import re
+import pandas as pd
+from tabulate import tabulate
+from pathlib import Path
+from get_deps import deps_all
+
+# TOP is tinyusb root dir
+TOP = Path(__file__).parent.parent.resolve()
+
+
+# -----------------------------------------
+# Dependencies
+# -----------------------------------------
+def gen_deps_doc():
+    deps_rst = Path(TOP) / "docs/reference/dependencies.rst"
+    df = pd.DataFrame.from_dict(deps_all, orient='index', columns=['Repo', 'Commit', 'Required by'])
+    df = df[['Repo', 'Commit', 'Required by']].sort_index()
+    df = df.rename_axis("Local Path")
+
+    outstr = f"""\
+************
+Dependencies
+************
+
+MCU low-level peripheral driver and external libraries for building TinyUSB examples
+
+{tabulate(df, headers="keys", tablefmt='rst')}
+"""
+
+    with deps_rst.open('w') as f:
+        f.write(outstr)
+
+
+# -----------------------------------------
+# Dependencies
+# -----------------------------------------
+def extract_metadata(file_path):
+    metadata = {}
+    try:
+        with open(file_path, 'r') as file:
+            content = file.read()
+            # Match metadata block
+            match = re.search(r'/\*\s*metadata:(.*?)\*/', content, re.DOTALL)
+            if match:
+                block = match.group(1)
+                # Extract key-value pairs
+                for line in block.splitlines():
+                    key_value = re.match(r'\s*(\w+):\s*(.+)', line)
+                    if key_value:
+                        key, value = key_value.groups()
+                        metadata[key] = value.strip()
+    except FileNotFoundError:
+        pass
+    return metadata
+
+
+def gen_boards_doc():
+    # 'Manufacturer' : { 'Board' }
+    vendor_data = {}
+    # 'Board' : [ 'Name', 'Family', 'url', 'note' ]
+    all_boards = {}
+    #  extract metadata from family.c
+    for family_dir in sorted((Path(TOP) / "hw/bsp").iterdir()):
+        if family_dir.is_dir():
+            family_c = family_dir / "family.c"
+            if not family_c.exists():
+                family_c = family_dir / "boards/family.c"
+            f_meta = extract_metadata(family_c)
+            if not f_meta:
+                continue
+            manuf = f_meta.get('manufacturer', '')
+            if manuf not in vendor_data:
+                vendor_data[manuf] = {}
+            # extract metadata from board.h
+            for board_dir in sorted((family_dir / "boards").iterdir()):
+                if board_dir.is_dir():
+                    b_meta = extract_metadata(board_dir / "board.h")
+                    if not b_meta:
+                        continue
+                    b_entry = [
+                        b_meta.get('name', ''),
+                        family_dir.name,
+                        b_meta.get('url', ''),
+                        b_meta.get('note', '')
+                    ]
+                    vendor_data[manuf][board_dir.name] = b_entry
+    boards_rst = Path(TOP) / "docs/reference/boards.rst"
+    with boards_rst.open('w') as f:
+        title = f"""\
+****************
+Supported Boards
+****************
+
+The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project.
+It is responsible for getting the MCU started and the USB peripheral clocked with minimal of on-board devices
+
+-  One LED : for status
+-  One Button : to get input from user
+-  One UART : needed for logging with LOGGER=uart, maybe required for host/dual examples
+
+Following boards are supported"""
+        f.write(title)
+        for manuf, boards in sorted(vendor_data.items()):
+            f.write(f"\n\n{manuf}\n")
+            f.write(f"{'-' * len(manuf)}\n\n")
+            df = pd.DataFrame.from_dict(boards, orient='index', columns=['Name', 'Family', 'URL', 'Note'])
+            df = df.rename_axis("Board")
+            f.write(tabulate(df, headers="keys", tablefmt='rst'))
+
+
+# -----------------------------------------
+# Main
+# -----------------------------------------
+if __name__ == "__main__":
+    gen_deps_doc()
+    gen_boards_doc()
diff --git a/tools/get_dependencies.py b/tools/get_dependencies.py
deleted file mode 100644
index e7d3e0a76..000000000
--- a/tools/get_dependencies.py
+++ /dev/null
@@ -1,25 +0,0 @@
-import os
-import sys
-import subprocess
-
-
-# dependency lookup (ABC sorted)
-# deps = {
-#    'LPC11UXX' : [ [] ]
-# }
-
-
-def get_family_dep(family):
-    for entry in os.scandir("hw/bsp/{}/boards".format(family)):
-        if entry.is_dir():
-            result = subprocess.run("make -C examples/device/board_test BOARD={} get-deps".format(entry.name),
-                                    shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-            print(result.stdout.decode("utf-8"))
-            return result.returncode
-
-status = 0
-all_family = sys.argv[1:]
-for f in all_family:
-    status += get_family_dep(f)
-
-sys.exit(status)
\ No newline at end of file
diff --git a/tools/get_deps.py b/tools/get_deps.py
new file mode 100755
index 000000000..c8459c1f1
--- /dev/null
+++ b/tools/get_deps.py
@@ -0,0 +1,309 @@
+#!/usr/bin/env python3
+import argparse
+import sys
+import subprocess
+from pathlib import Path
+from multiprocessing import Pool
+
+# Mandatory Dependencies that is always fetched
+# path, url, commit, family (Alphabet sorted by path)
+deps_mandatory = {
+    'lib/FreeRTOS-Kernel': ['https://github.com/FreeRTOS/FreeRTOS-Kernel.git',
+                            'cc0e0707c0c748713485b870bb980852b210877f',
+                            'all'],
+    'lib/lwip': ['https://github.com/lwip-tcpip/lwip.git',
+                 '159e31b689577dbf69cf0683bbaffbd71fa5ee10',
+                 'all'],
+    'tools/uf2': ['https://github.com/microsoft/uf2.git',
+                  'c594542b2faa01cc33a2b97c9fbebc38549df80a',
+                  'all'],
+}
+
+# Optional Dependencies per MCU
+# path, url, commit, family (Alphabet sorted by path)
+deps_optional = {
+    'hw/mcu/allwinner': ['https://github.com/hathach/allwinner_driver.git',
+                         '8e5e89e8e132c0fd90e72d5422e5d3d68232b756',
+                         'fc100s'],
+    'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git',
+                             'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75',
+                             'max32650 max32666 max32690 max78002'],
+    'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git',
+                                         '91060164afe239fcb394122e8bf9eb24d3194eb1',
+                                         'brtmm90x'],
+    'hw/mcu/broadcom': ['https://github.com/adafruit/broadcom-peripherals.git',
+                        '08370086080759ed54ac1136d62d2ad24c6fa267',
+                        'broadcom_32bit broadcom_64bit'],
+    'hw/mcu/gd/nuclei-sdk': ['https://github.com/Nuclei-Software/nuclei-sdk.git',
+                             '7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7',
+                             'gd32vf103'],
+    'hw/mcu/infineon/mtb-xmclib-cat3': ['https://github.com/Infineon/mtb-xmclib-cat3.git',
+                                        'daf5500d03cba23e68c2f241c30af79cd9d63880',
+                                        'xmc4000'],
+    'hw/mcu/microchip': ['https://github.com/hathach/microchip_driver.git',
+                         '9e8b37e307d8404033bb881623a113931e1edf27',
+                         'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg'],
+    'hw/mcu/mindmotion/mm32sdk': ['https://github.com/hathach/mm32sdk.git',
+                                  'b93e856211060ae825216c6a1d6aa347ec758843',
+                                  'mm32'],
+    'hw/mcu/nordic/nrfx': ['https://github.com/NordicSemiconductor/nrfx.git',
+                           '7c47cc0a56ce44658e6da2458e86cd8783ccc4a2',
+                           'nrf'],
+    'hw/mcu/nuvoton': ['https://github.com/majbthrd/nuc_driver.git',
+                       '2204191ec76283371419fbcec207da02e1bc22fa',
+                       'nuc'],
+    'hw/mcu/nxp/lpcopen': ['https://github.com/hathach/nxp_lpcopen.git',
+                           'b41cf930e65c734d8ec6de04f1d57d46787c76ae',
+                           'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
+    'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
+                            '144f1eb7ea8c06512e12f12b27383601c0272410',
+                            'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
+    'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
+                                         'fe9133fc513b82cc3dc62c67cb51f2339cf29ef7',
+                                         'rp2040'],
+    'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git',
+                           'edcc97d684b6f716728a60d7a6fea049d9870bd6',
+                           'ra'],
+    'hw/mcu/renesas/rx': ['https://github.com/kkitayam/rx_device.git',
+                          '706b4e0cf485605c32351e2f90f5698267996023',
+                          'rx'],
+    'hw/mcu/silabs/cmsis-dfp-efm32gg12b': ['https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git',
+                                           'f1c31b7887669cb230b3ea63f9b56769078960bc',
+                                           'efm32'],
+    'hw/mcu/sony/cxd56/spresense-exported-sdk': ['https://github.com/sonydevworld/spresense-exported-sdk.git',
+                                                 '2ec2a1538362696118dc3fdf56f33dacaf8f4067',
+                                                 'spresense'],
+    'hw/mcu/st/cmsis_device_c0': ['https://github.com/STMicroelectronics/cmsis_device_c0.git',
+                                  'fb56b1b70c73b74eacda2a4bcc36886444364ab3',
+                                  'stm32c0'],
+    'hw/mcu/st/cmsis_device_f0': ['https://github.com/STMicroelectronics/cmsis_device_f0.git',
+                                  '2fc25ee22264bc27034358be0bd400b893ef837e',
+                                  'stm32f0'],
+    'hw/mcu/st/cmsis_device_f1': ['https://github.com/STMicroelectronics/cmsis_device_f1.git',
+                                  '6601104a6397299b7304fd5bcd9a491f56cb23a6',
+                                  'stm32f1'],
+    'hw/mcu/st/cmsis_device_f2': ['https://github.com/STMicroelectronics/cmsis_device_f2.git',
+                                  '182fcb3681ce116816feb41b7764f1b019ce796f',
+                                  'stm32f2'],
+    'hw/mcu/st/cmsis_device_f3': ['https://github.com/STMicroelectronics/cmsis_device_f3.git',
+                                  '5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b',
+                                  'stm32f3'],
+    'hw/mcu/st/cmsis_device_f4': ['https://github.com/STMicroelectronics/cmsis_device_f4.git',
+                                  '2615e866fa48fe1ff1af9e31c348813f2b19e7ec',
+                                  'stm32f4'],
+    'hw/mcu/st/cmsis_device_f7': ['https://github.com/STMicroelectronics/cmsis_device_f7.git',
+                                  '25b0463439303b7a38f0d27b161f7d2f3c096e79',
+                                  'stm32f7'],
+    'hw/mcu/st/cmsis_device_g0': ['https://github.com/STMicroelectronics/cmsis_device_g0.git',
+                                  '3a23e1224417f3f2d00300ecd620495e363f2094',
+                                  'stm32g0'],
+    'hw/mcu/st/cmsis_device_g4': ['https://github.com/STMicroelectronics/cmsis_device_g4.git',
+                                  'ce822adb1dc552b3aedd13621edbc7fdae124878',
+                                  'stm32g4'],
+    'hw/mcu/st/cmsis_device_h7': ['https://github.com/STMicroelectronics/cmsis_device_h7.git',
+                                  '60dc2c913203dc8629dc233d4384dcc41c91e77f',
+                                  'stm32h7'],
+    'hw/mcu/st/cmsis_device_h5': ['https://github.com/STMicroelectronics/cmsis_device_h5.git',
+                                  'cd2d1d579743de57b88ccaf61a968b9c05848ffc',
+                                  'stm32h5'],
+    'hw/mcu/st/cmsis_device_l0': ['https://github.com/STMicroelectronics/cmsis_device_l0.git',
+                                  '69cd5999fd40ae6e546d4905b21635c6ca1bcb92',
+                                  'stm32l0'],
+    'hw/mcu/st/cmsis_device_l1': ['https://github.com/STMicroelectronics/cmsis_device_l1.git',
+                                  '7f16ec0a1c4c063f84160b4cc6bf88ad554a823e',
+                                  'stm32l1'],
+    'hw/mcu/st/cmsis_device_l4': ['https://github.com/STMicroelectronics/cmsis_device_l4.git',
+                                  '6ca7312fa6a5a460b5a5a63d66da527fdd8359a6',
+                                  'stm32l4'],
+    'hw/mcu/st/cmsis_device_l5': ['https://github.com/STMicroelectronics/cmsis_device_l5.git',
+                                  'd922865fc0326a102c26211c44b8e42f52c1e53d',
+                                  'stm32l5'],
+    'hw/mcu/st/cmsis_device_u5': ['https://github.com/STMicroelectronics/cmsis_device_u5.git',
+                                  '5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309',
+                                  'stm32u5'],
+    'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git',
+                                  '9c5d1920dd9fabbe2548e10561d63db829bb744f',
+                                  'stm32wb'],
+    'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git',
+                                     '7f4389efee9c6a655b55e5df3fceef5586b35f9b',
+                                     'stm32h7'],
+    'hw/mcu/st/stm32c0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git',
+                                       '41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3',
+                                       'stm32c0'],
+    'hw/mcu/st/stm32f0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git',
+                                       '0e95cd88657030f640a11e690a8a5186c7712ea5',
+                                       'stm32f0'],
+    'hw/mcu/st/stm32f1xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git',
+                                       '1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29',
+                                       'stm32f1'],
+    'hw/mcu/st/stm32f2xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git',
+                                       'c75ace9b908a9aca631193ebf2466963b8ea33d0',
+                                       'stm32f2'],
+    'hw/mcu/st/stm32f3xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git',
+                                       '1761b6207318ede021706e75aae78f452d72b6fa',
+                                       'stm32f3'],
+    'hw/mcu/st/stm32f4xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git',
+                                       '04e99fbdabd00ab8f370f377c66b0a4570365b58',
+                                       'stm32f4'],
+    'hw/mcu/st/stm32f7xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git',
+                                       'f7ffdf6bf72110e58b42c632b0a051df5997e4ee',
+                                       'stm32f7'],
+    'hw/mcu/st/stm32g0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git',
+                                       'e911b12c7f67084d7f6b76157a4c0d4e2ec3779c',
+                                       'stm32g0'],
+    'hw/mcu/st/stm32g4xx_hal_driver': ['https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git',
+                                       '8b4518417706d42eef5c14e56a650005abf478a8',
+                                       'stm32g4'],
+    'hw/mcu/st/stm32h7xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git',
+                                       'd8461b980b59b1625207d8c4f2ce0a9c2a7a3b04',
+                                       'stm32h7'],
+    'hw/mcu/st/stm32h5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git',
+                                       '2cf77de584196d619cec1b4586c3b9e2820a254e',
+                                       'stm32h5'],
+    'hw/mcu/st/stm32l0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git',
+                                       'fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b',
+                                       'stm32l0'],
+    'hw/mcu/st/stm32l1xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git',
+                                       '44efc446fa69ed8344e7fd966e68ed11043b35d9',
+                                       'stm32l1'],
+    'hw/mcu/st/stm32l4xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git',
+                                       'aee3d5bf283ae5df87532b781bdd01b7caf256fc',
+                                       'stm32l4'],
+    'hw/mcu/st/stm32l5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git',
+                                       '675c32a75df37f39d50d61f51cb0dcf53f07e1cb',
+                                       'stm32l5'],
+    'hw/mcu/st/stm32u5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git',
+                                       '4d93097a67928e9377e655ddd14622adc31b9770',
+                                       'stm32u5'],
+    'hw/mcu/st/stm32wbxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git',
+                                       '2c5f06638be516c1b772f768456ba637f077bac8',
+                                       'stm32wb'],
+    'hw/mcu/ti': ['https://github.com/hathach/ti_driver.git',
+                  '143ed6cc20a7615d042b03b21e070197d473e6e5',
+                  'msp430 msp432e4 tm4c'],
+    'hw/mcu/wch/ch32v103': ['https://github.com/openwch/ch32v103.git',
+                            '7578cae0b21f86dd053a1f781b2fc6ab99d0ec17',
+                            'ch32v10x'],
+    'hw/mcu/wch/ch32v20x': ['https://github.com/openwch/ch32v20x.git',
+                            'c4c38f507e258a4e69b059ccc2dc27dde33cea1b',
+                            'ch32v20x'],
+    'hw/mcu/wch/ch32v307': ['https://github.com/openwch/ch32v307.git',
+                            '184f21b852cb95eed58e86e901837bc9fff68775',
+                            'ch32v307'],
+    'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git',
+                            '77c4095087e5ed2c548ec9058e655d0b8757663b',
+                            'ch32f20x'],
+    'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
+                    '2b7495b8535bdcb306dac29b9ded4cfb679d7e5c',
+                    'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x '
+                    'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 '
+                    'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 '
+                    'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb '
+                    'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg '
+                    'tm4c '],
+    'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git',
+                    'b0bbb0423b278ca632cfe1474eb227961d835fd2',
+                    'ra'],
+    'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
+                         'e73e04ca63495672d955f9268e003cffe168fcd8',
+                         'lpc55'],
+}
+
+# combined 2 deps
+deps_all = {**deps_mandatory, **deps_optional}
+
+# TOP is tinyusb root dir
+TOP = Path(__file__).parent.parent.resolve()
+
+
+def run_cmd(cmd):
+    return subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+
+
+def get_a_dep(d):
+    if d not in deps_all.keys():
+        print('{} is not found in dependency list')
+        return 1
+    url = deps_all[d][0]
+    commit = deps_all[d][1]
+    families = deps_all[d][2]
+
+    print(f'cloning {d} with {url}')
+
+    p = Path(TOP / d)
+    git_cmd = f"git -C {p}"
+
+    # Init git deps if not existed
+    if not p.exists():
+        p.mkdir(parents=True)
+        run_cmd(f"{git_cmd} init")
+        run_cmd(f"{git_cmd} remote add origin {url}")
+
+    # Check if commit is already fetched
+    result = run_cmd(f"{git_cmd} rev-parse HEAD")
+    head = result.stdout.decode("utf-8").splitlines()[0]
+    run_cmd(f"{git_cmd} reset --hard")
+    if commit != head:
+        run_cmd(f"{git_cmd} fetch --depth 1 origin {commit}")
+        run_cmd(f"{git_cmd} checkout FETCH_HEAD")
+
+    return 0
+
+
+def find_family(board):
+    bsp_dir = Path(TOP / "hw/bsp")
+    for family_dir in bsp_dir.iterdir():
+        if family_dir.is_dir():
+            board_dir = family_dir / 'boards' / board
+            if board_dir.exists():
+                return family_dir.name
+    return None
+
+
+def main():
+    parser = argparse.ArgumentParser()
+    parser.add_argument('families', nargs='*', default=[], help='Families to fetch')
+    parser.add_argument('-b', '--board', action='append', default=[], help='Boards to fetch')
+    parser.add_argument('-f1', '--build-flags-on', action='append', default=[], help='Have no effect')
+    parser.add_argument('--print', action='store_true', help='Print commit hash only')
+    args = parser.parse_args()
+
+    families = args.families
+    boards = args.board
+    print_only = args.print
+
+    status = 0
+    deps = list(deps_mandatory.keys())
+
+    if 'all' in families:
+        deps += deps_optional.keys()
+    else:
+        families = list(families)
+        if boards is not None:
+            for b in boards:
+                f = find_family(b)
+                if f is not None:
+                    families.append(f)
+
+        for f in families:
+            for d in deps_optional:
+                if d not in deps and f in deps_optional[d][2]:
+                    deps.append(d)
+
+    if print_only:
+        pvalue = {}
+        # print only without arguments, always add CMSIS_5
+        if len(families) == 0 and len(boards) == 0:
+            deps.append('lib/CMSIS_5')
+        for d in deps:
+            commit = deps_all[d][1]
+            pvalue[d] = commit
+        print(pvalue)
+    else:
+        with Pool() as pool:
+            status = sum(pool.map(get_a_dep, deps))
+    return status
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/tools/iar_gen.py b/tools/iar_gen.py
old mode 100644
new mode 100755
index 73c8b29fc..8d45659db
--- a/tools/iar_gen.py
+++ b/tools/iar_gen.py
@@ -1,51 +1,87 @@
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 import os
+import sys
 import xml.dom.minidom as XML
+import glob
 
-# Read base configuration
-base = ""
-with open("iar_template.ipcf") as f:
-    base = f.read()
+def Main():
+    # Read base configuration
+    base = ""
+    with open("iar_template.ipcf") as f:
+        base = f.read()
 
-# Enumerate all device/host examples
-dir_1 = os.listdir("../examples")
-for dir_2 in dir_1:
-    if os.path.isdir("../examples/{}".format(dir_2)):
-        print(dir_2)
-        examples = os.listdir("../examples/{}".format(dir_2))
-        for example in examples:
-            if os.path.isdir("../examples/{}/{}".format(dir_2, example)):
-                print("../examples/{}/{}".format(dir_2, example))
-                conf = XML.parseString(base)
-                files = conf.getElementsByTagName("files")[0]
-                inc   = conf.getElementsByTagName("includePath")[0]
-                # Add bsp inc
-                path = conf.createElement('path')
-                path_txt = conf.createTextNode("$TUSB_DIR$/hw")
-                path.appendChild(path_txt)
-                inc.appendChild(path)
-                # Add board.c/.h
-                grp = conf.createElement('group')
-                grp.setAttribute("name", "bsp")
-                path = conf.createElement('path')
-                path_txt = conf.createTextNode("$TUSB_DIR$/hw/bsp/board.c")
-                path.appendChild(path_txt)
-                grp.appendChild(path)
-                files.appendChild(grp)
-                # Add example's .c/.h
-                grp = conf.createElement('group')
-                grp.setAttribute("name", "example")
-                for file in os.listdir("../examples/{}/{}/src".format(dir_2, example)):
-                    if file.endswith(".c") or file.endswith(".h"):
-                        path = conf.createElement('path')
-                        path.setAttribute("copyTo", "$PROJ_DIR$/{}".format(file))
-                        path_txt = conf.createTextNode("$TUSB_DIR$/examples/{0}/{1}/src/{2}".format(dir_2, example, file))
-                        path.appendChild(path_txt)
-                        grp.appendChild(path)
-                files.appendChild(grp)
-                cfg_str = conf.toprettyxml()
-                cfg_str = '\n'.join([s for s in cfg_str.splitlines() if s.strip()])
-                #print(cfg_str)
-                with open("../examples/{0}/{1}/iar_{1}.ipcf".format(dir_2, example), 'w') as f:
-                    f.write(cfg_str)
+    # Enumerate all device/host examples
+    dir_1 = os.listdir("../examples")
+    for dir_2 in dir_1:
+        if os.path.isdir("../examples/{}".format(dir_2)):
+            print(dir_2)
+            examples = os.listdir("../examples/{}".format(dir_2))
+            for example in examples:
+                if os.path.isdir("../examples/{}/{}".format(dir_2, example)):
+                    print("../examples/{}/{}".format(dir_2, example))
+                    conf = XML.parseString(base)
+                    files = conf.getElementsByTagName("files")[0]
+                    inc   = conf.getElementsByTagName("includePath")[0]
+                    # Add bsp inc
+                    path = conf.createElement('path')
+                    path_txt = conf.createTextNode("$TUSB_DIR$/hw")
+                    path.appendChild(path_txt)
+                    inc.appendChild(path)
+                    # Add board.c/.h
+                    grp = conf.createElement('group')
+                    grp.setAttribute("name", "bsp")
+                    path = conf.createElement('path')
+                    path_txt = conf.createTextNode("$TUSB_DIR$/hw/bsp/board.c")
+                    path.appendChild(path_txt)
+                    grp.appendChild(path)
+                    files.appendChild(grp)
+                    # Add example's .c/.h
+                    grp = conf.createElement('group')
+                    grp.setAttribute("name", "example")
+                    for file in os.listdir("../examples/{}/{}/src".format(dir_2, example)):
+                        if file.endswith(".c") or file.endswith(".h"):
+                            path = conf.createElement('path')
+                            path.setAttribute("copyTo", "$PROJ_DIR$/{}".format(file))
+                            path_txt = conf.createTextNode("$TUSB_DIR$/examples/{0}/{1}/src/{2}".format(dir_2, example, file))
+                            path.appendChild(path_txt)
+                            grp.appendChild(path)
+                    files.appendChild(grp)
+                    cfg_str = conf.toprettyxml()
+                    cfg_str = '\n'.join([s for s in cfg_str.splitlines() if s.strip()])
+                    #print(cfg_str)
+                    with open("../examples/{0}/{1}/iar_{1}.ipcf".format(dir_2, example), 'w') as f:
+                        f.write(cfg_str)
+
+def ListPath(path, blacklist=[]):
+    # Get all .c files
+    files = glob.glob(f'../{path}/**/*.c', recursive=True)
+    files.extend(glob.glob(f'../{path}/**/*.h', recursive=True))
+    # Filter
+    files = [x for x in files if all(y not in x for y in blacklist)]
+    # Get common dir list
+    dirs = []
+    for file in files:
+        dir = os.path.dirname(file)
+        if dir not in dirs:
+            dirs.append(dir)
+    # Print .c grouped by dir
+    for dir in dirs:
+        print('<group name="' + dir.replace('../', '').replace('\\','/') + '">')
+        for file in files:
+            if os.path.dirname(file) == dir:
+                print('    <path>$TUSB_DIR$/' + file.replace('../','').replace('\\','/')+'</path>')
+        print('</group>')
+
+def List():
+    ListPath('src', [ 'template.c', 'dcd_synopsys.c', 'dcd_esp32sx.c' ])
+    ListPath('lib/SEGGER_RTT')
+
+if __name__ == "__main__":
+    if os.path.dirname(os.getcwd()) != 'tools':
+        os.chdir('tools')
+    if (len(sys.argv) > 1):
+        if (sys.argv[1] == 'l'):
+            List()
+    else:
+        Main()
diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index ba54fe057..33a6ef045 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -4,142 +4,273 @@
 	<includePath>
 		<path>$TUSB_DIR$/src</path>
         <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+        <path>$TUSB_DIR$/lib/SEGGER_RTT/Config</path>
         <path>$PROJ_DIR$</path>
 	</includePath>
 	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/ecm_rndis_device.c</path>
-			<path>$TUSB_DIR$/src/class/net/ncm_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
         <group name="src">
             <path>$TUSB_DIR$/src/tusb.c</path>
+            <path>$TUSB_DIR$/src/tusb.h</path>
+            <path>$TUSB_DIR$/src/tusb_option.h</path>
         </group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/synopsys/dwc2">
-			<path>$TUSB_DIR$/src/portable/synopsys/dwc2/dcd_dwc2.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/mentor/musb">
-			<path>$TUSB_DIR$/src/portable/mentor/musb/dcd_musb.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-        <group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+        <group name="src/class/audio">
+            <path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+            <path>$TUSB_DIR$/src/class/audio/audio.h</path>
+            <path>$TUSB_DIR$/src/class/audio/audio_device.h</path>
+        </group>
+        <group name="src/class/bth">
+            <path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+            <path>$TUSB_DIR$/src/class/bth/bth_device.h</path>
+        </group>
+        <group name="src/class/cdc">
+            <path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+            <path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+            <path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+            <path>$TUSB_DIR$/src/class/cdc/cdc.h</path>
+            <path>$TUSB_DIR$/src/class/cdc/cdc_device.h</path>
+            <path>$TUSB_DIR$/src/class/cdc/cdc_host.h</path>
+            <path>$TUSB_DIR$/src/class/cdc/cdc_rndis.h</path>
+            <path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.h</path>
+        </group>
+        <group name="src/class/dfu">
+            <path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+            <path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+            <path>$TUSB_DIR$/src/class/dfu/dfu.h</path>
+            <path>$TUSB_DIR$/src/class/dfu/dfu_device.h</path>
+            <path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.h</path>
+        </group>
+        <group name="src/class/hid">
+            <path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+            <path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+            <path>$TUSB_DIR$/src/class/hid/hid.h</path>
+            <path>$TUSB_DIR$/src/class/hid/hid_device.h</path>
+            <path>$TUSB_DIR$/src/class/hid/hid_host.h</path>
+        </group>
+        <group name="src/class/midi">
+            <path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+            <path>$TUSB_DIR$/src/class/midi/midi.h</path>
+            <path>$TUSB_DIR$/src/class/midi/midi_device.h</path>
+        </group>
+        <group name="src/class/msc">
+            <path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+            <path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+            <path>$TUSB_DIR$/src/class/msc/msc.h</path>
+            <path>$TUSB_DIR$/src/class/msc/msc_device.h</path>
+            <path>$TUSB_DIR$/src/class/msc/msc_host.h</path>
+        </group>
+        <group name="src/class/net">
+            <path>$TUSB_DIR$/src/class/net/ecm_rndis_device.c</path>
+            <path>$TUSB_DIR$/src/class/net/ncm_device.c</path>
+            <path>$TUSB_DIR$/src/class/net/ncm.h</path>
+            <path>$TUSB_DIR$/src/class/net/net_device.h</path>
+        </group>
+        <group name="src/class/usbtmc">
+            <path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+            <path>$TUSB_DIR$/src/class/usbtmc/usbtmc.h</path>
+            <path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.h</path>
+        </group>
+        <group name="src/class/vendor">
+            <path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+            <path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+            <path>$TUSB_DIR$/src/class/vendor/vendor_device.h</path>
+            <path>$TUSB_DIR$/src/class/vendor/vendor_host.h</path>
+        </group>
+        <group name="src/class/video">
+            <path>$TUSB_DIR$/src/class/video/video_device.c</path>
+            <path>$TUSB_DIR$/src/class/video/video.h</path>
+            <path>$TUSB_DIR$/src/class/video/video_device.h</path>
+        </group>
+        <group name="src/common">
+            <path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+            <path>$TUSB_DIR$/src/common/tusb_common.h</path>
+            <path>$TUSB_DIR$/src/common/tusb_compiler.h</path>
+            <path>$TUSB_DIR$/src/common/tusb_debug.h</path>
+            <path>$TUSB_DIR$/src/common/tusb_fifo.h</path>
+            <path>$TUSB_DIR$/src/common/tusb_mcu.h</path>
+            <path>$TUSB_DIR$/src/common/tusb_private.h</path>
+            <path>$TUSB_DIR$/src/common/tusb_types.h</path>
+            <path>$TUSB_DIR$/src/common/tusb_verify.h</path>
+        </group>
+        <group name="src/device">
+            <path>$TUSB_DIR$/src/device/usbd.c</path>
+            <path>$TUSB_DIR$/src/device/usbd_control.c</path>
+            <path>$TUSB_DIR$/src/device/dcd.h</path>
+            <path>$TUSB_DIR$/src/device/usbd.h</path>
+            <path>$TUSB_DIR$/src/device/usbd_pvt.h</path>
+        </group>
+        <group name="src/host">
+            <path>$TUSB_DIR$/src/host/hub.c</path>
+            <path>$TUSB_DIR$/src/host/usbh.c</path>
+            <path>$TUSB_DIR$/src/host/hcd.h</path>
+            <path>$TUSB_DIR$/src/host/hub.h</path>
+            <path>$TUSB_DIR$/src/host/usbh.h</path>
+            <path>$TUSB_DIR$/src/host/usbh_pvt.h</path>
+        </group>
+        <group name="src/portable/analog/max3421">
+            <path>$TUSB_DIR$/src/portable/analog/max3421/hcd_max3421.c</path>
+        </group>
+        <group name="src/portable/bridgetek/ft9xx">
+            <path>$TUSB_DIR$/src/portable/bridgetek/ft9xx/dcd_ft9xx.c</path>
+        </group>
+        <group name="src/portable/chipidea/ci_fs">
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_fs/dcd_ci_fs.c</path>
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_fs/ci_fs_kinetis.h</path>
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_fs/ci_fs_mcx.h</path>
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_fs/ci_fs_type.h</path>
+        </group>
+        <group name="src/portable/chipidea/ci_hs">
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_hs/dcd_ci_hs.c</path>
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_hs/hcd_ci_hs.c</path>
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_hs/ci_hs_imxrt.h</path>
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h</path>
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_hs/ci_hs_mcx.h</path>
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_hs/ci_hs_type.h</path>
+        </group>
+        <group name="src/portable/dialog/da146xx">
+            <path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+        </group>
+        <group name="src/portable/ehci">
+            <path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+            <path>$TUSB_DIR$/src/portable/ehci/ehci.h</path>
+            <path>$TUSB_DIR$/src/portable/ehci/ehci_api.h</path>
+        </group>
+        <group name="src/portable/mentor/musb">
+            <path>$TUSB_DIR$/src/portable/mentor/musb/dcd_musb.c</path>
+            <path>$TUSB_DIR$/src/portable/mentor/musb/hcd_musb.c</path>
+            <path>$TUSB_DIR$/src/portable/mentor/musb/musb_msp432e.h</path>
+            <path>$TUSB_DIR$/src/portable/mentor/musb/musb_tm4c.h</path>
+            <path>$TUSB_DIR$/src/portable/mentor/musb/musb_type.h</path>
+        </group>
+        <group name="src/portable/microchip/pic">
+            <path>$TUSB_DIR$/src/portable/microchip/pic/dcd_pic.c</path>
+        </group>
+        <group name="src/portable/microchip/pic32mz">
+            <path>$TUSB_DIR$/src/portable/microchip/pic32mz/dcd_pic32mz.c</path>
+            <path>$TUSB_DIR$/src/portable/microchip/pic32mz/usbhs_registers.h</path>
+        </group>
+        <group name="src/portable/microchip/samd">
+            <path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+        </group>
+        <group name="src/portable/microchip/samg">
+            <path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+        </group>
+        <group name="src/portable/microchip/samx7x">
+            <path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+            <path>$TUSB_DIR$/src/portable/microchip/samx7x/common_usb_regs.h</path>
+        </group>
+        <group name="src/portable/mindmotion/mm32">
+            <path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+        </group>
+        <group name="src/portable/nordic/nrf5x">
+            <path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+        </group>
+        <group name="src/portable/nuvoton/nuc120">
+            <path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+        </group>
+        <group name="src/portable/nuvoton/nuc121">
+            <path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+        </group>
+        <group name="src/portable/nuvoton/nuc505">
+            <path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+        </group>
+        <group name="src/portable/nxp/khci">
+            <path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+            <path>$TUSB_DIR$/src/portable/nxp/khci/hcd_khci.c</path>
+        </group>
+        <group name="src/portable/nxp/lpc17_40">
+            <path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+            <path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+            <path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.h</path>
+        </group>
+        <group name="src/portable/nxp/lpc_ip3511">
+            <path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+        </group>
+        <group name="src/portable/ohci">
+            <path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+            <path>$TUSB_DIR$/src/portable/ohci/ohci.h</path>
+        </group>
+        <group name="src/portable/raspberrypi/pio_usb">
+            <path>$TUSB_DIR$/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c</path>
+            <path>$TUSB_DIR$/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c</path>
+        </group>
+        <group name="src/portable/raspberrypi/rp2040">
+            <path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+            <path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+            <path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+            <path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.h</path>
+        </group>
+        <group name="src/portable/renesas/rusb2">
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/dcd_rusb2.c</path>
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/hcd_rusb2.c</path>
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/rusb2_common.c</path>
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/rusb2_ra.h</path>
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/rusb2_rx.h</path>
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/rusb2_type.h</path>
+        </group>
+        <group name="src/portable/sony/cxd56">
+            <path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+        </group>
+        <group name="src/portable/st/stm32_fsdev">
+            <path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+            <path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h</path>
+        </group>
+        <group name="src/portable/st/typec">
+            <path>$TUSB_DIR$/src/portable/st/typec/typec_stm32.c</path>
+        </group>
+        <group name="src/portable/sunxi">
+            <path>$TUSB_DIR$/src/portable/sunxi/dcd_sunxi_musb.c</path>
+            <path>$TUSB_DIR$/src/portable/sunxi/musb_def.h</path>
+        </group>
+        <group name="src/portable/synopsys/dwc2">
+            <path>$TUSB_DIR$/src/portable/synopsys/dwc2/dcd_dwc2.c</path>
+            <path>$TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_bcm.h</path>
+            <path>$TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_efm32.h</path>
+            <path>$TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_esp32.h</path>
+            <path>$TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_gd32.h</path>
+            <path>$TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_stm32.h</path>
+            <path>$TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_type.h</path>
+            <path>$TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_xmc.h</path>
+        </group>
+        <group name="src/portable/ti/msp430x5xx">
+            <path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+        </group>
+        <group name="src/portable/valentyusb/eptri">
+            <path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+            <path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.h</path>
+        </group>
+        <group name="src/portable/wch">
+            <path>$TUSB_DIR$/src/portable/wch/dcd_ch32_usbfs.c</path>
+            <path>$TUSB_DIR$/src/portable/wch/dcd_ch32_usbhs.c</path>
+            <path>$TUSB_DIR$/src/portable/wch/ch32_usbhs_reg.h</path>
+        </group>
+        <group name="src/typec">
+            <path>$TUSB_DIR$/src/typec/usbc.c</path>
+            <path>$TUSB_DIR$/src/typec/pd_types.h</path>
+            <path>$TUSB_DIR$/src/typec/tcd.h</path>
+            <path>$TUSB_DIR$/src/typec/usbc.h</path>
+        </group>
+        <group name="src/class/cdc/serial">
+            <path>$TUSB_DIR$/src/class/cdc/serial/ch34x.h</path>
+            <path>$TUSB_DIR$/src/class/cdc/serial/cp210x.h</path>
+            <path>$TUSB_DIR$/src/class/cdc/serial/ftdi_sio.h</path>
+        </group>
+        <group name="src/osal">
+            <path>$TUSB_DIR$/src/osal/osal.h</path>
+            <path>$TUSB_DIR$/src/osal/osal_freertos.h</path>
+            <path>$TUSB_DIR$/src/osal/osal_mynewt.h</path>
+            <path>$TUSB_DIR$/src/osal/osal_none.h</path>
+            <path>$TUSB_DIR$/src/osal/osal_pico.h</path>
+            <path>$TUSB_DIR$/src/osal/osal_rtthread.h</path>
+            <path>$TUSB_DIR$/src/osal/osal_rtx4.h</path>
+        </group>
+        <group name="lib/SEGGER_RTT/RTT">
+            <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
             <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-            <path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
+            <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.h</path>
+        </group>
+        <group name="lib/SEGGER_RTT/Config">
+            <path>$TUSB_DIR$/lib/SEGGER_RTT/Config/SEGGER_RTT_Conf.h</path>
+        </group>
     </files>
-    
+
 </iarProjectConnection>
diff --git a/tools/make_release.py b/tools/make_release.py
new file mode 100755
index 000000000..c1caf3300
--- /dev/null
+++ b/tools/make_release.py
@@ -0,0 +1,53 @@
+#!/usr/bin/env python3
+import re
+import gen_doc
+
+version = '0.18.0'
+
+print('version {}'.format(version))
+ver_id = version.split('.')
+
+###################
+# src/tusb_option.h
+###################
+f_option_h = 'src/tusb_option.h'
+with open(f_option_h) as f:
+    fdata = f.read()
+    fdata = re.sub(r'(#define TUSB_VERSION_MAJOR *) \d+', r"\1 {}".format(ver_id[0]), fdata)
+    fdata = re.sub(r'(#define TUSB_VERSION_MINOR *) \d+', r"\1 {}".format(ver_id[1]), fdata)
+    fdata = re.sub(r'(#define TUSB_VERSION_REVISION *) \d+', r"\1 {}".format(ver_id[2]), fdata)
+
+# Write the file out again
+with open(f_option_h, 'w') as f:
+    f.write(fdata)
+
+###################
+# repository.yml
+###################
+f_repository_yml = 'repository.yml'
+with open(f_repository_yml) as f:
+    fdata = f.read()
+
+if fdata.find(version) < 0:
+    fdata = re.sub(r'("0-latest"): "\d+\.\d+\.\d+"', r'"{}": "{}"\r\n    \1: "{}"'.format(version, version, version), fdata)
+    with open(f_repository_yml, 'w') as f:
+        f.write(fdata)
+
+###################
+# library.json
+###################
+f_library_json = 'library.json'
+with open(f_library_json) as f:
+    fdata = f.read()
+    fdata = re.sub(r'( {4}"version":) "\d+\.\d+\.\d+"', rf'\1 "{version}"', fdata)
+
+with open(f_library_json, 'w') as f:
+    f.write(fdata)
+
+###################
+# docs/info/changelog.rst
+###################
+
+gen_doc.gen_deps_doc()
+
+print("Update docs/info/changelog.rst")
diff --git a/tools/mksunxi.py b/tools/mksunxi.py
old mode 100644
new mode 100755
index 04786f429..fd8557cfc
--- a/tools/mksunxi.py
+++ b/tools/mksunxi.py
@@ -45,4 +45,4 @@ if __name__ == "__main__":
     if len(sys.argv) != 3:
         print("Usage: mksunxi.py input.bin output.bin")
         exit(1)
-    exit(process_file(sys.argv[1], sys.argv[2]))
\ No newline at end of file
+    exit(process_file(sys.argv[1], sys.argv[2]))
diff --git a/tools/pcapng_to_corpus.py b/tools/pcapng_to_corpus.py
new file mode 100755
index 000000000..3089f0bb6
--- /dev/null
+++ b/tools/pcapng_to_corpus.py
@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+import argparse
+import pcapng
+import zipfile
+import hashlib
+
+def extract_packets(pcap_file):
+    """Reads a wireshark packet capture and extracts the binary packets"""
+    packets = []
+    with open(pcap_file, 'rb') as fp:
+        scanner = pcapng.FileScanner(fp)
+        for block in scanner:
+            if isinstance(block, pcapng.blocks.EnhancedPacket):
+                packets.append(block.packet_data)
+    return packets
+
+def build_corpus_zip(zip_file_output, packets):
+    """Builds a zip file with a file per packet
+
+    The structure of this zip corpus is a simple content addressable storage
+    i.e. seed_file_name == sha256_digest(packet).
+    """
+    with zipfile.ZipFile(zip_file_output, 'a') as out:
+        for packet in packets:
+            hash = hashlib.sha256(packet).hexdigest()
+            if hash not in out.namelist():
+                out.writestr(hash, packet)
+
+
+def main(pcap_file, output_zip_file):
+    packets = extract_packets(pcap_file)
+    build_corpus_zip(output_zip_file, packets)
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(
+        prog = "pcapng_to_corpus.py",
+        description="""Converts a wireshark capture to a zip of binary packet
+                    files suitable for an oss-fuzz corpus. In the case the
+                    zip corpus already exists, this script will modify
+                    the zip file in place adding seed entries.""")
+    parser.add_argument('pcapng_capture_file')
+    parser.add_argument('oss_fuzz_corpus_zip')
+    args = parser.parse_args()
+    main(args.pcapng_capture_file, args.oss_fuzz_corpus_zip)
diff --git a/tools/top.mk b/tools/top.mk
deleted file mode 100644
index 84523a557..000000000
--- a/tools/top.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-ifneq ($(lastword a b),b)
-$(error This Makefile require make 3.81 or newer)
-endif
-
-# Detect whether shell style is windows or not
-# https://stackoverflow.com/questions/714100/os-detecting-makefile/52062069#52062069
-ifeq '$(findstring ;,$(PATH))' ';'
-CMDEXE := 1
-endif
-
-# Set TOP to be the path to get from the current directory (where make was
-# invoked) to the top of the tree. $(lastword $(MAKEFILE_LIST)) returns
-# the name of this makefile relative to where make was invoked.
-
-THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
-TOP := $(patsubst %/tools/top.mk,%,$(THIS_MAKEFILE))
-
-ifeq ($(CMDEXE),1)
-TOP := $(subst \,/,$(shell for %%i in ( $(TOP) ) do echo %%~fi))
-else
-TOP := $(shell realpath $(TOP))
-endif
-#$(info Top directory is $(TOP))
-
-ifeq ($(CMDEXE),1)
-CURRENT_PATH := $(subst $(TOP)/,,$(subst \,/,$(shell echo %CD%)))
-else
-CURRENT_PATH := $(shell realpath --relative-to=$(TOP) `pwd`)
-endif
-#$(info Path from top is $(CURRENT_PATH))
diff --git a/tools/uf2 b/tools/uf2
deleted file mode 160000
index 196154077..000000000
--- a/tools/uf2
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 19615407727073e36d81bf239c52108ba92e7660
diff --git a/tools/usb_drivers/tinyusb_win_usbser.inf b/tools/usb_drivers/tinyusb_win_usbser.inf
index e7f7a9b22..659f048ae 100644
--- a/tools/usb_drivers/tinyusb_win_usbser.inf
+++ b/tools/usb_drivers/tinyusb_win_usbser.inf
@@ -105,4 +105,4 @@ DRIVERFILENAME ="usbser"
 MFGNAME="tinyusb.org"
 INSTDISK="tinyusb CDC Driver"
 DESCRIPTION="tinyusb Serial"
-SERVICE="USB RS-232 Emulation Driver"
\ No newline at end of file
+SERVICE="USB RS-232 Emulation Driver"